Update docs, fix multiple initial block case

Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>

docs/guide/languages.rst

@@ -451,17 +451,14 @@ disable
 force, release
   Verilator supports the procedural `force` (and corresponding `release`)
   statement. However, the behavior of the `force` statement does not
-  entirely comply with IEEE 1800:
+  entirely comply with IEEE 1800-2023:
   1. Using forced variable as a value to another force statement is currently
-     not supported. Force statement that depends on the other one is ignored.
-  2. Function calls on the RHS of force statements are not reevaluated when
-     their dependencies change. Value from first call is forced.
-  3. Forcing at time 0 from different active block immediately updates
-     forced variable.
-  4. Force/release with procedural continuous assignment is not supported.
-     Assignment is treated as procedural one.
-  5. Expressions using multiple VarRefs on forced RHS are not sensitive to
-     dependency changes.
+     not supported. The dependant force statement is forced by an initial
+     constant value.
+  2. Force/release with procedural continuous assignment is not supported.
+     Assignment is treated as a procedural one.
+  3. Expressions using multiple variable references or function calls on
+     forced right-hand side are not sensitive to dependency changes.
 
 inside
   Inside expressions may not include unpacked array traversal or $ as an

src/V3Force.cpp

@@ -96,7 +96,7 @@ class ForceState final {
                 AstAssign* const assignp = new AstAssign{flp, lhsp, rhsp};
                 AstActive* const activep = new AstActive{
                     flp, "force-init",
-                    new AstSenTree{flp, new AstSenItem{flp, AstSenItem::Initial{}}}};
+                    new AstSenTree{flp, new AstSenItem{flp, AstSenItem::Static{}}}};
                 activep->sensesStorep(activep->sensesp());
 
                 activep->addStmtsp(new AstInitial{flp, assignp});

test_regress/t/t_force_initial.py

@@ -13,6 +13,6 @@
 
 test.compile(verilator_flags2=["--exe", "--main", "--timing"])
 
-test.execute(expect_filename=test.golden_filename)
+test.execute()
 
 test.passes()

test_regress/t/t_force_initial.v

@@ -23,17 +23,16 @@ module t;
     a = 1;
     #1;
     `checkh(a, 1);
-    // TODO trigger forced variable update from different initial block.
     `checkh(b, 1);
 
-    a = 2;
+    a = 3;
     #1;
-    `checkh(a, 2);
-    `checkh(b, 2);
+    `checkh(a, 3);
+    `checkh(b, 3);
 
     release b;
-    `checkh(a, 2);
-    `checkh(b, 2);
+    `checkh(a, 3);
+    `checkh(b, 3);
 
     b = 0;
     #1;