From a379382d32b1b52f8490c4d0ddf0d186f8c4d1e8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bart=C5=82omiej=20Chmiel?= <bchmiel@antmicro.com>
Date: Tue, 28 Jan 2025 13:30:40 +0100
Subject: [PATCH] Fix handling forced assigns in V3Life (#5757)

---
 src/V3Life.cpp                   |  4 ++--
 test_regress/t/t_force_assign.py | 18 ++++++++++++++++++
 test_regress/t/t_force_assign.v  | 24 ++++++++++++++++++++++++
 3 files changed, 44 insertions(+), 2 deletions(-)
 create mode 100755 test_regress/t/t_force_assign.py
 create mode 100644 test_regress/t/t_force_assign.v

diff --git a/src/V3Life.cpp b/src/V3Life.cpp
index 47a7468b86..556fc23c03 100644
--- a/src/V3Life.cpp
+++ b/src/V3Life.cpp
@@ -287,8 +287,8 @@ class LifeVisitor final : public VNVisitor {
         }
     }
     void visit(AstNodeAssign* nodep) override {
-        if (nodep->isTimingControl()) {
-            // V3Life doesn't understand time sense - don't optimize
+        if (nodep->isTimingControl() || VN_IS(nodep, AssignForce)) {
+            // V3Life doesn't understand time sense nor force assigns - don't optimize
             setNoopt();
             iterateChildren(nodep);
             return;
diff --git a/test_regress/t/t_force_assign.py b/test_regress/t/t_force_assign.py
new file mode 100755
index 0000000000..f989a35fba
--- /dev/null
+++ b/test_regress/t/t_force_assign.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_force_assign.v b/test_regress/t/t_force_assign.v
new file mode 100644
index 0000000000..7b3724dd53
--- /dev/null
+++ b/test_regress/t/t_force_assign.v
@@ -0,0 +1,24 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+  reg [2:0] a = 0;
+
+  initial begin
+    a = 1;
+    if (a != 1) $stop;
+
+    force a = 2;
+    if (a != 2) $stop;
+
+    a = 3;
+    if (a != 2) $stop;
+
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+
+endmodule