Fix resolution of function args after package scope

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
antmicro · Mar 3, 2025 · 600cb42 · 600cb42
1 parent faa1865
commit 600cb42
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diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
@@ -2762,6 +2762,9 @@ class LinkDotResolveVisitor final : public VNVisitor {
                 if (!lhsp->classOrPackageSkipp() && lhsp->name() != "local::") {
                     revisitLater(nodep);
                     m_ds = lastStates;
+                    if (auto* ftaskrefp = VN_CAST(nodep->rhsp(), NodeFTaskRef)) {
+                        iterateAndNextNull(ftaskrefp->pinsp());
+                    }
                     return;
                 }
                 m_ds.m_dotPos = DP_PACKAGE;
@@ -2784,11 +2787,17 @@ class LinkDotResolveVisitor final : public VNVisitor {
                     if (!crefp->classOrPackageSkipp()) {
                         revisitLater(nodep);
                         m_ds = lastStates;
+                        if (auto* ftaskrefp = VN_CAST(nodep->rhsp(), NodeFTaskRef)) {
+                            iterateAndNextNull(ftaskrefp->pinsp());
+                        }
                         return;
                     }
                 }
                 if (m_lastDeferredp == nodep->lhsp()) {
                     m_ds = lastStates;
+                    if (auto* ftaskrefp = VN_CAST(nodep->rhsp(), NodeFTaskRef)) {
+                        iterateAndNextNull(ftaskrefp->pinsp());
+                    }
                     return;
                 }
                 UINFO(8, indent() << "iter.ldone " << m_ds.ascii() << " " << nodep << endl);

diff --git a/test_regress/t/t_param_resolve_args.py b/test_regress/t/t_param_resolve_args.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_param_resolve_args.v b/test_regress/t/t_param_resolve_args.v
@@ -0,0 +1,31 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+class Foo;
+  static function int get(int x);
+    return x;
+  endfunction
+endclass
+
+class Bar;
+  static function int get;
+    return 42;
+  endfunction
+endclass
+
+class Qux #(type Tfoo, type Tbar);
+  static function int get();
+    return Tfoo::get(Tbar::get());
+  endfunction
+endclass
+
+module t;
+  initial begin
+    if (Qux#(Foo, Bar)::get() != 42) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule