Add clk port to random variables tests (#439)

antmicro · Nov 20, 2023 · c94a527 · c94a527
1 parent 9dce10c
commit c94a527
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Showing 5 changed files with 9 additions and 5 deletions.
diff --git a/tests/random-variables/post_randomize.sv b/tests/random-variables/post_randomize.sv
@@ -20,7 +20,8 @@ class Cls;
 endclass
 
 module top (
-    output logic [7:0] o
+            input              clk,
+            output logic [7:0] o
 );
     Cls obj;
     initial begin

diff --git a/tests/random-variables/pre_randomize.sv b/tests/random-variables/pre_randomize.sv
@@ -20,7 +20,8 @@ class Cls;
 endclass
 
 module top (
-    output logic [7:0] o
+            input              clk,
+            output logic [7:0] o
 );
     Cls obj;
     initial begin

diff --git a/tests/random-variables/rand_mode.sv b/tests/random-variables/rand_mode.sv
@@ -15,7 +15,8 @@ class Cls;
 endclass
 
 module top (
-    output logic [7:0] o
+            input              clk,
+            output logic [7:0] o
 );
     Cls obj;
     initial begin

diff --git a/tests/random-variables/randcase.sv b/tests/random-variables/randcase.sv
@@ -6,7 +6,8 @@
 */
 
 module top (
-    output int o
+            input clk,
+            output int o
 );
    int val;
    initial begin

diff --git a/tests/random-variables/randsequence.sv b/tests/random-variables/randsequence.sv
@@ -5,7 +5,7 @@
    *** End of description
 */
 
-module top;
+module top(input clk);
    task display_sequence();
    // Example
      randsequence (main)