APB

#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1110-g18392a46)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
S_000001bef3ad2ac0 .scope module, "APB_tb" "APB_tb" 2 1;
 .timescale 0 0;
v000001bef3b36d30_0 .var "Address", 4 0;
v000001bef3b36f10_0 .var "PCLK", 0 0;
v000001bef3b37cd0_0 .var "PRESETn", 0 0;
v000001bef3b36e70_0 .var "Transfer", 0 0;
v000001bef3b372d0_0 .var "Wr_Rd", 0 0;
v000001bef3b38130_0 .net "read_data", 31 0, v000001bef3b35fa0_0;  1 drivers
v000001bef3b384f0_0 .var "write_data", 31 0;
S_000001bef3ad2c50 .scope module, "DUT" "APB_top" 2 6, 3 4 0, S_000001bef3ad2ac0;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "PCLK";
    .port_info 1 /INPUT 1 "PRESETn";
    .port_info 2 /INPUT 1 "Transfer";
    .port_info 3 /INPUT 1 "Wr_Rd";
    .port_info 4 /INPUT 5 "Address";
    .port_info 5 /INPUT 32 "write_data";
    .port_info 6 /OUTPUT 32 "read_data";
v000001bef3b365e0_0 .net "Address", 4 0, v000001bef3b36d30_0;  1 drivers
v000001bef3b35c80_0 .net "PADDR", 4 0, v000001bef3acd350_0;  1 drivers
v000001bef3b367c0_0 .net "PCLK", 0 0, v000001bef3b36f10_0;  1 drivers
v000001bef3b358c0_0 .net "PENABLE", 0 0, v000001bef3ad95b0_0;  1 drivers
v000001bef3b35960_0 .net "PRDATA", 31 0, v000001bef3b36540_0;  1 drivers
v000001bef3b35a00_0 .net "PREADY", 0 0, v000001bef3b35d20_0;  1 drivers
v000001bef3b35aa0_0 .net "PRESETn", 0 0, v000001bef3b37cd0_0;  1 drivers
v000001bef3b35b40_0 .net "PSELx", 0 0, v000001bef3a92960_0;  1 drivers
v000001bef3b35be0_0 .net "PSLVERR", 0 0, v000001bef3b360e0_0;  1 drivers
v000001bef3b37ff0_0 .net "PWDATA", 31 0, v000001bef3a92aa0_0;  1 drivers
v000001bef3b37370_0 .net "PWRITE", 0 0, v000001bef3a92b40_0;  1 drivers
v000001bef3b37e10_0 .net "Transfer", 0 0, v000001bef3b36e70_0;  1 drivers
v000001bef3b37eb0_0 .net "Wr_Rd", 0 0, v000001bef3b372d0_0;  1 drivers
v000001bef3b36970_0 .net "read_data", 31 0, v000001bef3b35fa0_0;  alias, 1 drivers
v000001bef3b37870_0 .net "write_data", 31 0, v000001bef3b384f0_0;  1 drivers
S_000001bef3ad2de0 .scope module, "Design_master" "APB_master" 3 16, 4 1 0, S_000001bef3ad2c50;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "Transfer";
    .port_info 1 /INPUT 1 "Wr_Rd";
    .port_info 2 /INPUT 5 "Address";
    .port_info 3 /INPUT 32 "write_data";
    .port_info 4 /OUTPUT 32 "read_data";
    .port_info 5 /INPUT 1 "PCLK";
    .port_info 6 /INPUT 1 "PRESETn";
    .port_info 7 /INPUT 1 "PREADY";
    .port_info 8 /INPUT 32 "PRDATA";
    .port_info 9 /INPUT 1 "PSLVERR";
    .port_info 10 /OUTPUT 5 "PADDR";
    .port_info 11 /OUTPUT 1 "PSELx";
    .port_info 12 /OUTPUT 1 "PENABLE";
    .port_info 13 /OUTPUT 1 "PWRITE";
    .port_info 14 /OUTPUT 32 "PWDATA";
P_000001bef3ad92c0 .param/l "ACCESS" 0 4 17, C4<10>;
P_000001bef3ad92f8 .param/l "IDLE" 0 4 17, C4<00>;
P_000001bef3ad9330 .param/l "SETUP" 0 4 17, C4<01>;
v000001bef3ad9470_0 .net "Address", 4 0, v000001bef3b36d30_0;  alias, 1 drivers
v000001bef3acd350_0 .var "PADDR", 4 0;
v000001bef3ad9510_0 .net "PCLK", 0 0, v000001bef3b36f10_0;  alias, 1 drivers
v000001bef3ad95b0_0 .var "PENABLE", 0 0;
v000001bef3ad9650_0 .net "PRDATA", 31 0, v000001bef3b36540_0;  alias, 1 drivers
v000001bef3ad96f0_0 .net "PREADY", 0 0, v000001bef3b35d20_0;  alias, 1 drivers
v000001bef3a928c0_0 .net "PRESETn", 0 0, v000001bef3b37cd0_0;  alias, 1 drivers
v000001bef3a92960_0 .var "PSELx", 0 0;
v000001bef3a92a00_0 .net "PSLVERR", 0 0, v000001bef3b360e0_0;  alias, 1 drivers
v000001bef3a92aa0_0 .var "PWDATA", 31 0;
v000001bef3a92b40_0 .var "PWRITE", 0 0;
v000001bef3a92be0_0 .net "Transfer", 0 0, v000001bef3b36e70_0;  alias, 1 drivers
v000001bef3b36400_0 .net "Wr_Rd", 0 0, v000001bef3b372d0_0;  alias, 1 drivers
v000001bef3b36180_0 .var "ns", 1 0;
v000001bef3b36680_0 .var "ps", 1 0;
v000001bef3b35fa0_0 .var "read_data", 31 0;
v000001bef3b36720_0 .net "write_data", 31 0, v000001bef3b384f0_0;  alias, 1 drivers
E_000001bef3ab9570 .event anyedge, v000001bef3ad96f0_0, v000001bef3a92be0_0, v000001bef3b36680_0;
E_000001bef3ab95b0 .event posedge, v000001bef3ad9510_0;
S_000001bef3ac38d0 .scope module, "Design_slave" "APB_slave" 3 17, 5 1 0, S_000001bef3ad2c50;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "PCLK";
    .port_info 1 /INPUT 1 "PRESETn";
    .port_info 2 /INPUT 5 "PADDR";
    .port_info 3 /INPUT 1 "PSELx";
    .port_info 4 /INPUT 1 "PENABLE";
    .port_info 5 /INPUT 1 "PWRITE";
    .port_info 6 /INPUT 32 "PWDATA";
    .port_info 7 /OUTPUT 1 "PREADY";
    .port_info 8 /OUTPUT 32 "PRDATA";
    .port_info 9 /OUTPUT 1 "PSLVERR";
v000001bef3b362c0_0 .net "PADDR", 4 0, v000001bef3acd350_0;  alias, 1 drivers
v000001bef3b36040_0 .net "PCLK", 0 0, v000001bef3b36f10_0;  alias, 1 drivers
v000001bef3b364a0_0 .net "PENABLE", 0 0, v000001bef3ad95b0_0;  alias, 1 drivers
v000001bef3b36540_0 .var "PRDATA", 31 0;
v000001bef3b35d20_0 .var "PREADY", 0 0;
v000001bef3b35dc0_0 .net "PRESETn", 0 0, v000001bef3b37cd0_0;  alias, 1 drivers
v000001bef3b36220_0 .net "PSELx", 0 0, v000001bef3a92960_0;  alias, 1 drivers
v000001bef3b360e0_0 .var "PSLVERR", 0 0;
v000001bef3b35e60_0 .net "PWDATA", 31 0, v000001bef3a92aa0_0;  alias, 1 drivers
v000001bef3b35f00_0 .net "PWRITE", 0 0, v000001bef3a92b40_0;  alias, 1 drivers
v000001bef3b36360 .array "mem", 31 0, 31 0;
E_000001bef3ab9d70/0 .event anyedge, v000001bef3a928c0_0, v000001bef3a92960_0, v000001bef3ad95b0_0, v000001bef3a92b40_0;
v000001bef3b36360_0 .array/port v000001bef3b36360, 0;
v000001bef3b36360_1 .array/port v000001bef3b36360, 1;
v000001bef3b36360_2 .array/port v000001bef3b36360, 2;
E_000001bef3ab9d70/1 .event anyedge, v000001bef3acd350_0, v000001bef3b36360_0, v000001bef3b36360_1, v000001bef3b36360_2;
v000001bef3b36360_3 .array/port v000001bef3b36360, 3;
v000001bef3b36360_4 .array/port v000001bef3b36360, 4;
v000001bef3b36360_5 .array/port v000001bef3b36360, 5;
v000001bef3b36360_6 .array/port v000001bef3b36360, 6;
E_000001bef3ab9d70/2 .event anyedge, v000001bef3b36360_3, v000001bef3b36360_4, v000001bef3b36360_5, v000001bef3b36360_6;
v000001bef3b36360_7 .array/port v000001bef3b36360, 7;
v000001bef3b36360_8 .array/port v000001bef3b36360, 8;
v000001bef3b36360_9 .array/port v000001bef3b36360, 9;
v000001bef3b36360_10 .array/port v000001bef3b36360, 10;
E_000001bef3ab9d70/3 .event anyedge, v000001bef3b36360_7, v000001bef3b36360_8, v000001bef3b36360_9, v000001bef3b36360_10;
v000001bef3b36360_11 .array/port v000001bef3b36360, 11;
v000001bef3b36360_12 .array/port v000001bef3b36360, 12;
v000001bef3b36360_13 .array/port v000001bef3b36360, 13;
v000001bef3b36360_14 .array/port v000001bef3b36360, 14;
E_000001bef3ab9d70/4 .event anyedge, v000001bef3b36360_11, v000001bef3b36360_12, v000001bef3b36360_13, v000001bef3b36360_14;
v000001bef3b36360_15 .array/port v000001bef3b36360, 15;
v000001bef3b36360_16 .array/port v000001bef3b36360, 16;
v000001bef3b36360_17 .array/port v000001bef3b36360, 17;
v000001bef3b36360_18 .array/port v000001bef3b36360, 18;
E_000001bef3ab9d70/5 .event anyedge, v000001bef3b36360_15, v000001bef3b36360_16, v000001bef3b36360_17, v000001bef3b36360_18;
v000001bef3b36360_19 .array/port v000001bef3b36360, 19;
v000001bef3b36360_20 .array/port v000001bef3b36360, 20;
v000001bef3b36360_21 .array/port v000001bef3b36360, 21;
v000001bef3b36360_22 .array/port v000001bef3b36360, 22;
E_000001bef3ab9d70/6 .event anyedge, v000001bef3b36360_19, v000001bef3b36360_20, v000001bef3b36360_21, v000001bef3b36360_22;
v000001bef3b36360_23 .array/port v000001bef3b36360, 23;
v000001bef3b36360_24 .array/port v000001bef3b36360, 24;
v000001bef3b36360_25 .array/port v000001bef3b36360, 25;
v000001bef3b36360_26 .array/port v000001bef3b36360, 26;
E_000001bef3ab9d70/7 .event anyedge, v000001bef3b36360_23, v000001bef3b36360_24, v000001bef3b36360_25, v000001bef3b36360_26;
v000001bef3b36360_27 .array/port v000001bef3b36360, 27;
v000001bef3b36360_28 .array/port v000001bef3b36360, 28;
v000001bef3b36360_29 .array/port v000001bef3b36360, 29;
v000001bef3b36360_30 .array/port v000001bef3b36360, 30;
E_000001bef3ab9d70/8 .event anyedge, v000001bef3b36360_27, v000001bef3b36360_28, v000001bef3b36360_29, v000001bef3b36360_30;
v000001bef3b36360_31 .array/port v000001bef3b36360, 31;
E_000001bef3ab9d70/9 .event anyedge, v000001bef3b36360_31, v000001bef3a92aa0_0;
E_000001bef3ab9d70 .event/or E_000001bef3ab9d70/0, E_000001bef3ab9d70/1, E_000001bef3ab9d70/2, E_000001bef3ab9d70/3, E_000001bef3ab9d70/4, E_000001bef3ab9d70/5, E_000001bef3ab9d70/6, E_000001bef3ab9d70/7, E_000001bef3ab9d70/8, E_000001bef3ab9d70/9;
    .scope S_000001bef3ad2de0;
T_0 ;
    %wait E_000001bef3ab95b0;
    %load/vec4 v000001bef3a928c0_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_0.0, 8;
    %pushi/vec4 0, 0, 2;
    %assign/vec4 v000001bef3b36680_0, 0;
    %jmp T_0.1;
T_0.0 ;
    %load/vec4 v000001bef3b36180_0;
    %assign/vec4 v000001bef3b36680_0, 0;
T_0.1 ;
    %jmp T_0;
    .thread T_0;
    .scope S_000001bef3ad2de0;
T_1 ;
    %wait E_000001bef3ab9570;
    %load/vec4 v000001bef3a928c0_0;
    %nor/r;
    %flag_set/vec4 8;
    %load/vec4 v000001bef3a92be0_0;
    %nor/r;
    %flag_set/vec4 9;
    %flag_or 9, 8;
    %jmp/0xz  T_1.0, 9;
    %pushi/vec4 0, 0, 2;
    %assign/vec4 v000001bef3b36180_0, 0;
    %jmp T_1.1;
T_1.0 ;
    %load/vec4 v000001bef3b36400_0;
    %store/vec4 v000001bef3a92b40_0, 0, 1;
    %load/vec4 v000001bef3b36680_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 2;
    %cmp/u;
    %jmp/1 T_1.2, 6;
    %dup/vec4;
    %pushi/vec4 1, 0, 2;
    %cmp/u;
    %jmp/1 T_1.3, 6;
    %dup/vec4;
    %pushi/vec4 2, 0, 2;
    %cmp/u;
    %jmp/1 T_1.4, 6;
    %pushi/vec4 0, 0, 2;
    %assign/vec4 v000001bef3b36180_0, 0;
    %jmp T_1.6;
T_1.2 ;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001bef3a92960_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001bef3ad95b0_0, 0, 1;
    %pushi/vec4 1, 0, 2;
    %assign/vec4 v000001bef3b36180_0, 0;
    %jmp T_1.6;
T_1.3 ;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000001bef3a92960_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001bef3ad95b0_0, 0, 1;
    %load/vec4 v000001bef3ad9470_0;
    %store/vec4 v000001bef3acd350_0, 0, 5;
    %load/vec4 v000001bef3a92b40_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_1.7, 8;
    %load/vec4 v000001bef3b36720_0;
    %assign/vec4 v000001bef3a92aa0_0, 0;
T_1.7 ;
    %load/vec4 v000001bef3a92a00_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_1.9, 8;
    %pushi/vec4 2, 0, 2;
    %assign/vec4 v000001bef3b36180_0, 0;
    %jmp T_1.10;
T_1.9 ;
    %pushi/vec4 0, 0, 2;
    %assign/vec4 v000001bef3b36180_0, 0;
T_1.10 ;
    %jmp T_1.6;
T_1.4 ;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000001bef3a92960_0, 0, 1;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000001bef3ad95b0_0, 0, 1;
    %load/vec4 v000001bef3a92a00_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_1.11, 8;
    %load/vec4 v000001bef3ad96f0_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_1.13, 8;
    %load/vec4 v000001bef3a92b40_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_1.15, 8;
    %pushi/vec4 2, 0, 2;
    %assign/vec4 v000001bef3b36180_0, 0;
    %jmp T_1.16;
T_1.15 ;
    %load/vec4 v000001bef3a92b40_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_1.17, 8;
    %load/vec4 v000001bef3ad9650_0;
    %store/vec4 v000001bef3b35fa0_0, 0, 32;
    %pushi/vec4 2, 0, 2;
    %assign/vec4 v000001bef3b36180_0, 0;
T_1.17 ;
T_1.16 ;
    %jmp T_1.14;
T_1.13 ;
    %load/vec4 v000001bef3ad96f0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_1.19, 8;
    %pushi/vec4 1, 0, 2;
    %assign/vec4 v000001bef3b36180_0, 0;
T_1.19 ;
T_1.14 ;
    %jmp T_1.12;
T_1.11 ;
    %pushi/vec4 0, 0, 2;
    %assign/vec4 v000001bef3b36180_0, 0;
T_1.12 ;
    %jmp T_1.6;
T_1.6 ;
    %pop/vec4 1;
T_1.1 ;
    %jmp T_1;
    .thread T_1, $push;
    .scope S_000001bef3ac38d0;
T_2 ;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001bef3b360e0_0, 0, 1;
    %end;
    .thread T_2;
    .scope S_000001bef3ac38d0;
T_3 ;
    %wait E_000001bef3ab9d70;
    %load/vec4 v000001bef3b35dc0_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_3.0, 8;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001bef3b35d20_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001bef3b360e0_0, 0, 1;
    %jmp T_3.1;
T_3.0 ;
    %load/vec4 v000001bef3b36220_0;
    %load/vec4 v000001bef3b364a0_0;
    %nor/r;
    %and;
    %load/vec4 v000001bef3b35f00_0;
    %nor/r;
    %and;
    %flag_set/vec4 8;
    %jmp/0xz  T_3.2, 8;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001bef3b35d20_0, 0, 1;
    %jmp T_3.3;
T_3.2 ;
    %load/vec4 v000001bef3b36220_0;
    %load/vec4 v000001bef3b364a0_0;
    %and;
    %load/vec4 v000001bef3b35f00_0;
    %nor/r;
    %and;
    %flag_set/vec4 8;
    %jmp/0xz  T_3.4, 8;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000001bef3b35d20_0, 0, 1;
    %load/vec4 v000001bef3b362c0_0;
    %pad/u 7;
    %ix/vec4 4;
    %load/vec4a v000001bef3b36360, 4;
    %store/vec4 v000001bef3b36540_0, 0, 32;
    %jmp T_3.5;
T_3.4 ;
    %load/vec4 v000001bef3b36220_0;
    %load/vec4 v000001bef3b364a0_0;
    %nor/r;
    %and;
    %load/vec4 v000001bef3b35f00_0;
    %and;
    %flag_set/vec4 8;
    %jmp/0xz  T_3.6, 8;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001bef3b35d20_0, 0, 1;
    %jmp T_3.7;
T_3.6 ;
    %load/vec4 v000001bef3b36220_0;
    %load/vec4 v000001bef3b364a0_0;
    %and;
    %load/vec4 v000001bef3b35f00_0;
    %and;
    %flag_set/vec4 8;
    %jmp/0xz  T_3.8, 8;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000001bef3b35d20_0, 0, 1;
    %load/vec4 v000001bef3b35e60_0;
    %load/vec4 v000001bef3b362c0_0;
    %pad/u 7;
    %ix/vec4 4;
    %store/vec4a v000001bef3b36360, 4, 0;
    %jmp T_3.9;
T_3.8 ;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001bef3b35d20_0, 0, 1;
T_3.9 ;
T_3.7 ;
T_3.5 ;
T_3.3 ;
T_3.1 ;
    %jmp T_3;
    .thread T_3, $push;
    .scope S_000001bef3ad2ac0;
T_4 ;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001bef3b36f10_0, 0, 1;
T_4.0 ;
    %delay 5, 0;
    %load/vec4 v000001bef3b36f10_0;
    %inv;
    %store/vec4 v000001bef3b36f10_0, 0, 1;
    %jmp T_4.0;
    %end;
    .thread T_4;
    .scope S_000001bef3ad2ac0;
T_5 ;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000001bef3b37cd0_0, 0, 1;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000001bef3b36e70_0, 0, 1;
    %pushi/vec4 18, 0, 5;
    %store/vec4 v000001bef3b36d30_0, 0, 5;
    %delay 10, 0;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000001bef3b372d0_0, 0, 1;
    %pushi/vec4 3735928559, 0, 32;
    %store/vec4 v000001bef3b384f0_0, 0, 32;
    %delay 10, 0;
    %pushi/vec4 21, 0, 5;
    %store/vec4 v000001bef3b36d30_0, 0, 5;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000001bef3b372d0_0, 0, 1;
    %pushi/vec4 3669740286, 0, 32;
    %store/vec4 v000001bef3b384f0_0, 0, 32;
    %delay 30, 0;
    %pushi/vec4 4294967295, 4294967295, 32;
    %store/vec4 v000001bef3b384f0_0, 0, 32;
    %delay 10, 0;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001bef3b36e70_0, 0, 1;
    %delay 15, 0;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000001bef3b36e70_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001bef3b372d0_0, 0, 1;
    %pushi/vec4 18, 0, 5;
    %store/vec4 v000001bef3b36d30_0, 0, 5;
    %delay 30, 0;
    %pushi/vec4 21, 0, 5;
    %store/vec4 v000001bef3b36d30_0, 0, 5;
    %delay 20, 0;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000001bef3b36e70_0, 0, 1;
    %delay 20, 0;
    %vpi_call 2 46 "$finish" {0 0 0};
    %end;
    .thread T_5;
    .scope S_000001bef3ad2ac0;
T_6 ;
    %vpi_call 2 52 "$dumpfile", "APB_wave.vcd" {0 0 0};
    %vpi_call 2 53 "$dumpvars" {0 0 0};
    %end;
    .thread T_6;
# The file index is used to find the file name in the following table.
:file_names 6;
    "N/A";
    "<interactive>";
    ".\APB_tb.v";
    ".\APB_top.v";
    "./APB_master.v";
    "./APB_slave.v";