Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

ad7616: Updated FPGA part number #134

Merged
merged 1 commit into from
Nov 13, 2024
Merged

ad7616: Updated FPGA part number #134

merged 1 commit into from
Nov 13, 2024

Conversation

IstvanZsSzekely
Copy link
Contributor

Using the 7-series Xilinx FPGA part, since the original Ultrascale+ part has different properties and requirements for the MMCM clock generation and the AD7616 project implementation is only available for Zedboard.
This fix is proposed since the latest update on the HDL for adding the FPGA_TECHNOLOGY for VCU boards affects the axi_clk_gen IP used in this project. Other projects are unaffected by this change.

- Using the 7-series Xilinx FPGA part, since the original Ultrascale+ part has different properties and requirements for the MMCM clock generation and the AD7616 project implementation is only available for Zedboard

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely IstvanZsSzekely added the bug Something isn't working label Nov 13, 2024
@IstvanZsSzekely IstvanZsSzekely self-assigned this Nov 13, 2024
@IstvanZsSzekely IstvanZsSzekely merged commit ee6a6d7 into main Nov 13, 2024
2 checks passed
@IstvanZsSzekely IstvanZsSzekely deleted the ad7616_fix branch November 13, 2024 09:58
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
bug Something isn't working
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants