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chore: fix brk.
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@YSawc
YSawc committed Apr 6, 2024
1 parent f43be24 commit 10fada8
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Showing 4 changed files with 37 additions and 101 deletions.
89 changes: 5 additions & 84 deletions dump_logs/nestest.log
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Original file line number Diff line number Diff line change
Expand Up @@ -8988,87 +8988,8 @@ c69a 8d 6 40 STA ABS A:ff X:ff Y:15 P:a5 S:fb pc: c69d, reg_addr: 4006, cycl
c69d a9 0 8d LDA IMM A:ff X:ff Y:15 P:a5 S:fb pc: c69f, reg_addr: 0, cycle: 26572
c69f 8d 7 40 STA ABS A: 0 X:ff Y:15 P:27 S:fb pc: c6a2, reg_addr: 4007, cycle: 26576
c6a2 60 a0 4e RTS IMPL A: 0 X:ff Y:15 P:27 S:fb pc: c66e, reg_addr: 0, cycle: 26582
c66e 60 a9 3 RTS IMPL A: 0 X:ff Y:15 P:27 S:fd pc: 25, reg_addr: 0, cycle: 26588
25 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 26, reg_addr: 0, cycle: 26595
26 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 27, reg_addr: 0, cycle: 26602
27 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 28, reg_addr: 0, cycle: 26609
28 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 29, reg_addr: 0, cycle: 26616
29 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 2a, reg_addr: 0, cycle: 26623
2a 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 2b, reg_addr: 0, cycle: 26630
2b 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 2c, reg_addr: 0, cycle: 26637
2c 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 2d, reg_addr: 0, cycle: 26644
2d 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 2e, reg_addr: 0, cycle: 26651
2e 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 2f, reg_addr: 0, cycle: 26658
2f 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 30, reg_addr: 0, cycle: 26665
30 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 31, reg_addr: 0, cycle: 26672
31 0 0 44 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 32, reg_addr: 0, cycle: 26679
32 0 44 4 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 33, reg_addr: 0, cycle: 26686
33 44 4 0 DOP ZP A: 0 X:ff Y:15 P:27 S:ff pc: 35, reg_addr: 4, cycle: 26689
35 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 36, reg_addr: 0, cycle: 26696
36 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 37, reg_addr: 0, cycle: 26703
37 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 38, reg_addr: 0, cycle: 26710
38 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 39, reg_addr: 0, cycle: 26717
39 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 3a, reg_addr: 0, cycle: 26724
3a 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 3b, reg_addr: 0, cycle: 26731
3b 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 3c, reg_addr: 0, cycle: 26738
3c 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 3d, reg_addr: 0, cycle: 26745
3d 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 3e, reg_addr: 0, cycle: 26752
3e 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 3f, reg_addr: 0, cycle: 26759
3f 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 40, reg_addr: 0, cycle: 26766
40 0 0 0 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 41, reg_addr: 0, cycle: 26773
41 0 0 ff BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 42, reg_addr: 0, cycle: 26780
42 0 ff 4 BRK IMPL A: 0 X:ff Y:15 P:27 S:ff pc: 43, reg_addr: 0, cycle: 26787
43 ff 4 48 ISB ABSX A: 0 X:ff Y:15 P:27 S:ff pc: 46, reg_addr: 4903, cycle: 26795
46 5 9b 6 ORA ZP A:ff X:ff Y:15 P:a4 S:ff pc: 48, reg_addr: 9b, cycle: 26798
48 6 0 0 ASL ZP A:ff X:ff Y:15 P:a4 S:ff pc: 4a, reg_addr: 0, cycle: 26803
4a 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 4b, reg_addr: 0, cycle: 26810
4b 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 4c, reg_addr: 0, cycle: 26817
4c 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 4d, reg_addr: 0, cycle: 26824
4d 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 4e, reg_addr: 0, cycle: 26831
4e 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 4f, reg_addr: 0, cycle: 26838
4f 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 50, reg_addr: 0, cycle: 26845
50 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 51, reg_addr: 0, cycle: 26852
51 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 52, reg_addr: 0, cycle: 26859
52 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 53, reg_addr: 0, cycle: 26866
53 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 54, reg_addr: 0, cycle: 26873
54 0 0 66 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 55, reg_addr: 0, cycle: 26880
55 0 66 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 56, reg_addr: 0, cycle: 26887
56 66 0 0 ROR ZP A:ff X:ff Y:15 P:26 S:ff pc: 58, reg_addr: 0, cycle: 26892
58 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 59, reg_addr: 0, cycle: 26899
59 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 5a, reg_addr: 0, cycle: 26906
5a 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 5b, reg_addr: 0, cycle: 26913
5b 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 5c, reg_addr: 0, cycle: 26920
5c 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 5d, reg_addr: 0, cycle: 26927
5d 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 5e, reg_addr: 0, cycle: 26934
5e 0 0 89 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 5f, reg_addr: 0, cycle: 26941
5f 0 89 4 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 60, reg_addr: 0, cycle: 26948
60 89 4 0 DOP IMM A:ff X:ff Y:15 P:26 S:ff pc: 62, reg_addr: 4, cycle: 26950
62 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 63, reg_addr: 0, cycle: 26957
63 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 64, reg_addr: 0, cycle: 26964
64 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 65, reg_addr: 0, cycle: 26971
65 0 0 87 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 66, reg_addr: 0, cycle: 26978
66 0 87 32 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 67, reg_addr: 0, cycle: 26985
67 87 32 0 SAX ZP A:ff X:ff Y:15 P:26 S:ff pc: 69, reg_addr: 32, cycle: 26988
69 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 6a, reg_addr: 0, cycle: 26995
6a 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 6b, reg_addr: 0, cycle: 27002
6b 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 6c, reg_addr: 0, cycle: 27009
6c 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 6d, reg_addr: 0, cycle: 27016
6d 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 6e, reg_addr: 0, cycle: 27023
6e 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 6f, reg_addr: 0, cycle: 27030
6f 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 70, reg_addr: 0, cycle: 27037
70 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 71, reg_addr: 0, cycle: 27044
71 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 72, reg_addr: 0, cycle: 27051
72 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 73, reg_addr: 0, cycle: 27058
73 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 74, reg_addr: 0, cycle: 27065
74 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 75, reg_addr: 0, cycle: 27072
75 0 0 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 76, reg_addr: 0, cycle: 27079
76 0 0 33 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 77, reg_addr: 0, cycle: 27086
77 0 33 0 BRK IMPL A:ff X:ff Y:15 P:26 S:ff pc: 78, reg_addr: 0, cycle: 27093
78 33 0 0 RLA INDY A:ff X:ff Y:15 P:26 S:ff pc: 7a, reg_addr: ff15, cycle: 27101
7a 0 0 0 BRK IMPL A:8e X:ff Y:15 P:a4 S:ff pc: 7b, reg_addr: 0, cycle: 27108
7b 0 0 0 BRK IMPL A:8e X:ff Y:15 P:a4 S:ff pc: 7c, reg_addr: 0, cycle: 27115
7c 0 0 0 BRK IMPL A:8e X:ff Y:15 P:a4 S:ff pc: 7d, reg_addr: 0, cycle: 27122
7d 0 0 69 BRK IMPL A:8e X:ff Y:15 P:a4 S:ff pc: 7e, reg_addr: 0, cycle: 27129
7e 0 69 0 BRK IMPL A:8e X:ff Y:15 P:a4 S:ff pc: 7f, reg_addr: 0, cycle: 27136
7f 69 0 2 ADC IMM A:8e X:ff Y:15 P:a4 S:ff pc: 81, reg_addr: 0, cycle: 27138
81 2 0 3 KIL IMPL A:8e X:ff Y:15 P:a4 S:ff
c66e 60 a9 3 RTS IMPL A: 0 X:ff Y:15 P:27 S:fd pc: 1, reg_addr: 0, cycle: 26588
1 ff 0 0 ISB ABSX A: 0 X:ff Y:15 P:27 S:ff pc: 4, reg_addr: ff, cycle: 26595
4 0 99 0 BRK IMPL A:b9 X:ff Y:15 P:a4 S:ff pc: c5f4, reg_addr: 0, cycle: 26602
c5f4 40 a2 0 RTI IMPL A:b9 X:ff Y:15 P:b4 S:fc pc: 6, reg_addr: 0, cycle: 26608
6 0 0 0 BRK IMPL A:b9 X:ff Y:15 P:b4 S:ff
41 changes: 29 additions & 12 deletions src/cpu/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -437,6 +437,10 @@ impl CPU {
self.register.mut_access_p().set_break_mode(data);
}

fn get_break_mode(&self) -> bool {
self.register.access_p().get_break_mode()
}

pub fn set_interrupt(&mut self, data: bool) {
self.register.mut_access_p().set_interrupt(data);
}
Expand Down Expand Up @@ -518,15 +522,20 @@ impl CPU {
self.register.get_s()
}

fn set_p(&mut self, data: u8) {
pub fn set_p(&mut self, data: u8) {
self.register.set_p(data);
}

pub fn dec_p(&mut self, data: u8) {
let s = self.register.get_s().wrapping_sub(data);
self.register.set_s(s);
}

pub fn get_p(&self) -> u8 {
self.register.get_p()
}

fn set_pc(&mut self, data: u16) {
pub fn set_pc(&mut self, data: u16) {
self.register.set_pc(data);
}

Expand All @@ -538,10 +547,6 @@ impl CPU {
self.register.inc_pc(data);
}

fn dec_pc(&mut self, data: u16) {
self.register.dec_pc(data);
}

fn fetch_register(&mut self) -> u8 {
self.bus.addr(self.get_pc())
}
Expand Down Expand Up @@ -759,9 +764,17 @@ impl CPU {

fn is_branch_enable(&self) -> bool {
if self.get_interrupt() {
false
true
} else {
false
}
}

fn is_break_enable(&self) -> bool {
if self.get_break_mode() {
true
} else {
false
}
}

Expand Down Expand Up @@ -1165,15 +1178,19 @@ impl CPU {
self.set_pc(self.get_pc().wrapping_add(1));
}
fn brk(&mut self) {
if self.is_break_enable() {
self.kil();
}

if self.is_branch_enable() {
self.dec_pc(1);
self.inc_pc(1);
self.push_pc();
let p = self.get_p();
self.push_stack(p);
self.set_break_mode(true);
self.set_interrupt(true);
let p = self.get_p();
self.push_stack(p);
let (h_data, l_data) = self.bus.cpu_bus.hl_addr(0xFFFE);
self.set_pc(combine_high_low(l_data, h_data));
self.set_pc(combine_high_low(h_data, l_data));
}
}
fn rti(&mut self) {
Expand Down Expand Up @@ -1321,7 +1338,7 @@ impl CPU {
"pc: {:>4x?}, reg_addr: {:>4x}, cycle: {:>6}",
self.register.get_pc(),
reg_addr,
self.total_cycle
self.total_cycle,
);
}
}
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/register.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@ impl Register {
a: 0,
x: 0,
y: 0,
s: u8::MAX,
s: 0,
p: P::default(),
pc: 0,
}
Expand Down
6 changes: 2 additions & 4 deletions src/emulator/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -117,10 +117,8 @@ impl Emulator {
}

pub fn startup(&mut self) {
let pc = self.cpu.get_pc() as u8;
self.cpu.push_stack(pc);
let p = self.cpu.get_p();
self.cpu.push_stack(p);
self.cpu.set_pc(0xFFFC);
self.cpu.dec_p(3);
self.cpu.reset();
}

Expand Down

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