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Refactoring of RTL MVAU/VVAU ops#977

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mmrahorovic wants to merge 141 commits intoXilinx:refactor/rtl_integrationXilinx/finn:refactor/rtl_integrationfrom mmrahorovic:refactor/mvu_vvu_rtl_opmmrahorovic/finn:refactor/mvu_vvu_rtl_opCopy head branch name to clipboard

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Commits on Jan 3, 2023

• First changes to custom_op for RTL-based MVAU

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Commits on Apr 5, 2023

• Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing

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Commits on Apr 6, 2023

• [rtl custom op]: initial implementation of mvu_8sx9

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• [rtl custom op]: testbench for mvu_8sx9

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• [rtl custom op]: initial implementation of flow control component for mvu_8sx9

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• [rtl custom op]: implementation of replay buffer for mvu

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• [rtl custom op]: testbench for mvu_8sx9_axi (including axi_wrapper & compute kernel)

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• [rtl custom op]: initial implementation of verilog wrapper for mvu_8sx9_axi

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• Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing

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Commits on Apr 11, 2023

• [rtl mvu]: fix tab indentation

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Commits on Apr 12, 2023

• [rtl custom op]: fix to indentation

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• [rtl custom-op]: minor changes for compiler integration

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• [rtl custom op]: moved testbenches to separate directory

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• [rtl custom op]: fixed output width to ACCU_WIDTH

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• [rtl custom op]: renamed file and added generic to switch between compute kernels

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• [rtl custom op]: renamed file and added generic to switch between compute kernels

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Commits on May 8, 2023

• [rtl mvu]: added behavioral model DSP58

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• [rtl mvu]: extended flow control wrapper with additional compute core and other minor changes

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• [rtl mvu]: fix to done_len flag when SIMD dimension fully unrolled and PyVerilator-related syntax change

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• [rtl mvu tb]: updated testbench

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• [builder]: added specialize_to_rtl step and changed standalone threshold layers to be by default true

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• [builder]: added specialize_to_rtl step

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• [custom op]: added custom op MatrixVectorActivation_rtl

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• [custom op]: added additional attribute to enable conversion to RTL (custom-op)

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• [custom op]: modified ip-stitching and code generation

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• [tests]: initial version of unit test for RTL custom op and specialize_to_rtl transformation for MVU

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• [rtl mvu]: specialized compute core for 4-bit weights and activations for DSP48/DSP58

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• [rtl mvu]: specialized compute core for > 4-bit weights and activations for DSP48

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• [fpgadataflow transform]: initial specialize_to_rtl_layers-transform for MVU

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Commits on May 9, 2023

• Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing

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• [rtl mvu] fixes for latest memstream + linting

  

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Commits on May 11, 2023

• [rtl custom_op]: add support for external weights

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• Specify clock and reset associations of bus interfaces.

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Commits on May 21, 2023

• Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing

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Commits on May 23, 2023

• Merge branch 'dev' into feature/dsp_packing

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• [rtlmvu] More fixes for memstream and param gen

  

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• [Build] apply config to only FIFO nodes in step_set_fifo_depths

  

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Commits on May 24, 2023

• Revised control interface attributes.

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• Merge branch 'dev' into feature/dsp_packing

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• Mask device primitives from Verilator in favor of using behavioral code.

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• [Deps] update qonnx

  

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• Adding folding hints. Impl selection by case statement.

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• Merge branch 'feature/verilator_workarounds' into feature/dsp_packing

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• Fixed behavioral sideband prediction.

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• Merge remote-tracking branch 'origin/feature/dsp_packing' into feature/dsp_packing

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• [rtl mvu]: extension to allow selecting PE values that are not multiples of 4

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• [rtlmvu] Avoid unintentional verilator metacomments

  

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• Merge remote-tracking branch 'origin/feature/dsp_packing' into feature/dsp_packing

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• [rtl mvu]: extension to allow selecting PE values that are not multiples of 2

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• [rtl mvu axi]: updated comments on folding hints

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Commits on Jun 2, 2023

• [rtl custom op]: minor fixes to codegen

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• [specialize-to-rtl]: add ram_style and rt_writeable_weights support

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• [rtllib]: change string type to parameter type due to Vivado error

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• [rtllib]: renamed variable for consistency

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• Fix improper blocking assignment & linting.

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• [test rtl mvu]: modified/extended test cases

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Commits on Jun 30, 2023

• [rtl mvu]: updated DSP58 >4-bit variant to lift SIMD%3==0 restriction

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• [rtl mvu]: bug fix for SIMD=1 init_leave_loads

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Commits on Jul 13, 2023

• [mvu rtl]: restrict index i to be less than 3 (within bounds of hi4)

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Commits on Jul 17, 2023

• Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing

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Commits on Jul 27, 2023

• Rewrite replay_buffer for input elasticity.

  

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Commits on Jul 31, 2023

• Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing

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Commits on Aug 16, 2023

• Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing

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Commits on Sep 5, 2023

• [to-rtl]: Infer unique node names after transformation is applied

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Commits on Sep 18, 2023

• [mvu rtl]: add synthesis directive to handle 'X in simulation

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• [replay buffer rtl]: minor fix to when LEN=1 (= AWIDTH=0)

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• [mvu lut]: LUT-based MVU compute core

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Commits on Sep 19, 2023

• [custom op]: add preferred_backend attribute

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Commits on Sep 21, 2023

• Ensure a minimum of two buffer slots even for length-1 sequences.

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• Merge pull request #1 from Xilinx/bugfix/replay_len1

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• Merge remote-tracking branch 'origin/feature/dsp_packing' into feature/dsp_packing

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• [rtl mvu wrapper]: support for vvu layer and rename

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• [mvu vvu tb]: modified testbench to also support testing VVU on DSP58

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• [axi wrapper]: minor modification to comment description

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• [mvu axi]: add support for VVU on DSP58

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• [mvu vvu axi]: renamed file for consistency purposes

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• [mvu 8sx9]: added support for VVU on DSP58, resolved PyVerilator-caused error and added synthesis directive to handle 'X in input data

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• [mvu vvu 8sx9]: renamed compute core for consistency

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• [axi wrapper]: changed parameter to localparam

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• [axi]: added support for LUT-based VVU

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• [mvu vvu 8sx9]: minor change to list of generics

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• [mvu lut]: added support for VVU

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• [mvu vvu lut]: renamed file for consistency

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• Revert to proper address truncation without generation bit.

  

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• remove deletd/renamed files

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• [mvu vvu 8sx9]: renamed for consistency

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• [mvu vvu axi]: changes for renamed module

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Commits on Sep 25, 2023

• [mvu vvu wrapper]: convert localparam to param

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• [mvau-rtl custom-op]: bugfix to instantiate memstreamer, modified renamed files and axi wrapper template fill-out

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• [specialize to rtl]: fix to changed attribute name and added support for converting HLS-based VVU custom-ops to RTL-based custom-ops

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• Adding core for DSP48 backport.

  

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• [mvu rtl core]: added support for signed activations for DSP48-based MVUs

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• [rtl mvu custom-op]: add upper bound to SEGMENTLEN equal to number of DSP58s chained together

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Commits on Oct 13, 2023

• [mvu_vvu dsp58]: change weight input to 2D instead of 3D array

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• [mvu_vvu axi]: re-wire weights appropriately for VVU DSP58

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• [mvu_vvu axi wrapper]: fix to IS_MVU parameter

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• [mvu_vvu tb]: WIP -- changes to self-checker and shape of input data

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Commits on Nov 27, 2023

• [mvu vvu axi]: minor bugfixes to enable VVU

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• [mvu vvu axi]: minor fix -- define mvauin_weight_t

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• Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing

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Commits on Nov 29, 2023

• [rtl mvu op]: minor fix to chain length estimation and enabled behavioral mode for rtl sim

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Commits on Jan 4, 2024

• [rtlsim]: use pyverilator util functions

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• [mvu vvu axi]: sign extend output tdata (byte-aligned)

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Commits on Jan 8, 2024

• [mvu core]: dsp48 convert unpacked array to packed array to work around limitation on max array indices in Verilator

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• [mvu axi]: update list of deduced parameters

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• [mvu custom-op]: remove lut-based implementation and update compute core selection

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• [mvu axi]: remove LUT-based compute core

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Commits on Jan 11, 2024

• [hls custom-op]: enable reset in sim

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• [test mvu rtl]: updated test flow (DSP58 only)

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• [mvu vvu axi]: reworked flow control and backpressure handling by tpreusser

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Commits on Jan 31, 2024

• Adding DSP48E1 support for 8-bit compute. Todo: finer core differentiation to select DSP48E2 explicitly again.

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• Adding DSP48E1 support for 4-bit compute. Todo: finer core differentiation to select DSP48E2 explicitly again.

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• [Tests] Temporarily re-enable SWG exception for bnn_w2_a2_cnv_Pynq-Z1 test

  

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• [Tests] Fix fpgadataflow split large fifos test

  

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• Fix linting

  

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• Merge pull request Xilinx#969 from Xilinx/bugfix/fifo_sizing_tests

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Commits on Feb 7, 2024

• [mvu vvu axi]: minor bugfixes to enable VVU

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• [mvu tb]: created separate vvu testbench and renamed mvu_vvu_axi tb

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• [mvu vvu axi]: minor fix -- define mvauin_weight_t

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• [folding]: first attempt to extend folding transformation to parallelize multi-packed DSPs in MVU/VVU more efficiently

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• Merge remote-tracking branch 'upstream/dev' into feature/dsp_packing_vvu

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• [mvu axi]: update list of deduced parameters

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• [mvu vvu axi]: reworked flow control and backpressure handling by tpreusser

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• [mvu/vvu axi]: picked out modifications from another branch to enable VVU

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• [mvu test]: cleaned up test

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Commits on Feb 8, 2024

• Revised control interface attributes.

  

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• [rtl mvu]: extension to allow selecting PE values that are not multiples of 4

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• Starting on pumped DSP compute.

  

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• pulled latest changes related to double-pumping

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• minor fix to param

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• Merge remote-tracking branch 'origin/feature/mvu_vvu_dsp_pumping' into refactor/mvu_vvu_rtl_op

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• added RTL-based MVAU and VVAU custom-ops

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• [builder]: renamed specialize_to_rtl step to specialize_layers step, default standalone_thresholds set to False

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• [builder]: added first version of specialize_layer step

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• pulled latest changes

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• fixed broken merge

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• [mvau hls]: added lut/dsp estimation functions, function for stitching the ip and small fix to node execution

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• [hwcustom op]: removed do_reset flag

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• [mvau hw-op]: moved lut/dsp estimations to specialized ops, modified stitched-ip method

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Commits on Feb 13, 2024

• [hls mvau]: fixed cppsim bipolar activations, added call to util functions from pyverilator and method to wire in IP

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• [hw mvau]: fixed bug for executing 2D arrays, modified create-stitched-ip method and reverted default resType to LUT

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