From eddbd270806da2d8e4a6febd5d5be89e887267e3 Mon Sep 17 00:00:00 2001
From: Felix Jentzsch <felix.jentzsch@upb.de>
Date: Thu, 4 Jan 2024 08:52:17 +0100
Subject: [PATCH] [RTL SWG] Use sliced vector assignment to avoid Verilator
 limitation

---
 finn-rtllib/swg/swg_common.sv | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/finn-rtllib/swg/swg_common.sv b/finn-rtllib/swg/swg_common.sv
index f2cdc333ca..c1d388550a 100644
--- a/finn-rtllib/swg/swg_common.sv
+++ b/finn-rtllib/swg/swg_common.sv
@@ -195,8 +195,7 @@ for (genvar e=0; e<DEPTH; e++)
 
 always @ (posedge clk) begin
     if (shift_enable) begin
-        for (int i=DEPTH-1; i>0; i--)
-            Data[i] <= Data[i-1];
+        if (DEPTH > 1) Data[DEPTH-1:1] <= Data[DEPTH-2:0];
         Data[0] <= shift_in;
     end
 end