lx2162som: add support for serdes 1 protocol 2 using 100MHz refclk

LX2162A SoM has an assembly option for replacing the default serdes 1 reference clock of 161MHz used for high-speed networking with a 100MHz clock supporting 1G networking and PCI. Add support for protocol 2 (4x 1Gbps) on LX2162A Clearfog Evaluation Board.
SolidRun · Dec 31, 2024 · 716a952 · 716a952
1 parent 497e9eb
commit 716a952
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diff --git a/patches/linux/0026-net-phy-ds250dfx10-add-support-for-1Gbps-SGMII-data-.patch b/patches/linux/0026-net-phy-ds250dfx10-add-support-for-1Gbps-SGMII-data-.patch
@@ -0,0 +1,130 @@
+From a185ff883ab8e3d2823590e73b7b000f470f02a2 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Tue, 31 Dec 2024 15:39:17 +0100
+Subject: [PATCH] net: phy: ds250dfx10: add support for 1Gbps SGMII data rate
+
+The DS250DFx10 retimers support a wide range of data rates, from
+1.25Gbps to 25.8.
+
+Add support for 1.25Gbps SGMII rate using the manual override registers.
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ drivers/phy/ti/phy-ti-ds250dfx10.c | 80 ++++++++++++++++++++++++++++++
+ 1 file changed, 80 insertions(+)
+
+diff --git a/drivers/phy/ti/phy-ti-ds250dfx10.c b/drivers/phy/ti/phy-ti-ds250dfx10.c
+index bfbbf35c430c..0ba6a1417533 100644
+--- a/drivers/phy/ti/phy-ti-ds250dfx10.c
++++ b/drivers/phy/ti/phy-ti-ds250dfx10.c
+@@ -71,6 +71,59 @@ static int ds250dfx10_write_register(struct i2c_client *client, uint8_t address,
+ 	return 0;
+ }
+
++static void ds250dfx10_config_1g(struct i2c_client *client, uint8_t channel)
++{
++	int ret = 0;
++
++	// enable smbus access to single channel
++	ret |= ds250dfx10_write_register(client, 0xFF, 0x01, 0x03);
++
++	// select channel
++	ret |= ds250dfx10_write_register(client, 0xFC, 1 << channel, 0xFF);
++
++	// reset channel registers
++	ret |= ds250dfx10_write_register(client, 0x00, 0x04, 0x04);
++
++	// assert cdr
++	ret |= ds250dfx10_write_register(client, 0x0A, 0x0C, 0x0C);
++
++	// set manual data rate override to 1.25Gbps
++	ret |= ds250dfx10_write_register(client, 0x60, 0x00, 0xFF);
++	ret |= ds250dfx10_write_register(client, 0x61, 0xb2, 0xFF);
++	ret |= ds250dfx10_write_register(client, 0x62, 0x00, 0xFF);
++	ret |= ds250dfx10_write_register(client, 0x63, 0xb2, 0xFF);
++
++	// set maximum ppm delta tolerance
++	ret |= ds250dfx10_write_register(client, 0x64, 0xFF, 0xFF);
++
++	// enable manual divider override
++	ret |= ds250dfx10_write_register(client, 0x09, 0x04, 0x04);
++
++	// set divider to 16
++	ret |= ds250dfx10_write_register(client, 0x18, 0x40, 0x70);
++
++	// enable pre- and post-fir
++	ret |= ds250dfx10_write_register(client, 0x3D, 0x80, 0x80);
++
++	// set main cursor magnitude +15
++	ret |= ds250dfx10_write_register(client, 0x3D, 0x00, 0x40);
++	ret |= ds250dfx10_write_register(client, 0x3D, 0x0F, 0x1F);
++
++	// set pre cursor magnitude -4
++	ret |= ds250dfx10_write_register(client, 0x3E, 0x40, 0x40);
++	ret |= ds250dfx10_write_register(client, 0x3E, 0x04, 0x0F);
++
++	// set post cursor magnitude -4
++	ret |= ds250dfx10_write_register(client, 0x3F, 0x40, 0x40);
++	ret |= ds250dfx10_write_register(client, 0x3F, 0x04, 0x0F);
++
++	// deassert cdr
++	ret |= ds250dfx10_write_register(client, 0x0A, 0x00, 0x0C);
++
++	if (!ret)
++		dev_info(&client->dev, "configured channel %u for 1G\n", channel);
++}
++
+ static void ds250dfx10_config_10g(struct i2c_client *client, uint8_t channel)
+ {
+ 	int ret = 0;
+@@ -87,6 +140,18 @@ static void ds250dfx10_config_10g(struct i2c_client *client, uint8_t channel)
+ 	// assert cdr
+ 	ret |= ds250dfx10_write_register(client, 0x0A, 0x0C, 0x0C);
+
++	// disable manual data rate override
++	ret |= ds250dfx10_write_register(client, 0x60, 0x00, 0xFF);
++	ret |= ds250dfx10_write_register(client, 0x61, 0x00, 0xFF);
++	ret |= ds250dfx10_write_register(client, 0x62, 0x00, 0xFF);
++	ret |= ds250dfx10_write_register(client, 0x63, 0x00, 0xFF);
++
++	// set minimum ppm delta tolerance (reset-default)
++	ret |= ds250dfx10_write_register(client, 0x64, 0x00, 0xFF);
++
++	// disable manual divider override
++	ret |= ds250dfx10_write_register(client, 0x09, 0x00, 0x04);
++
+ 	// select 10.3125 rate
+ 	ret |= ds250dfx10_write_register(client, 0x2F, 0x00, 0xF0);
+
+@@ -128,6 +193,18 @@ static void ds250dfx10_config_25g(struct i2c_client *client, uint8_t channel)
+ 	// assert cdr
+ 	ret |= ds250dfx10_write_register(client, 0x0A, 0x0C, 0x0C);
+
++	// disable manual data rate override
++	ret |= ds250dfx10_write_register(client, 0x60, 0x00, 0xFF);
++	ret |= ds250dfx10_write_register(client, 0x61, 0x00, 0xFF);
++	ret |= ds250dfx10_write_register(client, 0x62, 0x00, 0xFF);
++	ret |= ds250dfx10_write_register(client, 0x63, 0x00, 0xFF);
++
++	// set minimum ppm delta tolerance (reset-default)
++	ret |= ds250dfx10_write_register(client, 0x64, 0x00, 0xFF);
++
++	// disable manual divider override
++	ret |= ds250dfx10_write_register(client, 0x09, 0x00, 0x04);
++
+ 	// select 25.78125 rate
+ 	ret |= ds250dfx10_write_register(client, 0x2F, 0x50, 0xF0);
+
+@@ -161,6 +238,9 @@ static int ds250dfx10_phy_set_mode(struct phy *phy, enum phy_mode mode, int subm
+ 		return -EOPNOTSUPP;
+
+ 	switch (submode) {
++	case PHY_INTERFACE_MODE_SGMII:
++		ds250dfx10_config_1g(priv->client, priv->channel);
++		break;
+ 	case PHY_INTERFACE_MODE_10GBASER:
+ 		ds250dfx10_config_10g(priv->client, priv->channel);
+ 		break;
+-- 
+2.43.0
+
diff --git a/patches/rcw/0021-lx2162asom-add-configuration-for-serdes-1-protocol-2.patch b/patches/rcw/0021-lx2162asom-add-configuration-for-serdes-1-protocol-2.patch
@@ -0,0 +1,132 @@
+From 2b1985294275e363693f8425c71f5f77c814ef32 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Tue, 31 Dec 2024 13:46:14 +0100
+Subject: [PATCH] lx2162asom: add configuration for serdes 1 protocol 2
+
+This configuration requires changing clock generator U10 on the SoM from
+161MHz to 100MHz.
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ .../rcw_2000_650_2900_2_11_0_auto.rcw         | 22 +++++++++++++++++++
+ .../clearfog/rcw_2000_650_2900_2_7_0_auto.rcw | 22 +++++++++++++++++++
+ .../clearfog/rcw_2000_650_2900_2_9_0_auto.rcw | 19 ++++++++++++++++
+ lx2162asom_rev2/include/SD1_2.rcwi            | 22 +++++++++++++++++++
+ 4 files changed, 85 insertions(+)
+ create mode 100644 lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_11_0_auto.rcw
+ create mode 100644 lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_7_0_auto.rcw
+ create mode 100644 lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_9_0_auto.rcw
+ create mode 100644 lx2162asom_rev2/include/SD1_2.rcwi
+
+diff --git a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_11_0_auto.rcw b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_11_0_auto.rcw
+new file mode 100644
+index 0000000..683028a
+--- /dev/null
++++ b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_11_0_auto.rcw
+@@ -0,0 +1,22 @@
++/*
++ * SerDes Protocol 1 -  2
++ * SerDes Protocol 2 -  11
++ *
++ * Frequencies:
++ * Core     -- 2000 MHz
++ * Platform -- 650  MHz
++ * DDR      -- 2900 MT/s
++ *
++ */
++
++#define HAVE_PEX3
++#define HAVE_PEX4
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_650_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2162asom_rev2/include/common.rcwi>
++#include <../lx2162asom_rev2/include/SD1_2.rcwi>
++#include <../lx2162asom_rev2/include/SD2_11.rcwi>
++#include <../lx2160acex7/include/SD3_0.rcwi>
++#include <../lx2162asom_rev2/include/common_pbi.rcwi>
+diff --git a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_7_0_auto.rcw b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_7_0_auto.rcw
+new file mode 100644
+index 0000000..b08b804
+--- /dev/null
++++ b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_7_0_auto.rcw
+@@ -0,0 +1,22 @@
++/*
++ * SerDes Protocol 1 -  2
++ * SerDes Protocol 2 -  7
++ *
++ * Frequencies:
++ * Core     -- 2000 MHz
++ * Platform -- 650  MHz
++ * DDR      -- 2900 MT/s
++ *
++ */
++
++#define HAVE_PEX3
++#define HAVE_PEX4
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_650_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2162asom_rev2/include/common.rcwi>
++#include <../lx2162asom_rev2/include/SD1_2.rcwi>
++#include <../lx2162asom_rev2/include/SD2_7.rcwi>
++#include <../lx2160acex7/include/SD3_0.rcwi>
++#include <../lx2162asom_rev2/include/common_pbi.rcwi>
+diff --git a/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_9_0_auto.rcw b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_9_0_auto.rcw
+new file mode 100644
+index 0000000..d1a53ae
+--- /dev/null
++++ b/lx2162asom_rev2/clearfog/rcw_2000_650_2900_2_9_0_auto.rcw
+@@ -0,0 +1,19 @@
++/*
++ * SerDes Protocol 1 -  2
++ * SerDes Protocol 2 -  9
++ *
++ * Frequencies:
++ * Core     -- 2000 MHz
++ * Platform -- 650  MHz
++ * DDR      -- 2900 MT/s
++ *
++ */
++
++#include <../lx2160asi/lx2160a.rcwi>
++#include <../lx2160acex7/include/pll_2000_650_xxxx.rcwi>
++#include <../lx2160acex7/include/pll_xxxx_xxx_2900.rcwi>
++#include <../lx2162asom_rev2/include/common.rcwi>
++#include <../lx2162asom_rev2/include/SD1_2.rcwi>
++#include <../lx2162asom_rev2/include/SD2_9.rcwi>
++#include <../lx2160acex7/include/SD3_0.rcwi>
++#include <../lx2162asom_rev2/include/common_pbi.rcwi>
+diff --git a/lx2162asom_rev2/include/SD1_2.rcwi b/lx2162asom_rev2/include/SD1_2.rcwi
+new file mode 100644
+index 0000000..d2877db
+--- /dev/null
++++ b/lx2162asom_rev2/include/SD1_2.rcwi
+@@ -0,0 +1,22 @@
++/*
++ * This conmfiguration requires changing reference clock on SoM U10 from 161MHz to 100MHz.
++ */
++
++/* Serdes 1 Protocol 2: 4x1Gbps */
++SRDS_PRTCL_S1=2
++
++/* Disable Serdes 1 PLLF */
++SRDS_PLL_PD_PLL1=1
++
++/* Enable Serdes 1 PLLS */
++SRDS_PLL_PD_PLL2=0
++
++/* Use Serdes 1 PLLF for PLLS (LX2162A has no physical input for PLLS) */
++SRDS_INTRA_REF_CLK_S1=1
++
++/*
++ * Select Serdes 1 PLLF frequency 100MHz for 1GE mode (don't care): Bit 0 = 0
++ * Select Serdes 1 PLLS frequency 100MHz for 1GE mode: Bit 1 = 0
++ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932)
++ */
++SRDS_PLL_REF_CLK_SEL_S1=0
+-- 
+2.43.0
+
diff --git a/runme.sh b/runme.sh
@@ -106,15 +106,15 @@ case "${TARGET}" in
 		UBOOT_DEFCONFIG=lx2160acex7_tfa_defconfig
 		RCW_BOARD=CLEARFOG-CX
 	;;
-	LX2162A_SOM_CLEARFOG_18_9_0)
+	LX2162A_SOM_CLEARFOG_2_9_0|LX2162A_SOM_CLEARFOG_18_9_0)
 		ATF_PLATFORM=lx2162asom
 		DPC=clearfog-s1_3-s2_9-dpc.dtb
 		DPL=clearfog-s1_3-s2_9-dpl.dtb
 		DEFAULT_FDT_FILE="freescale/fsl-lx2162a-clearfog.dtb"
 		OPTEE_PLATFORM=ls-lx2160ardb
 		UBOOT_DEFCONFIG=lx2160acex7_tfa_defconfig
 	;;
-	LX2162A_SOM_CLEARFOG_18_7_0|LX2162A_SOM_CLEARFOG_18_11_0)
+	LX2162A_SOM_CLEARFOG_2_7_0|LX2162A_SOM_CLEARFOG_2_11_0|LX2162A_SOM_CLEARFOG_18_7_0|LX2162A_SOM_CLEARFOG_18_11_0)
 		ATF_PLATFORM=lx2162asom
 		DPC=clearfog-s1_3-s2_7-dpc.dtb
 		DPL=clearfog-s1_3-s2_7-dpl.dtb