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在运行tcl脚本生成FPGA工程时报错,缺少DifftestRunaheadEvent.v和DifftestRunaheadRedirectEvent.v #204

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huoyin01 opened this issue Jul 23, 2024 · 0 comments · Fixed by #206

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@huoyin01
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在make FPGA工程时会报找不到build/SimTop.v的错误,手动修改了Makefile文件,将其原本生成的build/rtl/Top.sv改为需要的SimTop.v文件后能够通过Makefile,但是在生成代码后使用Vivado的tcl脚本建立FPGA项目失败,查看tcl脚本发现其需求DifftestRunaheadEvent.v和DifftestRunaheadRedirectEvent.v文件,但我在编译后没有得到这些文件,是编译时哪里需要额外的设置吗?

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