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poemonsensepoemonsense
authoredAug 26, 2024··
Merge pull request #206 from zhangziqing/oscpu-master-wip
NutShell master branch re-adaption for FPGA platforms
2 parents d114ea0 + ecce4b9 commit 5dafeda

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10 files changed

+46
-35
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10 files changed

+46
-35
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‎.github/workflows/main.yml

+9-1
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,15 @@ jobs:
4545
source ./env.sh
4646
make clean
4747
make verilog
48-
48+
- name: Generate Verilog for FPGA
49+
run: |
50+
cd $GITHUB_WORKSPACE/../xs-env
51+
source ./env.sh
52+
cd $GITHUB_WORKSPACE/../xs-env/NutShell
53+
source ./env.sh
54+
make clean
55+
make verilog BOARD=pynq
56+
4957
- name: Microbench - Nutshell
5058
run: |
5159
cd $GITHUB_WORKSPACE/../xs-env

‎Makefile

+6-3
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,13 @@
11
TOP = TopMain
22
SIM_TOP = SimTop
3-
FPGATOP = NutShellFPGATop
3+
FPGATOP = Top
4+
REAL_TOP = $(if $(strip $(subst sim,,$(BOARD))),$(FPGATOP),$(SIM_TOP))
45

56
BUILD_DIR = $(abspath ./build)
67

78
RTL_DIR = $(BUILD_DIR)/rtl
89
RTL_SUFFIX ?= sv
9-
SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).$(RTL_SUFFIX)
10+
SIM_TOP_V = $(RTL_DIR)/$(REAL_TOP).$(RTL_SUFFIX) # if use FPGA, use FPGATOP
1011
TOP_V = $(RTL_DIR)/$(TOP).$(RTL_SUFFIX)
1112

1213
SCALA_FILE = $(shell find ./src/main/scala -name '*.scala')
@@ -40,7 +41,9 @@ $(TOP_V): $(SCALA_FILE)
4041
mkdir -p $(@D)
4142
mill -i generator.test.runMain top.$(TOP) $(MILL_ARGS_ALL) $(FPGA_ARGS)
4243
@mv $(SIM_TOP_V) $(TOP_V)
43-
sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' $@
44+
@for file in $(RTL_DIR)/*.$(RTL_SUFFIX); do \
45+
sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' "$$file"; \
46+
done
4447
@git log -n 1 >> .__head__
4548
@git diff >> .__diff__
4649
@sed -i 's/^/\/\// ' .__head__

‎fpga/NutShell.tcl

+1-3
Original file line numberDiff line numberDiff line change
@@ -25,9 +25,7 @@ set current_vivado_version [version -short]
2525

2626
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
2727
puts ""
28-
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
29-
30-
return 1
28+
catch {common::send_msg_id "BD_TCL-1002" "WARNING" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
3129
}
3230

3331
################################################################

‎fpga/board/PXIe/bd/arm.tcl

+1-3
Original file line numberDiff line numberDiff line change
@@ -25,9 +25,7 @@ set current_vivado_version [version -short]
2525

2626
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
2727
puts ""
28-
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
29-
30-
return 1
28+
catch {common::send_msg_id "BD_TCL-1002" "WARNING" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
3129
}
3230

3331
################################################################

‎fpga/board/axu3cg/bd/arm.tcl

+1-3
Original file line numberDiff line numberDiff line change
@@ -25,9 +25,7 @@ set current_vivado_version [version -short]
2525

2626
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
2727
puts ""
28-
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
29-
30-
return 1
28+
catch {common::send_msg_id "BD_TCL-1002" "WARNING" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
3129
}
3230

3331
################################################################

‎fpga/board/common.tcl

+8-9
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ set bd_dir ${script_dir}/bd
3030
set constr_dir ${script_dir}/constr
3131
set data_dir ${script_dir}/data
3232
set ip_dir ${script_dir}/ip
33+
set nutshell_build_dir ${fpga_dir}/../build/rtl
3334

3435
create_project $project_name -force -dir $project_dir/ -part ${device}
3536
if {[info exists board]} {
@@ -44,17 +45,15 @@ add_files -norecurse -fileset sources_1 $inc_files
4445
set_property is_global_include true [get_files $inc_files]
4546

4647
# Add files for nutshell
47-
lappend src_files "[file normalize "${fpga_dir}/../build/TopMain.v"]" \
48-
"[file normalize "${fpga_dir}/../build/DifftestRunaheadEvent.v"]" \
49-
"[file normalize "${fpga_dir}/../build/DifftestRunaheadRedirectEvent.v"]"
48+
set nutshell_rtl [glob -d ${nutshell_build_dir} *.sv or *.v]
5049

51-
add_files -norecurse -fileset sources_1 $src_files
50+
foreach src_file ${nutshell_rtl} {
51+
lappend src_files [file normalize $src_file]
52+
}
5253

53-
# Mark file type of difftest files as SystemVerilog to support DPI statements
54-
set_property file_type SystemVerilog -objects [get_files -of_objects [get_filesets sources_1] [list \
55-
"*/DifftestRunaheadRedirectEvent.v" \
56-
"*/DifftestRunaheadEvent.v" \
57-
]]
54+
add_files -norecurse -fileset sources_1 $src_files
55+
set_property file_type Verilog -objects [get_files -of_objects [get_filesets sources_1] *NutShell.sv]
56+
# vivado do not support a system verilog file be the top of a reference design, this may be removed as reference design is not need actually
5857

5958
if {[info exists xdc_files]} {
6059
add_files -norecurse -fileset constrs_1 $xdc_files

‎fpga/board/pynq/bd/standalone.tcl

+1-3
Original file line numberDiff line numberDiff line change
@@ -25,9 +25,7 @@ set current_vivado_version [version -short]
2525

2626
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
2727
puts ""
28-
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
29-
30-
return 1
28+
catch {common::send_msg_id "BD_TCL-1002" "WARNING" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
3129
}
3230

3331
################################################################

‎src/main/scala/nutcore/backend/fu/CSR.scala

+5-1
Original file line numberDiff line numberDiff line change
@@ -885,7 +885,11 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
885885
}}
886886

887887
val nutcoretrap = WireInit(false.B)
888-
BoringUtils.addSink(nutcoretrap, "nutcoretrap")
888+
if (!p.FPGAPlatform) {
889+
BoringUtils.addSink(nutcoretrap, "nutcoretrap")
890+
} else {
891+
nutcoretrap := 0.U
892+
}
889893
def readWithScala(addr: Int): UInt = mapping(addr)._1
890894

891895
if (!p.FPGAPlatform) {

‎src/main/scala/top/Settings.scala

+6-3
Original file line numberDiff line numberDiff line change
@@ -51,21 +51,24 @@ object PynqSettings {
5151
"MemMapBase" -> 0x0000000010000000L,
5252
"MemMapRegionBits" -> 28,
5353
"MMIOBase" -> 0x00000000e0000000L,
54-
"MMIOSize" -> 0x0000000020000000L
54+
"MMIOSize" -> 0x0000000020000000L,
55+
"EnableDebug" -> false
5556
)
5657
}
5758

5859
object Axu3cgSettings {
5960
def apply() = Map(
6061
"FPGAPlatform" -> true,
61-
"NrExtIntr" -> 2
62+
"NrExtIntr" -> 2,
63+
"EnableDebug" -> false
6264
)
6365
}
6466

6567
object PXIeSettings {
6668
def apply() = Map(
6769
"FPGAPlatform" -> true,
68-
"NrExtIntr" -> 5
70+
"NrExtIntr" -> 5,
71+
"EnableDebug" -> false
6972
)
7073
}
7174

‎src/main/scala/utils/Debug.scala

+8-6
Original file line numberDiff line numberDiff line change
@@ -42,12 +42,14 @@ object LogUtil {
4242
def apply(debugLevel: LogLevel)
4343
(prefix: Boolean, cond: Bool, pable: Printable)
4444
(implicit name: String): Any = {
45-
val c = control()
46-
val commonInfo = p"[${c._2}] $name: "
47-
when (cond && c._1) {
48-
if(prefix) printf(commonInfo)
49-
printf(pable)
50-
}
45+
if (NutCoreConfig().EnableDebug){
46+
val c = control()
47+
val commonInfo = p"[${c._2}] $name: "
48+
when (cond && c._1) {
49+
if(prefix) printf(commonInfo)
50+
printf(pable)
51+
}
52+
}
5153
}
5254
}
5355

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