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AMD mailbox driver support #7270

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Akshay-Belsare
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@Akshay-Belsare Akshay-Belsare commented Feb 10, 2025

Add support for the AMD Mailbox Service for use on AMD platforms.
The Mailbox Service requires the Local IPI ID as a mandatory input,
provided via CFG_MAILBOX_LOCAL_ID.
Mailbox initialization for CFG_MAILBOX_LOCAL_ID occurs as a late init
service and will be utilized by various drivers to communicate with other
firmware.
The remote ID will be supplied by different drivers using the mailbox
service.

@Akshay-Belsare Akshay-Belsare changed the title Amd mailbox driver support AMD mailbox driver support Feb 10, 2025
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Please fix the checkpatch issues.
This code is unused, do you plan to upstream code that uses the mailbox driver any time soon?

core/drivers/amd/mailbox_driver.c Outdated Show resolved Hide resolved
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Add support for the AMD Mailbox Service for use on AMD platforms.
The Mailbox Service requires the Local IPI ID as a mandatory input,
provided via CFG_MAILBOX_LOCAL_ID.
Mailbox initialization for CFG_MAILBOX_LOCAL_ID occurs as a late init
service and will be utilized by various drivers to communicate with other
firmware.
The remote ID will be supplied by different drivers using the mailbox
service.

Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
core/drivers/amd/mailbox_driver.c Outdated Show resolved Hide resolved
{
TEE_Result res = TEE_ERROR_GENERIC;

cache_operation(TEE_CACHEINVALIDATE, ipi_info.rsp, payload_size);
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By the way, cache_operation() may return an error code. If never awaited, maybe asserting the return value is enough. That said, I see that almost all callers of that function do not check the return value :(
There are all in core/drivers/.... Note that if ipi_info.rsp is NULL, the function would have returned an error.

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Let me revisit and modify accordingly.

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ldts commented Feb 13, 2025

um, isnt this driver just the same than versal_mbox.c currently upstream? it seems that the only difference is the base address 0xEB3F0000 instead of 0xFF3F0000
it has less features - no tracing support, no validation of multiple buffers - but other than that I fail to see the difference.

could you comment please?

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ldts commented Feb 13, 2025

Also, if this is an init_late it means you wont be able to use some of the chip cryptographic features like the PUF or SHA (or fuses for that matter) during boot. Not sure if it applies to your platform but just a heads up.
This is the reason why on versal we chose to open the mailbox early.

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ldts commented Feb 13, 2025

Also notice that given the nature of the firmware receiving the requests, mbox requests/responses usually consist of several buffers and the payload and each buffer had alignment requirements. as @jenswi-linaro mentioned, if would be nice to have an example of usage.

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Akshay-Belsare commented Feb 13, 2025

@ldts This driver is meant for a newer AMD Versal Gen 2 family and later versions. This change is having the base infra, more will be added to it later. The use case is different from the the versal platform.

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ldts commented Feb 13, 2025

@ldts This driver is meant for a newer AMD Versal Gen 2 family and later versions. This change is having the base infra, more will be added to it later. The use case is different from the the versal platform.

What do you mean by "more will be added to it later"? Are you referring to additional changes to this mailbox driver under review? This driver is a simplified version of versal_mbox.c, and my concern is that you may eventually need to make it more complex, resulting in something similar to what already exists.

Add AMD mailbox driver support for AMD Versal Gen 2 platform.
Keeping the config CFG_MAILBOX_DRIVER disabled by default.
Once a driver using the mailbox service is added and enabled
for this platform the configuration to be updated.

Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Address upstream review comments

Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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ldts commented Feb 13, 2025

one other piece of information, @jcorbier is doing some extensions to the versal_mbox driver (buffer memory management, mailbox timeouts etc 5418d26 ). So maybe that is something that you could also use (ie, timeouts)

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Akshay-Belsare commented Feb 13, 2025

@ldts

What do you mean by "more will be added to it later"? Are you referring to additional changes to this mailbox driver under review? This driver is a simplified version of versal_mbox.c, and my concern is that you may eventually need to make it more complex, resulting in something similar to what already exists.

As I mentioned, AMD Versal Gen 2 is new family and the underlying workings are not exactly same as Versal and Versal NET.

one other piece of information, @jcorbier is doing some extensions to the versal_mbox driver (buffer memory management, mailbox timeouts etc 5418d26 ). So maybe that is something that you could also use (ie, timeouts)

Appreciate, will have a look in to those changes as well.

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ldts commented Feb 13, 2025

thanks. but please, do take the time to ask my questions to avoid going in circles. This driver is a simplified version of what we currently have.

Address error condition cases as per review comments.

Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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@etienne-lms @jenswi-linaro
Added new patch addressing the review comments.

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ldts commented Feb 13, 2025

um you made me curious about the IPI Gen2 now, where can I find the PLM code? should it still be in the embeddedsw repo or is it now hosted somwhere else?

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4 participants