diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000..c18a021 --- /dev/null +++ b/.gitattributes @@ -0,0 +1,4 @@ +*.png filter=lfs diff=lfs merge=lfs -text +*.PNG filter=lfs diff=lfs merge=lfs -text +*.ai filter=lfs diff=lfs merge=lfs -text +*.pdf filter=lfs diff=lfs merge=lfs -text diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..ecb47e7 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "ofs-common"] + url = https://github.com/OFS/ofs-fim-common.git + path = ofs-common diff --git a/LICENSE.txt b/LICENSE.txt new file mode 100644 index 0000000..31591e9 --- /dev/null +++ b/LICENSE.txt @@ -0,0 +1,19 @@ +Copyright (c) 2022 Intel Corporation + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/README.md b/README.md new file mode 100644 index 0000000..f206065 --- /dev/null +++ b/README.md @@ -0,0 +1,41 @@ +# D5005 FPGA Development Directory + +This is the OFS D5005 Stratix 10 FPGA development top-level directory. + +## Cloning this repository + +*NOTE:* This repository uses [Git LFS](https://git-lfs.com/) to capture large files in the history without forcing the download of historic files during a plain `clone` operation. Please follow your preferred installation method [from the project's guide](https://github.com/git-lfs/git-lfs#installing) before proceeding. After installation, run `git lfs install` once to install hooks which will transparently fetch the large files into your workspace for use. + +To fetch both the `FIM` and `ofs-common` files in a single step, run the following command: + + `git clone --recurse-submodules https://github.com/OFS/ofs-d5005.git` + +## Directories + +### Evaluation Scripts (***eval\_scripts***) + - Contains resources to report and setup D5005 development environment. +### External Tools (***external***) + - Contains the software repositories needed for OFS/OPAE development and integration. + - Lightweight virtual environment containing the required Python packages needed for this repo and its tools. +### IP Subsystems (***ipss***) + - Contains the code and supporting files that define or set up the IP subsystems contained in the D5005 FPGA Interface Manager (FIM) +### Licensing for Quartus (***license***) + - Contains the license setup software for the version of Quartus used for this distribution/release of the D5005 product. +### OFS Common Content Directory (**Link to top-level directory _ofs-common_**) + - Contains the scripts, source code, and verification environment resources that are common to all of the repositories. + - This directory is referenced via a link within each of the FPGA-Specific repositories. +### Simulation + - Contains the testbenches and supporting code for all of the unit test simulations. + - Bus Functional Model code is contained here. + - Scripts are included for automating a myriad of tasks. + - All of the individual unit tests and their supporting code is also located here. +### FPGA Interface Module (FIM) Source code (***src***) + - This directory contains all of the structural and behavioral code for the FIM. + - Also included are scripts for generating the AXI buses for module interconnect. + - Top-level RTL for synthesis is located in this directory. + - Accelerated Functional Unit (AFU) infrastructure code is contained in this directory. +### FPGA Synthesis + - This directory contains all of the scripts, settings, and setup files for running synthesis on the FIM. +### Verification (UVM) (***verification***) + - This directory contains all of the scripts, testbenches, and test cases for the supported UVM tests for the D5005 FIM. + - **NOTE:** UVM resources are currently not available in this release due to difficulties in open-sourcing some components. It is hoped that this will be included in future releases. diff --git a/SECURITY.md b/SECURITY.md new file mode 100644 index 0000000..e70fcb0 --- /dev/null +++ b/SECURITY.md @@ -0,0 +1,6 @@ +# Security Policy +Intel is committed to rapidly addressing security vulnerabilities affecting our customers and providing clear guidance on the solution, impact, severity and mitigation. + +## Reporting a Vulnerability +Please report any security vulnerabilities in this project [utilizing the guidelines here](https://www.intel.com/content/www/us/en/security-center/vulnerability-handling-guidelines.html). + diff --git a/ipss/.gitignore b/ipss/.gitignore new file mode 100644 index 0000000..912bad8 --- /dev/null +++ b/ipss/.gitignore @@ -0,0 +1,20 @@ +*.bsf +*.cmp +*.csv +*.html +*.qgsimc +*.qgsynthc +*.sopcinfo +*.xml +*_bb.v +*.rpt +*_inst.v +*_inst.vhd +*.BAK.ip +.qsys_edit +aldec +cadence +ncsim_files.tcl +riviera_files.tcl +xcelium_files.tcl +xcelium diff --git a/ipss/README.md b/ipss/README.md new file mode 100644 index 0000000..0758f33 --- /dev/null +++ b/ipss/README.md @@ -0,0 +1,25 @@ +# D5005 IP Subsystem Directory + +This directory contains the code and supporting files that define or set up the IP subsystems contained in the D5005 FPGA Interface Manager (FIM) + +## Directories + +### High Speed Serial Interface (HSSI) Ethernet (***hssi***) + - This directory contains the top-level description of the HSSI block and all of its supporting code. + +### DDR4 Memory (***mem***) + - This directory contains the top-level description of the DDR4 subsystem. + - This directory also contains a lot of the settings regarding the physical interface management and PHY settings. + +### Peripheral Component Interconnect Express (PCIe) Interface (***pcie***) + - This directory contains the top-level description of the system's Peripheral Component Interconnect Express (PCIe) interface. + - This is the main connection between the D5005 card and the host computer system. + +### Platform Management Interface Controller (PMCI) (***pmci***) + - This directory contains the top-level RTL block that connects one of the FPGA's AXI-Lite interfaces to its system controller via a SPI Bridge. + +### Serial Peripheral Interconnect (SPI) (***spi***) + - This directory contains the top-level RTL for the SPI bridge. + - A set of Control and Status Registers (CSRs) are also defined here. + - The RTL defining these registers and their function is included here. + - An Excel spreadsheet is also contained here that provides a better human-readable format describing the CSRs and their intended function. diff --git a/ipss/hssi/inc/ofs_fim_eth_avst_if.sv b/ipss/hssi/inc/ofs_fim_eth_avst_if.sv new file mode 100755 index 0000000..94ea53f --- /dev/null +++ b/ipss/hssi/inc/ofs_fim_eth_avst_if.sv @@ -0,0 +1,137 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +//----------------------------------------------------------------------------- +// Description +//----------------------------------------------------------------------------- +// +// Avalon stream wrappers around the same payloads as the Ethernet AXI +// streams in ofs_fim_eth_if.sv. While AXI-S is used as the transport +// from the MAC to the AFU across the PR boundary, AFUs may be written +// using Avalon interfaces. The Platform Interface Manager provides a shim +// for mapping between the two protocols. +// +//----------------------------------------------------------------------------- + +// Interface of Eth RX AVST channel (MAC -> AFU) +interface ofs_fim_eth_rx_avst_if (); + logic clk; + logic rst_n; // Active-low reset + + import ofs_fim_eth_avst_if_pkg::*; + + t_avst_eth_rx rx; + + // Ready signal + logic ready; + + // AVST channel master (MAC side) + modport master ( + input ready, + output clk, + output rst_n, + output rx + ); + + // AVST channel slave + modport slave ( + output ready, + input clk, + input rst_n, + input rx + ); + +endinterface : ofs_fim_eth_rx_avst_if + + +// Interface of Eth TX AVST channel (MAC -> AFU) +interface ofs_fim_eth_tx_avst_if (); + logic clk; + logic rst_n; // Active-low reset + + import ofs_fim_eth_avst_if_pkg::*; + + t_avst_eth_tx tx; + + // Ready signal + logic ready; + + // AVST channel master (MAC side) + modport master ( + input ready, + input clk, + input rst_n, + output tx + ); + + // AVST channel slave + modport slave ( + output ready, + output clk, + output rst_n, + input tx + ); + +endinterface : ofs_fim_eth_tx_avst_if + + +// +// RX Interface of Eth sideband AVST channel (MAC -> AFU). +// +// There is no tready flow control on this interface. The payload may be +// time-sensitive. +// +interface ofs_fim_eth_sideband_rx_avst_if (); + logic clk; + logic rst_n; // Active-low reset + + import ofs_fim_eth_avst_if_pkg::*; + + t_avst_eth_sideband_rx sb; + + // AVST channel master (MAC side) + modport master ( + output clk, + output rst_n, + output sb + ); + + // AVST channel slave + modport slave ( + input clk, + input rst_n, + input sb + ); + +endinterface : ofs_fim_eth_sideband_rx_avst_if + + +// +// Tx Interface of Eth sideband AVST channel (AFU -> MAC) +// +// There is no tready flow control on this interface. The payload may be +// time-sensitive. +// +interface ofs_fim_eth_sideband_tx_avst_if (); + logic clk; + logic rst_n; // Active-low reset + + import ofs_fim_eth_avst_if_pkg::*; + + t_avst_eth_sideband_tx sb; + + // AVST channel master + modport master ( + input clk, + input rst_n, + output sb + ); + + // AVST channel slave (MAC side) + modport slave ( + output clk, + output rst_n, + input sb + ); + +endinterface : ofs_fim_eth_sideband_tx_avst_if diff --git a/ipss/hssi/inc/ofs_fim_eth_avst_if_pkg.sv b/ipss/hssi/inc/ofs_fim_eth_avst_if_pkg.sv new file mode 100755 index 0000000..51b4646 --- /dev/null +++ b/ipss/hssi/inc/ofs_fim_eth_avst_if_pkg.sv @@ -0,0 +1,111 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// AVST equivalent of the AXI-S Ethernet interface data structures. Types +// are derived from the AXI-S configuration. +// +//---------------------------------------------------------------------------- + +package ofs_fim_eth_avst_if_pkg; + +localparam MAX_NUM_AVST_ETH_CHANNELS = ofs_fim_eth_plat_if_pkg::MAX_NUM_ETH_CHANNELS; +localparam NUM_AVST_ETH_CHANNELS = ofs_fim_eth_plat_if_pkg::NUM_ETH_CHANNELS; + +localparam AVST_ETH_PACKET_WIDTH = ofs_fim_eth_plat_if_pkg::ETH_PACKET_WIDTH; +// Unlike AXI-S "tkeep", which is a mask, "empty" is a count of the number +// of unused bytes at the end of "data". +localparam AVST_ETH_EMPTY_WIDTH = $clog2(AVST_ETH_PACKET_WIDTH/8); + +localparam AVST_ETH_RX_ERROR_WIDTH = ofs_fim_eth_plat_if_pkg::ETH_RX_ERROR_WIDTH; +localparam AVST_ETH_TX_ERROR_WIDTH = ofs_fim_eth_plat_if_pkg::ETH_TX_ERROR_WIDTH; + +// Clocks exported by the MAC for use by the AFU. The primary "clk" is +// guaranteed. Others are platform-specific. +typedef ofs_fim_eth_plat_if_pkg::t_eth_clocks t_avst_eth_clocks; + +typedef ofs_fim_eth_plat_if_pkg::t_axis_eth_rx_tuser t_avst_eth_rx_user; +typedef ofs_fim_eth_plat_if_pkg::t_axis_eth_tx_tuser t_avst_eth_tx_user; + +// AVST RX channel (MAC -> AFU) +typedef struct packed { + logic valid; + logic sop; + logic eop; + logic [AVST_ETH_PACKET_WIDTH-1:0] data; + logic [AVST_ETH_EMPTY_WIDTH-1:0] empty; + t_avst_eth_rx_user user; +} t_avst_eth_rx; +localparam AVST_ETH_RX_WIDTH = $bits(t_avst_eth_rx); + +// AVST TX channel (AFU -> MAC) +typedef struct packed { + logic valid; + logic sop; + logic eop; + logic [AVST_ETH_PACKET_WIDTH-1:0] data; + logic [AVST_ETH_EMPTY_WIDTH-1:0] empty; + t_avst_eth_tx_user user; +} t_avst_eth_tx; +localparam AVST_ETH_TX_WIDTH = $bits(t_avst_eth_tx); + +// AVST sideband RX channel (MAC -> AFU) +typedef ofs_fim_eth_plat_if_pkg::t_eth_sideband_from_mac t_eth_sideband_from_mac; +localparam AVST_ETH_SIDEBAND_RX_PACKET_WIDTH = $bits(t_eth_sideband_from_mac); + +typedef struct packed { + logic valid; + t_eth_sideband_from_mac data; +} t_avst_eth_sideband_rx; + +// AVST sideband TX channel (AFU -> MAC) +typedef ofs_fim_eth_plat_if_pkg::t_eth_sideband_to_mac t_eth_sideband_to_mac; +localparam AVST_ETH_SIDEBAND_TX_PACKET_WIDTH = $bits(t_eth_sideband_to_mac); + +typedef struct packed { + logic valid; + t_eth_sideband_to_mac data; +} t_avst_eth_sideband_tx; + + +// Convert an AXI-S data payload to an AVST payload. The two use opposite byte +// order. +function automatic logic [AVST_ETH_PACKET_WIDTH-1:0] eth_axi_to_avst_data(logic [AVST_ETH_PACKET_WIDTH-1:0] i_data); + logic [AVST_ETH_PACKET_WIDTH-1:0] o_data; + + for (int b = 0; b < AVST_ETH_PACKET_WIDTH/8; b = b + 1) begin + o_data[8 * (AVST_ETH_PACKET_WIDTH/8 - 1 - b) +: 8] = i_data[8 * b +: 8]; + end + + return o_data; +endfunction + +// Convert an AVST data payload to an AXI-S payload. +function automatic logic [AVST_ETH_PACKET_WIDTH-1:0] eth_avst_to_axi_data(logic [AVST_ETH_PACKET_WIDTH-1:0] i_data); + // Reversing is the same operation in both directions + return eth_axi_to_avst_data(i_data); +endfunction + + +// Convert an AXI-S tkeep mask to an AVST empty. Empty is the count of unused +// bytes at the end of data. Tkeep is a byte mask. The MAC uses the empty encoding, +// so only the highest group of 0's in tkeep can act as a mask. +function automatic logic [AVST_ETH_EMPTY_WIDTH-1:0] eth_tkeep_to_empty(logic [ofs_fim_eth_if_pkg::ETH_TKEEP_WIDTH-1:0] tkeep); + logic [AVST_ETH_EMPTY_WIDTH-1:0] num_empty = 0; + + for (int b = ofs_fim_eth_if_pkg::ETH_TKEEP_WIDTH-1; b >= 0; b = b - 1) begin + if (tkeep[b]) break; + num_empty = num_empty + 1; + end + + return num_empty; +endfunction // eth_tkeep_to_empty + +// Reverse of eth_tkeep_to_empty above +function automatic logic [ofs_fim_eth_if_pkg::ETH_TKEEP_WIDTH-1:0] eth_empty_to_tkeep(logic [AVST_ETH_EMPTY_WIDTH-1:0] empty); + return {ofs_fim_eth_if_pkg::ETH_TKEEP_WIDTH{1'b1}} >> empty; +endfunction // eth_tkeep_to_empty + +endpackage diff --git a/ipss/hssi/inc/ofs_fim_eth_if.sv b/ipss/hssi/inc/ofs_fim_eth_if.sv new file mode 100755 index 0000000..f1c6a3f --- /dev/null +++ b/ipss/hssi/inc/ofs_fim_eth_if.sv @@ -0,0 +1,475 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +//----------------------------------------------------------------------------- +// Description +//----------------------------------------------------------------------------- +// +// Platform-independent AXI streams between an Ethernet MAC and an AFU. +// TX is AFU to FIM, RX is FIM to AFU. +// +// All clocks can be assumed to be common, coming from the MAC. +// +//----------------------------------------------------------------------------- + +`ifdef OFS_FIM_ASSERT_OFF + `define OFS_FIM_AXIS_IF_ASSERT_OFF +`endif // OFS_FIM_ASSERT_OFF + +// Interface of Eth RX AXIS channel (MAC -> AFU) +interface ofs_fim_eth_rx_axis_if (); + logic clk; + logic rst_n; // Active-low reset + + import ofs_fim_eth_if_pkg::*; + + // struct declaration contains tvalid, tlast, tdata, and tuser signals of the AXIS channel + t_axis_eth_rx rx; + + // Ready signal + logic tready; + + // AXI-S channel master (MAC side) + modport master ( + input tready, + output clk, + output rst_n, + output rx + ); + + // AXI-S channel slave + modport slave ( + output tready, + input clk, + input rst_n, + input rx + ); + +`ifndef OFS_FIM_AXIS_IF_ASSERT_OFF +// synthesis translate_off + logic enable_assertion; + + initial begin + enable_assertion = 1'b0; + repeat(2) + @(posedge clk); + + wait (rst_n === 1'b0); + wait (rst_n === 1'b1); + + enable_assertion = 1'b1; + end + + assert_tvalid_undef_when_not_in_reset: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (!$isunknown(rx.tvalid))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, rx.tvalid is undefined", $time)); + + assert_tready_undef_when_not_in_reset: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (!$isunknown(tready))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tready is undefined", $time)); + + assert_payload_undef_when_valid_high: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (rx.tvalid) |-> (!$isunknown(rx))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, rx contains undefined bits when tvalid is asserted", $time)); +// synthesis translate_on +`endif // OFS_FIM_AXIS_IF_ASSERT_OFF + +endinterface : ofs_fim_eth_rx_axis_if + + +// Interface of Eth TX AXIS channel (AFU -> MAC) +interface ofs_fim_eth_tx_axis_if (); + logic clk; + logic rst_n; // Active-low reset + + import ofs_fim_eth_if_pkg::*; + + // struct declaration contains tvalid, tlast, tdata, and tuser signals of the AXIS channel + t_axis_eth_tx tx; + + // Ready signal + logic tready; + + // AXI-S channel master + modport master ( + input tready, + input clk, + input rst_n, + output tx + ); + + // AXI-S channel slave (MAC side) + modport slave ( + output tready, + output clk, + output rst_n, + input tx + ); + +`ifndef OFS_FIM_AXIS_IF_ASSERT_OFF +// synthesis translate_off + logic enable_assertion; + + initial begin + enable_assertion = 1'b0; + repeat(2) + @(posedge clk); + + wait (rst_n === 1'b0); + wait (rst_n === 1'b1); + + enable_assertion = 1'b1; + end + + assert_tvalid_undef_when_not_in_reset: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (!$isunknown(tx.tvalid))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tx.tvalid is undefined", $time)); + + assert_tready_undef_when_not_in_reset: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (!$isunknown(tready))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tready is undefined", $time)); + + assert_payload_undef_when_valid_high: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (tx.tvalid) |-> (!$isunknown(tx))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tx contains undefined bits when tvalid is asserted", $time)); +// synthesis translate_on +`endif // OFS_FIM_AXIS_IF_ASSERT_OFF + +endinterface : ofs_fim_eth_tx_axis_if + + +// +// RX Interface of Eth sideband AXIS channel (MAC -> AFU). +// +// There is no tready flow control on this interface. The payload may be +// time-sensitive. +// +interface ofs_fim_eth_sideband_rx_axis_if (); + logic clk; + logic rst_n; // Active-low reset + + import ofs_fim_eth_if_pkg::*; + + // struct declaration contains tvalid, tdata, signals of the AXIS channel + t_axis_eth_sideband_rx sb; + + // AXI-S channel master (MAC side) + modport master ( + output clk, + output rst_n, + output sb + ); + + // AXI-S channel slave + modport slave ( + input clk, + input rst_n, + input sb + ); + +`ifndef OFS_FIM_AXIS_IF_ASSERT_OFF +// synthesis translate_off + logic enable_assertion; + + initial begin + enable_assertion = 1'b0; + repeat(2) + @(posedge clk); + + wait (rst_n === 1'b0); + wait (rst_n === 1'b1); + + enable_assertion = 1'b1; + end + + assert_tvalid_undef_when_not_in_reset: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (!$isunknown(sb.tvalid))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, rx.tvalid is undefined", $time)); + + assert_payload_undef_when_valid_high: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (sb.tvalid) |-> (!$isunknown(sb))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, sb contains undefined bits when tvalid is asserted", $time)); +// synthesis translate_on +`endif // OFS_FIM_AXIS_IF_ASSERT_OFF + +endinterface : ofs_fim_eth_sideband_rx_axis_if + + +// +// Tx Interface of Eth sideband AXIS channel (AFU -> MAC) +// +// There is no tready flow control on this interface. The payload may be +// time-sensitive. +// +interface ofs_fim_eth_sideband_tx_axis_if (); + logic clk; + logic rst_n; // Active-low reset + + import ofs_fim_eth_if_pkg::*; + + // struct declaration contains tvalid, tdata, signals of the AXIS channel + t_axis_eth_sideband_tx sb; + + // AXI-S channel master + modport master ( + input clk, + input rst_n, + output sb + ); + + // AXI-S channel slave (MAC side) + modport slave ( + output clk, + output rst_n, + input sb + ); + +`ifndef OFS_FIM_AXIS_IF_ASSERT_OFF +// synthesis translate_off + logic enable_assertion; + + initial begin + enable_assertion = 1'b0; + repeat(2) + @(posedge clk); + + wait (rst_n === 1'b0); + wait (rst_n === 1'b1); + + enable_assertion = 1'b1; + end + + assert_tvalid_undef_when_not_in_reset: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (!$isunknown(sb.tvalid))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, rx.tvalid is undefined", $time)); + + assert_payload_undef_when_valid_high: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (sb.tvalid) |-> (!$isunknown(sb))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, sb contains undefined bits when tvalid is asserted", $time)); +// synthesis translate_on +`endif // OFS_FIM_AXIS_IF_ASSERT_OFF + +endinterface : ofs_fim_eth_sideband_tx_axis_if + +//----------------HSSI SS related--------- + +// Interface of HSSI SS RX AXIS channel (HSSI SS -> HE-HSSI) +interface ofs_fim_hssi_ss_rx_axis_if (); + logic clk; + logic rst_n; // Active-low reset + + import ofs_fim_eth_if_pkg::*; + + // struct declaration contains tvalid, tlast, tdata, and tuser signals of the AXIS channel + t_axis_hssi_ss_rx rx; + + // AXI-S channel SS side + modport mac ( + output clk, + output rst_n, + output rx + ); + + // AXI-S channel HE side + modport client ( + input clk, + input rst_n, + input rx + ); + +`ifndef OFS_FIM_AXIS_IF_ASSERT_OFF +// synthesis translate_off + logic enable_assertion; + + initial begin + enable_assertion = 1'b0; + repeat(2) + @(posedge clk); + + wait (rst_n === 1'b0); + wait (rst_n === 1'b1); + + enable_assertion = 1'b1; + end + + assert_tvalid_undef_when_not_in_reset: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (!$isunknown(rx.tvalid))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, rx.tvalid is undefined", $time)); + + assert_payload_undef_when_valid_high: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (rx.tvalid) |-> (!$isunknown(rx))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, rx contains undefined bits when tvalid is asserted", $time)); +// synthesis translate_on +`endif // OFS_FIM_AXIS_IF_ASSERT_OFF + +endinterface : ofs_fim_hssi_ss_rx_axis_if + + +// Interface of HSSI SS TX AXIS channel (HE-HSSI-> HSSI SS) +interface ofs_fim_hssi_ss_tx_axis_if (); + logic clk; + logic rst_n; // Active-low reset + + import ofs_fim_eth_if_pkg::*; + + // struct declaration contains tvalid, tlast, tdata, and tuser signals of the AXIS channel + t_axis_hssi_ss_tx tx; + + // Ready signal + logic tready; + + // AXI-S channel HE side + modport client ( + input tready, + input clk, + input rst_n, + output tx + ); + + // AXI-S channel SS side + modport mac ( + output tready, + output clk, + output rst_n, + input tx + ); + +`ifndef OFS_FIM_AXIS_IF_ASSERT_OFF +// synthesis translate_off + logic enable_assertion; + + initial begin + enable_assertion = 1'b0; + repeat(2) + @(posedge clk); + + wait (rst_n === 1'b0); + wait (rst_n === 1'b1); + + enable_assertion = 1'b1; + end + + assert_tvalid_undef_when_not_in_reset: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (!$isunknown(tx.tvalid))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tx.tvalid is undefined", $time)); + + assert_tready_undef_when_not_in_reset: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (!$isunknown(tready))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tready is undefined", $time)); + + assert_payload_undef_when_valid_high: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (tx.tvalid) |-> (!$isunknown(tx))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tx contains undefined bits when tvalid is asserted", $time)); +// synthesis translate_on +`endif // OFS_FIM_AXIS_IF_ASSERT_OFF + +endinterface : ofs_fim_hssi_ss_tx_axis_if + +// Serial interface for HSSI SS +interface ofs_fim_hssi_serial_if #( + parameter NUM_LANES = 1 +); + logic [NUM_LANES-1:0] tx_p; + // logic [NUM_LANES-1:0] tx_n; + logic [NUM_LANES-1:0] rx_p; + // logic [NUM_LANES-1:0] rx_n; + + // AXI-S channel master + modport qsfp ( + output tx_p, + // output tx_n, + input rx_p + // input rx_n + ); +endinterface : ofs_fim_hssi_serial_if + +// Flow Control interface for HSSI SS +interface ofs_fim_hssi_fc_if (); + logic tx_pause; + logic [7:0] tx_pfc; + logic rx_pause; + logic [7:0] rx_pfc; + + // Connected to HSSI SS/MAC + modport mac ( + input tx_pause, + input tx_pfc, + output rx_pause, + output rx_pfc + ); + // Connected AFU/Client + modport client ( + output tx_pause, + output tx_pfc, + input rx_pause, + input rx_pfc + ); +endinterface : ofs_fim_hssi_fc_if + +//----------------PTP & TOD related--------- + +// TOD interface for HSSI SS +interface ofs_fim_hssi_ptp_tx_tod_if (); + logic tvalid; + logic [95:0] tdata; + + // Connected to HSSI SS/MAC + modport mac ( + input tvalid, + input tdata + ); + // Connected AFU/Client + modport client ( + output tvalid, + output tdata + ); +endinterface : ofs_fim_hssi_ptp_tx_tod_if + +interface ofs_fim_hssi_ptp_rx_tod_if (); + logic tvalid; + logic [95:0] tdata; + + // Connected to HSSI SS/MAC + modport mac ( + input tvalid, + input tdata + ); + // Connected AFU/Client + modport client ( + output tvalid, + output tdata + ); +endinterface : ofs_fim_hssi_ptp_rx_tod_if + +// TS interface for HSSI SS +interface ofs_fim_hssi_ptp_tx_egrts_if (); + logic tvalid; + logic [103:0] tdata; + + // Connected to HSSI SS/MAC + modport mac ( + output tvalid, + output tdata + ); + // Connected AFU/Client + modport client ( + input tvalid, + input tdata + ); +endinterface : ofs_fim_hssi_ptp_tx_egrts_if + +interface ofs_fim_hssi_ptp_rx_ingrts_if (); + logic tvalid; + logic [95:0] tdata; + + // Connected to HSSI SS/MAC + modport mac ( + output tvalid, + output tdata + ); + // Connected AFU/Client + modport client ( + input tvalid, + input tdata + ); +endinterface : ofs_fim_hssi_ptp_rx_ingrts_if diff --git a/ipss/hssi/inc/ofs_fim_eth_if_pkg.sv b/ipss/hssi/inc/ofs_fim_eth_if_pkg.sv new file mode 100755 index 0000000..fed2904 --- /dev/null +++ b/ipss/hssi/inc/ofs_fim_eth_if_pkg.sv @@ -0,0 +1,128 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// This package defines the following interfaces/channels in CoreFIM +// 1. Platform-independent Ethernet data streams +// 2. Platform-independent Ethernet sideband streams +// +// The interface is derived from platform-specific configuration in +// ofs_fim_eth_plat_if_pkg. +// +//---------------------------------------------------------------------------- + +package ofs_fim_eth_if_pkg; + +localparam MAX_NUM_ETH_CHANNELS = ofs_fim_eth_plat_if_pkg::MAX_NUM_ETH_CHANNELS; +localparam NUM_ETH_CHANNELS = ofs_fim_eth_plat_if_pkg::NUM_ETH_CHANNELS; +localparam NUM_LANES = ofs_fim_eth_plat_if_pkg::NUM_LANES; + +localparam ETH_PACKET_WIDTH = ofs_fim_eth_plat_if_pkg::ETH_PACKET_WIDTH; +localparam ETH_TKEEP_WIDTH = ETH_PACKET_WIDTH/8; + +localparam ETH_RX_ERROR_WIDTH = ofs_fim_eth_plat_if_pkg::ETH_RX_ERROR_WIDTH; +localparam ETH_TX_ERROR_WIDTH = ofs_fim_eth_plat_if_pkg::ETH_TX_ERROR_WIDTH; + +// Clocks exported by the MAC for use by the AFU. The primary "clk" is +// guaranteed. Others are platform-specific. +typedef ofs_fim_eth_plat_if_pkg::t_eth_clocks t_axis_eth_clocks; + +typedef ofs_fim_eth_plat_if_pkg::t_axis_eth_rx_tuser t_axis_eth_rx_tuser; +typedef ofs_fim_eth_plat_if_pkg::t_axis_eth_tx_tuser t_axis_eth_tx_tuser; + +typedef ofs_fim_eth_plat_if_pkg::t_axis_hssi_ss_rx_tuser t_axis_hssi_ss_rx_tuser; +typedef ofs_fim_eth_plat_if_pkg::t_axis_hssi_ss_tx_tuser t_axis_hssi_ss_tx_tuser; + +// AXIS RX channel (MAC -> AFU) +typedef struct packed { + logic tvalid; + logic tlast; + logic [ETH_PACKET_WIDTH-1:0] tdata; + logic [ETH_TKEEP_WIDTH-1 :0] tkeep; + t_axis_eth_rx_tuser tuser; +} t_axis_eth_rx; +localparam AXIS_ETH_RX_WIDTH = $bits(t_axis_eth_rx); + +// AXIS TX channel (AFU -> MAC) +typedef struct packed { + logic tvalid; + logic tlast; + logic [ETH_PACKET_WIDTH-1:0] tdata; + logic [ETH_TKEEP_WIDTH-1 :0] tkeep; + t_axis_eth_tx_tuser tuser; +} t_axis_eth_tx; +localparam AXIS_ETH_TX_WIDTH = $bits(t_axis_eth_tx); + +// AXIS sideband RX channel (MAC -> AFU) +typedef ofs_fim_eth_plat_if_pkg::t_eth_sideband_from_mac t_eth_sideband_from_mac; +localparam ETH_SIDEBAND_RX_PACKET_WIDTH = $bits(t_eth_sideband_from_mac); + +typedef struct packed { + logic tvalid; + t_eth_sideband_from_mac tdata; +} t_axis_eth_sideband_rx; + +// AXIS sideband TX channel (AFU -> MAC) +typedef ofs_fim_eth_plat_if_pkg::t_eth_sideband_to_mac t_eth_sideband_to_mac; +localparam ETH_SIDEBAND_TX_PACKET_WIDTH = $bits(t_eth_sideband_to_mac); + +typedef struct packed { + logic tvalid; + t_eth_sideband_to_mac tdata; +} t_axis_eth_sideband_tx; + + +// AXIS RX channel (HSSI SS -> Client) +typedef struct packed { + logic tvalid; + logic tlast; + logic [ETH_PACKET_WIDTH-1:0] tdata; + logic [ETH_TKEEP_WIDTH-1 :0] tkeep; + t_axis_hssi_ss_rx_tuser tuser; +} t_axis_hssi_ss_rx; +localparam AXIS_HSSI_SS_RX_WIDTH = $bits(t_axis_hssi_ss_rx); + +// AXIS TX channel (Client -> HSSI SS) +typedef struct packed { + logic tvalid; + logic tlast; + logic [ETH_PACKET_WIDTH-1:0] tdata; + logic [ETH_TKEEP_WIDTH-1 :0] tkeep; + t_axis_hssi_ss_tx_tuser tuser; +} t_axis_hssi_ss_tx; +localparam AXIS_HSSI_SS_TX_WIDTH = $bits(t_axis_hssi_ss_tx); + + +//---------------------------------------------- +// Debugging functions +//---------------------------------------------- + +function automatic string func_axis_eth_rx_to_string ( + input t_axis_eth_rx rx +); + return $sformatf("tlast %x tuser 0x%x tkeep 0x%x tdata 0x%x", + rx.tlast, rx.tuser, rx.tkeep, rx.tdata); +endfunction + +function automatic string func_axis_eth_tx_to_string ( + input t_axis_eth_tx tx +); + return $sformatf("tlast %x tuser 0x%x tkeep 0x%x tdata 0x%x", + tx.tlast, tx.tuser, tx.tkeep, tx.tdata); +endfunction + +function automatic string func_axis_eth_sb_rx_to_string ( + input t_axis_eth_sideband_rx rx +); + return $sformatf("tdata 0x%x", rx.tdata); +endfunction + +function automatic string func_axis_eth_sb_tx_to_string ( + input t_axis_eth_sideband_tx tx +); + return $sformatf("tdata 0x%x", tx.tdata); +endfunction + +endpackage diff --git a/ipss/hssi/lib/bridge/acl_scfifo_wrapped.sv b/ipss/hssi/lib/bridge/acl_scfifo_wrapped.sv new file mode 100644 index 0000000..86e923f --- /dev/null +++ b/ipss/hssi/lib/bridge/acl_scfifo_wrapped.sv @@ -0,0 +1,214 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +/////////////////////////////////////////////////////////////////////////////////////// +// // +// ACL SCFIFO WRAPPED // +// // +// DESCRIPTION // +// =========== // +// This is a wrapper around the scfifo component and behaves in // +// the exact same way when the parameter enable_ecc is set to "FALSE". The // +// module has the added (soft) ECC feature. // +// // +// The module has the exact same interface except for // +// * One addtional parameter: // +// - "enable_ecc": accepts "TRUE" or "FALSE". The default is "FALSE" // +// * One additional output port: // +// - "ecc_err_status": this is a 2-bit status signal that behaves as follows: // +// ---------------------------------------------------------------- // +// Status Meaning // +// ---------------------------------------------------------------- // +// 00 No error detected // +// 10 Error detected and corrected (single bit error) // +// x1 Error detected but uncorrectable (double bit error) // +// ---------------------------------------------------------------- // +// // +// Required files // +// ============== // +// acl_ecc_encoder.sv // +// acl_ecc_decoder.sv // +// // +// Usage // +// ===== // +// Only if using A10, this module can be used with the "enable_ecc" parameter // +// set to "TRUE" to enable ECC. When ECC is disabled, the wrapper can be used // +// with any family in almost the exact same way as the scfifo IP. // +// // +/////////////////////////////////////////////////////////////////////////////////////// + +`default_nettype none +//`include "acl_ecc.svh" + +module acl_scfifo_wrapped #( + // GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1, //Specifies the width of the data and q ports + parameter lpm_widthu = 1, //Specifies the width of the usedw port + parameter lpm_numwords = 2, //Specifies the depths of the FIFO you require. The value must be at least 4. The value assigned must comply to the following equation: 2^LPM_WIDTHU + parameter lpm_showahead = "OFF", //Specifies whether the FIFO is in normal mode (OFF) or show-ahead mode (ON). + parameter lpm_type = "scfifo", //Identifies the library of parameterized modules (LPM) entity name. The values are SCFIFO and DCFIFO. + parameter lpm_hint = "USE_EAB=ON", + parameter intended_device_family = "Arria 10", + parameter underflow_checking = "ON", + parameter overflow_checking = "ON", + parameter allow_rwcycle_when_full = "OFF", + parameter use_eab = "ON", //Specifies whether or not the FIFO IP core is constructed using the RAM blocks. The values are ON or OFF. + parameter add_ram_output_register = "OFF", //Specifies whether to register the q output of the internal scfifo before going into the decoder. + parameter almost_full_value = 0, + parameter almost_empty_value = 0, + parameter maximum_depth = 0, + parameter enable_ecc = "FALSE" +) +( + // INPUT PORT DECLARATION + input wire [lpm_width-1:0] data, //Holds the data to be written in the FIFO IP core when the wrreq signal is asserted + input wire clock, + input wire wrreq, //Assert this signal to request for a write operation + input wire rdreq, //Assert this signal to request for a read operation. + input wire aclr, + input wire sclr, + + // OUTPUT PORT DECLARATION + output logic [lpm_width-1:0] q, //Shows the data read from the read request operation + output logic [lpm_widthu-1:0] usedw, //Asserted when the usedw signal is greater than or equal to the almost_full_value parameter. + output logic full, //When asserted, the FIFO IP core is considered full. Do not perform write request operation when the FIFO IP core is full. + output logic empty, //When asserted, the FIFO IP core is considered empty. Do not perform read request operation when the FIFO IP core is empty + output logic almost_full, //Asserted when the usedw signal is greater than or equal to the almost_full_value parameter. + output logic almost_empty, //Asserted when the usedw signal is less than the almost_empty_value parameter. + output logic [1:0] ecc_err_status //10 = error detected and corrected (memory in not updated), 01 = error detected but uncorrectable +); + + // use localparams to calcultate internal parameters + localparam int MAX_ECC_WIDTH = 32; //this value should be ECC_GROUP_SIZE and can be swept to tradeoff fmax vs memory overhead. Do not set this value larger than 64 due to altecc implementation + //localparam int SCFIFO_WIDTH = (enable_ecc == "TRUE") ? getEncodedBitsEccGroup(lpm_width, MAX_ECC_WIDTH) : lpm_width; // width of codewords + localparam int SCFIFO_WIDTH = lpm_width; // width of codewords + + // signals for making internal connections + logic [SCFIFO_WIDTH-1:0] codeword_wr; // data to write into the memory, including any ECC bits + logic [SCFIFO_WIDTH-1:0] codeword_rd; // data read out of the memory, including any ECC bits + + logic err_fatal; // ecc status signal for detected uncorrected error + logic err_corrected; // ecc status signal for detected corrected error + + localparam int ERR_CORRECTED_PULSE_EXTENSION_WIDTH = 3; // amount of pulse stretching for the "error corrected" signal. + + genvar i; + generate + if (enable_ecc == "TRUE") begin : GEN_ECC_ENABLED + logic err_corrected_int; + logic err_corrected_pulse_extended; + + logic err_fatal_int; + logic err_fatal_latched; + + logic [ERR_CORRECTED_PULSE_EXTENSION_WIDTH-1:0] d; + + // instantiate the ECC encoder for port a + acl_ecc_encoder #( + .DATA_WIDTH (lpm_width), + .ECC_GROUP_SIZE (MAX_ECC_WIDTH), + .INPUT_PIPELINE_STAGES (0), + .OUTPUT_PIPELINE_STAGES (0) + ) altecc_encoder_inst_a ( + .clock (clock), + .clock_enable (1'b1), + .i_data (data), + .o_encoded (codeword_wr) + ); + + // instantiate the ECC decoder for port a + acl_ecc_decoder #( + .DATA_WIDTH (lpm_width), + .ECC_GROUP_SIZE (MAX_ECC_WIDTH), + .INPUT_PIPELINE_STAGES (0), + .OUTPUT_PIPELINE_STAGES (0), + .STATUS_PIPELINE_STAGES (0) + ) altecc_decoder_inst_a ( + .clock (clock), + .clock_enable (1'b1), + .i_encoded (codeword_rd), + .o_single_error_corrected (err_corrected_int), //Flag signal to reflect the status of data received. Denotes single-bit error found and corrected. You can use the data because it has already been corrected. + .o_double_error_detected (err_fatal_int), // Flag signal to reflect the status of data received. Denotes double-bit error found, but not corrected. You must not use the data if this signal is asserted. + .o_data (q) + ); + + always_ff @(posedge clock or posedge aclr) begin + + if (aclr) begin + err_fatal_latched <= 1'b0; + err_corrected_pulse_extended <= 1'b0; + d <= 'b0; + + end else begin + + if (!empty) begin + err_fatal_latched <= err_fatal_latched | err_fatal_int; + + d[0] <= err_corrected_int; + for (int i = 1; i < ERR_CORRECTED_PULSE_EXTENSION_WIDTH; i++) begin + d[i] <= d[i-1]; + end + + err_corrected_pulse_extended <= ( | d) | err_corrected_int; + end + + if (sclr) begin + err_fatal_latched <= 1'b0; + err_corrected_pulse_extended <= 1'b0; + d <= 'b0; + end + end + end + + assign err_fatal = err_fatal_latched; + assign err_corrected = err_corrected_pulse_extended; + assign ecc_err_status = {err_corrected,err_fatal}; + + end else begin : GEN_ECC_DISABLED // soft_ecc is false + + assign err_corrected = 1'b0; + assign err_fatal = 1'b0; + assign ecc_err_status = {err_corrected,err_fatal}; + assign codeword_wr = data; + assign q = codeword_rd; + + end + + endgenerate + + scfifo #( + .add_ram_output_register (add_ram_output_register), + .lpm_numwords (lpm_numwords), + .lpm_showahead (lpm_showahead), + .lpm_type (lpm_type), + .lpm_hint (lpm_hint), + .lpm_width (SCFIFO_WIDTH), + .lpm_widthu (lpm_widthu), + .intended_device_family (intended_device_family), + .overflow_checking (overflow_checking), + .underflow_checking (underflow_checking), + .allow_rwcycle_when_full (allow_rwcycle_when_full), + .use_eab (use_eab), + .almost_full_value (almost_full_value), + .almost_empty_value (almost_empty_value), + .maximum_depth (maximum_depth), + .enable_ecc ("FALSE") + ) scfifo_inst ( + .data (codeword_wr), + .clock (clock), + .wrreq (wrreq), + .rdreq (rdreq), + .aclr (aclr), + .sclr (sclr), + .q (codeword_rd), + .usedw (usedw), + .full (full), + .empty (empty), + .almost_full (almost_full), + .almost_empty (almost_empty), + .eccstatus () + ); + +endmodule // acl_scfifo_wrapped + +`default_nettype wire diff --git a/ipss/hssi/lib/bridge/fast_bridge.v b/ipss/hssi/lib/bridge/fast_bridge.v new file mode 100644 index 0000000..281a990 --- /dev/null +++ b/ipss/hssi/lib/bridge/fast_bridge.v @@ -0,0 +1,97 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + + module fast_bridge +#( + parameter DATA_WIDTH = 32, // bit width of the AVMM data interface + parameter EXTERNAL_PIPE_DEPTH = 1, // Specifies how many feed-forward (unstallable) pipe stages are placed outside this block. + parameter INTERNAL_PIPE_DEPTH = 1, // Specifies how many feed-forward (unstallable) pipe stages to be placed inside this block. + + parameter FIFO_DEPTH = 32 + +) +( + input clk, // clock input + input reset, // reset input + + output s0_ready, + input [DATA_WIDTH-1:0] s0_data, + input s0_valid, + + input m0_ready, + output [DATA_WIDTH-1:0] m0_data, + output m0_valid +); + + localparam REQ_FIFO_ALMOST_FULL_THRES = 2*INTERNAL_PIPE_DEPTH + 2*EXTERNAL_PIPE_DEPTH + 2; + + wire req_almost_full; + wire [DATA_WIDTH-1:0] req_data_in; + wire req_valid_in; + + reg req_valid_out; + wire req_fifo_pop; + wire req_fifo_empty; + + +pipe_hssi_ch #( + .TDATA_WIDTH ( DATA_WIDTH ), + .PL_DEPTH ( INTERNAL_PIPE_DEPTH) +) pipe_inst ( + .clk (clk), + .rst_n (~reset), + + .s_ready (s0_ready), + .s_data (s0_data), + .s_valid (s0_valid), + + .m_ready (~req_almost_full), + .m_data (req_data_in), + .m_valid (req_valid_in) +); + + + acl_scfifo_wrapped #( + .add_ram_output_register ( "ON"), + .intended_device_family ("Stratix 10"), + .lpm_numwords (FIFO_DEPTH), + .lpm_showahead ( "OFF"), + .lpm_type ( "scfifo"), + .lpm_width (DATA_WIDTH), + .lpm_widthu ($clog2(FIFO_DEPTH)), + .overflow_checking ( "OFF"), + .underflow_checking ( "ON"), + .use_eab ( "ON"), + .almost_full_value(FIFO_DEPTH - REQ_FIFO_ALMOST_FULL_THRES), + //.connect_clr_to_scfifo (1'b1), + .enable_ecc ("FALSE") + ) fast_bridge_req_fifo ( + .clock (clk), + .data (req_data_in), + .wrreq (req_valid_in & s0_ready), + .rdreq (req_fifo_pop), + .usedw (), + .empty (req_fifo_empty), + .full (), + .q (m0_data), + .almost_empty (), + .almost_full (req_almost_full), + .sclr (reset), + .aclr (reset), + .ecc_err_status() + ); + +always @(posedge clk) begin + if (reset) + req_valid_out <= 1'b0; + else if (m0_ready) + req_valid_out <= req_fifo_pop; + else + req_valid_out <= req_valid_out; +end + +assign req_fifo_pop = ~req_fifo_empty & m0_ready; +assign m0_valid = req_valid_out; + + +endmodule diff --git a/ipss/hssi/lib/bridge/ofs_fim_eth_afu_avst_to_fim_axis_bridge.sv b/ipss/hssi/lib/bridge/ofs_fim_eth_afu_avst_to_fim_axis_bridge.sv new file mode 100755 index 0000000..14b5b19 --- /dev/null +++ b/ipss/hssi/lib/bridge/ofs_fim_eth_afu_avst_to_fim_axis_bridge.sv @@ -0,0 +1,68 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +//----------------------------------------------------------------------------- +// Description +//----------------------------------------------------------------------------- +// +// FIM AVST <-> AFU AXIS bridge +// +//----------------------------------------------------------------------------- + +module ofs_fim_eth_afu_avst_to_fim_axis_bridge ( + // FIM-side AVST interfaces + ofs_fim_eth_tx_avst_if.slave avst_tx_st, + ofs_fim_eth_rx_avst_if.master avst_rx_st, + + // AFU-side AXI-S interfaces + ofs_fim_eth_tx_axis_if.master axi_tx_st, + ofs_fim_eth_rx_axis_if.slave axi_rx_st +); + + logic is_rx_sop; + + // **************************************************** + // *-------------- FIM -> AFU Rx Bridge --------------* + // **************************************************** + assign avst_rx_st.clk = axi_rx_st.clk; + assign avst_rx_st.rst_n = axi_rx_st.rst_n; + + always_comb + begin + axi_rx_st.tready = avst_rx_st.ready; + avst_rx_st.rx.valid = axi_rx_st.rx.tvalid; + // AVST data is first Symbol In High Order Bits + avst_rx_st.rx.data = ofs_fim_eth_avst_if_pkg::eth_axi_to_avst_data(axi_rx_st.rx.tdata); + avst_rx_st.rx.sop = axi_rx_st.rx.tvalid & is_rx_sop; + avst_rx_st.rx.eop = axi_rx_st.rx.tvalid & axi_rx_st.rx.tlast; + avst_rx_st.rx.user.error = axi_rx_st.rx.tuser.error; + avst_rx_st.rx.empty = ofs_fim_eth_avst_if_pkg::eth_tkeep_to_empty(axi_rx_st.rx.tkeep); + end + + // Rx SOP always follows a tlast AXI-S flit + always_ff @(posedge axi_rx_st.clk) + begin + if (!axi_rx_st.rst_n) + is_rx_sop <= 1'b1; + else if (axi_rx_st.rx.tvalid && axi_rx_st.tready) + is_rx_sop <= axi_rx_st.rx.tlast; + end + + // **************************************************** + // *-------------- AFU -> FIM Tx Bridge --------------* + // **************************************************** + assign avst_tx_st.clk = axi_tx_st.clk; + assign avst_tx_st.rst_n = axi_tx_st.rst_n; + + always_comb + begin + avst_tx_st.ready = axi_tx_st.tready; + axi_tx_st.tx.tvalid = avst_tx_st.tx.valid; + // AVST data is first Symbol In High Order Bits + axi_tx_st.tx.tdata = ofs_fim_eth_avst_if_pkg::eth_avst_to_axi_data(avst_tx_st.tx.data); + axi_tx_st.tx.tlast = avst_tx_st.tx.eop & avst_tx_st.tx.valid; + axi_tx_st.tx.tuser.error = avst_tx_st.tx.user.error; + axi_tx_st.tx.tkeep = ofs_fim_eth_avst_if_pkg::eth_empty_to_tkeep(avst_tx_st.tx.empty); + end + +endmodule diff --git a/ipss/hssi/lib/bridge/ofs_fim_eth_axis_connect.sv b/ipss/hssi/lib/bridge/ofs_fim_eth_axis_connect.sv new file mode 100755 index 0000000..27f38a5 --- /dev/null +++ b/ipss/hssi/lib/bridge/ofs_fim_eth_axis_connect.sv @@ -0,0 +1,59 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +//----------------------------------------------------------------------------- +// Description +//----------------------------------------------------------------------------- +// +// Wire together two instances of Ethernet AXI-S interfaces. +// +//----------------------------------------------------------------------------- + +module ofs_fim_eth_axis_connect_rx ( + ofs_fim_eth_rx_axis_if.master to_afu, + ofs_fim_eth_rx_axis_if.slave to_fim +); + + assign to_afu.clk = to_fim.clk; + assign to_afu.rst_n = to_fim.rst_n; + assign to_fim.tready = to_afu.tready; + assign to_afu.rx = to_fim.rx; + +endmodule // ofs_fim_eth_axis_connect_rx + + +module ofs_fim_eth_axis_connect_tx ( + ofs_fim_eth_tx_axis_if.slave to_afu, + ofs_fim_eth_tx_axis_if.master to_fim +); + + assign to_afu.clk = to_fim.clk; + assign to_afu.rst_n = to_fim.rst_n; + assign to_afu.tready = to_fim.tready; + assign to_fim.tx = to_afu.tx; + +endmodule // ofs_fim_eth_axis_connect_tx + + +module ofs_fim_eth_axis_connect_sb_rx ( + ofs_fim_eth_sideband_rx_axis_if.master to_afu, + ofs_fim_eth_sideband_rx_axis_if.slave to_fim +); + + assign to_afu.clk = to_fim.clk; + assign to_afu.rst_n = to_fim.rst_n; + assign to_afu.sb = to_fim.sb; + +endmodule // ofs_fim_eth_axis_connect_sb_rx + + +module ofs_fim_eth_axis_connect_sb_tx ( + ofs_fim_eth_sideband_tx_axis_if.slave to_afu, + ofs_fim_eth_sideband_tx_axis_if.master to_fim +); + + assign to_afu.clk = to_fim.clk; + assign to_afu.rst_n = to_fim.rst_n; + assign to_fim.sb = to_afu.sb; + +endmodule // ofs_fim_eth_axis_connect_sb_tx diff --git a/ipss/hssi/lib/bridge/ofs_fim_eth_sb_afu_avst_to_fim_axis_bridge.sv b/ipss/hssi/lib/bridge/ofs_fim_eth_sb_afu_avst_to_fim_axis_bridge.sv new file mode 100755 index 0000000..f5277c0 --- /dev/null +++ b/ipss/hssi/lib/bridge/ofs_fim_eth_sb_afu_avst_to_fim_axis_bridge.sv @@ -0,0 +1,38 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +//----------------------------------------------------------------------------- +// Description +//----------------------------------------------------------------------------- +// +// Sideband FIM AVST <-> AFU AXIS bridge +// +//----------------------------------------------------------------------------- + +module ofs_fim_eth_sb_afu_avst_to_fim_axis_bridge ( + // FIM-side AVST interfaces + ofs_fim_eth_sideband_tx_avst_if.slave avst_tx_st, + ofs_fim_eth_sideband_rx_avst_if.master avst_rx_st, + + // AFU-side AXI-S interfaces + ofs_fim_eth_sideband_tx_axis_if.master axi_tx_st, + ofs_fim_eth_sideband_rx_axis_if.slave axi_rx_st +); + + // **************************************************** + // *-------------- FIM -> AFU Rx Bridge --------------* + // **************************************************** + assign avst_rx_st.clk = axi_rx_st.clk; + assign avst_rx_st.rst_n = axi_rx_st.rst_n; + assign avst_rx_st.sb.valid = axi_rx_st.sb.tvalid; + assign avst_rx_st.sb.data = axi_rx_st.sb.tdata; + + // **************************************************** + // *-------------- AFU -> FIM Tx Bridge --------------* + // **************************************************** + assign avst_tx_st.clk = axi_tx_st.clk; + assign avst_tx_st.rst_n = axi_tx_st.rst_n; + assign axi_tx_st.sb.tvalid = avst_tx_st.sb.valid; + assign axi_tx_st.sb.tdata = avst_tx_st.sb.data; + +endmodule diff --git a/ipss/hssi/lib/pipeline/pr_eth_axis_if_reg.sv b/ipss/hssi/lib/pipeline/pr_eth_axis_if_reg.sv new file mode 100755 index 0000000..44ebdc2 --- /dev/null +++ b/ipss/hssi/lib/pipeline/pr_eth_axis_if_reg.sv @@ -0,0 +1,130 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Green BS PCIE AXI-S interface pipeline registers +// +//----------------------------------------------------------------------------- + +import ofs_fim_eth_if_pkg::ETH_PACKET_WIDTH; +import ofs_fim_eth_if_pkg::ETH_RX_ERROR_WIDTH; +import ofs_fim_eth_if_pkg::ETH_TX_ERROR_WIDTH; + +module pr_eth_axis_if_reg ( + // AXIS Ethernet RX channels + ofs_fim_eth_rx_axis_if.slave s_eth_rx_st, + ofs_fim_eth_rx_axis_if.master m_eth_rx_st, + + // AXIS Ethernet TX channels + ofs_fim_eth_tx_axis_if.slave s_eth_tx_st, + ofs_fim_eth_tx_axis_if.master m_eth_tx_st, + // AXIS Ethernet RX sideband + ofs_fim_eth_sideband_rx_axis_if.slave s_sideband_rx, + ofs_fim_eth_sideband_rx_axis_if.master m_sideband_rx, + // AXIS Ethernet RX sideband + ofs_fim_eth_sideband_tx_axis_if.slave s_sideband_tx, + ofs_fim_eth_sideband_tx_axis_if.master m_sideband_tx +); + + //-------------------- + // RX pipeline + //-------------------- + axis_register #( + .MODE (0), // 0: skid buffer 1: simple buffer 2: bypass + .TREADY_RST_VAL (0), // Keep tready deasserted during reset + .ENABLE_TKEEP (1), + .ENABLE_TLAST (1), + .ENABLE_TID (0), + .ENABLE_TDEST (0), + .ENABLE_TUSER (1), + .TDATA_WIDTH (ETH_PACKET_WIDTH), + .TUSER_WIDTH (ETH_RX_ERROR_WIDTH ) + ) rx_pipeln ( + .clk (s_eth_rx_st.clk), + .rst_n (s_eth_rx_st.rst_n), + // Slave interface + .s_tready (s_eth_rx_st.tready), + .s_tvalid (s_eth_rx_st.rx.tvalid), + .s_tdata (s_eth_rx_st.rx.tdata), + .s_tlast (s_eth_rx_st.rx.tlast), + .s_tkeep (s_eth_rx_st.rx.tkeep), + .s_tuser (s_eth_rx_st.rx.tuser), + // Master interface + .m_tready (m_eth_rx_st.tready), + .m_tvalid (m_eth_rx_st.rx.tvalid), + .m_tdata (m_eth_rx_st.rx.tdata), + .m_tlast (m_eth_rx_st.rx.tlast), + .m_tkeep (m_eth_rx_st.rx.tkeep), + .m_tuser (m_eth_rx_st.rx.tuser) + ); + // Connect Clock and resets + assign m_eth_rx_st.clk = s_eth_rx_st.clk; + assign m_eth_rx_st.rst_n = s_eth_rx_st.rst_n; + + //-------------------- + // TX pipeline + //-------------------- + axis_register #( + .MODE (0), // 0: skid buffer 1: simple buffer 2: bypass + .TREADY_RST_VAL (0), // Keep tready deasserted during reset + .ENABLE_TKEEP (1), + .ENABLE_TLAST (1), + .ENABLE_TID (0), + .ENABLE_TDEST (0), + .ENABLE_TUSER (1), + .TDATA_WIDTH (ETH_PACKET_WIDTH), + .TUSER_WIDTH (ETH_TX_ERROR_WIDTH) + ) tx_pipeln ( + .clk (m_eth_tx_st.clk), + .rst_n (m_eth_tx_st.rst_n), + // Slave interface + .s_tready (s_eth_tx_st.tready), + .s_tvalid (s_eth_tx_st.tx.tvalid), + .s_tdata (s_eth_tx_st.tx.tdata), + .s_tlast (s_eth_tx_st.tx.tlast), + .s_tkeep (s_eth_tx_st.tx.tkeep), + .s_tuser (s_eth_tx_st.tx.tuser), + // Master interface + .m_tready (m_eth_tx_st.tready), + .m_tvalid (m_eth_tx_st.tx.tvalid), + .m_tdata (m_eth_tx_st.tx.tdata), + .m_tlast (m_eth_tx_st.tx.tlast), + .m_tkeep (m_eth_tx_st.tx.tkeep), + .m_tuser (m_eth_tx_st.tx.tuser) + ); + // Connect Clock and resets + assign s_eth_tx_st.clk = m_eth_tx_st.clk; + assign s_eth_tx_st.rst_n = m_eth_tx_st.rst_n; + + //-------------------- + // Ethernet Sideband pipeline + //-------------------- + + always @(posedge s_sideband_rx.clk) begin + if (~s_sideband_rx.rst_n) begin + m_sideband_rx.sb.tvalid <= 1'b0; + end + else begin + m_sideband_rx.sb <= s_sideband_rx.sb; + end + end + + always @(posedge m_sideband_tx.clk) begin + if (~m_sideband_tx.rst_n) begin + m_sideband_tx.sb.tvalid <= 1'b0; + end + else begin + m_sideband_tx.sb <= s_sideband_tx.sb; + end + end + // Connect Clock and resets + assign m_sideband_rx.clk = s_sideband_rx.clk; + assign m_sideband_rx.rst_n = s_sideband_rx.rst_n; + + assign s_sideband_tx.clk = m_sideband_tx.clk; + assign s_sideband_tx.rst_n = m_sideband_tx.rst_n; + +endmodule + diff --git a/ipss/hssi/s10/altera_eth_10g_mac_base_r_wrap.sv b/ipss/hssi/s10/altera_eth_10g_mac_base_r_wrap.sv new file mode 100755 index 0000000..a55c519 --- /dev/null +++ b/ipss/hssi/s10/altera_eth_10g_mac_base_r_wrap.sv @@ -0,0 +1,315 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +`timescale 1 ps / 1 ps +import ofs_fim_eth_if_pkg::*; +import hssi_csr_pkg::*; + +module altera_eth_10g_mac_base_r_wrap ( + // clock and reset + input wire csr_clk, + input wire csr_rst_n, + input wire tx_clk_312, + input wire tx_clk_156, + input wire sync_tx_rst_n, + input wire rx_clk_312, + input wire rx_clk_156, + input wire sync_rx_rst_n, + + input wire ref_clk_clk, + + //avlon_st tx interface + input wire avalon_st_tx_startofpacket, + input wire avalon_st_tx_endofpacket, + input wire avalon_st_tx_valid, + input wire [31:0] avalon_st_tx_data, + input wire [1:0] avalon_st_tx_empty, + input wire avalon_st_tx_error, + output wire avalon_st_tx_ready, + + // avalon_st rx interface + output wire avalon_st_rx_startofpacket, + output wire avalon_st_rx_endofpacket, + output wire avalon_st_rx_valid, + output wire [31:0] avalon_st_rx_data, + output wire [1:0] avalon_st_rx_empty, + input wire avalon_st_rx_ready, + output wire [5:0] avalon_st_rx_error, + + // additional st interface + input wire [1:0] avalon_st_pause_data, + input wire [15:0] avalon_st_tx_pfc_gen_data, // avalon_st_tx_pfc_gen_data.export + output wire [7:0] avalon_st_rx_pfc_pause_data, + output wire avalon_st_txstatus_valid, + output wire [39:0] avalon_st_txstatus_data, + output wire [6:0] avalon_st_txstatus_error, + + output wire avalon_st_rxstatus_valid, + output wire [6:0] avalon_st_rxstatus_error, + output wire [39:0] avalon_st_rxstatus_data, + + output wire [1:0] link_fault_status_xgmii_rx_data, + + // reset controller + output wire tx_ready_export, + output wire rx_ready_export, + output wire block_lock, + input wire atx_pll_locked, + + output wire tx_serial_data, + input wire rx_serial_data, + + input wire mac_csr_read, + input wire mac_csr_write, + output wire [31:0] mac_csr_readdata, + input wire [31:0] mac_csr_writedata, + output wire mac_csr_waitrequest, + input wire [9:0] mac_csr_address, + + input wire phy_csr_read, + input wire phy_csr_write, + output wire [31:0] phy_csr_readdata, + input wire [31:0] phy_csr_writedata, + output wire phy_csr_waitrequest, + input wire [10:0] phy_csr_address, + + input wire tx_serial_clk, + input wire final_channel_rst, + input wire final_reconfig_rst, + output hssi_stats_struct_t hssi_stats + +); + + +wire [7:0] xgmii_tx_control; +wire [63:0] xgmii_tx_data; +wire [71:0] xgmii_tx; + +wire [7:0] xgmii_rx_control; +wire [63:0] xgmii_rx_data; +wire [71:0] xgmii_rx; + +reg [71:0] xgmii_tx_reg; +reg [71:0] xgmii_rx_reg; + +//reset controller +wire tx_analogreset; +wire tx_digitalreset; +wire rx_analogreset; +wire rx_digitalreset; +wire rx_analogreset_stat; +wire rx_digitalreset_stat; +wire tx_analogreset_stat; +wire tx_digitalreset_stat; +wire tx_transfer_ready; +wire rx_transfer_ready; +wire tx_fifo_ready; +wire rx_fifo_ready; +wire rx_digitalreset_timeout; +wire tx_digitalreset_timeout; +wire rx_is_lockedtoref; +wire rx_is_lockedtodata; +wire tx_cal_busy; +wire rx_cal_busy; + +wire tx_clkout; +wire rx_clkout; + + + + // Map HSSI stats signals to structs + assign hssi_stats.rx_ready = rx_ready_export; + assign hssi_stats.tx_ready = tx_ready_export; + assign hssi_stats.rx_is_lockedtoref = rx_is_lockedtoref ; + assign hssi_stats.rx_is_lockedtodata = rx_is_lockedtodata; + assign hssi_stats.rx_cal_busy = rx_cal_busy; + assign hssi_stats.tx_cal_busy = tx_cal_busy; + assign hssi_stats.rx_transfer_ready = rx_transfer_ready; + assign hssi_stats.tx_transfer_ready = tx_transfer_ready; + assign hssi_stats.rx_fifo_ready = rx_fifo_ready; + assign hssi_stats.tx_fifo_ready = tx_fifo_ready; + assign hssi_stats.rx_digitalreset_timeout = rx_digitalreset_timeout; + assign hssi_stats.tx_digitalreset_timeout = tx_digitalreset_timeout; + assign hssi_stats.rx_digitalreset_stat = rx_digitalreset_stat; + assign hssi_stats.rx_analogreset_stat = rx_analogreset_stat; + assign hssi_stats.tx_digitalreset_stat = tx_digitalreset_stat; + assign hssi_stats.tx_analogreset_stat = tx_analogreset_stat; + + + +assign xgmii_tx_data = { + xgmii_tx_reg[70:63], + xgmii_tx_reg[61:54], + xgmii_tx_reg[52:45], + xgmii_tx_reg[43:36], + xgmii_tx_reg[34:27], + xgmii_tx_reg[25:18], + xgmii_tx_reg[16:9], + xgmii_tx_reg[7:0] +}; + +assign xgmii_tx_control = { + xgmii_tx_reg[71], + xgmii_tx_reg[62], + xgmii_tx_reg[53], + xgmii_tx_reg[44], + xgmii_tx_reg[35], + xgmii_tx_reg[26], + xgmii_tx_reg[17], + xgmii_tx_reg[8] +}; + +assign xgmii_rx = { + xgmii_rx_control[7], xgmii_rx_data[63:56], + xgmii_rx_control[6], xgmii_rx_data[55:48], + xgmii_rx_control[5], xgmii_rx_data[47:40], + xgmii_rx_control[4], xgmii_rx_data[39:32], + xgmii_rx_control[3], xgmii_rx_data[31:24], + xgmii_rx_control[2], xgmii_rx_data[23:16], + xgmii_rx_control[1], xgmii_rx_data[15:8], + xgmii_rx_control[0], xgmii_rx_data[7:0]}; + +always @(posedge tx_clk_156) +begin + xgmii_tx_reg <= xgmii_tx; +end + +always @(posedge rx_clk_156) +begin + xgmii_rx_reg <= xgmii_rx; +end + +altera_eth_10g_mac mac_inst ( + + .csr_read (mac_csr_read), + .csr_write (mac_csr_write), + .csr_writedata (mac_csr_writedata), + .csr_readdata (mac_csr_readdata), + .csr_waitrequest (mac_csr_waitrequest), + .csr_address (mac_csr_address), + .csr_clk (csr_clk), + .csr_rst_n (~final_reconfig_rst), + .tx_rst_n (sync_tx_rst_n), + .rx_rst_n (sync_rx_rst_n), + .avalon_st_tx_startofpacket (avalon_st_tx_startofpacket), + .avalon_st_tx_endofpacket (avalon_st_tx_endofpacket), + .avalon_st_tx_valid (avalon_st_tx_valid), + .avalon_st_tx_data (avalon_st_tx_data), + .avalon_st_tx_empty (avalon_st_tx_empty), + .avalon_st_tx_error (avalon_st_tx_error), + .avalon_st_tx_ready (avalon_st_tx_ready), + .avalon_st_pause_data (avalon_st_pause_data), + .avalon_st_tx_pfc_gen_data (avalon_st_tx_pfc_gen_data ), + .avalon_st_rx_pfc_pause_data(avalon_st_rx_pfc_pause_data), + .avalon_st_txstatus_valid (avalon_st_txstatus_valid), + .avalon_st_txstatus_data (avalon_st_txstatus_data), + .avalon_st_txstatus_error (avalon_st_txstatus_error), + .link_fault_status_xgmii_rx_data (link_fault_status_xgmii_rx_data), + .avalon_st_rx_data (avalon_st_rx_data), + .avalon_st_rx_startofpacket (avalon_st_rx_startofpacket), + .avalon_st_rx_valid (avalon_st_rx_valid), + .avalon_st_rx_empty (avalon_st_rx_empty), + .avalon_st_rx_error (avalon_st_rx_error), + .avalon_st_rx_ready (avalon_st_rx_ready), + .avalon_st_rx_endofpacket (avalon_st_rx_endofpacket), + .avalon_st_rxstatus_valid (avalon_st_rxstatus_valid), + .avalon_st_rxstatus_data (avalon_st_rxstatus_data), + .avalon_st_rxstatus_error (avalon_st_rxstatus_error), + + .rx_156_25_clk (rx_clk_156), + .rx_312_5_clk (rx_clk_312), + .tx_156_25_clk (tx_clk_156), + .tx_312_5_clk (tx_clk_312), + + .xgmii_rx (xgmii_rx_reg), + .xgmii_tx (xgmii_tx) + +); + + +altera_eth_10gbaser_phy baser_inst ( + + .tx_analogreset (tx_analogreset), + .tx_digitalreset (tx_digitalreset), + .rx_analogreset (rx_analogreset), + .rx_digitalreset (rx_digitalreset), + .tx_transfer_ready (tx_transfer_ready), + .rx_transfer_ready (rx_transfer_ready), + .tx_fifo_ready (tx_fifo_ready), + .rx_fifo_ready (rx_fifo_ready), + .tx_cal_busy (tx_cal_busy), + .rx_cal_busy (rx_cal_busy), + .tx_serial_clk0 (tx_serial_clk), + .rx_cdr_refclk0 (ref_clk_clk), + .tx_serial_data (tx_serial_data), + .rx_serial_data (rx_serial_data), + .rx_is_lockedtoref (rx_is_lockedtoref), + .rx_is_lockedtodata (rx_is_lockedtodata), + .tx_coreclkin (tx_clk_156), + .rx_coreclkin (rx_clk_156), + .tx_clkout (), + .rx_clkout (), + .tx_parallel_data (xgmii_tx_data), + .rx_parallel_data (xgmii_rx_data), + .tx_control (xgmii_tx_control), + .tx_err_ins (1'b0), + .unused_tx_parallel_data (6'b0), + // .unused_tx_control (9'b0), + .rx_control (xgmii_rx_control), + // .tx_enh_data_valid (xgmii_tx_valid), + // .rx_enh_data_valid (xgmii_rx_valid), + .rx_enh_highber (), + .rx_enh_blk_lock (block_lock), + .unused_rx_parallel_data (), + // .unused_rx_control (), + .rx_analogreset_stat (rx_analogreset_stat), // rx_analogreset_stat.rx_analogreset_stat + .rx_digitalreset_stat (rx_digitalreset_stat), // rx_digitalreset_stat.rx_digitalreset_stat + .tx_analogreset_stat (tx_analogreset_stat), // tx_analogreset_stat.tx_analogreset_stat + .tx_digitalreset_stat (tx_digitalreset_stat), // tx_digitalreset_stat.tx_digitalreset_stat + .tx_digitalreset_timeout (tx_digitalreset_timeout), + .rx_digitalreset_timeout (rx_digitalreset_timeout), + .reconfig_clk (csr_clk), + .reconfig_reset (final_reconfig_rst), + .reconfig_write (phy_csr_write), + .reconfig_read (phy_csr_read), + .reconfig_address (phy_csr_address), + .reconfig_writedata (phy_csr_writedata), + .reconfig_readdata (phy_csr_readdata), + .reconfig_waitrequest (phy_csr_waitrequest) + // .rx_pma_div_clkout (), + // .tx_pma_div_clkout (), + // .rx_enh_fifo_del (), + // .rx_enh_fifo_empty (), + // .rx_enh_fifo_full (), + // .rx_enh_fifo_insert (), + // .tx_enh_fifo_empty (), + // .tx_enh_fifo_full (), + // .tx_enh_fifo_pempty (), + // .tx_enh_fifo_pfull () + +); + + + +reset_control reset_controller_inst( + .clock (csr_clk), + .reset (final_channel_rst), + .tx_analogreset (tx_analogreset), + .tx_digitalreset (tx_digitalreset), + .tx_ready (tx_ready_export), + .pll_locked (atx_pll_locked), + .pll_select (1'b0), + .tx_cal_busy (tx_cal_busy), + .rx_analogreset (rx_analogreset), + .rx_digitalreset (rx_digitalreset), + .rx_analogreset_stat (rx_analogreset_stat), + .rx_digitalreset_stat (rx_digitalreset_stat), + .tx_analogreset_stat (tx_analogreset_stat), + .tx_digitalreset_stat (tx_digitalreset_stat), + .rx_ready (rx_ready_export), + .rx_is_lockedtodata (rx_is_lockedtodata), + .rx_cal_busy (rx_cal_busy) + +); + +endmodule diff --git a/ipss/hssi/s10/altera_eth_10g_mac_base_r_wrap.v b/ipss/hssi/s10/altera_eth_10g_mac_base_r_wrap.v new file mode 100755 index 0000000..a55c519 --- /dev/null +++ b/ipss/hssi/s10/altera_eth_10g_mac_base_r_wrap.v @@ -0,0 +1,315 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +`timescale 1 ps / 1 ps +import ofs_fim_eth_if_pkg::*; +import hssi_csr_pkg::*; + +module altera_eth_10g_mac_base_r_wrap ( + // clock and reset + input wire csr_clk, + input wire csr_rst_n, + input wire tx_clk_312, + input wire tx_clk_156, + input wire sync_tx_rst_n, + input wire rx_clk_312, + input wire rx_clk_156, + input wire sync_rx_rst_n, + + input wire ref_clk_clk, + + //avlon_st tx interface + input wire avalon_st_tx_startofpacket, + input wire avalon_st_tx_endofpacket, + input wire avalon_st_tx_valid, + input wire [31:0] avalon_st_tx_data, + input wire [1:0] avalon_st_tx_empty, + input wire avalon_st_tx_error, + output wire avalon_st_tx_ready, + + // avalon_st rx interface + output wire avalon_st_rx_startofpacket, + output wire avalon_st_rx_endofpacket, + output wire avalon_st_rx_valid, + output wire [31:0] avalon_st_rx_data, + output wire [1:0] avalon_st_rx_empty, + input wire avalon_st_rx_ready, + output wire [5:0] avalon_st_rx_error, + + // additional st interface + input wire [1:0] avalon_st_pause_data, + input wire [15:0] avalon_st_tx_pfc_gen_data, // avalon_st_tx_pfc_gen_data.export + output wire [7:0] avalon_st_rx_pfc_pause_data, + output wire avalon_st_txstatus_valid, + output wire [39:0] avalon_st_txstatus_data, + output wire [6:0] avalon_st_txstatus_error, + + output wire avalon_st_rxstatus_valid, + output wire [6:0] avalon_st_rxstatus_error, + output wire [39:0] avalon_st_rxstatus_data, + + output wire [1:0] link_fault_status_xgmii_rx_data, + + // reset controller + output wire tx_ready_export, + output wire rx_ready_export, + output wire block_lock, + input wire atx_pll_locked, + + output wire tx_serial_data, + input wire rx_serial_data, + + input wire mac_csr_read, + input wire mac_csr_write, + output wire [31:0] mac_csr_readdata, + input wire [31:0] mac_csr_writedata, + output wire mac_csr_waitrequest, + input wire [9:0] mac_csr_address, + + input wire phy_csr_read, + input wire phy_csr_write, + output wire [31:0] phy_csr_readdata, + input wire [31:0] phy_csr_writedata, + output wire phy_csr_waitrequest, + input wire [10:0] phy_csr_address, + + input wire tx_serial_clk, + input wire final_channel_rst, + input wire final_reconfig_rst, + output hssi_stats_struct_t hssi_stats + +); + + +wire [7:0] xgmii_tx_control; +wire [63:0] xgmii_tx_data; +wire [71:0] xgmii_tx; + +wire [7:0] xgmii_rx_control; +wire [63:0] xgmii_rx_data; +wire [71:0] xgmii_rx; + +reg [71:0] xgmii_tx_reg; +reg [71:0] xgmii_rx_reg; + +//reset controller +wire tx_analogreset; +wire tx_digitalreset; +wire rx_analogreset; +wire rx_digitalreset; +wire rx_analogreset_stat; +wire rx_digitalreset_stat; +wire tx_analogreset_stat; +wire tx_digitalreset_stat; +wire tx_transfer_ready; +wire rx_transfer_ready; +wire tx_fifo_ready; +wire rx_fifo_ready; +wire rx_digitalreset_timeout; +wire tx_digitalreset_timeout; +wire rx_is_lockedtoref; +wire rx_is_lockedtodata; +wire tx_cal_busy; +wire rx_cal_busy; + +wire tx_clkout; +wire rx_clkout; + + + + // Map HSSI stats signals to structs + assign hssi_stats.rx_ready = rx_ready_export; + assign hssi_stats.tx_ready = tx_ready_export; + assign hssi_stats.rx_is_lockedtoref = rx_is_lockedtoref ; + assign hssi_stats.rx_is_lockedtodata = rx_is_lockedtodata; + assign hssi_stats.rx_cal_busy = rx_cal_busy; + assign hssi_stats.tx_cal_busy = tx_cal_busy; + assign hssi_stats.rx_transfer_ready = rx_transfer_ready; + assign hssi_stats.tx_transfer_ready = tx_transfer_ready; + assign hssi_stats.rx_fifo_ready = rx_fifo_ready; + assign hssi_stats.tx_fifo_ready = tx_fifo_ready; + assign hssi_stats.rx_digitalreset_timeout = rx_digitalreset_timeout; + assign hssi_stats.tx_digitalreset_timeout = tx_digitalreset_timeout; + assign hssi_stats.rx_digitalreset_stat = rx_digitalreset_stat; + assign hssi_stats.rx_analogreset_stat = rx_analogreset_stat; + assign hssi_stats.tx_digitalreset_stat = tx_digitalreset_stat; + assign hssi_stats.tx_analogreset_stat = tx_analogreset_stat; + + + +assign xgmii_tx_data = { + xgmii_tx_reg[70:63], + xgmii_tx_reg[61:54], + xgmii_tx_reg[52:45], + xgmii_tx_reg[43:36], + xgmii_tx_reg[34:27], + xgmii_tx_reg[25:18], + xgmii_tx_reg[16:9], + xgmii_tx_reg[7:0] +}; + +assign xgmii_tx_control = { + xgmii_tx_reg[71], + xgmii_tx_reg[62], + xgmii_tx_reg[53], + xgmii_tx_reg[44], + xgmii_tx_reg[35], + xgmii_tx_reg[26], + xgmii_tx_reg[17], + xgmii_tx_reg[8] +}; + +assign xgmii_rx = { + xgmii_rx_control[7], xgmii_rx_data[63:56], + xgmii_rx_control[6], xgmii_rx_data[55:48], + xgmii_rx_control[5], xgmii_rx_data[47:40], + xgmii_rx_control[4], xgmii_rx_data[39:32], + xgmii_rx_control[3], xgmii_rx_data[31:24], + xgmii_rx_control[2], xgmii_rx_data[23:16], + xgmii_rx_control[1], xgmii_rx_data[15:8], + xgmii_rx_control[0], xgmii_rx_data[7:0]}; + +always @(posedge tx_clk_156) +begin + xgmii_tx_reg <= xgmii_tx; +end + +always @(posedge rx_clk_156) +begin + xgmii_rx_reg <= xgmii_rx; +end + +altera_eth_10g_mac mac_inst ( + + .csr_read (mac_csr_read), + .csr_write (mac_csr_write), + .csr_writedata (mac_csr_writedata), + .csr_readdata (mac_csr_readdata), + .csr_waitrequest (mac_csr_waitrequest), + .csr_address (mac_csr_address), + .csr_clk (csr_clk), + .csr_rst_n (~final_reconfig_rst), + .tx_rst_n (sync_tx_rst_n), + .rx_rst_n (sync_rx_rst_n), + .avalon_st_tx_startofpacket (avalon_st_tx_startofpacket), + .avalon_st_tx_endofpacket (avalon_st_tx_endofpacket), + .avalon_st_tx_valid (avalon_st_tx_valid), + .avalon_st_tx_data (avalon_st_tx_data), + .avalon_st_tx_empty (avalon_st_tx_empty), + .avalon_st_tx_error (avalon_st_tx_error), + .avalon_st_tx_ready (avalon_st_tx_ready), + .avalon_st_pause_data (avalon_st_pause_data), + .avalon_st_tx_pfc_gen_data (avalon_st_tx_pfc_gen_data ), + .avalon_st_rx_pfc_pause_data(avalon_st_rx_pfc_pause_data), + .avalon_st_txstatus_valid (avalon_st_txstatus_valid), + .avalon_st_txstatus_data (avalon_st_txstatus_data), + .avalon_st_txstatus_error (avalon_st_txstatus_error), + .link_fault_status_xgmii_rx_data (link_fault_status_xgmii_rx_data), + .avalon_st_rx_data (avalon_st_rx_data), + .avalon_st_rx_startofpacket (avalon_st_rx_startofpacket), + .avalon_st_rx_valid (avalon_st_rx_valid), + .avalon_st_rx_empty (avalon_st_rx_empty), + .avalon_st_rx_error (avalon_st_rx_error), + .avalon_st_rx_ready (avalon_st_rx_ready), + .avalon_st_rx_endofpacket (avalon_st_rx_endofpacket), + .avalon_st_rxstatus_valid (avalon_st_rxstatus_valid), + .avalon_st_rxstatus_data (avalon_st_rxstatus_data), + .avalon_st_rxstatus_error (avalon_st_rxstatus_error), + + .rx_156_25_clk (rx_clk_156), + .rx_312_5_clk (rx_clk_312), + .tx_156_25_clk (tx_clk_156), + .tx_312_5_clk (tx_clk_312), + + .xgmii_rx (xgmii_rx_reg), + .xgmii_tx (xgmii_tx) + +); + + +altera_eth_10gbaser_phy baser_inst ( + + .tx_analogreset (tx_analogreset), + .tx_digitalreset (tx_digitalreset), + .rx_analogreset (rx_analogreset), + .rx_digitalreset (rx_digitalreset), + .tx_transfer_ready (tx_transfer_ready), + .rx_transfer_ready (rx_transfer_ready), + .tx_fifo_ready (tx_fifo_ready), + .rx_fifo_ready (rx_fifo_ready), + .tx_cal_busy (tx_cal_busy), + .rx_cal_busy (rx_cal_busy), + .tx_serial_clk0 (tx_serial_clk), + .rx_cdr_refclk0 (ref_clk_clk), + .tx_serial_data (tx_serial_data), + .rx_serial_data (rx_serial_data), + .rx_is_lockedtoref (rx_is_lockedtoref), + .rx_is_lockedtodata (rx_is_lockedtodata), + .tx_coreclkin (tx_clk_156), + .rx_coreclkin (rx_clk_156), + .tx_clkout (), + .rx_clkout (), + .tx_parallel_data (xgmii_tx_data), + .rx_parallel_data (xgmii_rx_data), + .tx_control (xgmii_tx_control), + .tx_err_ins (1'b0), + .unused_tx_parallel_data (6'b0), + // .unused_tx_control (9'b0), + .rx_control (xgmii_rx_control), + // .tx_enh_data_valid (xgmii_tx_valid), + // .rx_enh_data_valid (xgmii_rx_valid), + .rx_enh_highber (), + .rx_enh_blk_lock (block_lock), + .unused_rx_parallel_data (), + // .unused_rx_control (), + .rx_analogreset_stat (rx_analogreset_stat), // rx_analogreset_stat.rx_analogreset_stat + .rx_digitalreset_stat (rx_digitalreset_stat), // rx_digitalreset_stat.rx_digitalreset_stat + .tx_analogreset_stat (tx_analogreset_stat), // tx_analogreset_stat.tx_analogreset_stat + .tx_digitalreset_stat (tx_digitalreset_stat), // tx_digitalreset_stat.tx_digitalreset_stat + .tx_digitalreset_timeout (tx_digitalreset_timeout), + .rx_digitalreset_timeout (rx_digitalreset_timeout), + .reconfig_clk (csr_clk), + .reconfig_reset (final_reconfig_rst), + .reconfig_write (phy_csr_write), + .reconfig_read (phy_csr_read), + .reconfig_address (phy_csr_address), + .reconfig_writedata (phy_csr_writedata), + .reconfig_readdata (phy_csr_readdata), + .reconfig_waitrequest (phy_csr_waitrequest) + // .rx_pma_div_clkout (), + // .tx_pma_div_clkout (), + // .rx_enh_fifo_del (), + // .rx_enh_fifo_empty (), + // .rx_enh_fifo_full (), + // .rx_enh_fifo_insert (), + // .tx_enh_fifo_empty (), + // .tx_enh_fifo_full (), + // .tx_enh_fifo_pempty (), + // .tx_enh_fifo_pfull () + +); + + + +reset_control reset_controller_inst( + .clock (csr_clk), + .reset (final_channel_rst), + .tx_analogreset (tx_analogreset), + .tx_digitalreset (tx_digitalreset), + .tx_ready (tx_ready_export), + .pll_locked (atx_pll_locked), + .pll_select (1'b0), + .tx_cal_busy (tx_cal_busy), + .rx_analogreset (rx_analogreset), + .rx_digitalreset (rx_digitalreset), + .rx_analogreset_stat (rx_analogreset_stat), + .rx_digitalreset_stat (rx_digitalreset_stat), + .tx_analogreset_stat (tx_analogreset_stat), + .tx_digitalreset_stat (tx_digitalreset_stat), + .rx_ready (rx_ready_export), + .rx_is_lockedtodata (rx_is_lockedtodata), + .rx_cal_busy (rx_cal_busy) + +); + +endmodule diff --git a/ipss/hssi/s10/av_axi_st_bridge.sv b/ipss/hssi/s10/av_axi_st_bridge.sv new file mode 100755 index 0000000..8b21ee4 --- /dev/null +++ b/ipss/hssi/s10/av_axi_st_bridge.sv @@ -0,0 +1,88 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +//----------------------------------------------------------------------------- + +`timescale 1 ps / 1 ps + +import ofs_fim_eth_if_pkg::*; +import ofs_fim_eth_avst_if_pkg::*; +//Assumption : All packets are more than a cycle long +module av_axi_st_eth_bridge ( + + //clock & reset + input wire tx_clk, + input wire tx_rst_n, + input wire rx_clk, + input wire rx_rst_n, + + // Tx AXI streaming interface (i/p) + ofs_fim_eth_tx_axis_if.slave axi_tx_st, + + //TX Av streaming interface (o/p) + output logic avalon_st_tx_startofpacket, + output logic avalon_st_tx_endofpacket, + output logic avalon_st_tx_valid, + output logic [ETH_PACKET_WIDTH-1:0] avalon_st_tx_data, + output logic [AVST_ETH_EMPTY_WIDTH-1:0] avalon_st_tx_empty, + output logic [ETH_TX_ERROR_WIDTH-1:0] avalon_st_tx_error, + input logic avalon_st_tx_ready, + + //RX Av streaming interface (i/p) + input logic avalon_st_rx_startofpacket, + input logic avalon_st_rx_endofpacket, + input logic avalon_st_rx_valid, + input logic [ETH_PACKET_WIDTH-1:0] avalon_st_rx_data, + input logic [AVST_ETH_EMPTY_WIDTH-1:0] avalon_st_rx_empty, + output logic avalon_st_rx_ready, + input logic [ETH_RX_ERROR_WIDTH-1:0] avalon_st_rx_error, + + //RX AXI streaming interface (o/p) + ofs_fim_eth_rx_axis_if.master axi_rx_st +); + +logic is_tx_sop; + +// **************************************************** +// *-----------------TX Bridge------------------------* +// **************************************************** +always_comb +begin + axi_tx_st.tready = avalon_st_tx_ready; + avalon_st_tx_valid = axi_tx_st.tx.tvalid; + avalon_st_tx_data = ofs_fim_eth_avst_if_pkg::eth_axi_to_avst_data(axi_tx_st.tx.tdata); + avalon_st_tx_startofpacket = avalon_st_tx_ready & axi_tx_st.tx.tvalid & is_tx_sop; + avalon_st_tx_endofpacket = avalon_st_tx_ready & axi_tx_st.tx.tvalid & axi_tx_st.tx.tlast; + avalon_st_tx_error = axi_tx_st.tx.tuser.error; + avalon_st_tx_empty = ofs_fim_eth_avst_if_pkg::eth_tkeep_to_empty(axi_tx_st.tx.tkeep); + + axi_tx_st.clk = tx_clk; + axi_tx_st.rst_n = tx_rst_n; +end + +// Tx SOP always follows a tlast AXI-S flit +always_ff @(posedge tx_clk) +begin + if (!tx_rst_n) + is_tx_sop <= 1'b1; + else if (axi_tx_st.tx.tvalid && axi_tx_st.tready) + is_tx_sop <= axi_tx_st.tx.tlast; +end + +// **************************************************** +// *-----------------RX Bridge------------------------* +// **************************************************** +always_comb +begin + avalon_st_rx_ready = axi_rx_st.tready; + axi_rx_st.rx.tvalid = avalon_st_rx_valid ; + axi_rx_st.rx.tdata = ofs_fim_eth_avst_if_pkg::eth_avst_to_axi_data(avalon_st_rx_data); + axi_rx_st.rx.tlast = avalon_st_rx_endofpacket& avalon_st_rx_valid; + axi_rx_st.rx.tuser.error = avalon_st_rx_error ; + axi_rx_st.rx.tkeep = ofs_fim_eth_avst_if_pkg::eth_empty_to_tkeep(avalon_st_rx_empty); + + axi_rx_st.clk = rx_clk; + axi_rx_st.rst_n = rx_rst_n; +end + +endmodule diff --git a/ipss/hssi/s10/eth_ac_wrapper.sv b/ipss/hssi/s10/eth_ac_wrapper.sv new file mode 100755 index 0000000..83a3056 --- /dev/null +++ b/ipss/hssi/s10/eth_ac_wrapper.sv @@ -0,0 +1,153 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// AC Eth Wrapper module instantiate and eth_top module and maps signals to make +// it compatible with HSSI SS IP ports so as to use same HE-HSSI module at client +// side +// +//----------------------------------------------------------------------------- +// + + +import ofs_fim_eth_if_pkg::NUM_LANES; +import ofs_fim_eth_if_pkg::MAX_NUM_ETH_CHANNELS; +import ofs_fim_eth_if_pkg::NUM_ETH_CHANNELS; + +module eth_ac_wrapper ( + input logic clk_csr, + input logic rst_n_csr, + input logic clk_100M, + input logic rst_n_100M, + + ofs_fim_axi_lite_if.slave csr_lite_if, + + // Streaming data interfaces + ofs_fim_hssi_ss_tx_axis_if.mac hssi_ss_st_tx [MAX_NUM_ETH_CHANNELS-1:0], + ofs_fim_hssi_ss_rx_axis_if.mac hssi_ss_st_rx [MAX_NUM_ETH_CHANNELS-1:0], + + // Flow control interfaces + ofs_fim_hssi_fc_if.mac hssi_fc [MAX_NUM_ETH_CHANNELS-1:0], + + output wire [NUM_ETH_CHANNELS-1:0][NUM_LANES-1:0] tx_serial, + output wire [NUM_ETH_CHANNELS-1:0][NUM_LANES-1:0] tx_serial_n, + input wire [NUM_ETH_CHANNELS-1:0][NUM_LANES-1:0] rx_serial, + input wire [NUM_ETH_CHANNELS-1:0][NUM_LANES-1:0] rx_serial_n, + + input wire subsystem_cold_rst_n, + + input logic [1:0] i_clk_ref, + output logic [MAX_NUM_ETH_CHANNELS-1:0] o_hssi_clk_pll, + output logic [MAX_NUM_ETH_CHANNELS-1:0] o_hssi_rx_clk_pll + +); + +//Signal declarations for Ethernet interface +(*noprune*) logic [NUM_ETH_CHANNELS-1:0] tx_ready_export; +(*noprune*) logic [NUM_ETH_CHANNELS-1:0] rx_ready_export; +(*noprune*) logic [NUM_ETH_CHANNELS-1:0] block_lock; +(*noprune*) logic atx_pll_locked; + +// Tx AXI streaming interface +ofs_fim_eth_tx_axis_if axis_eth_tx [NUM_ETH_CHANNELS-1:0](); +//RX AXI streaming interface +ofs_fim_eth_rx_axis_if axis_eth_rx [NUM_ETH_CHANNELS-1:0](); +// Sideband signals +ofs_fim_eth_sideband_rx_axis_if axi_eth_sideband_rx [NUM_ETH_CHANNELS-1:0] (); +ofs_fim_eth_sideband_tx_axis_if axi_eth_sideband_tx [NUM_ETH_CHANNELS-1:0] (); + +// E-tile to H-tile Shim +// -----------------CSR Shim---------------------------------// + +ofs_fim_axi_mmio_if csr_if(); + +axi_lite2mmio hssi_csr_shim // Converting AXI-Lite to AXI-MM +( + .clk(clk_csr), + .rst_n(rst_n_csr), + .lite_if(csr_lite_if), + .mmio_if(csr_if) +); + +//========== start loop for number of ethernet channels======================== + +genvar portid; +generate + +for (portid =0; portid < NUM_ETH_CHANNELS; portid = portid+1) +begin: CHANNEL + //-----------------------------Clk Shim---------------------------// + assign o_hssi_clk_pll[portid] = axis_eth_tx[portid].clk ; + + //----------------------------Tx/Rx Streaming Datapath------------------// + assign hssi_ss_st_tx[portid].clk = axis_eth_tx[portid].clk; + assign hssi_ss_st_tx[portid].rst_n = axis_eth_tx[portid].rst_n; + assign hssi_ss_st_tx[portid].tready = axis_eth_tx[portid].tready; + assign axis_eth_tx[portid].tx.tvalid = hssi_ss_st_tx[portid].tx.tvalid; + assign axis_eth_tx[portid].tx.tdata = hssi_ss_st_tx[portid].tx.tdata; + assign axis_eth_tx[portid].tx.tkeep = hssi_ss_st_tx[portid].tx.tkeep; + assign axis_eth_tx[portid].tx.tlast = hssi_ss_st_tx[portid].tx.tlast; + assign axis_eth_tx[portid].tx.tuser = hssi_ss_st_tx[portid].tx.tuser.client[0]; + assign hssi_ss_st_rx[portid].clk = axis_eth_rx[portid].clk; + assign hssi_ss_st_rx[portid].rst_n = axis_eth_rx[portid].rst_n; + assign hssi_ss_st_rx[portid].rx.tvalid = axis_eth_rx[portid].rx.tvalid; + assign hssi_ss_st_rx[portid].rx.tdata = axis_eth_rx[portid].rx.tdata; + assign hssi_ss_st_rx[portid].rx.tkeep = axis_eth_rx[portid].rx.tkeep; + assign hssi_ss_st_rx[portid].rx.tlast = axis_eth_rx[portid].rx.tlast; + `ifdef ETH_100G + assign hssi_ss_st_rx[portid].rx.tuser.client[0] = axis_eth_rx[portid].rx.tuser[0]; + assign hssi_ss_st_rx[portid].rx.tuser.client[6] = 1'b0; + `else + assign hssi_ss_st_rx[portid].rx.tuser.client[0] = 1'b0; + assign hssi_ss_st_rx[portid].rx.tuser.client[6] = axis_eth_rx[portid].rx.tuser[0]; + `endif + assign hssi_ss_st_rx[portid].rx.tuser.client[5] = axis_eth_rx[portid].rx.tuser[1]; + assign hssi_ss_st_rx[portid].rx.tuser.client[2] = axis_eth_rx[portid].rx.tuser[2]; + assign hssi_ss_st_rx[portid].rx.tuser.client[3] = axis_eth_rx[portid].rx.tuser[3]; + assign hssi_ss_st_rx[portid].rx.tuser.client[4] = axis_eth_rx[portid].rx.tuser[4]; + assign hssi_ss_st_rx[portid].rx.tuser.client[1] = 1'b0; + assign hssi_ss_st_rx[portid].rx.tuser.sts = 5'h0; + assign axis_eth_rx[portid].tready = 1'b1; + + //----------------Tx/Rx Sideband Interface-------------------------------// + assign axi_eth_sideband_tx[portid].sb.tvalid = hssi_fc[portid].tx_pause | (hssi_fc[portid].tx_pfc); + assign axi_eth_sideband_tx[portid].sb.tdata.pause_xoff = hssi_fc[portid].tx_pause; + assign axi_eth_sideband_tx[portid].sb.tdata.pfc_xoff = hssi_fc[portid].tx_pfc; + assign axi_eth_sideband_tx[portid].sb.tdata.pause_xon = '0; + + assign hssi_fc[portid].rx_pause = axi_eth_sideband_rx[portid].sb.tdata.rx_pause & axi_eth_sideband_rx[portid].sb.tvalid; + assign hssi_fc[portid].rx_pfc = axi_eth_sideband_rx[portid].sb.tdata.pfc_pause & axi_eth_sideband_rx[portid].sb.tvalid; +end //for loop end +endgenerate + +eth_top eth_top ( + // clock and reset + .csr_clk (clk_100M), + .csr_rst_n (rst_n_100M), + .tx_rst_n (subsystem_cold_rst_n), + .rx_rst_n (subsystem_cold_rst_n), + .ref_clk_clk (i_clk_ref), + // reset controller + .tx_ready_export (tx_ready_export), + .rx_ready_export (rx_ready_export), + .block_lock (block_lock), + .atx_pll_locked (atx_pll_locked), + .tx_serial_data (tx_serial), + .rx_serial_data (rx_serial), + + .csr_if (csr_if), + + .pr_freeze (), + + // Tx AXI streaming interface + .axi_tx_st (axis_eth_tx), + // Rx AXI streaming interface + .axi_rx_st (axis_eth_rx), + // AXI-S sideband interface + .axi_sideband_rx (axi_eth_sideband_rx), + .axi_sideband_tx (axi_eth_sideband_tx) +); + +endmodule diff --git a/ipss/hssi/s10/eth_top.sv b/ipss/hssi/s10/eth_top.sv new file mode 100755 index 0000000..79f1256 --- /dev/null +++ b/ipss/hssi/s10/eth_top.sv @@ -0,0 +1,642 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Top level module of HSSI subsystem. +// +//----------------------------------------------------------------------------- + +`default_nettype none +import ofs_fim_eth_if_pkg::NUM_ETH_CHANNELS; +import ofs_fim_eth_if_pkg::MAX_NUM_ETH_CHANNELS; + +import hssi_csr_pkg::*; + +module eth_top ( + + // clock and reset + input wire csr_clk, + input wire csr_rst_n, + input wire tx_rst_n, + input wire rx_rst_n, + input wire ref_clk_clk, + + // Status and debug signals + output wire [NUM_ETH_CHANNELS-1:0] tx_ready_export, + output wire [NUM_ETH_CHANNELS-1:0] rx_ready_export, + output wire [NUM_ETH_CHANNELS-1:0] block_lock, + output wire atx_pll_locked, + output wire core_pll_locked, + + // Serial data + output wire [NUM_ETH_CHANNELS-1:0] tx_serial_data, + input wire [NUM_ETH_CHANNELS-1:0] rx_serial_data, + + // AXI4 CSR interface + ofs_fim_axi_mmio_if.slave csr_if, + + // PR Freeze signal to stop ready while PR process is in progress + input wire pr_freeze, + + // Tx AXI streaming interface + ofs_fim_eth_tx_axis_if.slave axi_tx_st [NUM_ETH_CHANNELS-1:0], + + //RX AXI streaming interface + ofs_fim_eth_rx_axis_if.master axi_rx_st [NUM_ETH_CHANNELS-1:0], + + // RX AXI sideband interface + ofs_fim_eth_sideband_rx_axis_if.master axi_sideband_rx [NUM_ETH_CHANNELS-1:0], + + // TX AXI sideband interface + ofs_fim_eth_sideband_tx_axis_if.slave axi_sideband_tx [NUM_ETH_CHANNELS-1:0] +); + +parameter DEVICE_FAMILY = "Stratix 10"; +localparam AVM_ADDR_WIDTH = 11 ; + +wire csr_waitrequest; +wire [31:0] csr_readdata; +wire [31:0] csr_writedata; +wire [15:0] csr_address; +wire csr_write; +wire csr_read; + +wire [NUM_ETH_CHANNELS-1:0] mac_csr_read_32; +wire [NUM_ETH_CHANNELS-1:0] mac_csr_write_32; +wire [NUM_ETH_CHANNELS-1:0][31:0] mac_csr_readdata_32; +wire [NUM_ETH_CHANNELS-1:0][31:0] mac_csr_writedata_32; +wire [NUM_ETH_CHANNELS-1:0] mac_csr_waitrequest_32; +wire [NUM_ETH_CHANNELS-1:0][9:0] mac_csr_address_32; + +wire [MAX_NUM_ETH_CHANNELS-1:0] mac_csr_read_64; +wire [MAX_NUM_ETH_CHANNELS-1:0] mac_csr_write_64; +wire [MAX_NUM_ETH_CHANNELS-1:0][31:0] mac_csr_readdata_64; +wire [MAX_NUM_ETH_CHANNELS-1:0][31:0] mac_csr_writedata_64; +wire [MAX_NUM_ETH_CHANNELS-1:0] mac_csr_waitrequest_64; +wire [MAX_NUM_ETH_CHANNELS-1:0][13:0] mac_csr_address_64; + +wire [MAX_NUM_ETH_CHANNELS-1:0] phy_csr_read; +wire [MAX_NUM_ETH_CHANNELS-1:0] phy_csr_write; +wire [MAX_NUM_ETH_CHANNELS-1:0][31:0] phy_csr_readdata; +wire [MAX_NUM_ETH_CHANNELS-1:0][31:0] phy_csr_writedata; +wire [MAX_NUM_ETH_CHANNELS-1:0] phy_csr_waitrequest; +wire [MAX_NUM_ETH_CHANNELS-1:0][AVM_ADDR_WIDTH-1:0] phy_csr_address; + +wire [NUM_ETH_CHANNELS-1:0][1:0] avalon_st_pause_data_sync , avalon_st_tx_pause_data_156; +wire [NUM_ETH_CHANNELS-1:0][15:0] avalon_st_tx_pfc_data_sync, avalon_st_tx_pfc_data_156; +wire [NUM_ETH_CHANNELS-1:0][7:0] avalon_st_rx_pfc_data_sync, avalon_st_rx_pfc_pause_data_156; +logic [NUM_ETH_CHANNELS-1:0][39:0] avalon_st_rxstatus_data_312; +logic [NUM_ETH_CHANNELS-1:0][4:0] avalon_st_rxstatus_data_156; +logic [NUM_ETH_CHANNELS-1:0] avalon_st_rxstatus_valid_312, avalon_st_rxstatus_valid_156; + +wire sync_rx_rst_n; +wire sync_rx_half_rst_n; +wire sync_tx_half_rst_n; +wire sync_tx_rst_n; + +wire sync_tx_half_rst; +wire sync_rx_half_rst; + +wire sync_tx_rst; +wire sync_rx_rst; + +wire tx_serial_clk; +wire core_clk_312; +wire core_clk_156; +wire csr_clk_156 ; +wire csr_rst_n_156; +assign sync_tx_rst_n = ~sync_tx_rst; +assign sync_rx_rst_n = ~sync_rx_rst; + +assign sync_rx_half_rst_n = ~sync_rx_half_rst; +assign sync_tx_half_rst_n = ~sync_tx_half_rst; + + +assign csr_clk_156 = core_clk_156; +assign csr_rst_n_156 = sync_tx_half_rst_n; + +wire [NUM_ETH_CHANNELS-1:0][31:0] mac_in_data; +wire [NUM_ETH_CHANNELS-1:0] mac_in_valid; +wire [NUM_ETH_CHANNELS-1:0] mac_in_ready; +wire [NUM_ETH_CHANNELS-1:0] mac_in_startofpacket; +wire [NUM_ETH_CHANNELS-1:0] mac_in_endofpacket; +wire [NUM_ETH_CHANNELS-1:0][1:0] mac_in_empty; +wire [NUM_ETH_CHANNELS-1:0][0:0] mac_in_error; +wire [NUM_ETH_CHANNELS-1:0] mac_in_ready_pr; + +wire [NUM_ETH_CHANNELS-1:0][63:0] tx_out_data; +wire [NUM_ETH_CHANNELS-1:0] tx_out_valid; +wire [NUM_ETH_CHANNELS-1:0] tx_out_ready; +wire [NUM_ETH_CHANNELS-1:0] tx_out_startofpacket; +wire [NUM_ETH_CHANNELS-1:0] tx_out_endofpacket; +wire [NUM_ETH_CHANNELS-1:0][2:0] tx_out_empty; +wire [NUM_ETH_CHANNELS-1:0][0:0] tx_out_error; + +wire [NUM_ETH_CHANNELS-1:0][31:0] mac_out_data; +wire [NUM_ETH_CHANNELS-1:0] mac_out_valid; +wire [NUM_ETH_CHANNELS-1:0] mac_out_ready; +wire [NUM_ETH_CHANNELS-1:0] mac_out_startofpacket; +wire [NUM_ETH_CHANNELS-1:0] mac_out_endofpacket; +wire [NUM_ETH_CHANNELS-1:0][1:0] mac_out_empty; +wire [NUM_ETH_CHANNELS-1:0][5:0] mac_out_error; + +wire [NUM_ETH_CHANNELS-1:0][63:0] rx_in_data; +wire [NUM_ETH_CHANNELS-1:0] rx_in_valid; +wire [NUM_ETH_CHANNELS-1:0] rx_in_ready; +wire [NUM_ETH_CHANNELS-1:0] rx_in_startofpacket; +wire [NUM_ETH_CHANNELS-1:0] rx_in_endofpacket; +wire [NUM_ETH_CHANNELS-1:0][2:0] rx_in_empty; +wire [NUM_ETH_CHANNELS-1:0][5:0] rx_in_error; + +hssi_stats_struct_t hssi_stats[NUM_ETH_CHANNELS-1:0]; +wire [NUM_ETH_CHANNELS-1:0] final_channel_rst; +wire [7:0] final_reconfig_rst; + +wire hssi_pr_freeze; + +// PLLs locked +wire plls_locked ; +assign plls_locked = atx_pll_locked & core_pll_locked; + +//HSSI CSR +localparam MM_CMD_W = 3; // MM Reconfiguration Controller command width +localparam MM_ADDR_W = 20; // MM Reconfiguration Controller address width +localparam MM_DATA_W = 32; // MM Reconfiguration Controller data width +localparam RCFG_ADDR_W = 16; // PHY reconfiguration address width +localparam RCFG_DATA_W = 32; // PHY reconfiguration data width + +hssi_csr #( + .CMD_W (MM_CMD_W), // User command width + .USER_ADDR_W (MM_ADDR_W), // User address width + .AVMM_ADDR_W (RCFG_ADDR_W), // AVMM address width + .DATA_W (RCFG_DATA_W), // Data width + .SIM (0) +)hssi_csr_inst ( + .csr_clk (csr_clk_156), + .csr_rst (~csr_rst_n_156), + .csr_if (csr_if), + .i_avmm_waitrequest (csr_waitrequest), + .i_avmm_readdata (csr_readdata), + .o_avmm_writedata (csr_writedata), + .o_avmm_addr (csr_address), + .o_avmm_write (csr_write), + .o_avmm_read (csr_read), + .plls_locked (plls_locked), + .hssi_stats (hssi_stats), + .final_channel_rst (final_channel_rst), + .final_reconfig_rst (final_reconfig_rst) +); + +// Address decoder to map indirect access csr address into MAC and PHY space +address_decode address_decoder_inst ( + + .clk_csr_clk (csr_clk_156), + .csr_reset_n (csr_rst_n_156), + + .tx_xcvr_half_clk_clk (core_clk_156), + .sync_tx_half_rst_reset_n (sync_tx_half_rst_n), + .tx_xcvr_clk_clk (core_clk_312), + .sync_tx_rst_reset_n (sync_tx_rst_n), + .rx_xcvr_clk_clk (core_clk_312), + .sync_rx_rst_reset_n (sync_rx_rst_n), + + .merlin_master_translator_0_avalon_anti_master_0_address (csr_address), + .merlin_master_translator_0_avalon_anti_master_0_waitrequest (csr_waitrequest), + .merlin_master_translator_0_avalon_anti_master_0_read (csr_read), + .merlin_master_translator_0_avalon_anti_master_0_readdata (csr_readdata), + .merlin_master_translator_0_avalon_anti_master_0_write (csr_write), + .merlin_master_translator_0_avalon_anti_master_0_writedata (csr_writedata), + .mac_0_avalon_anti_slave_0_address (mac_csr_address_64[0][12:0]), + .mac_0_avalon_anti_slave_0_write (mac_csr_write_64[0]), + .mac_0_avalon_anti_slave_0_read (mac_csr_read_64[0]), + .mac_0_avalon_anti_slave_0_readdata (mac_csr_readdata_64[0]), + .mac_0_avalon_anti_slave_0_writedata (mac_csr_writedata_64[0]), + .mac_0_avalon_anti_slave_0_waitrequest (mac_csr_waitrequest_64[0]), + .phy_0_avalon_anti_slave_0_address (phy_csr_address[0]), + .phy_0_avalon_anti_slave_0_write (phy_csr_write[0]), + .phy_0_avalon_anti_slave_0_read (phy_csr_read[0]), + .phy_0_avalon_anti_slave_0_readdata (phy_csr_readdata[0]), + .phy_0_avalon_anti_slave_0_writedata (phy_csr_writedata[0]), + .phy_0_avalon_anti_slave_0_waitrequest (phy_csr_waitrequest[0]) + ); + +//========== start loop for number of ethernet channels======================== + +genvar portid; +generate + +for (portid =0; portid < NUM_ETH_CHANNELS; portid = portid+1) +begin: CHANNEL + + // csr adapter to convert legacy megacore 64b IP CSR address to LL 32b IP interface + altera_eth_avalon_mm_adapter csr_adapter_inst( + // Avalon Slave Interface + .sl_clock (csr_clk_156), + .sl_reset (~csr_rst_n_156), + .sl_csr_readdata_o (mac_csr_readdata_64[portid]), + .sl_csr_address_i (mac_csr_address_64[portid][12:0]), + .sl_csr_read_i (mac_csr_read_64[portid]), + .sl_csr_write_i (mac_csr_write_64[portid]), + .sl_csr_writedata_i (mac_csr_writedata_64[portid]), + .sl_csr_waitrequest_o (mac_csr_waitrequest_64[portid]), + + // Avalon Master Interface + .ms_clock (), + .ms_reset (), + .ms_csr_readdata_i (mac_csr_readdata_32[portid]), + .ms_csr_address_o (mac_csr_address_32[portid]), + .ms_csr_read_o (mac_csr_read_32[portid]), + .ms_csr_write_o (mac_csr_write_32[portid]), + .ms_csr_writedata_o (mac_csr_writedata_32[portid]), + .ms_csr_waitrequest_i (mac_csr_waitrequest_32[portid]) + ); + + // HSSI AVST <-> HE-HSSI AXIS conversion + av_axi_st_eth_bridge av_axi_st_eth_bridge_inst ( + .tx_clk (core_clk_156), + .tx_rst_n (sync_tx_half_rst_n), + .rx_clk (core_clk_156), + .rx_rst_n (sync_rx_half_rst_n), + + .axi_tx_st (axi_tx_st[portid]), + .avalon_st_tx_startofpacket (tx_out_startofpacket[portid]), + .avalon_st_tx_endofpacket (tx_out_endofpacket[portid]), + .avalon_st_tx_valid (tx_out_valid[portid]), + .avalon_st_tx_data (tx_out_data[portid]), + .avalon_st_tx_empty (tx_out_empty[portid]), + .avalon_st_tx_ready (tx_out_ready[portid]), + .avalon_st_tx_error (tx_out_error[portid]), + + .axi_rx_st (axi_rx_st[portid]), + .avalon_st_rx_startofpacket (rx_in_startofpacket[portid]), + .avalon_st_rx_endofpacket (rx_in_endofpacket[portid]), + .avalon_st_rx_valid (rx_in_valid[portid]), + .avalon_st_rx_data (rx_in_data[portid]), + .avalon_st_rx_empty (rx_in_empty[portid]), + .avalon_st_rx_ready (rx_in_ready[portid]), + .avalon_st_rx_error (rx_in_error[portid]) + ); + + // Deassert tx ready when pr_freeze is high + assign mac_in_ready_pr[portid] = hssi_pr_freeze ? 'b0 : mac_in_ready[portid]; + // Tx (AFU -> MAC) sideband requests XOFF/XON pause frames + assign axi_sideband_tx[portid].clk = core_clk_156; + assign axi_sideband_tx[portid].rst_n = sync_tx_half_rst_n; + assign avalon_st_tx_pause_data_156[portid] = axi_sideband_tx[portid].sb.tvalid ? + { axi_sideband_tx[portid].sb.tdata.pause_xoff, axi_sideband_tx[portid].sb.tdata.pause_xon } : + '0; + // Flow control signal assignements + assign avalon_st_tx_pfc_data_156[portid][0] = '0; + assign avalon_st_tx_pfc_data_156[portid][2] = '0; + assign avalon_st_tx_pfc_data_156[portid][4] = '0; + assign avalon_st_tx_pfc_data_156[portid][6] = '0; + assign avalon_st_tx_pfc_data_156[portid][8] = '0; + assign avalon_st_tx_pfc_data_156[portid][10] = '0; + assign avalon_st_tx_pfc_data_156[portid][12] = '0; + assign avalon_st_tx_pfc_data_156[portid][14] = '0; + + assign avalon_st_tx_pfc_data_156[portid][1] = axi_sideband_tx[portid].sb.tdata.pfc_xoff[0]; + assign avalon_st_tx_pfc_data_156[portid][3] = axi_sideband_tx[portid].sb.tdata.pfc_xoff[1]; + assign avalon_st_tx_pfc_data_156[portid][5] = axi_sideband_tx[portid].sb.tdata.pfc_xoff[2]; + assign avalon_st_tx_pfc_data_156[portid][7] = axi_sideband_tx[portid].sb.tdata.pfc_xoff[3]; + assign avalon_st_tx_pfc_data_156[portid][9] = axi_sideband_tx[portid].sb.tdata.pfc_xoff[4]; + assign avalon_st_tx_pfc_data_156[portid][11] = axi_sideband_tx[portid].sb.tdata.pfc_xoff[5]; + assign avalon_st_tx_pfc_data_156[portid][13] = axi_sideband_tx[portid].sb.tdata.pfc_xoff[6]; + assign avalon_st_tx_pfc_data_156[portid][15] = axi_sideband_tx[portid].sb.tdata.pfc_xoff[7]; + + // Rx sideband not currently used + assign axi_sideband_rx[portid].clk = core_clk_156; + assign axi_sideband_rx[portid].rst_n = sync_rx_half_rst_n; + assign axi_sideband_rx[portid].sb.tvalid = (|avalon_st_rx_pfc_pause_data_156[portid] || avalon_st_rxstatus_data_156[portid][0]); + assign axi_sideband_rx[portid].sb.tdata.pfc_pause = avalon_st_rx_pfc_pause_data_156[portid]; + assign axi_sideband_rx[portid].sb.tdata.rx_pause = avalon_st_rxstatus_data_156[portid][0]; //FC Bit + + // AVST adapter to convert legacy megacore 64b IP interface to LL 32b IP interface + altera_eth_avalon_st_adapter #( + .DEVICE_FAMILY (DEVICE_FAMILY), + .ENABLE_PFC (1) + ) dc_fifo_adapter_inst( + + .csr_tx_adptdcff_rdwtrmrk (3'b010), + .csr_tx_adptdcff_vldpkt_minwt (3'b010), + .csr_tx_adptdcff_rdwtrmrk_dis (1'b0), + + .avalon_st_tx_clk_312 (core_clk_312), + .avalon_st_tx_312_reset_n (sync_tx_rst_n), + .avalon_st_tx_clk_156 (core_clk_156), + .avalon_st_tx_156_reset_n (sync_tx_half_rst_n), + + .avalon_st_tx_156_ready (tx_out_ready[portid]), + .avalon_st_tx_156_valid (tx_out_valid[portid]), + .avalon_st_tx_156_data (tx_out_data[portid]), + .avalon_st_tx_156_error (tx_out_error[portid]), + .avalon_st_tx_156_startofpacket (tx_out_startofpacket[portid]), + .avalon_st_tx_156_endofpacket (tx_out_endofpacket[portid]), + .avalon_st_tx_156_empty (tx_out_empty[portid]), + + .avalon_st_tx_312_ready (mac_in_ready[portid]), + .avalon_st_tx_312_valid (mac_in_valid[portid]), + .avalon_st_tx_312_data (mac_in_data[portid]), + .avalon_st_tx_312_error (mac_in_error[portid]), + .avalon_st_tx_312_startofpacket (mac_in_startofpacket[portid]), + .avalon_st_tx_312_endofpacket (mac_in_endofpacket[portid]), + .avalon_st_tx_312_empty (mac_in_empty[portid]), + + //rx clock and reset + .avalon_st_rx_clk_312 (core_clk_312), + .avalon_st_rx_312_reset_n (sync_rx_rst_n), + .avalon_st_rx_clk_156 (core_clk_156), + .avalon_st_rx_156_reset_n (sync_rx_half_rst_n), + + .avalon_st_rx_312_ready (mac_out_ready[portid]), + .avalon_st_rx_312_valid (mac_out_valid[portid]), + .avalon_st_rx_312_data (mac_out_data[portid]), + .avalon_st_rx_312_error (mac_out_error[portid]), + .avalon_st_rx_312_startofpacket (mac_out_startofpacket[portid]), + .avalon_st_rx_312_endofpacket (mac_out_endofpacket[portid]), + .avalon_st_rx_312_empty (mac_out_empty[portid]), + + .avalon_st_rx_156_ready (rx_in_ready[portid]), + .avalon_st_rx_156_valid (rx_in_valid[portid]), + .avalon_st_rx_156_data (rx_in_data[portid]), + .avalon_st_rx_156_error (rx_in_error[portid]), + .avalon_st_rx_156_startofpacket (rx_in_startofpacket[portid]), + .avalon_st_rx_156_endofpacket (rx_in_endofpacket[portid]), + .avalon_st_rx_156_empty (rx_in_empty[portid]), + + // TX 1588 signals at 156mhz domain + .tx_egress_timestamp_request_valid_156 (1'b0), + .tx_egress_timestamp_request_fingerprint_156 (4'b0), + .tx_etstamp_ins_ctrl_timestamp_insert_156 (1'b0), + .tx_etstamp_ins_ctrl_timestamp_format_156 (1'b0), + .tx_etstamp_ins_ctrl_residence_time_update_156 (1'b0), + .tx_etstamp_ins_ctrl_ingress_timestamp_96b_156 (96'b0), + .tx_etstamp_ins_ctrl_ingress_timestamp_64b_156 (64'b0), + .tx_etstamp_ins_ctrl_residence_time_calc_format_156 (1'b0), + .tx_etstamp_ins_ctrl_checksum_zero_156 (1'b0), + .tx_etstamp_ins_ctrl_checksum_correct_156 (1'b0), + .tx_etstamp_ins_ctrl_offset_timestamp_156 (16'b0), + .tx_etstamp_ins_ctrl_offset_correction_field_156 (16'b0), + .tx_etstamp_ins_ctrl_offset_checksum_field_156 (16'b0), + .tx_etstamp_ins_ctrl_offset_checksum_correction_156 (16'b0), + + // TX 1588 signals at 312mhz domain + .tx_egress_timestamp_96b_data_312 (96'b0), + .tx_egress_timestamp_96b_valid_312 (1'b0), + .tx_egress_timestamp_96b_fingerprint_312 (4'b0), + .tx_egress_timestamp_64b_data_312 (64'b0), + .tx_egress_timestamp_64b_valid_312 (1'b0), + .tx_egress_timestamp_64b_fingerprint_312 (4'b0), + + //TX Status Signals + .avalon_st_txstatus_valid_156 (), + .avalon_st_txstatus_data_156 (), + .avalon_st_txstatus_error_156 (), + + .avalon_st_txstatus_valid_312 (1'b0), + .avalon_st_txstatus_data_312 (40'b0), + .avalon_st_txstatus_error_312 (7'b0), + + //TX PFC Status Signals + .avalon_st_tx_pfc_data_156 (avalon_st_tx_pfc_data_156[portid]), + .avalon_st_tx_pfc_status_valid_312 (1'b0), + .avalon_st_tx_pfc_status_data_312 (16'b0), + + // TX Pause Data + .avalon_st_tx_pause_data_156 (avalon_st_tx_pause_data_156[portid]), + + // Pause Quanta (For TX only variant) + .avalon_st_tx_pause_length_valid_156 (1'b0), + .avalon_st_tx_pause_length_data_156 (16'b0), + + // RX 1588 signals + .rx_ingress_timestamp_96b_valid_312 (1'b0), + .rx_ingress_timestamp_96b_data_312 (96'b0), + .rx_ingress_timestamp_64b_valid_312 (1'b0), + .rx_ingress_timestamp_64b_data_312 (64'b0), + + //RX Status Signals + .avalon_st_rxstatus_valid_312 (1'b0), + .avalon_st_rxstatus_data_312 (/*avalon_st_rxstatus_data_312*/), + .avalon_st_rxstatus_error_312 (7'b0), + + //RX PFC Status Signals + .avalon_st_rx_pfc_pause_data_312 (avalon_st_rx_pfc_data_sync[portid]), + .avalon_st_rx_pfc_status_valid_312 (1'b0), + .avalon_st_rx_pfc_status_data_312 (16'b0), + + // Pause Quanta (For RX only variant) + .avalon_st_rx_pause_length_valid_312 (1'b0), + .avalon_st_rx_pause_length_data_312 (16'b0), + + .tx_egress_timestamp_96b_data_156 (), + .tx_egress_timestamp_96b_valid_156 (), + .tx_egress_timestamp_96b_fingerprint_156 (), + .tx_egress_timestamp_64b_data_156 (), + .tx_egress_timestamp_64b_valid_156 (), + .tx_egress_timestamp_64b_fingerprint_156 (), + .tx_egress_timestamp_request_valid_312 (), + .tx_egress_timestamp_request_fingerprint_312 (), + .tx_etstamp_ins_ctrl_timestamp_insert_312 (), + .tx_etstamp_ins_ctrl_timestamp_format_312 (), + + .tx_etstamp_ins_ctrl_residence_time_update_312 (), + .tx_etstamp_ins_ctrl_ingress_timestamp_96b_312 (), + .tx_etstamp_ins_ctrl_ingress_timestamp_64b_312 (), + .tx_etstamp_ins_ctrl_residence_time_calc_format_312 (), + .tx_etstamp_ins_ctrl_checksum_zero_312 (), + .tx_etstamp_ins_ctrl_checksum_correct_312 (), + .tx_etstamp_ins_ctrl_offset_timestamp_312 (), + .tx_etstamp_ins_ctrl_offset_correction_field_312 (), + .tx_etstamp_ins_ctrl_offset_checksum_field_312 (), + .tx_etstamp_ins_ctrl_offset_checksum_correction_312 (), + + .avalon_st_tx_pfc_data_312 (avalon_st_tx_pfc_data_sync[portid]), + .avalon_st_tx_pfc_status_valid_156 (), + .avalon_st_tx_pfc_status_data_156 (), + .avalon_st_tx_pause_data_312 (avalon_st_pause_data_sync[portid]), + .avalon_st_tx_pause_length_valid_312 (), + .avalon_st_tx_pause_length_data_312 (), + .rx_ingress_timestamp_96b_valid_156 (), + .rx_ingress_timestamp_96b_data_156 (), + .rx_ingress_timestamp_64b_valid_156 (), + .rx_ingress_timestamp_64b_data_156 (), + + .avalon_st_rxstatus_valid_156 (), + .avalon_st_rxstatus_data_156 (/*avalon_st_rxstatus_data_156*/), + .avalon_st_rxstatus_error_156 (), + .avalon_st_rx_pfc_pause_data_156 (avalon_st_rx_pfc_pause_data_156[portid]), + .avalon_st_rx_pfc_status_valid_156 (), + .avalon_st_rx_pfc_status_data_156 (), + .avalon_st_rx_pause_length_valid_156 (), + .avalon_st_rx_pause_length_data_156 () + + ); + + // MAC+PHY Instance + altera_eth_10g_mac_base_r_wrap wrapper_inst ( + + .csr_clk (csr_clk_156), + .csr_rst_n (csr_rst_n_156), + .tx_clk_312 (core_clk_312), + .tx_clk_156 (core_clk_156), + .sync_tx_rst_n (sync_tx_rst_n), + .rx_clk_312 (core_clk_312), + .rx_clk_156 (core_clk_156), + .sync_rx_rst_n (sync_rx_rst_n), + .ref_clk_clk (ref_clk_clk), + + .avalon_st_tx_startofpacket (mac_in_startofpacket[portid]), + .avalon_st_tx_endofpacket (mac_in_endofpacket[portid]), + .avalon_st_tx_valid (mac_in_valid[portid]), + .avalon_st_tx_data (mac_in_data[portid]), + .avalon_st_tx_empty (mac_in_empty[portid]), + .avalon_st_tx_ready (mac_in_ready[portid]), + .avalon_st_tx_error (mac_in_error[portid]), + + .avalon_st_rx_startofpacket (mac_out_startofpacket[portid]), + .avalon_st_rx_endofpacket (mac_out_endofpacket[portid]), + .avalon_st_rx_valid (mac_out_valid[portid]), + .avalon_st_rx_data (mac_out_data[portid]), + .avalon_st_rx_empty (mac_out_empty[portid]), + .avalon_st_rx_ready (mac_out_ready[portid]), + .avalon_st_rx_error (mac_out_error[portid]), + + .avalon_st_pause_data (avalon_st_pause_data_sync[portid]), + .avalon_st_tx_pfc_gen_data (avalon_st_tx_pfc_data_sync[portid]), + .avalon_st_rx_pfc_pause_data (avalon_st_rx_pfc_data_sync[portid]), + .avalon_st_txstatus_valid (), + .avalon_st_txstatus_data (), + .avalon_st_txstatus_error (), + + .avalon_st_rxstatus_valid (avalon_st_rxstatus_valid_312[portid]), + .avalon_st_rxstatus_error (), + .avalon_st_rxstatus_data (avalon_st_rxstatus_data_312[portid]), + + .link_fault_status_xgmii_rx_data (), + + .tx_ready_export (tx_ready_export[portid]), + .rx_ready_export (rx_ready_export[portid]), + .block_lock (block_lock[portid]), + + .tx_serial_data (tx_serial_data[portid]), + .rx_serial_data (rx_serial_data[portid]), + + .mac_csr_read (mac_csr_read_32[portid]), + .mac_csr_write (mac_csr_write_32[portid]), + .mac_csr_readdata (mac_csr_readdata_32[portid]), + .mac_csr_writedata (mac_csr_writedata_32[portid]), + .mac_csr_waitrequest (mac_csr_waitrequest_32[portid]), + .mac_csr_address (mac_csr_address_32[portid]), + + .phy_csr_read (phy_csr_read[portid]), + .phy_csr_write (phy_csr_write[portid]), + .phy_csr_readdata (phy_csr_readdata[portid]), + .phy_csr_writedata (phy_csr_writedata[portid]), + .phy_csr_waitrequest (phy_csr_waitrequest[portid]), + .phy_csr_address (phy_csr_address[portid]), + + .tx_serial_clk (tx_serial_clk), + .atx_pll_locked (atx_pll_locked), + .hssi_stats (hssi_stats[portid]), + .final_channel_rst (final_channel_rst[portid]), + .final_reconfig_rst (final_reconfig_rst[portid]) + ); + + //RX Status signals sync + // Use the pr_freeze signal to mask the tx ready + resync #( + .SYNC_CHAIN_LENGTH (2), + .WIDTH (5), + .INIT_VALUE (0), + .NO_CUT (1) + ) rx_status_sync ( + .clk (core_clk_156), + .reset (sync_rx_half_rst), + .d (avalon_st_rxstatus_data_312[portid][39:35]), + .q (avalon_st_rxstatus_data_156[portid][0]) + ); + + //Sync Valid signal + resync #( + .SYNC_CHAIN_LENGTH (2), + .WIDTH (NUM_ETH_CHANNELS), + .INIT_VALUE (0), + .NO_CUT (1) + ) rx_status_valid ( + .clk (core_clk_156), + .reset (sync_rx_half_rst), + .d (avalon_st_rxstatus_valid_312[portid]), + .q (avalon_st_rxstatus_valid_156[portid]) + ); + +end //for loop end +endgenerate + +// +pll fpll_inst ( + .pll_refclk0 (ref_clk_clk), + .pll_cal_busy (), + .outclk_div2 (core_clk_156), // 156.25MHz clock + .outclk_div1 (core_clk_312), // 312.50MHz clock + .pll_locked (core_pll_locked) +); + +altera_xcvr_atx_pll_ip atx_pll_inst( + .pll_refclk0 (ref_clk_clk), + .tx_serial_clk (tx_serial_clk), + .pll_locked (atx_pll_locked) +); + +altera_reset_synchronizer # ( + .ASYNC_RESET (1), + .DEPTH (4) +) tx_reset_synchronizer_inst( + .clk (core_clk_312), + .reset_in (~tx_rst_n), + .reset_out (sync_tx_rst) +); + +altera_reset_synchronizer # ( + .ASYNC_RESET (1), + .DEPTH (4) +) rx_reset_synchronizer_inst( + .clk (core_clk_312), + .reset_in (~rx_rst_n), + .reset_out (sync_rx_rst) +); + +altera_reset_synchronizer # ( + .ASYNC_RESET (1), + .DEPTH (4) +) tx_half_clk_reset_synchronizer_inst( + .clk (core_clk_156), + .reset_in (~tx_rst_n), + .reset_out (sync_tx_half_rst) +); + +altera_reset_synchronizer # ( + .ASYNC_RESET (1), + .DEPTH (4) +) rx_half_clk_reset_synchronizer_inst( + .clk (core_clk_156), + .reset_in (~rx_rst_n), + .reset_out (sync_rx_half_rst) +); + +// Use the pr_freeze signal to mask the tx ready +resync #( + .SYNC_CHAIN_LENGTH (2), + .WIDTH (1), + .INIT_VALUE (0), + .NO_CUT (1) +) pr_freeze_sync ( + .clk (core_clk_312), + .reset (1'b0), + .d (pr_freeze), + .q (hssi_pr_freeze) +); + +endmodule diff --git a/ipss/hssi/s10/hssi_csr.sv b/ipss/hssi/s10/hssi_csr.sv new file mode 100755 index 0000000..cb83fff --- /dev/null +++ b/ipss/hssi/s10/hssi_csr.sv @@ -0,0 +1,564 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +//----------------------------------------------------------------------------- +// Description +//----------------------------------------------------------------------------- +// +// HSSI CSR module +// +//----------------------------------------------------------------------------- +import ofs_fim_eth_if_pkg::NUM_ETH_CHANNELS; +import hssi_csr_pkg::*; + +module hssi_csr #( + parameter END_OF_LIST = 1'b0, + parameter NEXT_DFH_OFFSET = 24'h01_0000, + + parameter CMD_W = 16, // User command width + parameter USER_ADDR_W = 16, // User address width + parameter AVMM_ADDR_W = 13, // AVMM address width + parameter DATA_W = 32, // Data width + parameter SIM = 0 + )( + ofs_fim_axi_mmio_if.slave csr_if, + input wire csr_clk, + input wire csr_rst, + input wire plls_locked, + // Avalon-MM Interface + output logic [AVMM_ADDR_W-1:0] o_avmm_addr, // AVMM address + output logic o_avmm_read, // AVMM read request + output logic o_avmm_write, // AVMM write request + output logic [DATA_W-1:0] o_avmm_writedata, // AVMM write data + input logic [DATA_W-1:0] i_avmm_readdata, // AVMM read data + input logic i_avmm_waitrequest, // AVMM wait request + input hssi_stats_struct_t hssi_stats[NUM_ETH_CHANNELS-1:0], + output wire [NUM_ETH_CHANNELS-1:0] final_channel_rst, + output wire [7:0] final_reconfig_rst +); + +import ofs_fim_cfg_pkg::*; +import ofs_csr_pkg::*; + + + +//------------------------------------- +// Number of feature and register +//------------------------------------- + +// To add a register, append a new register ID to e_csr_offset +// The register address offset is calculated in CALC_CSR_OFFSET() in 8 bytes increment +// based on the position of the register ID in e_csr_offset. +// The calculated offset is stored in CSR_OFFSET and can be indexed using the register ID +enum { + HSSI_ETH_DFH, // 'h0 + HSSI_CAPABILITY, // 'h8 + HSSI_CTRL, // 'h10 + HSSI_STAT0, // 'h18 + HSSI_STAT1, // 'h20 + HSSI_RCFG_CMD, // 'h28 + HSSI_RCFG_DATA, // 'h30 + HSSI_SCRATCHPAD, // 'h38 + HSSI_MAX_OFFSET +} e_csr_id; + +localparam CSR_NUM_REG = HSSI_MAX_OFFSET; +localparam CSR_REG_ADDR_WIDTH = $clog2(CSR_NUM_REG) + 3; + +localparam MAX_CSR_REG_NUM = 512; // 4KB address space - 512 x 8B register +localparam CSR_ADDR_WIDTH = $clog2(MAX_CSR_REG_NUM) + 3; +localparam ADDR_WIDTH = ofs_fim_cfg_pkg::MMIO_ADDR_WIDTH; +localparam DATA_WIDTH = ofs_fim_cfg_pkg::MMIO_DATA_WIDTH; +localparam WSTRB_WIDTH = (DATA_WIDTH/8); + +//------------------------------------- +// Register address +//------------------------------------- +function automatic bit [CSR_NUM_REG-1:0][ADDR_WIDTH-1:0] CALC_CSR_OFFSET (); + bit [31:0] offset; + for (int i=0; i + + + Altera Corporation + address_decode + address_decode + 1.0 + + + + $${FILENAME} + $${FILENAME} + 1.0 + + + System + QsysPro + + + + + board + Board + Unknown + + + bonusData + bonusData + bonusData +{ + element $system + { + } + element clk_csr + { + datum _sortIndex + { + value = "5"; + type = "int"; + } + } + element master_0 + { + datum _sortIndex + { + value = "7"; + type = "int"; + } + } + element merlin_master_translator_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } + element mm_to_mac_0 + { + datum _sortIndex + { + value = "1"; + type = "int"; + } + } + element mm_to_mac_0.avalon_universal_slave_0 + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + } + element mm_to_phy_0 + { + datum _sortIndex + { + value = "2"; + type = "int"; + } + } + element mm_to_phy_0.avalon_universal_slave_0 + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "32768"; + type = "String"; + } + } + element rx_xcvr_clk + { + datum _sortIndex + { + value = "3"; + type = "int"; + } + } + element tx_xcvr_clk + { + datum _sortIndex + { + value = "4"; + type = "int"; + } + } + element tx_xcvr_half_clk + { + datum _sortIndex + { + value = "6"; + type = "int"; + } + } +} + + + + designId + designId + + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + fabricMode + fabricMode + QSYS + + + generateLegacySim + generateLegacySim + false + + + generationId + Generation Id + 0 + + + globalResetBus + Global reset + false + + + hdlLanguage + hdlLanguage + VERILOG + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + + + + sopcBorderPoints + Use SOPC Builder port naming + false + + + systemHash + systemHash + 0 + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk_csr</key> + <value> + <connectionPointName>clk_csr</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>merlin_master_translator_0_avalon_anti_master_0</key> + <value> + <connectionPointName>merlin_master_translator_0_avalon_anti_master_0</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='merlin_master_translator_0.avalon_anti_master_0' start='0x0' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>18</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>rx_xcvr_clk</key> + <value> + <connectionPointName>rx_xcvr_clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>tx_xcvr_clk</key> + <value> + <connectionPointName>tx_xcvr_clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>tx_xcvr_half_clk</key> + <value> + <connectionPointName>tx_xcvr_half_clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + systemScripts + systemScripts + + + + testBenchDutName + Use Test Bench Naming Pattern + + + + timeStamp + timeStamp + 0 + + + useTestBenchNamingPattern + Use Test Bench Naming Pattern + false + + + + + + + + + Altera Corporation + clk_csr + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk_in</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>clk</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>125000000</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>reset</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk_in</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>clk_out</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>clk_in</value> + </entry> + <entry> + <key>clockRate</key> + <value>125000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>true</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>reset_n_out</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>clock_source</className> + <displayName>Clock Source</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>inputClockFrequency</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk_in</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>125000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>clk_in</key> + <value> + <connectionPointName>clk_in</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clk_in</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>clk</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>125000000</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>reset</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk_in</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>clk_out</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>clk_in</value> + </entry> + <entry> + <key>clockRate</key> + <value>125000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>true</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>reset_n_out</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>address_decode_clk_csr</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>address_decode_clk_csr</fileSetName> + <fileSetFixedName>address_decode_clk_csr</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_clk_csr</fileSetName> + <fileSetFixedName>address_decode_clk_csr</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_clk_csr</fileSetName> + <fileSetFixedName>address_decode_clk_csr</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_clk_csr</fileSetName> + <fileSetFixedName>address_decode_clk_csr</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/address_decode/address_decode_clk_csr.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + master_0 + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk_reset_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>master_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>master_reset_reset</name> + <role>reset</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>none</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>master</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>master_address</name> + <role>address</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_byteenable</name> + <role>byteenable</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>debug.controlledBy</key> + <value>in_stream</value> + </entry> + <entry> + <key>debug.providesServices</key> + <value>master</value> + </entry> + <entry> + <key>debug.typeName</key> + <value>altera_jtag_avalon_master.master</value> + </entry> + <entry> + <key>debug.visible</key> + <value>true</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>clk_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_jtag_avalon_master</className> + <version>19.1</version> + <displayName>JTAG to Avalon Master Bridge Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>AUTO_DEVICE</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>AUTO_DEVICE_FAMILY</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE_FAMILY</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>AUTO_DEVICE_SPEEDGRADE</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>DEVICE_SPEEDGRADE</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>COMPONENT_CLOCK</parameterName> + <parameterType>java.lang.Integer</parameterType> + <systemInfoArgs>clock</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk_reset_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>master_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>master_reset_reset</name> + <role>reset</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>none</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>master</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>master_address</name> + <role>address</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_byteenable</name> + <role>byteenable</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>debug.controlledBy</key> + <value>in_stream</value> + </entry> + <entry> + <key>debug.providesServices</key> + <value>master</value> + </entry> + <entry> + <key>debug.typeName</key> + <value>altera_jtag_avalon_master.master</value> + </entry> + <entry> + <key>debug.visible</key> + <value>true</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>clk_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>address_decode_master_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>address_decode_master_0</fileSetName> + <fileSetFixedName>address_decode_master_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_master_0</fileSetName> + <fileSetFixedName>address_decode_master_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_master_0</fileSetName> + <fileSetFixedName>address_decode_master_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_master_0</fileSetName> + <fileSetFixedName>address_decode_master_0</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/address_decode/address_decode_master_0.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap> + <entry> + <key>debug.hostConnection</key> + <value>type jtag id 110:132</value> + </entry> + </assignmentValueMap> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + merlin_master_translator_0 + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>avalon_universal_master_0</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>uav_address</name> + <role>address</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_burstcount</name> + <role>burstcount</role> + <direction>Output</direction> + <width>10</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_byteenable</name> + <role>byteenable</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_lock</name> + <role>lock</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_debugaccess</name> + <role>debugaccess</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>merlin.flow.avalon_anti_master_0</key> + <value>avalon_anti_master_0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>avalon_anti_master_0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>av_address</name> + <role>address</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + <entry> + <key>merlin.flow.avalon_universal_master_0</key> + <value>avalon_universal_master_0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>262144</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_merlin_master_translator</className> + <version>19.1</version> + <displayName>Avalon-MM Master Translator Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>avalon_anti_master_0</key> + <value> + <connectionPointName>avalon_anti_master_0</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='avalon_anti_master_0' start='0x0' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>18</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>avalon_universal_master_0</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>uav_address</name> + <role>address</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_burstcount</name> + <role>burstcount</role> + <direction>Output</direction> + <width>10</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_byteenable</name> + <role>byteenable</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_lock</name> + <role>lock</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_debugaccess</name> + <role>debugaccess</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>merlin.flow.avalon_anti_master_0</key> + <value>avalon_anti_master_0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>avalon_anti_master_0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>av_address</name> + <role>address</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + <entry> + <key>merlin.flow.avalon_universal_master_0</key> + <value>avalon_universal_master_0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>262144</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>address_decode_merlin_master_translator_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>address_decode_merlin_master_translator_0</fileSetName> + <fileSetFixedName>address_decode_merlin_master_translator_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_merlin_master_translator_0</fileSetName> + <fileSetFixedName>address_decode_merlin_master_translator_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_merlin_master_translator_0</fileSetName> + <fileSetFixedName>address_decode_merlin_master_translator_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_merlin_master_translator_0</fileSetName> + <fileSetFixedName>address_decode_merlin_master_translator_0</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/address_decode/address_decode_merlin_master_translator_0.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + mm_to_mac_0 + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>avalon_universal_slave_0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>uav_address</name> + <role>address</role> + <direction>Input</direction> + <width>15</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_burstcount</name> + <role>burstcount</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_readdatavalid</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_lock</name> + <role>lock</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_debugaccess</name> + <role>debugaccess</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + <entry> + <key>merlin.flow.avalon_anti_slave_0</key> + <value>avalon_anti_slave_0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>32768</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>32768</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>64</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>avalon_anti_slave_0</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>av_address</name> + <role>address</role> + <direction>Output</direction> + <width>13</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_merlin_slave_translator</className> + <version>19.1</version> + <displayName>Avalon-MM Slave Translator Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>avalon_universal_slave_0</key> + <value> + <connectionPointName>avalon_universal_slave_0</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='avalon_universal_slave_0' start='0x0' end='0x8000' datawidth='32' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>15</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>125000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>avalon_universal_slave_0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>uav_address</name> + <role>address</role> + <direction>Input</direction> + <width>15</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_burstcount</name> + <role>burstcount</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_readdatavalid</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_lock</name> + <role>lock</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_debugaccess</name> + <role>debugaccess</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + <entry> + <key>merlin.flow.avalon_anti_slave_0</key> + <value>avalon_anti_slave_0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>32768</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>32768</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>64</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>avalon_anti_slave_0</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>av_address</name> + <role>address</role> + <direction>Output</direction> + <width>13</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>address_decode_mm_to_mac</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>address_decode_mm_to_mac</fileSetName> + <fileSetFixedName>address_decode_mm_to_mac</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_mm_to_mac</fileSetName> + <fileSetFixedName>address_decode_mm_to_mac</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_mm_to_mac</fileSetName> + <fileSetFixedName>address_decode_mm_to_mac</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_mm_to_mac</fileSetName> + <fileSetFixedName>address_decode_mm_to_mac</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/address_decode/address_decode_mm_to_mac.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + mm_to_phy_0 + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>avalon_universal_slave_0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>uav_address</name> + <role>address</role> + <direction>Input</direction> + <width>13</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_burstcount</name> + <role>burstcount</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_readdatavalid</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_lock</name> + <role>lock</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_debugaccess</name> + <role>debugaccess</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + <entry> + <key>merlin.flow.avalon_anti_slave_0</key> + <value>avalon_anti_slave_0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8192</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>8192</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>64</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>avalon_anti_slave_0</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>av_address</name> + <role>address</role> + <direction>Output</direction> + <width>11</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_merlin_slave_translator</className> + <version>19.1</version> + <displayName>Avalon-MM Slave Translator Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>1</parameterDefaultValue> + <parameterName>CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>avalon_universal_slave_0</key> + <value> + <connectionPointName>avalon_universal_slave_0</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='avalon_universal_slave_0' start='0x0' end='0x2000' datawidth='32' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>13</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>125000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>avalon_universal_slave_0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>uav_address</name> + <role>address</role> + <direction>Input</direction> + <width>13</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_burstcount</name> + <role>burstcount</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_readdatavalid</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_lock</name> + <role>lock</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_debugaccess</name> + <role>debugaccess</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + <entry> + <key>merlin.flow.avalon_anti_slave_0</key> + <value>avalon_anti_slave_0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8192</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>8192</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>64</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>avalon_anti_slave_0</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>av_address</name> + <role>address</role> + <direction>Output</direction> + <width>11</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>address_decode_mm_to_phy</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>address_decode_mm_to_phy</fileSetName> + <fileSetFixedName>address_decode_mm_to_phy</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_mm_to_phy</fileSetName> + <fileSetFixedName>address_decode_mm_to_phy</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_mm_to_phy</fileSetName> + <fileSetFixedName>address_decode_mm_to_phy</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_mm_to_phy</fileSetName> + <fileSetFixedName>address_decode_mm_to_phy</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/address_decode/address_decode_mm_to_phy.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + rx_xcvr_clk + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk_in</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>clk</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>312500000</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>reset</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>clk_out</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>clk_in</value> + </entry> + <entry> + <key>clockRate</key> + <value>312500000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>true</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>reset_n_out</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>clock_source</className> + <displayName>Clock Source</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>inputClockFrequency</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk_in</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>312500000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>clk_in</key> + <value> + <connectionPointName>clk_in</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clk_in</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>clk</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>312500000</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>reset</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>clk_out</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>clk_in</value> + </entry> + <entry> + <key>clockRate</key> + <value>312500000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>true</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>reset_n_out</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>address_decode_rx_xcvr_clk</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>address_decode_rx_xcvr_clk</fileSetName> + <fileSetFixedName>address_decode_rx_xcvr_clk</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_rx_xcvr_clk</fileSetName> + <fileSetFixedName>address_decode_rx_xcvr_clk</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_rx_xcvr_clk</fileSetName> + <fileSetFixedName>address_decode_rx_xcvr_clk</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_rx_xcvr_clk</fileSetName> + <fileSetFixedName>address_decode_rx_xcvr_clk</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/address_decode/address_decode_rx_xcvr_clk.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + tx_xcvr_clk + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk_in</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>clk</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>312500000</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>reset</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>clk_out</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>clk_in</value> + </entry> + <entry> + <key>clockRate</key> + <value>312500000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>true</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>reset_n_out</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>clock_source</className> + <displayName>Clock Source</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>inputClockFrequency</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk_in</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>312500000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>clk_in</key> + <value> + <connectionPointName>clk_in</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clk_in</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>clk</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>312500000</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>reset</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>clk_out</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>clk_in</value> + </entry> + <entry> + <key>clockRate</key> + <value>312500000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>true</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>reset_n_out</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>address_decode_tx_xcvr_clk</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>address_decode_tx_xcvr_clk</fileSetName> + <fileSetFixedName>address_decode_tx_xcvr_clk</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_tx_xcvr_clk</fileSetName> + <fileSetFixedName>address_decode_tx_xcvr_clk</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_tx_xcvr_clk</fileSetName> + <fileSetFixedName>address_decode_tx_xcvr_clk</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_tx_xcvr_clk</fileSetName> + <fileSetFixedName>address_decode_tx_xcvr_clk</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/address_decode/address_decode_tx_xcvr_clk.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + tx_xcvr_half_clk + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk_in</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>clk</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>156250000</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>reset</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>clk_out</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>clk_in</value> + </entry> + <entry> + <key>clockRate</key> + <value>156250000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>true</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>reset_n_out</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>clock_source</className> + <displayName>Clock Source</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>inputClockFrequency</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk_in</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>156250000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>clk_in</key> + <value> + <connectionPointName>clk_in</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clk_in</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>clk</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>156250000</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>reset</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>clk_out</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>clk_in</value> + </entry> + <entry> + <key>clockRate</key> + <value>156250000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>true</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>reset_n_out</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>address_decode_tx_xcvr_half_clk</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>address_decode_tx_xcvr_half_clk</fileSetName> + <fileSetFixedName>address_decode_tx_xcvr_half_clk</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_tx_xcvr_half_clk</fileSetName> + <fileSetFixedName>address_decode_tx_xcvr_half_clk</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_tx_xcvr_half_clk</fileSetName> + <fileSetFixedName>address_decode_tx_xcvr_half_clk</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>address_decode_tx_xcvr_half_clk</fileSetName> + <fileSetFixedName>address_decode_tx_xcvr_half_clk</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/address_decode/address_decode_tx_xcvr_half_clk.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Intel Corporation + addressMap + addressMap + 1.0 + + + mm_to_phy_0.avalon_universal_slave_0 + + + + mm_to_mac_0.avalon_universal_slave_0 + + + + master_0.master + + + + 0x0000_8000 + + + + + mm_to_mac_0.avalon_universal_slave_0 + + + + mm_to_phy_0.avalon_universal_slave_0 + + + + merlin_master_translator_0.avalon_universal_master_0 + + + + 0x0000_0000 + + + + + mm_to_mac_0.avalon_anti_slave_0 + + + + + mm_to_phy_0.avalon_anti_slave_0 + + + + + + + master_0.master + + + mm_to_phy_0.avalon_universal_slave_0 + 0x0000_8000 + 0x0000_2000 + + + mm_to_mac_0.avalon_universal_slave_0 + 0x0000_0000 + 0x0000_8000 + + + + + merlin_master_translator_0.avalon_universal_master_0 + + + mm_to_mac_0.avalon_universal_slave_0 + 0x0000_0000 + 0x0000_8000 + + + mm_to_phy_0.avalon_universal_slave_0 + 0x0000_8000 + 0x0000_2000 + + + + + + + + false + false + + \ No newline at end of file diff --git a/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_clk_csr.ip b/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_clk_csr.ip new file mode 100755 index 0000000..00053b8 --- /dev/null +++ b/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_clk_csr.ip @@ -0,0 +1,563 @@ + + + + Altera Corporation + address_decode_clk_csr + clk_csr + 23.1 + + + clk_in + + + + + + + + clk + + + in_clk + + + + + + + + + clockRate + Clock rate + 125000000 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + qsys.ui.export_name + clk + + + + + + + clk_in_reset + + + + + + + + reset_n + + + reset_n + + + + + + + + + associatedClock + Associated clock + clk_in + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + + + qsys.ui.export_name + reset + + + + + + + clk + + + + + + + + clk + + + clk_out + + + + + + + + + associatedDirectClock + Associated direct clock + clk_in + + + clockRate + Clock rate + 125000000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + true + + + ptfSchematicName + PTF schematic name + + + + + + clk_reset + + + + + + + + reset_n + + + reset_n_out + + + + + + + + + associatedClock + Associated clock + clk + + + associatedDirectReset + Associated direct reset + clk_in_reset + + + associatedResetSinks + Associated reset sinks + clk_in_reset + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + clock_source + + QUARTUS_SYNTH + + + + + + in_clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + reset_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + clk_out + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + reset_n_out + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Altera Corporation + address_decode_clk_csr + clock_source + 23.1 + + + + + clockFrequency + Clock frequency + 125000000 + + + clockFrequencyKnown + Clock frequency is known + true + + + inputClockFrequency + inputClockFrequency + 0 + + + resetSynchronousEdges + Reset synchronous edges + DEASSERT + + + + + + + board + Board + Unknown + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element address_decode_clk_csr + { + datum _originalVersion + { + value = "16.1"; + type = "String"; + } + } + element clk_csr + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + true + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clk_in</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>clk</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>125000000</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>reset</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk_in</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>clk_out</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>clk_in</value> + </entry> + <entry> + <key>clockRate</key> + <value>125000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>true</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>reset_n_out</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>125000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>clk_in</key> + <value> + <connectionPointName>clk_in</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_master_0.ip b/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_master_0.ip new file mode 100755 index 0000000..887b1b6 --- /dev/null +++ b/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_master_0.ip @@ -0,0 +1,1062 @@ + + + + Intel Corporation + address_decode_master_0 + address_decode_master_0 + 19.1 + + + clk + + + + + + + + clk + + + clk_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + clk_reset + + + + + + + + reset + + + clk_reset_reset + + + + + + + + + associatedClock + Associated clock + + + + synchronousEdges + Synchronous edges + NONE + + + + + master_reset + + + + + + + + reset + + + master_reset_reset + + + + + + + + + associatedClock + Associated clock + + + + associatedDirectReset + Associated direct reset + + + + associatedResetSinks + Associated reset sinks + none + + + synchronousEdges + Synchronous edges + NONE + + + + + master + + + + + + + + address + + + master_address + + + + + readdata + + + master_readdata + + + + + read + + + master_read + + + + + write + + + master_write + + + + + writedata + + + master_writedata + + + + + waitrequest + + + master_waitrequest + + + + + readdatavalid + + + master_readdatavalid + + + + + byteenable + + + master_byteenable + + + + + + + + + adaptsTo + Adapts to + + + + addressGroup + Address group + 0 + + + addressUnits + Address units + SYMBOLS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + clk + + + associatedReset + Associated reset + clk_reset + + + bitsPerSymbol + Bits per symbol + 8 + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + dBSBigEndian + dBS big endian + false + + + doStreamReads + Use flow control for read transfers + false + + + doStreamWrites + Use flow control for write transfers + false + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isAsynchronous + Is asynchronous + false + + + isBigEndian + Is big endian + false + + + isReadable + Is readable + false + + + isWriteable + Is writeable + false + + + linewrapBursts + Linewrap bursts + false + + + maxAddressWidth + Maximum address width + 32 + + + maximumPendingReadTransactions + Maximum pending read transactions + 0 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + readLatency + Read latency + 0 + + + readWaitTime + Read wait + 1 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + waitrequestAllowance + Waitrequest allowance + 0 + + + writeWaitTime + Write wait + 0 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + + + + + debug.controlledBy + in_stream + + + debug.providesServices + master + + + debug.typeName + altera_jtag_avalon_master.master + + + debug.visible + true + + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_jtag_avalon_master + + QUARTUS_SYNTH + + + + + + clk_clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + clk_reset_reset + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + master_reset_reset + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + master_address + + out + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + master_readdata + + in + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + master_read + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + master_write + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + master_writedata + + out + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + master_waitrequest + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + master_readdatavalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + master_byteenable + + out + + + 0 + 3 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + address_decode_master_0 + altera_jtag_avalon_master + 19.1 + + + + + USE_PLI + Use Simulation Link Mode + 0 + + + PLI_PORT + Simulation Link Server Port + 50000 + + + COMPONENT_CLOCK + COMPONENT_CLOCK + 0 + + + FAST_VER + Enhanced transaction master + 0 + + + FIFO_DEPTHS + FIFO depth + 2 + + + AUTO_DEVICE_FAMILY + Auto DEVICE_FAMILY + Stratix 10 + + + AUTO_DEVICE + Auto DEVICE + 1SX280HN2F43E2VG + + + AUTO_DEVICE_SPEEDGRADE + Auto DEVICE_SPEEDGRADE + 2 + + + + + + + debug.hostConnection + type jtag id 110:132 + + + + + + + board + Board + Unknown + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element address_decode_master_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + true + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk_reset_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>master_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>master_reset_reset</name> + <role>reset</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>none</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>master</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>master_address</name> + <role>address</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>master_byteenable</name> + <role>byteenable</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>debug.controlledBy</key> + <value>in_stream</value> + </entry> + <entry> + <key>debug.providesServices</key> + <value>master</value> + </entry> + <entry> + <key>debug.typeName</key> + <value>altera_jtag_avalon_master.master</value> + </entry> + <entry> + <key>debug.visible</key> + <value>true</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>clk_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_merlin_master_translator_0.ip b/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_merlin_master_translator_0.ip new file mode 100755 index 0000000..04d8242 --- /dev/null +++ b/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_merlin_master_translator_0.ip @@ -0,0 +1,1901 @@ + + + + Intel Corporation + address_decode_merlin_master_translator_0 + merlin_master_translator_0 + 19.2 + + + clk + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset + + + reset + + + + + + + + + associatedClock + Associated clock + clk + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + avalon_universal_master_0 + + + + + + + + address + + + uav_address + + + + + burstcount + + + uav_burstcount + + + + + read + + + uav_read + + + + + write + + + uav_write + + + + + waitrequest + + + uav_waitrequest + + + + + readdatavalid + + + uav_readdatavalid + + + + + byteenable + + + uav_byteenable + + + + + readdata + + + uav_readdata + + + + + writedata + + + uav_writedata + + + + + lock + + + uav_lock + + + + + debugaccess + + + uav_debugaccess + + + + + + + + + adaptsTo + Adapts to + + + + addressGroup + Address group + 0 + + + addressUnits + Address units + SYMBOLS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + clk + + + associatedReset + Associated reset + reset + + + bitsPerSymbol + Bits per symbol + 8 + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + SYMBOLS + + + constantBurstBehavior + Constant burst behavior + false + + + dBSBigEndian + dBS big endian + false + + + doStreamReads + Use flow control for read transfers + false + + + doStreamWrites + Use flow control for write transfers + false + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isAsynchronous + Is asynchronous + false + + + isBigEndian + Is big endian + false + + + isReadable + Is readable + false + + + isWriteable + Is writeable + false + + + linewrapBursts + Linewrap bursts + false + + + maxAddressWidth + Maximum address width + 32 + + + maximumPendingReadTransactions + Maximum pending read transactions + 0 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + readLatency + Read latency + 0 + + + readWaitTime + Read wait + 0 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + waitrequestAllowance + Waitrequest allowance + 0 + + + writeWaitTime + Write wait + 0 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + + + + + merlin.flow.avalon_anti_master_0 + avalon_anti_master_0 + + + + + + + avalon_anti_master_0 + + + + + + + + address + + + av_address + + + + + waitrequest + + + av_waitrequest + + + + + read + + + av_read + + + + + readdata + + + av_readdata + + + + + write + + + av_write + + + + + writedata + + + av_writedata + + + + + + + + + addressAlignment + Agent addressing + DYNAMIC + + + addressGroup + Address group + 0 + + + addressSpan + Address span + 262144 + + + addressUnits + Address units + WORDS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + clk + + + associatedReset + Associated reset + reset + + + bitsPerSymbol + Bits per symbol + 8 + + + bridgedAddressOffset + Bridged Address Offset + 0 + + + bridgesToMaster + Bridges to host + + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + explicitAddressSpan + Explicit address span + 0 + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isBigEndian + Big endian + false + + + isFlash + Flash memory + false + + + isMemoryDevice + Memory device + false + + + isNonVolatileStorage + Non-volatile storage + false + + + linewrapBursts + Linewrap bursts + false + + + maximumPendingReadTransactions + Maximum pending read transactions + 0 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + minimumUninterruptedRunLength + Minimum uninterrupted run length + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + printableDevice + Can receive stdout/stderr + false + + + readLatency + Read latency + 0 + + + readWaitStates + Read wait states + 0 + + + readWaitTime + Read wait + 0 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + transparentBridge + Transparent bridge + false + + + waitrequestAllowance + Waitrequest allowance + 0 + + + wellBehavedWaitrequest + Well-behaved waitrequest + false + + + writeLatency + Write latency + 0 + + + writeWaitStates + Write wait states + 0 + + + writeWaitTime + Write wait + 0 + + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + merlin.flow.avalon_universal_master_0 + avalon_universal_master_0 + + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_merlin_master_translator + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + reset + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + uav_address + + out + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + uav_burstcount + + out + + + 0 + 9 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + uav_read + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + uav_write + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + uav_waitrequest + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + uav_readdatavalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + uav_byteenable + + out + + + 0 + 3 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + uav_readdata + + in + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + uav_writedata + + out + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + uav_lock + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + uav_debugaccess + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + av_address + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + av_waitrequest + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + av_read + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + av_readdata + + out + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + av_write + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + av_writedata + + in + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + address_decode_merlin_master_translator_0 + altera_merlin_master_translator + 19.2 + + + + + AV_ADDRESS_W + Component address width + 16 + + + AV_DATA_W + Component Data width + 32 + + + AV_BURSTCOUNT_W + Component burstcount width + 1 + + + AV_BYTEENABLE_W + Component byteenable width + 4 + + + UAV_ADDRESS_W + Network address width + 32 + + + UAV_BURSTCOUNT_W + Network burstcount width + 10 + + + AV_READLATENCY + readLatency + 0 + + + AV_WRITE_WAIT + writeWaitTime + 0 + + + AV_READ_WAIT + readWaitTime + 0 + + + AV_DATA_HOLD + Hold time + 0 + + + AV_SETUP_WAIT + setupTime + 0 + + + USE_READDATA + Use readdata + 1 + + + USE_WRITEDATA + Use writedata + 1 + + + USE_READ + Use read + 1 + + + USE_WRITE + Use write + 1 + + + USE_BEGINBURSTTRANSFER + Use beginbursttransfer + 0 + + + USE_BEGINTRANSFER + Use begintransfer + 0 + + + USE_BYTEENABLE + Use byteenable + 0 + + + USE_CHIPSELECT + Use chipselect + 0 + + + USE_ADDRESS + Use address + 1 + + + USE_BURSTCOUNT + Use burstcount + 0 + + + USE_DEBUGACCESS + Use debugaccess + 0 + + + USE_CLKEN + Use network clken + 0 + + + USE_READDATAVALID + Use readdatavalid + 0 + + + USE_WAITREQUEST + Use waitrequest + 1 + + + USE_LOCK + Use lock + 0 + + + USE_READRESPONSE + Use readresponse + 0 + + + USE_WRITERESPONSE + Use writeresponse + 0 + + + AV_SYMBOLS_PER_WORD + Symbols per word + 4 + + + AV_ADDRESS_SYMBOLS + Address symbols + 0 + + + AV_BURSTCOUNT_SYMBOLS + Burstcount symbols + 0 + + + AV_CONSTANT_BURST_BEHAVIOR + Component constantBurstBehavior + 0 + + + UAV_CONSTANT_BURST_BEHAVIOR + Network constantBurstBehavior + 0 + + + AV_LINEWRAPBURSTS + linewrapBursts + 0 + + + AV_MAX_PENDING_READ_TRANSACTIONS + maxPendingReadTransactions + 0 + + + AV_BURSTBOUNDARIES + burstOnBurstBoundariesOnly + 0 + + + AV_INTERLEAVEBURSTS + interleaveBursts + 0 + + + AV_BITS_PER_SYMBOL + Bits/symbol + 8 + + + AV_ISBIGENDIAN + isBigEndian + 0 + + + AV_ADDRESSGROUP + Component address group + 0 + + + UAV_ADDRESSGROUP + Network address group + 0 + + + AV_REGISTEROUTGOINGSIGNALS + registerOutgoingSignals + 0 + + + AV_REGISTERINCOMINGSIGNALS + registerIncomingSignals + 0 + + + AV_ALWAYSBURSTMAXBURST + Always burst max-burst + 0 + + + SYNC_RESET + Use synchronous resets + 0 + + + WAITREQUEST_ALLOWANCE + Waitrequest Allowance + 0 + + + USE_OUTPUTENABLE + Use outputenable + 0 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element address_decode_merlin_master_translator_0 + { + datum _originalVersion + { + value = "16.1"; + type = "String"; + } + } + element merlin_master_translator_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + true + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>avalon_universal_master_0</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>uav_address</name> + <role>address</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_burstcount</name> + <role>burstcount</role> + <direction>Output</direction> + <width>10</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_byteenable</name> + <role>byteenable</role> + <direction>Output</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_lock</name> + <role>lock</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_debugaccess</name> + <role>debugaccess</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>merlin.flow.avalon_anti_master_0</key> + <value>avalon_anti_master_0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>avalon_anti_master_0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>av_address</name> + <role>address</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + <entry> + <key>merlin.flow.avalon_universal_master_0</key> + <value>avalon_universal_master_0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>262144</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>avalon_anti_master_0</key> + <value> + <connectionPointName>avalon_anti_master_0</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='avalon_anti_master_0' start='0x0' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>18</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_mm_to_mac.ip b/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_mm_to_mac.ip new file mode 100755 index 0000000..3683cd1 --- /dev/null +++ b/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_mm_to_mac.ip @@ -0,0 +1,1944 @@ + + + + Intel Corporation + address_decode_mm_to_mac + mm_to_mac + 19.1 + + + clk + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset + + + reset + + + + + + + + + associatedClock + Associated clock + clk + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + avalon_universal_slave_0 + + + + + + + + address + + + uav_address + + + + + burstcount + + + uav_burstcount + + + + + read + + + uav_read + + + + + write + + + uav_write + + + + + waitrequest + + + uav_waitrequest + + + + + readdatavalid + + + uav_readdatavalid + + + + + byteenable + + + uav_byteenable + + + + + readdata + + + uav_readdata + + + + + writedata + + + uav_writedata + + + + + lock + + + uav_lock + + + + + debugaccess + + + uav_debugaccess + + + + + + + + + addressAlignment + Agent addressing + DYNAMIC + + + addressGroup + Address group + 0 + + + addressSpan + Address span + 32768 + + + addressUnits + Address units + SYMBOLS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + clk + + + associatedReset + Associated reset + reset + + + bitsPerSymbol + Bits per symbol + 8 + + + bridgedAddressOffset + Bridged Address Offset + 0 + + + bridgesToMaster + Bridges to host + + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + SYMBOLS + + + constantBurstBehavior + Constant burst behavior + false + + + explicitAddressSpan + Explicit address span + 32768 + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isBigEndian + Big endian + false + + + isFlash + Flash memory + false + + + isMemoryDevice + Memory device + false + + + isNonVolatileStorage + Non-volatile storage + false + + + linewrapBursts + Linewrap bursts + false + + + maximumPendingReadTransactions + Maximum pending read transactions + 64 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + minimumUninterruptedRunLength + Minimum uninterrupted run length + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + printableDevice + Can receive stdout/stderr + false + + + readLatency + Read latency + 0 + + + readWaitStates + Read wait states + 0 + + + readWaitTime + Read wait + 0 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + transparentBridge + Transparent bridge + false + + + waitrequestAllowance + Waitrequest allowance + 0 + + + wellBehavedWaitrequest + Well-behaved waitrequest + false + + + writeLatency + Write latency + 0 + + + writeWaitStates + Write wait states + 0 + + + writeWaitTime + Write wait + 0 + + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + merlin.flow.avalon_anti_slave_0 + avalon_anti_slave_0 + + + + + + + avalon_anti_slave_0 + + + + + + + + address + + + av_address + + + + + write + + + av_write + + + + + read + + + av_read + + + + + readdata + + + av_readdata + + + + + writedata + + + av_writedata + + + + + waitrequest + + + av_waitrequest + + + + + + + + + adaptsTo + Adapts to + + + + addressGroup + Address group + 0 + + + addressUnits + Address units + WORDS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + clk + + + associatedReset + Associated reset + reset + + + bitsPerSymbol + Bits per symbol + 8 + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + dBSBigEndian + dBS big endian + false + + + doStreamReads + Use flow control for read transfers + false + + + doStreamWrites + Use flow control for write transfers + false + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isAsynchronous + Is asynchronous + false + + + isBigEndian + Is big endian + false + + + isReadable + Is readable + false + + + isWriteable + Is writeable + false + + + linewrapBursts + Linewrap bursts + false + + + maxAddressWidth + Maximum address width + 32 + + + maximumPendingReadTransactions + Maximum pending read transactions + 0 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + readLatency + Read latency + 0 + + + readWaitTime + Read wait + 1 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + waitrequestAllowance + Waitrequest allowance + 0 + + + writeWaitTime + Write wait + 0 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_merlin_slave_translator + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + reset + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + uav_address + + in + + + 0 + 14 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + uav_burstcount + + in + + + 0 + 3 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + uav_read + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + uav_write + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + uav_waitrequest + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + uav_readdatavalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + uav_byteenable + + in + + + 0 + 3 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + uav_readdata + + out + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + uav_writedata + + in + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + uav_lock + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + uav_debugaccess + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + av_address + + out + + + 0 + 12 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + av_write + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + av_read + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + av_readdata + + in + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + av_writedata + + out + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + av_waitrequest + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + address_decode_mm_to_mac + altera_merlin_slave_translator + 19.1 + + + + + AV_ADDRESS_W + Component address width + 13 + + + AV_DATA_W + Component Data width + 32 + + + UAV_DATA_W + Network Data width + 32 + + + AV_BURSTCOUNT_W + Component burstcount width + 4 + + + AV_BYTEENABLE_W + Component byteenable width + 4 + + + UAV_BYTEENABLE_W + Network byteenable width + 4 + + + UAV_ADDRESS_W + Network address width + 15 + + + UAV_BURSTCOUNT_W + Network burstcount width + 4 + + + AV_READLATENCY + readLatency + 0 + + + AV_SETUP_WAIT + setupTime + 0 + + + AV_WRITE_WAIT + writeWaitTime + 0 + + + AV_READ_WAIT + readWaitTime + 1 + + + AV_DATA_HOLD + Hold time + 0 + + + AV_TIMING_UNITS + Timing units + 1 + + + USE_READDATA + Use readdata + 1 + + + USE_WRITEDATA + Use writedata + 1 + + + USE_READ + Use read + 1 + + + USE_WRITE + Use write + 1 + + + USE_BEGINBURSTTRANSFER + Use beginbursttransfer + 0 + + + USE_BEGINTRANSFER + Use begintransfer + 0 + + + USE_BYTEENABLE + Use byteenable + 0 + + + USE_CHIPSELECT + Use chipselect + 0 + + + USE_ADDRESS + Use address + 1 + + + USE_BURSTCOUNT + Use burstcount + 0 + + + USE_READDATAVALID + Use readdatavalid + 0 + + + USE_WAITREQUEST + Use waitrequest + 1 + + + USE_WRITEBYTEENABLE + Use writebyteenable + 0 + + + USE_LOCK + Use lock + 0 + + + USE_AV_CLKEN + Use component clken + 0 + + + USE_UAV_CLKEN + Use network clken + 0 + + + USE_OUTPUTENABLE + Use outputenable + 0 + + + USE_DEBUGACCESS + Use debugaccess + 0 + + + USE_READRESPONSE + Use readresponse + 0 + + + USE_WRITERESPONSE + Use writeresponse + 0 + + + AV_SYMBOLS_PER_WORD + Symbols per word + 4 + + + AV_ADDRESS_SYMBOLS + Address symbols + 0 + + + AV_BURSTCOUNT_SYMBOLS + Burstcount symbols + 0 + + + AV_CONSTANT_BURST_BEHAVIOR + Component constantBurstBehavior + 0 + + + UAV_CONSTANT_BURST_BEHAVIOR + Network constantBurstBehavior + 0 + + + AV_REQUIRE_UNALIGNED_ADDRESSES + Unaligned addresses + 0 + + + AV_LINEWRAPBURSTS + linewrapBursts + 0 + + + AV_MAX_PENDING_READ_TRANSACTIONS + maxPendingReadTransactions + 64 + + + AV_MAX_PENDING_WRITE_TRANSACTIONS + maxPendingWriteTransactions + 0 + + + AV_BURSTBOUNDARIES + burstOnBurstBoundariesOnly + 0 + + + AV_INTERLEAVEBURSTS + interleaveBursts + 0 + + + AV_BITS_PER_SYMBOL + Bits/symbol + 8 + + + AV_ISBIGENDIAN + isBigEndian + 0 + + + AV_ADDRESSGROUP + Component address group + 0 + + + UAV_ADDRESSGROUP + Network address group + 0 + + + AV_REGISTEROUTGOINGSIGNALS + registerOutgoingSignals + 0 + + + AV_REGISTERINCOMINGSIGNALS + registerIncomingSignals + 0 + + + AV_ALWAYSBURSTMAXBURST + Always burst max-burst + 0 + + + CHIPSELECT_THROUGH_READLATENCY + Chipselect through read latency + 0 + + + CLOCK_RATE + CLOCK_RATE + 125000000 + + + WAITREQUEST_ALLOWANCE + Waitrequest Allowance + 0 + + + SYNC_RESET + Use synchronous resets + 0 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element address_decode_mm_to_mac + { + datum _originalVersion + { + value = "16.1"; + type = "String"; + } + } + element mm_to_mac + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + true + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>avalon_universal_slave_0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>uav_address</name> + <role>address</role> + <direction>Input</direction> + <width>15</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_burstcount</name> + <role>burstcount</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_readdatavalid</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_lock</name> + <role>lock</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_debugaccess</name> + <role>debugaccess</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + <entry> + <key>merlin.flow.avalon_anti_slave_0</key> + <value>avalon_anti_slave_0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>32768</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>32768</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>64</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>avalon_anti_slave_0</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>av_address</name> + <role>address</role> + <direction>Output</direction> + <width>13</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>avalon_universal_slave_0</key> + <value> + <connectionPointName>avalon_universal_slave_0</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='avalon_universal_slave_0' start='0x0' end='0x8000' datawidth='32' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>15</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>125000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_mm_to_phy.ip b/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_mm_to_phy.ip new file mode 100755 index 0000000..fab7c08 --- /dev/null +++ b/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_mm_to_phy.ip @@ -0,0 +1,1944 @@ + + + + Intel Corporation + address_decode_mm_to_phy + mm_to_phy + 19.1 + + + clk + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset + + + reset + + + + + + + + + associatedClock + Associated clock + clk + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + avalon_universal_slave_0 + + + + + + + + address + + + uav_address + + + + + burstcount + + + uav_burstcount + + + + + read + + + uav_read + + + + + write + + + uav_write + + + + + waitrequest + + + uav_waitrequest + + + + + readdatavalid + + + uav_readdatavalid + + + + + byteenable + + + uav_byteenable + + + + + readdata + + + uav_readdata + + + + + writedata + + + uav_writedata + + + + + lock + + + uav_lock + + + + + debugaccess + + + uav_debugaccess + + + + + + + + + addressAlignment + Agent addressing + DYNAMIC + + + addressGroup + Address group + 0 + + + addressSpan + Address span + 8192 + + + addressUnits + Address units + SYMBOLS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + clk + + + associatedReset + Associated reset + reset + + + bitsPerSymbol + Bits per symbol + 8 + + + bridgedAddressOffset + Bridged Address Offset + 0 + + + bridgesToMaster + Bridges to host + + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + SYMBOLS + + + constantBurstBehavior + Constant burst behavior + false + + + explicitAddressSpan + Explicit address span + 8192 + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isBigEndian + Big endian + false + + + isFlash + Flash memory + false + + + isMemoryDevice + Memory device + false + + + isNonVolatileStorage + Non-volatile storage + false + + + linewrapBursts + Linewrap bursts + false + + + maximumPendingReadTransactions + Maximum pending read transactions + 64 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + minimumUninterruptedRunLength + Minimum uninterrupted run length + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + printableDevice + Can receive stdout/stderr + false + + + readLatency + Read latency + 0 + + + readWaitStates + Read wait states + 0 + + + readWaitTime + Read wait + 0 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + transparentBridge + Transparent bridge + false + + + waitrequestAllowance + Waitrequest allowance + 0 + + + wellBehavedWaitrequest + Well-behaved waitrequest + false + + + writeLatency + Write latency + 0 + + + writeWaitStates + Write wait states + 0 + + + writeWaitTime + Write wait + 0 + + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + merlin.flow.avalon_anti_slave_0 + avalon_anti_slave_0 + + + + + + + avalon_anti_slave_0 + + + + + + + + address + + + av_address + + + + + write + + + av_write + + + + + read + + + av_read + + + + + readdata + + + av_readdata + + + + + writedata + + + av_writedata + + + + + waitrequest + + + av_waitrequest + + + + + + + + + adaptsTo + Adapts to + + + + addressGroup + Address group + 0 + + + addressUnits + Address units + WORDS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + clk + + + associatedReset + Associated reset + reset + + + bitsPerSymbol + Bits per symbol + 8 + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + dBSBigEndian + dBS big endian + false + + + doStreamReads + Use flow control for read transfers + false + + + doStreamWrites + Use flow control for write transfers + false + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isAsynchronous + Is asynchronous + false + + + isBigEndian + Is big endian + false + + + isReadable + Is readable + false + + + isWriteable + Is writeable + false + + + linewrapBursts + Linewrap bursts + false + + + maxAddressWidth + Maximum address width + 32 + + + maximumPendingReadTransactions + Maximum pending read transactions + 0 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + readLatency + Read latency + 0 + + + readWaitTime + Read wait + 1 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + waitrequestAllowance + Waitrequest allowance + 0 + + + writeWaitTime + Write wait + 0 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_merlin_slave_translator + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + reset + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + uav_address + + in + + + 0 + 12 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + uav_burstcount + + in + + + 0 + 3 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + uav_read + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + uav_write + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + uav_waitrequest + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + uav_readdatavalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + uav_byteenable + + in + + + 0 + 3 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + uav_readdata + + out + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + uav_writedata + + in + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + uav_lock + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + uav_debugaccess + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + av_address + + out + + + 0 + 10 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + av_write + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + av_read + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + av_readdata + + in + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + av_writedata + + out + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + av_waitrequest + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + address_decode_mm_to_phy + altera_merlin_slave_translator + 19.1 + + + + + AV_ADDRESS_W + Component address width + 11 + + + AV_DATA_W + Component Data width + 32 + + + UAV_DATA_W + Network Data width + 32 + + + AV_BURSTCOUNT_W + Component burstcount width + 4 + + + AV_BYTEENABLE_W + Component byteenable width + 4 + + + UAV_BYTEENABLE_W + Network byteenable width + 4 + + + UAV_ADDRESS_W + Network address width + 13 + + + UAV_BURSTCOUNT_W + Network burstcount width + 4 + + + AV_READLATENCY + readLatency + 0 + + + AV_SETUP_WAIT + setupTime + 0 + + + AV_WRITE_WAIT + writeWaitTime + 0 + + + AV_READ_WAIT + readWaitTime + 1 + + + AV_DATA_HOLD + Hold time + 0 + + + AV_TIMING_UNITS + Timing units + 1 + + + USE_READDATA + Use readdata + 1 + + + USE_WRITEDATA + Use writedata + 1 + + + USE_READ + Use read + 1 + + + USE_WRITE + Use write + 1 + + + USE_BEGINBURSTTRANSFER + Use beginbursttransfer + 0 + + + USE_BEGINTRANSFER + Use begintransfer + 0 + + + USE_BYTEENABLE + Use byteenable + 0 + + + USE_CHIPSELECT + Use chipselect + 0 + + + USE_ADDRESS + Use address + 1 + + + USE_BURSTCOUNT + Use burstcount + 0 + + + USE_READDATAVALID + Use readdatavalid + 0 + + + USE_WAITREQUEST + Use waitrequest + 1 + + + USE_WRITEBYTEENABLE + Use writebyteenable + 0 + + + USE_LOCK + Use lock + 0 + + + USE_AV_CLKEN + Use component clken + 0 + + + USE_UAV_CLKEN + Use network clken + 0 + + + USE_OUTPUTENABLE + Use outputenable + 0 + + + USE_DEBUGACCESS + Use debugaccess + 0 + + + USE_READRESPONSE + Use readresponse + 0 + + + USE_WRITERESPONSE + Use writeresponse + 0 + + + AV_SYMBOLS_PER_WORD + Symbols per word + 4 + + + AV_ADDRESS_SYMBOLS + Address symbols + 0 + + + AV_BURSTCOUNT_SYMBOLS + Burstcount symbols + 0 + + + AV_CONSTANT_BURST_BEHAVIOR + Component constantBurstBehavior + 0 + + + UAV_CONSTANT_BURST_BEHAVIOR + Network constantBurstBehavior + 0 + + + AV_REQUIRE_UNALIGNED_ADDRESSES + Unaligned addresses + 0 + + + AV_LINEWRAPBURSTS + linewrapBursts + 0 + + + AV_MAX_PENDING_READ_TRANSACTIONS + maxPendingReadTransactions + 64 + + + AV_MAX_PENDING_WRITE_TRANSACTIONS + maxPendingWriteTransactions + 0 + + + AV_BURSTBOUNDARIES + burstOnBurstBoundariesOnly + 0 + + + AV_INTERLEAVEBURSTS + interleaveBursts + 0 + + + AV_BITS_PER_SYMBOL + Bits/symbol + 8 + + + AV_ISBIGENDIAN + isBigEndian + 0 + + + AV_ADDRESSGROUP + Component address group + 0 + + + UAV_ADDRESSGROUP + Network address group + 0 + + + AV_REGISTEROUTGOINGSIGNALS + registerOutgoingSignals + 0 + + + AV_REGISTERINCOMINGSIGNALS + registerIncomingSignals + 0 + + + AV_ALWAYSBURSTMAXBURST + Always burst max-burst + 0 + + + CHIPSELECT_THROUGH_READLATENCY + Chipselect through read latency + 0 + + + CLOCK_RATE + CLOCK_RATE + 125000000 + + + WAITREQUEST_ALLOWANCE + Waitrequest Allowance + 0 + + + SYNC_RESET + Use synchronous resets + 0 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element address_decode_mm_to_phy + { + datum _originalVersion + { + value = "16.1"; + type = "String"; + } + } + element mm_to_phy + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + true + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>avalon_universal_slave_0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>uav_address</name> + <role>address</role> + <direction>Input</direction> + <width>13</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_burstcount</name> + <role>burstcount</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_readdatavalid</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>4</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_lock</name> + <role>lock</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>uav_debugaccess</name> + <role>debugaccess</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + <entry> + <key>merlin.flow.avalon_anti_slave_0</key> + <value>avalon_anti_slave_0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8192</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>8192</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>64</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>avalon_anti_slave_0</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>av_address</name> + <role>address</role> + <direction>Output</direction> + <width>11</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>av_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>avalon_universal_slave_0</key> + <value> + <connectionPointName>avalon_universal_slave_0</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='avalon_universal_slave_0' start='0x0' end='0x2000' datawidth='32' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>13</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>125000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_rx_xcvr_clk.ip b/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_rx_xcvr_clk.ip new file mode 100755 index 0000000..1806f7b --- /dev/null +++ b/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_rx_xcvr_clk.ip @@ -0,0 +1,561 @@ + + + + Altera Corporation + address_decode_rx_xcvr_clk + rx_xcvr_clk + 23.1 + + + clk_in + + + + + + + + clk + + + in_clk + + + + + + + + + clockRate + Clock rate + 312500000 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + qsys.ui.export_name + clk + + + + + + + clk_in_reset + + + + + + + + reset_n + + + reset_n + + + + + + + + + associatedClock + Associated clock + + + + synchronousEdges + Synchronous edges + NONE + + + + + + + qsys.ui.export_name + reset + + + + + + + clk + + + + + + + + clk + + + clk_out + + + + + + + + + associatedDirectClock + Associated direct clock + clk_in + + + clockRate + Clock rate + 312500000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + true + + + ptfSchematicName + PTF schematic name + + + + + + clk_reset + + + + + + + + reset_n + + + reset_n_out + + + + + + + + + associatedClock + Associated clock + + + + associatedDirectReset + Associated direct reset + clk_in_reset + + + associatedResetSinks + Associated reset sinks + clk_in_reset + + + synchronousEdges + Synchronous edges + NONE + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + clock_source + + QUARTUS_SYNTH + + + + + + in_clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + reset_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + clk_out + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + reset_n_out + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Altera Corporation + address_decode_rx_xcvr_clk + clock_source + 23.1 + + + + + clockFrequency + Clock frequency + 312500000 + + + clockFrequencyKnown + Clock frequency is known + true + + + inputClockFrequency + inputClockFrequency + 0 + + + resetSynchronousEdges + Reset synchronous edges + NONE + + + + + + + board + Board + Unknown + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element address_decode_rx_xcvr_clk + { + datum _originalVersion + { + value = "16.1"; + type = "String"; + } + } + element rx_xcvr_clk + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + true + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clk_in</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>clk</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>312500000</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>reset</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>clk_out</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>clk_in</value> + </entry> + <entry> + <key>clockRate</key> + <value>312500000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>true</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>reset_n_out</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>312500000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>clk_in</key> + <value> + <connectionPointName>clk_in</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_tx_xcvr_clk.ip b/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_tx_xcvr_clk.ip new file mode 100755 index 0000000..66e2914 --- /dev/null +++ b/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_tx_xcvr_clk.ip @@ -0,0 +1,561 @@ + + + + Altera Corporation + address_decode_tx_xcvr_clk + tx_xcvr_clk + 23.1 + + + clk_in + + + + + + + + clk + + + in_clk + + + + + + + + + clockRate + Clock rate + 312500000 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + qsys.ui.export_name + clk + + + + + + + clk_in_reset + + + + + + + + reset_n + + + reset_n + + + + + + + + + associatedClock + Associated clock + + + + synchronousEdges + Synchronous edges + NONE + + + + + + + qsys.ui.export_name + reset + + + + + + + clk + + + + + + + + clk + + + clk_out + + + + + + + + + associatedDirectClock + Associated direct clock + clk_in + + + clockRate + Clock rate + 312500000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + true + + + ptfSchematicName + PTF schematic name + + + + + + clk_reset + + + + + + + + reset_n + + + reset_n_out + + + + + + + + + associatedClock + Associated clock + + + + associatedDirectReset + Associated direct reset + clk_in_reset + + + associatedResetSinks + Associated reset sinks + clk_in_reset + + + synchronousEdges + Synchronous edges + NONE + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + clock_source + + QUARTUS_SYNTH + + + + + + in_clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + reset_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + clk_out + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + reset_n_out + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Altera Corporation + address_decode_tx_xcvr_clk + clock_source + 23.1 + + + + + clockFrequency + Clock frequency + 312500000 + + + clockFrequencyKnown + Clock frequency is known + true + + + inputClockFrequency + inputClockFrequency + 0 + + + resetSynchronousEdges + Reset synchronous edges + NONE + + + + + + + board + Board + Unknown + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element address_decode_tx_xcvr_clk + { + datum _originalVersion + { + value = "16.1"; + type = "String"; + } + } + element tx_xcvr_clk + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + true + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clk_in</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>clk</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>312500000</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>reset</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>clk_out</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>clk_in</value> + </entry> + <entry> + <key>clockRate</key> + <value>312500000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>true</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>reset_n_out</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>312500000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>clk_in</key> + <value> + <connectionPointName>clk_in</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_tx_xcvr_half_clk.ip b/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_tx_xcvr_half_clk.ip new file mode 100755 index 0000000..606e9f0 --- /dev/null +++ b/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_tx_xcvr_half_clk.ip @@ -0,0 +1,553 @@ + + + + Altera Corporation + address_decode_tx_xcvr_half_clk + tx_xcvr_half_clk + 23.1 + + + clk_in + + + + + + + + clk + + + in_clk + + + + + + + + + clockRate + Clock rate + 156250000 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + qsys.ui.export_name + clk + + + + + + + clk_in_reset + + + + + + + + reset_n + + + reset_n + + + + + + + + + associatedClock + Associated clock + + + + synchronousEdges + Synchronous edges + NONE + + + + + + + qsys.ui.export_name + reset + + + + + + + clk + + + + + + + + clk + + + clk_out + + + + + + + + + associatedDirectClock + Associated direct clock + clk_in + + + clockRate + Clock rate + 156250000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + true + + + ptfSchematicName + PTF schematic name + + + + + + clk_reset + + + + + + + + reset_n + + + reset_n_out + + + + + + + + + associatedClock + Associated clock + + + + associatedDirectReset + Associated direct reset + clk_in_reset + + + associatedResetSinks + Associated reset sinks + clk_in_reset + + + synchronousEdges + Synchronous edges + NONE + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + clock_source + + QUARTUS_SYNTH + + + + + + in_clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + reset_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + clk_out + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + reset_n_out + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Altera Corporation + address_decode_tx_xcvr_half_clk + clock_source + 23.1 + + + + + clockFrequency + Clock frequency + 156250000 + + + clockFrequencyKnown + Clock frequency is known + true + + + inputClockFrequency + inputClockFrequency + 0 + + + resetSynchronousEdges + Reset synchronous edges + NONE + + + + + + + board + Board + Unknown + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element tx_xcvr_half_clk + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + true + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clk_in</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>clk</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>156250000</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>qsys.ui.export_name</key> + <value>reset</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>clk_out</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>clk_in</value> + </entry> + <entry> + <key>clockRate</key> + <value>156250000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>true</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clk_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>reset_n_out</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>clk_in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>156250000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>clk_in</key> + <value> + <connectionPointName>clk_in</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/ipss/hssi/s10/ip/mac/.gitignore b/ipss/hssi/s10/ip/mac/.gitignore new file mode 100755 index 0000000..99d7f84 --- /dev/null +++ b/ipss/hssi/s10/ip/mac/.gitignore @@ -0,0 +1,3 @@ +#altera_eth_10g_mac/altera_eth_10g_mac* +#altera_eth_10g_mac/synth/ +altera_eth_10g_mac/alt_em10g32_1930/synth/ diff --git a/ipss/hssi/s10/ip/mac/altera_eth_10g_mac.ip b/ipss/hssi/s10/ip/mac/altera_eth_10g_mac.ip new file mode 100755 index 0000000..05094e3 --- /dev/null +++ b/ipss/hssi/s10/ip/mac/altera_eth_10g_mac.ip @@ -0,0 +1,2828 @@ + + + + Intel Corporation + altera_eth_10g_mac + alt_em10g32_0 + 22.0.1 + + + csr + + + + + + + + read + + + csr_read + + + + + write + + + csr_write + + + + + writedata + + + csr_writedata + + + + + readdata + + + csr_readdata + + + + + waitrequest + + + csr_waitrequest + + + + + address + + + csr_address + + + + + + + + + addressAlignment + Agent addressing + DYNAMIC + + + addressGroup + Address group + 0 + + + addressSpan + Address span + 4096 + + + addressUnits + Address units + WORDS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + csr_clk + + + associatedReset + Associated reset + csr_rst_n + + + bitsPerSymbol + Bits per symbol + 8 + + + bridgedAddressOffset + Bridged Address Offset + 0 + + + bridgesToMaster + Bridges to host + + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + explicitAddressSpan + Explicit address span + 0 + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isBigEndian + Big endian + false + + + isFlash + Flash memory + false + + + isMemoryDevice + Memory device + false + + + isNonVolatileStorage + Non-volatile storage + false + + + linewrapBursts + Linewrap bursts + false + + + maximumPendingReadTransactions + Maximum pending read transactions + 0 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + minimumUninterruptedRunLength + Minimum uninterrupted run length + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + printableDevice + Can receive stdout/stderr + false + + + readLatency + Read latency + 0 + + + readWaitStates + Read wait states + 0 + + + readWaitTime + Read wait + 0 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + transparentBridge + Transparent bridge + false + + + waitrequestAllowance + Waitrequest allowance + 0 + + + wellBehavedWaitrequest + Well-behaved waitrequest + false + + + writeLatency + Write latency + 0 + + + writeWaitStates + Write wait states + 0 + + + writeWaitTime + Write wait + 0 + + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + + + + + tx_312_5_clk + + + + + + + + clk + + + tx_312_5_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + tx_156_25_clk + + + + + + + + clk + + + tx_156_25_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + rx_312_5_clk + + + + + + + + clk + + + rx_312_5_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + rx_156_25_clk + + + + + + + + clk + + + rx_156_25_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + csr_clk + + + + + + + + clk + + + csr_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + csr_rst_n + + + + + + + + reset_n + + + csr_rst_n + + + + + + + + + associatedClock + Associated clock + csr_clk + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + tx_rst_n + + + + + + + + reset_n + + + tx_rst_n + + + + + + + + + associatedClock + Associated clock + tx_312_5_clk + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + rx_rst_n + + + + + + + + reset_n + + + rx_rst_n + + + + + + + + + associatedClock + Associated clock + rx_312_5_clk + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + avalon_st_tx + + + + + + + + startofpacket + + + avalon_st_tx_startofpacket + + + + + endofpacket + + + avalon_st_tx_endofpacket + + + + + valid + + + avalon_st_tx_valid + + + + + data + + + avalon_st_tx_data + + + + + empty + + + avalon_st_tx_empty + + + + + error + + + avalon_st_tx_error + + + + + ready + + + avalon_st_tx_ready + + + + + + + + + associatedClock + associatedClock + tx_312_5_clk + + + associatedReset + associatedReset + tx_rst_n + + + beatsPerCycle + Beats Per Cycle + 1 + + + dataBitsPerSymbol + Data bits per symbol + 8 + + + emptyWithinPacket + emptyWithinPacket + false + + + errorDescriptor + Error descriptor + + + + firstSymbolInHighOrderBits + First Symbol In High-Order Bits + true + + + highOrderSymbolAtMSB + highOrderSymbolAtMSB + false + + + maxChannel + Maximum channel + 0 + + + packetDescription + Packet description + + + + prSafe + Partial Reconfiguration Safe + false + + + readyAllowance + Ready allowance + 0 + + + readyLatency + Ready latency + 0 + + + symbolsPerBeat + Symbols per beat + 1 + + + + + avalon_st_pause + + + + + + + + data + + + avalon_st_pause_data + + + + + + + + + associatedClock + associatedClock + tx_312_5_clk + + + associatedReset + associatedReset + tx_rst_n + + + beatsPerCycle + Beats Per Cycle + 1 + + + dataBitsPerSymbol + Data bits per symbol + 2 + + + emptyWithinPacket + emptyWithinPacket + false + + + errorDescriptor + Error descriptor + + + + firstSymbolInHighOrderBits + First Symbol In High-Order Bits + true + + + highOrderSymbolAtMSB + highOrderSymbolAtMSB + false + + + maxChannel + Maximum channel + 0 + + + packetDescription + Packet description + + + + prSafe + Partial Reconfiguration Safe + false + + + readyAllowance + Ready allowance + 0 + + + readyLatency + Ready latency + 0 + + + symbolsPerBeat + Symbols per beat + 1 + + + + + avalon_st_tx_pfc_gen_data + + + + + + + + export + + + avalon_st_tx_pfc_gen_data + + + + + + + + + associatedClock + associatedClock + tx_312_5_clk + + + associatedReset + associatedReset + tx_rst_n + + + prSafe + Partial Reconfiguration Safe + false + + + + + xgmii_tx + + + + + + + + data + + + xgmii_tx + + + + + + + + + associatedClock + associatedClock + tx_156_25_clk + + + associatedReset + associatedReset + tx_rst_n + + + beatsPerCycle + Beats Per Cycle + 1 + + + dataBitsPerSymbol + Data bits per symbol + 72 + + + emptyWithinPacket + emptyWithinPacket + false + + + errorDescriptor + Error descriptor + + + + firstSymbolInHighOrderBits + First Symbol In High-Order Bits + true + + + highOrderSymbolAtMSB + highOrderSymbolAtMSB + false + + + maxChannel + Maximum channel + 0 + + + packetDescription + Packet description + + + + prSafe + Partial Reconfiguration Safe + false + + + readyAllowance + Ready allowance + 0 + + + readyLatency + Ready latency + 0 + + + symbolsPerBeat + Symbols per beat + 1 + + + + + avalon_st_txstatus + + + + + + + + valid + + + avalon_st_txstatus_valid + + + + + data + + + avalon_st_txstatus_data + + + + + error + + + avalon_st_txstatus_error + + + + + + + + + associatedClock + associatedClock + tx_312_5_clk + + + associatedReset + associatedReset + tx_rst_n + + + beatsPerCycle + Beats Per Cycle + 1 + + + dataBitsPerSymbol + Data bits per symbol + 8 + + + emptyWithinPacket + emptyWithinPacket + false + + + errorDescriptor + Error descriptor + + + + firstSymbolInHighOrderBits + First Symbol In High-Order Bits + true + + + highOrderSymbolAtMSB + highOrderSymbolAtMSB + false + + + maxChannel + Maximum channel + 0 + + + packetDescription + Packet description + + + + prSafe + Partial Reconfiguration Safe + false + + + readyAllowance + Ready allowance + 0 + + + readyLatency + Ready latency + 0 + + + symbolsPerBeat + Symbols per beat + 1 + + + + + avalon_st_tx_pfc_status + + + + + + + + valid + + + avalon_st_tx_pfc_status_valid + + + + + data + + + avalon_st_tx_pfc_status_data + + + + + + + + + associatedClock + associatedClock + tx_312_5_clk + + + associatedReset + associatedReset + tx_rst_n + + + beatsPerCycle + Beats Per Cycle + 1 + + + dataBitsPerSymbol + Data bits per symbol + 8 + + + emptyWithinPacket + emptyWithinPacket + false + + + errorDescriptor + Error descriptor + + + + firstSymbolInHighOrderBits + First Symbol In High-Order Bits + true + + + highOrderSymbolAtMSB + highOrderSymbolAtMSB + false + + + maxChannel + Maximum channel + 0 + + + packetDescription + Packet description + + + + prSafe + Partial Reconfiguration Safe + false + + + readyAllowance + Ready allowance + 0 + + + readyLatency + Ready latency + 0 + + + symbolsPerBeat + Symbols per beat + 1 + + + + + xgmii_rx + + + + + + + + data + + + xgmii_rx + + + + + + + + + associatedClock + associatedClock + rx_156_25_clk + + + associatedReset + associatedReset + rx_rst_n + + + beatsPerCycle + Beats Per Cycle + 1 + + + dataBitsPerSymbol + Data bits per symbol + 72 + + + emptyWithinPacket + emptyWithinPacket + false + + + errorDescriptor + Error descriptor + + + + firstSymbolInHighOrderBits + First Symbol In High-Order Bits + true + + + highOrderSymbolAtMSB + highOrderSymbolAtMSB + false + + + maxChannel + Maximum channel + 0 + + + packetDescription + Packet description + + + + prSafe + Partial Reconfiguration Safe + false + + + readyAllowance + Ready allowance + 0 + + + readyLatency + Ready latency + 0 + + + symbolsPerBeat + Symbols per beat + 1 + + + + + link_fault_status_xgmii_rx + + + + + + + + data + + + link_fault_status_xgmii_rx_data + + + + + + + + + associatedClock + associatedClock + rx_312_5_clk + + + associatedReset + associatedReset + rx_rst_n + + + beatsPerCycle + Beats Per Cycle + 1 + + + dataBitsPerSymbol + Data bits per symbol + 2 + + + emptyWithinPacket + emptyWithinPacket + false + + + errorDescriptor + Error descriptor + + + + firstSymbolInHighOrderBits + First Symbol In High-Order Bits + true + + + highOrderSymbolAtMSB + highOrderSymbolAtMSB + false + + + maxChannel + Maximum channel + 0 + + + packetDescription + Packet description + + + + prSafe + Partial Reconfiguration Safe + false + + + readyAllowance + Ready allowance + 0 + + + readyLatency + Ready latency + 0 + + + symbolsPerBeat + Symbols per beat + 1 + + + + + avalon_st_rx + + + + + + + + data + + + avalon_st_rx_data + + + + + startofpacket + + + avalon_st_rx_startofpacket + + + + + valid + + + avalon_st_rx_valid + + + + + empty + + + avalon_st_rx_empty + + + + + error + + + avalon_st_rx_error + + + + + ready + + + avalon_st_rx_ready + + + + + endofpacket + + + avalon_st_rx_endofpacket + + + + + + + + + associatedClock + associatedClock + rx_312_5_clk + + + associatedReset + associatedReset + rx_rst_n + + + beatsPerCycle + Beats Per Cycle + 1 + + + dataBitsPerSymbol + Data bits per symbol + 8 + + + emptyWithinPacket + emptyWithinPacket + false + + + errorDescriptor + Error descriptor + + + + firstSymbolInHighOrderBits + First Symbol In High-Order Bits + true + + + highOrderSymbolAtMSB + highOrderSymbolAtMSB + false + + + maxChannel + Maximum channel + 0 + + + packetDescription + Packet description + + + + prSafe + Partial Reconfiguration Safe + false + + + readyAllowance + Ready allowance + 0 + + + readyLatency + Ready latency + 0 + + + symbolsPerBeat + Symbols per beat + 1 + + + + + avalon_st_rxstatus + + + + + + + + valid + + + avalon_st_rxstatus_valid + + + + + data + + + avalon_st_rxstatus_data + + + + + error + + + avalon_st_rxstatus_error + + + + + + + + + associatedClock + associatedClock + rx_312_5_clk + + + associatedReset + associatedReset + rx_rst_n + + + beatsPerCycle + Beats Per Cycle + 1 + + + dataBitsPerSymbol + Data bits per symbol + 8 + + + emptyWithinPacket + emptyWithinPacket + false + + + errorDescriptor + Error descriptor + + + + firstSymbolInHighOrderBits + First Symbol In High-Order Bits + true + + + highOrderSymbolAtMSB + highOrderSymbolAtMSB + false + + + maxChannel + Maximum channel + 0 + + + packetDescription + Packet description + + + + prSafe + Partial Reconfiguration Safe + false + + + readyAllowance + Ready allowance + 0 + + + readyLatency + Ready latency + 0 + + + symbolsPerBeat + Symbols per beat + 1 + + + + + avalon_st_rx_pfc_status + + + + + + + + valid + + + avalon_st_rx_pfc_status_valid + + + + + data + + + avalon_st_rx_pfc_status_data + + + + + + + + + associatedClock + associatedClock + rx_312_5_clk + + + associatedReset + associatedReset + rx_rst_n + + + beatsPerCycle + Beats Per Cycle + 1 + + + dataBitsPerSymbol + Data bits per symbol + 8 + + + emptyWithinPacket + emptyWithinPacket + false + + + errorDescriptor + Error descriptor + + + + firstSymbolInHighOrderBits + First Symbol In High-Order Bits + true + + + highOrderSymbolAtMSB + highOrderSymbolAtMSB + false + + + maxChannel + Maximum channel + 0 + + + packetDescription + Packet description + + + + prSafe + Partial Reconfiguration Safe + false + + + readyAllowance + Ready allowance + 0 + + + readyLatency + Ready latency + 0 + + + symbolsPerBeat + Symbols per beat + 1 + + + + + avalon_st_rx_pfc_pause + + + + + + + + data + + + avalon_st_rx_pfc_pause_data + + + + + + + + + associatedClock + associatedClock + rx_312_5_clk + + + associatedReset + associatedReset + rx_rst_n + + + beatsPerCycle + Beats Per Cycle + 1 + + + dataBitsPerSymbol + Data bits per symbol + 8 + + + emptyWithinPacket + emptyWithinPacket + false + + + errorDescriptor + Error descriptor + + + + firstSymbolInHighOrderBits + First Symbol In High-Order Bits + true + + + highOrderSymbolAtMSB + highOrderSymbolAtMSB + false + + + maxChannel + Maximum channel + 0 + + + packetDescription + Packet description + + + + prSafe + Partial Reconfiguration Safe + false + + + readyAllowance + Ready allowance + 0 + + + readyLatency + Ready latency + 0 + + + symbolsPerBeat + Symbols per beat + 1 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + 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INSERT_XGMII_ADAPTOR + Use legacy Ethernet 10G MAC XGMII interface + 1 + + + DATAPATH_OPTION + Datapath options + 3 + + + ENABLE_SUPP_ADDR + Enable supplementary address + 1 + + + ENABLE_PFC + Enable priority-based flow control (PFC) + 1 + + + PFC_PRIORITY_NUMBER + Number of PFC queues + 8 + + + INSTANTIATE_STATISTICS + Enable statistics collection + 1 + + + REGISTER_BASED_STATISTICS + Statistics counters + 0 + + + PREAMBLE_PASSTHROUGH + Enable preamble pass-through mode + 0 + + + ENABLE_TIMESTAMPING + Enable time stamping + 0 + + + ENABLE_PTP_1STEP + Enable PTP one-step clock support + 0 + + + ENABLE_ASYMMETRY + Enable asymmetry support + 0 + + + ENABLE_P2P + Enable peer-to-peer support + 0 + + + TSTAMP_FP_WIDTH + Timestamp fingerprint width + 4 + + + TIME_OF_DAY_FORMAT + Time Of Day Format + 2 + + + ENABLE_1G10G_MAC + Speed + 0 + + + ENABLE_MEM_ECC + Enable ECC on memory blocks + 0 + + + ENABLE_UNIDIRECTIONAL + Enable unidirectional feature + 0 + + + ENABLE_10GBASER_REG_MODE + Enable 10GBASE-R register mode + 0 + + + ENABLE_TXRX_DATAPATH + TX and RX datapath Reset/Default To Enable + 1 + + + SHOW_HIDDEN_OPTIONS + Show hidden options + 0 + + + SELECT_SUPPORTED_VARIANT + Select Design + 0 + + + ENABLE_ED_FILESET_SYNTHESIS + Synthesis + 1 + + + ENABLE_ED_FILESET_SIM + Simulation + 1 + + + SELECT_ED_FILESET + Generate File Format + 0 + + + SELECT_TARGETED_DEVICE + Select Board + 0 + + + SELECT_CUSTOM_DEVICE + Change Target Device + 1 + + + SELECT_NUMBER_OF_CHANNEL + Specify Number of Channels + 1 + + + ANLG_VOLTAGE + Analog Voltage + 1_0V + + + ENABLE_ADME + Enable Native PHY Debug Master Endpoint (NPDME) + 0 + + + DEVKIT_DEVICE + Devkit device part + 10AX115S4F45E3SGE3 + + + QSF_PATH + QSF Path + + + + die_types + die_types + HSSI_CRETE2E,MAIN_ND5 + + + INTERNAL_FEATURE + INTERNAL_FEATURE + false + + + PR_READY + Partial Reconfiguration Ready + 0 + + + + + + + board + Board + Unknown + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element alt_em10g32_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + true + + + lockedInterfaceDefinition + lockedInterfaceDefinition + + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>csr</key> + <value> + <connectionPointName>csr</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='csr' start='0x0' end='0x1000' datawidth='32' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>12</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + 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ui.blockdiagram.direction + output + + + + + + + rx_fifo_full + + + + + + + + rx_fifo_full + + + rx_fifo_full + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + rx_fifo_empty + + + + + + + + rx_fifo_empty + + + rx_fifo_empty + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + rx_fifo_insert + + + + + + + + rx_fifo_insert + + + rx_fifo_insert + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + rx_fifo_del + + + + + + + + rx_fifo_del + + + rx_fifo_del + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + rx_enh_highber + + + + + + + + rx_enh_highber + + + rx_enh_highber + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + rx_enh_blk_lock + + + + + + + + rx_enh_blk_lock + + + rx_enh_blk_lock + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + reconfig_clk + + + + + + + + clk + + + reconfig_clk + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + input + + + + + + + reconfig_reset + + + + + + + + reset + + + reconfig_reset + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + input + + + + + + + reconfig_avmm + + + + + + + + write + + + reconfig_write + + + + + read + + + reconfig_read + + + + + address + + + reconfig_address + + + + + writedata + + + reconfig_writedata + + + + + readdata + + + reconfig_readdata + + + + + waitrequest + + + reconfig_waitrequest + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + input + + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_xcvr_native_s10_htile + + QUARTUS_SYNTH + + + + + + tx_analogreset + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_analogreset + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + tx_digitalreset + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_digitalreset + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + tx_transfer_ready + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_transfer_ready + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + osc_transfer_en + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + tx_fifo_ready + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_fifo_ready + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + tx_digitalreset_timeout + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_digitalreset_timeout + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + tx_analogreset_stat + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_analogreset_stat + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + tx_digitalreset_stat + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_digitalreset_stat + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + tx_cal_busy + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_cal_busy + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + tx_serial_clk0 + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_cdr_refclk0 + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + tx_serial_data + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_serial_data + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_seriallpbken + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_is_lockedtoref + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_is_lockedtodata + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + tx_coreclkin + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_coreclkin + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + tx_clkout + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_clkout + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + tx_parallel_data + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + tx_control + + in + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + tx_err_ins + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + tx_enh_data_valid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + unused_tx_parallel_data + + in + + + 0 + 5 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_parallel_data + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_control + + out + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_enh_data_valid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + unused_rx_parallel_data + + out + + + 0 + 6 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + tx_fifo_full + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + tx_fifo_empty + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + tx_fifo_pfull + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + tx_fifo_pempty + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_fifo_full + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_fifo_empty + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_fifo_insert + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_fifo_del + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_enh_highber + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_enh_blk_lock + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + reconfig_clk + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + reconfig_reset + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + reconfig_write + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + reconfig_read + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + reconfig_address + + in + + + 0 + 10 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + reconfig_writedata + + in + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + reconfig_readdata + + out + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + reconfig_waitrequest + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + altera_eth_10gbaser_phy + altera_xcvr_native_s10_htile + 19.3.0 + + + + + rcfg_debug + rcfg_debug + 0 + + + rcfg_enable + Enable dynamic reconfiguration + 1 + + + rcfg_jtag_enable + Enable Native PHY Debug Master Endpoint + 0 + + + rcfg_separate_avmm_busy + Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE + 0 + + + rcfg_enable_avmm_busy_port + Enable avmm_busy port + 0 + + + set_capability_reg_enable + Enable capability registers + 1 + + + set_user_identifier + Set user-defined IP identifier + 0 + + + set_csr_soft_logic_enable + Enable control and status registers + 1 + + + rcfg_file_prefix + Configuration file prefix + altera_xcvr_rcfg_10 + + + rcfg_files_as_common_package + Declare SystemVerilog package file as common package file + 0 + + + rcfg_sv_file_enable + Generate SystemVerilog package file + 0 + + + rcfg_h_file_enable + Generate C header file + 0 + + + rcfg_txt_file_enable + Generate text file + 0 + + + rcfg_mif_file_enable + Generate MIF (Memory Initialize File) + 0 + + + rcfg_multi_enable + Enable multiple reconfiguration profiles + 0 + + + set_rcfg_emb_strm_enable + Enable embedded reconfiguration streamer + 0 + + + rcfg_reduced_files_enable + Generate reduced reconfiguration files + 0 + + + rcfg_profile_cnt + Number of reconfiguration profiles + 2 + + + rcfg_profile_select + Store current configuration to profile: + 1 + + + rcfg_profile_data0 + rcfg_profile_data0 + + + + rcfg_profile_data1 + rcfg_profile_data1 + + + + rcfg_profile_data2 + rcfg_profile_data2 + + + + rcfg_profile_data3 + rcfg_profile_data3 + + + + rcfg_profile_data4 + rcfg_profile_data4 + + + + rcfg_profile_data5 + rcfg_profile_data5 + + + + rcfg_profile_data6 + rcfg_profile_data6 + + + + rcfg_profile_data7 + rcfg_profile_data7 + + + + rcfg_sdc_derived_profile_data0 + rcfg_sdc_derived_profile_data0 + + + + rcfg_sdc_derived_profile_data1 + rcfg_sdc_derived_profile_data1 + + + + rcfg_sdc_derived_profile_data2 + rcfg_sdc_derived_profile_data2 + + + + rcfg_sdc_derived_profile_data3 + rcfg_sdc_derived_profile_data3 + + + + rcfg_sdc_derived_profile_data4 + rcfg_sdc_derived_profile_data4 + + + + rcfg_sdc_derived_profile_data5 + rcfg_sdc_derived_profile_data5 + + + + rcfg_sdc_derived_profile_data6 + rcfg_sdc_derived_profile_data6 + + + + rcfg_sdc_derived_profile_data7 + rcfg_sdc_derived_profile_data7 + + + + device_family + device_family + Stratix 10 + + + device + device + 1SX280HN2F43E2VG + + + base_device + base_device + ND5_45 + + + device_die_types + device_die_types + HSSI_CRETE2E,MAIN_ND5 + + + device_die_revisions + device_die_revisions + HSSI_CRETE2E_REVB,MAIN_ND5_REVC + + + design_environment + design_environment + NATIVE + + + message_level + Message level for rule violations + error + + + reduced_reset_sim_time + Use fast reset for simulation + 0 + + + support_mode + Protocol support mode + user_mode + + + channel_type + Transceiver channel type + GX + + + protocol_mode + Transceiver configuration rules + teng_baser_mode + + + pma_mode + PMA configuration rules + basic + + + duplex_mode + Transceiver mode + duplex + + + channels + Number of data channels + 1 + + + set_data_rate + Data rate + 10312.5 + + + rcfg_iface_enable + Enable datapath and interface reconfiguration + 0 + + + enable_simple_interface + Enable simplified data interface + 1 + + + enable_split_interface + Provide separate interface for each channel + 0 + + + set_enable_calibration + Enable calibration + 1 + + + enable_channel_powerdown + Enable PMA/PCS powerdown support + 0 + + + enable_transparent_pcs + Enable transparent PCS + 0 + + + enable_double_rate_transfer + Enable double rate transfer mode + 0 + + + enable_background_cal_gui + Enable background calibration + 0 + + + set_enable_eios_rx_protect + Enable PIPE EIOS RX Protection + 0 + + + enable_direct_reset_control + Enable direct reset control + 0 + + + disable_reset_sequencer + Disable reset sequencer + 0 + + + disable_digital_reset_sequencer + Disable digital reset sequencer + 0 + + + bonded_mode + TX channel bonding mode + not_bonded + + + set_pcs_bonding_master + PCS TX channel bonding master + Auto + + + pcs_reset_sequencing_mode + PCS reset sequence + not_bonded + + + enable_manual_bonding_settings + Enable manual PCS bonding settings + 0 + + + manual_pcs_bonding_mode + PCS TX channel bonding mode + individual + + + manual_pcs_bonding_comp_cnt + PCS TX bonding compensation counter + 0 + + + manual_tx_hssi_aib_bonding_mode + TX HSSI AIB bonding mode + individual + + + manual_tx_hssi_aib_bonding_comp_cnt + TX HSSI AIB compensation counter + 0 + + + manual_tx_core_aib_bonding_mode + TX Core AIB bonding mode + individual + + + manual_tx_core_aib_bonding_comp_cnt + TX Core AIB compensation counter + 0 + + + manual_rx_hssi_aib_bonding_mode + RX HSSI AIB bonding mode + individual + + + manual_rx_hssi_aib_bonding_comp_cnt + RX HSSI AIB compensation counter + 0 + + + manual_rx_core_aib_bonding_mode + RX Core AIB bonding mode + individual + + + manual_rx_core_aib_bonding_comp_cnt + RX Core AIB compensation counter + 0 + + + manual_tx_hssi_aib_indv + TX HSSI AIB sychronous bonding setting + indv_en + + + manual_tx_core_aib_indv + TX Core AIB sychronous bonding setting + indv_en + + + manual_rx_hssi_aib_indv + RX HSSI AIB sychronous bonding setting + indv_en + + + manual_rx_core_aib_indv + RX Core AIB sychronous bonding setting + indv_en + + + tx_pma_clk_div + TX local clock division factor + 1 + + + plls + Number of TX PLL clock inputs per channel + 1 + + + pll_select + Initial TX PLL clock input selection + 0 + + + enable_port_tx_pma_iqtxrx_clkout + Enable tx_pma_iqtxrx_clkout port + 0 + + + enable_port_tx_pma_elecidle + Enable tx_pma_elecidle port + 0 + + + number_physical_bonding_clocks + Number of physical bonding clock ports to use. + 1 + + + enable_qpi_mode + Enable QPI mode + 0 + + + enable_qpi_async_transfer + Use asynchronous QPI signals + 0 + + + enable_port_tx_pma_qpipullup + Enable tx_pma_qpipullup port + 0 + + + enable_port_tx_pma_qpipulldn + Enable tx_pma_qpipulldn port + 0 + + + enable_port_tx_pma_rxfound + Enable tx_pma_rxfound port + 0 + + + enable_port_rx_pma_qpipulldn + Enable rx_pma_qpipulldn port + 0 + + + enable_port_tx_pma_txdetectrx + Enable tx_pma_txdetectrx port + 0 + + + cdr_refclk_cnt + Number of CDR reference clocks + 1 + + + cdr_refclk_select + Selected CDR reference clock + 0 + + + set_cdr_refclk_freq + Selected CDR reference clock frequency + 644.531250 + + + rx_ppm_detect_threshold + PPM detector threshold + 1000 + + + set_cdr_refclk_receiver_detect_src + set_cdr_refclk_receiver_detect_src + iqclk + + + enable_port_rx_pma_iqtxrx_clkout + Enable rx_pma_iqtxrx_clkout port + 0 + + + enable_port_rx_pma_clkslip + Enable rx_pma_clkslip port + 0 + + + enable_port_rx_is_lockedtodata + Enable rx_is_lockedtodata port + 1 + + + enable_port_rx_is_lockedtoref + Enable rx_is_lockedtoref port + 1 + + + enable_ports_rx_manual_cdr_mode + Enable rx_set_locktodata and rx_set_locktoref ports + 0 + + + enable_ports_rx_prbs + Enable PRBS verifier control and status ports + 0 + + + enable_port_rx_seriallpbken + Enable rx_seriallpbken port + 1 + + + std_pcs_pma_width + Standard PCS / PMA interface width + 10 + + + std_low_latency_bypass_enable + Enable 'Standard PCS' low latency mode + 0 + + + enable_hip + Enable PCIe hard IP support + 0 + + + enable_hard_reset + Enable hard reset controller (HIP) + 0 + + + set_hip_cal_en + Enable PCIe hard IP calibration + 0 + + + hip_mode + PCIe channel HIP mode + disable_hip + + + hip_prot_mode + PCIe HIP protocol mode + gen1 + + + hip_channels + Number of PCIe HIP channels + x1 + + + enable_ehip + Enable Ethernet Hard IP Support + 0 + + + avmm_ehip_mode + Ethernet channel AVMM HIP mode + disable_hip + + + adapter_ehip_mode + Ethernet channel Adapter HIP mode + disable_hip + + + std_tx_byte_ser_mode + TX byte serializer mode + Disabled + + + std_rx_byte_deser_mode + RX byte deserializer mode + Disabled + + + std_tx_8b10b_enable + Enable TX 8B/10B encoder + 0 + + + std_tx_8b10b_disp_ctrl_enable + Enable TX 8B/10B disparity control + 0 + + + std_rx_8b10b_enable + Enable RX 8B/10B decoder + 0 + + + std_rx_rmfifo_mode + RX rate match FIFO mode + disabled + + + std_rx_rmfifo_pattern_n + RX rate match insert/delete -ve pattern (hex) + 0 + + + std_rx_rmfifo_pattern_p + RX rate match insert/delete +ve pattern (hex) + 0 + + + enable_port_rx_std_rmfifo_full + Enable rx_std_rmfifo_full port + 0 + + + enable_port_rx_std_rmfifo_empty + Enable rx_std_rmfifo_empty port + 0 + + + pcie_rate_match + PCI Express Gen 3 rate match FIFO mode + Bypass + + + std_tx_bitslip_enable + Enable TX bitslip + 0 + + + enable_port_tx_std_bitslipboundarysel + Enable tx_std_bitslipboundarysel port + 0 + + + std_rx_word_aligner_mode + RX word aligner mode + bitslip + + + std_rx_word_aligner_pattern_len + RX word aligner pattern length + 7 + + + std_rx_word_aligner_pattern + RX word aligner pattern (hex) + 0 + + + std_rx_word_aligner_rknumber + Number of word alignment patterns to achieve sync + 3 + + + std_rx_word_aligner_renumber + Number of invalid data words to lose sync + 3 + + + std_rx_word_aligner_rgnumber + Number of valid data words to decrement error count + 3 + + + std_rx_word_aligner_rvnumber + Number of valid data patterns required to achieve word alignment + 0 + + + std_rx_word_aligner_fast_sync_status_enable + Enable fast sync status reporting for deterministic latency SM + 0 + + + enable_port_rx_std_wa_patternalign + Enable rx_std_wa_patternalign port + 0 + + + enable_port_rx_std_wa_a1a2size + Enable rx_std_wa_a1a2size port + 0 + + + enable_port_rx_std_bitslipboundarysel + Enable rx_std_bitslipboundarysel port + 0 + + + enable_port_rx_std_bitslip + Enable rx_bitslip port + 0 + + + std_tx_bitrev_enable + Enable TX bit reversal + 0 + + + std_tx_byterev_enable + Enable TX byte reversal + 0 + + + std_tx_polinv_enable + Enable TX polarity inversion + 0 + + + enable_port_tx_polinv + Enable tx_polinv port + 0 + + + std_rx_bitrev_enable + Enable RX bit reversal + 0 + + + enable_port_rx_std_bitrev_ena + Enable rx_std_bitrev_ena port + 0 + + + std_rx_byterev_enable + Enable RX byte reversal + 0 + + + enable_port_rx_std_byterev_ena + Enable rx_std_byterev_ena port + 0 + + + std_rx_polinv_enable + Enable RX polarity inversion + 0 + + + enable_port_rx_polinv + Enable rx_polinv port + 0 + + + enable_port_rx_std_signaldetect + Enable rx_std_signaldetect port + 0 + + + enable_ports_pipe_sw + Enable PCIe dynamic datarate switch ports + 0 + + + enable_ports_pipe_rx_elecidle + Enable PCIe electrical idle control and status ports + 0 + + + enable_ports_pipe_hclk + Enable PCIe pipe_hclk_in and pipe_hclk_out ports + 0 + + + enable_early_spd_chng + Enable early speed change + 0 + + + early_spd_chng_t1 + Delay T1 for early_spd_chng + 60 + + + early_spd_chng_t2 + Pulse width T2 + 150 + + + early_spd_chng_t3 + Delay T3 for pipe_sw + 1000 + + + enh_pcs_pma_width + Enhanced PCS / PMA interface width + 32 + + + enh_pld_pcs_width + FPGA fabric / Enhanced PCS interface width + 66 + + + enh_low_latency_enable + Enable 'Enhanced PCS' low latency mode + 0 + + + enh_advanced_user_mode + Enable 'Enhanced PCS' advanced user mode + 0 + + + enh_tx_frmgen_enable + Enable Interlaken frame generator + 0 + + + enh_tx_frmgen_mfrm_length + Frame generator metaframe length + 2048 + + + enh_tx_frmgen_burst_enable + Enable frame generator burst control + 0 + + + enable_port_tx_enh_frame + Enable tx_enh_frame port + 0 + + + enable_port_tx_enh_frame_diag_status + Enable tx_enh_frame_diag_status port + 0 + + + enable_port_tx_enh_frame_burst_en + Enable tx_enh_frame_burst_en port + 0 + + + enh_rx_frmsync_enable + Enable Interlaken frame synchronizer + 0 + + + enh_rx_frmsync_mfrm_length + Frame synchronizer metaframe length + 2048 + + + enable_port_rx_enh_frame + Enable rx_enh_frame port + 0 + + + enable_port_rx_enh_frame_lock + Enable rx_enh_frame_lock port + 0 + + + enable_port_rx_enh_frame_diag_status + Enable rx_enh_frame_diag_status port + 0 + + + enh_tx_crcgen_enable + Enable Interlaken TX CRC-32 generator + 0 + + + enh_tx_crcerr_enable + Enable Interlaken TX CRC-32 generator error insertion + 0 + + + enh_rx_crcchk_enable + Enable Interlaken RX CRC-32 checker + 0 + + + enable_port_rx_enh_crc32_err + Enable rx_enh_crc32_err port + 0 + + + enable_port_rx_enh_highber + Enable rx_enh_highber port (10GBASE-R) + 1 + + + enable_port_rx_enh_highber_clr_cnt + Enable rx_enh_highber_clr_cnt port (10GBASE-R) + 0 + + + enable_port_rx_enh_clr_errblk_count + Enable rx_enh_clr_errblk_count port (10GBASE-R & FEC) + 0 + + + enh_tx_64b66b_enable + Enable TX 64b/66b encoder + 1 + + + enh_rx_64b66b_enable + Enable RX 64b/66b decoder + 1 + + + enh_tx_sh_err + Enable TX sync header error insertion + 0 + + + enh_tx_scram_enable + Enable TX scrambler (10GBASE-R/Interlaken) + 1 + + + enh_tx_scram_seed + TX scrambler seed (10GBASE-R/Interlaken) + 288230376151711743 + + + enh_rx_descram_enable + Enable RX descrambler (10GBASE-R/Interlaken) + 1 + + + enh_tx_dispgen_enable + Enable Interlaken TX disparity generator + 0 + + + enh_rx_dispchk_enable + Enable Interlaken RX disparity checker + 0 + + + enh_tx_randomdispbit_enable + Enable Interlaken TX random disparity bit + 0 + + + enh_rx_blksync_enable + Enable RX block synchronizer + 1 + + + enable_port_rx_enh_blk_lock + Enable rx_enh_blk_lock port + 1 + + + enh_tx_bitslip_enable + Enable TX data bitslip + 0 + + + enh_tx_polinv_enable + Enable TX data polarity inversion + 0 + + + enh_rx_bitslip_enable + Enable RX data bitslip + 0 + + + enh_rx_polinv_enable + Enable RX data polarity inversion + 0 + + + enable_port_tx_enh_bitslip + Enable tx_enh_bitslip port + 0 + + + enable_port_rx_enh_bitslip + Enable rx_bitslip port + 0 + + + enh_rx_krfec_err_mark_enable + Enable RX KR-FEC error marking + 0 + + + enh_rx_krfec_err_mark_type + Error marking type + 10G + + + enh_tx_krfec_burst_err_enable + Enable KR-FEC TX error insertion + 0 + + + enh_tx_krfec_burst_err_len + KR-FEC TX error insertion spacing + 1 + + + enable_port_krfec_tx_enh_frame + Enable tx_enh_frame port + 0 + + + enable_port_krfec_rx_enh_frame + Enable rx_enh_frame port + 0 + + + enable_port_krfec_rx_enh_frame_diag_status + Enable rx_enh_frame_diag_status port + 0 + + + pcs_direct_width + PCS Direct interface width + 8 + + + enable_tx_fast_pipeln_reg + Enable TX fast pipeline registers + 0 + + + enable_rx_fast_pipeln_reg + Enable RX fast pipeline registers + 0 + + + parallel_loopback_mode + Parallel loopback mode + disable + + + loopback_tx_clk_sel + Parallel loopback mode TX clock source selection + internal_clk + + + enable_debug_ports + Enable PCS reset status ports + 1 + + + enable_advanced_user_mode + Enable advanced user mode + 0 + + + tx_fifo_mode + TX Core Interface FIFO mode + Phase compensation + + + tx_fifo_pfull + TX FIFO partially full threshold + 10 + + + tx_fifo_pempty + TX FIFO partially empty threshold + 2 + + + enable_port_tx_fifo_full + Enable tx_fifo_full port + 1 + + + enable_port_tx_fifo_empty + Enable tx_fifo_empty port + 1 + + + enable_port_tx_fifo_pfull + Enable tx_fifo_pfull port + 1 + + + enable_port_tx_fifo_pempty + Enable tx_fifo_pempty port + 1 + + + enable_port_tx_pcs_fifo_full + Enable tx_pcs_fifo_full port + 0 + + + enable_port_tx_pcs_fifo_empty + Enable tx_pcs_fifo_empty port + 0 + + + enable_port_tx_dll_lock + Enable tx_dll_lock port + 0 + + + rx_fifo_mode + RX PCS-Core Interface FIFO mode (PCS FIFO-Core FIFO) + 10GBase-R + + + rx_fifo_pfull + RX FIFO partially full threshold + 25 + + + rx_fifo_pempty + RX FIFO partially empty threshold + 4 + + + rx_fifo_align_del + Enable RX FIFO alignment word deletion (Interlaken) + 0 + + + rx_fifo_control_del + Enable RX FIFO control word deletion (Interlaken) + 0 + + + enable_port_rx_data_valid + Enable rx_data_valid port + 0 + + + enable_port_rx_fifo_full + Enable rx_fifo_full port + 1 + + + enable_port_rx_fifo_empty + Enable rx_fifo_empty port + 1 + + + enable_port_rx_fifo_pfull + Enable rx_fifo_pfull port + 0 + + + enable_port_rx_fifo_pempty + Enable rx_fifo_pempty port + 0 + + + enable_port_rx_fifo_del + Enable rx_fifo_del port (10GBASE-R) + 1 + + + enable_port_rx_fifo_insert + Enable rx_fifo_insert port (10GBASE-R) + 1 + + + enable_port_rx_fifo_rd_en + Enable rx_fifo_rd_en port + 0 + + + enable_port_rx_fifo_align_clr + Enable rx_fifo_align_clr port (Interlaken) + 0 + + + enable_port_rx_pcs_fifo_full + Enable rx_pcs_fifo_full port + 0 + + + enable_port_rx_pcs_fifo_empty + Enable rx_pcs_fifo_empty port + 0 + + + tx_clkout_sel + Selected tx_clkout clock source + pma_div_clkout + + + enable_port_tx_clkout2 + Enable tx_clkout2 port + 0 + + + tx_clkout2_sel + Selected tx_clkout2 clock source + pcs_clkout + + + enable_port_tx_clkout_hioint + Enable tx_clkout_hioint port + 0 + + + enable_port_tx_clkout2_hioint + Enable tx_clkout2_hioint port + 0 + + + tx_pma_div_clkout_divider + TX pma_div_clkout division factor + 2 + + + tx_coreclkin_clock_network + Selected tx_coreclkin clock network + dedicated + + + tx_pcs_bonding_clock_network + Selected TX PCS bonding clock network + dedicated + + + rx_clkout_sel + Selected rx_clkout clock source + pma_div_clkout + + + enable_port_rx_clkout2 + Enable rx_clkout2 port + 0 + + + rx_clkout2_sel + Selected rx_clkout2 clock source + pcs_clkout + + + enable_port_rx_clkout_hioint + Enable rx_clkout_hioint port + 0 + + + enable_port_rx_clkout2_hioint + Enable rx_clkout2_hioint port + 0 + + + rx_pma_div_clkout_divider + RX pma_div_clkout division factor + 2 + + + rx_coreclkin_clock_network + Selected rx_coreclkin clock network + dedicated + + + osc_clk_divider + OSC clock division factor + 1 + + + enable_port_tx_fifo_latency_adj_ena + Enable TX FIFO latency adjustment port + 0 + + + enable_port_rx_fifo_latency_adj_ena + Enable RX FIFO latency adjustment port + 0 + + + enable_port_latency_measurement + Enable latency measurement ports + 0 + + + enable_port_clock_delay_measurement + Enable clock delay measurement ports + 0 + + + delay_measurement_clkout_sel + Selected delay_measurement_clkout clock source + clock_delay_measurement_clkout + + + delay_measurement_clkout2_sel + Selected delay_measurement_clkout2 clock source + clock_delay_measurement_clkout + + + generate_docs + Generate parameter documentation file + 1 + + + generate_add_hdl_instance_example + Generate '_hw.tcl' 'add_hdl_instance' example file + 0 + + + validation_rule_select + View validation rule for parameter + + + + enable_tx_coreclkin2 + Enable tx_coreclkin2 port + 0 + + + ovrd_tx_dv_mode + Enable TX Data Valid Gen manual setting + 0 + + + usr_tx_dv_mode + Generate TX Data Valid by Core AIB FIFO + enable + + + ovrd_rx_dv_mode + Enable RX Data Valid Rcv manual setting + 0 + + + usr_rx_dv_mode + Consume RX Data Valid by Core AIB FIFO + enable + + + rcfg_shared + Share reconfiguration interface + 0 + + + rcfg_use_clk_reset_only + Use AVMM clock and reset ports only + 0 + + + set_embedded_debug_enable + Enable embedded debug + 0 + + + set_prbs_soft_logic_enable + Enable prbs soft accumulators + 0 + + + set_odi_soft_logic_enable + Enable odi acceleration logic + 0 + + + enable_rcfg_tx_digitalreset_release_ctrl + Enable rcfg_tx_digitalreset_release_ctrl port + 0 + + + suppress_design_example_messages + suppress_design_example_messages + 0 + + + enable_workaround_rules + Enable workaround rules + 0 + + + tx_pll_type + Tx PLL type + ATX + + + tx_pll_refclk + Tx PLL reference clock frequency + 125.0 + + + use_tx_clkout2 + Use tx_clkout2 as source for tx_coreclkin + 0 + + + use_rx_clkout2 + Use rx_clkout2 as source for rx_coreclkin + 0 + + + enable_de_hardware_debug + Enable soft register map for System Console + 0 + + + enable_fast_sim + Enable fast simulations + 0 + + + enable_mac_total_control + Enable MAC total control of PHY settings + 0 + + + enable_insert_eios_err + Enable PCIe EIOS error insertion + 0 + + + tile_type_suffix + Xcvr Tile Type Suffix + + + + design_example_filename + Design example filename + top + + + anlg_voltage + VCCR_GXB and VCCT_GXB supply voltage for the Transceiver + 1_0V + + + anlg_link + Tranceiver Link Type + sr + + + enable_ports_adaptation + Enable adaptation control ports + 0 + + + qsf_assignments_enable + Provide sample QSF assignments + 1 + + + tx_pma_analog_mode + TX PMA analog mode rules + user_custom + + + rx_pma_analog_mode + RX PMA analog mode rules + user_custom + + + tx_pma_optimal_settings + Use default TX PMA analog settings + 1 + + + tx_pma_output_swing_ctrl + Output Swing Level (VOD) + 12 + + + tx_pma_pre_emp_sign_pre_tap_1t + Pre-Emphasis First Pre-Tap Polarity + negative + + + tx_pma_pre_emp_switching_ctrl_pre_tap_1t + Pre-Emphasis First Pre-Tap Magnitude + 0 + + + tx_pma_pre_emp_sign_1st_post_tap + Pre-Emphasis First Post-Tap Polarity + negative + + + tx_pma_pre_emp_switching_ctrl_1st_post_tap + Pre-Emphasis First Post-Tap Magnitude + 0 + + + tx_pma_slew_rate_ctrl + Slew Rate Control + 0 + + + tx_pma_term_sel + On-Chip Termination + r_r1 + + + tx_pma_compensation_en + High Speed Compensation + enable + + + rx_pma_optimal_settings + Use default RX PMA analog settings + 1 + + + rx_pma_adapt_mode + RX adaptation mode + ctle_dfe_tap1 + + + rx_pma_term_sel + RX On-chip Termination + r_r4 + + + rx_ctle_ac_gain + CTLE AC Gain + 0 + + + rx_ctle_eq_gain + CTLE EQ Gain + 0 + + + rx_vga_dc_gain + VGA DC Gain + 0 + + + rx_pma_adapt_start_gui + Start PMA DFE Auto Adaptation + 0 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element xcvr_native_s10_htile_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/ipss/hssi/s10/ip/pll_atxpll/altera_xcvr_atx_pll_ip.ip b/ipss/hssi/s10/ip/pll_atxpll/altera_xcvr_atx_pll_ip.ip new file mode 100755 index 0000000..8326948 --- /dev/null +++ b/ipss/hssi/s10/ip/pll_atxpll/altera_xcvr_atx_pll_ip.ip @@ -0,0 +1,814 @@ + + + + Intel Corporation + altera_xcvr_atx_pll_ip + xcvr_atx_pll_s10_htile_0 + 19.1.1 + + + pll_refclk0 + + + + + + + + clk + + + pll_refclk0 + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + input + + + + + + + tx_serial_clk + + + + + + + + clk + + + tx_serial_clk + + + + + + + + + clockRate + Clock rate + 0 + + + + + + + ui.blockdiagram.direction + output + + + + + + + pll_locked + + + + + + + + pll_locked + + + pll_locked + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + pll_cal_busy + + + + + + + + pll_cal_busy + + + pll_cal_busy + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_xcvr_atx_pll_s10_htile + + QUARTUS_SYNTH + + + + + + pll_refclk0 + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + tx_serial_clk + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + pll_locked + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + pll_cal_busy + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + altera_xcvr_atx_pll_ip + altera_xcvr_atx_pll_s10_htile + 19.1.1 + + + + + rcfg_debug + rcfg_debug + 0 + + + rcfg_enable + Enable dynamic reconfiguration + 0 + + + rcfg_jtag_enable + Enable Native PHY Debug Master Endpoint + 0 + + + rcfg_separate_avmm_busy + Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE + 0 + + + rcfg_enable_avmm_busy_port + Enable avmm_busy port + 0 + + + set_capability_reg_enable + Enable capability registers + 0 + + + set_user_identifier + Set user-defined IP identifier + 0 + + + set_csr_soft_logic_enable + Enable control and status registers + 0 + + + rcfg_file_prefix + Configuration file prefix + altera_xcvr_atx_pll_s10 + + + rcfg_files_as_common_package + Declare SystemVerilog package file as common package file + 0 + + + rcfg_sv_file_enable + Generate SystemVerilog package file + 0 + + + rcfg_h_file_enable + Generate C header file + 0 + + + rcfg_txt_file_enable + Generate text file + 0 + + + rcfg_mif_file_enable + Generate MIF (Memory Initialize File) + 0 + + + rcfg_multi_enable + Enable multiple reconfiguration profiles + 0 + + + set_rcfg_emb_strm_enable + Enable embedded reconfiguration streamer + 0 + + + rcfg_reduced_files_enable + Generate reduced reconfiguration files + 0 + + + rcfg_profile_cnt + Number of reconfiguration profiles + 2 + + + rcfg_profile_select + Store current configuration to profile: + 1 + + + rcfg_profile_data0 + rcfg_profile_data0 + + + + rcfg_profile_data1 + rcfg_profile_data1 + + + + rcfg_profile_data2 + rcfg_profile_data2 + + + + rcfg_profile_data3 + rcfg_profile_data3 + + + + rcfg_profile_data4 + rcfg_profile_data4 + + + + rcfg_profile_data5 + rcfg_profile_data5 + + + + rcfg_profile_data6 + rcfg_profile_data6 + + + + rcfg_profile_data7 + rcfg_profile_data7 + + + + rcfg_sdc_derived_profile_data0 + rcfg_sdc_derived_profile_data0 + + + + rcfg_sdc_derived_profile_data1 + rcfg_sdc_derived_profile_data1 + + + + rcfg_sdc_derived_profile_data2 + rcfg_sdc_derived_profile_data2 + + + + rcfg_sdc_derived_profile_data3 + rcfg_sdc_derived_profile_data3 + + + + rcfg_sdc_derived_profile_data4 + rcfg_sdc_derived_profile_data4 + + + + rcfg_sdc_derived_profile_data5 + rcfg_sdc_derived_profile_data5 + + + + rcfg_sdc_derived_profile_data6 + rcfg_sdc_derived_profile_data6 + + + + rcfg_sdc_derived_profile_data7 + rcfg_sdc_derived_profile_data7 + + + + enable_manual_configuration + enable_manual_configuration + 1 + + + generate_add_hdl_instance_example + Generate '_hw.tcl' 'add_hdl_instance' example file + 0 + + + device_family + device_family + Stratix 10 + + + device + device + 1SX280HN2F43E2VG + + + base_device + base_device + cr2v0 + + + device_die_types + device_die_types + HSSI_CRETE2E,MAIN_ND5 + + + device_die_revisions + device_die_revisions + HSSI_CRETE2E_REVB,MAIN_ND5_REVC + + + test_mode + Enable Test Mode + 0 + + + enable_pld_atx_cal_busy_port + enable_pld_atx_cal_busy_port + 1 + + + enable_debug_ports_parameters + Enable debug ports & parameters + 0 + + + support_mode + Support mode + user_mode + + + message_level + Message level for rule violations + error + + + prot_mode + Protocol mode + Basic + + + bw_sel + Bandwidth + low + + + refclk_cnt + Number of PLL reference clocks + 1 + + + refclk_index + Selected reference clock source + 0 + + + silicon_rev + Silicon revision ES + false + + + primary_pll_buffer + Primary PLL clock output buffer + GX clock output buffer + + + enable_pll_lock + Enable ATX PLL lock output port + 1 + + + enable_8G_path + Enable GX clock output port (tx_serial_clk) + 1 + + + enable_28G_output_frm_abv_atx + Enable GXT clock output port to above ATX PLL (gxt_output_to_abv_atx) + 0 + + + enable_28G_output_frm_blw_atx + Enable GXT clock output port to below ATX PLL (gxt_output_to_blw_atx) + 0 + + + enable_28G_local_atx_path + Enable GXT local clock output port (tx_serial_clk_gxt) + 0 + + + enable_28G_input_frm_abv_atx + Enable GXT clock input port from above ATX PLL (gxt_input_from_abv_atx) + 0 + + + enable_28G_input_frm_blw_atx + Enable GXT clock input port from below ATX PLL (gxt_input_from_blw_atx) + 0 + + + enable_GXT_out_buffer_abv + Enable GXT clock buffer to above ATX PLL + 0 + + + enable_GXT_out_buffer_blw + Enable GXT clock buffer to below ATX PLL + 0 + + + enable_GXT_clock_source + GXT output clock source + disabled + + + enable_pcie_clk + Enable PCIe clock output port + 0 + + + enable_cascade_out + Enable cascade clock output port + 0 + + + enable_hip_cal_done_port + Enable calibration status ports for HIP + 0 + + + set_hip_cal_en + Enable PCIe hard IP calibration + 0 + + + set_output_clock_frequency + PLL output frequency + 5156.25 + + + set_auto_reference_clock_frequency + PLL auto mode reference clock frequency (Integer) + 644.53125 + + + set_manual_reference_clock_frequency + PLL manual mode reference clock frequency + 200.0 + + + set_fref_clock_frequency + PLL auto mode reference clock frequency (Fractional) + 156.25 + + + set_m_counter + Multiply factor (M-Counter) + 24 + + + set_ref_clk_div + Divide factor (N-Counter) + 1 + + + set_l_counter + Divide factor (L-Counter) + 4 + + + set_l_cascade_counter + Divide factor (L-Cascade Counter) + 4 + + + set_l_cascade_predivider + Divide factor (L-Cascade-Predivider) + 1 + + + set_k_counter + Fractional multiply factor (K) + 1 + + + set_altera_xcvr_atx_pll_s10_calibration_en + Enable calibration + 1 + + + enable_analog_resets + Enable pll_powerdown and mcgb_rst ports + 0 + + + enable_ext_lockdetect_ports + Enable clklow and fref ports + 0 + + + enable_vco_bypass + Enable VCO Bypass feature + 0 + + + enable_pcie_hip_connectivity + enable_pcie_hip_connectivity + 0 + + + usr_analog_voltage + VCCR_GXB and VCCT_GXB supply voltage for the Transceiver + 1_0V + + + enable_mcgb + Include Master Clock Generation Block + 0 + + + mcgb_div + Clock division factor + 1 + + + enable_hfreq_clk + Enable x24 non-bonded high-speed clock output port + 0 + + + enable_mcgb_pcie_clksw + Enable PCIe clock switch interface + 0 + + + enable_mcgb_reset + Enable mcgb_rst and mcgb_rst_stat ports + 0 + + + mcgb_aux_clkin_cnt + Number of auxiliary MCGB clock input ports. + 0 + + + enable_bonding_clks + Enable bonding clock output ports + 0 + + + enable_fb_comp_bonding + Enable feedback compensation bonding + 0 + + + pma_width + PMA interface width + 64 + + + enable_pld_mcgb_cal_busy_port + enable_pld_mcgb_cal_busy_port + 0 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element xcvr_atx_pll_s10_htile_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/ipss/hssi/s10/ip/pll_mpll/pll.ip b/ipss/hssi/s10/ip/pll_mpll/pll.ip new file mode 100755 index 0000000..53d1ef4 --- /dev/null +++ b/ipss/hssi/s10/ip/pll_mpll/pll.ip @@ -0,0 +1,934 @@ + + + + Intel Corporation + pll + xcvr_fpll_s10_htile_0 + 19.1.2 + + + pll_refclk0 + + + + + + + + clk + + + pll_refclk0 + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + input + + + + + + + outclk_div1 + + + + + + + + clk + + + outclk_div1 + + + + + + + + + associatedDirectClock + Associated direct clock + + + + clockRate + Clock rate + 0 + + + clockRateKnown + Clock rate known + false + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + output + + + + + + + outclk_div2 + + + + + + + + clk + + + outclk_div2 + + + + + + + + + associatedDirectClock + Associated direct clock + + + + clockRate + Clock rate + 0 + + + clockRateKnown + Clock rate known + false + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + ui.blockdiagram.direction + output + + + + + + + pll_locked + + + + + + + + pll_locked + + + pll_locked + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + pll_cal_busy + + + + + + + + pll_cal_busy + + + pll_cal_busy + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_xcvr_fpll_s10_htile + + QUARTUS_SYNTH + + + + + + pll_refclk0 + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + outclk_div1 + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + outclk_div2 + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + pll_locked + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + pll_cal_busy + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + pll + altera_xcvr_fpll_s10_htile + 19.1.2 + + + + + rcfg_debug + rcfg_debug + 0 + + + rcfg_enable + Enable dynamic reconfiguration + 0 + + + rcfg_jtag_enable + Enable Native PHY Debug Master Endpoint + 0 + + + rcfg_separate_avmm_busy + Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE + 0 + + + rcfg_enable_avmm_busy_port + Enable avmm_busy port + 0 + + + set_capability_reg_enable + Enable capability registers + 0 + + + set_user_identifier + Set user-defined IP identifier + 0 + + + set_csr_soft_logic_enable + Enable control and status registers + 0 + + + rcfg_file_prefix + Configuration file prefix + altera_xcvr_fpll_s10 + + + rcfg_files_as_common_package + Declare SystemVerilog package file as common package file + 0 + + + rcfg_sv_file_enable + Generate SystemVerilog package file + 0 + + + rcfg_h_file_enable + Generate C header file + 0 + + + rcfg_txt_file_enable + Generate text file + 0 + + + rcfg_mif_file_enable + Generate MIF (Memory Initialize File) + 0 + + + rcfg_multi_enable + Enable multiple reconfiguration profiles + 0 + + + set_rcfg_emb_strm_enable + Enable embedded reconfiguration streamer + 0 + + + rcfg_reduced_files_enable + Generate reduced reconfiguration files + 0 + + + rcfg_profile_cnt + Number of reconfiguration profiles + 2 + + + rcfg_profile_select + Store current configuration to profile: + 1 + + + rcfg_profile_data0 + rcfg_profile_data0 + + + + rcfg_profile_data1 + rcfg_profile_data1 + + + + rcfg_profile_data2 + rcfg_profile_data2 + + + + rcfg_profile_data3 + rcfg_profile_data3 + + + + rcfg_profile_data4 + rcfg_profile_data4 + + + + rcfg_profile_data5 + rcfg_profile_data5 + + + + rcfg_profile_data6 + rcfg_profile_data6 + + + + rcfg_profile_data7 + rcfg_profile_data7 + + + + rcfg_sdc_derived_profile_data0 + rcfg_sdc_derived_profile_data0 + + + + rcfg_sdc_derived_profile_data1 + rcfg_sdc_derived_profile_data1 + + + + rcfg_sdc_derived_profile_data2 + rcfg_sdc_derived_profile_data2 + + + + rcfg_sdc_derived_profile_data3 + rcfg_sdc_derived_profile_data3 + + + + rcfg_sdc_derived_profile_data4 + rcfg_sdc_derived_profile_data4 + + + + rcfg_sdc_derived_profile_data5 + rcfg_sdc_derived_profile_data5 + + + + rcfg_sdc_derived_profile_data6 + rcfg_sdc_derived_profile_data6 + + + + rcfg_sdc_derived_profile_data7 + rcfg_sdc_derived_profile_data7 + + + + enable_manual_configuration + enable_manual_configuration + 1 + + + generate_docs + Generate parameter documentation file + 1 + + + generate_add_hdl_instance_example + Generate '_hw.tcl' 'add_hdl_instance' example file + 0 + + + device_family + device_family + Stratix 10 + + + device + device + 1SX280HN2F43E2VG + + + base_device + base_device + cr2v0 + + + device_die_types + device_die_types + HSSI_CRETE2E,MAIN_ND5 + + + device_die_revisions + device_die_revisions + HSSI_CRETE2E_REVB,MAIN_ND5_REVC + + + set_x1_core_clock + Enable /1 output clock + true + + + set_x2_core_clock + Enable /2 output clock + true + + + set_x4_core_clock + Enable /4 output clock + false + + + set_primary_use + FPLL Mode + 0 + + + test_mode + Enable Test Mode + false + + + enable_pld_fpll_cal_busy_port + enable_pld_fpll_cal_busy_port + 1 + + + usr_enable_vco_bypass + Enable FPLL VCO Bypass + false + + + enable_debug_ports_parameters + Enable debug ports && parameters + 0 + + + support_mode + Support mode + user_mode + + + message_level + Message level for rule violations + error + + + powerdown_mode + powerdown_mode + powerup + + + set_prot_mode + Protocol mode + 0 + + + set_bw_sel + Bandwidth + medium + + + set_refclk_cnt + Number of PLL reference clocks + 1 + + + set_refclk_index + Selected reference clock source + 0 + + + silicon_rev + Silicon revision ES + false + + + set_enable_hclk_out + Enable PCIe clock output port + 0 + + + enable_hip_cal_done_port + Enable calibration status ports for HIP + 0 + + + enable_mcgb_hip_cal_done_port + Enable MCGB calibration status ports for HIP + 0 + + + set_hip_cal_en + Enable PCIe hard IP calibration + 0 + + + set_output_clock_frequency + PLL output frequency + 312.5 + + + set_manual_output_clock_frequency + PLL output frequency + 2500.0 + + + set_enable_fractional + Enable fractional mode + 0 + + + set_auto_reference_clock_frequency + PLL integer mode reference clock frequency + 644.53125 + + + set_manual_reference_clock_frequency + PLL reference clock frequency + 100.0 + + + set_fref_clock_frequency + PLL fractional mode reference clock frequency + 100.0 + + + set_initial_phase_shift_units + PLL phase shift units + degrees + + + set_initial_phase_shift + PLL initial phase shift + 0.0 + + + set_enable_dps + Enable dynamic phase shift + 0 + + + select_manual_config + Configure counters manually + false + + + set_manual_m_counter + Multiply factor (M-Counter) + 50 + + + set_manual_ref_clk_div + Divide factor (N-Counter) + 1 + + + set_manual_l_counter + Divide factor (L-Counter) + 2 + + + set_manual_c_counter + Divide factor (C-Counter) + 4 + + + set_manual_k_counter + Fractional multiply factor (K) + 1 + + + set_altera_xcvr_fpll_s10_calibration_en + Enable calibration + 1 + + + outclk_en + outclk_en + false + + + enable_pcie_hip_connectivity + enable_pcie_hip_connectivity + 0 + + + set_power_mode + VCCR_GXB and VCCT_GXB supply voltage for the Transceiver: + 1_0V + + + enable_analog_resets + Enable pll_powerdown and mcgb_rst ports + false + + + enable_mcgb + Include Master Clock Generation Block + 0 + + + mcgb_div + Clock division factor + 1 + + + enable_hfreq_clk + Enable x24 non-bonded high-speed clock output port + 0 + + + enable_mcgb_pcie_clksw + Enable PCIe clock switch interface + 0 + + + enable_mcgb_reset + Enable mcgb_rst and mcgb_rst_stat ports + 0 + + + mcgb_aux_clkin_cnt + Number of auxiliary MCGB clock input ports. + 0 + + + enable_bonding_clks + Enable bonding clock output ports + 0 + + + enable_fb_comp_bonding + Enable feedback compensation bonding + 0 + + + pma_width + PMA interface width + 64 + + + enable_pld_mcgb_cal_busy_port + enable_pld_mcgb_cal_busy_port + 0 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element xcvr_fpll_s10_htile_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>outclk_div1</key> + <value> + <connectionPointName>outclk_div1</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>outclk_div2</key> + <value> + <connectionPointName>outclk_div2</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/ipss/hssi/s10/ip/xcvr_reset_controller/reset_control.ip b/ipss/hssi/s10/ip/xcvr_reset_controller/reset_control.ip new file mode 100755 index 0000000..5176e55 --- /dev/null +++ b/ipss/hssi/s10/ip/xcvr_reset_controller/reset_control.ip @@ -0,0 +1,1255 @@ + + + + Intel Corporation + reset_control + xcvr_reset_control_s10_0 + 19.1.1 + + + clock + + + + + + + + clk + + + clock + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset + + + reset + + + + + + + + + associatedClock + Associated clock + + + + synchronousEdges + Synchronous edges + NONE + + + + + tx_analogreset + + + + + + + + tx_analogreset + + + tx_analogreset + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + tx_digitalreset + + + + + + + + tx_digitalreset + + + tx_digitalreset + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + tx_ready + + + + + + + + tx_ready + + + tx_ready + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + pll_locked + + + + + + + + pll_locked + + + pll_locked + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + input + + + + + + + pll_select + + + + + + + + pll_select + + + pll_select + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + input + + + + + + + tx_cal_busy + + + + + + + + tx_cal_busy + + + tx_cal_busy + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + input + + + + + + + tx_analogreset_stat + + + + + + + + tx_analogreset_stat + + + tx_analogreset_stat + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + input + + + + + + + tx_digitalreset_stat + + + + + + + + tx_digitalreset_stat + + + tx_digitalreset_stat + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + input + + + + + + + rx_analogreset + + + + + + + + rx_analogreset + + + rx_analogreset + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + rx_digitalreset + + + + + + + + rx_digitalreset + + + rx_digitalreset + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + rx_ready + + + + + + + + rx_ready + + + rx_ready + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + rx_is_lockedtodata + + + + + + + + rx_is_lockedtodata + + + rx_is_lockedtodata + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + input + + + + + + + rx_cal_busy + + + + + + + + rx_cal_busy + + + rx_cal_busy + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + input + + + + + + + rx_analogreset_stat + + + + + + + + rx_analogreset_stat + + + rx_analogreset_stat + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + input + + + + + + + rx_digitalreset_stat + + + + + + + + rx_digitalreset_stat + + + rx_digitalreset_stat + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + input + + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_xcvr_reset_control_s10 + + QUARTUS_SYNTH + + + + + + clock + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + reset + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + tx_analogreset + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + tx_digitalreset + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + tx_ready + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + pll_locked + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + pll_select + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + tx_cal_busy + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + tx_analogreset_stat + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + tx_digitalreset_stat + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_analogreset + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_digitalreset + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_ready + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_is_lockedtodata + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_cal_busy + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_analogreset_stat + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + rx_digitalreset_stat + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + reset_control + altera_xcvr_reset_control_s10 + 19.1.1 + + + + + device_family + device_family + Stratix 10 + + + TILE_TYPE + Tile type of Native PHY IP + h_tile + + + CHANNELS + Number of transceiver channels + 1 + + + PLLS + Number of TX PLLs + 1 + + + SYS_CLK_IN_MHZ + Input clock frequency + 125 + + + REDUCED_SIM_TIME + Use fast reset for simulation + 1 + + + ENABLE_DIGITAL_SEQ + Sequence RX digital reset after TX digital reset + 0 + + + gui_split_interfaces + Separate interface per channel/PLL + 0 + + + TX_PLL_ENABLE + Enable TX PLL reset control + 0 + + + T_PLL_POWERDOWN + pll_powerdown duration + 1000 + + + TX_ENABLE + Enable TX channel reset control + 1 + + + TX_PER_CHANNEL + Use separate TX reset per channel + 0 + + + TX_MANUAL_RESET + TX digital reset mode + 0 + + + T_TX_ANALOGRESET + tx_analogreset duration + 0 + + + T_TX_DIGITALRESET + tx_digitalreset duration + 20 + + + T_PLL_LOCK_HYST + pll_locked input hysteresis + 0 + + + gui_pll_cal_busy + Enable pll_cal_busy input port + 0 + + + RX_ENABLE + Enable RX channel reset control + 1 + + + RX_PER_CHANNEL + Use separate RX reset per channel + 0 + + + RX_MANUAL_RESET + RX digital reset mode + 0 + + + T_RX_ANALOGRESET + rx_analogreset duration + 40 + + + T_RX_DIGITALRESET + rx_digitalreset duration + 5000 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element xcvr_reset_control_s10_0 + { + datum _originalDeviceFamily + { + value = "Stratix 10"; + type = "String"; + } + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + true + + + lockedInterfaceDefinition + lockedInterfaceDefinition + + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/ipss/hssi/s10/lib/ofs_fim_eth_plat_clocks_noprune.sv b/ipss/hssi/s10/lib/ofs_fim_eth_plat_clocks_noprune.sv new file mode 100755 index 0000000..0525260 --- /dev/null +++ b/ipss/hssi/s10/lib/ofs_fim_eth_plat_clocks_noprune.sv @@ -0,0 +1,37 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// For use in green_bs: consume and preserve Ethernet PR clocks. +// +//----------------------------------------------------------------------------- + +module ofs_fim_eth_plat_clocks_noprune ( + input ofs_fim_eth_plat_if_pkg::t_eth_clocks eth_clocks +); + + (* noprune *) logic clk_q1, clk_q2; + always_ff @(posedge eth_clocks.clk) begin + clk_q1 <= clk_q2; + clk_q2 <= ~clk_q1; + + // Generally force 0 when not in reset to reduce power (the opposite of normal) + if (eth_clocks.rst_n) begin + clk_q1 <= 1'b0; + end + end + + (* noprune *) logic clkDiv2_q1, clkDiv2_q2; + always_ff @(posedge eth_clocks.clkDiv2) begin + clkDiv2_q1 <= clkDiv2_q2; + clkDiv2_q2 <= ~clkDiv2_q1; + + // Generally force 0 when not in reset to reduce power (the opposite of normal) + if (eth_clocks.rstDiv2_n) begin + clkDiv2_q1 <= 1'b0; + end + end + +endmodule // ofs_fim_eth_plat_clocks_noprune diff --git a/ipss/hssi/s10/lib/pipe_hssi_ch.v b/ipss/hssi/s10/lib/pipe_hssi_ch.v new file mode 100755 index 0000000..c24f9fe --- /dev/null +++ b/ipss/hssi/s10/lib/pipe_hssi_ch.v @@ -0,0 +1,98 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +//----------------------------------------------------------------------------- +// Description: hssi avst pipeline register +//----------------------------------------------------------------------------- + +`timescale 1 ps / 1 ps +module pipe_hssi_ch +#( + parameter MODE = 0, // 0: skid buffer 1: simple buffer 2: simple buffer (bubble) 3: bypass + parameter TREADY_RST_VAL = 0, // 0: tready deasserted during reset + // 1: tready asserted during reset + parameter ENABLE_TKEEP = 0, + parameter ENABLE_TLAST = 0, + parameter ENABLE_TID = 0, + parameter ENABLE_TDEST = 0, + parameter ENABLE_TUSER = 0, + + parameter TDATA_WIDTH = 512, + parameter TID_WIDTH = 8, + parameter TDEST_WIDTH = 8, + parameter TUSER_WIDTH = 10, + + parameter PL_DEPTH = 1 + +)( + input logic clk, + input logic rst_n, + + output logic s_ready, + input logic s_valid, + input logic [TDATA_WIDTH-1:0] s_data, + + input logic m_ready, + output logic m_valid, + output logic [TDATA_WIDTH-1:0] m_data + +); + + reg [PL_DEPTH:0] pipe_ready; + reg [PL_DEPTH:0][TDATA_WIDTH-1:0] pipe_data; + reg [PL_DEPTH:0] pipe_valid; + +always_comb begin + + s_ready = pipe_ready[0]; + pipe_data[0] = s_data; + pipe_valid[0] = s_valid; + + m_valid = pipe_valid[PL_DEPTH]; + m_data = pipe_data[PL_DEPTH]; + pipe_ready[PL_DEPTH] = m_ready; +end + +genvar n; +generate + for(n=0; n1 + parameter WIDTH = 1, // Number of bits to resync + parameter SLOW_CLOCK = 0, // See description above + parameter INIT_VALUE = 0, + parameter NO_CUT = 1 // See description above + ) ( + input wire clk, + input wire reset, + input wire [WIDTH-1:0] d, + output wire [WIDTH-1:0] q + ); + +localparam INT_LEN = (SYNC_CHAIN_LENGTH > 1) ? SYNC_CHAIN_LENGTH : 2; +localparam L_INIT_VALUE = (INIT_VALUE == 1) ? 1'b1 : 1'b0; + +genvar ig; + +// Generate a synchronizer chain for each bit +generate + for(ig=0;ig 1)) & ~avm_waitrequest) next = WBURST; + else next = IDLE; + end + // Write burst state. We exit on an error (read during write) or when the write completes, or when a clear command or reset preempts + state[WBURST_BIT]: begin + if (avs_read) begin // If a read occurs during write, we'll still let this write through but we'll flag an error and move to completion + next = WCOMPL; + end + else if (!avm_waitrequest & avs_write & (wcompl_count == 2) & !log_clear) next = IDLE; // Write burst is ending + else if (log_clear | afu_reset) next = WCOMPL; // Preempted by clear or reset + else next = WBURST; // Continue bursting + end + // Write completion state. We get here from the burst state + state[WCOMPL_BIT]: begin + if (wcompl_count == 2) begin + if(log_error) next = ERROR; + else next = IDLE; + end + else next = WCOMPL; + end + // Clear state. We got here from the IDLE state + state[CLEAR_BIT]: + begin + if(~clearing) next = IDLE; // Clearing starts the same cycle we get here and ends one clock cycle before we leave + else next = CLEAR; + end + + state[ERROR_BIT]: + begin + if(afu_reset & !start_error) next = IDLE; + else next = ERROR; + end + endcase // case (1'b1) + end // always_comb begin + + //******** End State Machine ********** + //************************************* + + assign clear_address = { clear_count[ADDRESS_W-1 : BURSTCOUNT_W-1] , {(BURSTCOUNT_W-1){1'b0}} }; + + // command + assign avm_write = clearing | state[WCOMPL_BIT] | (avs_write & ~error & ~log_clear & ~state[CLEAR_BIT]) ; + + assign avm_read = avs_read & ~start_error & state[IDLE_BIT]; // only allow reads through during idle + + assign avm_byteenable = clearing ? '1 : avs_byteenable; + assign avm_writedata = clearing_data ? '0 : avs_writedata; + assign avm_burstcount = clearing ? MAX_BURST : avs_burstcount; + assign avm_address = clearing_addr ? clear_address : avs_address; + + // response + assign avs_waitrequest = avm_waitrequest | (state[CLEAR_BIT]) | (state[WCOMPL_BIT]) | (state[ERROR_BIT]); + assign avs_readdata = avm_readdata; + assign avs_readdatavalid = avm_readdatavalid; + +endmodule // avmm_chkr diff --git a/ipss/mem/axi_bridge/.gitignore b/ipss/mem/axi_bridge/.gitignore new file mode 100644 index 0000000..8433c93 --- /dev/null +++ b/ipss/mem/axi_bridge/.gitignore @@ -0,0 +1,23 @@ +*.bsf +*.cmp +*.csv +*.html +*.qgsimc +*.qgsynthc +*.sopcinfo +*.spd +*.xml +*_bb.v +*.rpt +*_inst.v +*_inst.vhd +aldec +cadence +modelsim_files.tcl +ncsim_files.tcl +riviera_files.tcl +xcelium_files.tcl +vcsmx_files.tcl +mentor +vcsmx +xcelium diff --git a/ipss/mem/axi_bridge/ddr_avmm_slave_endpoint.sv b/ipss/mem/axi_bridge/ddr_avmm_slave_endpoint.sv new file mode 100644 index 0000000..8af5d43 --- /dev/null +++ b/ipss/mem/axi_bridge/ddr_avmm_slave_endpoint.sv @@ -0,0 +1,60 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Connector component to connect DDR AXI master interface +// to QSYS interconnect +// +//----------------------------------------------------------------------------- + +module ddr_avmm_slave_endpoint #( + parameter S_ADDR_WIDTH = 27, + parameter S_DATA_WIDTH = 1024, + parameter S_BYTEENABLE_WIDTH = 128, + parameter S_BURSTCOUNT_WIDTH = 7, + + parameter M_ADDR_WIDTH = 27, + parameter M_DATA_WIDTH = 576, + parameter M_BYTEENABLE_WIDTH = 72, + parameter M_BURSTCOUNT_WIDTH = 7 +)( + input logic clk, + input logic reset, + + input logic [S_ADDR_WIDTH-1:0] s0_address, + input logic s0_write, + input logic s0_read, + input logic [S_BURSTCOUNT_WIDTH-1:0] s0_burstcount, + input logic [S_DATA_WIDTH-1:0] s0_writedata, + input logic [S_BYTEENABLE_WIDTH-1:0] s0_byteenable, + output logic s0_readdatavalid, + output logic [S_DATA_WIDTH-1:0] s0_readdata, + output logic s0_waitrequest, + + output logic [M_ADDR_WIDTH-1:0] m0_address, + output logic m0_write, + output logic m0_read, + output logic [M_BURSTCOUNT_WIDTH-1:0] m0_burstcount, + output logic [M_DATA_WIDTH-1:0] m0_writedata, + output logic [M_BYTEENABLE_WIDTH-1:0] m0_byteenable, + input logic m0_readdatavalid, + input logic [M_DATA_WIDTH-1:0] m0_readdata, + input logic m0_waitrequest +); + + // Interface connections + assign m0_address = s0_address; + assign m0_write = s0_write; + assign m0_read = s0_read; + assign m0_burstcount = s0_burstcount [0+:M_BURSTCOUNT_WIDTH]; + assign m0_writedata = s0_writedata [0+:M_DATA_WIDTH]; + assign m0_byteenable = s0_byteenable [0+:M_BYTEENABLE_WIDTH]; + + assign s0_readdatavalid = m0_readdatavalid; + assign s0_readdata = m0_readdata [0+:M_DATA_WIDTH]; + assign s0_waitrequest = m0_waitrequest; + +endmodule + diff --git a/ipss/mem/axi_bridge/ddr_avmm_slave_endpoint_hw.tcl b/ipss/mem/axi_bridge/ddr_avmm_slave_endpoint_hw.tcl new file mode 100644 index 0000000..f1b3ac5 --- /dev/null +++ b/ipss/mem/axi_bridge/ddr_avmm_slave_endpoint_hw.tcl @@ -0,0 +1,243 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# TCL File Generated by Component Editor 19.2 +# Wed Apr 29 23:39:33 PDT 2020 +# DO NOT MODIFY + + +# +# ddr_avmm_slave_endpoint "ddr_avmm_slave_endpoint" v1.0 +# Intel 2020.04.29.23:39:33 +# DDR AVMM Slave Endpoint +# + +# +# request TCL package from ACDS 19.4 +# +package require -exact qsys 19.4 + + +# +# module ddr_avmm_slave_endpoint +# +set_module_property DESCRIPTION "DDR AVMM Slave Endpoint" +set_module_property NAME ddr_avmm_slave_endpoint +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP Interface +set_module_property AUTHOR Intel +set_module_property DISPLAY_NAME ddr_avmm_slave_endpoint +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false +set_module_property LOAD_ELABORATION_LIMIT 0 + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL ddr_avmm_slave_endpoint +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file ddr_avmm_slave_endpoint.sv SYSTEM_VERILOG PATH ddr_avmm_slave_endpoint.sv TOP_LEVEL_FILE + +add_fileset SIM_VERILOG SIM_VERILOG "" "" +set_fileset_property SIM_VERILOG TOP_LEVEL ddr_avmm_slave_endpoint +set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file ddr_avmm_slave_endpoint.sv SYSTEM_VERILOG PATH ddr_avmm_slave_endpoint.sv + + +# +# parameters +# +add_parameter S_ADDR_WIDTH INTEGER 27 +set_parameter_property S_ADDR_WIDTH DEFAULT_VALUE 27 +set_parameter_property S_ADDR_WIDTH DISPLAY_NAME S_ADDR_WIDTH +set_parameter_property S_ADDR_WIDTH ENABLED false +set_parameter_property S_ADDR_WIDTH UNITS None +set_parameter_property S_ADDR_WIDTH ALLOWED_RANGES 1:64 +set_parameter_property S_ADDR_WIDTH HDL_PARAMETER true +add_parameter S_DATA_WIDTH INTEGER 1024 "" +set_parameter_property S_DATA_WIDTH DEFAULT_VALUE 1024 +set_parameter_property S_DATA_WIDTH DISPLAY_NAME S_DATA_WIDTH +set_parameter_property S_DATA_WIDTH ENABLED false +set_parameter_property S_DATA_WIDTH UNITS None +set_parameter_property S_DATA_WIDTH ALLOWED_RANGES 8:1024 +set_parameter_property S_DATA_WIDTH DESCRIPTION "" +set_parameter_property S_DATA_WIDTH HDL_PARAMETER true +add_parameter S_BYTEENABLE_WIDTH INTEGER 128 "" +set_parameter_property S_BYTEENABLE_WIDTH DEFAULT_VALUE 128 +set_parameter_property S_BYTEENABLE_WIDTH DISPLAY_NAME S_BYTEENABLE_WIDTH +set_parameter_property S_BYTEENABLE_WIDTH ENABLED false +set_parameter_property S_BYTEENABLE_WIDTH UNITS None +set_parameter_property S_BYTEENABLE_WIDTH ALLOWED_RANGES 1:128 +set_parameter_property S_BYTEENABLE_WIDTH DESCRIPTION "" +set_parameter_property S_BYTEENABLE_WIDTH HDL_PARAMETER true +add_parameter S_BURSTCOUNT_WIDTH INTEGER 7 "" +set_parameter_property S_BURSTCOUNT_WIDTH DEFAULT_VALUE 7 +set_parameter_property S_BURSTCOUNT_WIDTH DISPLAY_NAME S_BURSTCOUNT_WIDTH +set_parameter_property S_BURSTCOUNT_WIDTH ENABLED false +set_parameter_property S_BURSTCOUNT_WIDTH UNITS None +set_parameter_property S_BURSTCOUNT_WIDTH ALLOWED_RANGES 7 +set_parameter_property S_BURSTCOUNT_WIDTH DESCRIPTION "" +set_parameter_property S_BURSTCOUNT_WIDTH HDL_PARAMETER true +add_parameter M_ADDR_WIDTH INTEGER 27 +set_parameter_property M_ADDR_WIDTH DEFAULT_VALUE 27 +set_parameter_property M_ADDR_WIDTH DISPLAY_NAME M_ADDR_WIDTH +set_parameter_property M_ADDR_WIDTH ENABLED false +set_parameter_property M_ADDR_WIDTH UNITS None +set_parameter_property M_ADDR_WIDTH ALLOWED_RANGES 1:64 +set_parameter_property M_ADDR_WIDTH HDL_PARAMETER true +add_parameter M_DATA_WIDTH INTEGER 576 +set_parameter_property M_DATA_WIDTH DEFAULT_VALUE 576 +set_parameter_property M_DATA_WIDTH DISPLAY_NAME M_DATA_WIDTH +set_parameter_property M_DATA_WIDTH ENABLED false +set_parameter_property M_DATA_WIDTH UNITS None +set_parameter_property M_DATA_WIDTH ALLOWED_RANGES 8:1024 +set_parameter_property M_DATA_WIDTH HDL_PARAMETER true +add_parameter M_BYTEENABLE_WIDTH INTEGER 72 +set_parameter_property M_BYTEENABLE_WIDTH DEFAULT_VALUE 72 +set_parameter_property M_BYTEENABLE_WIDTH DISPLAY_NAME M_BYTEENABLE_WIDTH +set_parameter_property M_BYTEENABLE_WIDTH ENABLED false +set_parameter_property M_BYTEENABLE_WIDTH UNITS None +set_parameter_property M_BYTEENABLE_WIDTH ALLOWED_RANGES 1:128 +set_parameter_property M_BYTEENABLE_WIDTH HDL_PARAMETER true +add_parameter M_BURSTCOUNT_WIDTH INTEGER 7 +set_parameter_property M_BURSTCOUNT_WIDTH DEFAULT_VALUE 7 +set_parameter_property M_BURSTCOUNT_WIDTH DISPLAY_NAME M_BURSTCOUNT_WIDTH +set_parameter_property M_BURSTCOUNT_WIDTH ENABLED false +set_parameter_property M_BURSTCOUNT_WIDTH UNITS None +set_parameter_property M_BURSTCOUNT_WIDTH ALLOWED_RANGES 7 +set_parameter_property M_BURSTCOUNT_WIDTH HDL_PARAMETER true + + +# +# display items +# + + +# +# connection point av_s0 +# +add_interface av_s0 avalon end +set_interface_property av_s0 addressGroup 0 +set_interface_property av_s0 addressUnits WORDS +set_interface_property av_s0 associatedClock clock +set_interface_property av_s0 associatedReset reset +set_interface_property av_s0 bitsPerSymbol 8 +set_interface_property av_s0 bridgedAddressOffset 0 +set_interface_property av_s0 bridgesToMaster "" +set_interface_property av_s0 burstOnBurstBoundariesOnly false +set_interface_property av_s0 burstcountUnits WORDS +set_interface_property av_s0 explicitAddressSpan 0 +set_interface_property av_s0 holdTime 0 +set_interface_property av_s0 linewrapBursts false +set_interface_property av_s0 maximumPendingReadTransactions 32 +set_interface_property av_s0 maximumPendingWriteTransactions 0 +set_interface_property av_s0 minimumResponseLatency 1 +set_interface_property av_s0 readLatency 0 +set_interface_property av_s0 readWaitTime 1 +set_interface_property av_s0 setupTime 0 +set_interface_property av_s0 timingUnits Cycles +set_interface_property av_s0 transparentBridge false +set_interface_property av_s0 waitrequestAllowance 0 +set_interface_property av_s0 writeWaitTime 0 +set_interface_property av_s0 ENABLED true +set_interface_property av_s0 EXPORT_OF "" +set_interface_property av_s0 PORT_NAME_MAP "" +set_interface_property av_s0 CMSIS_SVD_VARIABLES "" +set_interface_property av_s0 SVD_ADDRESS_GROUP "" +set_interface_property av_s0 IPXACT_REGISTER_MAP_VARIABLES "" + +add_interface_port av_s0 s0_address address Input "((S_ADDR_WIDTH - 1)) - (0) + 1" +add_interface_port av_s0 s0_write write Input 1 +add_interface_port av_s0 s0_read read Input 1 +add_interface_port av_s0 s0_writedata writedata Input 1024 +add_interface_port av_s0 s0_byteenable byteenable Input 128 +add_interface_port av_s0 s0_burstcount burstcount Input "((S_BURSTCOUNT_WIDTH - 1)) - (0) + 1" +add_interface_port av_s0 s0_readdatavalid readdatavalid Output 1 +add_interface_port av_s0 s0_readdata readdata Output 1024 +add_interface_port av_s0 s0_waitrequest waitrequest Output 1 +set_interface_assignment av_s0 embeddedsw.configuration.isFlash 0 +set_interface_assignment av_s0 embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment av_s0 embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment av_s0 embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point av_m0 +# +add_interface av_m0 avalon start +set_interface_property av_m0 addressGroup 0 +set_interface_property av_m0 addressUnits SYMBOLS +set_interface_property av_m0 associatedClock clock +set_interface_property av_m0 associatedReset reset +set_interface_property av_m0 bitsPerSymbol 8 +set_interface_property av_m0 burstOnBurstBoundariesOnly false +set_interface_property av_m0 burstcountUnits WORDS +set_interface_property av_m0 doStreamReads false +set_interface_property av_m0 doStreamWrites false +set_interface_property av_m0 holdTime 0 +set_interface_property av_m0 linewrapBursts false +set_interface_property av_m0 maximumPendingReadTransactions 0 +set_interface_property av_m0 maximumPendingWriteTransactions 0 +set_interface_property av_m0 minimumResponseLatency 1 +set_interface_property av_m0 readLatency 0 +set_interface_property av_m0 readWaitTime 1 +set_interface_property av_m0 setupTime 0 +set_interface_property av_m0 timingUnits Cycles +set_interface_property av_m0 waitrequestAllowance 0 +set_interface_property av_m0 writeWaitTime 0 +set_interface_property av_m0 ENABLED true +set_interface_property av_m0 EXPORT_OF "" +set_interface_property av_m0 PORT_NAME_MAP "" +set_interface_property av_m0 CMSIS_SVD_VARIABLES "" +set_interface_property av_m0 SVD_ADDRESS_GROUP "" +set_interface_property av_m0 IPXACT_REGISTER_MAP_VARIABLES "" + +add_interface_port av_m0 m0_address address Output "((M_ADDR_WIDTH - 1)) - (0) + 1" +add_interface_port av_m0 m0_write write Output 1 +add_interface_port av_m0 m0_read read Output 1 +add_interface_port av_m0 m0_writedata writedata Output 576 +add_interface_port av_m0 m0_byteenable byteenable Output "((M_BYTEENABLE_WIDTH - 1)) - (0) + 1" +add_interface_port av_m0 m0_burstcount burstcount Output "((M_BURSTCOUNT_WIDTH - 1)) - (0) + 1" +add_interface_port av_m0 m0_readdatavalid readdatavalid Input 1 +add_interface_port av_m0 m0_readdata readdata Input "((M_DATA_WIDTH - 1)) - (0) + 1" +add_interface_port av_m0 m0_waitrequest waitrequest Input 1 + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" +set_interface_property clock IPXACT_REGISTER_MAP_VARIABLES "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges BOTH +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" +set_interface_property reset IPXACT_REGISTER_MAP_VARIABLES "" + +add_interface_port reset reset reset Input 1 + diff --git a/ipss/mem/axi_bridge/ddr_axi_master_endpoint.sv b/ipss/mem/axi_bridge/ddr_axi_master_endpoint.sv new file mode 100644 index 0000000..3ba3ea9 --- /dev/null +++ b/ipss/mem/axi_bridge/ddr_axi_master_endpoint.sv @@ -0,0 +1,278 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// QSYS endpoint component to allow an external DDR AXI master interface +// to be connected to QSYS interconnect +// +// DDR AXI slave interface has the following requirements: +// * awsize (128B) +// * LSB 64B : data +// * MSB 64B : {unused, 8B ECC} +// * awburst (INCR) +// +// Currently, the endpoint doesn't perform any error checking. +// It assumes all requests coming from the AXI master comply with +// DDR slave interface requirements. +// +// Future release may include error checking to return error response +// for unsupported requests. +// +//----------------------------------------------------------------------------- + +module ddr_axi_master_endpoint #( + parameter ID_WIDTH = 6, + parameter ADDR_WIDTH = 34, + parameter DATA_WIDTH = 1024, + parameter ACTUAL_DATA_WIDTH = 576, // Number of bits in 1024-bit data that is actually used + // i.e. only lower 576 bits are used, 512-bit data and 64-bit ECC + + // Derived parameter + parameter WSTRB_WIDTH = (DATA_WIDTH/8), + parameter ACTUAL_WSTRB_WIDTH = (ACTUAL_DATA_WIDTH/8) +)( + + //--------------------------------- + // AXI slave interface + //--------------------------------- + input logic axi_s0_clk, + input logic axi_s0_resetn, + + // Write address channel + input logic axi_s0_awvalid, + input logic [ID_WIDTH-1:0] axi_s0_awid, + input logic [ADDR_WIDTH-1:0] axi_s0_awaddr, + input logic [7:0] axi_s0_awlen, + input logic [2:0] axi_s0_awsize, + input logic [1:0] axi_s0_awburst, + output logic axi_s0_awready, + + // Write data channel + input logic axi_s0_wvalid, + input logic [DATA_WIDTH-1:0] axi_s0_wdata, + input logic [WSTRB_WIDTH-1:0] axi_s0_wstrb, + input logic axi_s0_wlast, + output logic axi_s0_wready, + + // Write response channel + output logic axi_s0_bvalid, + output logic [ID_WIDTH-1:0] axi_s0_bid, + output logic [1:0] axi_s0_bresp, + input logic axi_s0_bready, + + // Read address channel + input logic axi_s0_arvalid, + input logic [ID_WIDTH-1:0] axi_s0_arid, + input logic [ADDR_WIDTH-1:0] axi_s0_araddr, + input logic [7:0] axi_s0_arlen, + input logic [2:0] axi_s0_arsize, + input logic [1:0] axi_s0_arburst, + output logic axi_s0_arready, + + // Read response channel + output logic axi_s0_rvalid, + output logic [ID_WIDTH-1:0] axi_s0_rid, + output logic [DATA_WIDTH-1:0] axi_s0_rdata, + output logic [1:0] axi_s0_rresp, + output logic axi_s0_rlast, + input logic axi_s0_rready, + + //--------------------------------- + // AXI master interface + //--------------------------------- + output logic axi_m0_clk, + output logic axi_m0_resetn, + + // Write address channel + output logic axi_m0_awvalid, + output logic [ID_WIDTH-1:0] axi_m0_awid, + output logic [ADDR_WIDTH-1:0] axi_m0_awaddr, + output logic [7:0] axi_m0_awlen, + output logic [2:0] axi_m0_awsize, + output logic [1:0] axi_m0_awburst, + output logic [2:0] axi_m0_awprot, + input logic axi_m0_awready, + + // Write data channel + output logic axi_m0_wvalid, + output logic [DATA_WIDTH-1:0] axi_m0_wdata, + output logic [WSTRB_WIDTH-1:0] axi_m0_wstrb, + output logic axi_m0_wlast, + input logic axi_m0_wready, + + // Write response channel + input logic axi_m0_bvalid, + input logic [ID_WIDTH-1:0] axi_m0_bid, + input logic [1:0] axi_m0_bresp, + output logic axi_m0_bready, + + // Read address channel + output logic axi_m0_arvalid, + output logic [ID_WIDTH-1:0] axi_m0_arid, + output logic [ADDR_WIDTH-1:0] axi_m0_araddr, + output logic [7:0] axi_m0_arlen, + output logic [2:0] axi_m0_arsize, + output logic [1:0] axi_m0_arburst, + output logic [2:0] axi_m0_arprot, + input logic axi_m0_arready, + + // Read response channel + input logic axi_m0_rvalid, + input logic [ID_WIDTH-1:0] axi_m0_rid, + input logic [DATA_WIDTH-1:0] axi_m0_rdata, + input logic [1:0] axi_m0_rresp, + input logic axi_m0_rlast, + output logic axi_m0_rready +); + +localparam MAX_PENDING_READS = 16; +localparam MAX_PENDING_READS_WIDTH = $clog2(MAX_PENDING_READS); + +typedef struct packed { + logic [ID_WIDTH-1:0] arid; + logic [ADDR_WIDTH-1:0] araddr; + logic [7:0] arlen; + logic [2:0] arsize; + logic [1:0] arburst; +} t_ar_if; +localparam AR_IF_WIDTH = $bits(t_ar_if); + +logic m0_arvalid; +logic m0_arready; +t_ar_if m0_ar_if; + +logic s0_arready; +t_ar_if axi_s0_ar_if; +t_ar_if s0_ar_if; + +logic [MAX_PENDING_READS_WIDTH:0] pending_reads_cnt; +logic max_pending_hit; + +logic last_response; + +//-------------------------------------------------------------- + +//-------------------------- +// Slave interface pipeline +//-------------------------- +assign axi_s0_ar_if.arid = axi_s0_arid; +assign axi_s0_ar_if.araddr = axi_s0_araddr; +assign axi_s0_ar_if.arlen = axi_s0_arlen; +assign axi_s0_ar_if.arsize = axi_s0_arsize; +assign axi_s0_ar_if.arburst = axi_s0_arburst; + +ofs_pipeline_reg #( + .REG_MODE (0), // skid-buffer + .WIDTH (AR_IF_WIDTH) +) axi_s0_arreg ( + .clk (axi_s0_clk), + .rst_n (axi_s0_resetn), + .s_ready (axi_s0_arready), + .s_valid (axi_s0_arvalid), + .s_data (axi_s0_ar_if), + .m_ready (s0_arready), + .m_valid (s0_arvalid), + .m_data (s0_ar_if) +); + +assign max_pending_hit = pending_reads_cnt[MAX_PENDING_READS_WIDTH]; +assign m0_arready = (~axi_m0_arvalid || axi_m0_arready); +assign s0_arready = m0_arready && ~max_pending_hit; + +//-------------------------- +// Max pending reads = 16 +//-------------------------- +// +// Restrict maximum pending reads to 16 to meet QSYS read FIFO size limitation (2^23) +// AXI-4 supports up to 256 burst length, so, the maximum payload per read request is 256*1024-bit (2^18) +// QSYS appended 2 extra bits to the payload (1026-bit) when it is written into the readdata FIFO in QSYS interconnect +// So, with 2^23 bits limitation, the max pending reads that can be supported is 16 (2^4) +// +// The pending_reads_cnt tracks the number of pending reads +// s0_arready will be de-asserted when the counter reaches the max pending reads allowed +// +//-------------------------- + +// Decrement the counter in the next cycle after the last response of a read reqeust is received +// to reduce fanin to pending_reads_cnt, adding 1 cycle of pessimism +always_ff @(posedge axi_s0_clk) begin + if (~axi_s0_resetn) begin + last_response <= 1'b0; + end else begin + last_response <= (axi_m0_rvalid && axi_m0_rlast && axi_m0_rready); + end +end + +always_ff @(posedge axi_s0_clk) begin + if (~axi_s0_resetn) begin + pending_reads_cnt <= 'd1; + end else begin + if (m0_arvalid && m0_arready) begin + if (~last_response) pending_reads_cnt <= pending_reads_cnt + 1'b1; + end else if (last_response) begin + pending_reads_cnt <= pending_reads_cnt - 1'b1; + end + end +end + +//-------------------------- +// Master interface pipeline +//-------------------------- +always_ff @(posedge axi_s0_clk) begin + if (m0_arready) m0_ar_if <= s0_ar_if; +end + +always_ff @(posedge axi_s0_clk) begin + if (~axi_s0_resetn) begin + m0_arvalid <= 1'b0; + end else if (m0_arready) begin + m0_arvalid <= 1'b0; + if (s0_arvalid && ~max_pending_hit) m0_arvalid <= 1'b1; + end +end + +//------------------------ +// Interface assignments +//------------------------ +assign axi_m0_clk = axi_s0_clk; +assign axi_m0_resetn = axi_s0_resetn; + +assign axi_m0_awvalid = axi_s0_awvalid; +assign axi_m0_awid = axi_s0_awid; +assign axi_m0_awaddr = axi_s0_awaddr; +assign axi_m0_awlen = axi_s0_awlen; +assign axi_m0_awsize = axi_s0_awsize; +assign axi_m0_awburst = axi_s0_awburst; +assign axi_m0_awprot = '0; +assign axi_s0_awready = axi_m0_awready; + +assign axi_m0_wvalid = axi_s0_wvalid; +assign axi_m0_wdata = axi_s0_wdata[0+:ACTUAL_DATA_WIDTH]; +assign axi_m0_wstrb = {'0, axi_s0_wstrb[0+:ACTUAL_WSTRB_WIDTH]}; +assign axi_m0_wlast = axi_s0_wlast; +assign axi_s0_wready = axi_m0_wready; + +assign axi_s0_bvalid = axi_m0_bvalid; +assign axi_s0_bid = axi_m0_bid; +assign axi_s0_bresp = axi_m0_bresp; +assign axi_m0_bready = axi_s0_bready; + +assign axi_m0_arvalid = m0_arvalid; +assign axi_m0_arid = m0_ar_if.arid; +assign axi_m0_araddr = m0_ar_if.araddr; +assign axi_m0_arlen = m0_ar_if.arlen; +assign axi_m0_arsize = m0_ar_if.arsize; +assign axi_m0_arburst = m0_ar_if.arburst; +assign axi_m0_arprot = '0; + +assign axi_s0_rvalid = axi_m0_rvalid; +assign axi_s0_rid = axi_m0_rid; +assign axi_s0_rdata = {'0, axi_m0_rdata[0+:ACTUAL_DATA_WIDTH]}; +assign axi_s0_rresp = axi_m0_rresp; +assign axi_s0_rlast = axi_m0_rlast; +assign axi_m0_rready = axi_s0_rready; + +endmodule + diff --git a/ipss/mem/axi_bridge/ddr_axi_master_endpoint_hw.tcl b/ipss/mem/axi_bridge/ddr_axi_master_endpoint_hw.tcl new file mode 100644 index 0000000..ad5818d --- /dev/null +++ b/ipss/mem/axi_bridge/ddr_axi_master_endpoint_hw.tcl @@ -0,0 +1,279 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# TCL File Generated by Component Editor 19.2 +# Wed Apr 29 14:07:58 PDT 2020 +# DO NOT MODIFY + + +# +# ddr_axi_master_endpoint "ddr_axi_master_endpoint" v1.0 +# Intel 2020.04.29.14:07:58 +# DDR AXI master endpoint +# + +# +# request TCL package from ACDS 19.4 +# +package require -exact qsys 19.4 + + +# +# module ddr_axi_master_endpoint +# +set_module_property DESCRIPTION "DDR AXI master endpoint" +set_module_property NAME ddr_axi_master_endpoint +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP Interface +set_module_property AUTHOR Intel +set_module_property DISPLAY_NAME ddr_axi_master_endpoint +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false +set_module_property LOAD_ELABORATION_LIMIT 0 + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL ddr_axi_master_endpoint +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file ddr_axi_master_endpoint.sv SYSTEM_VERILOG PATH ddr_axi_master_endpoint.sv TOP_LEVEL_FILE +add_fileset_file ofs_pipeline_reg.sv SYSTEM_VERILOG PATH ofs_pipeline_reg.sv + +add_fileset SIM_VERILOG SIM_VERILOG "" "" +set_fileset_property SIM_VERILOG TOP_LEVEL ddr_axi_master_endpoint +set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file ddr_axi_master_endpoint.sv SYSTEM_VERILOG PATH ddr_axi_master_endpoint.sv +add_fileset_file ofs_pipeline_reg.sv SYSTEM_VERILOG PATH ofs_pipeline_reg.sv + + +# +# parameters +# +add_parameter ID_WIDTH INTEGER 6 "" +set_parameter_property ID_WIDTH DEFAULT_VALUE 6 +set_parameter_property ID_WIDTH DISPLAY_NAME ID_WIDTH +set_parameter_property ID_WIDTH WIDTH "" +set_parameter_property ID_WIDTH ENABLED false +set_parameter_property ID_WIDTH UNITS None +set_parameter_property ID_WIDTH ALLOWED_RANGES 1:32 +set_parameter_property ID_WIDTH DESCRIPTION "" +set_parameter_property ID_WIDTH HDL_PARAMETER true +add_parameter ADDR_WIDTH INTEGER 34 "" +set_parameter_property ADDR_WIDTH DEFAULT_VALUE 34 +set_parameter_property ADDR_WIDTH DISPLAY_NAME ADDR_WIDTH +set_parameter_property ADDR_WIDTH ENABLED false +set_parameter_property ADDR_WIDTH UNITS None +set_parameter_property ADDR_WIDTH ALLOWED_RANGES 1:64 +set_parameter_property ADDR_WIDTH DESCRIPTION "" +set_parameter_property ADDR_WIDTH HDL_PARAMETER true +add_parameter DATA_WIDTH INTEGER 1024 "" +set_parameter_property DATA_WIDTH DEFAULT_VALUE 1024 +set_parameter_property DATA_WIDTH DISPLAY_NAME DATA_WIDTH +set_parameter_property DATA_WIDTH ENABLED false +set_parameter_property DATA_WIDTH UNITS None +set_parameter_property DATA_WIDTH ALLOWED_RANGES 8:1024 +set_parameter_property DATA_WIDTH DESCRIPTION "" +set_parameter_property DATA_WIDTH HDL_PARAMETER true +add_parameter ACTUAL_DATA_WIDTH INTEGER 576 "" +set_parameter_property ACTUAL_DATA_WIDTH DEFAULT_VALUE 576 +set_parameter_property ACTUAL_DATA_WIDTH DISPLAY_NAME ACTUAL_DATA_WIDTH +set_parameter_property ACTUAL_DATA_WIDTH ENABLED false +set_parameter_property ACTUAL_DATA_WIDTH UNITS None +set_parameter_property ACTUAL_DATA_WIDTH ALLOWED_RANGES 8:1024 +set_parameter_property ACTUAL_DATA_WIDTH DESCRIPTION "" +set_parameter_property ACTUAL_DATA_WIDTH HDL_PARAMETER true +add_parameter WSTRB_WIDTH INTEGER 128 "" +set_parameter_property WSTRB_WIDTH DEFAULT_VALUE 128 +set_parameter_property WSTRB_WIDTH DISPLAY_NAME WSTRB_WIDTH +set_parameter_property WSTRB_WIDTH ENABLED false +set_parameter_property WSTRB_WIDTH UNITS None +set_parameter_property WSTRB_WIDTH ALLOWED_RANGES 1:128 +set_parameter_property WSTRB_WIDTH DESCRIPTION "" +set_parameter_property WSTRB_WIDTH HDL_PARAMETER true +add_parameter ACTUAL_WSTRB_WIDTH INTEGER 72 "" +set_parameter_property ACTUAL_WSTRB_WIDTH DEFAULT_VALUE 72 +set_parameter_property ACTUAL_WSTRB_WIDTH DISPLAY_NAME ACTUAL_WSTRB_WIDTH +set_parameter_property ACTUAL_WSTRB_WIDTH ENABLED false +set_parameter_property ACTUAL_WSTRB_WIDTH UNITS None +set_parameter_property ACTUAL_WSTRB_WIDTH ALLOWED_RANGES 1:128 +set_parameter_property ACTUAL_WSTRB_WIDTH DESCRIPTION "" +set_parameter_property ACTUAL_WSTRB_WIDTH HDL_PARAMETER true + + +# +# display items +# + + +# +# connection point axi_s0_resetn +# +add_interface axi_s0_resetn reset end +set_interface_property axi_s0_resetn associatedClock axi_s0_clk +set_interface_property axi_s0_resetn synchronousEdges BOTH +set_interface_property axi_s0_resetn ENABLED true +set_interface_property axi_s0_resetn EXPORT_OF "" +set_interface_property axi_s0_resetn PORT_NAME_MAP "" +set_interface_property axi_s0_resetn CMSIS_SVD_VARIABLES "" +set_interface_property axi_s0_resetn SVD_ADDRESS_GROUP "" +set_interface_property axi_s0_resetn IPXACT_REGISTER_MAP_VARIABLES "" + +add_interface_port axi_s0_resetn axi_s0_resetn reset_n Input 1 + + +# +# connection point axi_s0_clk +# +add_interface axi_s0_clk clock end +set_interface_property axi_s0_clk ENABLED true +set_interface_property axi_s0_clk EXPORT_OF "" +set_interface_property axi_s0_clk PORT_NAME_MAP "" +set_interface_property axi_s0_clk CMSIS_SVD_VARIABLES "" +set_interface_property axi_s0_clk SVD_ADDRESS_GROUP "" +set_interface_property axi_s0_clk IPXACT_REGISTER_MAP_VARIABLES "" + +add_interface_port axi_s0_clk axi_s0_clk clk Input 1 + + +# +# connection point axi_m0_resetn +# +add_interface axi_m0_resetn reset start +set_interface_property axi_m0_resetn associatedClock axi_m0_clock +set_interface_property axi_m0_resetn associatedDirectReset axi_s0_resetn +set_interface_property axi_m0_resetn associatedResetSinks axi_s0_resetn +set_interface_property axi_m0_resetn synchronousEdges BOTH +set_interface_property axi_m0_resetn ENABLED true +set_interface_property axi_m0_resetn EXPORT_OF "" +set_interface_property axi_m0_resetn PORT_NAME_MAP "" +set_interface_property axi_m0_resetn CMSIS_SVD_VARIABLES "" +set_interface_property axi_m0_resetn SVD_ADDRESS_GROUP "" +set_interface_property axi_m0_resetn IPXACT_REGISTER_MAP_VARIABLES "" + +add_interface_port axi_m0_resetn axi_m0_resetn reset_n Output 1 + + +# +# connection point axi_m0_clock +# +add_interface axi_m0_clock clock start +set_interface_property axi_m0_clock associatedDirectClock axi_s0_clk +set_interface_property axi_m0_clock ENABLED true +set_interface_property axi_m0_clock EXPORT_OF "" +set_interface_property axi_m0_clock PORT_NAME_MAP "" +set_interface_property axi_m0_clock CMSIS_SVD_VARIABLES "" +set_interface_property axi_m0_clock SVD_ADDRESS_GROUP "" +set_interface_property axi_m0_clock IPXACT_REGISTER_MAP_VARIABLES "" + +add_interface_port axi_m0_clock axi_m0_clk clk Output 1 + + +# +# connection point axi_m0 +# +add_interface axi_m0 axi4 start +set_interface_property axi_m0 associatedClock axi_m0_clock +set_interface_property axi_m0 associatedReset axi_m0_resetn +set_interface_property axi_m0 readIssuingCapability 16 +set_interface_property axi_m0 writeIssuingCapability 16 +set_interface_property axi_m0 combinedIssuingCapability 16 +set_interface_property axi_m0 issuesINCRBursts true +set_interface_property axi_m0 issuesWRAPBursts false +set_interface_property axi_m0 issuesFIXEDBursts false +set_interface_property axi_m0 ENABLED true +set_interface_property axi_m0 EXPORT_OF "" +set_interface_property axi_m0 PORT_NAME_MAP "" +set_interface_property axi_m0 CMSIS_SVD_VARIABLES "" +set_interface_property axi_m0 SVD_ADDRESS_GROUP "" +set_interface_property axi_m0 IPXACT_REGISTER_MAP_VARIABLES "" + +add_interface_port axi_m0 axi_m0_awid awid Output "((ID_WIDTH - 1)) - (0) + 1" +add_interface_port axi_m0 axi_m0_awaddr awaddr Output "((ADDR_WIDTH - 1)) - (0) + 1" +add_interface_port axi_m0 axi_m0_awlen awlen Output 8 +add_interface_port axi_m0 axi_m0_awsize awsize Output 3 +add_interface_port axi_m0 axi_m0_awburst awburst Output 2 +add_interface_port axi_m0 axi_m0_awprot awprot Output 3 +add_interface_port axi_m0 axi_m0_awvalid awvalid Output 1 +add_interface_port axi_m0 axi_m0_awready awready Input 1 +add_interface_port axi_m0 axi_m0_wdata wdata Output 1024 +add_interface_port axi_m0 axi_m0_wstrb wstrb Output 128 +add_interface_port axi_m0 axi_m0_wlast wlast Output 1 +add_interface_port axi_m0 axi_m0_wvalid wvalid Output 1 +add_interface_port axi_m0 axi_m0_wready wready Input 1 +add_interface_port axi_m0 axi_m0_bid bid Input "((ID_WIDTH - 1)) - (0) + 1" +add_interface_port axi_m0 axi_m0_bresp bresp Input 2 +add_interface_port axi_m0 axi_m0_bvalid bvalid Input 1 +add_interface_port axi_m0 axi_m0_bready bready Output 1 +add_interface_port axi_m0 axi_m0_arid arid Output "((ID_WIDTH - 1)) - (0) + 1" +add_interface_port axi_m0 axi_m0_araddr araddr Output "((ADDR_WIDTH - 1)) - (0) + 1" +add_interface_port axi_m0 axi_m0_arlen arlen Output 8 +add_interface_port axi_m0 axi_m0_arsize arsize Output 3 +add_interface_port axi_m0 axi_m0_arburst arburst Output 2 +add_interface_port axi_m0 axi_m0_arprot arprot Output 3 +add_interface_port axi_m0 axi_m0_arvalid arvalid Output 1 +add_interface_port axi_m0 axi_m0_arready arready Input 1 +add_interface_port axi_m0 axi_m0_rid rid Input "((ID_WIDTH - 1)) - (0) + 1" +add_interface_port axi_m0 axi_m0_rdata rdata Input 1024 +add_interface_port axi_m0 axi_m0_rlast rlast Input 1 +add_interface_port axi_m0 axi_m0_rresp rresp Input 2 +add_interface_port axi_m0 axi_m0_rvalid rvalid Input 1 +add_interface_port axi_m0 axi_m0_rready rready Output 1 + + +# +# connection point axi_s0 +# +add_interface axi_s0 axi4 end +set_interface_property axi_s0 associatedClock axi_s0_clk +set_interface_property axi_s0 associatedReset axi_s0_resetn +set_interface_property axi_s0 readAcceptanceCapability 16 +set_interface_property axi_s0 writeAcceptanceCapability 16 +set_interface_property axi_s0 combinedAcceptanceCapability 16 +set_interface_property axi_s0 readDataReorderingDepth 1 +set_interface_property axi_s0 bridgesToMaster "" +set_interface_property axi_s0 ENABLED true +set_interface_property axi_s0 EXPORT_OF "" +set_interface_property axi_s0 PORT_NAME_MAP "" +set_interface_property axi_s0 CMSIS_SVD_VARIABLES "" +set_interface_property axi_s0 SVD_ADDRESS_GROUP "" +set_interface_property axi_s0 IPXACT_REGISTER_MAP_VARIABLES "" + +add_interface_port axi_s0 axi_s0_awid awid Input "((ID_WIDTH - 1)) - (0) + 1" +add_interface_port axi_s0 axi_s0_awaddr awaddr Input "((ADDR_WIDTH - 1)) - (0) + 1" +add_interface_port axi_s0 axi_s0_awlen awlen Input 8 +add_interface_port axi_s0 axi_s0_awsize awsize Input 3 +add_interface_port axi_s0 axi_s0_awburst awburst Input 2 +add_interface_port axi_s0 axi_s0_awvalid awvalid Input 1 +add_interface_port axi_s0 axi_s0_awready awready Output 1 +add_interface_port axi_s0 axi_s0_wdata wdata Input "((DATA_WIDTH - 1)) - (0) + 1" +add_interface_port axi_s0 axi_s0_wstrb wstrb Input "((WSTRB_WIDTH - 1)) - (0) + 1" +add_interface_port axi_s0 axi_s0_wlast wlast Input 1 +add_interface_port axi_s0 axi_s0_wvalid wvalid Input 1 +add_interface_port axi_s0 axi_s0_wready wready Output 1 +add_interface_port axi_s0 axi_s0_bid bid Output "((ID_WIDTH - 1)) - (0) + 1" +add_interface_port axi_s0 axi_s0_bresp bresp Output 2 +add_interface_port axi_s0 axi_s0_bvalid bvalid Output 1 +add_interface_port axi_s0 axi_s0_bready bready Input 1 +add_interface_port axi_s0 axi_s0_arid arid Input "((ID_WIDTH - 1)) - (0) + 1" +add_interface_port axi_s0 axi_s0_araddr araddr Input "((ADDR_WIDTH - 1)) - (0) + 1" +add_interface_port axi_s0 axi_s0_arlen arlen Input 8 +add_interface_port axi_s0 axi_s0_arsize arsize Input 3 +add_interface_port axi_s0 axi_s0_arburst arburst Input 2 +add_interface_port axi_s0 axi_s0_arvalid arvalid Input 1 +add_interface_port axi_s0 axi_s0_arready arready Output 1 +add_interface_port axi_s0 axi_s0_rid rid Output "((ID_WIDTH - 1)) - (0) + 1" +add_interface_port axi_s0 axi_s0_rdata rdata Output "((DATA_WIDTH - 1)) - (0) + 1" +add_interface_port axi_s0 axi_s0_rlast rlast Output 1 +add_interface_port axi_s0 axi_s0_rresp rresp Output 2 +add_interface_port axi_s0 axi_s0_rvalid rvalid Output 1 +add_interface_port axi_s0 axi_s0_rready rready Input 1 + diff --git a/ipss/mem/axi_bridge/ip/ofs_ddr_axi_bridge/amm_clock.ip b/ipss/mem/axi_bridge/ip/ofs_ddr_axi_bridge/amm_clock.ip new file mode 100644 index 0000000..6898ca4 --- /dev/null +++ b/ipss/mem/axi_bridge/ip/ofs_ddr_axi_bridge/amm_clock.ip @@ -0,0 +1,344 @@ + + + + Intel Corporation + amm_clock + amm_clock + 19.2.0 + + + in_clk + + + + + + + + clk + + + in_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + out_clk + + + + + + + + clk + + + out_clk + + + + + + + + + associatedDirectClock + Associated direct clock + in_clk + + + clockRate + Clock rate + 0 + + + clockRateKnown + Clock rate known + false + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_clock_bridge + + QUARTUS_SYNTH + + + + + + in_clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + out_clk + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + amm_clock + altera_clock_bridge + 19.2.0 + + + + + DERIVED_CLOCK_RATE + Derived clock rate + 0 + + + EXPLICIT_CLOCK_RATE + Explicit clock rate + 0 + + + NUM_CLOCK_OUTPUTS + Number of Clock Outputs + 1 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element amm_clock + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>in_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>in_clk</value> + </entry> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>false</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>in_clk</key> + <value> + <connectionPointName>in_clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>out_clk</key> + <value> + <connectionPointName>out_clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/ipss/mem/axi_bridge/ip/ofs_ddr_axi_bridge/amm_reset.ip b/ipss/mem/axi_bridge/ip/ofs_ddr_axi_bridge/amm_reset.ip new file mode 100644 index 0000000..4cb2381 --- /dev/null +++ b/ipss/mem/axi_bridge/ip/ofs_ddr_axi_bridge/amm_reset.ip @@ -0,0 +1,315 @@ + + + + Intel Corporation + amm_reset + amm_reset + 19.2.0 + + + in_reset + + + + + + + + reset + + + in_reset + + + + + + + + + associatedClock + Associated clock + + + + synchronousEdges + Synchronous edges + NONE + + + + + out_reset + + + + + + + + reset + + + out_reset + + + + + + + + + associatedClock + Associated clock + + + + associatedDirectReset + Associated direct reset + in_reset + + + associatedResetSinks + Associated reset sinks + in_reset + + + synchronousEdges + Synchronous edges + NONE + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_reset_bridge + + QUARTUS_SYNTH + + + + + + in_reset + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + out_reset + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + amm_reset + altera_reset_bridge + 19.2.0 + + + + + ACTIVE_LOW_RESET + Active low reset + 0 + + + SYNCHRONOUS_EDGES + Synchronous edges + none + + + NUM_RESET_OUTPUTS + Number of reset outputs + 1 + + + USE_RESET_REQUEST + Use reset request signal + 0 + + + SYNC_RESET + Use synchronous resets + 0 + + + AUTO_CLK_CLOCK_RATE + Auto CLOCK_RATE + -1 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element amm_reset + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_reset</name> + <role>reset</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/ipss/mem/axi_bridge/ip/ofs_ddr_axi_bridge/avmm_ep.ip b/ipss/mem/axi_bridge/ip/ofs_ddr_axi_bridge/avmm_ep.ip new file mode 100644 index 0000000..b3582ee --- /dev/null +++ b/ipss/mem/axi_bridge/ip/ofs_ddr_axi_bridge/avmm_ep.ip @@ -0,0 +1,1698 @@ + + + Intel + avmm_ep + avmm_ep + 1.0 + + + av_s0 + + + + + + + + address + + + s0_address + + + + + write + + + s0_write + + + + + read + + + s0_read + + + + + writedata + + + s0_writedata + + + + + byteenable + + + s0_byteenable + + + + + burstcount + + + s0_burstcount + + + + + readdatavalid + + + s0_readdatavalid + + + + + readdata + + + s0_readdata + + + + + waitrequest + + + s0_waitrequest + + + + + + + + + addressAlignment + Slave addressing + DYNAMIC + + + addressGroup + Address group + 0 + + + addressSpan + Address span + 17179869184 + + + addressUnits + Address units + WORDS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + bitsPerSymbol + Bits per symbol + 8 + + + bridgedAddressOffset + Bridged Address Offset + 0 + + + bridgesToMaster + Bridges to master + + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + explicitAddressSpan + Explicit address span + 0 + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isBigEndian + Big endian + false + + + isFlash + Flash memory + false + + + isMemoryDevice + Memory device + false + + + isNonVolatileStorage + Non-volatile storage + false + + + linewrapBursts + Linewrap bursts + false + + + maximumPendingReadTransactions + Maximum pending read transactions + 32 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + minimumUninterruptedRunLength + Minimum uninterrupted run length + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + printableDevice + Can receive stdout/stderr + false + + + readLatency + Read latency + 0 + + + readWaitStates + Read wait states + 1 + + + readWaitTime + Read wait + 1 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + transparentBridge + Transparent bridge + false + + + waitrequestAllowance + Waitrequest allowance + 0 + + + wellBehavedWaitrequest + Well-behaved waitrequest + false + + + writeLatency + Write latency + 0 + + + writeWaitStates + Write wait states + 0 + + + writeWaitTime + Write wait + 0 + + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + + + + + av_m0 + + + + + + + + address + + + m0_address + + + + + write + + + m0_write + + + + + read + + + m0_read + + + + + writedata + + + m0_writedata + + + + + byteenable + + + m0_byteenable + + + + + burstcount + + + m0_burstcount + + + + + readdatavalid + + + m0_readdatavalid + + + + + readdata + + + m0_readdata + + + + + waitrequest + + + m0_waitrequest + + + + + + + + + adaptsTo + Adapts to + + + + addressGroup + Address group + 0 + + + addressUnits + Address units + SYMBOLS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + bitsPerSymbol + Bits per symbol + 8 + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + dBSBigEndian + dBS big endian + false + + + doStreamReads + Use flow control for read transfers + false + + + doStreamWrites + Use flow control for write transfers + false + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isAsynchronous + Is asynchronous + false + + + isBigEndian + Is big endian + false + + + isReadable + Is readable + false + + + isWriteable + Is writeable + false + + + linewrapBursts + Linewrap bursts + false + + + maxAddressWidth + Maximum address width + 32 + + + maximumPendingReadTransactions + Maximum pending read transactions + 0 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + readLatency + Read latency + 0 + + + readWaitTime + Read wait + 1 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + waitrequestAllowance + Waitrequest allowance + 0 + + + writeWaitTime + Write wait + 0 + + + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset + + + reset + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + BOTH + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + ddr_avmm_slave_endpoint + + QUARTUS_SYNTH + + + + + + + s0_address + + in + + + 0 + 26 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_write + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_read + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_writedata + + in + + + 0 + 1023 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_byteenable + + in + + + 0 + 127 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_burstcount + + in + + + 0 + 6 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_readdatavalid + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_readdata + + out + + + 0 + 1023 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_waitrequest + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_address + + out + + + 0 + 26 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m0_write + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_read + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_writedata + + out + + + 0 + 575 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m0_byteenable + + out + + + 0 + 71 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m0_burstcount + + out + + + 0 + 6 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m0_readdatavalid + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_readdata + + in + + + 0 + 575 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m0_waitrequest + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + clk + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + reset + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel + avmm_ep + ddr_avmm_slave_endpoint + 1.0 + + + + + S_ADDR_WIDTH + S_ADDR_WIDTH + 27 + + + S_DATA_WIDTH + S_DATA_WIDTH + 1024 + + + S_BYTEENABLE_WIDTH + S_BYTEENABLE_WIDTH + 128 + + + S_BURSTCOUNT_WIDTH + S_BURSTCOUNT_WIDTH + 7 + + + M_ADDR_WIDTH + M_ADDR_WIDTH + 27 + + + M_DATA_WIDTH + M_DATA_WIDTH + 576 + + + M_BYTEENABLE_WIDTH + M_BYTEENABLE_WIDTH + 72 + + + M_BURSTCOUNT_WIDTH + M_BURSTCOUNT_WIDTH + 7 + + + + + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element $system + { + datum _originalDeviceFamily + { + value = "Stratix 10"; + type = "String"; + } + } + element avmm_ep + { + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>av_s0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_address</name> + <role>address</role> + <direction>Input</direction> + <width>27</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>s0_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>s0_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>s0_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>1024</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>s0_byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>128</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>s0_burstcount</name> + <role>burstcount</role> + <direction>Input</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>s0_readdatavalid</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>s0_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>1024</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>s0_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>17179869184</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>av_m0</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>m0_address</name> + <role>address</role> + <direction>Output</direction> + <width>27</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>m0_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>m0_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>m0_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>576</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>m0_byteenable</name> + <role>byteenable</role> + <direction>Output</direction> + <width>72</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>m0_burstcount</name> + <role>burstcount</role> + <direction>Output</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>m0_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>m0_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>576</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>m0_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>BOTH</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>av_s0</key> + <value> + <connectionPointName>av_s0</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='av_s0' start='0x0' end='0x400000000' datawidth='1024' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>34</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>1024</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/ipss/mem/axi_bridge/ip/ofs_ddr_axi_bridge/axi_ep.ip b/ipss/mem/axi_bridge/ip/ofs_ddr_axi_bridge/axi_ep.ip new file mode 100644 index 0000000..cc545d4 --- /dev/null +++ b/ipss/mem/axi_bridge/ip/ofs_ddr_axi_bridge/axi_ep.ip @@ -0,0 +1,2787 @@ + + + Intel + axi_ep + axi_ep + 1.0 + + + axi_s0_resetn + + + + + + + + reset_n + + + axi_s0_resetn + + + + + + + + + associatedClock + Associated clock + axi_s0_clk + + + synchronousEdges + Synchronous edges + BOTH + + + + + axi_s0_clk + + + + + + + + clk + + + axi_s0_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + axi_m0_resetn + + + + + + + + reset_n + + + axi_m0_resetn + + + + + + + + + associatedClock + Associated clock + axi_m0_clock + + + associatedDirectReset + Associated direct reset + axi_s0_resetn + + + associatedResetSinks + Associated reset sinks + axi_s0_resetn + + + synchronousEdges + Synchronous edges + BOTH + + + + + axi_m0_clock + + + + + + + + clk + + + axi_m0_clk + + + + + + + + + associatedDirectClock + Associated direct clock + axi_s0_clk + + + clockRate + Clock rate + 0 + + + clockRateKnown + Clock rate known + false + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + axi_m0 + + + + + + + + awid + + + axi_m0_awid + + + + + awaddr + + + axi_m0_awaddr + + + + + awlen + + + axi_m0_awlen + + + + + awsize + + + axi_m0_awsize + + + + + awburst + + + axi_m0_awburst + + + + + awprot + + + axi_m0_awprot + + + + + awvalid + + + axi_m0_awvalid + + + + + awready + + + axi_m0_awready + + + + + wdata + + + axi_m0_wdata + + + + + wstrb + + + axi_m0_wstrb + + + + + wlast + + + axi_m0_wlast + + + + + wvalid + + + axi_m0_wvalid + + + + + wready + + + axi_m0_wready + + + + + bid + + + axi_m0_bid + + + + + bresp + + + axi_m0_bresp + + + + + bvalid + + + axi_m0_bvalid + + + + + bready + + + axi_m0_bready + + + + + arid + + + axi_m0_arid + + + + + araddr + + + axi_m0_araddr + + + + + arlen + + + axi_m0_arlen + + + + + arsize + + + axi_m0_arsize + + + + + arburst + + + axi_m0_arburst + + + + + arprot + + + axi_m0_arprot + + + + + arvalid + + + axi_m0_arvalid + + + + + arready + + + axi_m0_arready + + + + + rid + + + axi_m0_rid + + + + + rdata + + + axi_m0_rdata + + + + + rlast + + + axi_m0_rlast + + + + + rresp + + + axi_m0_rresp + + + + + rvalid + + + axi_m0_rvalid + + + + + rready + + + axi_m0_rready + + + + + + + + + associatedClock + Associated clock + axi_m0_clock + + + associatedReset + Associated reset + axi_m0_resetn + + + trustzoneAware + TrustZone-aware + true + + + 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Read acceptance capability + 16 + + + writeAcceptanceCapability + Write acceptance capability + 16 + + + combinedAcceptanceCapability + Combined acceptance capability + 16 + + + readDataReorderingDepth + Read data reordering depth + 1 + + + bridgesToMaster + bridgesToMaster + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + ddr_axi_master_endpoint + + QUARTUS_SYNTH + + + + + + + axi_s0_resetn + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + axi_s0_clk + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + axi_m0_resetn + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + axi_m0_clk + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + axi_m0_awid + + out + + + 0 + 5 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + axi_m0_awaddr + + out + + + 0 + 33 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + axi_m0_awlen + + out + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + axi_m0_awsize + + out + + + 0 + 2 + + + + + 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+ axi_s0_wvalid + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + axi_s0_wready + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + axi_s0_bid + + out + + + 0 + 5 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + axi_s0_bresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + axi_s0_bvalid + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + axi_s0_bready + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + axi_s0_arid + + in + + + 0 + 5 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + axi_s0_araddr + + in + + + 0 + 33 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + axi_s0_arlen + + in + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + axi_s0_arsize + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + axi_s0_arburst + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + axi_s0_arvalid + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + axi_s0_arready + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + axi_s0_rid + + out + + + 0 + 5 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + axi_s0_rdata + + out + + + 0 + 1023 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + axi_s0_rlast + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + axi_s0_rresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + axi_s0_rvalid + + out + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + axi_s0_rready + + in + + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel + axi_ep + ddr_axi_master_endpoint + 1.0 + + + + + ID_WIDTH + ID_WIDTH + 6 + + + ADDR_WIDTH + ADDR_WIDTH + 34 + + + DATA_WIDTH + DATA_WIDTH + 1024 + + + ACTUAL_DATA_WIDTH + ACTUAL_DATA_WIDTH + 576 + + + WSTRB_WIDTH + WSTRB_WIDTH + 128 + + + ACTUAL_WSTRB_WIDTH + ACTUAL_WSTRB_WIDTH + 72 + + + + + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element $system + { + datum _originalDeviceFamily + { + value = "Stratix 10"; + type = "String"; + } + } + element axi_ep + { + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>axi_s0_resetn</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>axi_s0_resetn</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>axi_s0_clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>BOTH</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>axi_s0_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>axi_s0_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>axi_m0_resetn</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>axi_m0_resetn</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>axi_m0_clock</value> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>axi_s0_resetn</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>axi_s0_resetn</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>BOTH</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>axi_m0_clock</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>axi_m0_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>axi_s0_clk</value> + </entry> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>false</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>axi_m0</name> + <type>axi4</type> + <isStart>true</isStart> + <ports> + <port> + <name>axi_m0_awid</name> + <role>awid</role> + <direction>Output</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>34</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_awlen</name> + <role>awlen</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_awsize</name> + <role>awsize</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_awburst</name> + <role>awburst</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_m0_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_m0_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>1024</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>128</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_wlast</name> + <role>wlast</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_m0_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_m0_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_m0_bid</name> + <role>bid</role> + <direction>Input</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_m0_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_m0_arid</name> + <role>arid</role> + <direction>Output</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>34</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_arlen</name> + <role>arlen</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_arsize</name> + <role>arsize</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_arburst</name> + <role>arburst</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_m0_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_m0_rid</name> + <role>rid</role> + <direction>Input</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>1024</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_rlast</name> + <role>rlast</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_m0_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_m0_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>axi_m0_clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>axi_m0_resetn</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>issuesINCRBursts</key> + <value>true</value> + </entry> + <entry> + <key>issuesWRAPBursts</key> + <value>false</value> + </entry> + <entry> + <key>issuesFIXEDBursts</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>axi_s0</name> + <type>axi4</type> + <isStart>false</isStart> + <ports> + <port> + <name>axi_s0_awid</name> + <role>awid</role> + <direction>Input</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>34</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_awlen</name> + <role>awlen</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_awsize</name> + <role>awsize</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_awburst</name> + <role>awburst</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_s0_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_s0_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>1024</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>128</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_wlast</name> + <role>wlast</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_s0_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_s0_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_s0_bid</name> + <role>bid</role> + <direction>Output</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_s0_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_s0_arid</name> + <role>arid</role> + <direction>Input</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>34</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_arlen</name> + <role>arlen</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_arsize</name> + <role>arsize</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_arburst</name> + <role>arburst</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_s0_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_s0_rid</name> + <role>rid</role> + <direction>Output</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>1024</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_rlast</name> + <role>rlast</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_s0_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_s0_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>axi_s0_clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>axi_s0_resetn</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>axi_m0_clock</key> + <value> + <connectionPointName>axi_m0_clock</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>axi_s0</key> + <value> + <connectionPointName>axi_s0</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='axi_s0' start='0x0' end='0x400000000' datawidth='1024' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>34</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>1024</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/ipss/mem/axi_bridge/ofs_ddr_axi_bridge.qsys b/ipss/mem/axi_bridge/ofs_ddr_axi_bridge.qsys new file mode 100644 index 0000000..db9ec5f --- /dev/null +++ b/ipss/mem/axi_bridge/ofs_ddr_axi_bridge.qsys @@ -0,0 +1,3732 @@ + + + + Altera Corporation + ofs_ddr_axi_bridge + ofs_ddr_axi_bridge + 1.0 + + + + $${FILENAME} + $${FILENAME} + 1.0 + + + System + QsysPro + + + + + board + Board + default + + + bonusData + bonusData + bonusData +{ + element $system + { + } + element amm_clock + { + datum _sortIndex + { + value = "2"; + type = "int"; + } + } + element amm_reset + { + datum _sortIndex + { + value = "3"; + type = "int"; + } + } + element avmm_ep + { + datum _sortIndex + { + value = "1"; + type = "int"; + } + } + element axi_ep + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + designId + designId + + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + fabricMode + fabricMode + QSYS + + + generateLegacySim + generateLegacySim + false + + + generationId + Generation Id + 0 + + + globalResetBus + Global reset + false + + + hdlLanguage + hdlLanguage + VERILOG + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + + + + sopcBorderPoints + Use SOPC Builder port naming + false + + + systemHash + systemHash + 0 + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>amm_m0_clock</key> + <value> + <connectionPointName>amm_m0_clock</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>axi_s0</key> + <value> + <connectionPointName>axi_s0</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='axi_ep.axi_s0' start='0x0' end='0x400000000' datawidth='1024' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>34</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>1024</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + systemScripts + systemScripts + + + + testBenchDutName + Use Test Bench Naming Pattern + + + + timeStamp + timeStamp + 0 + + + useTestBenchNamingPattern + Use Test Bench Naming Pattern + false + + + + + + + + + Altera Corporation + amm_clock + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>in_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>in_clk</value> + </entry> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>false</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_clock_bridge</className> + <version>19.1</version> + <displayName>Clock Bridge Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>DERIVED_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>in_clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>in_clk</key> + <value> + <connectionPointName>in_clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>out_clk</key> + <value> + <connectionPointName>out_clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>in_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>in_clk</value> + </entry> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>false</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>amm_clock</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>amm_clock</fileSetName> + <fileSetFixedName>amm_clock</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>amm_clock</fileSetName> + <fileSetFixedName>amm_clock</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>amm_clock</fileSetName> + <fileSetFixedName>amm_clock</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/ofs_ddr_axi_bridge/amm_clock.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + amm_reset + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_reset</name> + <role>reset</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_reset_bridge</className> + <version>19.1</version> + <displayName>Reset Bridge Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_CLK_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_reset</name> + <role>reset</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>amm_reset</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>amm_reset</fileSetName> + <fileSetFixedName>amm_reset</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>amm_reset</fileSetName> + <fileSetFixedName>amm_reset</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>amm_reset</fileSetName> + <fileSetFixedName>amm_reset</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/ofs_ddr_axi_bridge/amm_reset.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + avmm_ep + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>av_s0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_address</name> + <role>address</role> + <direction>Input</direction> + <width>27</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>1024</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>128</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_burstcount</name> + <role>burstcount</role> + <direction>Input</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_readdatavalid</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>1024</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>17179869184</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>av_m0</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>m0_address</name> + <role>address</role> + <direction>Output</direction> + <width>27</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>576</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_byteenable</name> + <role>byteenable</role> + <direction>Output</direction> + <width>72</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_burstcount</name> + <role>burstcount</role> + <direction>Output</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>576</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>BOTH</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>ddr_avmm_slave_endpoint</className> + <version>1.0</version> + <displayName>ddr_avmm_slave_endpoint</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>av_s0</key> + <value> + <connectionPointName>av_s0</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='av_s0' start='0x0' end='0x400000000' datawidth='1024' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>34</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>1024</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>av_s0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_address</name> + <role>address</role> + <direction>Input</direction> + <width>27</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>s0_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>s0_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>s0_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>1024</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>s0_byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>128</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>s0_burstcount</name> + <role>burstcount</role> + <direction>Input</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>s0_readdatavalid</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>s0_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>1024</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>s0_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>17179869184</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>av_m0</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>m0_address</name> + <role>address</role> + <direction>Output</direction> + <width>27</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>m0_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>m0_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>m0_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>576</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>m0_byteenable</name> + <role>byteenable</role> + <direction>Output</direction> + <width>72</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>m0_burstcount</name> + <role>burstcount</role> + <direction>Output</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>m0_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>m0_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>576</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>m0_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>BOTH</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>avmm_ep</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>avmm_ep</fileSetName> + <fileSetFixedName>avmm_ep</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>avmm_ep</fileSetName> + <fileSetFixedName>avmm_ep</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>avmm_ep</fileSetName> + <fileSetFixedName>avmm_ep</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/ofs_ddr_axi_bridge/avmm_ep.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + axi_ep + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>axi_s0_resetn</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>axi_s0_resetn</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>axi_s0_clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>BOTH</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>axi_s0_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>axi_s0_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>axi_m0_resetn</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>axi_m0_resetn</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>axi_m0_clock</value> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>axi_s0_resetn</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>axi_s0_resetn</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>BOTH</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>axi_m0_clock</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>axi_m0_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>axi_s0_clk</value> + </entry> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>false</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>axi_m0</name> + <type>axi4</type> + <isStart>true</isStart> + <ports> + <port> + <name>axi_m0_awid</name> + <role>awid</role> + <direction>Output</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>34</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_awlen</name> + <role>awlen</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_awsize</name> + <role>awsize</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_awburst</name> + <role>awburst</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>1024</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>128</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_wlast</name> + <role>wlast</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_bid</name> + <role>bid</role> + <direction>Input</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_arid</name> + <role>arid</role> + <direction>Output</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>34</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_arlen</name> + <role>arlen</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_arsize</name> + <role>arsize</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_arburst</name> + <role>arburst</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_rid</name> + <role>rid</role> + <direction>Input</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>1024</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_rlast</name> + <role>rlast</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_m0_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>axi_m0_clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>axi_m0_resetn</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + <entry> + <key>issuesINCRBursts</key> + <value>true</value> + </entry> + <entry> + <key>issuesWRAPBursts</key> + <value>false</value> + </entry> + <entry> + <key>issuesFIXEDBursts</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>axi_s0</name> + <type>axi4</type> + <isStart>false</isStart> + <ports> + <port> + <name>axi_s0_awid</name> + <role>awid</role> + <direction>Input</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>34</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_awlen</name> + <role>awlen</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_awsize</name> + <role>awsize</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_awburst</name> + <role>awburst</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>1024</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>128</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_wlast</name> + <role>wlast</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_bid</name> + <role>bid</role> + <direction>Output</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_arid</name> + <role>arid</role> + <direction>Input</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>34</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_arlen</name> + <role>arlen</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_arsize</name> + <role>arsize</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_arburst</name> + <role>arburst</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_rid</name> + <role>rid</role> + <direction>Output</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>1024</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_rlast</name> + <role>rlast</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>axi_s0_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>axi_s0_clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>axi_s0_resetn</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>ddr_axi_master_endpoint</className> + <version>1.0</version> + <displayName>ddr_axi_master_endpoint</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>axi_m0_clock</key> + <value> + <connectionPointName>axi_m0_clock</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>axi_s0</key> + <value> + <connectionPointName>axi_s0</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='axi_s0' start='0x0' end='0x400000000' datawidth='1024' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>34</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>1024</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>axi_s0_resetn</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>axi_s0_resetn</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>axi_s0_clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>BOTH</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>axi_s0_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>axi_s0_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>axi_m0_resetn</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>axi_m0_resetn</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>axi_m0_clock</value> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>axi_s0_resetn</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>axi_s0_resetn</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>BOTH</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>axi_m0_clock</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>axi_m0_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>axi_s0_clk</value> + </entry> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>false</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>axi_m0</name> + <type>axi4</type> + <isStart>true</isStart> + <ports> + <port> + <name>axi_m0_awid</name> + <role>awid</role> + <direction>Output</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>34</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_awlen</name> + <role>awlen</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_awsize</name> + <role>awsize</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_awburst</name> + <role>awburst</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_m0_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_m0_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>1024</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>128</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_wlast</name> + <role>wlast</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_m0_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_m0_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_m0_bid</name> + <role>bid</role> + <direction>Input</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_m0_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_m0_arid</name> + <role>arid</role> + <direction>Output</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>34</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_arlen</name> + <role>arlen</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_arsize</name> + <role>arsize</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_arburst</name> + <role>arburst</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_m0_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_m0_rid</name> + <role>rid</role> + <direction>Input</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>1024</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_rlast</name> + <role>rlast</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_m0_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_m0_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_m0_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>axi_m0_clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>axi_m0_resetn</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>issuesINCRBursts</key> + <value>true</value> + </entry> + <entry> + <key>issuesWRAPBursts</key> + <value>false</value> + </entry> + <entry> + <key>issuesFIXEDBursts</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>axi_s0</name> + <type>axi4</type> + <isStart>false</isStart> + <ports> + <port> + <name>axi_s0_awid</name> + <role>awid</role> + <direction>Input</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>34</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_awlen</name> + <role>awlen</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_awsize</name> + <role>awsize</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_awburst</name> + <role>awburst</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_s0_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_s0_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>1024</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>128</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_wlast</name> + <role>wlast</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_s0_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_s0_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_s0_bid</name> + <role>bid</role> + <direction>Output</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_s0_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_s0_arid</name> + <role>arid</role> + <direction>Input</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>34</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_arlen</name> + <role>arlen</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_arsize</name> + <role>arsize</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_arburst</name> + <role>arburst</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_s0_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_s0_rid</name> + <role>rid</role> + <direction>Output</direction> + <width>6</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>1024</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_rlast</name> + <role>rlast</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_s0_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>axi_s0_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>axi_s0_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>axi_s0_clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>axi_s0_resetn</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>axi_ep</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>axi_ep</fileSetName> + <fileSetFixedName>axi_ep</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>axi_ep</fileSetName> + <fileSetFixedName>axi_ep</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>axi_ep</fileSetName> + <fileSetFixedName>axi_ep</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/ofs_ddr_axi_bridge/axi_ep.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Intel Corporation + addressMap + addressMap + 1.0 + + + avmm_ep.av_m0 + + + + + avmm_ep.av_s0 + + + + axi_ep.axi_m0 + + + + 0x0000_0000_0000_0000 + + + + + + + axi_ep.axi_m0 + + + avmm_ep.av_s0 + 0x0000_0000_0000_0000 + 0x0000_0004_0000_0000 + + + + + + + + false + false + + \ No newline at end of file diff --git a/ipss/mem/axi_bridge/ofs_pipeline_reg.sv b/ipss/mem/axi_bridge/ofs_pipeline_reg.sv new file mode 100644 index 0000000..1d3dda8 --- /dev/null +++ b/ipss/mem/axi_bridge/ofs_pipeline_reg.sv @@ -0,0 +1,166 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Pipeline register for interface which implements valid-ready handshaking +// +//----------------------------------------------------------------------------- + +`timescale 1 ps / 1 ps +module ofs_pipeline_reg +#( + // Register mode for read address channel + parameter REG_MODE = 0, // 0: skid buffer 1: simple buffer 2: bypass + parameter WIDTH = 8 +)( + input clk, + input rst_n, + + // Slave interface + output logic s_ready, + input logic s_valid, + input logic [WIDTH-1:0] s_data, + + // Master interface + input logic m_ready, + output logic m_valid, + output logic [WIDTH-1:0] m_data +); + +generate +if (REG_MODE == 0) begin + // -------------------------------------- + // skid buffer + // -------------------------------------- + // Registers & signals + logic s_valid_reg; + logic [WIDTH-1:0] s_data_reg; + logic s_ready_reg; + logic s_ready_reg_dup; + logic use_reg; + + logic m_valid_pre; + logic [WIDTH-1:0] m_data_pre; + logic m_valid_reg; + logic [WIDTH-1:0] m_data_reg; + + // -------------------------------------- + // Pipeline stage + // + // s_tready is delayed by one cycle, master will see tready assertions one cycle later. + // Buffer the data when tready transitions from high->low + // + // This implementation buffers idle cycles should ready transition on such cycles. + // i.e. It doesn't take in new data from s_* even though m_valid_reg=0 or when m_ready=0 + // This is a potential cause for throughput loss. + // Not buffering idle cycles costs logic on the tready path. + // -------------------------------------- + assign s_ready_pre = (m_ready || ~m_valid); + + always @(posedge clk) begin + if (~rst_n) begin + s_ready_reg <= 1'b0; + s_ready_reg_dup <= 1'b0; + end else begin + s_ready_reg <= s_ready_pre; + s_ready_reg_dup <= m_ready; + end + end + + // -------------------------------------- + // On the first cycle after reset, the pass-through + // must not be used or downstream logic may sample + // the same command twice because of the delay in + // transmitting a rising ready. + // -------------------------------------- + // Check whether to drive the output with buffer registers when output is ready + always @(posedge clk) begin + if (~rst_n) begin + use_reg <= 1'b1; + end else if (s_ready_pre) begin + // stop using the buffer when s_ready_pre is high (m_ready=1 or m_valid=0) + use_reg <= 1'b0; + end else if (~m_ready && s_ready_reg) begin + use_reg <= 1'b1; + end + end + + // Buffer registers + always @(posedge clk) begin + if (~rst_n) s_valid_reg <= 1'b0; + else if (s_ready_reg_dup) s_valid_reg <= s_valid; + end + + always @(posedge clk) begin + if (s_ready_reg_dup) s_data_reg <= s_data; + end + + // Output selection (between buffer register and input) + assign m_valid_pre = use_reg ? s_valid_reg : s_valid; + assign m_data_pre = use_reg ? s_data_reg : s_data; + + // Register AXI signals + always @(posedge clk) begin + if (m_ready) m_data_reg <= m_data_pre; + end + + // Generate ready and valid signals + always @(posedge clk) begin + if (~rst_n) m_valid_reg <= 1'b0; + else if (m_ready) m_valid_reg <= m_valid_pre; + end + + // Output assignment + assign s_ready = s_ready_reg; + assign m_valid = m_valid_reg; + assign m_data = m_data_reg; + +end else if (REG_MODE == 1) begin + + // -------------------------------------- + // Simple pipeline register with bubble cycle + // -------------------------------------- + logic s_ready_reg; + logic m_valid_reg; + logic [WIDTH-1:0] m_data_reg; + + // Generate ready and valid signals + always @(posedge clk) begin + if (~rst_n) begin + s_ready_reg <= 1'b0; + m_valid_reg <= 1'b0; + end else begin + if (s_ready_reg && s_valid) begin + s_ready_reg <= 1'b0; + m_valid_reg <= 1'b1; + end else if (~s_ready_reg && m_ready) begin + s_ready_reg <= 1'b1; + m_valid_reg <= 1'b0; + end + end + end + + // Register AXI signals + always @(posedge clk) begin + if (s_ready_reg) m_data_reg <=s_data; + end + + // Output assignment + assign s_ready = s_ready_reg; + assign m_valid = m_valid_reg; + assign m_data = m_data_reg; + +end else begin + + // -------------------------------------- + // bypass mode + // -------------------------------------- + assign s_ready = m_ready; + assign m_valid = s_valid; + assign m_data = s_data; +end +endgenerate + +endmodule diff --git a/ipss/mem/custom_altera_avalon_mm_bridge.sv b/ipss/mem/custom_altera_avalon_mm_bridge.sv new file mode 100755 index 0000000..c0d24ff --- /dev/null +++ b/ipss/mem/custom_altera_avalon_mm_bridge.sv @@ -0,0 +1,299 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +//----------------------------------------------------------------------------- +// Description +//----------------------------------------------------------------------------- +// Customized version of Avalon-MM pipeline bridge IP for DCP local memory +// subsystem usage +// -------------------------------------- +// +// Changes to improve timing +// 1. Updated burstcount and byteenable power-up value from high to low. +// This will prevent synthesis from inserting inverters at the input and output +// of the register. +// +// Implication: No +// +// 2. Changed reset scheme to synchronous reset. Only control signals are reset. +// Implication: No +// +// 3. Duplicated wr_waitrequest_reg to wr_waitrequest_reg_dup and have it +// drives the enable port of buffer registers wr_reg_* which were +// previously driven by wait_rise comb cell. +// With this update, the buffer registers will sample new value when +// wr_waitrequest_reg_dup is de-asserted and stop sampling when it is asserted. +// +// Implication: No +// +// 4. Remove cmd_read and cmd_write from the enable path of CMD registers +// to get rid of a comb cell that drives the enable port of CMD registers. +// This requires the slave to not assert waitrequest in IDLE state (no +// command) which is true for Arria 10 EMIF IP. +// +// Implication: +// There will be 2 NOP cycles when CMD registers and buffer +// registers have no read/write CMD right before slave waitrequest is asserted. +// This is different from previous implementation in that the CMD registers and buffer registers +// stop sampling new value when slave waitrequest is asserted. +// +// 5. Added CMD_PIPE_DEPTH option to control the pipeline stages for command datapath. +// Added READDATA_PIPE_DEPTH option to control the pipeline stage for read resposne datapath +// +// -------------------------------------- + +`timescale 1 ns / 1 ns +module custom_altera_avalon_mm_bridge +#( + parameter DATA_WIDTH = 32, + parameter SYMBOL_WIDTH = 8, + parameter RESPONSE_WIDTH = 2, + parameter HDL_ADDR_WIDTH = 10, + parameter BURSTCOUNT_WIDTH = 1, + + parameter CMD_PIPE_DEPTH = 1, // Specifies how many feed-forward (unstallable) pipe stages are placed on the command path. Min value 1. + parameter READDATA_PIPE_DEPTH = 1, // Specifies how many stages of pipelining are placed on the readdata and readdatavalid. Min value 1. + + // -------------------------------------- + // Derived parameters + // -------------------------------------- + parameter BYTEEN_WIDTH = DATA_WIDTH / SYMBOL_WIDTH +) +( + input clk, + input reset, + + output s0_waitrequest, + output [DATA_WIDTH-1:0] s0_readdata, + output s0_readdatavalid, + output [RESPONSE_WIDTH-1:0] s0_response, + input [BURSTCOUNT_WIDTH-1:0] s0_burstcount, + input [DATA_WIDTH-1:0] s0_writedata, + input [HDL_ADDR_WIDTH-1:0] s0_address, + input s0_write, + input s0_read, + input [BYTEEN_WIDTH-1:0] s0_byteenable, + input s0_debugaccess, + + input m0_waitrequest, + input [DATA_WIDTH-1:0] m0_readdata, + input m0_readdatavalid, + input [RESPONSE_WIDTH-1:0] m0_response, + output [BURSTCOUNT_WIDTH-1:0] m0_burstcount, + output [DATA_WIDTH-1:0] m0_writedata, + output [HDL_ADDR_WIDTH-1:0] m0_address, + output m0_write, + output m0_read, + output [BYTEEN_WIDTH-1:0] m0_byteenable, + output m0_debugaccess +); + // -------------------------------------- + // Registers & signals + // -------------------------------------- + wire cmd_waitrequest; +(*dont_retime*) reg [CMD_PIPE_DEPTH:1] [BURSTCOUNT_WIDTH-1:0] cmd_burstcount; +(*dont_retime*) reg [CMD_PIPE_DEPTH:1] [DATA_WIDTH-1:0] cmd_writedata; +(*dont_retime*) reg [CMD_PIPE_DEPTH:1] [HDL_ADDR_WIDTH-1:0] cmd_address; +(*dont_retime*) reg [CMD_PIPE_DEPTH:1] cmd_write; +(*dont_retime*) reg [CMD_PIPE_DEPTH:1] cmd_read; +(*dont_retime*) reg [CMD_PIPE_DEPTH:1] [BYTEEN_WIDTH-1:0] cmd_byteenable; +(*dont_retime*) reg [CMD_PIPE_DEPTH:1] cmd_debugaccess; + +(*dont_retime*) reg [BURSTCOUNT_WIDTH-1:0] wr_burstcount; +(*dont_retime*) reg [DATA_WIDTH-1:0] wr_writedata; +(*dont_retime*) reg [HDL_ADDR_WIDTH-1:0] wr_address; +(*dont_retime*) reg wr_write; +(*dont_retime*) reg wr_read; +(*dont_retime*) reg [BYTEEN_WIDTH-1:0] wr_byteenable; +(*dont_retime*) reg wr_debugaccess; + +(*dont_retime*) reg [BURSTCOUNT_WIDTH-1:0] wr_reg_burstcount; +(*dont_retime*) reg [DATA_WIDTH-1:0] wr_reg_writedata; +(*dont_retime*) reg [HDL_ADDR_WIDTH-1:0] wr_reg_address; +(*dont_retime*) reg wr_reg_write; +(*dont_retime*) reg wr_reg_read; +(*dont_retime*) reg [BYTEEN_WIDTH-1:0] wr_reg_byteenable; +(*dont_retime*) reg wr_reg_waitrequest; +(*dont_retime,dont_merge*) reg wr_reg_waitrequest_dup; +(*dont_retime*) reg wr_reg_debugaccess; + +(*dont_retime*) reg use_reg; + wire wait_rise; + + reg [READDATA_PIPE_DEPTH:1] [DATA_WIDTH-1:0] rsp_readdata; +(*dont_retime*) reg [READDATA_PIPE_DEPTH:1] rsp_readdatavalid; +(*dont_retime*) reg [READDATA_PIPE_DEPTH:1] [RESPONSE_WIDTH-1:0] rsp_response; + + // -------------------------------------- + // Command pipeline + // + // Registers all command signals, including waitrequest + // -------------------------------------- + // -------------------------------------- + // Waitrequest Pipeline Stage + // + // Output waitrequest is delayed by one cycle, which means + // that a master will see waitrequest assertions one cycle + // too late. + // + // Solution: buffer the command when waitrequest transitions + // from low->high. As an optimization, we can safely assume + // waitrequest is low by default because downstream logic + // in the bridge ensures this. + // + // Note: this implementation buffers idle cycles should + // waitrequest transition on such cycles. This is a potential + // cause for throughput loss, but ye olde pipeline bridge did + // the same for years and no one complained. Not buffering idle + // cycles costs logic on the waitrequest path. + // -------------------------------------- + assign s0_waitrequest = wr_reg_waitrequest; + assign wait_rise = ~wr_reg_waitrequest & cmd_waitrequest; + + always @(posedge clk) begin + if (reset) begin + wr_reg_waitrequest <= 1'b1; + wr_reg_waitrequest_dup <= 1'b1; + end else begin + wr_reg_waitrequest <= cmd_waitrequest; + wr_reg_waitrequest_dup <= cmd_waitrequest; + end + end + + // -------------------------------------- + // Bit of trickiness here, deserving of a long comment. + // + // On the first cycle after reset, the pass-through + // must not be used or downstream logic may sample + // the same command twice because of the delay in + // transmitting a falling waitrequest. + // + // Using the registered command works on the condition + // that downstream logic deasserts waitrequest + // immediately after reset, which is true of the + // next stage in this bridge. + // -------------------------------------- + always @(posedge clk) begin + if (~wr_reg_waitrequest_dup) begin + wr_reg_writedata <= s0_writedata; + wr_reg_byteenable <= s0_byteenable; + wr_reg_address <= s0_address; + wr_reg_write <= s0_write; + wr_reg_read <= s0_read; + wr_reg_burstcount <= s0_burstcount; + wr_reg_debugaccess <= s0_debugaccess; + end + + // stop using the buffer when waitrequest is low + if (~cmd_waitrequest) + use_reg <= 1'b0; + else if (wait_rise) begin + use_reg <= 1'b1; + end + + if (reset) begin + use_reg <= 1'b1; + wr_reg_write <= 1'b0; + wr_reg_read <= 1'b0; + wr_reg_debugaccess <= 1'b0; + end + end + + always @* begin + wr_burstcount = s0_burstcount; + wr_writedata = s0_writedata; + wr_address = s0_address; + wr_write = s0_write; + wr_read = s0_read; + wr_byteenable = s0_byteenable; + wr_debugaccess = s0_debugaccess; + + if (use_reg) begin + wr_burstcount = wr_reg_burstcount; + wr_writedata = wr_reg_writedata; + wr_address = wr_reg_address; + wr_write = wr_reg_write; + wr_read = wr_reg_read; + wr_byteenable = wr_reg_byteenable; + wr_debugaccess = wr_reg_debugaccess; + end + end + + // -------------------------------------- + // Master-Slave Signal Pipeline Stage + // + // cmd_waitrequest is deasserted during reset, + // which is not spec-compliant, but is ok for an internal signal. + // -------------------------------------- + assign cmd_waitrequest = m0_waitrequest; + + // First stage pipeline + always @(posedge clk) begin + if (~cmd_waitrequest) begin + cmd_writedata[1] <= wr_writedata; + cmd_byteenable[1] <= wr_byteenable; + cmd_address[1] <= wr_address; + cmd_write[1] <= wr_write; + cmd_read[1] <= wr_read; + cmd_burstcount[1] <= wr_burstcount; + cmd_debugaccess[1] <= wr_debugaccess; + end + + if (reset) begin + cmd_write[1] <= 1'b0; + cmd_read[1] <= 1'b0; + cmd_debugaccess[1] <= 1'b0; + end + end + + // Next-stage pipeline for CMD_PIPE_DEPTH > 1 + always @(posedge clk) begin + for (int i=2; i<= CMD_PIPE_DEPTH; i++) begin + cmd_writedata [i] <= cmd_writedata [i-1]; + cmd_byteenable [i] <= cmd_byteenable [i-1]; + cmd_address [i] <= cmd_address [i-1]; + cmd_write [i] <= cmd_write [i-1]; + cmd_read [i] <= cmd_read [i-1]; + cmd_burstcount [i] <= cmd_burstcount [i-1]; + cmd_debugaccess[i] <= cmd_debugaccess[i-1]; + end + end + + assign m0_burstcount = cmd_burstcount[CMD_PIPE_DEPTH]; + assign m0_writedata = cmd_writedata[CMD_PIPE_DEPTH]; + assign m0_address = cmd_address[CMD_PIPE_DEPTH]; + assign m0_write = cmd_write[CMD_PIPE_DEPTH]; + assign m0_read = cmd_read[CMD_PIPE_DEPTH]; + assign m0_byteenable = cmd_byteenable[CMD_PIPE_DEPTH]; + assign m0_debugaccess = cmd_debugaccess[CMD_PIPE_DEPTH]; + + // -------------------------------------- + // Response pipeline + // + // Registers all response signals + // -------------------------------------- + // First stage pipeline + always @(posedge clk) begin + rsp_readdatavalid[1] <= m0_readdatavalid; + rsp_readdata[1] <= m0_readdata; + rsp_response[1] <= m0_response; + + if (reset) begin + rsp_readdatavalid[1] <= 1'b0; + end + end + + // Next stage pipeline for READDATA_PIPE_DEPTH > 1 + always @(posedge clk) begin + for (int i=2; i<= READDATA_PIPE_DEPTH; i++) begin + rsp_readdatavalid[i] <= rsp_readdatavalid[i-1]; + rsp_readdata[i] <= rsp_readdata[i-1]; + rsp_response[i] <= rsp_response[i-1]; + end + end + + assign s0_readdatavalid = rsp_readdatavalid[READDATA_PIPE_DEPTH]; + assign s0_readdata = rsp_readdata[READDATA_PIPE_DEPTH]; + assign s0_response = rsp_response[READDATA_PIPE_DEPTH]; + +endmodule diff --git a/ipss/mem/custom_altera_avalon_mm_bridge.v b/ipss/mem/custom_altera_avalon_mm_bridge.v new file mode 100755 index 0000000..b6e0c13 --- /dev/null +++ b/ipss/mem/custom_altera_avalon_mm_bridge.v @@ -0,0 +1,299 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +//----------------------------------------------------------------------------- +// Description +//----------------------------------------------------------------------------- +// Customized version of Avalon-MM pipeline bridge IP for DCP local memory +// subsystem usage +// -------------------------------------- +// +// Changes to improve timing +// 1. Updated burstcount and byteenable power-up value from high to low. +// This will prevent synthesis from inserting inverters at the input and output +// of the register. +// +// Implication: No +// +// 2. Changed reset scheme to synchronous reset. Only control signals are reset. +// Implication: No +// +// 3. Duplicated wr_waitrequest_reg to wr_waitrequest_reg_dup and have it +// drives the enable port of buffer registers wr_reg_* which were +// previously driven by wait_rise comb cell. +// With this update, the buffer registers will sample new value when +// wr_waitrequest_reg_dup is de-asserted and stop sampling when it is asserted. +// +// Implication: No +// +// 4. Remove cmd_read and cmd_write from the enable path of CMD registers +// to get rid of a comb cell that drives the enable port of CMD registers. +// This requires the slave to not assert waitrequest in IDLE state (no +// command) which is true for Arria 10 EMIF IP. +// +// Implication: +// There will be 2 NOP cycles when CMD registers and buffer +// registers have no read/write CMD right before slave waitrequest is asserted. +// This is different from previous implementation in that the CMD registers and buffer registers +// stop sampling new value when slave waitrequest is asserted. +// +// 5. Added CMD_PIPE_DEPTH option to control the pipeline stages for command datapath. +// Added READDATA_PIPE_DEPTH option to control the pipeline stage for read resposne datapath +// +// -------------------------------------- + +`timescale 1 ns / 1 ns +module custom_altera_avalon_mm_bridge +#( + parameter DATA_WIDTH = 32, + parameter SYMBOL_WIDTH = 8, + parameter RESPONSE_WIDTH = 2, + parameter HDL_ADDR_WIDTH = 10, + parameter BURSTCOUNT_WIDTH = 1, + + parameter CMD_PIPE_DEPTH = 1, // Specifies how many feed-forward (unstallable) pipe stages are placed on the command path. Min value 1. + parameter READDATA_PIPE_DEPTH = 1, // Specifies how many stages of pipelining are placed on the readdata and readdatavalid. Min value 1. + + // -------------------------------------- + // Derived parameters + // -------------------------------------- + parameter BYTEEN_WIDTH = DATA_WIDTH / SYMBOL_WIDTH +) +( + input clk, + input reset, + + output s0_waitrequest, + output [DATA_WIDTH-1:0] s0_readdata, + output s0_readdatavalid, + output [RESPONSE_WIDTH-1:0] s0_response, + input [BURSTCOUNT_WIDTH-1:0] s0_burstcount, + input [DATA_WIDTH-1:0] s0_writedata, + input [HDL_ADDR_WIDTH-1:0] s0_address, + input s0_write, + input s0_read, + input [BYTEEN_WIDTH-1:0] s0_byteenable, + input s0_debugaccess, + + input m0_waitrequest, + input [DATA_WIDTH-1:0] m0_readdata, + input m0_readdatavalid, + input [RESPONSE_WIDTH-1:0] m0_response, + output [BURSTCOUNT_WIDTH-1:0] m0_burstcount, + output [DATA_WIDTH-1:0] m0_writedata, + output [HDL_ADDR_WIDTH-1:0] m0_address, + output m0_write, + output m0_read, + output [BYTEEN_WIDTH-1:0] m0_byteenable, + output m0_debugaccess +); + // -------------------------------------- + // Registers & signals + // -------------------------------------- + wire cmd_waitrequest; +(*dont_retime*) reg [CMD_PIPE_DEPTH:1] [BURSTCOUNT_WIDTH-1:0] cmd_burstcount; +(*dont_retime*) reg [CMD_PIPE_DEPTH:1] [DATA_WIDTH-1:0] cmd_writedata; +(*dont_retime*) reg [CMD_PIPE_DEPTH:1] [HDL_ADDR_WIDTH-1:0] cmd_address; +(*dont_retime*) reg [CMD_PIPE_DEPTH:1] cmd_write; +(*dont_retime*) reg [CMD_PIPE_DEPTH:1] cmd_read; +(*dont_retime*) reg [CMD_PIPE_DEPTH:1] [BYTEEN_WIDTH-1:0] cmd_byteenable; +(*dont_retime*) reg [CMD_PIPE_DEPTH:1] cmd_debugaccess; + +(*dont_retime*) reg [BURSTCOUNT_WIDTH-1:0] wr_burstcount; +(*dont_retime*) reg [DATA_WIDTH-1:0] wr_writedata; +(*dont_retime*) reg [HDL_ADDR_WIDTH-1:0] wr_address; +(*dont_retime*) reg wr_write; +(*dont_retime*) reg wr_read; +(*dont_retime*) reg [BYTEEN_WIDTH-1:0] wr_byteenable; +(*dont_retime*) reg wr_debugaccess; + +(*dont_retime*) reg [BURSTCOUNT_WIDTH-1:0] wr_reg_burstcount; +(*dont_retime*) reg [DATA_WIDTH-1:0] wr_reg_writedata; +(*dont_retime*) reg [HDL_ADDR_WIDTH-1:0] wr_reg_address; +(*dont_retime*) reg wr_reg_write; +(*dont_retime*) reg wr_reg_read; +(*dont_retime*) reg [BYTEEN_WIDTH-1:0] wr_reg_byteenable; +(*dont_retime*) reg wr_reg_waitrequest; +(*dont_retime,dont_merge*) reg wr_reg_waitrequest_dup; +(*dont_retime*) reg wr_reg_debugaccess; + +(*dont_retime*) reg use_reg; + wire wait_rise; + + reg [READDATA_PIPE_DEPTH:1] [DATA_WIDTH-1:0] rsp_readdata; +(*dont_retime*) reg [READDATA_PIPE_DEPTH:1] rsp_readdatavalid; +(*dont_retime*) reg [READDATA_PIPE_DEPTH:1] [RESPONSE_WIDTH-1:0] rsp_response; +integer i; + // -------------------------------------- + // Command pipeline + // + // Registers all command signals, including waitrequest + // -------------------------------------- + // -------------------------------------- + // Waitrequest Pipeline Stage + // + // Output waitrequest is delayed by one cycle, which means + // that a master will see waitrequest assertions one cycle + // too late. + // + // Solution: buffer the command when waitrequest transitions + // from low->high. As an optimization, we can safely assume + // waitrequest is low by default because downstream logic + // in the bridge ensures this. + // + // Note: this implementation buffers idle cycles should + // waitrequest transition on such cycles. This is a potential + // cause for throughput loss, but ye olde pipeline bridge did + // the same for years and no one complained. Not buffering idle + // cycles costs logic on the waitrequest path. + // -------------------------------------- + assign s0_waitrequest = wr_reg_waitrequest; + assign wait_rise = ~wr_reg_waitrequest & cmd_waitrequest; + + always @(posedge clk) begin + if (reset) begin + wr_reg_waitrequest <= 1'b1; + wr_reg_waitrequest_dup <= 1'b1; + end else begin + wr_reg_waitrequest <= cmd_waitrequest; + wr_reg_waitrequest_dup <= cmd_waitrequest; + end + end + + // -------------------------------------- + // Bit of trickiness here, deserving of a long comment. + // + // On the first cycle after reset, the pass-through + // must not be used or downstream logic may sample + // the same command twice because of the delay in + // transmitting a falling waitrequest. + // + // Using the registered command works on the condition + // that downstream logic deasserts waitrequest + // immediately after reset, which is true of the + // next stage in this bridge. + // -------------------------------------- + always @(posedge clk) begin + if (~wr_reg_waitrequest_dup) begin + wr_reg_writedata <= s0_writedata; + wr_reg_byteenable <= s0_byteenable; + wr_reg_address <= s0_address; + wr_reg_write <= s0_write; + wr_reg_read <= s0_read; + wr_reg_burstcount <= s0_burstcount; + wr_reg_debugaccess <= s0_debugaccess; + end + + // stop using the buffer when waitrequest is low + if (~cmd_waitrequest) + use_reg <= 1'b0; + else if (wait_rise) begin + use_reg <= 1'b1; + end + + if (reset) begin + use_reg <= 1'b1; + wr_reg_write <= 1'b0; + wr_reg_read <= 1'b0; + wr_reg_debugaccess <= 1'b0; + end + end + + always @* begin + wr_burstcount = s0_burstcount; + wr_writedata = s0_writedata; + wr_address = s0_address; + wr_write = s0_write; + wr_read = s0_read; + wr_byteenable = s0_byteenable; + wr_debugaccess = s0_debugaccess; + + if (use_reg) begin + wr_burstcount = wr_reg_burstcount; + wr_writedata = wr_reg_writedata; + wr_address = wr_reg_address; + wr_write = wr_reg_write; + wr_read = wr_reg_read; + wr_byteenable = wr_reg_byteenable; + wr_debugaccess = wr_reg_debugaccess; + end + end + + // -------------------------------------- + // Master-Slave Signal Pipeline Stage + // + // cmd_waitrequest is deasserted during reset, + // which is not spec-compliant, but is ok for an internal signal. + // -------------------------------------- + assign cmd_waitrequest = m0_waitrequest; + + // First stage pipeline + always @(posedge clk) begin + if (~cmd_waitrequest) begin + cmd_writedata[1] <= wr_writedata; + cmd_byteenable[1] <= wr_byteenable; + cmd_address[1] <= wr_address; + cmd_write[1] <= wr_write; + cmd_read[1] <= wr_read; + cmd_burstcount[1] <= wr_burstcount; + cmd_debugaccess[1] <= wr_debugaccess; + end + + if (reset) begin + cmd_write[1] <= 1'b0; + cmd_read[1] <= 1'b0; + cmd_debugaccess[1] <= 1'b0; + end + end + + // Next-stage pipeline for CMD_PIPE_DEPTH > 1 + always @(posedge clk) begin + for ( i=2; i<= CMD_PIPE_DEPTH; i=i+1) begin + cmd_writedata [i] <= cmd_writedata [i-1]; + cmd_byteenable [i] <= cmd_byteenable [i-1]; + cmd_address [i] <= cmd_address [i-1]; + cmd_write [i] <= cmd_write [i-1]; + cmd_read [i] <= cmd_read [i-1]; + cmd_burstcount [i] <= cmd_burstcount [i-1]; + cmd_debugaccess[i] <= cmd_debugaccess[i-1]; + end + end + + assign m0_burstcount = cmd_burstcount[CMD_PIPE_DEPTH]; + assign m0_writedata = cmd_writedata[CMD_PIPE_DEPTH]; + assign m0_address = cmd_address[CMD_PIPE_DEPTH]; + assign m0_write = cmd_write[CMD_PIPE_DEPTH]; + assign m0_read = cmd_read[CMD_PIPE_DEPTH]; + assign m0_byteenable = cmd_byteenable[CMD_PIPE_DEPTH]; + assign m0_debugaccess = cmd_debugaccess[CMD_PIPE_DEPTH]; + + // -------------------------------------- + // Response pipeline + // + // Registers all response signals + // -------------------------------------- + // First stage pipeline + always @(posedge clk) begin + rsp_readdatavalid[1] <= m0_readdatavalid; + rsp_readdata[1] <= m0_readdata; + rsp_response[1] <= m0_response; + + if (reset) begin + rsp_readdatavalid[1] <= 1'b0; + end + end + + // Next stage pipeline for READDATA_PIPE_DEPTH > 1 + always @(posedge clk) begin + for ( i=2; i<= READDATA_PIPE_DEPTH; i=i+1) begin + rsp_readdatavalid[i] <= rsp_readdatavalid[i-1]; + rsp_readdata[i] <= rsp_readdata[i-1]; + rsp_response[i] <= rsp_response[i-1]; + end + end + + assign s0_readdatavalid = rsp_readdatavalid[READDATA_PIPE_DEPTH]; + assign s0_readdata = rsp_readdata[READDATA_PIPE_DEPTH]; + assign s0_response = rsp_response[READDATA_PIPE_DEPTH]; + +endmodule diff --git a/ipss/mem/ddr_avmm_bridge.v b/ipss/mem/ddr_avmm_bridge.v new file mode 100644 index 0000000..ce8a3c2 --- /dev/null +++ b/ipss/mem/ddr_avmm_bridge.v @@ -0,0 +1,80 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +//----------------------------------------------------------------------------- +// Description +//----------------------------------------------------------------------------- +// ddr_avmm_bridge module is the top level instantiation of Customized +// Avalon-MM pipeline bridge + +`timescale 1 ps / 1 ps +module ddr_avmm_bridge #( + parameter DATA_WIDTH = 512, + parameter SYMBOL_WIDTH = 8, + parameter ADDR_WIDTH = 26, + parameter BURSTCOUNT_WIDTH = 1, + parameter READDATA_PIPE_DEPTH = 1, + + // Derived parameter + parameter BYTEEN_WIDTH = DATA_WIDTH / SYMBOL_WIDTH +) ( + input wire clk, // clk.clk + input wire m0_waitrequest, // m0.waitrequest + input wire [DATA_WIDTH-1:0] m0_readdata, // .readdata + input wire m0_readdatavalid, // .readdatavalid + output wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount, // .burstcount + output wire [DATA_WIDTH-1:0] m0_writedata, // .writedata + output wire [ADDR_WIDTH-1:0] m0_address, // .address + output wire m0_write, // .write + output wire m0_read, // .read + output wire [BYTEEN_WIDTH-1:0] m0_byteenable, // .byteenable + input wire reset, // reset.reset + output wire s0_waitrequest, // s0.waitrequest + output wire [DATA_WIDTH-1:0] s0_readdata, // .readdata + output wire s0_readdatavalid, // .readdatavalid + input wire [BURSTCOUNT_WIDTH-1:0] s0_burstcount, // .burstcount + input wire [DATA_WIDTH-1:0] s0_writedata, // .writedata + input wire [ADDR_WIDTH-1:0] s0_address, // .address + input wire s0_write, // .write + input wire s0_read, // .read + input wire [BYTEEN_WIDTH-1:0] s0_byteenable // .byteenable + ); + +//----------------------------------------------------------------------------- +// ddr_avmm_bridge module instantiation +//----------------------------------------------------------------------------- + custom_altera_avalon_mm_bridge #( + .DATA_WIDTH (DATA_WIDTH), + .SYMBOL_WIDTH (SYMBOL_WIDTH), + .HDL_ADDR_WIDTH (ADDR_WIDTH), + .BURSTCOUNT_WIDTH (BURSTCOUNT_WIDTH), + .CMD_PIPE_DEPTH (1), + .READDATA_PIPE_DEPTH (READDATA_PIPE_DEPTH) + ) ddr_avmm_bridge ( + .clk (clk), // clk.clk + .reset (reset), // reset.reset + .s0_waitrequest (s0_waitrequest), // s0.waitrequest + .s0_readdata (s0_readdata), // .readdata + .s0_readdatavalid (s0_readdatavalid), // .readdatavalid + .s0_burstcount (s0_burstcount), // .burstcount + .s0_writedata (s0_writedata), // .writedata + .s0_address (s0_address), // .address + .s0_write (s0_write), // .write + .s0_read (s0_read), // .read + .s0_byteenable (s0_byteenable), // .byteenable + .s0_debugaccess (1'b0), // .debugaccess + .m0_waitrequest (m0_waitrequest), // m0.waitrequest + .m0_readdata (m0_readdata), // .readdata + .m0_readdatavalid (m0_readdatavalid), // .readdatavalid + .m0_burstcount (m0_burstcount), // .burstcount + .m0_writedata (m0_writedata), // .writedata + .m0_address (m0_address), // .address + .m0_write (m0_write), // .write + .m0_read (m0_read), // .read + .m0_byteenable (m0_byteenable), // .byteenable + .m0_debugaccess (), // .debugaccess + .s0_response (), // (terminated) + .m0_response (2'b00) // (terminated) + ); + +endmodule diff --git a/ipss/mem/emif_csr.sv b/ipss/mem/emif_csr.sv new file mode 100644 index 0000000..8e865c3 --- /dev/null +++ b/ipss/mem/emif_csr.sv @@ -0,0 +1,252 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// EMIF FME and Port CSR module +// +//----------------------------------------------------------------------------- + +import ofs_fim_emif_cfg_pkg::*; + +module emif_csr #( + parameter NUM_LOCAL_MEM_BANKS = 1, + parameter END_OF_LIST = 1'b0, + parameter NEXT_DFH_OFFSET = 24'h05_0000 +) +( + ofs_fim_emif_sideband_if.csr emif_csr_sigs [NUM_LOCAL_MEM_BANKS-1:0], + ofs_fim_axi_mmio_if.slave csr_if +); + +import ofs_fim_cfg_pkg::*; +import ofs_csr_pkg::*; + +//------------------------------------- +// Number of feature and register +//------------------------------------- +localparam MAX_CSR_REG_NUM = 512; // 4KB address space - 512 x 8B register +localparam CSR_ADDR_WIDTH = $clog2(MAX_CSR_REG_NUM) + 3; + +localparam CSR_NUM_REG = 3; +localparam CSR_REG_ADDR_WIDTH = $clog2(CSR_NUM_REG) + 3; + +localparam ADDR_WIDTH = ofs_fim_cfg_pkg::MMIO_ADDR_WIDTH; +localparam DATA_WIDTH = ofs_fim_cfg_pkg::MMIO_DATA_WIDTH; +localparam WSTRB_WIDTH = (DATA_WIDTH/8); + +//------------------------------------- +// Register address +//------------------------------------- +localparam EMIF_DFH = 5'h0; +localparam EMIF_STAT = 5'h8; +localparam EMIF_CTRL = 5'h10; + +//------------------------------------- +// Signals +//------------------------------------- +logic clk; +logic rst_n; + +logic [ADDR_WIDTH-1:0] csr_waddr; +logic [DATA_WIDTH-1:0] csr_wdata; +logic [WSTRB_WIDTH-1:0] csr_wstrb; +logic csr_write; +csr_access_type_t csr_write_type; + +logic [ADDR_WIDTH-1:0] csr_raddr; +logic csr_read; +logic csr_read_32b; +logic [DATA_WIDTH-1:0] csr_readdata; +logic csr_readdata_valid; + +//-------------------------------------------------------------- +assign clk = csr_if.clk; +assign rst_n = csr_if.rst_n; + +//--------------------------------- +// Map AXI write/read request to CSR write/read, +// and send the write/read response back +//--------------------------------- +ofs_fim_axi_csr_slave emif_csr_slave ( + .csr_if (csr_if), + + .csr_write (csr_write), + .csr_waddr (csr_waddr), + .csr_write_type (csr_write_type), + .csr_wdata (csr_wdata), + .csr_wstrb (csr_wstrb), + + .csr_read (csr_read), + .csr_raddr (csr_raddr), + .csr_read_32b (csr_read_32b), + .csr_readdata (csr_readdata), + .csr_readdata_valid (csr_readdata_valid) +); + +//--------------------------------- +// CSR Registers +//--------------------------------- +logic [NUM_LOCAL_MEM_BANKS-1:0] emif_clear_busy, emif_clear_busy_sync; +logic [NUM_LOCAL_MEM_BANKS-1:0] emif_cal_failure, emif_cal_failure_sync; +logic [NUM_LOCAL_MEM_BANKS-1:0] emif_cal_success, emif_cal_success_sync; + +ofs_csr_hw_state_t hw_state; +logic range_valid; +logic csr_read_reg; +logic [ADDR_WIDTH-1:0] csr_raddr_reg; +logic csr_read_32b_reg; + +logic [DATA_WIDTH-1:0] csr_reg [CSR_NUM_REG-1:0]; + +//------------------- +// CSR read interface +//------------------- +// Register read control signals to spare 1 clock cycle +// for address range checking +always_ff @(posedge clk) begin + csr_read_reg <= csr_read; + csr_raddr_reg <= csr_raddr; + csr_read_32b_reg <= csr_read_32b; + + if (~rst_n) begin + csr_read_reg <= 1'b0; + end +end + +// CSR address range check +always_ff @(posedge clk) begin + range_valid <= (csr_raddr[CSR_ADDR_WIDTH-1:3] < CSR_NUM_REG) ? 1'b1 : 1'b0; +end + +// CSR readdata +always_ff @(posedge clk) begin + csr_readdata <= '0; + + if (csr_read_reg && range_valid) begin + if (csr_read_32b_reg) begin + if (csr_raddr_reg[2]) begin + csr_readdata[63:32] <= csr_reg[csr_raddr_reg[CSR_REG_ADDR_WIDTH-1:3]][63:32]; + end else begin + csr_readdata[31:0] <= csr_reg[csr_raddr_reg[CSR_REG_ADDR_WIDTH-1:3]][31:0]; + end + end else begin + csr_readdata <= csr_reg[csr_raddr_reg[CSR_REG_ADDR_WIDTH-1:3]]; + end + end +end + +// CSR readatavalid +always_ff @(posedge clk) begin + csr_readdata_valid <= csr_read_reg; +end + +//------------------- +// CSR Definition +//------------------- +assign hw_state.reset_n = rst_n; +assign hw_state.pwr_good_n = rst_n; +assign hw_state.wr_data = csr_wdata; +assign hw_state.write_type = csr_write_type; + +always_ff @(posedge clk) begin + def_reg (EMIF_DFH, + {64{RO}}, + /* + [63:60]: Feature Type + [59:52]: Reserved + [51:48]: If AFU - AFU Minor Revision Number (else, reserved) + [47:41]: Reserved + [40 ]: EOL (End of DFH list) + [39:16]: Next DFH Byte Offset + [15:12]: If AfU, AFU Major version number (else feature #) + [11:0 ]: Feature ID + */ + {4'h3,8'h00,4'h0,7'h00,END_OF_LIST,NEXT_DFH_OFFSET,4'h0,12'h009}, + {4'h3,8'h00,4'h0,7'h00,END_OF_LIST,NEXT_DFH_OFFSET,4'h0,12'h009} + ); + + def_reg (EMIF_STAT, + /* + [63:20]: Reserved + [19:16] EMIF clearing busy + [15:12] Reserved + [11: 8] EMIF Calibration failure + [ 7: 4] Reserved + [ 3: 0] EMIF Calibration complete + */ + {{40{RsvdZ}},{4{RO}},{4{RsvdZ}},{4{RO}},{4{RsvdZ}},{4{RO}}}, + 64'h0000000000000000, + {40'h0, + {(8-NUM_LOCAL_MEM_BANKS){1'b0}}, emif_clear_busy_sync, + {(8-NUM_LOCAL_MEM_BANKS){1'b0}}, emif_cal_failure_sync, + {(8-NUM_LOCAL_MEM_BANKS){1'b0}}, emif_cal_success_sync} + ); + + def_reg (EMIF_CTRL, + {{60{RsvdZ}},{4{RW1C}}}, + 64'h000000000000000f, + 64'h000000000000000f + ); +end + +genvar ig; +generate + for (ig=0; ig AVMM pipeline bridge -> Clear FSM -> + // AVMM protocol checker -> DDR EMIF IP + // -------------------------------------------------- + + // ------------------ + // AVMM Pipeline Bridge + // ------------------ + ddr_avmm_bridge #( + .DATA_WIDTH(AVMM_DATA_WIDTH), + .SYMBOL_WIDTH(8), + .ADDR_WIDTH(AVMM_ADDR_WIDTH), + .BURSTCOUNT_WIDTH(AVMM_BURSTCOUNT_WIDTH) + ) ddr4_bridge ( + .clk (ddr4_avmm[b].clk), + .m0_waitrequest (ddr4_avmm_chkr[b].waitrequest), + .m0_readdata (ddr4_avmm_chkr[b].readdata), + .m0_readdatavalid (ddr4_avmm_chkr[b].readdatavalid), + .m0_burstcount (ddr4_avmm_chkr[b].burstcount), + .m0_writedata (ddr4_avmm_chkr[b].writedata), + .m0_address (ddr4_avmm_chkr[b].address), + .m0_write (ddr4_avmm_chkr[b].write), + .m0_read (ddr4_avmm_chkr[b].read), + .m0_byteenable (ddr4_avmm_chkr[b].byteenable), + .reset (ddr4_afu_reset[b]), + .s0_waitrequest (ddr4_avmm[b].waitrequest), + .s0_readdata (ddr4_avmm[b].readdata), + .s0_readdatavalid (ddr4_avmm[b].readdatavalid), + .s0_burstcount (ddr4_avmm[b].burstcount), + .s0_writedata (ddr4_avmm[b].writedata), + .s0_address (ddr4_avmm[b].address), + .s0_write (ddr4_pr_avmm_write[b]), + .s0_read (ddr4_pr_avmm_read[b]), + .s0_byteenable (ddr4_avmm[b].byteenable) + ); + +`ifdef ENABLE_DDR_AVMM_CHKR + // AVMM Protocol Checker + avmm_chkr #( + .ADDRESS_W(AVMM_ADDR_WIDTH), + .DATA_W(AVMM_DATA_WIDTH) + ) ddr4_avmm_chkr_inst ( + .ddr_clear_en (~clear_ext_mem_req_n[b]), + .ddr_clear_busy (ddr4_sideband_sigs[b].clear_busy), + + .afu_reset (ddr4_afu_reset[b]), + .emif_prt_error (ddr4_sideband_sigs[b].chkr_error), + + .avm_read (ddr4_avmm_emif[b].read), + .avm_write (ddr4_avmm_emif[b].write), + .avm_address (ddr4_avmm_emif[b].address), + .avm_waitrequest (~ddr4_avmm_emif[b].waitrequest), + .avm_byteenable (ddr4_avmm_emif[b].byteenable), + .avm_burstcount (ddr4_avmm_emif[b].burstcount), + .avm_writedata (ddr4_avmm_emif[b].writedata), + .avm_readdata (ddr4_avmm_emif[b].readdata), + .avm_readdatavalid (ddr4_avmm_emif[b].readdatavalid), + + .avs_read (ddr4_avmm_chkr[b].read), + .avs_write (ddr4_avmm_chkr[b].write), + .avs_address (ddr4_avmm_chkr[b].address), + .avs_waitrequest (ddr4_avmm_chkr[b].waitrequest), + .avs_byteenable (ddr4_avmm_chkr[b].byteenable), + .avs_burstcount (ddr4_avmm_chkr[b].burstcount), + .avs_writedata (ddr4_avmm_chkr[b].writedata), + .avs_readdata (ddr4_avmm_chkr[b].readdata), + .avs_readdatavalid (ddr4_avmm_chkr[b].readdatavalid), + + .clk (ddr4_avmm[b].clk), + .rst_n (ddr4_rst_n_sync[b]) + ); +`else + // Bypass AVMM protocol checker + // Tie-off + assign ddr4_sideband_sigs[b].chkr_error = 1'b0; + assign ddr4_sideband_sigs[b].clear_busy = 1'b0; + + // Invert ddr4_avmm_emif[b].waitrequest because it is connected to ready signal on EMIF IP + // which is the invert of waitrequest, i.e. waitrequest=1 when ready=0 and vice versa + assign ddr4_avmm_chkr[b].waitrequest = ~ddr4_avmm_emif[b].waitrequest; + + assign ddr4_avmm_chkr[b].readdata = ddr4_avmm_emif[b].readdata; + assign ddr4_avmm_chkr[b].readdatavalid = ddr4_avmm_emif[b].readdatavalid; + assign ddr4_avmm_emif[b].read = ddr4_avmm_chkr[b].read; + assign ddr4_avmm_emif[b].write = ddr4_avmm_chkr[b].write; + assign ddr4_avmm_emif[b].address = ddr4_avmm_chkr[b].address; + assign ddr4_avmm_emif[b].byteenable = ddr4_avmm_chkr[b].byteenable; + assign ddr4_avmm_emif[b].burstcount = ddr4_avmm_chkr[b].burstcount; + assign ddr4_avmm_emif[b].writedata = ddr4_avmm_chkr[b].writedata; +`endif + + // ------------------ + // DDR4 EMIF IP + // ------------------ + assign ddr4_avmm[b].ecc_interrupt = 'b0; + emif_ddr4_no_ecc emif_ddr4_inst ( + .amm_ready_0 (ddr4_avmm_emif[b].waitrequest), + .amm_read_0 (ddr4_avmm_emif[b].read), + .amm_write_0 (ddr4_avmm_emif[b].write), + .amm_address_0 (ddr4_avmm_emif[b].address), + .amm_readdata_0 (ddr4_avmm_emif[b].readdata), + .amm_writedata_0 (ddr4_avmm_emif[b].writedata), + .amm_burstcount_0 (ddr4_avmm_emif[b].burstcount), + .amm_byteenable_0 (ddr4_avmm_emif[b].byteenable), + .amm_readdatavalid_0 (ddr4_avmm_emif[b].readdatavalid), + .emif_usr_clk (ddr4_avmm[b].clk), + .emif_usr_reset_n (ddr4_avmm[b].rst_n), + .local_reset_req (~emif_rst_n_q[b]), + .local_reset_done (ddr4_sideband_sigs[b].local_reset_done), + .mem_ck (ddr4_mem[b].ck), + .mem_ck_n (ddr4_mem[b].ck_n), + .mem_a (ddr4_mem[b].a), + .mem_act_n (ddr4_mem[b].act_n), + .mem_ba (ddr4_mem[b].ba), + .mem_bg (ddr4_mem[b].bg), + .mem_cke (ddr4_mem[b].cke), + .mem_cs_n (ddr4_mem[b].cs_n), + .mem_odt (ddr4_mem[b].odt), + .mem_reset_n (ddr4_mem[b].reset_n), + .mem_par (ddr4_mem[b].par), + .mem_alert_n (ddr4_mem[b].alert_n), + .mem_dqs (ddr4_mem[b].dqs), + .mem_dqs_n (ddr4_mem[b].dqs_n), + .mem_dq (ddr4_mem[b].dq), + .mem_dbi_n (ddr4_mem[b].dbi_n), + .oct_rzqin (ddr4_mem[b].oct_rzqin), + .pll_locked (ddr4_sideband_sigs[b].pll_locked), + .pll_ref_clk (ddr4_mem[b].ref_clk), + .pll_ref_clk_out (), + .local_cal_success (ddr4_sideband_sigs[b].cal_success), + .local_cal_fail (ddr4_sideband_sigs[b].cal_failure) + ); + + end : mem_bank + +endgenerate + +endmodule : emif_top diff --git a/ipss/mem/includes/ofs_fim_emif_afu_if.sv b/ipss/mem/includes/ofs_fim_emif_afu_if.sv new file mode 100755 index 0000000..eeb9ef8 --- /dev/null +++ b/ipss/mem/includes/ofs_fim_emif_afu_if.sv @@ -0,0 +1,148 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Definition of AFU Memory Mapped Interfaces to EMIF +// +//----------------------------------------------------------------------------- + +`ifndef __OFS_FIM_EMIF_AFU_IF_SV__ +`define __OFS_FIM_EMIF_AFU_IF_SV__ + +// EMIF AVMM interface +interface ofs_fim_emif_afu_avmm_if #( + parameter ADDR_WIDTH = 27, + parameter DATA_WIDTH = 576, + parameter BURSTCOUNT_WIDTH = 7, + parameter BYTEENABLE_WIDTH = 72 +); + //--------------------------- + // Memory clock and reset + //--------------------------- + logic mem_clk; + logic mem_rst_n; + + //--------------------------- + // AVMM interface signals + //--------------------------- + logic waitrequest; + logic readdatavalid; + logic [DATA_WIDTH-1:0] readdata; + + logic [ADDR_WIDTH-1:0] address; + logic write; + logic read; + logic [BURSTCOUNT_WIDTH-1:0] burstcount; + logic [DATA_WIDTH-1:0] writedata; + logic [BYTEENABLE_WIDTH-1:0] byteenable; + + modport slave ( + input read, write, writedata, address, burstcount, + byteenable, + output readdata, readdatavalid, waitrequest, mem_clk, mem_rst_n + ); + + modport master ( + output read, write, writedata, address, burstcount, + byteenable, + input readdata, readdatavalid, waitrequest, mem_clk, mem_rst_n + ); +endinterface : ofs_fim_emif_afu_avmm_if + +// EMIF AXI interface +interface ofs_fim_emif_afu_axi_if #( + parameter AWID_WIDTH = 6, + parameter AWADDR_WIDTH = 34, + parameter WDATA_WIDTH = 1024, + parameter ARID_WIDTH = 6, + parameter ARADDR_WIDTH = 34, + parameter RDATA_WIDTH = 1024 +); + + //--------------------------- + // Memory clock and reset + //--------------------------- + logic mem_clk; + logic mem_rst_n; + + //--------------------------- + // AXI interface signals + //--------------------------- + logic clk; + logic rst_n; + + // Write address channel + logic awready; + logic awvalid; + logic [AWID_WIDTH-1:0] awid; + logic [AWADDR_WIDTH-1:0] awaddr; + logic [7:0] awlen; + logic [2:0] awsize; + logic [1:0] awburst; + logic [2:0] awprot; + + // Write data channel + logic wready; + logic wvalid; + logic [WDATA_WIDTH-1:0] wdata; + logic [(WDATA_WIDTH/8-1):0] wstrb; + logic wlast; + + // Write response channel + logic bready; + logic bvalid; + logic [AWID_WIDTH-1:0] bid; + logic [1:0] bresp; + + // Read address channel + logic arready; + logic arvalid; + logic [ARID_WIDTH-1:0] arid; + logic [ARADDR_WIDTH-1:0] araddr; + logic [7:0] arlen; + logic [2:0] arsize; + logic [1:0] arburst; + logic [2:0] arprot; + + // Read response channel + logic rready; + logic rvalid; + logic [ARID_WIDTH-1:0] rid; + logic [RDATA_WIDTH-1:0] rdata; + logic [1:0] rresp; + logic rlast; + + modport master ( + input mem_clk, mem_rst_n, + awready, wready, + bvalid, bid, bresp, + arready, + rvalid, rid, rdata, rresp, rlast, + + output clk, rst_n, + awvalid, awid, awaddr, awlen, awsize, awburst, awprot, + wvalid, wdata, wstrb, wlast, + bready, + arvalid, arid, araddr, arlen, arsize, arburst, arprot, + rready + ); + + modport slave ( + output mem_clk, mem_rst_n, + awready, wready, + bvalid, bid, bresp, + arready, + rvalid, rid, rdata, rresp, rlast, + + input clk, rst_n, + awvalid, awid, awaddr, awlen, awsize, awburst, awprot, + wvalid, wdata, wstrb, wlast, + bready, + arvalid, arid, araddr, arlen, arsize, arburst, arprot, + rready + ); + +endinterface : ofs_fim_emif_afu_axi_if +`endif // __OFS_FIM_EMIF_AFU_IF_SV__ diff --git a/ipss/mem/includes/ofs_fim_emif_cfg_pkg.sv b/ipss/mem/includes/ofs_fim_emif_cfg_pkg.sv new file mode 100755 index 0000000..1779c6b --- /dev/null +++ b/ipss/mem/includes/ofs_fim_emif_cfg_pkg.sv @@ -0,0 +1,40 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// This file contains SystemVerilog package definitions for EMIF related +// parameters and types +// +//---------------------------------------------------------------------------- + +`ifndef __OFS_FIM_EMIF_CFG_PKG_SV__ +`define __OFS_FIM_EMIF_CFG_PKG_SV__ + +`include "fpga_defines.vh" + +package ofs_fim_emif_cfg_pkg; + + // Width of the "real" data bus (without ECC) + localparam AVMM_DATA_BASE_WIDTH = 512; + + // Width of extra ECC memory + localparam AVMM_ECC_WIDTH = 64; + + // Full data bus, including ECC + localparam AVMM_DATA_WIDTH = AVMM_DATA_BASE_WIDTH + AVMM_ECC_WIDTH; + localparam AVMM_BYTEENABLE_WIDTH = (AVMM_DATA_WIDTH / 8); + localparam AVMM_ADDR_WIDTH = 27; + localparam AVMM_BURSTCOUNT_WIDTH = 7; + + localparam MEM_ADDR_WIDTH = 17; + localparam MEM_BA_WIDTH = 2; + localparam MEM_BG_WIDTH = 2; + localparam MEM_DQS_WIDTH = 9; + localparam MEM_DQ_WIDTH = 72; + localparam MEM_DBI_WIDTH = 9; + +endpackage : ofs_fim_emif_cfg_pkg + +`endif // __OFS_FIM_EMIF_CFG_PKG_SV__ diff --git a/ipss/mem/includes/ofs_fim_emif_if.sv b/ipss/mem/includes/ofs_fim_emif_if.sv new file mode 100755 index 0000000..537b57c --- /dev/null +++ b/ipss/mem/includes/ofs_fim_emif_if.sv @@ -0,0 +1,105 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// This file contains SystemVerilog interface definitions defining +// EMIF/DDR4 related interfaces +// +//---------------------------------------------------------------------------- + +`ifndef __OFS_FIM_EMIF_IF_SV__ +`define __OFS_FIM_EMIF_IF_SV__ + +import ofs_fim_emif_cfg_pkg::*; + +// Interface between the EMIF IP and the user-logic/GBS. Includes an +// AVMM bus, EMIF source clock, reset, and ECC interrupt flag. +interface ofs_fim_emif_avmm_if #( + parameter ADDR_WIDTH = ofs_fim_emif_cfg_pkg::AVMM_ADDR_WIDTH, + parameter DATA_WIDTH = ofs_fim_emif_cfg_pkg::AVMM_DATA_WIDTH, + parameter BURSTCOUNT_WIDTH = ofs_fim_emif_cfg_pkg::AVMM_BURSTCOUNT_WIDTH, + parameter BYTEENABLE_WIDTH = ofs_fim_emif_cfg_pkg::AVMM_BYTEENABLE_WIDTH +); + logic clk; + logic rst_n; + logic ecc_interrupt; + + logic waitrequest; + logic [DATA_WIDTH-1:0] readdata; + logic readdatavalid; + + logic [BURSTCOUNT_WIDTH-1:0] burstcount; + logic [DATA_WIDTH-1:0] writedata; + logic [ADDR_WIDTH-1:0] address; + logic write; + logic read; + logic [BYTEENABLE_WIDTH-1:0] byteenable; + + modport emif ( + input read, write, writedata, address, burstcount, + byteenable, + output readdata, readdatavalid, waitrequest, clk, rst_n, ecc_interrupt + ); + modport user ( + output read, write, writedata, address, burstcount, + byteenable, + input readdata, readdatavalid, waitrequest, clk, rst_n, ecc_interrupt + ); +endinterface : ofs_fim_emif_avmm_if + +//Status and control signals between BBS/FME/CHKR and the EMIF IP. +interface ofs_fim_emif_sideband_if(); + logic pll_locked; + logic local_reset_done; + logic cal_success; + logic cal_failure; + logic clear_busy; + logic chkr_clear_n; + logic chkr_error; + + modport csr ( + output chkr_clear_n, + input local_reset_done, pll_locked, + cal_failure, cal_success, clear_busy, chkr_error + ); +endinterface : ofs_fim_emif_sideband_if + +//Interface defining the signals between the EMIF IP and external memory. +interface ofs_fim_emif_mem_if #( + parameter ADDR_WIDTH = ofs_fim_emif_cfg_pkg::MEM_ADDR_WIDTH, + parameter BA_WIDTH = ofs_fim_emif_cfg_pkg::MEM_BA_WIDTH, + parameter BG_WIDTH = ofs_fim_emif_cfg_pkg::MEM_BG_WIDTH, + parameter DQS_WIDTH = ofs_fim_emif_cfg_pkg::MEM_DQS_WIDTH, + parameter DQ_WIDTH = ofs_fim_emif_cfg_pkg::MEM_DQ_WIDTH, + parameter DBI_WIDTH = ofs_fim_emif_cfg_pkg::MEM_DBI_WIDTH +); + logic ck; + logic ck_n; + logic [ADDR_WIDTH-1:0] a; + logic act_n; + logic [BA_WIDTH-1:0] ba; + logic [BG_WIDTH-1:0] bg; + logic cke; + logic cs_n; + logic odt; + logic reset_n; + logic par; + logic alert_n; + wire [DQS_WIDTH-1:0] dqs; + wire [DQS_WIDTH-1:0] dqs_n; + wire [DQ_WIDTH-1:0] dq; + wire [DBI_WIDTH-1:0] dbi_n; + logic oct_rzqin; + logic ref_clk; + + modport emif ( + input alert_n, oct_rzqin, ref_clk, + output ck, ck_n, cke, reset_n, + a, act_n, ba, bg, cs_n, odt, par, + inout dqs, dqs_n, dq, dbi_n + ); +endinterface : ofs_fim_emif_mem_if + +`endif // __OFS_FIM_EMIF_IF_SV__ diff --git a/ipss/mem/ip/avmm_cdc.ip b/ipss/mem/ip/avmm_cdc.ip new file mode 100644 index 0000000..bde650d --- /dev/null +++ b/ipss/mem/ip/avmm_cdc.ip @@ -0,0 +1,1972 @@ + + + + Intel Corporation + avmm_cdc + avmm_cdc + 19.2.1 + + + m0_clk + + + + + + + + clk + + + m0_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + m0_reset + + + + + + + + reset + + + m0_reset + + + + + + + + + associatedClock + Associated clock + m0_clk + + + synchronousEdges + Synchronous edges + BOTH + + + + + s0_clk + + + + + + + + clk + + + s0_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + s0_reset + + + + + + + + reset + + + s0_reset + + + + + + + + + associatedClock + Associated clock + s0_clk + + + synchronousEdges + Synchronous edges + BOTH + + + + + s0 + + + + + + + + waitrequest + + + s0_waitrequest + + + + + readdata + + + s0_readdata + + + + + readdatavalid + + + s0_readdatavalid + + + + + burstcount + + + s0_burstcount + + + + + writedata + + + s0_writedata + + + + + address + + + s0_address + + + + + write + + + s0_write + + + + + read + + + s0_read + + + + + byteenable + + + s0_byteenable + + + + + debugaccess + + + s0_debugaccess + + + + + + + + + addressAlignment + Agent addressing + DYNAMIC + + + addressGroup + Address group + 0 + + + addressSpan + Address span + 134217728 + + + addressUnits + Address units + SYMBOLS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + s0_clk + + + associatedReset + Associated reset + s0_reset + + + bitsPerSymbol + Bits per symbol + 8 + + + bridgedAddressOffset + Bridged Address Offset + 0 + + + bridgesToMaster + Bridges to host + avmm_cdc.m0 + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + explicitAddressSpan + Explicit address span + 0 + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isBigEndian + Big endian + false + + + isFlash + Flash memory + false + + + isMemoryDevice + Memory device + false + + + isNonVolatileStorage + Non-volatile storage + false + + + linewrapBursts + Linewrap bursts + false + + + maximumPendingReadTransactions + Maximum pending read transactions + 128 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + minimumUninterruptedRunLength + Minimum uninterrupted run length + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + printableDevice + Can receive stdout/stderr + false + + + readLatency + Read latency + 0 + + + readWaitStates + Read wait states + 0 + + + readWaitTime + Read wait + 0 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + transparentBridge + Transparent bridge + false + + + waitrequestAllowance + Waitrequest allowance + 0 + + + wellBehavedWaitrequest + Well-behaved waitrequest + false + + + writeLatency + Write latency + 0 + + + writeWaitStates + Write wait states + 0 + + + writeWaitTime + Write wait + 0 + + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + + + + + m0 + + + + + + + + waitrequest + + + m0_waitrequest + + + + + readdata + + + m0_readdata + + + + + readdatavalid + + + m0_readdatavalid + + + + + burstcount + + + m0_burstcount + + + + + writedata + + + m0_writedata + + + + + address + + + m0_address + + + + + write + + + m0_write + + + + + read + + + m0_read + + + + + byteenable + + + m0_byteenable + + + + + debugaccess + + + m0_debugaccess + + + + + + + + + adaptsTo + Adapts to + + + + addressGroup + Address group + 0 + + + addressUnits + Address units + SYMBOLS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + m0_clk + + + associatedReset + Associated reset + m0_reset + + + bitsPerSymbol + Bits per symbol + 8 + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + dBSBigEndian + dBS big endian + false + + + doStreamReads + Use flow control for read transfers + false + + + doStreamWrites + Use flow control for write transfers + false + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isAsynchronous + Is asynchronous + false + + + isBigEndian + Is big endian + false + + + isReadable + Is readable + false + + + isWriteable + Is writeable + false + + + linewrapBursts + Linewrap bursts + false + + + maxAddressWidth + Maximum address width + 32 + + + maximumPendingReadTransactions + Maximum pending read transactions + 0 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + readLatency + Read latency + 0 + + + readWaitTime + Read wait + 1 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + waitrequestAllowance + Waitrequest allowance + 0 + + + writeWaitTime + Write wait + 0 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + mm_ccb + + QUARTUS_SYNTH + + + + + + m0_clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_reset + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_reset + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_waitrequest + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_readdata + + out + + + 0 + 575 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_readdatavalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_burstcount + + in + + + 0 + 3 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_writedata + + in + + + 0 + 575 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_address + + in + + + 0 + 26 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_write + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_read + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_byteenable + + in + + + 0 + 71 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_debugaccess + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_waitrequest + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_readdata + + in + + + 0 + 575 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m0_readdatavalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_burstcount + + out + + + 0 + 3 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m0_writedata + + out + + + 0 + 575 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m0_address + + out + + + 0 + 26 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m0_write + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_read + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_byteenable + + out + + + 0 + 71 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m0_debugaccess + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + avmm_cdc + mm_ccb + 19.2.1 + + + + + DATA_WIDTH + Data width + 576 + + + SYMBOL_WIDTH + Symbol width + 8 + + + ADDRESS_WIDTH + Address width + 27 + + + SYSINFO_ADDR_WIDTH + SYSINFO_ADDR_WIDTH + 10 + + + USE_AUTO_ADDRESS_WIDTH + Use automatically-determined address width + 0 + + + ADDRESS_UNITS + Address units + SYMBOLS + + + MAX_BURST_SIZE + Maximum burst size (words) + 8 + + + COMMAND_FIFO_DEPTH + Command FIFO depth + 32 + + + RESPONSE_FIFO_DEPTH + Response FIFO depth + 128 + + + MASTER_SYNC_DEPTH + Master clock domain synchronizer depth + 2 + + + SLAVE_SYNC_DEPTH + Slave clock domain synchronizer depth + 2 + + + SYNC_RESET + Use synchronous resets + 1 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element avmm_cdc + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>m0_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>m0_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>m0_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>m0_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>m0_clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>s0_clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>576</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_readdatavalid</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_burstcount</name> + <role>burstcount</role> + <direction>Input</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>576</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_address</name> + <role>address</role> + <direction>Input</direction> + <width>27</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>72</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_debugaccess</name> + <role>debugaccess</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>134217728</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>s0_clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>s0_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + <value>avmm_cdc.m0</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>128</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>m0</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>m0_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>576</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_burstcount</name> + <role>burstcount</role> + <direction>Output</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>576</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_address</name> + <role>address</role> + <direction>Output</direction> + <width>27</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_byteenable</name> + <role>byteenable</role> + <direction>Output</direction> + <width>72</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_debugaccess</name> + <role>debugaccess</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>m0_clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>m0_reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>m0</key> + <value> + <connectionPointName>m0</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_WIDTH</key> + <value>10</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>s0</key> + <value> + <connectionPointName>s0</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/ipss/mem/ip/avmm_pipeline_bridge.ip b/ipss/mem/ip/avmm_pipeline_bridge.ip new file mode 100644 index 0000000..845e9a7 --- /dev/null +++ b/ipss/mem/ip/avmm_pipeline_bridge.ip @@ -0,0 +1,1823 @@ + + + + Intel Corporation + avmm_pipeline_bridge + avmm_pipeline_bridge + 20.0.1 + + + clk + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset + + + reset + + + + + + + + + associatedClock + Associated clock + clk + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + s0 + + + + + + + + waitrequest + + + s0_waitrequest + + + + + readdata + + + s0_readdata + + + + + readdatavalid + + + s0_readdatavalid + + + + + burstcount + + + s0_burstcount + + + + + writedata + + + s0_writedata + + + + + address + + + s0_address + + + + + write + + + s0_write + + + + + read + + + s0_read + + + + + byteenable + + + s0_byteenable + + + + + debugaccess + + + s0_debugaccess + + + + + + + + + addressAlignment + Agent addressing + DYNAMIC + + + addressGroup + Address group + 0 + + + addressSpan + Address span + 134217728 + + + addressUnits + Address units + SYMBOLS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + clk + + + associatedReset + Associated reset + reset + + + bitsPerSymbol + Bits per symbol + 8 + + + bridgedAddressOffset + Bridged Address Offset + 0 + + + bridgesToMaster + Bridges to host + avmm_pipeline_bridge.m0 + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + explicitAddressSpan + Explicit address span + 0 + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isBigEndian + Big endian + false + + + isFlash + Flash memory + false + + + isMemoryDevice + Memory device + false + + + isNonVolatileStorage + Non-volatile storage + false + + + linewrapBursts + Linewrap bursts + false + + + maximumPendingReadTransactions + Maximum pending read transactions + 4 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + minimumUninterruptedRunLength + Minimum uninterrupted run length + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + printableDevice + Can receive stdout/stderr + false + + + readLatency + Read latency + 0 + + + readWaitStates + Read wait states + 0 + + + readWaitTime + Read wait + 0 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + transparentBridge + Transparent bridge + false + + + waitrequestAllowance + Waitrequest allowance + 0 + + + wellBehavedWaitrequest + Well-behaved waitrequest + false + + + writeLatency + Write latency + 0 + + + writeWaitStates + Write wait states + 0 + + + writeWaitTime + Write wait + 0 + + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + + + + + m0 + + + + + + + + waitrequest + + + m0_waitrequest + + + + + readdata + + + m0_readdata + + + + + readdatavalid + + + m0_readdatavalid + + + + + burstcount + + + m0_burstcount + + + + + writedata + + + m0_writedata + + + + + address + + + m0_address + + + + + write + + + m0_write + + + + + read + + + m0_read + + + + + byteenable + + + m0_byteenable + + + + + debugaccess + + + m0_debugaccess + + + + + + + + + adaptsTo + Adapts to + + + + addressGroup + Address group + 0 + + + addressUnits + Address units + SYMBOLS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + clk + + + associatedReset + Associated reset + reset + + + bitsPerSymbol + Bits per symbol + 8 + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + dBSBigEndian + dBS big endian + false + + + doStreamReads + Use flow control for read transfers + false + + + doStreamWrites + Use flow control for write transfers + false + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isAsynchronous + Is asynchronous + false + + + isBigEndian + Is big endian + false + + + isReadable + Is readable + false + + + isWriteable + Is writeable + false + + + linewrapBursts + Linewrap bursts + false + + + maxAddressWidth + Maximum address width + 32 + + + maximumPendingReadTransactions + Maximum pending read transactions + 0 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + readLatency + Read latency + 0 + + + readWaitTime + Read wait + 1 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + waitrequestAllowance + Waitrequest allowance + 0 + + + writeWaitTime + Write wait + 0 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_avalon_mm_bridge + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + reset + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_waitrequest + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_readdata + + out + + + 0 + 575 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_readdatavalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_burstcount + + in + + + 0 + 6 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_writedata + + in + + + 0 + 575 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_address + + in + + + 0 + 26 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_write + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_read + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s0_byteenable + + in + + + 0 + 71 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s0_debugaccess + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_waitrequest + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_readdata + + in + + + 0 + 575 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m0_readdatavalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m0_burstcount + + out + + + 0 + 6 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m0_writedata + + out + + + 0 + 575 + + + + + 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Line wrap bursts + 0 + + + PIPELINE_COMMAND + Pipeline command signals + 1 + + + PIPELINE_RESPONSE + Pipeline response signals + 1 + + + USE_RESPONSE + Use Avalon Transaction Responses + 0 + + + SYNC_RESET + Use synchronous resets + 0 + + + USE_WRITERESPONSE + Use Writeresponsevalid + 0 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element avmm_pipeline_bridge + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>s0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>s0_waitrequest</name> + <role>waitrequest</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_readdata</name> + <role>readdata</role> + <direction>Output</direction> + <width>576</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_readdatavalid</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_burstcount</name> + <role>burstcount</role> + <direction>Input</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_writedata</name> + <role>writedata</role> + <direction>Input</direction> + <width>576</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_address</name> + <role>address</role> + <direction>Input</direction> + <width>27</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_write</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_read</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_byteenable</name> + <role>byteenable</role> + <direction>Input</direction> + <width>72</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s0_debugaccess</name> + <role>debugaccess</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>134217728</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + <value>avmm_pipeline_bridge.m0</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>4</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>0</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>m0</name> + <type>avalon</type> + <isStart>true</isStart> + <ports> + <port> + <name>m0_waitrequest</name> + <role>waitrequest</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_readdata</name> + <role>readdata</role> + <direction>Input</direction> + <width>576</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_readdatavalid</name> + <role>readdatavalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_burstcount</name> + <role>burstcount</role> + <direction>Output</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_writedata</name> + <role>writedata</role> + <direction>Output</direction> + <width>576</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_address</name> + <role>address</role> + <direction>Output</direction> + <width>27</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_write</name> + <role>write</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_read</name> + <role>read</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_byteenable</name> + <role>byteenable</role> + <direction>Output</direction> + <width>72</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m0_debugaccess</name> + <role>debugaccess</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>adaptsTo</key> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressUnits</key> + <value>SYMBOLS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>dBSBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>doStreamReads</key> + <value>false</value> + </entry> + <entry> + <key>doStreamWrites</key> + <value>false</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isAsynchronous</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isReadable</key> + <value>false</value> + </entry> + <entry> + <key>isWriteable</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maxAddressWidth</key> + <value>32</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>m0</key> + <value> + <connectionPointName>m0</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_WIDTH</key> + <value>10</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>s0</key> + <value> + <connectionPointName>s0</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/ipss/mem/ip/emif_ddr4_no_ecc.ip b/ipss/mem/ip/emif_ddr4_no_ecc.ip new file mode 100755 index 0000000..6bfd9e9 --- /dev/null +++ b/ipss/mem/ip/emif_ddr4_no_ecc.ip @@ -0,0 +1,10224 @@ + + + + Intel Corporation + emif_ddr4_no_ecc + emif_s10_0 + 19.2.6 + + + local_reset_req + + + + + + + + local_reset_req + + + local_reset_req + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + local_reset_status + + + + + + + + local_reset_done + + + local_reset_done + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + pll_ref_clk + + + + + + + + clk + + + pll_ref_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + pll_ref_clk_out + + + + + + + + clk + + + pll_ref_clk_out + + + + + + + + + associatedDirectClock + Associated direct clock + + + + clockRate + Clock rate + 0 + + + clockRateKnown + Clock rate known + false + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + pll_locked + + + + + + + + pll_locked + + + pll_locked + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + oct + + + + + + + + oct_rzqin + + + oct_rzqin + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + mem + + + + + + + + mem_ck + + + mem_ck + + + + + mem_ck_n + + + mem_ck_n + + + + + mem_a + + + mem_a + + + + + mem_act_n + + + mem_act_n + + + + + mem_ba + + + mem_ba + + + + + mem_bg + + + mem_bg + + + + + mem_cke + + + mem_cke + + + + + mem_cs_n + + + mem_cs_n + + + + + mem_odt + + + mem_odt + + + + + mem_reset_n + + + mem_reset_n + + + + + mem_par + + + mem_par + + + + + mem_alert_n + + + mem_alert_n + + + + + mem_dqs + + + mem_dqs + + + + + mem_dqs_n + + + mem_dqs_n + + + + + mem_dq + + + mem_dq + + + + + mem_dbi_n + + + mem_dbi_n + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + status + + + + + + + + local_cal_success + + + local_cal_success + + + + + local_cal_fail + + + local_cal_fail + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + emif_usr_reset_n + + + + + + + + reset_n + + + emif_usr_reset_n + + + + + + + + + associatedClock + Associated clock + + + + associatedDirectReset + Associated direct reset + + + + associatedResetSinks + Associated reset sinks + none + + + synchronousEdges + Synchronous edges + NONE + + + + + emif_usr_clk + + + + + + + + clk + + + emif_usr_clk + + + + + + + + + associatedDirectClock + Associated direct clock + + + + clockRate + Clock rate + 300000000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + ctrl_amm_0 + + + + + + + + waitrequest_n + + + amm_ready_0 + + + + + read + + + amm_read_0 + + + + + write + + + amm_write_0 + + + + + address + + + amm_address_0 + + + + + readdata + + + amm_readdata_0 + + + + + writedata + + + amm_writedata_0 + + + + + burstcount + + + amm_burstcount_0 + + + + + byteenable + + + amm_byteenable_0 + + + + + readdatavalid + + + amm_readdatavalid_0 + + + + + + + + + addressAlignment + Agent addressing + DYNAMIC + + + addressGroup + Address group + 0 + + + addressSpan + Address span + 9663676416 + + + addressUnits + Address units + WORDS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + emif_usr_clk + + + associatedReset + Associated reset + emif_usr_reset_n + + + bitsPerSymbol + Bits per symbol + 8 + + + bridgedAddressOffset + Bridged Address Offset + 0 + + + bridgesToMaster + Bridges to host + + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + explicitAddressSpan + Explicit address span + 0 + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isBigEndian + Big endian + false + + + isFlash + Flash memory + false + + + isMemoryDevice + Memory device + true + + + isNonVolatileStorage + Non-volatile storage + false + + + linewrapBursts + Linewrap bursts + false + + + maximumPendingReadTransactions + Maximum pending read transactions + 64 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + minimumUninterruptedRunLength + Minimum uninterrupted run length + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + printableDevice + Can receive stdout/stderr + false + + + readLatency + Read latency + 0 + + + readWaitStates + Read wait states + 1 + + + readWaitTime + Read wait + 1 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + transparentBridge + Transparent bridge + false + + + waitrequestAllowance + Waitrequest allowance + 0 + + + wellBehavedWaitrequest + Well-behaved waitrequest + false + + + writeLatency + Write latency + 0 + + + writeWaitStates + Write wait states + 0 + + + writeWaitTime + Write wait + 0 + + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_emif_s10 + + QUARTUS_SYNTH + + + + + + local_reset_req + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + local_reset_done + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + pll_ref_clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + pll_ref_clk_out + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + pll_locked + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + oct_rzqin + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + mem_ck + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_ck_n + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_a + + out + + + 0 + 16 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_act_n + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_ba + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_bg + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_cke + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_cs_n + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_odt + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_reset_n + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_par + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_alert_n + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_dqs + + inout + + + 0 + 8 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_dqs_n + + inout + + + 0 + 8 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_dq + + inout + + + 0 + 71 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_dbi_n + + inout + + + 0 + 8 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + local_cal_success + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + local_cal_fail + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + emif_usr_reset_n + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + emif_usr_clk + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + amm_ready_0 + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + amm_read_0 + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + amm_write_0 + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + amm_address_0 + + in + + + 0 + 26 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + amm_readdata_0 + + out + + + 0 + 575 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + amm_writedata_0 + + in + + + 0 + 575 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + amm_burstcount_0 + + in + + + 0 + 6 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + amm_byteenable_0 + + in + + + 0 + 71 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + amm_readdatavalid_0 + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + emif_ddr4_no_ecc + altera_emif_s10 + 19.2.6 + + + + + SYS_INFO_DEVICE_FAMILY + PARAM_SYS_INFO_DEVICE_FAMILY_NAME + Stratix 10 + + + SYS_INFO_DEVICE + PARAM_SYS_INFO_DEVICE_NAME + 1SX280HN2F43E2VG + + + SYS_INFO_DEVICE_SPEEDGRADE + PARAM_SYS_INFO_DEVICE_SPEEDGRADE_NAME + 2 + + + SYS_INFO_DEVICE_TEMPERATURE_GRADE + PARAM_SYS_INFO_DEVICE_TEMPERATURE_GRADE_NAME + EXTENDED + + + SYS_INFO_DEVICE_POWER_MODEL + PARAM_SYS_INFO_DEVICE_POWER_MODEL_NAME + SMART_VID + + + SYS_INFO_DEVICE_DIE_REVISIONS + PARAM_SYS_INFO_DEVICE_DIE_REVISIONS_NAME + HSSI_CRETE2E_REVB,MAIN_ND5_REVC + + + TRAIT_SUPPORTS_VID + PARAM_TRAIT_SUPPORTS_VID_NAME + 1 + + + TRAIT_IOBANK_REVISION + PARAM_TRAIT_IOBANK_REVISION_NAME + + + + PROTOCOL_ENUM + Protocol + PROTOCOL_DDR4 + + + IS_ED_SLAVE + PARAM_IS_ED_SLAVE_NAME + false + + + INTERNAL_TESTING_MODE + PARAM_INTERNAL_TESTING_MODE_NAME + false + + + CAL_DEBUG_CLOCK_FREQUENCY + PARAM_CAL_DEBUG_CLOCK_FREQUENCY_NAME + 50000000 + + + SYS_INFO_UNIQUE_ID + PARAM_SYS_INFO_UNIQUE_ID_NAME + emif_ddr4_no_ecc_emif_s10_0 + + + PLL_ADD_EXTRA_CLKS + Specify additional core clocks based on existing PLL + false + + + PLL_USER_NUM_OF_EXTRA_CLKS + Number of additional core clocks + 0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_0 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_0 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_0 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_0_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_0 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_0_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_0 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_0_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_0 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_0_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_0 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_0_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_0 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_0_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_1 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_1 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_1 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_1_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_1 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_1_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_1 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_1_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_1 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_1_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_1 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_1_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_1 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_1_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_2 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_2 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_2 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_2_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_2 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_2_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_2 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_2_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_2 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_2_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_2 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_2_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_2 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_2_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_3 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_3 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_3 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_3_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_3 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_3_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_3 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_3_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_3 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_3_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_3 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_3_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_3 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_3_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_4 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_4 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_4 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_4_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_4 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_4_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_4 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_4_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_4 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_4_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_4 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_4_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_4 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_4_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_5 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_5_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_6 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_6_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_7 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_7_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8 + Frequency + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8 + Phase shift + 0.0 + + + PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8 + PARAM_PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8_NAME + 0.0 + + + PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8 + PARAM_PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8_NAME + ps + + + PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8 + PARAM_PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8_NAME + 0.0 + + + PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8 + PARAM_PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8_NAME + 0.0 + + + PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8 + PARAM_PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8_NAME + 50.0 + + + PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_8 + PARAM_PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_8_NAME + 50.0 + + + PHY_DDR3_CONFIG_ENUM + Configuration + CONFIG_PHY_AND_HARD_CTRL + + + PHY_DDR3_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_DDR3_MEM_CLK_FREQ_MHZ + Memory clock frequency + 1066.667 + + + PHY_DDR3_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + true + + + PHY_DDR3_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + -1.0 + + + PHY_DDR3_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_DDR3_RATE_ENUM + Clock rate of user logic + RATE_QUARTER + + + PHY_DDR3_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_DDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_DDR3_IO_VOLTAGE + Voltage + 1.5 + + + PHY_DDR3_DEFAULT_IO + Use default I/O settings + true + + + PHY_DDR3_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_DDR3_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + true + + + PHY_DDR3_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_DDR3_USER_AC_IO_STD_ENUM + I/O standard + unset + + + PHY_DDR3_USER_AC_MODE_ENUM + Output mode + unset + + + PHY_DDR3_USER_AC_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_DDR3_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDR3_USER_CK_IO_STD_ENUM + I/O standard + unset + + + PHY_DDR3_USER_CK_MODE_ENUM + Output mode + unset + + + PHY_DDR3_USER_CK_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_DDR3_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDR3_USER_DATA_IO_STD_ENUM + I/O standard + unset + + + PHY_DDR3_USER_DATA_OUT_MODE_ENUM + Output mode + unset + + + PHY_DDR3_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_DDR3_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDR3_USER_DATA_IN_MODE_ENUM + Input mode + unset + + + PHY_DDR3_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_DDR3_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + unset + + + PHY_DDR3_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + unset + + + PHY_DDR3_CAL_ADDR0 + PARAM_PHY_DDR3_CAL_ADDR0_NAME + 0 + + + PHY_DDR3_CAL_ADDR1 + PARAM_PHY_DDR3_CAL_ADDR1_NAME + 8 + + + PHY_DDR3_CAL_ENABLE_NON_DES + PARAM_PHY_DDR3_CAL_ENABLE_NON_DES_NAME + false + + + PHY_DDR4_CONFIG_ENUM + Configuration + CONFIG_PHY_AND_HARD_CTRL + + + PHY_DDR4_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_DDR4_USER_CLAMSHELL_EN + Use clamshell layout + false + + + PHY_DDR4_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + true + + + PHY_DDR4_MEM_CLK_FREQ_MHZ + Memory clock frequency + 1200.0 + + + PHY_DDR4_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + false + + + PHY_DDR4_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + 150.0 + + + PHY_DDR4_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_DDR4_RATE_ENUM + Clock rate of user logic + RATE_QUARTER + + + PHY_DDR4_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_DDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_DDR4_IO_VOLTAGE + Voltage + 1.2 + + + PHY_DDR4_DEFAULT_IO + Use default I/O settings + false + + + PHY_DDR4_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_DDR4_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_DDR4_ALLOW_72_DQ_WIDTH + Allow DQ Widths of 72 + false + + + PHY_DDR4_USER_AC_IO_STD_ENUM + I/O standard + IO_STD_SSTL_12 + + + PHY_DDR4_USER_AC_MODE_ENUM + Output mode + OUT_OCT_40_CAL + + + PHY_DDR4_USER_AC_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_DDR4_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDR4_USER_CK_IO_STD_ENUM + I/O standard + IO_STD_SSTL_12 + + + PHY_DDR4_USER_CK_MODE_ENUM + Output mode + OUT_OCT_40_CAL + + + PHY_DDR4_USER_CK_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_DDR4_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDR4_USER_DATA_IO_STD_ENUM + I/O standard + IO_STD_POD_12 + + + PHY_DDR4_USER_DATA_OUT_MODE_ENUM + Output mode + OUT_OCT_34_CAL + + + PHY_DDR4_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_DDR4_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDR4_USER_DATA_IN_MODE_ENUM + Input mode + IN_OCT_48_CAL + + + PHY_DDR4_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_DDR4_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + IO_STD_LVDS + + + PHY_DDR4_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + IO_STD_CMOS_12 + + + PHY_QDR2_CONFIG_ENUM + Configuration + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_QDR2_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_QDR2_MEM_CLK_FREQ_MHZ + Memory clock frequency + 633.333 + + + PHY_QDR2_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + true + + + PHY_QDR2_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + -1.0 + + + PHY_QDR2_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_QDR2_RATE_ENUM + Clock rate of user logic + RATE_HALF + + + PHY_QDR2_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_QDR2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_QDR2_IO_VOLTAGE + Voltage + 1.5 + + + PHY_QDR2_DEFAULT_IO + Use default I/O settings + true + + + PHY_QDR2_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_QDR2_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + true + + + PHY_QDR2_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_QDR2_USER_AC_IO_STD_ENUM + I/O standard + unset + + + PHY_QDR2_USER_AC_MODE_ENUM + Output mode + unset + + + PHY_QDR2_USER_AC_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_QDR2_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_QDR2_USER_CK_IO_STD_ENUM + I/O standard + unset + + + PHY_QDR2_USER_CK_MODE_ENUM + Output mode + unset + + + PHY_QDR2_USER_CK_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_QDR2_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_QDR2_USER_DATA_IO_STD_ENUM + I/O standard + unset + + + PHY_QDR2_USER_DATA_OUT_MODE_ENUM + Output mode + unset + + + PHY_QDR2_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_QDR2_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_QDR2_USER_DATA_IN_MODE_ENUM + Input mode + unset + + + PHY_QDR2_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_QDR2_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + unset + + + PHY_QDR2_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + unset + + + PHY_QDR4_CONFIG_ENUM + Configuration + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_QDR4_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_QDR4_MEM_CLK_FREQ_MHZ + Memory clock frequency + 1066.667 + + + PHY_QDR4_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + true + + + PHY_QDR4_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + -1.0 + + + PHY_QDR4_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_QDR4_RATE_ENUM + Clock rate of user logic + RATE_QUARTER + + + PHY_QDR4_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_QDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_QDR4_IO_VOLTAGE + Voltage + 1.2 + + + PHY_QDR4_DEFAULT_IO + Use default I/O settings + true + + + PHY_QDR4_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_QDR4_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + true + + + PHY_QDR4_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_QDR4_USER_AC_IO_STD_ENUM + I/O standard + unset + + + PHY_QDR4_USER_AC_MODE_ENUM + Output mode + unset + + + PHY_QDR4_USER_AC_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_QDR4_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_QDR4_USER_CK_IO_STD_ENUM + I/O standard + unset + + + PHY_QDR4_USER_CK_MODE_ENUM + Output mode + unset + + + PHY_QDR4_USER_CK_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_QDR4_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_QDR4_USER_DATA_IO_STD_ENUM + I/O standard + unset + + + PHY_QDR4_USER_DATA_OUT_MODE_ENUM + Output mode + unset + + + PHY_QDR4_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_QDR4_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_QDR4_USER_DATA_IN_MODE_ENUM + Input mode + unset + + + PHY_QDR4_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_QDR4_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + unset + + + PHY_QDR4_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + unset + + + PHY_RLD2_CONFIG_ENUM + Configuration + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_RLD2_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_RLD2_MEM_CLK_FREQ_MHZ + Memory clock frequency + 533.333 + + + PHY_RLD2_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + true + + + PHY_RLD2_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + -1.0 + + + PHY_RLD2_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_RLD2_RATE_ENUM + Clock rate of user logic + RATE_HALF + + + PHY_RLD2_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_RLD2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_RLD2_IO_VOLTAGE + Voltage + 1.8 + + + PHY_RLD2_DEFAULT_IO + Use default I/O settings + true + + + PHY_RLD2_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_RLD2_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + true + + + PHY_RLD2_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_RLD2_USER_AC_IO_STD_ENUM + I/O standard + unset + + + PHY_RLD2_USER_AC_MODE_ENUM + Output mode + unset + + + PHY_RLD2_USER_AC_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_RLD2_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_RLD2_USER_CK_IO_STD_ENUM + I/O standard + unset + + + PHY_RLD2_USER_CK_MODE_ENUM + Output mode + unset + + + PHY_RLD2_USER_CK_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_RLD2_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_RLD2_USER_DATA_IO_STD_ENUM + I/O standard + unset + + + PHY_RLD2_USER_DATA_OUT_MODE_ENUM + Output mode + unset + + + PHY_RLD2_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_RLD2_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_RLD2_USER_DATA_IN_MODE_ENUM + Input mode + unset + + + PHY_RLD2_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_RLD2_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + unset + + + PHY_RLD2_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + unset + + + PHY_RLD3_CONFIG_ENUM + Configuration + CONFIG_PHY_ONLY + + + PHY_RLD3_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_RLD3_MEM_CLK_FREQ_MHZ + Memory clock frequency + 1066.667 + + + PHY_RLD3_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + true + + + PHY_RLD3_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + -1.0 + + + PHY_RLD3_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_RLD3_RATE_ENUM + Clock rate of user logic + RATE_QUARTER + + + PHY_RLD3_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_RLD3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_RLD3_IO_VOLTAGE + Voltage + 1.2 + + + PHY_RLD3_DEFAULT_IO + Use default I/O settings + true + + + PHY_RLD3_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_RLD3_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + true + + + PHY_RLD3_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_RLD3_USER_AC_IO_STD_ENUM + I/O standard + unset + + + PHY_RLD3_USER_AC_MODE_ENUM + Output mode + unset + + + PHY_RLD3_USER_AC_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_RLD3_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_RLD3_USER_CK_IO_STD_ENUM + I/O standard + unset + + + PHY_RLD3_USER_CK_MODE_ENUM + Output mode + unset + + + PHY_RLD3_USER_CK_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_RLD3_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_RLD3_USER_DATA_IO_STD_ENUM + I/O standard + unset + + + PHY_RLD3_USER_DATA_OUT_MODE_ENUM + Output mode + unset + + + PHY_RLD3_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_RLD3_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_RLD3_USER_DATA_IN_MODE_ENUM + Input mode + unset + + + PHY_RLD3_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_RLD3_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + unset + + + PHY_RLD3_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + unset + + + PHY_LPDDR3_CONFIG_ENUM + Configuration + CONFIG_PHY_AND_HARD_CTRL + + + PHY_LPDDR3_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_LPDDR3_MEM_CLK_FREQ_MHZ + Memory clock frequency + 800.0 + + + PHY_LPDDR3_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + true + + + PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + -1.0 + + + PHY_LPDDR3_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_LPDDR3_RATE_ENUM + Clock rate of user logic + RATE_QUARTER + + + PHY_LPDDR3_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_LPDDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_LPDDR3_IO_VOLTAGE + Voltage + 1.2 + + + PHY_LPDDR3_DEFAULT_IO + Use default I/O settings + true + + + PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_LPDDR3_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + true + + + PHY_LPDDR3_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_LPDDR3_USER_AC_IO_STD_ENUM + I/O standard + unset + + + PHY_LPDDR3_USER_AC_MODE_ENUM + Output mode + unset + + + PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_LPDDR3_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_LPDDR3_USER_CK_IO_STD_ENUM + I/O standard + unset + + + PHY_LPDDR3_USER_CK_MODE_ENUM + Output mode + unset + + + PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_LPDDR3_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_LPDDR3_USER_DATA_IO_STD_ENUM + I/O standard + unset + + + PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM + Output mode + unset + + + PHY_LPDDR3_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_LPDDR3_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_LPDDR3_USER_DATA_IN_MODE_ENUM + Input mode + unset + + + PHY_LPDDR3_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_LPDDR3_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + unset + + + PHY_LPDDR3_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + unset + + + PHY_DDRT_CONFIG_ENUM + Configuration + CONFIG_PHY_AND_SOFT_CTRL + + + PHY_DDRT_USER_PING_PONG_EN + Instantiate two controllers sharing a Ping Pong PHY + false + + + PHY_DDRT_USER_DLL_CORE_UPDN_EN + Use linear search for DLL lock + false + + + PHY_DDRT_MEM_CLK_FREQ_MHZ + Memory clock frequency + 1200.0 + + + PHY_DDRT_DEFAULT_REF_CLK_FREQ + Use recommended PLL reference clock frequency + true + + + PHY_DDRT_USER_REF_CLK_FREQ_MHZ + PLL reference clock frequency + -1.0 + + + PHY_DDRT_REF_CLK_JITTER_PS + PLL reference clock jitter + 10.0 + + + PHY_DDRT_RATE_ENUM + Clock rate of user logic + RATE_QUARTER + + + PHY_DDRT_CORE_CLKS_SHARING_ENUM + Core clocks sharing + CORE_CLKS_SHARING_DISABLED + + + PHY_DDRT_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT + Export clks_sharing_slave_out to facilitate multi-slave connectivity + false + + + PHY_DDRT_IO_VOLTAGE + Voltage + 1.2 + + + PHY_DDRT_DEFAULT_IO + Use default I/O settings + true + + + PHY_DDRT_HPS_ENABLE_EARLY_RELEASE + Enable HPS Early Release Mode + false + + + PHY_DDRT_USER_PERIODIC_OCT_RECAL_ENUM + Periodic OCT re-calibration + PERIODIC_OCT_RECAL_AUTO + + + PHY_DDRT_MIMIC_HPS_EMIF + Mimic HPS EMIF + false + + + PHY_DDRT_IC_EN + Enable I2C Master + true + + + PHY_DDRT_2CH_EN + Enable 2 Channel + false + + + PHY_DDRT_USE_OLD_SMBUS_MULTICOL + Enable I2C Multicolumn + false + + + PHY_DDRT_EXPORT_CLK_STP_IF + Export Clock Stop Interface + false + + + PHY_DDRT_I2C_USE_SMC + PARAM_PHY_I2C_USE_SMC_NAME + false + + + PHY_DDRT_USER_AC_IO_STD_ENUM + I/O standard + unset + + + PHY_DDRT_USER_AC_MODE_ENUM + Output mode + unset + + + PHY_DDRT_USER_AC_IN_MODE_ENUM + Input mode + unset + + + PHY_DDRT_USER_AC_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_DDRT_USER_AC_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDRT_USER_CK_IO_STD_ENUM + I/O standard + unset + + + PHY_DDRT_USER_CK_MODE_ENUM + Output mode + unset + + + PHY_DDRT_USER_CK_SLEW_RATE_ENUM + Slew rate + SLEW_RATE_FAST + + + PHY_DDRT_USER_CK_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDRT_USER_DATA_IO_STD_ENUM + I/O standard + unset + + + PHY_DDRT_USER_DATA_OUT_MODE_ENUM + Output mode + unset + + + PHY_DDRT_USER_DATA_OUT_SLEW_RATE_ENUM + Slew rate + unset + + + PHY_DDRT_USER_DATA_OUT_DEEMPHASIS_ENUM + Deemphasis mode + unset + + + PHY_DDRT_USER_DATA_IN_MODE_ENUM + Input mode + unset + + + PHY_DDRT_USER_AUTO_STARTING_VREFIN_EN + Use recommended initial Vrefin + true + + + PHY_DDRT_USER_STARTING_VREFIN + Initial Vrefin + 70.0 + + + PHY_DDRT_USER_PLL_REF_CLK_IO_STD_ENUM + PLL reference clock I/O standard + unset + + + PHY_DDRT_USER_RZQ_IO_STD_ENUM + RZQ I/O standard + unset + + + MEM_DDR3_FORMAT_ENUM + Memory format + MEM_FORMAT_UDIMM + + + MEM_DDR3_DQ_WIDTH + DQ width + 72 + + + MEM_DDR3_DQ_PER_DQS + DQ pins per DQS group + 8 + + + MEM_DDR3_DISCRETE_CS_WIDTH + Number of chip selects + 1 + + + MEM_DDR3_NUM_OF_DIMMS + Number of DIMMs + 1 + + + MEM_DDR3_RANKS_PER_DIMM + Number of physical ranks per DIMM + 1 + + + MEM_DDR3_CKE_PER_DIMM + Number of clock enables per DIMM + 1 + + + MEM_DDR3_CK_WIDTH + Number of clocks + 1 + + + MEM_DDR3_ROW_ADDR_WIDTH + Row address width + 15 + + + MEM_DDR3_COL_ADDR_WIDTH + Column address width + 10 + + + MEM_DDR3_BANK_ADDR_WIDTH + Bank address width + 3 + + + MEM_DDR3_DM_EN + Enable DM pins + true + + + MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN + Enable address mirroring for odd chip-selects + false + + + MEM_DDR3_MIRROR_ADDRESSING_EN + Enable address mirroring for odd ranks + true + + + MEM_DDR3_HIDE_ADV_MR_SETTINGS + Hide advanced mode register settings + true + + + MEM_DDR3_RDIMM_CONFIG + DDR3 RDIMM/LRDIMM control words + 0000000000000000 + + + MEM_DDR3_LRDIMM_EXTENDED_CONFIG + DDR3 LRDIMM additional control words + 000000000000000000 + + + MEM_DDR3_ALERT_N_PLACEMENT_ENUM + ALERT# pin placement + DDR3_ALERT_N_PLACEMENT_AC_LANES + + + MEM_DDR3_ALERT_N_DQS_GROUP + DQS group of ALERT# + 0 + + + MEM_DDR3_BL_ENUM + Burst Length + DDR3_BL_BL8 + + + MEM_DDR3_BT_ENUM + Read Burst Type + DDR3_BT_SEQUENTIAL + + + MEM_DDR3_ASR_ENUM + Auto self-refresh method + DDR3_ASR_MANUAL + + + MEM_DDR3_SRT_ENUM + Self-refresh temperature + DDR3_SRT_NORMAL + + + MEM_DDR3_PD_ENUM + DLL precharge power down + DDR3_PD_OFF + + + MEM_DDR3_DRV_STR_ENUM + Output drive strength setting + DDR3_DRV_STR_RZQ_7 + + + MEM_DDR3_DLL_EN + Enable the DLL in memory device + true + + + MEM_DDR3_RTT_NOM_ENUM + ODT Rtt nominal value + DDR3_RTT_NOM_ODT_DISABLED + + + MEM_DDR3_RTT_WR_ENUM + Dynamic ODT (Rtt_WR) value + DDR3_RTT_WR_RZQ_4 + + + MEM_DDR3_WTCL + Memory write CAS latency setting + 10 + + + MEM_DDR3_ATCL_ENUM + Memory additive CAS latency setting + DDR3_ATCL_DISABLED + + + MEM_DDR3_TCL + Memory CAS latency setting + 14 + + + MEM_DDR3_USE_DEFAULT_ODT + Use Default ODT Assertion Tables + true + + + MEM_DDR3_R_ODTN_1X1 + Read Target + Rank 0 + + + MEM_DDR3_R_ODT0_1X1 + ODT0 + off + + + MEM_DDR3_W_ODTN_1X1 + Write Target + Rank 0 + + + MEM_DDR3_W_ODT0_1X1 + ODT0 + on + + + MEM_DDR3_R_ODTN_2X2 + Read Target + Rank 0,Rank 1 + + + MEM_DDR3_R_ODT0_2X2 + ODT0 + off,off + + + MEM_DDR3_R_ODT1_2X2 + ODT1 + off,off + + + MEM_DDR3_W_ODTN_2X2 + Write Target + Rank 0,Rank 1 + + + MEM_DDR3_W_ODT0_2X2 + ODT0 + on,off + + + MEM_DDR3_W_ODT1_2X2 + ODT1 + off,on + + + MEM_DDR3_R_ODTN_4X2 + Read Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_R_ODT0_4X2 + ODT0 + off,off,on,on + + + MEM_DDR3_R_ODT1_4X2 + ODT1 + on,on,off,off + + + MEM_DDR3_W_ODTN_4X2 + Write Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_W_ODT0_4X2 + ODT0 + off,off,on,on + + + MEM_DDR3_W_ODT1_4X2 + ODT1 + on,on,off,off + + + MEM_DDR3_R_ODTN_4X4 + Read Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_R_ODT0_4X4 + ODT0 + off,off,off,off + + + MEM_DDR3_R_ODT1_4X4 + ODT1 + off,off,on,on + + + MEM_DDR3_R_ODT2_4X4 + ODT2 + off,off,off,off + + + MEM_DDR3_R_ODT3_4X4 + ODT3 + on,on,off,off + + + MEM_DDR3_W_ODTN_4X4 + Write Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR3_W_ODT0_4X4 + ODT0 + on,on,off,off + + + MEM_DDR3_W_ODT1_4X4 + ODT1 + off,off,on,on + + + MEM_DDR3_W_ODT2_4X4 + ODT2 + off,off,on,on + + + MEM_DDR3_W_ODT3_4X4 + ODT3 + on,on,off,off + + + MEM_DDR3_SPEEDBIN_ENUM + Speed bin + DDR3_SPEEDBIN_2133 + + + MEM_DDR3_TIS_PS + tIS (base) + 60 + + + MEM_DDR3_TIS_AC_MV + tIS (base) AC level + 135 + + + MEM_DDR3_TIH_PS + tIH (base) + 95 + + + MEM_DDR3_TIH_DC_MV + tIH (base) DC level + 100 + + + MEM_DDR3_TDS_PS + tDS (base) + 53 + + + MEM_DDR3_TDS_AC_MV + tDS (base) AC level + 135 + + + MEM_DDR3_TDH_PS + tDH (base) + 55 + + + MEM_DDR3_TDH_DC_MV + tDH (base) DC level + 100 + + + MEM_DDR3_TDQSQ_PS + tDQSQ + 75 + + + MEM_DDR3_TQH_CYC + tQH + 0.38 + + + MEM_DDR3_TDQSCK_PS + tDQSCK + 180 + + + MEM_DDR3_TDQSS_CYC + tDQSS + 0.27 + + + MEM_DDR3_TQSH_CYC + tQSH + 0.4 + + + MEM_DDR3_TDSH_CYC + tDSH + 0.18 + + + MEM_DDR3_TWLS_PS + tWLS + 125.0 + + + MEM_DDR3_TWLH_PS + tWLH + 125.0 + + + MEM_DDR3_TDSS_CYC + tDSS + 0.18 + + + MEM_DDR3_TINIT_US + tINIT + 500 + + + MEM_DDR3_TMRD_CK_CYC + tMRD + 4 + + + MEM_DDR3_TRAS_NS + tRAS + 33.0 + + + MEM_DDR3_TRCD_NS + tRCD + 13.09 + + + MEM_DDR3_TRP_NS + tRP + 13.09 + + + MEM_DDR3_TREFI_US + tREFI + 7.8 + + + MEM_DDR3_TRFC_NS + tRFC + 160.0 + + + MEM_DDR3_TWR_NS + tWR + 15.0 + + + MEM_DDR3_TWTR_CYC + tWTR + 8 + + + MEM_DDR3_TFAW_NS + tFAW + 25.0 + + + MEM_DDR3_TRRD_CYC + tRRD + 6 + + + MEM_DDR3_TRTP_CYC + tRTP + 8 + + + MEM_DDR3_CFG_GEN_SBE + PARAM_MEM_DDR3_CFG_GEN_SBE_NAME + false + + + MEM_DDR3_CFG_GEN_DBE + PARAM_MEM_DDR3_CFG_GEN_DBE_NAME + false + + + MEM_DDR4_FORMAT_ENUM + Memory format + MEM_FORMAT_RDIMM + + + MEM_DDR4_DQ_WIDTH + DQ width + 72 + + + MEM_DDR4_DQ_PER_DQS + DQ pins per DQS group + 8 + + + MEM_DDR4_DISCRETE_CS_WIDTH + Number of chip selects + 1 + + + MEM_DDR4_NUM_OF_DIMMS + Number of DIMMs + 1 + + + MEM_DDR4_CHIP_ID_WIDTH + Chip ID width + 0 + + + MEM_DDR4_RANKS_PER_DIMM + Number of physical ranks per DIMM + 1 + + + MEM_DDR4_CKE_PER_DIMM + Number of clock enables per DIMM + 1 + + + MEM_DDR4_CK_WIDTH + Number of clocks + 1 + + + MEM_DDR4_ROW_ADDR_WIDTH + Row address width + 16 + + + MEM_DDR4_COL_ADDR_WIDTH + Column address width + 10 + + + MEM_DDR4_BANK_ADDR_WIDTH + Bank address width + 2 + + + MEM_DDR4_BANK_GROUP_WIDTH + Bank group width + 2 + + + MEM_DDR4_DM_EN + Data mask + true + + + MEM_DDR4_ALERT_PAR_EN + Enable ALERT#/PAR pins + true + + + MEM_DDR4_ALERT_N_PLACEMENT_ENUM + ALERT# pin placement + DDR4_ALERT_N_PLACEMENT_AC_LANES + + + MEM_DDR4_ALERT_N_DQS_GROUP + DQS group of ALERT# + 0 + + + MEM_DDR4_ALERT_N_AC_LANE + Address/command I/O lane of ALERT# + 0 + + + MEM_DDR4_ALERT_N_AC_PIN + Pin index of ALERT# + 10 + + + MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN + Enable address mirroring for odd chip-selects + false + + + MEM_DDR4_MIRROR_ADDRESSING_EN + Enable address mirroring for odd ranks + false + + + MEM_DDR4_HIDE_ADV_MR_SETTINGS + Hide advanced mode register settings + false + + + MEM_DDR4_INTEL_DEFAULT_TERM + Use Default Memory I/O Settings + true + + + MEM_DDR4_BL_ENUM + Burst Length + DDR4_BL_BL8 + + + MEM_DDR4_BT_ENUM + Read Burst Type + DDR4_BT_SEQUENTIAL + + + MEM_DDR4_TCL + Memory CAS latency setting + 21 + + + MEM_DDR4_RTT_NOM_ENUM + ODT Rtt nominal value + DDR4_RTT_NOM_RZQ_4 + + + MEM_DDR4_DLL_EN + Enable the DLL in memory device + true + + + MEM_DDR4_ATCL_ENUM + Memory additive CAS latency setting + DDR4_ATCL_DISABLED + + + MEM_DDR4_DRV_STR_ENUM + Output drive strength setting + DDR4_DRV_STR_RZQ_7 + + + MEM_DDR4_ASR_ENUM + Auto self-refresh method + DDR4_ASR_MANUAL_NORMAL + + + MEM_DDR4_RTT_WR_ENUM + Dynamic ODT (Rtt_WR) value + DDR4_RTT_WR_ODT_DISABLED + + + MEM_DDR4_WTCL + Memory write CAS latency setting + 16 + + + MEM_DDR4_WRITE_CRC + Write CRC enable + false + + + MEM_DDR4_GEARDOWN + DDR4 geardown mode + DDR4_GEARDOWN_HR + + + MEM_DDR4_PER_DRAM_ADDR + Per-DRAM addressability + false + + + MEM_DDR4_TEMP_SENSOR_READOUT + Temperature sensor readout + false + + + MEM_DDR4_FINE_GRANULARITY_REFRESH + Fine granularity refresh + DDR4_FINE_REFRESH_FIXED_1X + + + MEM_DDR4_MPR_READ_FORMAT + MPR read format + DDR4_MPR_READ_FORMAT_SERIAL + + + MEM_DDR4_MAX_POWERDOWN + Maximum power down mode + false + + + MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE + Temperature controlled refresh range + DDR4_TEMP_CONTROLLED_RFSH_NORMAL + + + MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA + Temperature controlled refresh enable + false + + + MEM_DDR4_INTERNAL_VREFDQ_MONITOR + Internal VrefDQ monitor + false + + + MEM_DDR4_CAL_MODE + CS to Addr/CMD Latency + 0 + + + MEM_DDR4_SELF_RFSH_ABORT + Self refresh abort + false + + + MEM_DDR4_READ_PREAMBLE_TRAINING + Read preamble training mode enable + false + + + MEM_DDR4_READ_PREAMBLE + Read preamble + 2 + + + MEM_DDR4_WRITE_PREAMBLE + Write preamble + 1 + + + MEM_DDR4_AC_PARITY_LATENCY + Addr/CMD parity latency + DDR4_AC_PARITY_LATENCY_4 + + + MEM_DDR4_ODT_IN_POWERDOWN + ODT input buffer during powerdown mode + true + + + MEM_DDR4_RTT_PARK + RTT PARK + DDR4_RTT_PARK_ODT_DISABLED + + + MEM_DDR4_AC_PERSISTENT_ERROR + Addr/CMD persistent error + false + + + MEM_DDR4_WRITE_DBI + Write DBI + false + + + MEM_DDR4_READ_DBI + Read DBI + true + + + MEM_DDR4_DEFAULT_VREFOUT + Use recommended initial VrefDQ value + true + + + MEM_DDR4_USER_VREFDQ_TRAINING_VALUE + VrefDQ training value + 56.0 + + + MEM_DDR4_USER_VREFDQ_TRAINING_RANGE + VrefDQ training range + DDR4_VREFDQ_TRAINING_RANGE_1 + + + MEM_DDR4_RCD_CA_IBT_ENUM + RCD CA Input Bus Termination + DDR4_RCD_CA_IBT_100 + + + MEM_DDR4_RCD_CS_IBT_ENUM + RCD DCS[3:0]_n Input Bus Termination + DDR4_RCD_CS_IBT_100 + + + MEM_DDR4_RCD_CKE_IBT_ENUM + RCD DCKE Input Bus Termination + DDR4_RCD_CKE_IBT_100 + + + MEM_DDR4_RCD_ODT_IBT_ENUM + RCD DODT Input Bus Termination + DDR4_RCD_ODT_IBT_100 + + + MEM_DDR4_DB_RTT_NOM_ENUM + DB Host Interface DQ RTT_NOM + DDR4_DB_RTT_NOM_ODT_DISABLED + + + MEM_DDR4_DB_RTT_WR_ENUM + DB Host Interface DQ RTT_WR + DDR4_DB_RTT_WR_RZQ_3 + + + MEM_DDR4_DB_RTT_PARK_ENUM + DB Host Interface DQ RTT_PARK + DDR4_DB_RTT_PARK_ODT_DISABLED + + + MEM_DDR4_DB_DQ_DRV_ENUM + DB Host Interface DQ Driver + DDR4_DB_DRV_STR_RZQ_7 + + + MEM_DDR4_SPD_137_RCD_CA_DRV + SPD Byte 137 - RCD Drive Strength for Command/Address + 0 + + + MEM_DDR4_SPD_138_RCD_CK_DRV + SPD Byte 138 - RCD Drive Strength for CK + 0 + + + MEM_DDR4_SPD_140_DRAM_VREFDQ_R0 + SPD Byte 140 - DRAM VrefDQ for Package Rank 0 + 29 + + + MEM_DDR4_SPD_141_DRAM_VREFDQ_R1 + SPD Byte 141 - DRAM VrefDQ for Package Rank 1 + 29 + + + MEM_DDR4_SPD_142_DRAM_VREFDQ_R2 + SPD Byte 142 - DRAM VrefDQ for Package Rank 2 + 29 + + + MEM_DDR4_SPD_143_DRAM_VREFDQ_R3 + SPD Byte 143 - DRAM VrefDQ for Package Rank 3 + 29 + + + MEM_DDR4_SPD_144_DB_VREFDQ + SPD Byte 144 - DB VrefDQ for DRAM Interface + 37 + + + MEM_DDR4_SPD_145_DB_MDQ_DRV + SPD Byte 145-147 - DB MDQ Drive Strength and RTT + 21 + + + MEM_DDR4_SPD_148_DRAM_DRV + SPD Byte 148 - DRAM Drive Strength + 0 + + + MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM + SPD Byte 149-151 - DRAM ODT (RTT_WR and RTT_NOM) + 20 + + + MEM_DDR4_SPD_152_DRAM_RTT_PARK + SPD Byte 152-154 - DRAM ODT (RTT_PARK) + 39 + + + MEM_DDR4_SPD_155_DB_VREFDQ_RANGE + SPD Byte 155 - DB VrefDQ for DRAM Interface Range + 0 + + + MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB + RCD and DB Manufacturer (LSB) + 0 + + + MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB + RCD and DB Manufacturer (MSB) + 0 + + + MEM_DDR4_SPD_135_RCD_REV + RCD Revision Number + 0 + + + MEM_DDR4_SPD_139_DB_REV + DB Revision Number + 0 + + + MEM_DDR4_LRDIMM_ODT_LESS_BS + PARAM_MEM_DDR4_LRDIMM_ODT_LESS_BS_NAME + true + + + MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM + PARAM_MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM_NAME + 240 + + + MEM_DDR4_USE_DEFAULT_ODT + Use Default ODT Assertion Tables + true + + + MEM_DDR4_R_ODTN_1X1 + Read Target + Rank 0 + + + MEM_DDR4_R_ODT0_1X1 + ODT0 + off + + + MEM_DDR4_W_ODTN_1X1 + Write Target + Rank 0 + + + MEM_DDR4_W_ODT0_1X1 + ODT0 + on + + + MEM_DDR4_R_ODTN_2X2 + Read Target + Rank 0,Rank 1 + + + MEM_DDR4_R_ODT0_2X2 + ODT0 + off,off + + + MEM_DDR4_R_ODT1_2X2 + ODT1 + off,off + + + MEM_DDR4_W_ODTN_2X2 + Write Target + Rank 0,Rank 1 + + + MEM_DDR4_W_ODT0_2X2 + ODT0 + on,off + + + MEM_DDR4_W_ODT1_2X2 + ODT1 + off,on + + + MEM_DDR4_R_ODTN_4X2 + Read Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_R_ODT0_4X2 + ODT0 + off,off,on,on + + + MEM_DDR4_R_ODT1_4X2 + ODT1 + on,on,off,off + + + MEM_DDR4_W_ODTN_4X2 + Write Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_W_ODT0_4X2 + ODT0 + off,off,on,on + + + MEM_DDR4_W_ODT1_4X2 + ODT1 + on,on,off,off + + + MEM_DDR4_R_ODTN_4X4 + Read Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_R_ODT0_4X4 + ODT0 + off,off,off,off + + + MEM_DDR4_R_ODT1_4X4 + ODT1 + off,off,on,on + + + MEM_DDR4_R_ODT2_4X4 + ODT2 + off,off,off,off + + + MEM_DDR4_R_ODT3_4X4 + ODT3 + on,on,off,off + + + MEM_DDR4_W_ODTN_4X4 + Write Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDR4_W_ODT0_4X4 + ODT0 + on,on,off,off + + + MEM_DDR4_W_ODT1_4X4 + ODT1 + off,off,on,on + + + MEM_DDR4_W_ODT2_4X4 + ODT2 + off,off,on,on + + + MEM_DDR4_W_ODT3_4X4 + ODT3 + on,on,off,off + + + MEM_DDR4_SPEEDBIN_ENUM + Speed bin + DDR4_SPEEDBIN_2400 + + + MEM_DDR4_TIS_PS + tIS (base) + 62 + + + MEM_DDR4_TIS_AC_MV + tIS (base) AC level + 100 + + + MEM_DDR4_TIH_PS + tIH (base) + 87 + + + MEM_DDR4_TIH_DC_MV + tIH (base) DC level + 75 + + + MEM_DDR4_TDIVW_TOTAL_UI + TdiVW_total + 0.2 + + + MEM_DDR4_VDIVW_TOTAL + VdiVW_total + 130 + + + MEM_DDR4_TDQSQ_UI + tDQSQ + 0.17 + + + MEM_DDR4_TQH_UI + tQH + 0.74 + + + MEM_DDR4_TDVWP_UI + tDVWp + 0.72 + + + MEM_DDR4_TDQSCK_PS + tDQSCK + 175 + + + MEM_DDR4_TDQSS_CYC + tDQSS + 0.27 + + + MEM_DDR4_TQSH_CYC + tQSH + 0.4 + + + MEM_DDR4_TDSH_CYC + tDSH + 0.18 + + + MEM_DDR4_TDSS_CYC + tDSS + 0.18 + + + MEM_DDR4_TWLS_CYC + tWLS + 0.13 + + + MEM_DDR4_TWLH_CYC + tWLH + 0.13 + + + MEM_DDR4_TINIT_US + tINIT + 500 + + + MEM_DDR4_TMRD_CK_CYC + tMRD + 8 + + + MEM_DDR4_TRAS_NS + tRAS + 32.0 + + + MEM_DDR4_TRCD_NS + tRCD + 14.16 + + + MEM_DDR4_TRP_NS + tRP + 14.16 + + + MEM_DDR4_TREFI_US + tREFI + 7.8 + + + MEM_DDR4_TRFC_NS + tRFC + 350.0 + + + MEM_DDR4_TWR_NS + tWR + 15.0 + + + MEM_DDR4_TWTR_L_CYC + tWTR_L + 9 + + + MEM_DDR4_TWTR_S_CYC + tWTR_S + 3 + + + MEM_DDR4_TFAW_NS + tFAW + 21.0 + + + MEM_DDR4_TRRD_L_CYC + tRRD_L + 6 + + + MEM_DDR4_TRRD_S_CYC + tRRD_S + 4 + + + MEM_DDR4_TCCD_L_CYC + tCCD_L + 6 + + + MEM_DDR4_TCCD_S_CYC + tCCD_S + 4 + + + MEM_DDR4_TRFC_DLR_NS + tRFC_dlr + 90.0 + + + MEM_DDR4_TFAW_DLR_CYC + tFAW_dlr + 16 + + + MEM_DDR4_TRRD_DLR_CYC + tRRD_dlr + 4 + + + MEM_DDR4_TDIVW_DJ_CYC + PARAM_MEM_DDR4_TDIVW_DJ_CYC_NAME + 0.1 + + + MEM_DDR4_TDQSQ_PS + PARAM_MEM_DDR4_TDQSQ_PS_NAME + 66 + + + MEM_DDR4_TQH_CYC + PARAM_MEM_DDR4_TQH_CYC_NAME + 0.38 + + + MEM_DDR4_CFG_GEN_SBE + PARAM_MEM_DDR4_CFG_GEN_SBE_NAME + false + + + MEM_DDR4_CFG_GEN_DBE + PARAM_MEM_DDR4_CFG_GEN_DBE_NAME + false + + + MEM_DDR4_LRDIMM_VREFDQ_VALUE + PARAM_MEM_DDR4_LRDIMM_VREFDQ_VALUE_NAME + + + + MEM_DDR4_TWLS_PS + PARAM_MEM_DDR4_TWLS_PS_NAME + 0.0 + + + MEM_DDR4_TWLH_PS + PARAM_MEM_DDR4_TWLH_PS_NAME + 0.0 + + + MEM_QDR2_WIDTH_EXPANDED + Enable width expansion + false + + + MEM_QDR2_DATA_PER_DEVICE + Data width per device + 36 + + + MEM_QDR2_ADDR_WIDTH + Address width + 19 + + + MEM_QDR2_BWS_EN + Enable BWS# pins + true + + + MEM_QDR2_BL + Burst length + 4 + + + MEM_QDR2_SPEEDBIN_ENUM + Speed bin + QDR2_SPEEDBIN_633 + + + MEM_QDR2_TRL_CYC + tRL + 2.5 + + + MEM_QDR2_TSA_NS + tSA + 0.23 + + + MEM_QDR2_THA_NS + tHA + 0.18 + + + MEM_QDR2_TSD_NS + tSD + 0.23 + + + MEM_QDR2_THD_NS + tHD + 0.18 + + + MEM_QDR2_TCQD_NS + tCQD + 0.09 + + + MEM_QDR2_TCQDOH_NS + tCQDOH + -0.09 + + + MEM_QDR2_INTERNAL_JITTER_NS + Internal Jitter + 0.08 + + + MEM_QDR2_TCQH_NS + tCQH + 0.71 + + + MEM_QDR2_TCCQO_NS + tCCQO + 0.45 + + + MEM_QDR4_WIDTH_EXPANDED + Enable width expansion + false + + + MEM_QDR4_DQ_PER_PORT_PER_DEVICE + DQ width per device + 36 + + + MEM_QDR4_ADDR_WIDTH + Address width + 21 + + + MEM_QDR4_SKIP_ODT_SWEEPING + Skip automatic optimization of Clock and Address/Command ODT setting during calibration + true + + + MEM_QDR4_CK_ODT_MODE_ENUM + ODT (Clock) + QDR4_ODT_25_PCT + + + MEM_QDR4_AC_ODT_MODE_ENUM + ODT (Address/Command) + QDR4_ODT_25_PCT + + + MEM_QDR4_DATA_ODT_MODE_ENUM + ODT (Data) + QDR4_ODT_25_PCT + + + MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM + Output drive (pull-up) + QDR4_OUTPUT_DRIVE_25_PCT + + + MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM + Output drive (pull-down) + QDR4_OUTPUT_DRIVE_25_PCT + + + MEM_QDR4_MEM_TYPE_ENUM + Memory Type + MEM_XP + + + MEM_QDR4_DATA_INV_ENA + Data bus inversion + true + + + MEM_QDR4_ADDR_INV_ENA + Address bus inversion + false + + + MEM_QDR4_USE_ADDR_PARITY + Use address parity bit + false + + + MEM_QDR4_SPEEDBIN_ENUM + Speed bin + QDR4_SPEEDBIN_2133 + + + MEM_QDR4_TISH_PS + tISH + 150 + + + MEM_QDR4_TQKQ_MAX_PS + tQKQ_max + 75 + + + MEM_QDR4_TQH_CYC + tQH + 0.4 + + + MEM_QDR4_TCKDK_MAX_PS + tCKDK_max + 150 + + + MEM_QDR4_TCKDK_MIN_PS + tCKDK_min + -150 + + + MEM_QDR4_TCKQK_MAX_PS + tCKQK_max + 225 + + + MEM_QDR4_TASH_PS + tASH + 170 + + + MEM_QDR4_TCSH_PS + tCSH + 170 + + + MEM_RLD2_WIDTH_EXPANDED + Enable width expansion + false + + + MEM_RLD2_DQ_PER_DEVICE + DQ width per device + 9 + + + MEM_RLD2_ADDR_WIDTH + Address width + 21 + + + MEM_RLD2_BANK_ADDR_WIDTH + Bank address width + 3 + + + MEM_RLD2_DM_EN + Enable DM pins + true + + + MEM_RLD2_BL + Burst length + 4 + + + MEM_RLD2_CONFIG_ENUM + Configuration + RLD2_CONFIG_TRC_8_TRL_8_TWL_9 + + + MEM_RLD2_DRIVE_IMPEDENCE_ENUM + Drive Impedance + RLD2_DRIVE_IMPEDENCE_INTERNAL_50 + + + MEM_RLD2_ODT_MODE_ENUM + On-Die Termination + RLD2_ODT_ON + + + MEM_RLD2_SPEEDBIN_ENUM + Speed bin + RLD2_SPEEDBIN_18 + + + MEM_RLD2_REFRESH_INTERVAL_US + Refresh Interval + 0.24 + + + MEM_RLD2_TCKH_CYC + tCKH + 0.45 + + + MEM_RLD2_TQKH_HCYC + tQKH + 0.9 + + + MEM_RLD2_TAS_NS + tAS + 0.3 + + + MEM_RLD2_TAH_NS + tAH + 0.3 + + + MEM_RLD2_TDS_NS + tDS + 0.17 + + + MEM_RLD2_TDH_NS + tDH + 0.17 + + + MEM_RLD2_TQKQ_MAX_NS + tQKQ_max + 0.12 + + + MEM_RLD2_TQKQ_MIN_NS + tQKQ_min + -0.12 + + + MEM_RLD2_TCKDK_MAX_NS + tCKDK_max + 0.3 + + + MEM_RLD2_TCKDK_MIN_NS + tCKDK_min + -0.3 + + + MEM_RLD2_TCKQK_MAX_NS + tCKQK_max + 0.2 + + + MEM_RLD3_WIDTH_EXPANDED + Enable width expansion + false + + + MEM_RLD3_DEPTH_EXPANDED + Enable depth expansion using twin die package + false + + + MEM_RLD3_DQ_PER_DEVICE + DQ width per device + 36 + + + MEM_RLD3_ADDR_WIDTH + Address width + 20 + + + MEM_RLD3_BANK_ADDR_WIDTH + Bank address width + 4 + + + MEM_RLD3_DM_EN + Enable DM pins + true + + + MEM_RLD3_BL + Burst length + 2 + + + MEM_RLD3_DATA_LATENCY_MODE_ENUM + Data Latency + RLD3_DL_RL16_WL17 + + + MEM_RLD3_T_RC_MODE_ENUM + tRC + RLD3_TRC_9 + + + MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM + Output drive + RLD3_OUTPUT_DRIVE_40 + + + MEM_RLD3_ODT_MODE_ENUM + ODT + RLD3_ODT_40 + + + MEM_RLD3_AREF_PROTOCOL_ENUM + AREF protocol + RLD3_AREF_BAC + + + MEM_RLD3_WRITE_PROTOCOL_ENUM + Write protocol + RLD3_WRITE_1BANK + + + MEM_RLD3_SPEEDBIN_ENUM + Speed bin + RLD3_SPEEDBIN_093E + + + MEM_RLD3_TDS_PS + tDS (base) + -30 + + + MEM_RLD3_TDS_AC_MV + tDS (base) AC level + 150 + + + MEM_RLD3_TDH_PS + tDH (base) + 5 + + + MEM_RLD3_TDH_DC_MV + tDH (base) DC level + 100 + + + MEM_RLD3_TQKQ_MAX_PS + tQKQ_max + 75 + + + MEM_RLD3_TQH_CYC + tQH + 0.38 + + + MEM_RLD3_TCKDK_MAX_CYC + tCKDK_max + 0.27 + + + MEM_RLD3_TCKDK_MIN_CYC + tCKDK_min + -0.27 + + + MEM_RLD3_TCKQK_MAX_PS + tCKQK_max + 135 + + + MEM_RLD3_TIS_PS + tIS (base) + 85 + + + MEM_RLD3_TIS_AC_MV + tIS (base) AC level + 150 + + + MEM_RLD3_TIH_PS + tIH (base) + 65 + + + MEM_RLD3_TIH_DC_MV + tIH (base) DC level + 100 + + + MEM_LPDDR3_DQ_WIDTH + DQ width + 32 + + + MEM_LPDDR3_DISCRETE_CS_WIDTH + Number of chip selects + 1 + + + MEM_LPDDR3_CK_WIDTH + Number of clocks + 1 + + + MEM_LPDDR3_DM_EN + Enable DM pins + true + + + MEM_LPDDR3_ROW_ADDR_WIDTH + Row address width + 15 + + + MEM_LPDDR3_COL_ADDR_WIDTH + Column address width + 10 + + + MEM_LPDDR3_BANK_ADDR_WIDTH + Bank address width + 3 + + + MEM_LPDDR3_BL + Burst length + LPDDR3_BL_BL8 + + + MEM_LPDDR3_DATA_LATENCY + Data latency + LPDDR3_DL_RL12_WL6 + + + MEM_LPDDR3_DRV_STR + Output drive strength setting + LPDDR3_DRV_STR_40D_40U + + + MEM_LPDDR3_DQODT + DQ ODT + LPDDR3_DQODT_DISABLE + + + MEM_LPDDR3_PDODT + Power down ODT + LPDDR3_PDODT_DISABLED + + + MEM_LPDDR3_USE_DEFAULT_ODT + Use Default ODT Assertion Tables + true + + + MEM_LPDDR3_R_ODTN_1X1 + Read Target + Rank 0 + + + MEM_LPDDR3_R_ODT0_1X1 + ODT0 + off + + + MEM_LPDDR3_W_ODTN_1X1 + Write Target + Rank 0 + + + MEM_LPDDR3_W_ODT0_1X1 + ODT0 + on + + + MEM_LPDDR3_R_ODTN_2X2 + Read Target + Rank 0,Rank 1 + + + MEM_LPDDR3_R_ODT0_2X2 + ODT0 + off,off + + + MEM_LPDDR3_R_ODT1_2X2 + ODT1 + off,off + + + MEM_LPDDR3_W_ODTN_2X2 + Write Target + Rank 0,Rank 1 + + + MEM_LPDDR3_W_ODT0_2X2 + ODT0 + on,on + + + MEM_LPDDR3_W_ODT1_2X2 + ODT1 + off,off + + + MEM_LPDDR3_R_ODTN_4X4 + Read Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_LPDDR3_R_ODT0_4X4 + ODT0 + off,off,off,off + + + MEM_LPDDR3_R_ODT1_4X4 + ODT1 + off,off,off,off + + + MEM_LPDDR3_R_ODT2_4X4 + ODT2 + off,off,off,off + + + MEM_LPDDR3_R_ODT3_4X4 + ODT3 + off,off,off,off + + + MEM_LPDDR3_W_ODTN_4X4 + Write Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_LPDDR3_W_ODT0_4X4 + ODT0 + on,on,on,on + + + MEM_LPDDR3_W_ODT1_4X4 + ODT1 + off,off,off,off + + + MEM_LPDDR3_W_ODT2_4X4 + ODT2 + off,off,off,off + + + MEM_LPDDR3_W_ODT3_4X4 + ODT3 + off,off,off,off + + + MEM_LPDDR3_SPEEDBIN_ENUM + Speed bin + LPDDR3_SPEEDBIN_1600 + + + MEM_LPDDR3_TIS_PS + tISCA (base) + 75 + + + MEM_LPDDR3_TIS_AC_MV + tISCA (base) AC level + 150 + + + MEM_LPDDR3_TIH_PS + tIHCA (base) + 100 + + + MEM_LPDDR3_TIH_DC_MV + tIHCA (base) DC level + 100 + + + MEM_LPDDR3_TDS_PS + tDS (base) + 75 + + + MEM_LPDDR3_TDS_AC_MV + tDS (base) AC level + 150 + + + MEM_LPDDR3_TDH_PS + tDH (base) + 100 + + + MEM_LPDDR3_TDH_DC_MV + tDH (base) DC level + 100 + + + MEM_LPDDR3_TDQSQ_PS + tDQSQ + 135 + + + MEM_LPDDR3_TQH_CYC + tQH + 0.38 + + + MEM_LPDDR3_TDQSCKDL + tDQSCKDL + 614 + + + MEM_LPDDR3_TDQSS_CYC + tDQSS (max) + 1.25 + + + MEM_LPDDR3_TQSH_CYC + tQSH + 0.38 + + + MEM_LPDDR3_TDSH_CYC + tDSH + 0.2 + + + MEM_LPDDR3_TWLS_PS + tWLS + 175.0 + + + MEM_LPDDR3_TWLH_PS + tWLH + 175.0 + + + MEM_LPDDR3_TDSS_CYC + tDSS + 0.2 + + + MEM_LPDDR3_TINIT_US + tINIT + 500 + + + MEM_LPDDR3_TMRR_CK_CYC + tMRR + 4 + + + MEM_LPDDR3_TMRW_CK_CYC + tMRW + 10 + + + MEM_LPDDR3_TRAS_NS + tRAS + 42.5 + + + MEM_LPDDR3_TRCD_NS + tRCD + 18.0 + + + MEM_LPDDR3_TRP_NS + tRPpb + 18.0 + + + MEM_LPDDR3_TREFI_US + tREFI + 3.9 + + + MEM_LPDDR3_TRFC_NS + tRFCab + 210.0 + + + MEM_LPDDR3_TWR_NS + tWR + 15.0 + + + MEM_LPDDR3_TWTR_CYC + tWTR + 6 + + + MEM_LPDDR3_TFAW_NS + tFAW + 50.0 + + + MEM_LPDDR3_TRRD_CYC + tRRD + 8 + + + MEM_LPDDR3_TRTP_CYC + tRTP + 6 + + + MEM_DDRT_FORMAT_ENUM + Memory format + MEM_FORMAT_LRDIMM + + + MEM_DDRT_DQ_WIDTH + DQ width + 72 + + + MEM_DDRT_DQ_PER_DQS + DQ pins per DQS group + 4 + + + MEM_DDRT_DISCRETE_CS_WIDTH + Number of chip selects + 1 + + + MEM_DDRT_NUM_OF_DIMMS + Number of DIMMs + 1 + + + MEM_DDRT_RANKS_PER_DIMM + Number of physical ranks per DIMM + 1 + + + MEM_DDRT_CKE_PER_DIMM + Number of clock enables per DIMM + 1 + + + MEM_DDRT_ROW_ADDR_WIDTH + Row address width + 18 + + + MEM_DDRT_COL_ADDR_WIDTH + Column address width + 10 + + + MEM_DDRT_BANK_ADDR_WIDTH + Bank address width + 2 + + + MEM_DDRT_BANK_GROUP_WIDTH + Bank group width + 2 + + + MEM_DDRT_DM_EN + Data mask + false + + + MEM_DDRT_ALERT_PAR_EN + Enable ALERT#/PAR pins + true + + + MEM_DDRT_ALERT_N_PLACEMENT_ENUM + ALERT# pin placement + DDRT_ALERT_N_PLACEMENT_AUTO + + + MEM_DDRT_ALERT_N_DQS_GROUP + DQS group of ALERT# + 0 + + + MEM_DDRT_ALERT_N_AC_LANE + Address/command I/O lane of ALERT# + 0 + + + MEM_DDRT_ALERT_N_AC_PIN + Pin index of ALERT# + 0 + + + MEM_DDRT_DISCRETE_MIRROR_ADDRESSING_EN + Enable address mirroring for odd chip-selects + false + + + MEM_DDRT_MIRROR_ADDRESSING_EN + Enable address mirroring for odd ranks + true + + + MEM_DDRT_HIDE_ADV_MR_SETTINGS + Hide advanced mode register settings + true + + + MEM_DDRT_HIDE_LATENCY_SETTINGS + Hide advanced latency settings + true + + + MEM_DDRT_PWR_MODE + DIMM Power Mode + DDRT_PWR_MODE_12W + + + MEM_DDRT_BL_ENUM + Burst Length + DDRT_BL_BL8 + + + MEM_DDRT_BT_ENUM + Read Burst Type + DDRT_BT_SEQUENTIAL + + + MEM_DDRT_TCL + Memory CAS latency setting + 15 + + + MEM_DDRT_RTT_NOM_ENUM + ODT Rtt nominal value + DDRT_RTT_NOM_RZQ_4 + + + MEM_DDRT_DLL_EN + Enable the DLL in memory device + true + + + MEM_DDRT_ATCL_ENUM + Memory additive CAS latency setting + DDRT_ATCL_DISABLED + + + MEM_DDRT_DRV_STR_ENUM + Output drive strength setting + DDRT_DRV_STR_RZQ_7 + + + MEM_DDRT_ASR_ENUM + Auto self-refresh method + DDRT_ASR_MANUAL_NORMAL + + + MEM_DDRT_RTT_WR_ENUM + Dynamic ODT (Rtt_WR) value + DDRT_RTT_WR_ODT_DISABLED + + + MEM_DDRT_WTCL + Memory write CAS latency setting + 18 + + + MEM_DDRT_WRITE_CRC + Write CRC enable + false + + + MEM_DDRT_GEARDOWN + DDRT geardown mode + DDRT_GEARDOWN_HR + + + MEM_DDRT_PER_DRAM_ADDR + Per-DRAM addressability + false + + + MEM_DDRT_TEMP_SENSOR_READOUT + Temperature sensor readout + false + + + MEM_DDRT_FINE_GRANULARITY_REFRESH + Fine granularity refresh + DDRT_FINE_REFRESH_FIXED_1X + + + MEM_DDRT_MPR_READ_FORMAT + MPR read format + DDRT_MPR_READ_FORMAT_SERIAL + + + MEM_DDRT_MAX_POWERDOWN + Maximum power down mode + false + + + MEM_DDRT_TEMP_CONTROLLED_RFSH_RANGE + Temperature controlled refresh range + DDRT_TEMP_CONTROLLED_RFSH_NORMAL + + + MEM_DDRT_TEMP_CONTROLLED_RFSH_ENA + Temperature controlled refresh enable + false + + + MEM_DDRT_INTERNAL_VREFDQ_MONITOR + Internal VrefDQ monitor + false + + + MEM_DDRT_CAL_MODE + CS to Addr/CMD Latency + 0 + + + MEM_DDRT_SELF_RFSH_ABORT + Self refresh abort + false + + + MEM_DDRT_READ_PREAMBLE_TRAINING + Read preamble training mode enable + false + + + MEM_DDRT_DEFAULT_PREAMBLE + Use recommended preamble settings + true + + + MEM_DDRT_USER_READ_PREAMBLE + Read preamble + 1 + + + MEM_DDRT_USER_WRITE_PREAMBLE + Write preamble + 1 + + + MEM_DDRT_AC_PARITY_LATENCY + Addr/CMD parity latency + DDRT_AC_PARITY_LATENCY_DISABLE + + + MEM_DDRT_ODT_IN_POWERDOWN + ODT input buffer during powerdown mode + true + + + MEM_DDRT_RTT_PARK + CTT PARK + DDRT_RTT_PARK_ODT_DISABLED + + + MEM_DDRT_AC_PERSISTENT_ERROR + Addr/CMD persistent error + false + + + MEM_DDRT_WRITE_DBI + Write DBI + false + + + MEM_DDRT_READ_DBI + Read DBI + false + + + MEM_DDRT_PARTIAL_WRITES + Partial Writes + false + + + MEM_DDRT_DEFAULT_VREFOUT + Use recommended initial VrefDQ value + true + + + MEM_DDRT_USER_VREFDQ_TRAINING_VALUE + VrefDQ training value + 56.0 + + + MEM_DDRT_USER_VREFDQ_TRAINING_RANGE + VrefDQ training range + DDRT_VREFDQ_TRAINING_RANGE_1 + + + MEM_DDRT_DEFAULT_ADDED_LATENCY + Use recommended additional latency settings + true + + + MEM_DDRT_USER_TCL_ADDED + Additional CAS latency at PHY + 0 + + + MEM_DDRT_USER_WTCL_ADDED + Additional write CAS latency at PHY + 6 + + + MEM_DDRT_RCD_CA_IBT_ENUM + RCD CA Input Bus Termination + DDRT_RCD_CA_IBT_100 + + + MEM_DDRT_RCD_CS_IBT_ENUM + RCD DCS[3:0]_n Input Bus Termination + DDRT_RCD_CS_IBT_100 + + + MEM_DDRT_RCD_CKE_IBT_ENUM + RCD DCKE Input Bus Termination + DDRT_RCD_CKE_IBT_100 + + + MEM_DDRT_RCD_ODT_IBT_ENUM + RCD DODT Input Bus Termination + DDRT_RCD_ODT_IBT_100 + + + MEM_DDRT_DB_RTT_NOM_ENUM + DB Host Interface DQ RTT_NOM + DDRT_DB_RTT_NOM_ODT_DISABLED + + + MEM_DDRT_DB_RTT_WR_ENUM + DB Host Interface DQ RTT_WR + DDRT_DB_RTT_WR_RZQ_4 + + + MEM_DDRT_DB_RTT_PARK_ENUM + DB Host Interface DQ RTT_PARK + DDRT_DB_RTT_PARK_ODT_DISABLED + + + MEM_DDRT_DB_DQ_DRV_ENUM + DB Host Interface DQ Driver + DDRT_DB_DRV_STR_RZQ_7 + + + MEM_DDRT_SPD_137_RCD_CA_DRV + SPD Byte 137 - RCD Drive Strength for Command/Address + 85 + + + MEM_DDRT_SPD_138_RCD_CK_DRV + SPD Byte 138 - RCD Drive Strength for CK + 5 + + + MEM_DDRT_SPD_140_DRAM_VREFDQ_R0 + SPD Byte 140 - DRAM VrefDQ for Package Rank 0 + 29 + + + MEM_DDRT_SPD_141_DRAM_VREFDQ_R1 + SPD Byte 141 - DRAM VrefDQ for Package Rank 1 + 29 + + + MEM_DDRT_SPD_142_DRAM_VREFDQ_R2 + SPD Byte 142 - DRAM VrefDQ for Package Rank 2 + 29 + + + MEM_DDRT_SPD_143_DRAM_VREFDQ_R3 + SPD Byte 143 - DRAM VrefDQ for Package Rank 3 + 29 + + + MEM_DDRT_SPD_144_DB_VREFDQ + SPD Byte 144 - DB VrefDQ for DRAM Interface + 25 + + + MEM_DDRT_SPD_145_DB_MDQ_DRV + SPD Byte 145-147 - DB MDQ Drive Strength and RTT + 21 + + + MEM_DDRT_SPD_148_DRAM_DRV + SPD Byte 148 - DRAM Drive Strength + 0 + + + MEM_DDRT_SPD_149_DRAM_RTT_WR_NOM + SPD Byte 149-151 - DRAM ODT (RTT_WR and RTT_NOM) + 20 + + + MEM_DDRT_SPD_152_DRAM_RTT_PARK + SPD Byte 152-154 - DRAM ODT (RTT_PARK) + 39 + + + MEM_DDRT_SPD_133_RCD_DB_VENDOR_LSB + RCD and DB Manufacturer (LSB) + 0 + + + MEM_DDRT_SPD_134_RCD_DB_VENDOR_MSB + RCD and DB Manufacturer (MSB) + 0 + + + MEM_DDRT_SPD_135_RCD_REV + RCD Revision Number + 0 + + + MEM_DDRT_SPD_139_DB_REV + DB Revision Number + 0 + + + MEM_DDRT_LRDIMM_ODT_LESS_BS + PARAM_MEM_DDRT_LRDIMM_ODT_LESS_BS_NAME + false + + + MEM_DDRT_LRDIMM_ODT_LESS_BS_PARK_OHM + PARAM_MEM_DDRT_LRDIMM_ODT_LESS_BS_PARK_OHM_NAME + 240 + + + MEM_DDRT_I2C_DIMM_0_SA + I2C SA Value for DIMM 0 + 0 + + + MEM_DDRT_I2C_DIMM_1_SA + I2C SA Value for DIMM 1 + 1 + + + MEM_DDRT_I2C_DIMM_2_SA + I2C SA Value for DIMM 2 + 2 + + + MEM_DDRT_I2C_DIMM_3_SA + I2C SA Value for DIMM 3 + 3 + + + MEM_DDRT_PERSISTENT_MODE + Persistent Mode + 1 + + + MEM_DDRT_USE_DEFAULT_ODT + Use Default ODT Assertion Tables + true + + + MEM_DDRT_R_ODTN_1X1 + Read Target + Rank 0 + + + MEM_DDRT_R_ODT0_1X1 + ODT0 + off + + + MEM_DDRT_W_ODTN_1X1 + Write Target + Rank 0 + + + MEM_DDRT_W_ODT0_1X1 + ODT0 + on + + + MEM_DDRT_R_ODTN_2X2 + Read Target + Rank 0,Rank 1 + + + MEM_DDRT_R_ODT0_2X2 + ODT0 + off,off + + + MEM_DDRT_R_ODT1_2X2 + ODT1 + off,off + + + MEM_DDRT_W_ODTN_2X2 + Write Target + Rank 0,Rank 1 + + + MEM_DDRT_W_ODT0_2X2 + ODT0 + on,off + + + MEM_DDRT_W_ODT1_2X2 + ODT1 + off,on + + + MEM_DDRT_R_ODTN_4X2 + Read Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_R_ODT0_4X2 + ODT0 + off,off,on,on + + + MEM_DDRT_R_ODT1_4X2 + ODT1 + on,on,off,off + + + MEM_DDRT_W_ODTN_4X2 + Write Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_W_ODT0_4X2 + ODT0 + off,off,on,on + + + MEM_DDRT_W_ODT1_4X2 + ODT1 + on,on,off,off + + + MEM_DDRT_R_ODTN_4X4 + Read Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_R_ODT0_4X4 + ODT0 + off,off,off,off + + + MEM_DDRT_R_ODT1_4X4 + ODT1 + off,off,on,on + + + MEM_DDRT_R_ODT2_4X4 + ODT2 + off,off,off,off + + + MEM_DDRT_R_ODT3_4X4 + ODT3 + on,on,off,off + + + MEM_DDRT_W_ODTN_4X4 + Write Target + Rank 0,Rank 1,Rank 2,Rank 3 + + + MEM_DDRT_W_ODT0_4X4 + ODT0 + on,on,off,off + + + MEM_DDRT_W_ODT1_4X4 + ODT1 + off,off,on,on + + + MEM_DDRT_W_ODT2_4X4 + ODT2 + off,off,on,on + + + MEM_DDRT_W_ODT3_4X4 + ODT3 + on,on,off,off + + + MEM_DDRT_SPEEDBIN_ENUM + Speed bin + DDRT_SPEEDBIN_2400 + + + MEM_DDRT_TIS_PS + tIS (base) + 60 + + + MEM_DDRT_TIS_AC_MV + tIS (base) AC level + 100 + + + MEM_DDRT_TIH_PS + tIH (base) + 95 + + + MEM_DDRT_TIH_DC_MV + tIH (base) DC level + 75 + + + MEM_DDRT_TDIVW_TOTAL_UI + TdiVW_total + 0.2 + + + MEM_DDRT_VDIVW_TOTAL + VdiVW_total + 136 + + + MEM_DDRT_TDQSQ_UI + tDQSQ + 0.16 + + + MEM_DDRT_TQH_UI + tQH + 0.76 + + + MEM_DDRT_TDVWP_UI + tDVWp + 0.72 + + + MEM_DDRT_TDQSCK_PS + tDQSCK + 165 + + + MEM_DDRT_TDQSS_CYC + tDQSS + 0.27 + + + MEM_DDRT_TQSH_CYC + tQSH + 0.38 + + + MEM_DDRT_TDSH_CYC + tDSH + 0.18 + + + MEM_DDRT_TDSS_CYC + tDSS + 0.18 + + + MEM_DDRT_TWLS_CYC + tWLS + 0.13 + + + MEM_DDRT_TWLH_CYC + tWLH + 0.13 + + + MEM_DDRT_TINIT_US + tINIT + 500 + + + MEM_DDRT_TMRD_CK_CYC + tMRD + 8 + + + MEM_DDRT_TRAS_NS + tRAS + 32.0 + + + MEM_DDRT_TRCD_NS + tRCD + 15.0 + + + MEM_DDRT_TRP_NS + tRP + 15.0 + + + MEM_DDRT_TREFI_US + tREFI + 7.8 + + + MEM_DDRT_TRFC_NS + tRFC + 260.0 + + + MEM_DDRT_TWR_NS + tWR + 15.0 + + + MEM_DDRT_TWTR_L_CYC + tWTR_L + 9 + + + MEM_DDRT_TWTR_S_CYC + tWTR_S + 3 + + + MEM_DDRT_TFAW_NS + tFAW + 21.0 + + + MEM_DDRT_TRRD_L_CYC + tRRD_L + 6 + + + MEM_DDRT_TRRD_S_CYC + tRRD_S + 4 + + + MEM_DDRT_TCCD_L_CYC + tCCD_L + 6 + + + MEM_DDRT_TCCD_S_CYC + tCCD_S + 4 + + + MEM_DDRT_TRFC_DLR_NS + tRFC_dlr + 90.0 + + + MEM_DDRT_TFAW_DLR_CYC + tFAW_dlr + 16 + + + MEM_DDRT_TRRD_DLR_CYC + tRRD_dlr + 4 + + + MEM_DDRT_TDIVW_DJ_CYC + PARAM_MEM_DDRT_TDIVW_DJ_CYC_NAME + 0.1 + + + MEM_DDRT_TDQSQ_PS + PARAM_MEM_DDRT_TDQSQ_PS_NAME + 66 + + + MEM_DDRT_TQH_CYC + PARAM_MEM_DDRT_TQH_CYC_NAME + 0.38 + + + MEM_DDRT_CFG_GEN_SBE + PARAM_MEM_DDRT_CFG_GEN_SBE_NAME + false + + + MEM_DDRT_CFG_GEN_DBE + PARAM_MEM_DDRT_CFG_GEN_DBE_NAME + false + + + MEM_DDRT_LRDIMM_VREFDQ_VALUE + PARAM_MEM_DDRT_LRDIMM_VREFDQ_VALUE_NAME + + + + MEM_DDRT_TWLS_PS + PARAM_MEM_DDRT_TWLS_PS_NAME + 0.0 + + + MEM_DDRT_TWLH_PS + PARAM_MEM_DDRT_TWLH_PS_NAME + 0.0 + + + BOARD_DDR3_USE_DEFAULT_SLEW_RATES + Use default slew rates + true + + + BOARD_DDR3_USE_DEFAULT_ISI_VALUES + Use default ISI/crosstalk values + true + + + BOARD_DDR3_USER_CK_SLEW_RATE + CK/CK# slew rate (Differential) + 4.0 + + + BOARD_DDR3_USER_AC_SLEW_RATE + Address and command slew rate + 2.0 + + + BOARD_DDR3_USER_RCLK_SLEW_RATE + Read DQS/DQS# slew rate (Differential) + 5.0 + + + BOARD_DDR3_USER_WCLK_SLEW_RATE + Write DQS/DQS# slew rate (Differential) + 4.0 + + + BOARD_DDR3_USER_RDATA_SLEW_RATE + Read DQ slew rate + 2.5 + + + BOARD_DDR3_USER_WDATA_SLEW_RATE + Write DQ slew rate + 2.0 + + + BOARD_DDR3_USER_AC_ISI_NS + Address and command ISI/crosstalk + 0.0 + + + BOARD_DDR3_USER_RCLK_ISI_NS + Read DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_DDR3_USER_WCLK_ISI_NS + Write DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_DDR3_USER_RDATA_ISI_NS + Read DQ ISI/crosstalk + 0.0 + + + BOARD_DDR3_USER_WDATA_ISI_NS + Write DQ ISI/crosstalk + 0.0 + + + BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED + Package deskewed with board layout (DQS group) + false + + + BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS + Maximum board skew within DQS group + 0.02 + + + BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS + Maximum system skew within DQS group + 0.02 + + + BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED + Package deskewed with board layout (address/command bus) + true + + + BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS + Maximum board skew within address/command bus + 0.02 + + + BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS + Maximum system skew within address/command bus + 0.02 + + + BOARD_DDR3_DQS_TO_CK_SKEW_NS + Average delay difference between DQS and CK + 0.02 + + + BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS + Maximum delay difference between DIMMs/devices + 0.05 + + + BOARD_DDR3_SKEW_BETWEEN_DQS_NS + Maximum skew between DQS groups + 0.02 + + + BOARD_DDR3_AC_TO_CK_SKEW_NS + Average delay difference between address/command and CK + 0.0 + + + BOARD_DDR3_MAX_CK_DELAY_NS + Maximum CK delay to DIMM/device + 0.6 + + + BOARD_DDR3_MAX_DQS_DELAY_NS + Maximum DQS delay to DIMM/device + 0.6 + + + BOARD_DDR4_USE_DEFAULT_SLEW_RATES + Use default slew rates + true + + + BOARD_DDR4_USE_DEFAULT_ISI_VALUES + Use default ISI/crosstalk values + true + + + BOARD_DDR4_USER_CK_SLEW_RATE + CK/CK# slew rate (Differential) + 4.0 + + + BOARD_DDR4_USER_AC_SLEW_RATE + Address and command slew rate + 2.0 + + + BOARD_DDR4_USER_RCLK_SLEW_RATE + Read DQS/DQS# slew rate (Differential) + 8.0 + + + BOARD_DDR4_USER_WCLK_SLEW_RATE + Write DQS/DQS# slew rate (Differential) + 4.0 + + + BOARD_DDR4_USER_RDATA_SLEW_RATE + Read DQ slew rate + 4.0 + + + BOARD_DDR4_USER_WDATA_SLEW_RATE + Write DQ slew rate + 2.0 + + + BOARD_DDR4_USER_AC_ISI_NS + Address and command ISI/crosstalk + 0.0 + + + BOARD_DDR4_USER_RCLK_ISI_NS + Read DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_DDR4_USER_WCLK_ISI_NS + Write DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_DDR4_USER_RDATA_ISI_NS + Read DQ ISI/crosstalk + 0.0 + + + BOARD_DDR4_USER_WDATA_ISI_NS + Write DQ ISI/crosstalk + 0.0 + + + BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED + Package deskewed with board layout (DQS group) + true + + + BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS + Maximum board skew within DQS group + 0.02 + + + BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS + Maximum system skew within DQS group + 0.02 + + + BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED + Package deskewed with board layout (address/command bus) + false + + + BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS + Maximum board skew within address/command bus + 0.02 + + + BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS + Maximum system skew within address/command bus + 0.02 + + + BOARD_DDR4_DQS_TO_CK_SKEW_NS + Average delay difference between DQS and CK + 0.02 + + + BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS + Maximum delay difference between DIMMs/devices + 0.05 + + + BOARD_DDR4_SKEW_BETWEEN_DQS_NS + Maximum skew between DQS groups + 0.02 + + + BOARD_DDR4_AC_TO_CK_SKEW_NS + Average delay difference between address/command and CK + 0.0 + + + BOARD_DDR4_MAX_CK_DELAY_NS + Maximum CK delay to DIMM/device + 0.6 + + + BOARD_DDR4_MAX_DQS_DELAY_NS + Maximum DQS delay to DIMM/device + 0.6 + + + BOARD_QDR2_USE_DEFAULT_SLEW_RATES + Use default slew rates + true + + + BOARD_QDR2_USE_DEFAULT_ISI_VALUES + Use default ISI/crosstalk values + true + + + BOARD_QDR2_USER_K_SLEW_RATE + K/K# slew rate (Differential) + 4.0 + + + BOARD_QDR2_USER_AC_SLEW_RATE + Address and command slew rate + 2.0 + + + BOARD_QDR2_USER_RCLK_SLEW_RATE + CQ/CQ# slew rate (Complementary) + 4.0 + + + BOARD_QDR2_USER_RDATA_SLEW_RATE + Read Q slew rate + 2.0 + + + BOARD_QDR2_USER_WDATA_SLEW_RATE + Write D slew rate + 2.0 + + + BOARD_QDR2_USER_AC_ISI_NS + Address and command ISI/crosstalk + 0.0 + + + BOARD_QDR2_USER_RCLK_ISI_NS + CQ/CQ# ISI/crosstalk + 0.0 + + + BOARD_QDR2_USER_WCLK_ISI_NS + K/K# ISI/crosstalk + 0.0 + + + BOARD_QDR2_USER_RDATA_ISI_NS + Read Q ISI/crosstalk + 0.0 + + + BOARD_QDR2_USER_WDATA_ISI_NS + Write D ISI/crosstalk + 0.0 + + + BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED + Package deskewed with board layout (Q group) + false + + + BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED + Package deskewed with board layout (D group) + false + + + BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED + Package deskewed with board layout (address/command bus) + true + + + BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS + Maximum board skew within Q group + 0.02 + + + BOARD_QDR2_BRD_SKEW_WITHIN_D_NS + Maximum board skew within D group + 0.02 + + + BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS + Maximum board skew within address/command bus + 0.02 + + + BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS + Maximum system skew within Q group + 0.02 + + + BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS + Maximum system skew within D group + 0.02 + + + BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS + Maximum system skew within address/command bus + 0.02 + + + BOARD_QDR2_AC_TO_K_SKEW_NS + Average delay difference between address/command and K + 0.0 + + + BOARD_QDR2_MAX_K_DELAY_NS + Maximum K delay to device + 0.6 + + + BOARD_QDR4_USE_DEFAULT_SLEW_RATES + Use default slew rates + true + + + BOARD_QDR4_USE_DEFAULT_ISI_VALUES + Use default ISI/crosstalk values + true + + + BOARD_QDR4_USER_CK_SLEW_RATE + CK/CK# slew rate (Differential) + 4.0 + + + BOARD_QDR4_USER_AC_SLEW_RATE + Address and command slew rate + 2.0 + + + BOARD_QDR4_USER_RCLK_SLEW_RATE + QK/QK# slew rate (Differential) + 5.0 + + + BOARD_QDR4_USER_WCLK_SLEW_RATE + DK/DK# slew rate (Differential) + 4.0 + + + BOARD_QDR4_USER_RDATA_SLEW_RATE + Read DQ slew rate + 2.5 + + + BOARD_QDR4_USER_WDATA_SLEW_RATE + Write DQ slew rate + 2.0 + + + BOARD_QDR4_USER_AC_ISI_NS + Address and command ISI/crosstalk + 0.0 + + + BOARD_QDR4_USER_RCLK_ISI_NS + QK/QK# ISI/crosstalk + 0.0 + + + BOARD_QDR4_USER_WCLK_ISI_NS + DK/DK# ISI/crosstalk + 0.0 + + + BOARD_QDR4_USER_RDATA_ISI_NS + Read DQ ISI/crosstalk + 0.0 + + + BOARD_QDR4_USER_WDATA_ISI_NS + Write DQ ISI/crosstalk + 0.0 + + + BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED + Package deskewed with board layout (QK group) + true + + + BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS + Maximum board skew within QK group + 0.02 + + + BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS + Maximum system skew within QK group + 0.02 + + + BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED + Package deskewed with board layout (address/command bus) + true + + + BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS + Maximum board skew within address/command bus + 0.02 + + + BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS + Maximum system skew within address/command bus + 0.02 + + + BOARD_QDR4_DK_TO_CK_SKEW_NS + Average delay difference between DK and CK + -0.02 + + + BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS + Maximum delay difference between devices + 0.05 + + + BOARD_QDR4_SKEW_BETWEEN_DK_NS + Maximum skew between DK groups + 0.02 + + + BOARD_QDR4_AC_TO_CK_SKEW_NS + Average delay difference between address/command and CK + 0.0 + + + BOARD_QDR4_MAX_CK_DELAY_NS + Maximum CK delay to device + 0.6 + + + BOARD_QDR4_MAX_DK_DELAY_NS + Maximum DK delay to device + 0.6 + + + BOARD_RLD3_USE_DEFAULT_SLEW_RATES + Use default slew rates + true + + + BOARD_RLD3_USE_DEFAULT_ISI_VALUES + Use default ISI/crosstalk values + true + + + BOARD_RLD3_USER_CK_SLEW_RATE + CK/CK# slew rate (Differential) + 4.0 + + + BOARD_RLD3_USER_AC_SLEW_RATE + Address and command slew rate + 2.0 + + + BOARD_RLD3_USER_RCLK_SLEW_RATE + QK/QK# slew rate (Differential) + 7.0 + + + BOARD_RLD3_USER_WCLK_SLEW_RATE + DK/DK# slew rate (Differential) + 4.0 + + + BOARD_RLD3_USER_RDATA_SLEW_RATE + Read DQ slew rate + 3.5 + + + BOARD_RLD3_USER_WDATA_SLEW_RATE + Write DQ slew rate + 2.0 + + + BOARD_RLD3_USER_AC_ISI_NS + Address and command ISI/crosstalk + 0.0 + + + BOARD_RLD3_USER_RCLK_ISI_NS + QK/QK# ISI/crosstalk + 0.0 + + + BOARD_RLD3_USER_WCLK_ISI_NS + DK/DK# ISI/crosstalk + 0.0 + + + BOARD_RLD3_USER_RDATA_ISI_NS + Read DQ ISI/crosstalk + 0.0 + + + BOARD_RLD3_USER_WDATA_ISI_NS + Write DQ ISI/crosstalk + 0.0 + + + BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED + Package deskewed with board layout (QK group) + false + + + BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS + Maximum board skew within QK group + 0.02 + + + BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS + Maximum system skew within QK group + 0.02 + + + BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED + Package deskewed with board layout (address/command bus) + true + + + BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS + Maximum board skew within address/command bus + 0.02 + + + BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS + Maximum system skew within address/command bus + 0.02 + + + BOARD_RLD3_DK_TO_CK_SKEW_NS + Average delay difference between DK and CK + -0.02 + + + BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS + Maximum delay difference between devices + 0.05 + + + BOARD_RLD3_SKEW_BETWEEN_DK_NS + Maximum skew between DK groups + 0.02 + + + BOARD_RLD3_AC_TO_CK_SKEW_NS + Average delay difference between address/command and CK + 0.0 + + + BOARD_RLD3_MAX_CK_DELAY_NS + Maximum CK delay to device + 0.6 + + + BOARD_RLD3_MAX_DK_DELAY_NS + Maximum DK delay to device + 0.6 + + + BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES + PARAM_BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES_NAME + true + + + BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES + Use default ISI/crosstalk values + true + + + BOARD_LPDDR3_USER_CK_SLEW_RATE + PARAM_BOARD_LPDDR3_USER_CK_SLEW_RATE_NAME + 4.0 + + + BOARD_LPDDR3_USER_AC_SLEW_RATE + PARAM_BOARD_LPDDR3_USER_AC_SLEW_RATE_NAME + 2.0 + + + BOARD_LPDDR3_USER_RCLK_SLEW_RATE + PARAM_BOARD_LPDDR3_USER_RCLK_SLEW_RATE_NAME + 4.0 + + + BOARD_LPDDR3_USER_WCLK_SLEW_RATE + PARAM_BOARD_LPDDR3_USER_WCLK_SLEW_RATE_NAME + 4.0 + + + BOARD_LPDDR3_USER_RDATA_SLEW_RATE + PARAM_BOARD_LPDDR3_USER_RDATA_SLEW_RATE_NAME + 2.0 + + + BOARD_LPDDR3_USER_WDATA_SLEW_RATE + PARAM_BOARD_LPDDR3_USER_WDATA_SLEW_RATE_NAME + 2.0 + + + BOARD_LPDDR3_USER_AC_ISI_NS + Address and command ISI/crosstalk + 0.0 + + + BOARD_LPDDR3_USER_RCLK_ISI_NS + Read DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_LPDDR3_USER_WCLK_ISI_NS + Write DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_LPDDR3_USER_RDATA_ISI_NS + Read DQ ISI/crosstalk + 0.0 + + + BOARD_LPDDR3_USER_WDATA_ISI_NS + Write DQ ISI/crosstalk + 0.0 + + + BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED + Package deskewed with board layout (DQS group) + false + + + BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS + Maximum board skew within DQS group + 0.02 + + + BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS + Maximum system skew within DQS group + 0.02 + + + BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED + Package deskewed with board layout (address/command bus) + true + + + BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS + Maximum board skew within address/command bus + 0.02 + + + BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS + Maximum system skew within address/command bus + 0.02 + + + BOARD_LPDDR3_DQS_TO_CK_SKEW_NS + Average delay difference between DQS and CK + 0.02 + + + BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS + Maximum delay difference between devices + 0.05 + + + BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS + Maximum skew between DQS groups + 0.02 + + + BOARD_LPDDR3_AC_TO_CK_SKEW_NS + Average delay difference between address/command and CK + 0.0 + + + BOARD_LPDDR3_MAX_CK_DELAY_NS + Maximum CK delay to device + 0.6 + + + BOARD_LPDDR3_MAX_DQS_DELAY_NS + Maximum DQS delay to device + 0.6 + + + BOARD_DDRT_USE_DEFAULT_SLEW_RATES + Use default slew rates + true + + + BOARD_DDRT_USE_DEFAULT_ISI_VALUES + Use default ISI/crosstalk values + true + + + BOARD_DDRT_USER_CK_SLEW_RATE + CK/CK# slew rate (Differential) + 4.0 + + + BOARD_DDRT_USER_AC_SLEW_RATE + Address and command slew rate + 2.0 + + + BOARD_DDRT_USER_RCLK_SLEW_RATE + Read DQS/DQS# slew rate (Differential) + 8.0 + + + BOARD_DDRT_USER_WCLK_SLEW_RATE + Write DQS/DQS# slew rate (Differential) + 4.0 + + + BOARD_DDRT_USER_RDATA_SLEW_RATE + Read DQ slew rate + 4.0 + + + BOARD_DDRT_USER_WDATA_SLEW_RATE + Write DQ slew rate + 2.0 + + + BOARD_DDRT_USER_AC_ISI_NS + Address and command ISI/crosstalk + 0.0 + + + BOARD_DDRT_USER_RCLK_ISI_NS + Read DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_DDRT_USER_WCLK_ISI_NS + Write DQS/DQS# ISI/crosstalk + 0.0 + + + BOARD_DDRT_USER_RDATA_ISI_NS + Read DQ ISI/crosstalk + 0.0 + + + BOARD_DDRT_USER_WDATA_ISI_NS + Write DQ ISI/crosstalk + 0.0 + + + BOARD_DDRT_IS_SKEW_WITHIN_DQS_DESKEWED + Package deskewed with board layout (DQS group) + true + + + BOARD_DDRT_BRD_SKEW_WITHIN_DQS_NS + Maximum board skew within DQS group + 0.02 + + + BOARD_DDRT_PKG_BRD_SKEW_WITHIN_DQS_NS + Maximum system skew within DQS group + 0.02 + + + BOARD_DDRT_IS_SKEW_WITHIN_AC_DESKEWED + Package deskewed with board layout (address/command bus) + false + + + BOARD_DDRT_BRD_SKEW_WITHIN_AC_NS + Maximum board skew within address/command bus + 0.02 + + + BOARD_DDRT_PKG_BRD_SKEW_WITHIN_AC_NS + Maximum system skew within address/command bus + 0.02 + + + BOARD_DDRT_DQS_TO_CK_SKEW_NS + Average delay difference between DQS and CK + 0.02 + + + BOARD_DDRT_SKEW_BETWEEN_DIMMS_NS + Maximum delay difference between DIMMs/devices + 0.05 + + + BOARD_DDRT_SKEW_BETWEEN_DQS_NS + Maximum skew between DQS groups + 0.02 + + + BOARD_DDRT_AC_TO_CK_SKEW_NS + Average delay difference between address/command and CK + 0.0 + + + BOARD_DDRT_MAX_CK_DELAY_NS + Maximum CK delay to DIMM/device + 0.6 + + + BOARD_DDRT_MAX_DQS_DELAY_NS + Maximum DQS delay to DIMM/device + 0.6 + + + CTRL_DDR3_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_DDR3_SELF_REFRESH_EN + Enable Self-Refresh Control + false + + + CTRL_DDR3_AUTO_POWER_DOWN_EN + Enable Auto Power-Down + false + + + CTRL_DDR3_AUTO_POWER_DOWN_CYCS + Auto Power-Down Cycles + 32 + + + CTRL_DDR3_USER_REFRESH_EN + Enable User Refresh Control + false + + + CTRL_DDR3_USER_PRIORITY_EN + Enable Command Priority Control + false + + + CTRL_DDR3_AUTO_PRECHARGE_EN + Enable Auto-Precharge Control + false + + + CTRL_DDR3_ADDR_ORDER_ENUM + Address Ordering + DDR3_CTRL_ADDR_ORDER_CS_R_B_C + + + CTRL_DDR3_ECC_EN + Enable Error Detection and Correction Logic with ECC + false + + + CTRL_DDR3_ECC_AUTO_CORRECTION_EN + Enable Auto Error Correction to External Memory + false + + + CTRL_DDR3_ECC_READDATAERROR_EN + Enable ctrl_ecc_readdataerror signal to indicate uncorrectable data errors + false + + + CTRL_DDR3_ECC_STATUS_EN + Export error-correction code (ECC) status ports + false + + + CTRL_DDR3_REORDER_EN + Enable Reordering + true + + + CTRL_DDR3_STARVE_LIMIT + Starvation limit for each command + 10 + + + CTRL_DDR3_MMR_EN + Enable Memory-Mapped Configuration and Status Register (MMR) Interface + false + + + CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (same rank) + 0 + + + CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (same rank) + 0 + + + CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional read-to-read turnaround time (different ranks) + 0 + + + CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (different ranks) + 0 + + + CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional write-to-write turnaround time (different ranks) + 0 + + + CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (different ranks) + 0 + + + CTRL_DDR4_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_DDR4_SELF_REFRESH_EN + Enable Self-Refresh Control + false + + + CTRL_DDR4_AUTO_POWER_DOWN_EN + Enable Auto Power-Down + false + + + CTRL_DDR4_AUTO_POWER_DOWN_CYCS + Auto Power-Down Cycles + 32 + + + CTRL_DDR4_USER_REFRESH_EN + Enable User Refresh Control + false + + + CTRL_DDR4_USER_PRIORITY_EN + Enable Command Priority Control + false + + + CTRL_DDR4_AUTO_PRECHARGE_EN + Enable Auto-Precharge Control + false + + + CTRL_DDR4_ADDR_ORDER_ENUM + Address Ordering + DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG + + + CTRL_DDR4_ECC_EN + Enable Error Detection and Correction Logic with ECC + false + + + CTRL_DDR4_ECC_AUTO_CORRECTION_EN + Enable Auto Error Correction to External Memory + false + + + CTRL_DDR4_ECC_READDATAERROR_EN + Enable ctrl_ecc_readdataerror signal to indicate uncorrectable data errors + false + + + CTRL_DDR4_ECC_STATUS_EN + Export error-correction code (ECC) status ports + false + + + CTRL_DDR4_REORDER_EN + Enable Reordering + true + + + CTRL_DDR4_STARVE_LIMIT + Starvation limit for each command + 10 + + + CTRL_DDR4_MMR_EN + Enable Memory-Mapped Configuration and Status Register (MMR) Interface + false + + + CTRL_DDR4_MAJOR_MODE_EN + Enable controller major mode + false + + + CTRL_DDR4_POST_REFRESH_EN + Enable controller post-pay refresh + true + + + CTRL_DDR4_POST_REFRESH_LOWER_LIMIT + Post-pay refresh lower limit + 0 + + + CTRL_DDR4_POST_REFRESH_UPPER_LIMIT + Post-pay refresh upper limit + 2 + + + CTRL_DDR4_PRE_REFRESH_EN + Enable controller pre-pay refresh + false + + + CTRL_DDR4_PRE_REFRESH_UPPER_LIMIT + Refresh pre-pay upper limit + 1 + + + CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (same rank) + 0 + + + CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (same rank) + 0 + + + CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional read-to-read turnaround time (different ranks) + 0 + + + CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (different ranks) + 0 + + + CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional write-to-write turnaround time (different ranks) + 0 + + + CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (different ranks) + 0 + + + CTRL_QDR2_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_QDR2_AVL_MAX_BURST_COUNT + Maximum Avalon-MM burst length + 4 + + + CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS + Generate power-of-2 data bus widths for Qsys + false + + + CTRL_QDR4_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_QDR4_AVL_MAX_BURST_COUNT + Maximum Avalon-MM burst length + 4 + + + CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS + Generate power-of-2 data bus widths for Qsys + false + + + CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC + Additional read-after-write turnaround time + 0 + + + CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC + Additional write-after-read turnaround time + 0 + + + CTRL_QDR4_DEF_RAW_TURNAROUND_DELAY_CYC + PARAM_CTRL_QDR4_DEF_RAW_TURNAROUND_DELAY_CYC_NAME + 7 + + + CTRL_RLD2_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_RLD3_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_RLD3_ADDR_ORDER_ENUM + Address Ordering + RLD3_CTRL_ADDR_ORDER_CS_R_B_C + + + CTRL_LPDDR3_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_LPDDR3_SELF_REFRESH_EN + Enable Self-Refresh Control + false + + + CTRL_LPDDR3_AUTO_POWER_DOWN_EN + Enable Auto Power-Down + false + + + CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS + Auto Power-Down Cycles + 32 + + + CTRL_LPDDR3_USER_REFRESH_EN + Enable User Refresh Control + false + + + CTRL_LPDDR3_USER_PRIORITY_EN + Enable Command Priority Control + false + + + CTRL_LPDDR3_AUTO_PRECHARGE_EN + Enable Auto-Precharge Control + false + + + CTRL_LPDDR3_ADDR_ORDER_ENUM + Address Ordering + LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C + + + CTRL_LPDDR3_REORDER_EN + Enable Reordering + true + + + CTRL_LPDDR3_STARVE_LIMIT + Starvation limit for each command + 10 + + + CTRL_LPDDR3_MMR_EN + Enable Memory-Mapped Configuration and Status Register (MMR) Interface + false + + + CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (same rank) + 0 + + + CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (same rank) + 0 + + + CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional read-to-read turnaround time (different ranks) + 0 + + + CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (different ranks) + 0 + + + CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional write-to-write turnaround time (different ranks) + 0 + + + CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (different ranks) + 0 + + + CTRL_DDRT_AVL_PROTOCOL_ENUM + Avalon Interface + CTRL_AVL_PROTOCOL_MM + + + CTRL_DDRT_SELF_REFRESH_EN + Enable Self-Refresh Control + false + + + CTRL_DDRT_AUTO_POWER_DOWN_EN + Enable Auto Power-Down + false + + + CTRL_DDRT_AUTO_POWER_DOWN_CYCS + Auto Power-Down Cycles + 32 + + + CTRL_DDRT_USER_REFRESH_EN + Enable User Refresh Control + false + + + CTRL_DDRT_USER_PRIORITY_EN + Enable Command Priority Control + false + + + CTRL_DDRT_AUTO_PRECHARGE_EN + Enable Auto-Precharge Control + false + + + CTRL_DDRT_ADDR_ORDER_ENUM + PARAM_CTRL_DDRT_ADDR_ORDER_ENUM_NAME + DDRT_CTRL_ADDR_ORDER_CS_R_B_C_BG + + + CTRL_DDRT_ECC_EN + Enable Error Detection and Correction Logic with ECC + false + + + CTRL_DDRT_ECC_AUTO_CORRECTION_EN + Enable Auto Error Correction to External Memory + false + + + CTRL_DDRT_ECC_READDATAERROR_EN + Enable ctrl_ecc_readdataerror signal to indicate uncorrectable data errors + true + + + CTRL_DDRT_ECC_STATUS_EN + Export error-correction code (ECC) status ports + true + + + CTRL_DDRT_REORDER_EN + Enable Reordering + true + + + CTRL_DDRT_STARVE_LIMIT + Starvation limit for each command + 10 + + + CTRL_DDRT_MMR_EN + Enable Memory-Mapped Configuration and Status Register (MMR) Interface + false + + + CTRL_DDRT_RD_TO_WR_SAME_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (same rank) + 0 + + + CTRL_DDRT_WR_TO_RD_SAME_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (same rank) + 0 + + + CTRL_DDRT_RD_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional read-to-read turnaround time (different ranks) + 0 + + + CTRL_DDRT_RD_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional read-to-write turnaround time (different ranks) + 0 + + + CTRL_DDRT_WR_TO_RD_DIFF_CHIP_DELTA_CYCS + Additional write-to-read turnaround time (different ranks) + 0 + + + CTRL_DDRT_DIMM_DENSITY + Capacity of Optane DIMM + 128 + + + CTRL_DDRT_NUM_OF_AXIS_ID + Number of AXI masters + 1 + + + CTRL_DDRT_WR_ACK_POLICY + Write Acknowldgement Policy + POSTED + + + CTRL_DDRT_ERR_REPLAY_EN + Replay on Error + false + + + CTRL_DDRT_HOST_VIRAL_FLOW_EN + Host Error Viral + false + + + CTRL_DDRT_DIMM_VIRAL_FLOW_EN + DIMM Error Viral + false + + + CTRL_DDRT_POISON_DETECTION_EN + Error Poison + false + + + CTRL_DDRT_PMM_ADR_FLOW_EN + PMM ADR Flow + false + + + CTRL_DDRT_PMM_WPQ_FLUSH_EN + PMM WPQ Flush + false + + + CTRL_DDRT_UPI_EN + UPI EN + false + + + CTRL_DDRT_UPI_ID_WIDTH + PARAM_CTRL_DDRT_UPI_ID_WIDTH_NAME + 8 + + + CTRL_DDRT_PARITY_CMD_EN + CMD Parity EN + false + + + CTRL_DDRT_ADDR_INTERLEAVING + Address Interleaving + COARSE + + + CTRL_DDRT_PORT_AFI_C_WIDTH + PARAM_CTRL_DDRT_PORT_AFI_C_WIDTH_NAME + 2 + + + CTRL_DDRT_ZQ_INTERVAL_MS + ZQCS command interval + 3 + + + CTRL_DDRT_ERR_INJECT_EN + Error Inject EN + false + + + CTRL_DDRT_EXT_ERR_INJECT_EN + Ext Error Inject EN + false + + + CTRL_DDRT_GNT_TO_WR_SAME_CHIP_DELTA_CYCS + Additional grant to write turnaround time (same DIMM) + 0 + + + CTRL_DDRT_WR_TO_GNT_SAME_CHIP_DELTA_CYCS + Additional write to grant turnaround time (same DIMM) + 0 + + + CTRL_DDRT_GNT_TO_GNT_DIFF_CHIP_DELTA_CYCS + Additional grant to grant turnaround time (different DIMM) + 0 + + + CTRL_DDRT_GNT_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional grant to write turnaround time (different DIMM) + 0 + + + CTRL_DDRT_WR_TO_GNT_DIFF_CHIP_DELTA_CYCS + Additional write to grant turnaround time (different DIMM) + 0 + + + CTRL_DDRT_WR_TO_WR_DIFF_CHIP_DELTA_CYCS + Additional write to write turnaround time (different DIMM) + 0 + + + DIAG_SIM_REGTEST_MODE + Simulation regtest mode + false + + + DIAG_TIMING_REGTEST_MODE + Timing regtest mode + false + + + DIAG_SYNTH_FOR_SIM + Synthesize for simulation + false + + + DIAG_FAST_SIM_OVERRIDE + Fast simulation override + FAST_SIM_OVERRIDE_DEFAULT + + + DIAG_SEQ_RESET_AUTO_RELEASE + PARAM_DIAG_SEQ_RESET_AUTO_RELEASE_NAME + avl + + + DIAG_DB_RESET_AUTO_RELEASE + PARAM_DIAG_DB_RESET_AUTO_RELEASE_NAME + avl_release + + + DIAG_ADD_READY_PIPELINE + Add additional pipeline on the ready/WaitRequest path. + true + + + DIAG_EXPOSE_EARLY_READY + Expose Early Ready + false + + + DIAG_EXPOSE_RD_TYPE + Expose Read Type + false + + + DIAG_VERBOSE_IOAUX + Show verbose IOAUX debug messages + false + + + DIAG_ECLIPSE_DEBUG + Enable Eclipse debugging + false + + + DIAG_EXPORT_VJI + Export Virtual JTAG Interface (VJI) + false + + + DIAG_ENABLE_JTAG_UART + Enable JTAG UART + false + + + DIAG_ENABLE_JTAG_UART_HEX + Enable JTAG UART hexfiles + false + + + DIAG_ENABLE_HPS_EMIF_DEBUG + Enable UART for HPS EMIF Debug + false + + + DIAG_SOFT_NIOS_MODE + Use Soft NIOS Processor for On-Chip Debug + SOFT_NIOS_MODE_DISABLED + + + DIAG_SOFT_NIOS_CLOCK_FREQUENCY + Calibration Processor External Clock Frequency + 100 + + + DIAG_USE_RS232_UART + Use an RS232 UART for Soft NIOS Calibration Processor debug output (requires code change) + false + + + DIAG_RS232_UART_BAUDRATE + RS232 UART Speed + 57600 + + + DIAG_EX_DESIGN_ADD_TEST_EMIFS + Add extra EMIFs to example design + + + + DIAG_EX_DESIGN_SEPARATE_RESETS + Use a separate global reset signal for every interface + false + + + DIAG_EXPOSE_DFT_SIGNALS + Expose test and debug signals + false + + + DIAG_EXTRA_CONFIGS + Extra configuration + TG_TEST_DURATION=MEDIUM + + + DIAG_USE_BOARD_DELAY_MODEL + Use board delay model during simulation + false + + + DIAG_BOARD_DELAY_CONFIG_STR + Board delay model configuration + + + + DIAG_TG_AVL_2_NUM_CFG_INTERFACES + Number of Traffic Generator 2.0 configuration interfaces + 0 + + + DIAG_EXPORT_PLL_REF_CLK_OUT + PARAM_DIAG_EXPORT_PLL_REF_CLK_OUT_NAME + true + + + DIAG_EXPORT_PLL_LOCKED + Export PLL lock signal + true + + + DIAG_HMC_HRC + PARAM_DIAG_HMC_HRC_NAME + auto + + + SHORT_QSYS_INTERFACE_NAMES + Use short Qsys interface names + true + + + DIAG_EXT_DOCS + PARAM_DIAG_EXT_DOCS_NAME + false + + + DIAG_DDR3_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_DDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_DDR3_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + false + + + DIAG_DDR3_INTERFACE_ID + Interface ID + 0 + + + DIAG_DDR3_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_DDR3_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_DDR3_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_DDR3_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_DDR3_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + false + + + DIAG_DDR3_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_DDR3_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_DDR3_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_DDR3_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_DDR3_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_JTAG + + + DIAG_DDR3_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_DDR3_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_DDR3_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + false + + + DIAG_DDR3_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_DDR3_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_DDR3_CA_LEVEL_EN + Enable address/command leveling calibration + false + + + DIAG_DDR3_CA_DESKEW_EN + Enable address/command deskew calibration + true + + + DIAG_DDR3_CAL_ADDR0 + Calibration address 0 + 0 + + + DIAG_DDR3_CAL_ADDR1 + Calibration address 1 + 8 + + + DIAG_DDR3_CAL_ENABLE_NON_DES + Enable refreshes during calibration + false + + + DIAG_DDR3_CAL_FULL_CAL_ON_RESET + Enable automatic calibration after reset + true + + + DIAG_DDR3_CAL_ENABLE_MICRON_AP + Enable Micron Automata Calibration + false + + + DIAG_DDR4_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_DDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_DDR4_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + false + + + DIAG_DDR4_INTERFACE_ID + Interface ID + 0 + + + DIAG_DDR4_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_DDR4_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_DDR4_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_DDR4_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + false + + + DIAG_DDR4_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_DDR4_ABSTRACT_PHY + Abstract phy for fast simulation + true + + + DIAG_DDR4_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_DDR4_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_DDR4_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_JTAG + + + DIAG_DDR4_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_DDR4_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_DDR4_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + false + + + DIAG_DDR4_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_DDR4_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_DDR4_SKIP_CA_LEVEL + Skip address/command leveling calibration + false + + + DIAG_DDR4_SKIP_CA_DESKEW + Skip address/command deskew calibration + false + + + DIAG_DDR4_SKIP_VREF_CAL + Skip VREF calibration + false + + + DIAG_DDR4_SKIP_AC_PARITY_CHECK + Skip address/command parity check during calibration + false + + + DIAG_DDR4_CAL_ADDR0 + Calibration address 0 + 0 + + + DIAG_DDR4_CAL_ADDR1 + Calibration address 1 + 8 + + + DIAG_DDR4_CAL_ENABLE_NON_DES + Enable refreshes during calibration + false + + + DIAG_DDR4_CAL_FULL_CAL_ON_RESET + Enable automatic calibration after reset + true + + + DIAG_QDR2_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_QDR2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_QDR2_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + false + + + DIAG_QDR2_INTERFACE_ID + Interface ID + 0 + + + DIAG_QDR2_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_QDR2_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_QDR2_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_QDR2_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_QDR2_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + false + + + DIAG_QDR2_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_QDR2_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_QDR2_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_QDR2_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_QDR2_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_JTAG + + + DIAG_QDR2_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_QDR2_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_QDR2_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + false + + + DIAG_QDR2_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_QDR2_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_QDR4_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_QDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_QDR4_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + false + + + DIAG_QDR4_INTERFACE_ID + Interface ID + 0 + + + DIAG_QDR4_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_QDR4_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_QDR4_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_QDR4_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_QDR4_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + false + + + DIAG_QDR4_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_QDR4_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_QDR4_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_QDR4_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_QDR4_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_JTAG + + + DIAG_QDR4_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_QDR4_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_QDR4_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + false + + + DIAG_QDR4_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_QDR4_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_QDR4_SKIP_VREF_CAL + Skip VREF_in calibration + false + + + DIAG_RLD2_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_RLD2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_RLD2_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + false + + + DIAG_RLD2_INTERFACE_ID + Interface ID + 0 + + + DIAG_RLD2_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_RLD2_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_RLD2_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_RLD2_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_RLD2_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + false + + + DIAG_RLD2_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_RLD2_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_RLD2_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_RLD2_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_RLD2_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_JTAG + + + DIAG_RLD2_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_RLD2_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_RLD2_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + false + + + DIAG_RLD2_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_RLD2_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_RLD3_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_RLD3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_RLD3_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + false + + + DIAG_RLD3_INTERFACE_ID + Interface ID + 0 + + + DIAG_RLD3_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_RLD3_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_RLD3_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_RLD3_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_RLD3_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + false + + + DIAG_RLD3_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_RLD3_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_RLD3_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_RLD3_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_RLD3_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_JTAG + + + DIAG_RLD3_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_RLD3_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_RLD3_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + true + + + DIAG_RLD3_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_RLD3_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_RLD3_CA_LEVEL_EN + Enable address/command leveling calibration + false + + + DIAG_RLD3_CA_DESKEW_EN + Enable address/command deskew calibration + true + + + DIAG_LPDDR3_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_LPDDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_LPDDR3_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + false + + + DIAG_LPDDR3_INTERFACE_ID + Interface ID + 0 + + + DIAG_LPDDR3_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_LPDDR3_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_LPDDR3_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_LPDDR3_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + false + + + DIAG_LPDDR3_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_LPDDR3_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_LPDDR3_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_LPDDR3_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_LPDDR3_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_JTAG + + + DIAG_LPDDR3_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_LPDDR3_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + false + + + DIAG_LPDDR3_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_LPDDR3_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_LPDDR3_SKIP_CA_LEVEL + Skip address/command leveling calibration + false + + + DIAG_LPDDR3_SKIP_CA_DESKEW + Skip address/command deskew calibration + false + + + DIAG_DDRT_SIM_CAL_MODE_ENUM + Calibration mode + SIM_CAL_MODE_SKIP + + + DIAG_DDRT_EXPORT_SEQ_AVALON_SLAVE + Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + CAL_DEBUG_EXPORT_MODE_DISABLED + + + DIAG_DDRT_EXPORT_SEQ_AVALON_MASTER + Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port + false + + + DIAG_DDRT_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN + First EMIF Instance in the Avalon Chain + true + + + DIAG_DDRT_EX_DESIGN_NUM_OF_SLAVES + Number of core clocks sharing slaves to instantiate in the example design + 1 + + + DIAG_DDRT_EX_DESIGN_ISSP_EN + Enable In-System-Sources-and-Probes + false + + + DIAG_DDRT_INTERFACE_ID + Interface ID + 0 + + + DIAG_DDRT_EFFICIENCY_MONITOR + Efficiency Monitor Mode + EFFMON_MODE_DISABLED + + + DIAG_DDRT_USE_NEW_EFFMON_S10 + Use Efficiency Monitor with Unified Toolkit + false + + + DIAG_DDRT_USER_SIM_MEMORY_PRELOAD + Preload memory + false + + + DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE + Memory preload-data filename for primary interface + EMIF_PRI_PRELOAD.txt + + + DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE + Memory preload-data filename for secondary interface + EMIF_SEC_PRELOAD.txt + + + DIAG_DDRT_USER_USE_SIM_MEMORY_VALIDATION_TG + Use traffic generator to validate memory contents in Example Design simulation + true + + + DIAG_DDRT_USE_TG_AVL_2 + Use configurable Avalon traffic generator 2.0 + true + + + DIAG_DDRT_USE_TG_HBM + PARAM_DIAG_USE_TG_HBM_NAME + false + + + DIAG_DDRT_ABSTRACT_PHY + Abstract phy for fast simulation + false + + + DIAG_DDRT_ENABLE_DEFAULT_MODE + Enable default traffic pattern (pattern configured during compile-time) + false + + + DIAG_DDRT_ENABLE_USER_MODE + Enable user-configured traffic pattern (pattern configured during run-time) + true + + + DIAG_DDRT_EXPORT_TG_CFG_AVALON_SLAVE + TG2 Configuration Interface Mode + TG_CFG_AMM_EXPORT_MODE_JTAG + + + DIAG_DDRT_TG2_TEST_DURATION + TG2 default traffic duration + SHORT + + + DIAG_DDRT_SEPARATE_READ_WRITE_ITFS + PARAM_DIAG_SEPARATE_READ_WRITE_ITFS_NAME + false + + + DIAG_DDRT_DISABLE_AFI_P2C_REGISTERS + Disable P2C Register Stage + false + + + DIAG_DDRT_AC_PARITY_ERR + Export Address/Command parity error indicator + false + + + DIAG_DDRT_EX_DESIGN_SEPARATE_RZQS + PARAM_DIAG_DDRT_EX_DESIGN_SEPARATE_RZQS_NAME + true + + + DIAG_DDRT_SIM_VERBOSE + Show verbose simulation debug messages + true + + + DIAG_DDRT_SKIP_CA_LEVEL + Skip address/command leveling calibration + false + + + DIAG_DDRT_SKIP_CA_DESKEW + Skip address/command deskew calibration + false + + + DIAG_DDRT_SKIP_VREF_CAL + Skip VREF calibration + false + + + DIAG_DDRT_CAL_ADDR0 + PARAM_DIAG_DDRT_CAL_ADDR0_NAME + 0 + + + DIAG_DDRT_CAL_ADDR1 + PARAM_DIAG_DDRT_CAL_ADDR1_NAME + 8 + + + DIAG_DDRT_CAL_ENABLE_NON_DES + PARAM_DIAG_DDRT_CAL_ENABLE_NON_DES_NAME + false + + + DIAG_DDRT_CAL_FULL_CAL_ON_RESET + PARAM_DIAG_DDRT_CAL_FULL_CAL_ON_RESET_NAME + true + + + DIAG_DDRT_ENABLE_ENHANCED_TESTING + Enable enhanced testing + false + + + DIAG_DDRT_ENABLE_DRIVER_MARGINING + Enable driver margining for DDR-T + false + + + DIAG_DDRT_EFF_TEST + PARAM_DIAG_DDRT_EFF_TEST_NAME + false + + + NUM_IPS + Number of IPs + 1 + + + EMIF_0_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_0_STORED_PARAM + PARAM_EMIF_0_STORED_PARAM_NAME + + + + EMIF_0_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_1_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_1_STORED_PARAM + PARAM_EMIF_1_STORED_PARAM_NAME + + + + EMIF_1_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_2_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_2_STORED_PARAM + PARAM_EMIF_2_STORED_PARAM_NAME + + + + EMIF_2_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_3_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_3_STORED_PARAM + PARAM_EMIF_3_STORED_PARAM_NAME + + + + EMIF_3_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_4_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_4_STORED_PARAM + PARAM_EMIF_4_STORED_PARAM_NAME + + + + EMIF_4_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_5_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_5_STORED_PARAM + PARAM_EMIF_5_STORED_PARAM_NAME + + + + EMIF_5_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_6_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_6_STORED_PARAM + PARAM_EMIF_6_STORED_PARAM_NAME + + + + EMIF_6_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_7_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_7_STORED_PARAM + PARAM_EMIF_7_STORED_PARAM_NAME + + + + EMIF_7_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_8_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_8_STORED_PARAM + PARAM_EMIF_8_STORED_PARAM_NAME + + + + EMIF_8_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_9_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_9_STORED_PARAM + PARAM_EMIF_9_STORED_PARAM_NAME + + + + EMIF_9_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_10_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_10_STORED_PARAM + PARAM_EMIF_10_STORED_PARAM_NAME + + + + EMIF_10_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_11_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_11_STORED_PARAM + PARAM_EMIF_11_STORED_PARAM_NAME + + + + EMIF_11_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_12_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_12_STORED_PARAM + PARAM_EMIF_12_STORED_PARAM_NAME + + + + EMIF_12_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_13_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_13_STORED_PARAM + PARAM_EMIF_13_STORED_PARAM_NAME + + + + EMIF_13_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_14_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_14_STORED_PARAM + PARAM_EMIF_14_STORED_PARAM_NAME + + + + EMIF_14_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EMIF_15_CONN_TO_CALIP + Cal-IP + CALIP_0 + + + EMIF_15_STORED_PARAM + PARAM_EMIF_15_STORED_PARAM_NAME + + + + EMIF_15_REF_CLK_SHARING + Ref-Clock + EXPORTED + + + EX_DESIGN_GUI_DDR3_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_DDR3_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_DDR3_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_DDR3_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_DDR3_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_DDR3_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDR3_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDR4_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_DDR4_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_DDR4_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_DDR4_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_DDR4_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_DDR4_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDR4_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR2_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_QDR2_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_QDR2_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_QDR2_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_QDR2_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_QDR2_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR2_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR4_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_QDR4_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_QDR4_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_QDR4_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_QDR4_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_QDR4_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_QDR4_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD2_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_RLD2_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_RLD2_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_RLD2_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_RLD2_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_RLD2_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD2_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD3_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_RLD3_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_RLD3_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_RLD3_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_RLD3_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_RLD3_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_RLD3_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_LPDDR3_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_LPDDR3_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_LPDDR3_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_LPDDR3_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_LPDDR3_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_LPDDR3_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_LPDDR3_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDRT_SEL_DESIGN + Select design + AVAIL_EX_DESIGNS_GEN_DESIGN + + + EX_DESIGN_GUI_DDRT_GEN_SIM + Simulation + true + + + EX_DESIGN_GUI_DDRT_GEN_SYNTH + Synthesis + true + + + EX_DESIGN_GUI_DDRT_GEN_BSI + Signal Integrity + false + + + EX_DESIGN_GUI_DDRT_GEN_CDC + Spyglass CDC + false + + + EX_DESIGN_GUI_DDRT_HDL_FORMAT + Simulation HDL format + HDL_FORMAT_VERILOG + + + EX_DESIGN_GUI_DDRT_TARGET_DEV_KIT + Select board + TARGET_DEV_KIT_NONE + + + EX_DESIGN_GUI_DDRT_PREV_PRESET + PARAM_EX_DESIGN_PREV_PRESET_NAME + TARGET_DEV_KIT_NONE + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element emif_s10_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + true + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>ctrl_amm_0</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>amm_ready_0</name> + <role>waitrequest_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>amm_read_0</name> + <role>read</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>amm_write_0</name> + <role>write</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>amm_address_0</name> + <role>address</role> + <direction>Input</direction> + <width>27</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>amm_readdata_0</name> + <role>readdata</role> + <direction>Output</direction> + <width>576</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>amm_writedata_0</name> + <role>writedata</role> + <direction>Input</direction> + <width>576</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>amm_burstcount_0</name> + <role>burstcount</role> + <direction>Input</direction> + <width>7</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>amm_byteenable_0</name> + <role>byteenable</role> + <direction>Input</direction> + <width>72</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>amm_readdatavalid_0</name> + <role>readdatavalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>DYNAMIC</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>9663676416</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>emif_usr_clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>emif_usr_reset_n</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>true</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>64</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>emif_usr_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>emif_usr_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + </entry> + <entry> + <key>clockRate</key> + <value>300000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>emif_usr_reset_n</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>emif_usr_reset_n</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedDirectReset</key> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>none</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>local_reset_req</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>local_reset_req</name> + <role>local_reset_req</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>local_reset_status</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>local_reset_done</name> + <role>local_reset_done</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>mem</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>mem_ck</name> + <role>mem_ck</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mem_ck_n</name> + <role>mem_ck_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mem_a</name> + <role>mem_a</role> + <direction>Output</direction> + <width>17</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mem_act_n</name> + <role>mem_act_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mem_ba</name> + <role>mem_ba</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mem_bg</name> + <role>mem_bg</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mem_cke</name> + <role>mem_cke</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mem_cs_n</name> + <role>mem_cs_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mem_odt</name> + <role>mem_odt</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mem_reset_n</name> + <role>mem_reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mem_par</name> + <role>mem_par</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mem_alert_n</name> + <role>mem_alert_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mem_dqs</name> + <role>mem_dqs</role> + <direction>Bidir</direction> + <width>9</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mem_dqs_n</name> + <role>mem_dqs_n</role> + <direction>Bidir</direction> + <width>9</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mem_dq</name> + <role>mem_dq</role> + <direction>Bidir</direction> + <width>72</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mem_dbi_n</name> + <role>mem_dbi_n</role> + <direction>Bidir</direction> + <width>9</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>oct</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>oct_rzqin</name> + <role>oct_rzqin</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>pll_locked</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>pll_locked</name> + <role>pll_locked</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>pll_ref_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>pll_ref_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>pll_ref_clk_out</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>pll_ref_clk_out</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + </entry> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>false</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>status</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>local_cal_success</name> + <role>local_cal_success</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>local_cal_fail</name> + <role>local_cal_fail</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>ctrl_amm_0</key> + <value> + <connectionPointName>ctrl_amm_0</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='ctrl_amm_0' start='0x0' end='0x240000000' datawidth='576' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>34</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>576</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>emif_usr_clk</key> + <value> + <connectionPointName>emif_usr_clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>300000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>pll_ref_clk_out</key> + <value> + <connectionPointName>pll_ref_clk_out</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Intel Corporation + addressAndMemoryMap + addressAndMemoryMap + 1.0 + + + arch.ctrl_amm_0 + + + + + + + + + false + false + + \ No newline at end of file diff --git a/ipss/mem/mem_intf.sv b/ipss/mem/mem_intf.sv new file mode 100755 index 0000000..c9b38d6 --- /dev/null +++ b/ipss/mem/mem_intf.sv @@ -0,0 +1,495 @@ +// Copyright 2021 Intel Corporation +// SPDX-License-Identifier: MIT + +// ----------------------------------------------------------------------------- +// Create Date : Jan 2021 +// Module Name : mem_intf_reorder +// Project : OFS D5005 +// Description : Memory Channel Interleaving Module +// ----------------------------------------------------------------------------- +// +// The main purpose of this module is to ensure responses from multi channel +// EMIF are sent back in the same order as requests. +// +// This module receives memory requests from HE on a single AVMM interface and +// sends it out to the MC controller address-interleaved in either 1,2 or 4 +// channels. The number of channels is specified by the MC_CHANNEL parameter. +// +// Memory Requests from HE are buffered in req_q. When req_q is full the AVMM +// interface is back pressured. Requests at the head of req_q are pushed to +// o_mc_* when i_mc_ready is 1. +// +// To track the order of requests, the request channel no. is also buffered in +// req_trk_q every time HE sends a request. +// +// Read responses from EMIF are buffered in rsp_q. There is 1 rsp_q per channel. +// +// The ch no. at the head of req_trk_q decides which channel's rsp_q to wait +// on. As soon as a response is available, it is pulled from the rsp_q and +// returned on the o_he_readdata* interface. Simultaneously the ch no. from the +// req_trk_q is also pulled and discarded. + +//FUTURE_IMPROVEMENT: size response queue for burst size greater than one. + +module mem_intf_reorder #( + parameter MC_CHANNEL = 1, + parameter DATA_WIDTH = 576, + parameter ADDR_WIDTH = 27, + parameter BURST_WIDTH = 7 +) +( + input logic clk , + input logic resetb , + + ofs_fim_emif_avmm_if.user mc_if [MC_CHANNEL-1:0] , //mem_intf to mem_controller + ofs_fim_emif_avmm_if.emif he_if //HE to mem_intf +); + +localparam CH_W = (MC_CHANNEL == 1) ? 1 : $clog2(MC_CHANNEL); //CH_W is no. of bits to represent the channel + +localparam BE_WIDTH = DATA_WIDTH/8; + +localparam REQ_FIFO_W = DATA_WIDTH + BE_WIDTH + ADDR_WIDTH + BURST_WIDTH + 2; //read,write +localparam REQ_FIFO_D_B2 = 4; +localparam REQ_FIFO_FULL_TH = (2**REQ_FIFO_D_B2) - 8; + +localparam REQ_TRK_FIFO_W = CH_W+BURST_WIDTH; +localparam REQ_TRK_FIFO_D_B2 = 7; +localparam REQ_TRK_FIFO_FULL_TH = (2**REQ_TRK_FIFO_D_B2) - 8; + +localparam RSP_FIFO_W = DATA_WIDTH; +localparam RSP_FIFO_D_B2 = 6; +localparam RSP_FIFO_FULL_TH = (2**RSP_FIFO_D_B2) - 8; + + +logic [MC_CHANNEL-1:0] i_mc_waitrequest ;// input; width = 1; +logic [MC_CHANNEL-1:0] o_mc_read ;// output; width = 1; +logic [MC_CHANNEL-1:0] o_mc_write ;// output; width = 1; +logic [ADDR_WIDTH-1:0] o_mc_address [MC_CHANNEL-1:0] ;// output; width = 46; +logic [DATA_WIDTH-1:0] i_mc_readdata [MC_CHANNEL-1:0] ;// input; width = 512; +logic [DATA_WIDTH-1:0] o_mc_writedata [MC_CHANNEL-1:0] ;// output; width = 512; +logic [BE_WIDTH-1:0] o_mc_byteenable [MC_CHANNEL-1:0] ;// output; width = 64; +logic [BURST_WIDTH-1:0] o_mc_burstcount [MC_CHANNEL-1:0] ;// output; width = 64; +logic [MC_CHANNEL-1:0] i_mc_readdatavalid ;// input; width = 1; + +logic req_wen; +logic [REQ_FIFO_W-1:0] req_din; +logic req_ren; +logic [REQ_FIFO_W-1:0] req_dout; +logic req_full; +logic req_nemp; +logic [1:0] req_ecc; +logic req_err; +logic req_wen_p; +logic [REQ_FIFO_W-1:0] req_din_p; +logic req_full_q; + +logic req_trk_wen; +logic [REQ_TRK_FIFO_W-1:0] req_trk_din; +logic req_trk_ren; +logic [REQ_TRK_FIFO_W-1:0] req_trk_dout; +logic req_trk_full; +logic req_trk_nemp; +logic [1:0] req_trk_ecc; +logic req_trk_err; +logic req_trk_wen_p; +logic [REQ_TRK_FIFO_W-1:0] req_trk_din_p; +logic req_trk_full_q; + +logic [MC_CHANNEL-1:0] rsp_wen ; +logic [RSP_FIFO_W-1:0] rsp_din [MC_CHANNEL-1:0] ; +logic [MC_CHANNEL-1:0] rsp_ren ; +logic [RSP_FIFO_W-1:0] rsp_dout [MC_CHANNEL-1:0] ; +logic [MC_CHANNEL-1:0] rsp_full ; +logic [MC_CHANNEL-1:0] rsp_nemp ; +logic [1:0] rsp_ecc [MC_CHANNEL-1:0] ; +logic [MC_CHANNEL-1:0] rsp_err ; + +logic req_dout_read ; +logic req_dout_write ; +logic [ADDR_WIDTH-1:0] req_dout_addr ; +logic [BURST_WIDTH-1:0] req_dout_burstcount ; +logic [BE_WIDTH-1:0] req_dout_be ; +logic [DATA_WIDTH-1:0] req_dout_writedata ; + +logic [MC_CHANNEL-1:0] s0_waitrequest ; +logic [DATA_WIDTH-1:0] s0_readdata [MC_CHANNEL-1:0] ; +logic [MC_CHANNEL-1:0] s0_readdatavalid ; +logic [BURST_WIDTH-1:0] s0_burstcount [MC_CHANNEL-1:0] ; +logic [DATA_WIDTH-1:0] s0_writedata [MC_CHANNEL-1:0] ; +logic [ADDR_WIDTH-1:0] s0_address [MC_CHANNEL-1:0] ; +logic [MC_CHANNEL-1:0] s0_write ; +logic [MC_CHANNEL-1:0] s0_read ; +logic [BE_WIDTH-1:0] s0_byteenable [MC_CHANNEL-1:0] ; + + +logic [MC_CHANNEL-1:0] i_mc_readdatavalid_T0 ; +logic [DATA_WIDTH-1:0] i_mc_readdata_T0 [MC_CHANNEL-1:0]; + +logic [MC_CHANNEL-1:0] i_mc_readdatavalid_T1 ; +logic [DATA_WIDTH-1:0] i_mc_readdata_T1 [MC_CHANNEL-1:0]; + +logic [DATA_WIDTH-1:0] o_he_readdata_T0; +logic o_he_readdatavalid_T0; + +logic [DATA_WIDTH-1:0] o_he_readdata_T1; +logic o_he_readdatavalid_T1; + +logic [7:0] ErrorVector; + +logic [BURST_WIDTH-1:0] rdburstcount; + +integer i, j, k; +genvar c; + +//Convert interface to signals +for(c=0; c 1) ? {he_if.burstcount,he_if.address[CH_W-1:0]} : 0 ; //Stores the Ch no. + + + //req_full_q <= req_full; + //req_trk_full_q <= req_trk_full; + + //he_if.waitrequest <= req_full_q | req_trk_full_q; + + if(!resetb) + begin + req_wen <= 1'b0; + req_trk_wen <= 1'b0; + end +end //always_comb + +// HA Request FIFO Output +assign {req_dout_read, + req_dout_write, + req_dout_addr, + req_dout_burstcount, + req_dout_be, + req_dout_writedata} = req_dout; + + + +// Request path to Memory controller +// Check CH_NUM of head of req FIFO. Pop/drive if channel is free +// AVMM Pipeline Bridge used per channel to help with timing +generate + +if(MC_CHANNEL == 1) +begin + +assign req_ren = (!resetb) ? 1'b0 : (req_nemp && (s0_waitrequest[0] == 1'b0)); + +//Assert read/write only for the CH that matches +assign s0_read [0] = req_nemp && req_dout_read; +assign s0_write [0] = req_nemp && req_dout_write; +assign s0_burstcount [0] = req_dout_burstcount;//'h1; +assign s0_writedata [0] = req_dout_writedata; +assign s0_address [0] = req_dout_addr; +assign s0_byteenable [0] = req_dout_be; + +end + +else // (MC_CHANNEL > 1) +begin + +assign req_ren = (!resetb) ? 1'b0 : (req_nemp && (s0_waitrequest[req_dout_addr[CH_W-1:0]] == 1'b0)); + +for(c=0; c> CH_W; + assign s0_byteenable [c] = req_dout_be; +end //for + +end //if(MC_CHANNEL) + +endgenerate + + +//1 AVMM pipeline bridge per channel to help with timing +generate +for(genvar c=0; c|ea_rx |<-------+ |axi_ea | |axi_ea | +// |_ser_q | |_tx_q_1 | |_tx_q_0 | +// | | | | | | +// | | | | | | +// +----- -----+ | | | | +// | +--------+ | +--------+ +--------+ +// | | ^ ^ +// | | | | +// \/ \/ | | +// +------------------------------+ +------------------------+ +// | | ^ +// | Decode & Realignment Block | | +// | | | +// +---------------|--------------+ | +// | st_tx_tvalid +// | +// \/ +// st_rx_tvalid +// +// =========================================================================================================================================================== +// +// Done: Byte Count +// Done: Request ID RAM +// Done: TX Tuser bits on IOFS EA interface is different from RX. Not fixed for +// uniformity in TX/RX direction. 2:0 used in pcie_top. +// Done: FLR +// Handled outside this adapter. +// Done: Questions for Vaibhav: 1. DMRd[20] and DMWr[60] So read/writes will always use 64 bit addressing ? +// Yes. Requests from HEs will always be DM_RD/DM_WR. This adapter checks address and decides which (3DW or 4DW) Fmttype and format to use. +// Done: Request ID is saved on oncoming request from Host. Returned back with completion. +// Done: What is slot number ? +// For multiple PCIe slots. Always kept 0. +// Note: EA VF is 13b & IOFS SS is 11b. We use only 11 bits. +// +// =========================================================================================================================================================== + +`include "vendor_defines.vh" + +module axi_s_adapter #( + parameter PASSTHRU_MODE = 0, + + parameter PU_CPL = PASSTHRU_MODE, + + parameter UNIQUE_TAG_WA = 0, + + parameter EA_CH = 2, + parameter AXI_EA_DATA_W = 392, + parameter AXI_EA_USER_W = 22, + + parameter SS_USER_W = 2, + parameter SS_DATA_W = 512, + localparam SS_KEEP_W = SS_DATA_W/8, + + parameter NUM_PF = 1, //Number of PFs + parameter NUM_VF = 3 //Number of VFs +) +( + input logic clk, + input logic resetb, + + output logic axi_ea_rx_tready, + input logic axi_ea_rx_tvalid, + input logic axi_ea_rx_tlast, + input logic [AXI_EA_USER_W-1:0] axi_ea_rx_tuser [EA_CH-1:0], + input logic [AXI_EA_DATA_W-1:0] axi_ea_rx_tdata [EA_CH-1:0], + + input logic axi_ea_tx_tready, + output logic axi_ea_tx_tvalid, + output logic axi_ea_tx_tlast, + output logic [AXI_EA_USER_W-1:0] axi_ea_tx_tuser [EA_CH-1:0], //[2:0] are used + output logic [AXI_EA_DATA_W-1:0] axi_ea_tx_tdata [EA_CH-1:0], + + input logic st_rx_tready, + output logic st_rx_tvalid, + output logic st_rx_tlast, + output logic [SS_USER_W-1:0] st_rx_tuser_vendor, + output logic [SS_DATA_W-1:0] st_rx_tdata, + output logic [SS_KEEP_W-1:0] st_rx_tkeep, + + output logic st_tx_tready, + input logic st_tx_tvalid, + input logic st_tx_tlast, + input logic [SS_USER_W-1:0] st_tx_tuser_vendor, + input logic [SS_DATA_W-1:0] st_tx_tdata, + input logic [SS_KEEP_W-1:0] st_tx_tkeep +); + + localparam TX_PASSTHRU = PASSTHRU_MODE; + localparam RX_PASSTHRU = PASSTHRU_MODE; + + localparam EA_DATA_VALID = 0; // 0 + localparam EA_DATA_SOP = EA_DATA_VALID + 1; // 1 + localparam EA_DATA_EOP = EA_DATA_SOP + 1; // 2 + localparam EA_DATA_RSVD_L = EA_DATA_EOP + 1; // 3 + localparam EA_DATA_RSVD_H = EA_DATA_EOP + 5; // 7 + localparam EA_DATA_HDR_L = EA_DATA_RSVD_H + 1; // 8 + localparam EA_DATA_HDR_H = EA_DATA_RSVD_H + 128; // 135 + localparam EA_DATA_PYLD_L = EA_DATA_HDR_H + 1; // 136 + localparam EA_DATA_PYLD_H = EA_DATA_HDR_H + 256; // 391 + localparam EA_DATA_VF_ACTIVE = EA_DATA_PYLD_H + 1 ; // 392 + + //RX Specific parameters + localparam EA_DATA_PFN_L = EA_DATA_VF_ACTIVE + 1; // 393 + localparam EA_DATA_PFN_H = EA_DATA_VF_ACTIVE + 3; // 395 + localparam EA_DATA_VFN_L = EA_DATA_PFN_H + 1; // 396 + localparam EA_DATA_VFN_H = EA_DATA_PFN_H + 13; // 408 + localparam EA_DATA_BAR_L = EA_DATA_VFN_H + 1; // 409 + localparam EA_DATA_BAR_H = EA_DATA_VFN_H + 3; // 411 + localparam EA_DATA_UMMIO_RD = EA_DATA_BAR_H + 1; // 412 + localparam EA_DATA_MMIO_REQ = EA_DATA_UMMIO_RD + 1; // 413 + localparam EA_DATA_LAST = EA_DATA_MMIO_REQ + 1; // 414 + + //TX Specific parameters + localparam EA_DATA_TX_AFU_IRQ = EA_DATA_PYLD_H + 1; //392 + localparam EA_DATA_TX_AFU_PORT_CSR_WR = EA_DATA_TX_AFU_IRQ + 1; //393 + localparam EA_DATA_TX_VF_ACTIVE = EA_DATA_TX_AFU_PORT_CSR_WR + 1; //394 + localparam EA_DATA_TX_LAST = EA_DATA_TX_VF_ACTIVE + 1; //395 + + //PCIe TLP Header (First 2 DWs. The 2nd and 3rd depend on the type) + localparam FIRST_DW_BE_L = 64; // 64 + localparam FIRST_DW_BE_H = FIRST_DW_BE_L + 3; // 67 + localparam LAST_DW_BE_L = FIRST_DW_BE_H + 1; // 68 + localparam LAST_DW_BE_H = FIRST_DW_BE_H + 4; // 71 + localparam TAG_L = LAST_DW_BE_H + 1; // 72 + localparam TAG_H = LAST_DW_BE_H + 8; // 79 + localparam REQ_ID_L = TAG_H + 1; // 80 + localparam REQ_ID_H = TAG_H + 16; // 95 + localparam LENGTH_L = REQ_ID_H + 1; // 96 + localparam LENGTH_H = REQ_ID_H + 10; // 105 + localparam AT_L = LENGTH_H + 1; // 106 + localparam AT_H = LENGTH_H + 2; // 107 + localparam ATTR_0 = AT_H + 1; // 108 + localparam ATTR_1 = ATTR_0 + 1; // 109 + localparam EP = ATTR_1 + 1; // 110 + localparam TD = EP + 1; // 111 + localparam TH = TD + 1; // 112 + localparam LN = TH + 1; // 113 + localparam ATTR_2 = LN + 1; // 114 + localparam TAG_8 = ATTR_2 + 1; // 115 + localparam TC_L = TAG_8 + 1; // 116 + localparam TC_H = TAG_8 + 3; // 118 + localparam TAG_9 = TC_H + 1; // 119 + localparam FMTTYPE_L = TAG_9 + 1; // 120 + localparam FMTTYPE_H = TAG_9 + 8; // 127 + + //PCIe SS Interface + localparam SS_TDATA_L = 0; // 0 + localparam SS_TDATA_H = SS_TDATA_L + 511; // 511 + localparam SS_TKEEP_L = SS_TDATA_H + 1; // 512 + localparam SS_TKEEP_H = SS_TDATA_H + SS_KEEP_W; // 575 + localparam SS_TUSER_L = SS_TKEEP_H + 1; // 576 + localparam SS_TUSER_H = SS_TKEEP_H + SS_USER_W; // 585 + localparam SS_TLAST = SS_TUSER_H + 1; // 586 + + //EA FIFO paramaters + localparam AXI_EA_Q_W = 1 + AXI_EA_USER_W + AXI_EA_DATA_W ; //+1 for tlast + localparam AXI_EA_Q_D_B2 = 4; + localparam AXI_EA_Q_FULL_TH = 4; + + //EA SER FIFO paramaters + localparam EA_SER_Q_W = AXI_EA_Q_W; + localparam EA_SER_Q_D_B2 = 5; + localparam EA_SER_Q_FULL_TH = (2**EA_SER_Q_D_B2) - 8; + + //PCIe SS FIFO parameters + localparam SS_DATA_Q_W = 1 + SS_USER_W + SS_KEEP_W + SS_DATA_W ; //+1 for tlast + localparam SS_DATA_Q_D_B2 = 4; + localparam SS_DATA_Q_FULL_TH = 4; + + localparam NUM_TAGS = 256; //8-bit tag supported by EA + localparam NUM_TAGS_B2 = $clog2(NUM_TAGS); + + localparam PF_W = (NUM_PF > 1) ? $clog2(NUM_PF) : 1; + localparam VF_W = (NUM_VF > 1) ? $clog2(NUM_VF) : 1; + + //Header format RAM parameters + localparam HDR_FORMAT_W = 1; // {0-PU/1-DM) + localparam HDR_FORMAT_D_B2 = 1 + PF_W + VF_W + NUM_TAGS_B2; // Extra bit needed for PF0 + + //TX States + localparam SOP = 0; + localparam DATA = 1; + + // --------------------------------------------------------------------------- + // AXI EA INPUT QUEUEs + // --------------------------------------------------------------------------- + logic [AXI_EA_Q_W-1:0] axi_ea_rx_din [EA_CH-1:0] ;// + logic [EA_CH-1:0] axi_ea_rx_wen ;// + logic [EA_CH-1:0] axi_ea_rx_ren ;// + logic [AXI_EA_Q_W-1:0] axi_ea_rx_dout [EA_CH-1:0] ;// + logic [EA_CH-1:0] axi_ea_rx_full ;// + logic [EA_CH-1:0] axi_ea_rx_nemp ;// + logic [1:0] axi_ea_rx_ecc [EA_CH-1:0] ;// + logic [EA_CH-1:0] axi_ea_rx_err ;// + + + // --------------------------------------------------------------------------- + // AXI EA SERIAL QUEUE + // --------------------------------------------------------------------------- + logic [EA_SER_Q_W-1:0] ea_ser_din [1:0] ;// + logic [1:0] ea_ser_wen ;// + logic [1:0] ea_ser_ren ;// + logic [EA_SER_Q_W-1:0] ea_ser_dout [1:0] ;// + logic [1:0] ea_ser_nemp ;// + logic ea_ser_full ;// + logic ea_ser_err ;// + logic ea_ser_perr ;// + + // --------------------------------------------------------------------------- + // AXI EA OUTPUT QUEUEs + // --------------------------------------------------------------------------- + logic [AXI_EA_Q_W-1:0] axi_ea_tx_din [EA_CH-1:0] ;// + logic [EA_CH-1:0] axi_ea_tx_wen ;// + logic [EA_CH-1:0] axi_ea_tx_ren ;// + logic [AXI_EA_Q_W-1:0] axi_ea_tx_dout [EA_CH-1:0] ;// + logic [EA_CH-1:0] axi_ea_tx_full ;// + logic [EA_CH-1:0] axi_ea_tx_nemp ;// + logic [1:0] axi_ea_tx_ecc [EA_CH-1:0] ;// + logic [EA_CH-1:0] axi_ea_tx_err ;// + + // --------------------------------------------------------------------------- + // PCIe SS TX INPUT PIPE + // --------------------------------------------------------------------------- + logic st_tx_tvalid_T1 ; + logic st_tx_tlast_T1 ; + logic [SS_USER_W-1:0] st_tx_tuser_vendor_T1 ; + logic [SS_DATA_W-1:0] st_tx_tdata_T1 ; + logic [SS_KEEP_W-1:0] st_tx_tkeep_T1 ; + + logic st_tx_tvalid_T2 ; + logic st_tx_tlast_T2 ; + logic [SS_USER_W-1:0] st_tx_tuser_vendor_T2 ; + logic [SS_DATA_W-1:0] st_tx_tdata_T2 ; + logic [SS_KEEP_W-1:0] st_tx_tkeep_T2 ; + + // --------------------------------------------------------------------------- + // PCIe SS RX OUTPUT PIPE + // --------------------------------------------------------------------------- + logic st_rx_tready_p; + logic st_rx_tvalid_p; + logic st_rx_sop_p; + logic st_rx_tlast_p; + logic [SS_USER_W-1:0] st_rx_tuser_vendor_p; + logic [SS_DATA_W-1:0] st_rx_tdata_p; + logic [SS_KEEP_W-1:0] st_rx_tkeep_p; + + logic st_rx_tready_p1; + logic st_rx_tvalid_p1; + logic st_rx_sop_p1; + logic st_rx_tlast_p1; + logic [SS_USER_W-1:0] st_rx_tuser_vendor_p1; + logic [SS_DATA_W-1:0] st_rx_tdata_p1; + logic [SS_KEEP_W-1:0] st_rx_tkeep_p1; + + logic st_rx_tready_p2; + logic st_rx_tvalid_p2; + logic st_rx_tlast_p2; + logic [SS_USER_W-1:0] st_rx_tuser_vendor_p2; + logic [SS_DATA_W-1:0] st_rx_tdata_p2; + logic [SS_KEEP_W-1:0] st_rx_tkeep_p2; + + logic [SS_USER_W-1:0] st_rx_tuser_vendor_p3; + + // --------------------------------------------------------------------------- + // AXI EA TX OUTPUT + // --------------------------------------------------------------------------- + logic axi_ea_tx_tready_p; + logic axi_ea_tx_tvalid_p; + logic axi_ea_tx_tlast_p; + logic [AXI_EA_USER_W-1:0] axi_ea_tx_tuser_p [EA_CH-1:0]; + logic [AXI_EA_DATA_W-1:0] axi_ea_tx_tdata_p [EA_CH-1:0]; + + + // --------------------------------------------------------------------------- + // AXI EA OUTPUT QUEUEs + // --------------------------------------------------------------------------- + logic [15:0] req_id_din ; //Request ID width + logic [NUM_TAGS_B2-1:0] req_id_wad ; //Width for 256 Tags + logic req_id_wen ; + logic [NUM_TAGS_B2-1:0] req_id_rad ; + logic req_id_ren ; + logic [15:0] req_id_dout ; + logic req_id_perr ; + + // --------------------------------------------------------------------------- + // HDR FORMAT RAM + // --------------------------------------------------------------------------- + logic [HDR_FORMAT_W-1:0] hdr_format_din ; // + logic [HDR_FORMAT_D_B2-1:0] hdr_format_wad ; // + logic hdr_format_wen ; + logic [HDR_FORMAT_D_B2-1:0] hdr_format_rad ; + logic [HDR_FORMAT_W-1:0] hdr_format_dout ; + logic [HDR_FORMAT_D_B2-1:0] hdr_func_wr_addr; + logic [HDR_FORMAT_D_B2-1:0] hdr_func_rd_addr; + logic [HDR_FORMAT_D_B2-1:0] hdr_format_rad_reg ; + + + // --------------------------------------------------------------------------- + // AXI TX variables + // --------------------------------------------------------------------------- + logic tx_state, next_tx_state; + logic [127:0] ea_ser_hdr [1:0]; + + integer i, j; + + // --------------------------------------------------------------------------- + // Write to EA AXI RX FIFOs + // --------------------------------------------------------------------------- + always @ (posedge clk) + begin + for(i=0; i 3DW MRd + st_tx_tdata_T2[31:24] == 8'h60 ? + 8'h40 : // 4DW -> 3DW MWr + st_tx_tdata_T2[31:24]; // 3DW MRd, 3DW MWr + end + else + begin + pcie_hdr[FMTTYPE_H:FMTTYPE_L] = st_tx_tdata_T2[31:24]; // 4DW MRd, 4DW MWr + end + + pcie_hdr[TAG_9] = st_tx_tdata_T2[23]; // T9 + pcie_hdr[TC_H:TC_L] = st_tx_tdata_T2[22:20]; // TC + pcie_hdr[TAG_8] = st_tx_tdata_T2[19]; // T8 + pcie_hdr[ATTR_2] = st_tx_tdata_T2[18]; // Attr_2 + pcie_hdr[LN] = st_tx_tdata_T2[17]; // LN + pcie_hdr[TH] = st_tx_tdata_T2[16]; // TH + pcie_hdr[TD] = st_tx_tdata_T2[15]; // TD + pcie_hdr[EP] = st_tx_tdata_T2[14]; // EP + pcie_hdr[ATTR_0] = st_tx_tdata_T2[12]; // Attr_0 + pcie_hdr[ATTR_1] = st_tx_tdata_T2[13]; // Attr_1 + pcie_hdr[AT_H:AT_L] = st_tx_tdata_T2[11:10]; // AT + pcie_hdr[LENGTH_H:LENGTH_L] = st_tx_tdata_T2[9:0]; // DW because Length[11:2] + + // DW 1 + pcie_hdr[REQ_ID_H:REQ_ID_L] = {st_tx_tdata_T2[173:163], 1'b0, st_tx_tdata_T2[162:160]}; // {VF,PF} - H-tile Spec + + if(UNIQUE_TAG_WA) + pcie_hdr[TAG_H:TAG_L] = {st_tx_tdata_T2[164:163], st_tx_tdata_T2[45:40]}; // VF, Tag[5:0] + else + pcie_hdr[TAG_H:TAG_L] = st_tx_tdata_T2[47:40]; // Tag[7:0] + + if ( pcie_hdr[LENGTH_H:LENGTH_L] == 'd1 ) + pcie_hdr[LAST_DW_BE_H:LAST_DW_BE_L] = 4'h0; // BE + else + pcie_hdr[LAST_DW_BE_H:LAST_DW_BE_L] = 4'hF; // BE + + pcie_hdr[FIRST_DW_BE_H:FIRST_DW_BE_L] = 4'hF; // BE + + if( ((st_tx_tdata_T2[31:24] == 8'h20) && (pcie_hdr[FMTTYPE_H:FMTTYPE_L] == 8'h00)) // M_RD64 -> 32 + || ((st_tx_tdata_T2[31:24] == 8'h60) && (pcie_hdr[FMTTYPE_H:FMTTYPE_L] == 8'h40)) ) // M_WR64 -> 32 + begin + // DW 2 + pcie_hdr[63:32] = st_tx_tdata_T2[127:96]; // Host Address[31:2], PH[1:0] + + // DW 3 + pcie_hdr[31:0] = '0; // 0 + end + else //DM_RD/DM_WR + begin + // DW 2 + pcie_hdr[63:32] = st_tx_tdata_T2[95:64]; // Host Address[63:32] + + // DW 3 + pcie_hdr[31:0] = st_tx_tdata_T2[127:96]; // Host Address[31:2], PH[1:0] + end + + + tx_dm_req_packer = pcie_hdr; + endfunction : tx_dm_req_packer + + // --------------------------------------------------------------------------- + // Pack TX Req Hdr (PU Format) + // Rd/Wr + // --------------------------------------------------------------------------- + function logic [127:0] tx_pu_req_packer(); + + logic [127:0] pcie_hdr; + + pcie_hdr = {128{1'b0}}; + + // DW 0 + pcie_hdr[FMTTYPE_H:FMTTYPE_L] = st_tx_tdata_T2[31:24]; // 4DW MRd, 4DW MWr + + pcie_hdr[TAG_9] = st_tx_tdata_T2[23]; // T9 + pcie_hdr[TC_H:TC_L] = st_tx_tdata_T2[22:20]; // TC + pcie_hdr[TAG_8] = st_tx_tdata_T2[19]; // T8 + pcie_hdr[ATTR_2] = st_tx_tdata_T2[18]; // Attr_2 + pcie_hdr[LN] = st_tx_tdata_T2[17]; // LN + pcie_hdr[TH] = st_tx_tdata_T2[16]; // TH + pcie_hdr[TD] = st_tx_tdata_T2[15]; // TD + pcie_hdr[EP] = st_tx_tdata_T2[14]; // EP + pcie_hdr[ATTR_0] = st_tx_tdata_T2[12]; // Attr_0 + pcie_hdr[ATTR_1] = st_tx_tdata_T2[13]; // Attr_1 + pcie_hdr[AT_H:AT_L] = st_tx_tdata_T2[11:10]; // AT + pcie_hdr[LENGTH_H:LENGTH_L] = st_tx_tdata_T2[9:0]; // DW because Length[11:2] + + // DW 1 + pcie_hdr[LAST_DW_BE_H:FIRST_DW_BE_L] = st_tx_tdata_T2[39:32]; // Last/First DW BE + + if(UNIQUE_TAG_WA) + pcie_hdr[TAG_H:TAG_L] = {st_tx_tdata_T2[164:163], st_tx_tdata_T2[45:40]}; // VF, Tag[5:0] + else + pcie_hdr[TAG_H:TAG_L] = st_tx_tdata_T2[47:40]; // Tag[7:0] + + pcie_hdr[REQ_ID_H:REQ_ID_L] = st_tx_tdata_T2[63:48]; // Requester ID + + // DW 2 + pcie_hdr[63:32] = st_tx_tdata_T2[95:64]; // Host Address[63:32] + + // DW 3 + pcie_hdr[31:0] = st_tx_tdata_T2[127:96]; // Host Address[31:2], PH[1:0] + + + tx_pu_req_packer = pcie_hdr; + endfunction: tx_pu_req_packer + + + // --------------------------------------------------------------------------- + // Pack TX Cpl Hdr + // CplD to MMIO REquests from the Host + // --------------------------------------------------------------------------- + function logic [127:0] tx_pu_cpl_packer(); + + logic [127:0] pcie_hdr; + + pcie_hdr = {128{1'b0}}; + + // DW 0 + pcie_hdr[FMTTYPE_H:FMTTYPE_L] = st_tx_tdata_T2[31:24]; // CplD + pcie_hdr[TAG_9] = st_tx_tdata_T2[23]; // T9 + pcie_hdr[TC_H:TC_L] = st_tx_tdata_T2[22:20]; // TC + pcie_hdr[TAG_8] = st_tx_tdata_T2[19]; // T8 + pcie_hdr[ATTR_2] = st_tx_tdata_T2[18]; // Attr_2 + pcie_hdr[LN] = st_tx_tdata_T2[17]; // LN + pcie_hdr[TH] = st_tx_tdata_T2[16]; // TH + pcie_hdr[TD] = st_tx_tdata_T2[15]; // TD + pcie_hdr[EP] = st_tx_tdata_T2[14]; // EP + pcie_hdr[ATTR_1] = st_tx_tdata_T2[13]; // Attr_1 + pcie_hdr[ATTR_0] = st_tx_tdata_T2[12]; // Attr_0 + pcie_hdr[AT_H:AT_L] = 2'b00; // AT + pcie_hdr[LENGTH_H:LENGTH_L] = st_tx_tdata_T2[9:0]; // DW because Length[11:2] + + // DW 1 + pcie_hdr[95:80] = st_tx_tdata_T2[63:48]; // Completer ID {VF, VF_ACTIVE, PF} - PCIe SS power user mode + +`ifndef R1_UNIT_TEST_ENV + + `ifdef HTILE + pcie_hdr[83] = 1'b0; // Completer ID {VF,PF} - H-Tile Spec + `endif + +`endif // R1_UNIT_TEST_ENV + + pcie_hdr[79:77] = st_tx_tdata_T2[47:45]; // Cpl Status + pcie_hdr[76] = 1'b0; // BCM + pcie_hdr[75:64] = st_tx_tdata_T2[43:32]; // Byte Count - MMIO responses will always be 4 -or- 8 bytes + + // DW 2 + if ( st_tx_tuser_vendor_T2[0] == 1'b0 ) //PU format + pcie_hdr[63:48] = st_tx_tdata_T2[95:80]; // Req ID comes from HE + else + pcie_hdr[63:48] = req_id_dout; // Req ID comes from this adapter + + pcie_hdr[47:40] = st_tx_tdata_T2[79:72]; // Tag (only using 8-bit tag. Data Mover supports 10-bit) + pcie_hdr[39] = 1'b0; // Rsvd + pcie_hdr[38:32] = st_tx_tdata_T2[70:64]; // Lower Address (only using 7-bit lower address) + + tx_pu_cpl_packer = pcie_hdr; + endfunction: tx_pu_cpl_packer + + // --------------------------------------------------------------------------- + // Pack TX Cpl Hdr + // CplD to MMIO REquests from the Host + // --------------------------------------------------------------------------- + function logic [127:0] tx_dm_cpl_packer(); + + logic [127:0] pcie_hdr; + + pcie_hdr = {128{1'b0}}; + + // DW 0 + pcie_hdr[FMTTYPE_H:FMTTYPE_L] = st_tx_tdata_T2[31:24]; // CplD + pcie_hdr[TAG_9] = st_tx_tdata_T2[127]; // T9 + pcie_hdr[TC_H:TC_L] = st_tx_tdata_T2[22:20]; // TC + pcie_hdr[TAG_8] = st_tx_tdata_T2[126]; // T8 + pcie_hdr[ATTR_2] = st_tx_tdata_T2[18]; // Attr_2 + pcie_hdr[LN] = st_tx_tdata_T2[17]; // LN + pcie_hdr[TH] = st_tx_tdata_T2[16]; // TH + pcie_hdr[TD] = st_tx_tdata_T2[15]; // TD + pcie_hdr[EP] = st_tx_tdata_T2[14]; // EP + pcie_hdr[ATTR_0] = st_tx_tdata_T2[12]; // Attr_0 + pcie_hdr[ATTR_1] = st_tx_tdata_T2[13]; // Attr_1 + pcie_hdr[AT_H:AT_L] = 2'b00; // AT + pcie_hdr[LENGTH_H:LENGTH_L] = st_tx_tdata_T2[9:0]; // DW because Length[11:2] + + // DW 1 + pcie_hdr[95:80] = {st_tx_tdata_T2[173:163], 1'b0, st_tx_tdata_T2[162:160]}; //Completer ID - {VF,PF} - H-Tile Spec + pcie_hdr[79:77] = st_tx_tdata_T2[47:45]; // Cpl Status + pcie_hdr[76] = 1'b0; // BCM + if ( TX_PASSTHRU ) + pcie_hdr[75:64] = st_tx_tdata_T2[43:32]; // Byte Count + else + pcie_hdr[75:64] = {st_tx_tdata_T2[9:0], 2'b00}; // Byte Count + + // DW 2 + if ( TX_PASSTHRU ) + pcie_hdr[63:48] = st_tx_tdata_T2[95:80]; // Req ID comes from HE + else + pcie_hdr[63:48] = req_id_dout; // Req ID comes from this adapter + + pcie_hdr[47:40] = st_tx_tdata_T2[125:118]; // Tag (only using 8-bit tag. Data Mover supports 10-bit) + pcie_hdr[39] = 1'b0; // Rsvd + pcie_hdr[38:32] = st_tx_tdata_T2[70:64]; // Lower Address (only using 7-bit lower address) + + tx_dm_cpl_packer = pcie_hdr; + endfunction: tx_dm_cpl_packer + + // --------------------------------------------------------------------------- + // Pack TX Intr Hdr + // Data Mover Interrupt from the Host + // --------------------------------------------------------------------------- + function logic [127:0] tx_dm_intr_packer(); + + logic [127:0] pcie_hdr; + + pcie_hdr = {128{1'b0}}; + + // DW 0 + pcie_hdr[15:0] = {st_tx_tdata_T2[174:163], + 1'b0, + st_tx_tdata_T2[162:160]}; // Requester ID - (VF Active, VF, PF) + pcie_hdr[23:16] = st_tx_tdata_T2[71:64]; // Interrupt ID + + tx_dm_intr_packer = pcie_hdr; + endfunction + + // --------------------------------------------------------------------------- + // Error Flags + // --------------------------------------------------------------------------- + /*synthesis translate_off */ + always @ (posedge clk) + begin + if(resetb & ((|axi_ea_rx_err) | (|axi_ea_tx_err) | ea_ser_err)) + begin + $display("======================================================================================================"); + $display("*** ERROR: AXI_S_ADAPTER: FIFO ERROR ***"); + $display("======================================================================================================"); + #100; + $finish() ; + end + end//always @ (posedge) + /*synthesis translate_on */ + + + // --------------------------------------------------------------------------- + // AXI EA FIFO + // --------------------------------------------------------------------------- + generate + genvar n; + + for(n=0; n FULL_THRESHOLD + .not_empty ( axi_ea_tx_nemp[n]) ,// FIFO is not empty + + .fifo_eccstatus ( axi_ea_tx_ecc[n] ) ,// FIFO parity error + .fifo_err ( axi_ea_tx_err[n] ) // FIFO overflow/underflow error + ); + + end //for EA_FIFO + endgenerate + + qfifo + #(.WIDTH ( EA_SER_Q_W ) ,// + .DEPTH ( EA_SER_Q_D_B2 ) ,// + .FULL_THRESHOLD ( EA_SER_Q_FULL_TH ) ,// + .REG_OUT ( 0 ) ,// + .GRAM_STYLE ( `GRAM_AUTO ) ,// + .BITS_PER_PARITY ( 32 ) + ) + ea_ser_rx_q + ( + .din0 ( ea_ser_din[0] ) ,// [WIDTH-1:0] data in port 0 + .wen0 ( ea_ser_wen[0] ) ,// write enable port 0 + .ren0 ( ea_ser_ren[0] ) ,// read enable port 0 + .din1 ( ea_ser_din[1] ) ,// [WIDTH-1:0] data in port 1 + .wen1 ( ea_ser_wen[1] ) ,// write enable port 1 + .ren1 ( ea_ser_ren[1] ) ,// read enable port 1 + + .resetb ( resetb ) ,// resetb (active low) + .clk ( clk ) ,// 1x clock + + .out0 ( ) ,// [WIDTH-1:0] read data output prot0 (comb out) + .out1 ( ) ,// [WIDTH-1:0] read data output port1 (comb out) + .dout0 ( ea_ser_dout[0] ) ,// [WIDTH-1:0] read data output port0 + .dout1 ( ea_ser_dout[1] ) ,// [WIDTH-1:0] read data output raddr0+1 + .not_empty0 ( ea_ser_nemp[0] ) ,// fifo is not empty + .not_empty1 ( ea_ser_nemp[1] ) ,// fifo is not empty + .full ( ea_ser_full ) ,// fifo_count > FULL_THRESHOLD + .fifo_err ( ea_ser_err ) ,// fifo overflow/underflow error + .fifo_perr ( ea_ser_perr ) // fifo overflow/underflow error + ); + + + // --------------------------------------------------------------------------- + // Requester ID RAM + // --------------------------------------------------------------------------- + ram_1r1w + #(.DEPTH ( NUM_TAGS_B2 ) ,// number of bits of address bus + .WIDTH ( 16 ) ,// number of bits of data bus + .GRAM_MODE ( 2'd2 ) ,// RdLatency = 1 and Wr2RdLatency = 2 + .GRAM_STYLE ( `GRAM_AUTO ) ,// GRAM_AUTO, GRAM_AUTO, GRAM_AUTO + .BITS_PER_PARITY ( 32 ) ,// number of data BITS PER parity bit + .PIPELINE_PERR ( 1 ) // Adds one pipeline register stage in parity error detection logic. + ) + req_id_ram + ( // + .din ( req_id_din ) ,// [WIDTH-1:0] data in port 0 + .waddr ( req_id_wad ) ,// [DEPTH-1:0] write address port 0 + .we ( req_id_wen ) ,// write enable port 0 + .raddr ( req_id_rad ) ,// read address port a + .re ( req_id_ren ) ,// + .clk ( clk ) ,// 1x clock + .dout ( req_id_dout ) ,// output port a + .perr ( req_id_perr ) // parity error read prota or portb + ); + + // --------------------------------------------------------------------------- + // Header Format RAM + // --------------------------------------------------------------------------- + altera_syncram hdr_format_ram ( + .address_a (hdr_format_wad), + .address_b (hdr_format_rad), + .clock0 (clk), + .data_a (hdr_format_din), + .wren_a (hdr_format_wen), + .q_b (hdr_format_dout), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address2_a (1'b1), + .address2_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({2{1'b1}}), + .eccencbypass (1'b0), + .eccencparity (8'b0), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .sclr (1'b0), + .wren_b (1'b0)); + defparam + hdr_format_ram.address_aclr_b = "NONE", + hdr_format_ram.address_reg_b = "CLOCK0", + hdr_format_ram.clock_enable_input_a = "BYPASS", + hdr_format_ram.clock_enable_input_b = "BYPASS", + hdr_format_ram.clock_enable_output_b = "BYPASS", + `ifdef DEVICE_FAMILY + hdr_format_ram.intended_device_family = `DEVICE_FAMILY, + `else + hdr_format_ram.intended_device_family = "Stratix 10", + `endif + hdr_format_ram.lpm_type = "altera_syncram", + hdr_format_ram.numwords_a = (2**HDR_FORMAT_D_B2), + hdr_format_ram.numwords_b = (2**HDR_FORMAT_D_B2), + hdr_format_ram.operation_mode = "DUAL_PORT", + hdr_format_ram.outdata_aclr_b = "NONE", + hdr_format_ram.outdata_sclr_b = "NONE", + hdr_format_ram.outdata_reg_b = "UNREGISTERED", + hdr_format_ram.power_up_uninitialized = "FALSE", + hdr_format_ram.read_during_write_mode_mixed_ports = "DONT_CARE", + hdr_format_ram.widthad_a = HDR_FORMAT_D_B2, + hdr_format_ram.widthad_b = HDR_FORMAT_D_B2, + hdr_format_ram.width_a = HDR_FORMAT_W, + hdr_format_ram.width_b = HDR_FORMAT_W, + hdr_format_ram.width_byteena_a = 1; + +endmodule diff --git a/ipss/pcie/rtl/ofs_fim_axis_if.sv b/ipss/pcie/rtl/ofs_fim_axis_if.sv new file mode 100755 index 0000000..d24a660 --- /dev/null +++ b/ipss/pcie/rtl/ofs_fim_axis_if.sv @@ -0,0 +1,409 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Definition of AXI4 streaming interfaces used in CoreFIM +// +//----------------------------------------------------------------------------- + +`ifndef __OFS_FIM_AXIS_IF_SV__ +`define __OFS_FIM_AXIS_IF_SV__ + +import ofs_fim_if_pkg::*; + +// Interface of PCIe RX AXIS channel with multiple TLP data streams +interface ofs_fim_pcie_rxs_axis_if (); + logic clk; + logic rst_n; // Active-low reset + + // struct declaration contains tvalid, tlast, tdata, and tuser signals of the AXIS channel + t_axis_pcie_rxs rx; + + // Ready signal + logic tready; + + // AXI-S channel master + modport master ( + input tready, + output clk, + output rst_n, + output rx + ); + + // AXI-S channel slave + modport slave ( + output tready, + input clk, + input rst_n, + input rx + ); + +`ifdef OFS_FIM_ASSERT_OFF + `define OFS_FIM_AXIS_IF_ASSERT_OFF +`endif // OFS_FIM_ASSERT_OFF + +`ifndef OFS_FIM_AXIS_IF_ASSERT_OFF +// synopsys translate_off + logic enable_assertion; + + initial begin + enable_assertion = 1'b0; + repeat(2) + @(posedge clk); + + wait (rst_n === 1'b0); + wait (rst_n === 1'b1); + + enable_assertion = 1'b1; + end + + assert_tvalid_undef_when_not_in_reset: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (!$isunknown(rx.tvalid))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, rx.tvalid is undefined", $time)); + + assert_tready_undef_when_not_in_reset: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (!$isunknown(tready))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tready is undefined", $time)); + + assert_valid_undef: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (rx.tvalid |-> (!$isunknown(rx.tdata[0].valid) && !$isunknown(rx.tdata[1].valid) ))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, rx.tdata[*].valid is undefined", $time)); + + assert_tdata_tuser_ch0_undef_when_valid_high: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) ((rx.tvalid && rx.tdata[0].valid) |-> (!$isunknown(rx.tdata[0]) && !$isunknown(rx.tuser[0])))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, rx.tdata[0] or rx.tuser[0] is undefined when rx.tdata[0].valid is asserted", $time)); + + assert_tdata_tuser_ch1_undef_when_valid_high: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) ((rx.tvalid && rx.tdata[1].valid) |-> (!$isunknown(rx.tdata[1]) && !$isunknown(rx.tuser[1])))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, rx.tdata[1] or rx.tuser[1] is undefined when rx.tdata[1].valid is asserted", $time)); + + assert_tvalid_tready_handshake: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) ( (rx.tvalid && ~tready) |-> ##1 rx.tvalid)) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, rx.tvalid is dropped before acknowledged by tready", $time)); +// synopsys translate_on +`endif // OFS_FIM_AXIS_IF_ASSERT_OFF + +endinterface : ofs_fim_pcie_rxs_axis_if + +// Interface of PCIe RX AXIS channel with 1 TLP data stream +interface ofs_fim_pcie_rx_axis_if (); + logic clk; + logic rst_n; // Active-low reset + + // struct declaration contains tvalid, tlast, tdata, and tuser signals of the AXIS channel + t_axis_pcie_rx rx; + + // Ready signal + logic tready; + + // AXI-S channel master + modport master ( + input tready, + output clk, + output rst_n, + output rx + ); + + // AXI-S channel slave + modport slave ( + output tready, + input clk, + input rst_n, + input rx + ); + +`ifdef OFS_FIM_ASSERT_OFF + `define OFS_FIM_AXIS_IF_ASSERT_OFF +`endif // OFS_FIM_ASSERT_OFF + +`ifndef OFS_FIM_AXIS_IF_ASSERT_OFF +// synopsys translate_off + logic enable_assertion; + + initial begin + enable_assertion = 1'b0; + repeat(2) + @(posedge clk); + + wait (rst_n === 1'b0); + wait (rst_n === 1'b1); + + enable_assertion = 1'b1; + end + + assert_tvalid_undef_when_not_in_reset: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (!$isunknown(rx.tvalid))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, rx.tvalid is undefined", $time)); + + assert_tready_undef_when_not_in_reset: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (!$isunknown(tready))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tready is undefined", $time)); + + assert_valid_undef: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (~rx.tvalid |-> !$isunknown(rx.tdata.valid))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, rx.tdata[*].valid is undefined", $time)); + + assert_tdata_tuser_ch0_undef_when_valid_high: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) ((rx.tvalid && rx.tdata.valid) |-> !$isunknown(rx.tdata) )) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, rx.tdata or rx.tuser is undefined when rx.tdata.valid is asserted", $time)); + + assert_tvalid_tready_handshake: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) ( (rx.tvalid && ~tready) |-> ##1 rx.tvalid)) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, rx.tvalid is dropped before acknowledged by tready", $time)); +// synopsys translate_on +`endif // OFS_FIM_AXIS_IF_ASSERT_OFF + +endinterface : ofs_fim_pcie_rx_axis_if + +// Interface of PCIe TX AXIS channel with multiple TLP data streams +interface ofs_fim_pcie_txs_axis_if (); + logic clk; + logic rst_n; // Active-low reset + + // struct declaration contains tvalid, tlast, tdata, and tuser signals of the AXIS channel + t_axis_pcie_txs tx; + + // Ready signal + logic tready; + + // AXI-S channel master + modport master ( + input tready, + output clk, + output rst_n, + output tx + ); + + // AXI-S channel master for PR boundary + // No global signals + modport afu_master ( + input tready, + output tx + ); + + // AXI-S channel slave + modport slave ( + output tready, + input clk, + input rst_n, + input tx + ); + +`ifdef OFS_FIM_ASSERT_OFF + `define OFS_FIM_AXIS_IF_ASSERT_OFF +`endif // OFS_FIM_ASSERT_OFF + +`ifndef OFS_FIM_AXIS_IF_ASSERT_OFF +// synopsys translate_off + logic enable_assertion; + + initial begin + enable_assertion = 1'b0; + repeat(2) + @(posedge clk); + + wait (rst_n === 1'b0); + wait (rst_n === 1'b1); + + enable_assertion = 1'b1; + end + + assert_tvalid_undef_when_not_in_reset: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (!$isunknown(tx.tvalid))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tvalid is undefined", $time)); + + assert_tready_undef_when_not_in_reset: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (!$isunknown(tready))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tready is undefined", $time)); + + assert_valid_undef: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (tx.tvalid |-> (!$isunknown(tx.tdata[0].valid) && !$isunknown(tx.tdata[1].valid)))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tx.tdata[*].valid is undefined", $time)); + + assert_tdata_tuser_ch0_undef_when_valid_high: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) ((tx.tvalid && tx.tdata[0].valid) |-> (!$isunknown(tx.tdata[0]) && !$isunknown(tx.tuser[0])))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tx.tdata[0] or tx.tuser[0] is undefined when tx.tdata[0].valid is asserted", $time)); + + assert_tdata_tuser_ch1_undef_when_valid_high: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) ((tx.tvalid && tx.tdata[1].valid) |-> (!$isunknown(tx.tdata[1]) && !$isunknown(tx.tuser[1])))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tx.tdata[1] or tx.tuser[1] is undefined when tx.tdata[1].valid is asserted", $time)); + + assert_tvalid_tready_handshake: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) ( (tx.tvalid && ~tready) |-> ##1 tx.tvalid)) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tx.tvalid is dropped before acknowledged by tready", $time)); +// synopsys translate_on +`endif // OFS_FIM_AXIS_IF_ASSERT_OFF + +endinterface : ofs_fim_pcie_txs_axis_if + +// Interface of PCIe TX AXIS channel with 1 TLP data stream +interface ofs_fim_pcie_tx_axis_if (); + logic clk; + logic rst_n; // Active-low reset + + // struct declaration contains tvalid, tlast, tdata, and tuser signals of the AXIS channel + t_axis_pcie_tx tx; + + // Ready signal + logic tready; + + // AXI-S channel master + modport master ( + input tready, + output clk, + output rst_n, + output tx + ); + + // AXI-S channel slave + modport slave ( + output tready, + input clk, + input rst_n, + input tx + ); + +`ifdef OFS_FIM_ASSERT_OFF + `define OFS_FIM_AXIS_IF_ASSERT_OFF +`endif // OFS_FIM_ASSERT_OFF + +`ifndef OFS_FIM_AXIS_IF_ASSERT_OFF +// synopsys translate_off + logic enable_assertion; + + initial begin + enable_assertion = 1'b0; + repeat(2) + @(posedge clk); + + wait (rst_n === 1'b0); + wait (rst_n === 1'b1); + + enable_assertion = 1'b1; + end + + assert_tvalid_undef_when_not_in_reset: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (!$isunknown(tx.tvalid))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tvalid is undefined", $time)); + + assert_tready_undef_when_not_in_reset: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (!$isunknown(tready))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tready is undefined", $time)); + + assert_valid_when_tvalid_high: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (tx.tvalid |-> !$isunknown(tx.tdata.valid))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tx.tdata[*].valid is undefined when tvalid is asserted", $time)); + + assert_tdata_tuser_ch0_undef_when_valid_high: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) ( (tx.tvalid && tx.tdata.valid) |-> !$isunknown(tx.tdata) )) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tx.tdata or tx.tuser is undefined when tvalid and valid is asserted", $time)); + + assert_tvalid_tready_handshake: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) ( (tx.tvalid && ~tready) |-> ##1 tx.tvalid)) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tx.tvalid is dropped before acknowledged by tready", $time)); +// synopsys translate_on +`endif // OFS_FIM_AXIS_IF_ASSERT_OFF + +endinterface : ofs_fim_pcie_tx_axis_if + +// Interface of PCIe AXIS interrupt response channel +interface ofs_fim_afu_irq_rsp_axis_if #( + parameter TDATA_WIDTH = 24 +); + logic clk; + logic rst_n; + logic tvalid; + logic tready; + logic [TDATA_WIDTH-1:0] tdata; + + modport master ( + input tready, + output clk, rst_n, tvalid, tdata + ); + modport slave ( + output tready, + input clk, rst_n, tvalid, tdata + ); + +`ifdef OFS_FIM_ASSERT_OFF + `define OFS_FIM_AXIS_IF_ASSERT_OFF +`endif // OFS_FIM_ASSERT_OFF + +`ifndef OFS_FIM_AXIS_IF_ASSERT_OFF +// synopsys translate_off + logic enable_assertion; + + initial begin + enable_assertion = 1'b0; + repeat(2) + @(posedge clk); + + wait (rst_n === 1'b0); + wait (rst_n === 1'b1); + + enable_assertion = 1'b1; + end + + assert_tvalid_undef_when_not_in_reset: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (!$isunknown(tvalid))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tvalid is undefined", $time)); + + assert_tready_undef_when_not_in_reset: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (!$isunknown(tready))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tready is undefined", $time)); + + assert_tdata_undef_when_tvalid_high: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (tvalid |-> (!$isunknown(tdata) ))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tdata is undefined when tdata.valid is asserted", $time)); + + assert_tvalid_tready_handshake: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) ( (tvalid && ~tready) |-> ##1 tvalid)) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tvalid is dropped before acknowledged by tready", $time)); +// synopsys translate_on +`endif // OFS_FIM_AXIS_IF_ASSERT_OFF + +endinterface : ofs_fim_afu_irq_rsp_axis_if + +// Interface of AXIS IRQ channel +interface ofs_fim_irq_axis_if (); + logic clk; + logic rst_n; + logic tvalid; + + modport master ( + output clk, rst_n, tvalid + ); + modport slave ( + input clk, rst_n, tvalid + ); + +`ifdef OFS_FIM_ASSERT_OFF + `define OFS_FIM_AXIS_IF_ASSERT_OFF +`endif // OFS_FIM_ASSERT_OFF + +`ifndef OFS_FIM_AXIS_IF_ASSERT_OFF +// synopsys translate_off + logic enable_assertion; + + initial begin + enable_assertion = 1'b0; + repeat(2) + @(posedge clk); + + wait (rst_n === 1'b0); + wait (rst_n === 1'b1); + + enable_assertion = 1'b1; + end + + assert_tvalid_undef_when_not_in_reset: + assert property (@(posedge clk) disable iff (~rst_n || ~enable_assertion) (!$isunknown(tvalid))) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, tvalid is undefined", $time)); +// synopsys translate_on +`endif // OFS_FIM_AXIS_IF_ASSERT_OFF + +endinterface : ofs_fim_irq_axis_if + +`endif // __OFS_FIM_AXIS_IF_SV__ diff --git a/ipss/pcie/rtl/ofs_fim_pcie_hdr_def.sv b/ipss/pcie/rtl/ofs_fim_pcie_hdr_def.sv new file mode 100755 index 0000000..9e3aef9 --- /dev/null +++ b/ipss/pcie/rtl/ofs_fim_pcie_hdr_def.sv @@ -0,0 +1,317 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// This package contains the parameter and struct definition for commonly used +// PCIe TLP header +// +//---------------------------------------------------------------------------- + +`ifndef __OFS_FIM_PCIE_HDR_DEF_SV__ +`define __OFS_FIM_PCIE_HDR_DEF_SV__ + +package ofs_fim_pcie_hdr_def; + +// PCIe FMTTYPE +localparam PCIE_TYPE_CPL = 5'b01010; +localparam PCIE_TYPE_MEM_RW = 5'b00000; +localparam PCIE_TYPE_MSG = 5'b10000; + +localparam PCIE_FMTTYPE_MEM_READ32 = 7'b000_0000; +localparam PCIE_FMTTYPE_MEM_READ64 = 7'b010_0000; +localparam PCIE_FMTTYPE_MEM_WRITE32 = 7'b100_0000; +localparam PCIE_FMTTYPE_MEM_WRITE64 = 7'b110_0000; +localparam PCIE_FMTTYPE_CFG_WRITE = 7'b100_0100; +localparam PCIE_FMTTYPE_CPL = 7'b000_1010; +localparam PCIE_FMTTYPE_CPLD = 7'b100_1010; +localparam PCIE_FMTTYPE_SWAP32 = 7'b100_1101; +localparam PCIE_FMTTYPE_SWAP64 = 7'b110_1101; +localparam PCIE_FMTTYPE_CAS32 = 7'b100_1110; +localparam PCIE_FMTTYPE_CAS64 = 7'b110_1110; + +// 1st DW in TLP header +typedef struct packed { + logic rsvd0; + logic [6:0] fmttype; + logic rsvd1; + logic [2:0] tc; + logic [2:0] rsvd2; + logic th; + logic td; + logic ep; + logic [1:0] attr; + logic [1:0] rsvd3; + logic [9:0] length; +} t_tlp_hdr_dw0; + +// PCIe memory request TLP header +typedef struct packed { + t_tlp_hdr_dw0 dw0; + logic [15:0] requester_id; + logic [7:0] tag; + logic [3:0] last_be; + logic [3:0] first_be; + logic [31:0] addr; // MWr64/MRd64:address[63:32]; MWr32/MRd32:address[31:0] + // The interpretation of lsb_addr with 32-bit addresses varies by FIM vs. AFU + // and by PCIe hardware. Some hardware (e.g. S10 H-Tile) treats the location as + // the first DWORD. Other hardware (e.g. S10 P-Tile) ignores the location and + // consumes data from the normal payload field. The FIM handles either case and + // guarantees that the encoding of the AFU TLP stream is always consistent. + // AFUs should simply clear lsb_addr for 32-bit requests and pass data in the + // payload field. + logic [31:0] lsb_addr; // MWr64/MRd64:address[31:0]; MWr32:data[31:0]; MRd32:Rsvd +} t_tlp_mem_req_hdr; +localparam TLP_MEM_REQ_HDR_WIDTH = $bits(t_tlp_mem_req_hdr); + +// PCIe completion TLP header +typedef struct packed { + t_tlp_hdr_dw0 dw0; + logic [15:0] completer_id; + logic [2:0] status; + logic bcm; + logic [11:0] byte_count; + logic [15:0] requester_id; + logic [7:0] tag; + logic rsvd0; + logic [6:0] lower_addr; + logic [31:0] rsvd1; +} t_tlp_cpl_hdr; +localparam TLP_CPL_HDR_WIDTH = $bits(t_tlp_cpl_hdr); + +// PCIe message TLP header +typedef struct packed { + t_tlp_hdr_dw0 dw0; + logic [15:0] requester_id; + logic [7:0] tag; + logic [7:0] msg_code; + logic [31:0] lower_msg; + logic [31:0] upper_msg; +} t_tlp_msg_hdr; +localparam TLP_MSG_HDR_WIDTH = $bits(t_tlp_msg_hdr); + +// PCIe message TLP header +typedef struct packed { + t_tlp_hdr_dw0 dw0; + logic [15:0] requester_id; + logic [7:0] tag; + logic [7:0] msg_code; + logic [15:0] pci_target_id; + logic [15:0] vendor_id; + logic [31:0] upper_msg; +} t_tlp_vdm_msg_hdr; +localparam TLP_VDM_MSG_HDR_WIDTH = $bits(t_tlp_vdm_msg_hdr); + +//-------------------------------- +// Functions and tasks +//-------------------------------- +function automatic bit func_is_addr32 ( + input logic [6:0] fmttype +); + return (fmttype[5] == 1'b0); +endfunction + +function automatic bit func_is_addr64 ( + input logic [6:0] fmttype +); + return (fmttype[5] == 1'b1); +endfunction + +function automatic bit func_has_data ( + input logic [6:0] fmttype +); + return (fmttype[6] == 1'b1); +endfunction + +function automatic bit func_is_completion ( + input logic [6:0] fmttype +); + return (fmttype[4:0] == PCIE_TYPE_CPL ? 1'b1 : 1'b0); +endfunction + +function automatic bit func_is_mem_req ( + input logic [6:0] fmttype +); + return (fmttype[4:0] == PCIE_TYPE_MEM_RW ? 1'b1 : 1'b0); +endfunction + +function automatic bit func_is_msg ( + input logic [6:0] fmttype +); + return (fmttype[4:0] == PCIE_TYPE_MSG ? 1'b1 : 1'b0); +endfunction + +function automatic bit func_is_mem_req64 ( + input logic [6:0] fmttype +); + return (func_is_mem_req(fmttype) && func_is_addr64(fmttype)); +endfunction + +function automatic bit func_is_mem_req32 ( + input logic [6:0] fmttype +); + return (func_is_mem_req(fmttype) && func_is_addr32(fmttype)); +endfunction + +function automatic bit func_is_mwr_req ( + input logic [6:0] fmttype +); + return (func_is_mem_req(fmttype) && fmttype[6]) ? 1'b1 : 1'b0; +endfunction + +function automatic bit func_is_mrd_req ( + input logic [6:0] fmttype +); + return (func_is_mem_req(fmttype) && ~fmttype[6]) ? 1'b1 : 1'b0; +endfunction + +function automatic bit func_is_msgD ( + input logic [6:0] fmttype +); + return (func_is_msg(fmttype) && fmttype[6]) ? 1'b1 : 1'b0; +endfunction + +// synthesis translate_off + +function automatic string func_fmttype_to_string ( + input logic [6:0] fmttype +); + string t; + + casex (fmttype) + 7'b000_0000 : t = "MRd"; + 7'b010_0000 : t = "MRd"; + 7'b000_0001 : t = "MRdLk"; + 7'b010_0001 : t = "MRdLk"; + 7'b100_0000 : t = "MWr"; + 7'b110_0000 : t = "MWr"; + 7'b000_0010 : t = "IORd"; + 7'b100_0010 : t = "IOWr"; + 7'b000_0100 : t = "CfgRd0"; + 7'b100_0100 : t = "CfgWr0"; + 7'b000_0101 : t = "CfgRd1"; + 7'b100_0101 : t = "CfgWr1"; + 7'b011_0XXX : t = "Msg"; + 7'b111_0XXX : t = "MsgD"; + 7'b000_1010 : t = "Cpl"; + 7'b100_1010 : t = "CplD"; + 7'b000_1011 : t = "CplLk"; + 7'b100_1011 : t = "CplDLk"; + default : t = "TDB"; + endcase + + if (func_is_mem_req32(fmttype)) t = { t, "32" }; + if (func_is_mem_req64(fmttype)) t = { t, "64" }; + + return t; +endfunction + +function automatic string func_dw0_to_string ( + input t_tlp_hdr_dw0 dw0 +); + return $sformatf("%6s len 0x%x [tc %0d th %0d td %0d ep %0d attr %0d]", + func_fmttype_to_string(dw0.fmttype), + dw0.length, dw0.tc, dw0.th, dw0.td, dw0.ep, dw0.attr); +endfunction + +function automatic string func_mem_req_to_string ( + input t_tlp_mem_req_hdr hdr +); + if (func_is_addr64(hdr.dw0.fmttype)) begin + return $sformatf("%s req_id 0x%h tag 0x%h lbe 0x%h fbe 0x%h addr 0x%h%h", + func_dw0_to_string(hdr.dw0), + hdr.requester_id, hdr.tag, hdr.last_be, hdr.first_be, + hdr.addr, hdr.lsb_addr); + end + else if (func_has_data(hdr.dw0.fmttype)) begin + return $sformatf("%s req_id 0x%h tag 0x%h lbe 0x%h fbe 0x%h addr 0x%h ht-data 0x%h", + func_dw0_to_string(hdr.dw0), + hdr.requester_id, hdr.tag, hdr.last_be, hdr.first_be, + hdr.addr, hdr.lsb_addr); + end + else begin + return $sformatf("%s req_id 0x%h tag 0x%h lbe 0x%h fbe 0x%h addr 0x%h", + func_dw0_to_string(hdr.dw0), + hdr.requester_id, hdr.tag, hdr.last_be, hdr.first_be, + hdr.addr); + end +endfunction + +function automatic string func_cpl_to_string ( + input t_tlp_cpl_hdr hdr +); + return $sformatf("%s cpl_id 0x%h st %h bcm %h bytes 0x%h req_id 0x%h tag 0x%h low_addr 0x%h", + func_dw0_to_string(hdr.dw0), + hdr.completer_id, hdr.status, hdr.bcm, hdr.byte_count, + hdr.requester_id, hdr.tag, hdr.lower_addr); +endfunction + +function automatic string func_msg_to_string ( + input t_tlp_msg_hdr hdr +); + return $sformatf("%s req_id 0x%h tag 0x%h code 0x%h lower 0x%h upper 0x%h", + func_dw0_to_string(hdr.dw0), + hdr.requester_id, hdr.tag, hdr.msg_code, + hdr.lower_msg, hdr.upper_msg); +endfunction + +function automatic string func_hdr_to_string ( + input logic [127:0] hdr +); + // Pick any header type to extract dw0 and the fmttype + t_tlp_mem_req_hdr mem_req = hdr; + t_tlp_hdr_dw0 dw0 = mem_req.dw0; + + string s; + if (func_is_mem_req(dw0.fmttype)) begin + s = func_mem_req_to_string(hdr); + end + else if (func_is_completion(dw0.fmttype)) begin + s = func_cpl_to_string(hdr); + end + else begin + s = func_msg_to_string(hdr); + end + + return s; +endfunction + +// Standard formatting of the contents of a channel +function automatic string func_flit_to_string ( + input logic sop, + input logic eop, + input t_tlp_mem_req_hdr hdr, + input logic [255:0] payload +); + string s; + + if (sop) + begin + // Format payload as a string if flit has data + string payload_str = ""; + if (func_has_data(hdr.dw0.fmttype)) begin + payload_str = $sformatf(" data 0x%x", payload); + end + + s = $sformatf("%s%s%s%s", + (sop ? "sop " : ""), + (eop ? "eop " : ""), + func_hdr_to_string(hdr), + payload_str); + end + else + begin + s = $sformatf(" %s data 0x%x", + (eop ? "eop " : ""), + payload); + end + + return s; +endfunction + +// synthesis translate_on + +endpackage : ofs_fim_pcie_hdr_def + +`endif // __OFS_FIM_PCIE_HDR_DEF_SV__ diff --git a/ipss/pcie/rtl/ofs_fim_pcie_pkg.sv b/ipss/pcie/rtl/ofs_fim_pcie_pkg.sv new file mode 100755 index 0000000..6af1305 --- /dev/null +++ b/ipss/pcie/rtl/ofs_fim_pcie_pkg.sv @@ -0,0 +1,268 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Package contains parameter and struct definition used in PCIe subsystem +// +//----------------------------------------------------------------------------- + +`ifndef __OFS_FIM_PCIE_PKG_SV__ +`define __OFS_FIM_PCIE_PKG_SV__ + +`include "fpga_defines.vh" + +package ofs_fim_pcie_pkg; + import ofs_fim_pcie_hdr_def::*; + +// PCIe AVST channel parameters +localparam PCIE_LANES = 16; +localparam NUM_AVST_CH = 2; + +localparam NUM_PF = 2; +localparam NUM_VF = 4; +localparam PF_WIDTH = (NUM_PF < 2) ? 1 : $clog2(NUM_PF); +localparam VF_WIDTH = (NUM_VF < 2) ? 1 : $clog2(NUM_VF); + +localparam PCIE_EP_MAX_TAGS = 128; +localparam PCIE_EP_TAG_WIDTH = $clog2(PCIE_EP_MAX_TAGS); + +localparam PCIE_HDR_WIDTH = 128; +localparam PCIE_MAX_LEN = 1024; // DW +localparam PCIE_MAX_LEN_WIDTH = $clog2(PCIE_MAX_LEN)+1; + +localparam AVST_HW = PCIE_HDR_WIDTH; +localparam AVST_DW = 256; // AVST data width +localparam AVST_EW = $clog2(AVST_DW/32); +localparam AVST_DWORD_LEN = (AVST_DW/32); // DWords in AVST data +localparam AVST_DWORD_LEN_WIDTH = $clog2(AVST_DWORD_LEN); + +localparam HDR_3DW_LEN = 3; +localparam HDR_4DW_LEN = 4; +localparam NON_SOP_DWORD_LEN = AVST_DWORD_LEN; +localparam SOP_3DW_DWORD_LEN = (AVST_DWORD_LEN - HDR_3DW_LEN); +localparam SOP_4DW_DWORD_LEN = (AVST_DWORD_LEN - HDR_4DW_LEN); + +localparam PCIE_CPL_CREDIT = 2500; // 16B (4DW) unit +localparam CPL_CREDIT_DWORD = PCIE_CPL_CREDIT*4; // PCIE_CPL_CREDIT is in 4DW unit, change it to DW unit +localparam CPL_CREDIT_WIDTH = $clog2(CPL_CREDIT_DWORD); +`ifdef SIM_PCIE_CPL_TIMEOUT + `ifdef SIM_PCIE_CPL_TIMEOUT_CYCLES + localparam PCIE_CPL_TIMEOUT = `SIM_PCIE_CPL_TIMEOUT_CYCLES; + `else + localparam PCIE_CPL_TIMEOUT = 26'd256; + `endif +`else + localparam PCIE_CPL_TIMEOUT = 26'd12500000; +`endif +localparam CPL_TIME_WIDTH = 26; + +typedef enum logic {HDR_3DW, HDR_4DW} t_hdr_len; + +typedef logic [PCIE_EP_TAG_WIDTH-1:0] t_tlp_tag; + +typedef logic [NUM_AVST_CH-1:0] t_avst_ch; + +typedef struct packed { + logic [VF_WIDTH-1:0] vfn; + logic [PF_WIDTH-1:0] pfn; + logic vf_active; +} t_tlp_func; + +typedef struct packed { + logic err_malformed_eop; + logic err_malformed_sop; + logic err_poison; + logic err_parity; + logic err_cpl_timeout; + logic err_cpl_status; + logic err_unexp_cpl; + logic err_fmttype; +} t_tlp_err; +localparam TLP_ERR_WIDTH = $bits(t_tlp_err); + +typedef struct packed { + logic rx_fifo_overflow; + t_tlp_err tlp_err; +} t_pcie_err; +localparam PCIE_ERR_WIDTH = $bits(t_pcie_err); + +// UMSG code to be ignored by PCIe checker +typedef enum logic [7:0] { + UMSG_CODE_PM_PME = 8'h19, + UMSG_CODE_SET_SLOT_PWR_LIMIT = 8'h50, + UMSG_CODE_VENDOR_TYPE_1 = 8'h7f +} umsg_code_t; + +// PCIe IP AVST RX interface signals +`ifdef HTILE + typedef struct packed { + logic valid; + logic sop; + logic eop; + logic [AVST_EW-1:0] empty; + logic [AVST_DW-1:0] data; + logic [2:0] bar; + logic vf_active; + logic [PF_WIDTH-1:0] pfn; + logic [VF_WIDTH-1:0] vfn; + logic mmio_req; + } t_avst_pcie_rx; +`elsif PTILE + typedef struct packed { + logic valid; + logic sop; + logic eop; + logic [AVST_HW-1:0] hdr; + logic [AVST_EW-1:0] empty; + logic [AVST_DW-1:0] data; + logic [2:0] bar; + logic vf_active; + logic [PF_WIDTH-1:0] pfn; + logic [VF_WIDTH-1:0] vfn; + logic mmio_req; + } t_avst_pcie_rx; +`endif +localparam PCIE_RX_AVST_IF_WIDTH = $bits(t_avst_pcie_rx); + +typedef t_avst_pcie_rx [NUM_AVST_CH-1:0] t_avst_rxs; + +// PCIe IP AVST TX interface signals +`ifdef HTILE + typedef struct packed { + logic valid; + logic sop; + logic eop; + logic [AVST_DW-1:0] data; + logic vf_active; + } t_avst_pcie_tx; +`elsif PTILE + typedef struct packed { + logic valid; + logic sop; + logic eop; + logic [AVST_HW-1:0] hdr; + logic [AVST_DW-1:0] data; + logic vf_active; + } t_avst_pcie_tx; +`endif +localparam PCIE_TX_AVST_IF_WIDTH = $bits(t_avst_pcie_tx); + +typedef t_avst_pcie_tx [NUM_AVST_CH-1:0] t_avst_txs; + +//-------------------------------- +// Functions and tasks +//-------------------------------- +// Increment a tag, which may have a space that isn't a power of 2. +function automatic t_tlp_tag incr_tlp_tag(t_tlp_tag tag); + t_tlp_tag tag_next; + tag_next = tag + 1'b1; + + // If the tag space isn't a power of 2 and the current tag is + // the maximum value, wrap to 0. + if ( (PCIE_EP_MAX_TAGS != 2 ** PCIE_EP_TAG_WIDTH) && + (tag == t_tlp_tag'(PCIE_EP_MAX_TAGS - 1))) + begin + tag_next = t_tlp_tag'(0); + end + + return tag_next; +endfunction + +function automatic logic [127:0] func_get_hdr ( + input t_avst_pcie_rx rx +); + `ifdef HTILE + for (int i=0; i<=3; i=i+1) begin + func_get_hdr[i*32+:32] = rx.data[(3-i)*32+:32]; + end + `else + func_get_hdr = rx.hdr; + `endif +endfunction + +function automatic logic [127:0] func_get_tx_hdr ( + input t_avst_pcie_tx tx +); + `ifdef HTILE + for (int i=0; i<=3; i=i+1) begin + func_get_tx_hdr[i*32+:32] = tx.data[(3-i)*32+:32]; + end + `else + func_get_tx_hdr = tx.hdr; + `endif +endfunction + +function automatic logic [31:0] func_get_hdr_dw0 ( + input t_avst_pcie_rx rx +); + `ifdef HTILE + func_get_hdr_dw0 = rx.data[31:0]; + `else + func_get_hdr_dw0 = rx.hdr[127:96]; + `endif +endfunction + + +// synthesis translate_off + +// Standard formatting of the contents of an RX channel +function automatic string func_rx_to_string ( + input t_avst_pcie_rx rx +); + string s; + + if (rx.sop) + begin + logic [127:0] hdr; + hdr = func_get_hdr(rx); + + s = $sformatf("%s%s%s raw data 0x%x", + (rx.sop ? "sop " : ""), + (rx.eop ? "eop " : ""), + ofs_fim_pcie_hdr_def::func_hdr_to_string(hdr), + rx.data); + end + else + begin + s = $sformatf(" %s data 0x%x", + (rx.eop ? "eop " : ""), + rx.data); + end + + return s; +endfunction + +// Standard formatting of the contents of a TX channel +function automatic string func_tx_to_string ( + input t_avst_pcie_tx tx +); + string s; + + if (tx.sop) + begin + logic [127:0] hdr; + hdr = func_get_tx_hdr(tx); + + s = $sformatf("%s%s%s raw data 0x%x", + (tx.sop ? "sop " : ""), + (tx.eop ? "eop " : ""), + ofs_fim_pcie_hdr_def::func_hdr_to_string(hdr), + tx.data); + end + else + begin + s = $sformatf(" %s data 0x%x", + (tx.eop ? "eop " : ""), + tx.data); + end + + return s; +endfunction + +// synthesis translate_on + +endpackage : ofs_fim_pcie_pkg + +`endif // __OFS_FIM_PCIE_PKG_SV__ diff --git a/ipss/pcie/rtl/pcie_bridge.sv b/ipss/pcie/rtl/pcie_bridge.sv new file mode 100755 index 0000000..3c63be5 --- /dev/null +++ b/ipss/pcie/rtl/pcie_bridge.sv @@ -0,0 +1,261 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Functions: +// * Adapt PCIe HIP IP AVST RX interface to AXI4-S RX streaming interface +// * Adapt AXI4-S TX streaming interface to PCIe HIP IP AVST TX interface +// * Check TLP packets received on the AVST RX interface +// +//----------------------------------------------------------------------------- + +import ofs_fim_pcie_pkg::*; +import ofs_fim_if_pkg::*; + +module pcie_bridge ( + // FIM clock and reset + input logic fim_clk, + input logic fim_rst_n, + + // PCIE AVST Interface + input logic avl_clk, + input logic avl_rst_n, + + input t_avst_rxs avl_rx_st, + output logic avl_rx_ready, + output t_avst_txs avl_tx_st, + input logic avl_tx_ready, + + // FIM AXI-S channels + ofs_fim_pcie_rxs_axis_if.master fim_axis_rx_st, + ofs_fim_pcie_txs_axis_if.slave fim_axis_tx_st, + + // Error sideband signals to upstream PCIe IP + output logic b2a_app_err_valid, + output logic [31:0] b2a_app_err_hdr, + output logic [10:0] b2a_app_err_info, + output logic [1:0] b2a_app_err_func_num, + + // Error signals to PCIe error status registers + output logic chk_rx_err, + output logic chk_rx_err_vf_act, + output logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] chk_rx_err_pfn, + output logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] chk_rx_err_vfn, + output logic [31:0] chk_rx_err_code +); + +localparam MRW_TYPE = 5'b00000; +localparam CPL_TYPE = 5'b01010; + +t_avst_ch rx_st_valid; + +logic fifo_wreq; +logic fifo_rdreq; +logic fifo_almfull; +logic fifo_full; +logic fifo_empty; +logic fifo_rvalid; + +t_avst_rxs fifo_dout, fifo_dout_q; +t_avst_ch fifo_rx_valid; +t_avst_ch fifo_rx_sop; + +t_avst_rxs fifo_avl_rx_st; +logic fifo_avl_rx_ready; + +t_avst_rxs chk_avl_rx_st; +logic chk_avl_rx_ready; + +t_avst_rxs fim_avl_rx_st; +logic fim_avl_rx_ready; + +logic tx_mrd_valid; +logic [PCIE_EP_TAG_WIDTH-1:0] tx_mrd_tag; +logic [PCIE_MAX_LEN_WIDTH-1:0] tx_mrd_length; +logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] tx_mrd_pfn; +logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] tx_mrd_vfn; +logic tx_mrd_active; + +logic cpl_pending_data_add; +logic [7:0] cpl_pending_data_add_val; +logic [CPL_CREDIT_WIDTH-1:0] cpl_pending_data_cnt; + +ofs_fim_pcie_txs_axis_if pcie_axis_tx_if(); + +t_tlp_err chk_tlp_err; +logic rx_avst_fifo_overflow; + +//----------------------------------------------------------------------------- +logic fifo_rdack; + +assign avl_rx_ready = ~fifo_almfull; + +always_comb begin + for (int i=0; i 1) begin + fifo_avl_rx_st[1].valid = fifo_rvalid && fifo_dout[1].valid; + end +end + +always_ff @(posedge avl_clk) begin + if (~avl_rst_n) begin + rx_avst_fifo_overflow <= 1'b0; + end else begin + if (fifo_full && |rx_st_valid) begin + rx_avst_fifo_overflow <= 1'b1; + end + end +end + +// synthesis translate_off + assert_rx_avst_fifo_overflow : + assert property ( @(posedge avl_clk) disable iff (~avl_rst_n) (fifo_full |-> ~|rx_st_valid) ) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, rx_avst_fifo overflow", $time)); +// synthesis translate_on + + +//----------------------------- +// RX TLP checker and CPL timeout tracker +//----------------------------- +// The checker doesn't backpressure the RX AVST FIFO. +// Backpressuring is implemented in the downstream pcie_rx_bridge +// The bridge makes sure there is enough "credit" to cover the latency +// along the packet datapath FIFO-checker-bridge +// + +logic tx_mrd_vf_act; + +pcie_checker #( + .ENABLE_MALFORMED_TLP_CHECK (1), + .ENABLE_COMPLETION_TIMEOUT_CHECK (1) +) pcie_checker ( + .avl_clk (avl_clk), + .avl_rst_n (avl_rst_n), + + // Rx + .i_avl_rx_st (fifo_avl_rx_st), + .o_avl_rx_ready (fifo_avl_rx_ready), + + .o_avl_rx_st (chk_avl_rx_st), + .i_avl_rx_ready (chk_avl_rx_ready), + + // TX MRd + .tx_mrd_valid (tx_mrd_valid), + .tx_mrd_length (tx_mrd_length), + .tx_mrd_tag (tx_mrd_tag), + .tx_mrd_pfn (tx_mrd_pfn), + .tx_mrd_vfn (tx_mrd_vfn), + .tx_mrd_vf_act (tx_mrd_vf_act), + .cpl_pending_data_cnt (cpl_pending_data_cnt), + + // Error reporting to PCIe IP + .b2a_app_err_valid (b2a_app_err_valid), + .b2a_app_err_hdr (b2a_app_err_hdr), + .b2a_app_err_info (b2a_app_err_info), + .b2a_app_err_func_num (b2a_app_err_func_num), + + // Error reporting to PCIe feature CSR + .chk_rx_err (chk_rx_err), + .chk_rx_err_vf_act (chk_rx_err_vf_act), + .chk_rx_err_pfn (chk_rx_err_pfn), + .chk_rx_err_vfn (chk_rx_err_vfn), + .chk_rx_err_code (chk_tlp_err) +); + +// avl_clk - fim_clk clock domain crossing +pcie_bridge_cdc pcie_bridge_cdc ( + .pcie_clk (avl_clk), + .pcie_rst_n (avl_rst_n), + + .fim_clk (fim_clk), + .fim_rst_n (fim_rst_n), + + //---------------------- + // PCIe RX bridge + //---------------------- + // AVST sink interface + .pcie_avl_rx_st (chk_avl_rx_st), + .pcie_avl_rx_ready (chk_avl_rx_ready), + + // AVST source interface + .fim_avl_rx_st (fim_avl_rx_st), + .fim_avl_rx_ready (fim_avl_rx_ready), + + //---------------------- + // PCIe TX bridge + //---------------------- + // AXIS slave interface + .fim_axis_tx_st (fim_axis_tx_st), + + // AXIS master interface + .pcie_axis_tx_st (pcie_axis_tx_if) +); + +// AVST interface to AXIS interface adapter +// (Both interfaces clocked by fim_clk) +pcie_rx_bridge pcie_rx_bridge ( + .avl_clk (fim_clk), + .avl_rst_n (fim_rst_n), + .avl_rx_st (fim_avl_rx_st), + .avl_rx_ready (fim_avl_rx_ready), + .axis_rx_st (fim_axis_rx_st) +); + +// AXIS interface to AVST interface adapter +// (Both interfaces clocked by avl_clk) +pcie_tx_bridge pcie_tx_bridge ( + .avl_clk (avl_clk), + .avl_rst_n (avl_rst_n), + .avl_tx_ready (avl_tx_ready), + .avl_tx_st (avl_tx_st), + .axis_tx_st (pcie_axis_tx_if), + + .tx_mrd_valid (tx_mrd_valid), + .tx_mrd_length (tx_mrd_length), + .tx_mrd_tag (tx_mrd_tag), + .tx_mrd_pfn (tx_mrd_pfn), + .tx_mrd_vfn (tx_mrd_vfn), + .tx_mrd_vf_act (tx_mrd_vf_act), + + .cpl_pending_data_cnt (cpl_pending_data_cnt) +); + +// Error output +assign chk_rx_err_code = {rx_avst_fifo_overflow, chk_tlp_err}; + +endmodule diff --git a/ipss/pcie/rtl/pcie_bridge_cdc.sv b/ipss/pcie/rtl/pcie_bridge_cdc.sv new file mode 100755 index 0000000..6ab33c2 --- /dev/null +++ b/ipss/pcie/rtl/pcie_bridge_cdc.sv @@ -0,0 +1,58 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Functions: +// * Clock crossing between PCIE clock domain and FIM clock domain +// +//----------------------------------------------------------------------------- + +import ofs_fim_pcie_pkg::*; +import ofs_fim_if_pkg::*; + +module pcie_bridge_cdc ( + input logic pcie_clk, + input logic pcie_rst_n, + + input logic fim_clk, + input logic fim_rst_n, + + input t_avst_rxs pcie_avl_rx_st, + output logic pcie_avl_rx_ready, + + output t_avst_rxs fim_avl_rx_st, + input logic fim_avl_rx_ready, + + ofs_fim_pcie_txs_axis_if.slave fim_axis_tx_st, + ofs_fim_pcie_txs_axis_if.master pcie_axis_tx_st +); + +//----------------------------------------------------------------------------- +// module instantion of PCIe RX bridge CDC +//----------------------------------------------------------------------------- +pcie_rx_bridge_cdc rx_cdc ( + .pcie_clk (pcie_clk), + .pcie_rst_n (pcie_rst_n), + .pcie_avl_rx_st (pcie_avl_rx_st), + .pcie_avl_rx_ready (pcie_avl_rx_ready), + + .fim_clk (fim_clk), + .fim_rst_n (fim_rst_n), + .fim_avl_rx_st (fim_avl_rx_st), + .fim_avl_rx_ready (fim_avl_rx_ready) +); + +//----------------------------------------------------------------------------- +// module instantion of PCIe TX bridge CDC +//----------------------------------------------------------------------------- +pcie_tx_bridge_cdc tx_cdc ( + .pcie_clk (pcie_clk), + .pcie_rst_n (pcie_rst_n), + .fim_axis_tx_st (fim_axis_tx_st), + .pcie_axis_tx_st (pcie_axis_tx_st) +); + +endmodule + diff --git a/ipss/pcie/rtl/pcie_ch0_align_tx.sv b/ipss/pcie/rtl/pcie_ch0_align_tx.sv new file mode 100644 index 0000000..29e00a8 --- /dev/null +++ b/ipss/pcie/rtl/pcie_ch0_align_tx.sv @@ -0,0 +1,151 @@ +// Copyright 2021 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Realign the AXI-S PCIe TX stream so that SOP typically begins on ch0. +// The PCIe SS adapter tends to put SOP in ch1 and the downstream PCIe +// bridge is more efficient when SOP is in ch0. +// +//----------------------------------------------------------------------------- + +`include "fpga_defines.vh" + +module pcie_ch0_align_tx + ( + input logic clk, + input logic rst_n, + + ofs_fim_pcie_txs_axis_if.slave axis_tx_st_in, + ofs_fim_pcie_txs_axis_if.master axis_tx_st_out + ); + + import ofs_fim_if_pkg::*; + import ofs_fim_pcie_pkg::*; + + assign axis_tx_st_out.clk = axis_tx_st_in.clk; + assign axis_tx_st_out.rst_n = axis_tx_st_in.rst_n; + + t_axis_pcie_txs tx_in; + assign tx_in = axis_tx_st_in.tx; + + generate + if (FIM_PCIE_TLP_CH != 2) + begin + // The code in this module is optimized for two parallel TLP + // channels. If the configuration is something else, just pass + // the messages straight through. + assign axis_tx_st_in.tready = axis_tx_st_out.tready; + assign axis_tx_st_out.tx = tx_in; + end + else + begin + // Preserved TX message from previous cycle, not yet forwarded + // if prev_tx.tvalid is set. + t_axis_pcie_txs prev_tx; + + // Construct the output stream, either from the input directly or + // by shifting the input using a combination of state from the previous + // message plus the current input. + always_comb + begin + axis_tx_st_in.tready = 1'b0; + + axis_tx_st_out.tx = tx_in; + axis_tx_st_out.tx.tvalid = 1'b0; + + if (prev_tx.tvalid) + begin + if (prev_tx.tdata[1].eop) + begin + // Previous message saved, but it is the end of a command. + // Send just the EOP and don't consume the input stream. + axis_tx_st_in.tready = 1'b0; + axis_tx_st_out.tx.tvalid = 1'b1; + axis_tx_st_out.tx.tlast = 1'b1; + axis_tx_st_out.tx.tdata[0] = prev_tx.tdata[1]; + axis_tx_st_out.tx.tdata[1] = '0; + axis_tx_st_out.tx.tuser[0] = prev_tx.tuser[1]; + axis_tx_st_out.tx.tuser[1] = '0; + end + else + begin + // Shift the input, combining the previous message and + // the new one. The part of the new message that doesn't + // fit will be stored in prev_tx below. + axis_tx_st_in.tready = axis_tx_st_out.tready; + axis_tx_st_out.tx.tvalid = tx_in.tvalid; + axis_tx_st_out.tx.tlast = tx_in.tdata[0].eop; + axis_tx_st_out.tx.tdata[0] = prev_tx.tdata[1]; + axis_tx_st_out.tx.tdata[1] = tx_in.tdata[0]; + axis_tx_st_out.tx.tuser[0] = prev_tx.tuser[1]; + axis_tx_st_out.tx.tuser[1] = tx_in.tuser[0]; + end + end + else if (tx_in.tvalid) + begin + if (tx_in.tdata[0].valid) + begin + // Slot 0 is used and no previous state recorded. Pass through. + axis_tx_st_in.tready = axis_tx_st_out.tready; + axis_tx_st_out.tx.tvalid = 1'b1; + end + else if (tx_in.tdata[1].valid && + tx_in.tdata[1].sop && !tx_in.tdata[1].eop) + begin + // Consume the input, but it will only be saved in prev_tx + // below. The channel 1 SOP will be moved to channel 0. + axis_tx_st_in.tready = 1'b1; + axis_tx_st_out.tx.tvalid = 1'b0; + end + else + begin + // If a message exists in the input stream, it is only + // in channel 1 and is also eop. Shift it to channel 0. + axis_tx_st_in.tready = axis_tx_st_out.tready; + axis_tx_st_out.tx.tvalid = tx_in.tdata[1].valid; + axis_tx_st_out.tx.tdata[0] = tx_in.tdata[1]; + axis_tx_st_out.tx.tuser[0] = tx_in.tuser[1]; + axis_tx_st_out.tx.tdata[1].valid = 1'b0; + axis_tx_st_out.tx.tdata[1].sop = 1'b0; + axis_tx_st_out.tx.tdata[1].eop = 1'b0; + end + end + end + + always_ff @(posedge clk) + begin + // A message was passed to the outbound interface, so whatever + // was in prev_tx is now gone. + if (axis_tx_st_out.tready && axis_tx_st_out.tx.tvalid) + begin + prev_tx.tvalid <= 1'b0; + end + + // Something came from the input stream. Does it need to be stored + // in prev_tx or was it forwarded completely to the output stream? + if (axis_tx_st_in.tready && tx_in.tvalid) + begin + prev_tx <= tx_in; + // Slot 1 is not forwarded immediately if: + // - There was previously buffered state. In this case, slot + // 0 will be forwarded directly, but slot 1 won't fit so + // must be saved. + // - Slot 0 of the input is empty and slot 1 begins but does + // not end a new command. + prev_tx.tvalid <= tx_in.tdata[1].valid && + (prev_tx.tvalid || + (!tx_in.tdata[0].valid && tx_in.tdata[1].valid && + tx_in.tdata[1].sop && !tx_in.tdata[1].eop)); + end + + if (!rst_n) + begin + prev_tx.tvalid <= 1'b0; + end + end + end + endgenerate + +endmodule // pcie_ch0_align_tx diff --git a/ipss/pcie/rtl/pcie_checker.sv b/ipss/pcie/rtl/pcie_checker.sv new file mode 100755 index 0000000..88af68b --- /dev/null +++ b/ipss/pcie/rtl/pcie_checker.sv @@ -0,0 +1,1407 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Functions: +// PCIe TLP checker & completion tracker +// +// The checker can only process 1 TLP of the same type on a single clock cycle. +// Examples of TLP combinations on AVST channel 0 and channel 1 that can't be processed in single cycle +// --------------------------------- +// | No | CH0 | CH1 | +// --------------------------------- +// | 1 | {MMIO SOP} | {MMIO SOP} | +// | 2 | {CPL* SOP} | {CPL* SOP} | +// | 3 | {CPLD EOP} | {CPL* SOP} | +// --------------------------------- +// +// The checker supports: +// * H-TILE and P-TILE x8 and x16 PCIe IP interface format +// * H-TILE: avst data channel contains both header and data +// * P-TILE: separate avst channel for header and data +// * H-TILE and P-TILE PCIe IP variants with single 256-bit channel (PCIe Gen3x8, PCIe Gen4x8) +// * H-TILE and P-TILE PCIe IP variants with two 256-bit channels (PCIe Gen3x16, PCIe Gen4x16) +// +// Clock domain : avl_clk +// Reset : avl_rst_n +// +//----------------------------------------------------------------------------- + +`include "vendor_defines.vh" +`include "fpga_defines.vh" +import ofs_fim_cfg_pkg::*; +import ofs_fim_pcie_pkg::*; +import ofs_fim_if_pkg::*; + +module pcie_checker #( + parameter ENABLE_MALFORMED_TLP_CHECK = 0, // 0:DISABLE 1:ENABLE + parameter ENABLE_COMPLETION_TIMEOUT_CHECK = 0 // 0:DISABLE 1:ENABLE +)( + input logic avl_clk, + input logic avl_rst_n, + + // Input RX TLP from upstream + input t_avst_rxs i_avl_rx_st, // AVST RX channels carrying Rx TLP from upstream logic + output logic o_avl_rx_ready, // Backpressure signal to upstream logic + + // Output RX TLP to downstream + output t_avst_rxs o_avl_rx_st, // AVST RX channels carrying Rx TLP to downstream logic + input logic i_avl_rx_ready, // Backpressure signal from downstream logic + + // Header fields of MRd requests that are sent upstream + // The header info is stored in mrd_rid_ram and is used to track unexpected cpl/cpld + // When a MRd request is sent upstream, the cpl_pending_data_cnt counter is incremented with the data length in the MRd request + input logic tx_mrd_valid, // Write to mrd_rid_ram; increment pending MRd data count + input logic [PCIE_MAX_LEN_WIDTH-1:0] tx_mrd_length, // MRd request data length + input logic [PCIE_EP_TAG_WIDTH-1:0] tx_mrd_tag, // MRd request tag + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] tx_mrd_pfn, // MRd request requester ID (PF) + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] tx_mrd_vfn, // MRd request requester ID (VF) + input logic tx_mrd_vf_act, // MRd request is sent by PF or VF + + // Current amount of data pending completion from host (for MRd requests sent to host) + output logic [CPL_CREDIT_WIDTH-1:0] cpl_pending_data_cnt, + + // Error sideband signals to upstream PCIe IP + output logic b2a_app_err_valid, // Error is detected in the incoming TLP + output logic [31:0] b2a_app_err_hdr, // Header of the erroneous TLP + output logic [10:0] b2a_app_err_info, // Info of the error + output logic [1:0] b2a_app_err_func_num, // Function number associated with the erroneous TLP + + // Error signals to PCIe error status registers + output logic chk_rx_err, // Error is detected in the incoming TLP + output logic chk_rx_err_vf_act, // Indicates if error is associated with PF or VF + output logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] chk_rx_err_pfn, // PF associated with the erroneous TLP + output logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] chk_rx_err_vfn, // VF associated with the erroneous TLP + output t_tlp_err chk_rx_err_code // Error info +); + +import ofs_fim_pcie_hdr_def::*; + +enum {T0, T1, T2} e_pipeln_stage; +localparam PIPELN = 2; + +enum {CH0, CH1} e_channel; +enum {MEM_WR, MEM_RD, CPL, CPLD, MSG, MAX_TLP_TYPE} e_tlp_type; +typedef logic [NUM_AVST_CH-1:0] t_ch; + +// MMIO struct +typedef struct packed { + logic mmio_req; + logic [2:0] bar; + t_tlp_func func; +} t_mmio_info; + +// Maximum data length in a non-SOP packet +localparam bit [PCIE_MAX_LEN_WIDTH-1:0] L_MAX_DATA_LEN = NON_SOP_DWORD_LEN[PCIE_MAX_LEN_WIDTH-1:0]; +localparam bit [PCIE_MAX_LEN_WIDTH-1:0] L_MAX_DATA_LEN_X2 = L_MAX_DATA_LEN*2; + +//------------------- +// Backpressure +//------------------- +logic dn_ready; // Downstream channel ready status to checker +logic ready; // Checker ready status back to upstream logic + +//------------------- +// Error status +//------------------- +t_tlp_err err_status_reg; +t_tlp_err [NUM_AVST_CH-1:0] err_status_t0, err_status; + +// Completion timeout error +logic err_cpl_timeout; +logic err_cpl_timeout_vf_act; +logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] err_cpl_timeout_pfn; +logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] err_cpl_timeout_vfn; + +// Unsupported request/response +t_ch err_fmttype_c; + +// Unexpected CPL/CPLD +t_ch err_unexp_cpl_c; + +// CPL status error +t_ch err_cpl_status_c; + +// Poison bit error +t_ch err_poison_c; + +// Malformed packet +t_ch err_sop; // Unexpected SOP in single cycle TLP +t_ch err_eop; // Unexpected EOP in single cycle TLP +t_ch err_sop_mc; // Unexpected SOP in multi-cycle TLP +t_ch err_eop_mc; // Unexpected EOP in multi-cycle TLP + +//------------------- +// Block erroneous TLP +//------------------- +t_ch block_err_tlp; // Block erroneous TLP from going downstream +t_ch block_unexp_cpl; // Block unexpected completion from going downstream +t_ch block_tlp; +logic invalid_prev_tlp; // Indicates if current TLP is part of an erroneous TLP detected earlier + +//------------------- +// RX TLP processing +//------------------- +// Detect if two cycles is required to process the incoming TLPs +logic enable_split; +logic second_tlp_valid; +logic first_tlp_cycle; // New TLP is received (or the first TLP in a two-cycle processing) +logic second_tlp_cycle; // Second cycle of TLP processing + +// Two-stage pipelines of incoming RX TLP +// (input) (stage 1) (stage 2) +// rx_tlp_pipeln[T0]-> rx_tlp_pipeln[T1]-> rx_tlp_pipeln[T2] (rx_tlp)-> rx_tlp_out +// +t_avst_rxs [PIPELN:0] rx_tlp_pipeln; +t_avst_rxs rx_tlp; + +t_ch sop; // Start-of-packet +t_ch sop_has_payload; // Current TLP contains data payload +t_ch eop_t1, eop; // End-of-packet + +// DW0 in TLP header of each pipeline stage +t_tlp_hdr_dw0 [NUM_AVST_CH-1:0] rx_hdr_dw0_t0, rx_hdr_dw0_t1, rx_hdr_dw0; + +// fmttype field in TLP header of each pipeline stage +logic [NUM_AVST_CH-1:0][6:0] rx_fmttype_t0, rx_fmttype_t1, rx_fmttype; + +// TLP type 1-hot bit vector : the corresponding bit in the vector is set +// based on the type of current TLP in rx_tlp and rx_tlp_pipeln[T1] +logic [NUM_AVST_CH-1:0][MAX_TLP_TYPE-1:0] tlp_type, tlp_type_t1; + +// TLP header +t_tlp_cpl_hdr [NUM_AVST_CH-1:0] cpl_hdr_t0, cpl_hdr_t1, cpl_hdr; // CPL/CPLD +t_tlp_msg_hdr [NUM_AVST_CH-1:0] msg_hdr; // MSG + +t_ch is_mmio_t1, is_mmio; + +t_ch rx_poison; // Poison bit is set in current TLP +t_ch is_completion_t0, is_completion_t1, is_completion; // Is CPL/CPLD? +logic cpld_active; // Is multi-cycle CPLD active? + +// Function associated with current TLP stream the checker is processing +t_tlp_func [NUM_AVST_CH-1:0] rx_func, rx_func_q; +// Stores the function of an active multi-cycle TLP stream +t_tlp_func mc_rx_func, mc_rx_func_q; +// Function number of a MRd request that has hit completion timeout +t_tlp_func cpl_timeout_func; +// Function associated with current erroneous TLP +t_tlp_func err_func_reg; + + +//----------------------------------------------------------------------------- +// 'i_avl_rx_ready' is driven by FIFO almfull flag downstream, we can safely assume +// it will be asserted when FIFO almost full flag is de-asserted +// and there is enough buffer in the FIFO to accept additional packets after almfull +// due to pipeline stages on the FIFO input datapath +// +// Checker accepts new TLP from upstream when the following conditions are TRUE, indicated by ready=1 +// * No active TLP downstream pending acknolwedgement (i_avl_rx_ready=1) +// * Current TLP packet(s) on the channel(s) does not require split transaction (two-cycle processing) +// * Checker has finished processing the second TLP of a split transaction + +// Backpressure signal from downstream +assign dn_ready = i_avl_rx_ready; + +// Backpressure signal to upstream +assign o_avl_rx_ready = ready; + +// Ready to consume next TLP +assign ready = ~enable_split && dn_ready; + +// RX TLP pipelines +assign rx_tlp = rx_tlp_pipeln[T2]; + +always_ff @(posedge avl_clk) begin + for (int ch=0; ch 1) begin + if (dn_ready) begin + if (enable_split) + begin + enable_split <= 1'b0; + end else if (&is_mmio_t1 || &is_completion_t1) + begin // Two MMIO requests on the same cycle OR two CPL/CPLD on the same cycle + enable_split <= 1'b1; + end else if (cpld_active && is_completion_t1[CH1]) + begin // End of multi-cycle CPLD on channel 0 and start of CPL/CPLD on channel 1 + enable_split <= 1'b1; + end + end + end + end +end + +// second_tlp_valid indicates it is ok to process the packet on channel 1 in a two-cycle processing +// second_tlp_valid is asserted on the same cycle the TLP on channel 0 is sent downstream (if not blocked due to error) +// and remains asserted until the first TLP is acknowledged by downstream receiver (downstream ready signal is asserted) +always_ff @(posedge avl_clk) begin + if (NUM_AVST_CH > 1) begin + if (~avl_rst_n) + second_tlp_valid <= 1'b0; + else if (dn_ready) + second_tlp_valid <= enable_split; + end +end + +assign first_tlp_cycle = dn_ready && ~second_tlp_valid; +assign second_tlp_cycle = dn_ready && second_tlp_valid; + + +//--------------------------------------------------------------- +// Check FMTTYPE +//--------------------------------------------------------------- +// +// Error detection: +// Detect fmttype that's not supported by downstream logic (FIM) +// +// Error handling: +// Drop illegal request and log the error +// Drop subsequent packets of the unsupported request +// +always_comb begin + for (int ch=0; ch hdr_packet_max_data_len_t1[ch]); + end + + if (NUM_AVST_CH > 1) begin + tlp_pending_payload_2ch <= (rx_hdr_dw0_t1[CH0].length - hdr_packet_max_data_len_t1[CH0] - L_MAX_DATA_LEN); + tlp_pending_2ch <= (rx_hdr_dw0_t1[CH0].length > (hdr_packet_max_data_len_t1[CH0] + L_MAX_DATA_LEN)); + end + end + end + + always_ff @(posedge avl_clk) begin + if (NUM_AVST_CH == 1) begin + if (first_tlp_cycle && tlp_active && rx_tlp[CH0].valid) + pending_dword_cnt <= pending_dword_cnt - L_MAX_DATA_LEN; + else if (first_tlp_cycle && sop_has_payload[CH0]) + pending_dword_cnt <= max_pcie_payload[CH0] ? 11'h400 : tlp_pending_payload[CH0]; + end else begin + if (first_tlp_cycle) begin + if (tlp_active) begin // Multi-cycle packet + if (rx_tlp[CH0].valid && rx_tlp[CH1].valid) + pending_dword_cnt <= pending_dword_cnt - L_MAX_DATA_LEN_X2; + else if (rx_tlp[CH0].valid || rx_tlp[CH1].valid) + pending_dword_cnt <= pending_dword_cnt - L_MAX_DATA_LEN; + end + + // Request/Response with data + if (sop_has_payload[CH1]) + pending_dword_cnt <= max_pcie_payload[CH1] ? 11'h400 : tlp_pending_payload[CH1]; + else if (sop_has_payload[CH0]) + pending_dword_cnt <= max_pcie_payload[CH0] ? 11'h400 + : rx_tlp[CH0].valid ? tlp_pending_payload_2ch : tlp_pending_payload[CH0]; + end + end + end + + // Track multi-cycle TLP + always_ff @(posedge avl_clk) begin + if (~avl_rst_n) begin + tlp_active <= 1'b0; + end else begin + if (NUM_AVST_CH == 1) begin + if (first_tlp_cycle && rx_tlp[CH0].valid) begin + tlp_active <= 1'b0; + if (sop_has_payload[CH0]) begin + if (~eop[CH0]) + tlp_active <= (max_pcie_payload[CH0] || tlp_pending[CH0]); + end else if (tlp_active && ~sop[CH0] && ~eop[CH0]) begin + tlp_active <= (pending_dword_cnt > L_MAX_DATA_LEN); + end + end + end else begin + if (first_tlp_cycle && (rx_tlp[CH0].valid || rx_tlp[CH1].valid)) begin + tlp_active <= 1'b0; + + if (sop_has_payload[CH1]) begin + if (~eop[CH1]) + tlp_active <= (max_pcie_payload[CH1] || tlp_pending[CH1]); + end else if (sop_has_payload[CH0]) begin + if (~eop[CH0]) begin + if (~rx_tlp[CH1].valid) + tlp_active <= (max_pcie_payload[CH0] || tlp_pending[CH0]); + else if (~sop[CH1] && ~eop[CH1]) + tlp_active <= (max_pcie_payload[CH0] || tlp_pending_2ch); + end + end else if (tlp_active) begin + if (~sop[CH0] && ~eop[CH0] && ~sop[CH1] && ~eop[CH1]) begin + if (rx_tlp[CH0].valid && rx_tlp[CH1].valid) + tlp_active <= (pending_dword_cnt > L_MAX_DATA_LEN_X2); + else + tlp_active <= (pending_dword_cnt > L_MAX_DATA_LEN); + end + end + end + end + end + end + + always_ff @(posedge avl_clk) begin + err_sop <= '0; + err_eop <= '0; + err_sop_mc <= '0; + err_eop_mc <= '0; + + if (NUM_AVST_CH == 1) begin + if (first_tlp_cycle) begin + if (tlp_active && rx_tlp[CH0].valid) begin // Multi-cycle packet + err_sop_mc[CH0] <= sop[CH0]; + err_eop_mc[CH0] <= (pending_dword_cnt <= L_MAX_DATA_LEN) ? ~eop[CH0] : eop[CH0]; + end + + if (sop_has_payload[CH0]) begin // Request/Response with data + if (max_pcie_payload[CH0] || tlp_pending[CH0]) + err_eop[CH0] <= eop[CH0]; + else + err_eop[CH0] <= ~eop[CH0]; + end else if (sop[CH0]) begin // Request/Response without data + err_eop[CH0] <= ~eop[CH0]; + end + end + end else begin + if (first_tlp_cycle) begin + // Multi-cycle packet transfer is active + if (tlp_active) begin + // Packets received on both channel 0 and channel 1 + if (rx_tlp[CH0].valid && rx_tlp[CH1].valid) begin + if (pending_dword_cnt <= L_MAX_DATA_LEN) begin + err_eop_mc[CH0] <= ~eop[CH0]; + err_sop_mc[CH0] <= sop[CH0]; + end else if (pending_dword_cnt <= L_MAX_DATA_LEN_X2) begin + err_eop_mc <= {~eop[CH1], eop[CH0]}; + err_sop_mc <= sop; + end else begin + err_eop_mc <= eop; + err_sop_mc <= sop; + end + // Packets received on either channel 0 or channel 1 + end else if (rx_tlp[CH0].valid || rx_tlp[CH1].valid) begin + if (pending_dword_cnt <= L_MAX_DATA_LEN) begin + err_sop_mc <= sop; + err_eop_mc[CH0] <= rx_tlp[CH0].valid && ~eop[CH0]; + err_eop_mc[CH1] <= rx_tlp[CH1].valid && ~eop[CH1]; + end else begin + err_eop_mc <= eop; + end + end + end + + // Request/Response received on channel 0 + if (sop_has_payload[CH0]) begin // with data + if (~max_pcie_payload[CH0] && ~tlp_pending[CH0]) begin + err_eop[CH0] <= ~eop[CH0]; + end else if (rx_tlp[CH1].valid && ~max_pcie_payload[CH0] && ~tlp_pending_2ch) begin + err_sop[CH1] <= sop[CH1]; + err_eop <= {~eop[CH1], eop[CH0]}; + end else begin + err_eop <= eop; + err_sop[CH1] <= sop[CH1]; + end + end else if (sop[CH0]) begin // without data + err_eop[CH0] <= ~eop[CH0]; + end + + // Request/Response received on channel 1 + if (sop_has_payload[CH1]) begin // with data + if (max_pcie_payload[CH1] || tlp_pending[CH1]) + err_eop[CH1] <= eop[CH1]; + else + err_eop[CH1] <= ~eop[CH1]; + end else if (sop[CH1]) begin // without data + err_eop[CH1] <= ~eop[CH1]; + end + end + end + + if (~avl_rst_n) begin + err_sop <= '0; + err_eop <= '0; + err_sop_mc <= '0; + err_eop_mc <= '0; + end + end +end else begin : malformed_tlp_off + assign err_eop = 1'b0; + assign err_sop = 1'b0; + assign err_sop_mc = 1'b0; + assign err_eop_mc = 1'b0; +end +endgenerate + +//--------------------------------------------------------------- +// Pending CPL data counter +//--------------------------------------------------------------- +// Total of pending read data that has been requested so far +// +// The counter is incremented with the data length in the memory read request TLP +// when the read request is sent to the host +// +// The counter is decremented with the data length in a read completion TLP +// when the completion is received +// +// The count is used to decide whether the CPLD buffer in PCIe IP +// has enough credit to take in more completion data +// +// PCIe TX bridge will stop sending memory read request if the amount +// of pending data hits the credit limit +// + +logic cpl_pending_data_add; // Increment pending data count +logic [PCIE_MAX_LEN_WIDTH-1:0] cpl_pending_data_add_val; // Pending data count value to be added +logic cpl_pending_data_sub_t0; // Decrement pending data count +logic cpl_pending_data_sub; +logic [PCIE_MAX_LEN_WIDTH-1:0] cpl_pending_data_sub_val_t0; // Completion payload to be decremented from pending data count +logic [PCIE_MAX_LEN_WIDTH-1:0] cpl_pending_data_sub_val; + +assign cpl_pending_data_add = tx_mrd_valid; +assign cpl_pending_data_add_val = tx_mrd_length; + +// Substract completion payload from pending data count +always_ff @(posedge avl_clk) begin + cpl_pending_data_sub_val_t0 <= '0; + + if (NUM_AVST_CH == 1) begin + if (tlp_type[CH0][CPL]) + cpl_pending_data_sub_val_t0 <= cpl_pend_dw[CH0]; + else if (tlp_type[CH0][CPLD]) + cpl_pending_data_sub_val_t0 <= cpl_hdr[CH0].dw0.length; + end else begin + // When new CPL/CPLD packet is received on channel 0 + if (first_tlp_cycle) begin + if (tlp_type[CH0][CPL]) + cpl_pending_data_sub_val_t0 <= cpl_pend_dw[CH0]; + else if (tlp_type[CH0][CPLD]) + cpl_pending_data_sub_val_t0 <= cpl_hdr[CH0].dw0.length; + end + + // When new CPL/CPLD is received on channel 1 and not channel 0 + // (OR) the CPL/CPLD on channel 1 is the second TLP of a split transaction + if (ready) begin + if (tlp_type[CH1][CPL]) + cpl_pending_data_sub_val_t0 <= cpl_pend_dw[CH1]; + if (tlp_type[CH1][CPLD]) + cpl_pending_data_sub_val_t0 <= cpl_hdr[CH1].dw0.length; + end + end +end + +always_ff @(posedge avl_clk) begin + cpl_pending_data_sub_val <= cpl_pending_data_sub_val_t0; +end + +always_ff @(posedge avl_clk) begin + if (~avl_rst_n) begin + cpl_pending_data_sub_t0 <= 1'b0; + end else begin + cpl_pending_data_sub_t0 <= 1'b0; + if (first_tlp_cycle && is_completion[CH0]) + begin + cpl_pending_data_sub_t0 <= 1'b1; + end + + if (NUM_AVST_CH > 1) begin + if (ready && is_completion[CH1]) + begin + cpl_pending_data_sub_t0 <= 1'b1; + end + end + end +end + +always_ff @(posedge avl_clk) begin + if (~avl_rst_n) begin + cpl_pending_data_sub <= 1'b0; + end else begin + // Don't substract unexpected completions from pending data count + if (|block_unexp_cpl) begin + cpl_pending_data_sub <= 1'b0; + end else begin + cpl_pending_data_sub <= cpl_pending_data_sub_t0; + end + end +end + +always_ff @(posedge avl_clk) begin + if (~avl_rst_n) begin + cpl_pending_data_cnt <= '0; + end else begin + case ({cpl_pending_data_add, cpl_pending_data_sub}) + 2'b10 : begin + cpl_pending_data_cnt <= cpl_pending_data_cnt + cpl_pending_data_add_val; + end + 2'b01 : begin + cpl_pending_data_cnt <= cpl_pending_data_cnt - cpl_pending_data_sub_val; + end + 2'b11 : begin + cpl_pending_data_cnt <= cpl_pending_data_cnt + cpl_pending_data_add_val - cpl_pending_data_sub_val; + end + endcase + end +end + +//--------------------------------------------------------------- +// Track active MRd request +//--------------------------------------------------------------- +// Bit vector of size MAX TAG count to indicate if a tag is already used in a pending MRd request +logic [PCIE_EP_MAX_TAGS-1:0] tr_tag_active; +t_ch cpl_tag_active; // If the tag in current CPL/CPLD exists in tr_tag_active + +t_ch last_cpl; // Is current completion the last completion of a MRd request? +logic last_cpl_active, last_cpl_active_q; // Is multi-cycle last completion TLP active? +t_tlp_tag last_cpl_tag, last_cpl_tag_q; // Tag in last completion TLP + +// Last packet of the last completion of a MRd request has been received +t_ch cpl_complete; +logic cpl_complete_q; +logic prev_cpl_complete; + +// Tag to be released to the tag pool +t_tlp_tag [NUM_AVST_CH-1:0] cpl_complete_tag; +t_tlp_tag cpl_complete_tag_q; +t_tlp_tag prev_cpl_complete_tag; + +always_comb begin + for (int ch=0; ch= cpl_hdr[ch].byte_count[11:2]); +end + +// A tag is released when the last completion packet of a memory read request is received +always_comb begin + cpl_complete = '0; + cpl_complete_tag = '0; + last_cpl_active = last_cpl_active_q; + last_cpl_tag = last_cpl_tag_q; + + if (first_tlp_cycle) begin + // CPL is received on channel 0, release the tag + if (tlp_type[CH0][CPL]) begin + cpl_complete[CH0] = 1'b1; + cpl_complete_tag[CH0] = cpl_hdr[CH0].tag[PCIE_EP_TAG_WIDTH-1:0]; + end else if(tlp_type[CH0][CPLD] && last_cpl[CH0]) begin + if ( |eop ) begin + // CPLD received on channel 0 is the last completion of a read request + // and the last packet is received on channel 0 or channel 1 + // Release the tag + cpl_complete[CH0] = 1'b1; + cpl_complete_tag[CH0] = cpl_hdr[CH0].tag[PCIE_EP_TAG_WIDTH-1:0]; + end else begin + // CPLD received on channel 0 is the last completion of a read request + // but the last packet has not been received yet either on channel 0 or channel 1 + // Store the CPL tag in the header and assert last_cpl_active_q to notify checker + // that subsequent packets are part of the last completion for a memory read + // De-assert last_cpl_active_q when the last packet is eventually received + last_cpl_active = 1'b1; + last_cpl_tag = cpl_hdr[CH0].tag[PCIE_EP_TAG_WIDTH-1:0]; + end + end else if (last_cpl_active_q && |eop) begin + // The last packet of a multi-cycle last completion of a memory read has been received + // Release the pre-stored tag and de-assert last_cpl_active_q + cpl_complete[CH0] = 1'b1; + cpl_complete_tag[CH0] = last_cpl_tag_q; + last_cpl_active = 1'b0; + end + end + + if (NUM_AVST_CH > 1) begin + if (ready) begin + // CPL is received on channel 1, release the tag + if (tlp_type[CH1][CPL]) begin + cpl_complete[CH1] = 1'b1; + cpl_complete_tag[CH1] = cpl_hdr[CH1].tag[PCIE_EP_TAG_WIDTH-1:0]; + end else if (tlp_type[CH1][CPLD] && last_cpl[CH1]) begin + if (eop[CH1]) begin + cpl_complete[CH1] = 1'b1; + cpl_complete_tag[CH1] = cpl_hdr[CH1].tag[PCIE_EP_TAG_WIDTH-1:0]; + end else begin + last_cpl_active = 1'b1; + last_cpl_tag = cpl_hdr[CH1].tag[PCIE_EP_TAG_WIDTH-1:0]; + end + end + end + end +end + +always_ff @(posedge avl_clk) begin + if (~avl_rst_n) + last_cpl_active_q <= 1'b0; + else + last_cpl_active_q <= last_cpl_active; +end + +always_ff @(posedge avl_clk) begin + last_cpl_tag_q <= last_cpl_tag; +end + +always_ff @(posedge avl_clk) begin + cpl_complete_q <= |cpl_complete; + if (dn_ready) + prev_cpl_complete <= |cpl_complete; + + if (NUM_AVST_CH == 1) begin + cpl_complete_tag_q <= cpl_complete_tag[CH0]; + if (dn_ready) + prev_cpl_complete_tag <= cpl_complete_tag[CH0]; + end else begin + cpl_complete_tag_q <= cpl_complete[CH0] ? cpl_complete_tag[CH0] : cpl_complete_tag[CH1]; + if (dn_ready) + prev_cpl_complete_tag <= cpl_complete[CH0] ? cpl_complete_tag[CH0] : cpl_complete_tag[CH1]; + end +end + +always @(posedge avl_clk) begin + if (~avl_rst_n) begin + tr_tag_active <= '0; + end else begin + if (tx_mrd_valid) + tr_tag_active[tx_mrd_tag] <= 1'b1; + if (cpl_complete_q) + tr_tag_active[cpl_complete_tag_q] <= 1'b0; + end +end + +//--------------------------------------------------------------- +// Catch unexpected CPL/CPLD +//--------------------------------------------------------------- +// +// Error detection: +// Detect unexpected CPL/CPLD when no memory read is sent with the tag +// +// Error handling: +// Log the error as unexpected completion status in AER +// Drop illegal request and subsequent packets of the unsupported request +// +always_ff @(posedge avl_clk) begin + for (int ch=0; ch 1) begin + if (ready && is_completion[CH1]) + begin + // (1) CPL tag is not active (no pending MRd request) -OR- + // (2) The tag is about to be de-activated in the next cycle + // because the final packet of a completion with similar tag has been received + // in previous cycle. It takes two cycles to de-activate a tag. + if (~cpl_tag_active[CH1] + || (prev_cpl_complete && (cpl_hdr[CH1].tag == prev_cpl_complete_tag))) + begin + err_unexp_cpl_c[CH1] = 1'b1; + end + end + end +end + +//--------------------------------------------------------------- +// Memory read completion timeout +//--------------------------------------------------------------- +generate +if (ENABLE_COMPLETION_TIMEOUT_CHECK == 1) begin : cpl_timeout + logic ttq_start_time_valid; // Tag is associated with an active MRd request pending completion + logic ttq_start_time_valid_t1, ttq_start_time_valid_t2; + t_tlp_tag ttq_tp; // Tag to check for completion timeout + t_tlp_tag ttq_start_time_raddr; + + logic [CPL_TIME_WIDTH-1:0] ttq_timer; // Free running timer + logic ttq_start_time_re; // Read the timestamp of an active MRd request + + logic [CPL_TIME_WIDTH-1:0] ttq_st_dout; // Timestamp of an active MRd request + logic ttq_vf_act; // Is MRd request sent by a VF? + logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] ttq_pfn; // PF number associated with the MRd request + logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] ttq_vfn; // VF number associated with the MRd request + + logic [CPL_TIME_WIDTH+1:0] ttq_elapsed_time; // How long a MRd request has been waiting for completion + logic ttq_elapsed_vf_act; // Is MRd request sent by VF? + logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] ttq_elapsed_pfn; // PF number associated with the MRd request + logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] ttq_elapsed_vfn; // VF number associated with the MRd request + + // Free-running timer + always_ff @(posedge avl_clk) begin + if (~avl_rst_n) + ttq_timer <= 26'h0; + else + ttq_timer <= ttq_timer + 1'b1; + end + + // In a round-robin fasion, check if the wait time for any in-flight memory read request + // has exceeded the timeout limit for host to return the completion + always_ff @(posedge avl_clk) begin + if (~avl_rst_n) begin + ttq_tp <= t_tlp_tag'(0); + ttq_elapsed_time <= 28'b0; + ttq_start_time_valid <= 1'b0; + ttq_start_time_valid_t1 <= 1'b0; + ttq_start_time_valid_t2 <= 1'b0; + ttq_start_time_raddr <= t_tlp_tag'(0); + end + else begin + // Check if there is an in-flight memory read request associated with the round-robin tag + ttq_start_time_valid <= tr_tag_active[ttq_tp]; + + // Read the start time of the in-flight memory read request from RAM, using the round-robin tag + // It takes 1 cycle to read from the ram + ttq_start_time_raddr <= ttq_tp; + ttq_start_time_valid_t1 <= ttq_start_time_valid; + ttq_start_time_valid_t2 <= ttq_start_time_valid_t1; + + // Register the start time and function for the memory read request that are retrieved from the ram + if (ttq_start_time_valid_t1) begin // memory read request pending for completion + ttq_elapsed_time <= {2'b01, ttq_timer} - {2'b00,ttq_st_dout}; + ttq_elapsed_vf_act <= ttq_vf_act; + ttq_elapsed_pfn <= ttq_pfn; + ttq_elapsed_vfn <= ttq_vfn; + end + + // Increement the round-robin tag + ttq_tp <= incr_tlp_tag(ttq_tp); + end + end + + // Gate read with avl_rst_n since clk may not be active during reset, and ram is not driven by reset + assign ttq_start_time_re = (~avl_rst_n) ? 1'b0 : ttq_start_time_valid; + + ram_1r1w #( + .DEPTH(PCIE_EP_TAG_WIDTH), + .WIDTH(1+ofs_fim_pcie_pkg::VF_WIDTH+ofs_fim_pcie_pkg::PF_WIDTH+CPL_TIME_WIDTH), + .GRAM_MODE(2'd1), + .GRAM_STYLE(`GRAM_AUTO), + .INCLUDE_PARITY(0) + ) + ttq_start_time_buf ( + .clk (avl_clk), + .din ({tx_mrd_vf_act, tx_mrd_vfn, tx_mrd_pfn, ttq_timer}), + .waddr (tx_mrd_tag), + .we (tx_mrd_valid), + .raddr (ttq_start_time_raddr), + .re (ttq_start_time_re), + .dout ({ttq_vf_act, ttq_vfn, ttq_pfn, ttq_st_dout}) + ); + + // Check if the waiting time has exceeded the completion timeout limit + always_ff @(posedge avl_clk) begin + if (~avl_rst_n) begin + err_cpl_timeout <= 1'b0; + end else begin + err_cpl_timeout <= 1'b0; + if (ttq_start_time_valid_t2) begin + if ({2'b0, ttq_elapsed_time[CPL_TIME_WIDTH-1:0]} > PCIE_CPL_TIMEOUT) begin + err_cpl_timeout <= 1'b1; + cpl_timeout_func <= {ttq_elapsed_vfn, ttq_elapsed_pfn, ttq_elapsed_vf_act}; + end + end + end + end +end else begin : cpl_timeout_off + assign err_cpl_timeout = 1'b0; + assign cpl_timeout_func = '0; +end +endgenerate + +//--------------------------------------------------------------- +// Block illegal packets below from going downstream +// * TLP with unsupported fmttype +// * Unexpected completion +// +// Malformed packets with illegal sop/eop can't be gracefully handled +// and will be flagged as uncorrectable fatal error that requires +// a system reboot/reprogram the FPGA +// +//--------------------------------------------------------------- +t_avst_rxs rx_tlp_out; + +always_ff @(posedge avl_clk) begin + for (int ch=0; ch 1) begin + if (first_tlp_cycle && enable_split) // Delay sending packet on channel 1 + begin + rx_tlp_out[CH1].valid <= 1'b0; + end + else if (second_tlp_cycle) // second cycle of two-cycle processing + begin + // Send the channel 1 packet which was delayed, de-activate channel 0 packet + rx_tlp_out[CH0].valid <= 1'b0; + rx_tlp_out[CH1].valid <= 1'b1; + end + end + + for (int ch=0; ch 1) begin + if (dn_ready && rx_tlp_out[CH1].valid) + begin + // Block the TLP if error is found on the packet on channel 1 or the packet is part of an illegal multi-cycle TLP + if (block_tlp[CH1]) + o_avl_rx_st[CH1].valid <= 1'b0; + // Current packet is part of an illegal TLP, block it + else if ((block_tlp[CH0] || (invalid_prev_tlp && rx_tlp_out[CH0].valid && ~rx_tlp_out[CH0].sop)) + && ~rx_tlp_out[CH1].sop) + o_avl_rx_st[CH1].valid <= 1'b0; + end + // Packet on channel 1 is acknowledged by downstream receiver, de-assert valid + else if (dn_ready) begin + o_avl_rx_st[CH1].valid <= 1'b0; + end + end +end + +//--------------------------------------------------------------- +// Error output assignment +//--------------------------------------------------------------- +always_comb begin + for (int ch=0; ch 1) begin + if (ready) begin + err_status_t0[CH1].err_poison <= err_poison_c [CH1]; + err_status_t0[CH1].err_cpl_status <= err_cpl_status_c [CH1]; + err_status_t0[CH1].err_unexp_cpl <= err_unexp_cpl_c [CH1]; + err_status_t0[CH1].err_fmttype <= err_fmttype_c [CH1]; + end + end + end +end + +always_comb begin + err_status = err_status_t0; + + err_status[CH0].err_cpl_timeout = err_cpl_timeout; + if (NUM_AVST_CH > 1) begin + err_status[CH1].err_cpl_timeout = 1'b0; + end + + for (int ch=0; ch= 32) csr_reg[addr[CSR_REG_ADDR_WIDTH-1:3]][i-32] <= 1'b0; + end else begin + // update 32 LSBs + if (i < 32) csr_reg[addr[CSR_REG_ADDR_WIDTH-1:3]][i] <= 1'b0; + end + end + end + else begin + // HW updates (set) only for active-high level + if (~csr_reg[mask_addr[CSR_REG_ADDR_WIDTH-1:3]][i] & update_val[i]) begin + csr_reg[addr[CSR_REG_ADDR_WIDTH-1:3]][i] <= 1'b1; + end + end + end + end +end +endtask + +endmodule diff --git a/ipss/pcie/rtl/pcie_flr_resync.sv b/ipss/pcie/rtl/pcie_flr_resync.sv new file mode 100755 index 0000000..6f8f3d2 --- /dev/null +++ b/ipss/pcie/rtl/pcie_flr_resync.sv @@ -0,0 +1,177 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Module instantiates CDC strobes, synchronizers, etc. for FLR control +// signals between PCIE EP & CoreFIM. +// +//----------------------------------------------------------------------------- + +`include "fpga_defines.vh" +import ofs_fim_cfg_pkg::*; +import ofs_fim_if_pkg::*; +import ofs_fim_pcie_pkg::*; + +module pcie_flr_resync ( + input logic avl_clk, + input logic avl_rst_n, + + input logic fim_clk, + input logic fim_rst_n, + + // To/From PCIE Top <-> CoreFIM + output t_sideband_from_pcie pcie_p2f_sideband, + input t_sideband_to_pcie pcie_c2p_sideband, + + // To/From PCIE EP <-> PCIE Top + input t_sideband_from_pcie p2f_sideband, + output t_sideband_to_pcie f2p_sideband +); + + + //CDC Signals + logic p2f_latched_ack, p2f_latched_valid, p2f_latched_valid_r; //PCIe to FLR Resync + logic f2p_latched_vf_ack, f2p_latched_vf_valid, f2p_latched_vf_valid_q; //CoreFim to FLR Resync + logic flr_completed_vf_strobe, flr_latched_vf_strobe_sync1, flr_latched_vf_strobe_sync2; + + t_sideband_from_pcie pcie_p2f_sb; + t_sideband_to_pcie pcie_f2p_sb; + + //------------------------ + // CDC into PCIE EP + //------------------------ + // VF FLR completion status + fim_cross_handshake #( + .WIDTH (1+FIM_PF_WIDTH+FIM_VF_WIDTH) + ) cfim_to_pcie_vf_hs( + .din_clk (fim_clk), + .din_srst (~fim_rst_n), + .din ({pcie_c2p_sideband.flr_completed_vf, + pcie_c2p_sideband.flr_completed_pf_num, + pcie_c2p_sideband.flr_completed_vf_num + }), + .din_valid (pcie_c2p_sideband.flr_completed_vf), + .din_ack (), + .dout_clk (avl_clk), + .dout_srst (~avl_rst_n), + .dout_ack (f2p_latched_vf_ack), + .dout_valid (f2p_latched_vf_valid), + .dout ({pcie_f2p_sb.flr_completed_vf, + pcie_f2p_sb.flr_completed_pf_num, + pcie_f2p_sb.flr_completed_vf_num + }) + ); + + always_ff @(posedge avl_clk) begin + f2p_latched_vf_valid_q <= f2p_latched_vf_valid; + flr_completed_vf_strobe <= (~f2p_latched_vf_valid_q & f2p_latched_vf_valid); + flr_latched_vf_strobe_sync1 <= flr_completed_vf_strobe; + flr_latched_vf_strobe_sync2 <= flr_latched_vf_strobe_sync1; + end + + always_ff @(posedge avl_clk) begin + if (~avl_rst_n) begin + f2p_latched_vf_ack <= 1'b0; + end else begin + f2p_latched_vf_ack <= f2p_latched_vf_valid & flr_latched_vf_strobe_sync2; + end + end + + always_ff @(posedge avl_clk) begin + if (~avl_rst_n) begin + f2p_sideband.flr_completed_vf <= 1'b0; + f2p_sideband.flr_completed_pf_num <= '0; + f2p_sideband.flr_completed_vf_num <= '0; + end + else if (flr_latched_vf_strobe_sync2) begin + f2p_sideband.flr_completed_vf <= pcie_f2p_sb.flr_completed_vf; + f2p_sideband.flr_completed_pf_num <= pcie_f2p_sb.flr_completed_pf_num; + f2p_sideband.flr_completed_vf_num <= pcie_f2p_sb.flr_completed_vf_num; + end + else begin + f2p_sideband.flr_completed_vf <= 1'b0; + end + end + + // PF FLR completion status + fim_resync #( + .SYNC_CHAIN_LENGTH (3), + .WIDTH (FIM_NUM_PF), + .INIT_VALUE (0), + .NO_CUT (1) + ) pf_flr_sts_resync ( + .clk (avl_clk), + .reset (~avl_rst_n), + .d (pcie_c2p_sideband.flr_completed_pf), + .q (f2p_sideband.flr_completed_pf) + ); + + //--------------------- + // CDC into CoreFIM + //--------------------- + // PF FLR + fim_resync #( + .SYNC_CHAIN_LENGTH (3), + .WIDTH (FIM_NUM_PF), + .INIT_VALUE (0), + .NO_CUT (1) + ) pf_flr_resync ( + .clk (fim_clk), + .reset (~fim_rst_n), + .d (p2f_sideband.flr_active_pf), + .q (pcie_p2f_sideband.flr_active_pf) + ); + + // VF FLR + fim_cross_handshake #( + .WIDTH (1+FIM_PF_WIDTH+FIM_VF_WIDTH) + ) pcie_to_cfim_hs ( + .din_clk (avl_clk), + .din_srst (~avl_rst_n), + .din ({p2f_sideband.flr_rcvd_vf, + p2f_sideband.flr_rcvd_pf_num, + p2f_sideband.flr_rcvd_vf_num + }), + .din_valid (p2f_sideband.flr_rcvd_vf), + .din_ack (), + .dout_clk (fim_clk), + .dout_srst (~fim_rst_n), + .dout_ack (p2f_latched_ack), + .dout_valid (p2f_latched_valid), + .dout ({pcie_p2f_sb.flr_rcvd_vf, + pcie_p2f_sb.flr_rcvd_pf_num, + pcie_p2f_sb.flr_rcvd_vf_num + }) + ); + + always_ff @(posedge fim_clk) begin + p2f_latched_valid_r <= p2f_latched_valid; + end + + always_ff @(posedge fim_clk) begin + if (~fim_rst_n) begin + p2f_latched_ack <= 1'b0; + end else begin + p2f_latched_ack <= p2f_latched_valid & ~p2f_latched_valid_r; + end + end + + always_ff @(posedge fim_clk) begin + if (~fim_rst_n) begin + pcie_p2f_sideband.flr_rcvd_vf <= 1'b0; + pcie_p2f_sideband.flr_rcvd_pf_num <= '0; + pcie_p2f_sideband.flr_rcvd_vf_num <= '0; + end + else if (p2f_latched_valid) begin + pcie_p2f_sideband.flr_rcvd_vf <= pcie_p2f_sb.flr_rcvd_vf; + pcie_p2f_sideband.flr_rcvd_pf_num <= pcie_p2f_sb.flr_rcvd_pf_num; + pcie_p2f_sideband.flr_rcvd_vf_num <= pcie_p2f_sb.flr_rcvd_vf_num; + end + else begin + pcie_p2f_sideband.flr_rcvd_vf <= 1'b0; + end + end + +endmodule diff --git a/ipss/pcie/rtl/pcie_msix_resync.sv b/ipss/pcie/rtl/pcie_msix_resync.sv new file mode 100755 index 0000000..f085a98 --- /dev/null +++ b/ipss/pcie/rtl/pcie_msix_resync.sv @@ -0,0 +1,100 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Module instantiates synchronizers for SHDW control +// signals between PCIE EP & CoreFIM. +// +//----------------------------------------------------------------------------- + +`include "fpga_defines.vh" +import ofs_fim_cfg_pkg::*; +import ofs_fim_if_pkg::*; +import ofs_fim_pcie_pkg::*; + +module pcie_msix_resync ( + + input logic fim_clk, + input logic fim_rst_n, + + input logic avl_clk, + input logic avl_rst_n, + + // To PCIE Top <-> CoreFIM + output t_sideband_from_pcie pcie_p2msix_sideband, + + input logic ctl_shdw_update, + input logic [1:0] ctl_shdw_pf_num, + input logic [10:0] ctl_shdw_vf_num, + input logic ctl_shdw_vf_active, + input logic [6:0] ctl_shdw_cfg, + output logic ctl_shdw_req_all +); + t_sideband_from_pcie msix2p_sideband; + + localparam DATA_WIDTH = $bits(pcie_p2msix_sideband); + logic vf0_msix_en; + + logic c2a_ctl_shdw_req_all; // MD - add declaration 12/8/2020 + + assign msix2p_sideband.cfg_ctl.max_payload_size = '0; + assign msix2p_sideband.cfg_ctl.max_read_req_size = '0; + assign msix2p_sideband.cfg_ctl.extended_tag_enable = '0; + assign msix2p_sideband.cfg_ctl.msix_enable = '0; + assign msix2p_sideband.cfg_ctl.msix_pf_mask_en = '0; + assign msix2p_sideband.flr_active_pf = '0; + assign msix2p_sideband.flr_rcvd_vf = '0; + assign msix2p_sideband.flr_rcvd_pf_num = '0; + assign msix2p_sideband.flr_rcvd_vf_num = '0; + assign msix2p_sideband.pcie_linkup = '0; + assign msix2p_sideband.pcie_chk_rx_err_code = '0; + + // Control Shadow Interface Query ------------------------------------- + // Check status of MSIX Cfg and Masking for PF/VF Config Regs in PCIe core + // a2c_ctl_shdw_cfg[6:0] + // [6]: enable field, bit 15 of ATX Ctrl reg + // [5]: TPH Requester enable, bit 8 of TPH Requester Ctrl reg + // [4:3]: TPH ST Mode select field, [1:0] TPH Requester Ctrl Reg + // [2]: MSIX enable, bit 14 MSIX MSG Ctrl reg + // [1]: MSIX fucntion mask bit, bit 14 MSIx Message Ctrl Reg + // [0]: Bus master enable, bit 2 of PCI Cmd reg + always @(posedge avl_clk) + if (~avl_rst_n) begin + vf0_msix_en <= 1'b0; + msix2p_sideband.cfg_ctl.vf0_msix_mask <= 1'b0; + end + else if (ctl_shdw_update) begin + if (ctl_shdw_vf_active & ctl_shdw_vf_num==0) begin + vf0_msix_en <= ctl_shdw_cfg[2]; + msix2p_sideband.cfg_ctl.vf0_msix_mask <= ctl_shdw_cfg[1]; + end else begin + vf0_msix_en <= 1'b0; + msix2p_sideband.cfg_ctl.vf0_msix_mask <= 1'b0; + end + end + + assign c2a_ctl_shdw_req_all = 'b1; + + //Synchronizing sideband signals to fim_clk + fim_resync # ( + .WIDTH(DATA_WIDTH), + .NO_CUT(0) ) + sync ( + .clk (fim_clk), + .reset (~fim_rst_n), + .d (msix2p_sideband), + .q (pcie_p2msix_sideband) + ); + +endmodule + + + + + + + + + diff --git a/ipss/pcie/rtl/pcie_rx_bridge.sv b/ipss/pcie/rtl/pcie_rx_bridge.sv new file mode 100755 index 0000000..5696cba --- /dev/null +++ b/ipss/pcie/rtl/pcie_rx_bridge.sv @@ -0,0 +1,114 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Adapt PCIe AVST RX interface to AXI4-S RX streaming interface +// +// ------- +// Clock domain +// ------- +// All the inputs and outputs are synchronous to input clock : avl_clk +// +//----------------------------------------------------------------------------- + +import ofs_fim_pcie_pkg::*; +import ofs_fim_if_pkg::*; + +module pcie_rx_bridge ( + input logic avl_clk, + input logic avl_rst_n, + input t_avst_rxs avl_rx_st, + output logic avl_rx_ready, + + ofs_fim_pcie_rxs_axis_if.master axis_rx_st +); + +`ifdef PTILE + pcie_rx_bridge_ptile pcie_rx_bridge_ptile + ( + .avl_clk (avl_clk), + .avl_rst_n (avl_rst_n), + .avl_rx_st (avl_rx_st), + .avl_rx_ready (avl_rx_ready), + .axis_rx_st (axis_rx_st) + ); +`else + pcie_rx_bridge_htile pcie_rx_bridge_htile + ( + .avl_clk (avl_clk), + .avl_rst_n (avl_rst_n), + .avl_rx_st (avl_rx_st), + .avl_rx_ready (avl_rx_ready), + .axis_rx_st (axis_rx_st) + ); +`endif + + +// synthesis translate_off + +initial +begin : rx_logger + static int log_fd = $fopen("log_ofs_fim_pcie_rx_bridge.tsv", "w"); + int cycle = 0; + forever @(posedge avl_clk) begin + if (avl_rst_n) begin + if (axis_rx_st.tready && axis_rx_st.rx.tvalid) begin + log_axis_rx_st(log_fd, "axis_rx_st", cycle, axis_rx_st.rx); + end + + if (avl_rx_ready) begin + log_avl_rx_st(log_fd, "avl_rx_st", cycle, avl_rx_st); + end + + cycle = cycle + 1; + end + end +end + +task log_axis_rx_st; + input int log_fd; + input string crx_name; + input int cycle; + input t_axis_pcie_rxs rx; +begin + for (int i = 0; i < FIM_PCIE_TLP_CH; i = i + 1) + begin + if (rx.tdata[i].valid) + begin + $fwrite(log_fd, "%s:\t%t [%d] ch%0d %s\n", + crx_name, $time, cycle, i, + ofs_fim_pcie_hdr_def::func_flit_to_string(rx.tdata[i].sop, + rx.tdata[i].eop, + rx.tdata[i].hdr, + rx.tdata[i].payload)); + $fflush(log_fd); + end + end +end +endtask // log_afu_rx_st + +task log_avl_rx_st; + input int log_fd; + input string crx_name; + input int cycle; + input t_avst_rxs rx; +begin + for (int i = 0; i < FIM_PCIE_TLP_CH; i = i + 1) + begin + if (rx[i].valid) + begin + $fwrite(log_fd, "%s:\t%t [%d] ch%0d %s\n", + crx_name, $time, cycle, i, + ofs_fim_pcie_pkg::func_rx_to_string(rx[i])); + + $fflush(log_fd); + end + end +end +endtask // log_avl_rx_st + +// synthesis translate_on + +endmodule diff --git a/ipss/pcie/rtl/pcie_rx_bridge_cdc.sv b/ipss/pcie/rtl/pcie_rx_bridge_cdc.sv new file mode 100755 index 0000000..4ca6cf8 --- /dev/null +++ b/ipss/pcie/rtl/pcie_rx_bridge_cdc.sv @@ -0,0 +1,113 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Functions: +// * Clock crossing PCIe RX bridge signals from PCIe clock domain to FIM clock domain +// +//----------------------------------------------------------------------------- + +import ofs_fim_pcie_pkg::*; +import ofs_fim_if_pkg::*; + +module pcie_rx_bridge_cdc ( + input logic pcie_clk, + input logic pcie_rst_n, + + input logic fim_clk, + input logic fim_rst_n, + + input t_avst_rxs pcie_avl_rx_st, + output logic pcie_avl_rx_ready, + + input logic fim_avl_rx_ready, + output t_avst_rxs fim_avl_rx_st +); + +// AVST interface signals +localparam RX_AVST_FIFO_WIDTH = NUM_AVST_CH * PCIE_RX_AVST_IF_WIDTH; + +logic fifo_wreq; +logic fifo_rdack; +logic fifo_full, fifo_almfull; +logic fifo_rvalid; + +t_avst_ch fifo_din_valid; +t_avst_rxs fifo_din; +t_avst_rxs fifo_dout_rx_st; + +logic fim_avl_rx_valid; + +///////////////////////////////////////////////////////////////////////////////// + +assign fifo_rdack = ~fim_avl_rx_valid || fim_avl_rx_ready; + +// AVL PCIE RX TLP FIFO +fim_rdack_dcfifo +#( + .DATA_WIDTH (RX_AVST_FIFO_WIDTH), + .DEPTH_LOG2 (6), // depth 64 + .ALMOST_FULL_THRESHOLD (4), // assert almfull when empty slots <= 8 + .WRITE_ACLR_SYNC ("ON") // add aclr synchronizer on write side +) +rx_avst_dcfifo +( + .wclk (pcie_clk), + .rclk (fim_clk), + .aclr (~fim_rst_n), + .wdata (fifo_din), + .wreq (fifo_wreq), + .rdack (fifo_rdack), + .rdata (fifo_dout_rx_st), + .wfull (fifo_full), + .almfull (fifo_almfull), + .rvalid (fifo_rvalid) +); + +// Write incoming AVL packets to FIFO when FIFO is not full +always_comb begin + for (int ch=0; ch +// [CH1] +// T1: [CH0] (EOP) data: +// +// AXIS data +// The bridge will move the packets from two transactions into 1 transaction on the AXIS channel +// [TLP CH0] (SOP) header:<128-bit header> data: +// [TLP CH1] (EOP) header: data: +// +// ------- +// Clock domain +// ------- +// All the inputs and outputs are synchronous to input clock : avl_clk +// +//----------------------------------------------------------------------------- + +import ofs_fim_pcie_pkg::*; +import ofs_fim_if_pkg::*; +import ofs_fim_pcie_hdr_def::*; + +module pcie_rx_bridge_htile ( + input logic avl_clk, + input logic avl_rst_n, + input t_avst_rxs avl_rx_st, + output logic avl_rx_ready, + + ofs_fim_pcie_rxs_axis_if.master axis_rx_st +); + +enum {CH0, CH1} e_channel; + +localparam HDR_3DW = 3; +localparam HDR_4DW = 4; +localparam HDR_LWIDTH = $clog2(HDR_4DW) + 1; + +localparam HDR_3DW_WIDTH = HDR_3DW*32; +localparam HDR_4DW_WIDTH = HDR_4DW*32; + +t_avst_ch is_hdr_4dw; +logic is_hdr_4dw_q; +logic empty; +logic [NUM_AVST_CH-1:0] [HDR_LWIDTH-1:0] hdr_len; + +t_avst_ch in_tlp_valid; +logic cur_tlp_valid, next_tlp_valid; +t_avst_rxs cur_tlp, next_tlp; + +t_tlp_hdr_dw0 [NUM_AVST_CH-1:0] cur_tlp_hdr_dw0; +t_avst_ch cur_rx_sop, cur_rx_eop; +t_avst_ch next_rx_sop, next_rx_eop; +logic wait_for_data; + +logic rx_ready; +t_axis_pcie_rxs rx_st_reg; + +////////////////////////////////////////////////////////////// + +// Interface assignment +assign axis_rx_st.clk = avl_clk; +assign axis_rx_st.rst_n = avl_rst_n; +assign axis_rx_st.rx = rx_st_reg; + +// Load the pipeline if there is no pending transfer or the current transfer is acknowledged +assign rx_ready = ~rx_st_reg.tvalid | axis_rx_st.tready; +assign avl_rx_ready = rx_ready; + +//----------------------------- +// Register new TLP when bridge is ready to process the next TLP +// Otherwise, keep the current TLP in the register +//----------------------------- +// TLP valid +always_comb begin + for (int ch=0; ch= (AVST_DWORD_LEN - next_tlp[CH0].empty)) begin + rx_st_reg.tdata[CH0].eop <= 1'b1; + empty <= 1'b1; + end + end + end + // Multi-cycle TLP, end of packet + else if (cur_rx_eop[CH0]) begin + fill_payload_lsb(CH0, hdr_len[CH0], cur_tlp[CH0]); + rx_st_reg.tdata[CH0].eop <= 1'b1; + end + // Multi-cycle TLP, data payload + else if (cur_tlp[CH0].valid) begin + fill_payload_lsb(CH0, hdr_len[CH0], cur_tlp[CH0]); + fill_payload_msb(CH0, hdr_len[CH0], next_tlp[CH0]); + if (next_rx_eop[CH0] && hdr_len[CH0] >= (AVST_DWORD_LEN - next_tlp[CH0].empty)) begin + rx_st_reg.tdata[CH0].eop <= 1'b1; + empty <= 1'b1; + end + end + end + end + end + end else begin + if (rx_ready) begin + empty <= 1'b0; + rx_st_reg.tvalid <= 1'b0; + + for (int ch=0; ch= (AVST_DWORD_LEN - cur_tlp[CH1].empty)) begin + rx_st_reg.tdata[CH0].eop <= 1'b1; + end else begin + rx_st_reg.tdata[CH1].valid <= 1'b1; + rx_st_reg.tdata[CH1].eop <= 1'b1; + end + end + // Start of multi-cycle TLP, SOP on channel 0 and channel 1 carries data payload + else begin + // H-tile PCIe HIP IP places packet on channel 1 when there is packet on channel 0 for a multi-cycle TLP + // i.e. when CH0.valid=1, then it is safe to assume CH1.valid=1 + fill_payload_msb(CH0, hdr_len[CH0], cur_tlp[CH1]); + fill_payload_lsb(CH1, hdr_len[CH0], cur_tlp[CH1]); + fill_payload_msb(CH1, hdr_len[CH0], next_tlp[CH0]); + + rx_st_reg.tdata[CH0].valid <= 1'b1; + rx_st_reg.tdata[CH1].valid <= 1'b1; + + if (next_rx_eop[CH0] && hdr_len[CH0] >= (AVST_DWORD_LEN - next_tlp[CH0].empty)) begin + rx_st_reg.tdata[CH1].eop <= 1'b1; + empty <= 1'b1; + end + end + end + // End of multi-cycle TLP on channel 0 + else if (cur_rx_eop[CH0]) begin + fill_payload_lsb(CH0, hdr_len[CH0], cur_tlp[CH0]); + rx_st_reg.tdata[CH0].valid <= 1'b1; + rx_st_reg.tdata[CH0].eop <= 1'b1; + end + // End of multi-cycle TLP on channel 1, channel 0 carries the data payload + else if (cur_tlp[CH0].valid && cur_rx_eop[CH1]) begin + fill_payload_lsb(CH0, hdr_len[CH0], cur_tlp[CH0]); + fill_payload_msb(CH0, hdr_len[CH0], cur_tlp[CH1]); + fill_payload_lsb(CH1, hdr_len[CH0], cur_tlp[CH1]); + + rx_st_reg.tdata[CH0].valid <= 1'b1; + if (hdr_len[CH0] >= (AVST_DWORD_LEN - cur_tlp[CH1].empty)) begin + rx_st_reg.tdata[CH0].eop <= 1'b1; + end else begin + rx_st_reg.tdata[CH1].valid <= 1'b1; + rx_st_reg.tdata[CH1].eop <= 1'b1; + end + end + // Mid of multi-cycle TLP: both channels carry the data payload + else if (cur_tlp[CH0].valid) begin + // H-tile PCIe HIP IP places packet on channel 1 when there is packet on channel 0 for a multi-cycle TLP + // i.e. when CH0.valid=1, then it is safe to assume CH1.valid=1 + fill_payload_lsb(CH0, hdr_len[CH0], cur_tlp[CH0]); + fill_payload_msb(CH0, hdr_len[CH0], cur_tlp[CH1]); + fill_payload_lsb(CH1, hdr_len[CH0], cur_tlp[CH1]); + fill_payload_msb(CH1, hdr_len[CH0], next_tlp[CH0]); + + rx_st_reg.tdata[CH0].valid <= 1'b1; + rx_st_reg.tdata[CH1].valid <= 1'b1; + if (next_rx_eop[CH0] && hdr_len[CH0] >= (AVST_DWORD_LEN - next_tlp[CH0].empty)) begin + rx_st_reg.tdata[CH1].eop <= 1'b1; + empty <= 1'b1; + end + end + end + + // Channel 1 + if (cur_rx_sop[CH1]) begin + rx_st_reg.tvalid <= 1'b1; + rx_st_reg.tdata[CH1].valid <= 1'b1; + + fill_payload_lsb(CH1, hdr_len[CH1], cur_tlp[CH1]); + // Start of single cycle TLP on channel 1 + if (cur_rx_eop[CH1]) begin + rx_st_reg.tdata[CH1].eop <= 1'b1; + end + // Start of multi-cycle TLP on channel 1 + else begin + fill_payload_msb(CH1, hdr_len[CH1], next_tlp[CH0]); + if (next_rx_eop[CH0] && hdr_len[CH1] >= (AVST_DWORD_LEN - next_tlp[CH0].empty)) begin + rx_st_reg.tdata[CH1].eop <= 1'b1; + empty <= 1'b1; + end + end + end + end + end + end + + if (~avl_rst_n) begin + empty <= 1'b0; + rx_st_reg.tvalid <= 1'b0; + for (int ch=0; ch data: +// +// AXIS header and data +// [TLP CH0] (SOP) header:<128-bit header> data: +// [TLP CH1] (EOP} header: data: +// +// ------- +// Clock domain +// ------- +// All the inputs and outputs are synchronous to input clock : avl_clk +// +//----------------------------------------------------------------------------- + +import ofs_fim_pcie_pkg::*; +import ofs_fim_if_pkg::*; + +module pcie_rx_bridge_ptile ( + input logic avl_clk, + input logic avl_rst_n, + + input t_avst_rxs avl_rx_st, + output logic avl_rx_ready, + + ofs_fim_pcie_rxs_axis_if.master axis_rx_st +); + +t_avst_ch in_tlp_valid; +logic cur_tlp_valid; +t_avst_rxs cur_tlp; +t_avst_ch cur_rx_sop, cur_rx_eop; + +logic rx_ready; +t_axis_pcie_rxs rx_st_reg; + +////////////////////////////////////////////////////////////// + +// Interface assignment +assign axis_rx_st.clk = avl_clk; +assign axis_rx_st.rst_n = avl_rst_n; +assign axis_rx_st.rx = rx_st_reg; + +// Load the pipeline if there is no pending transfer or the current transfer is acknowledged +assign rx_ready = ~rx_st_reg.tvalid | axis_rx_st.tready; +assign avl_rx_ready = rx_ready; + +//----------------------------- +// Register new TLP when bridge is ready to process the next TLP +// Otherwise, keep the current TLP in the register +//----------------------------- +// TLP valid +always_comb begin + for (int ch=0; ch AXIS +pcie_bridge pcie_bridge ( + .fim_clk (fim_clk), + .fim_rst_n (fim_rst_n), + + .avl_clk (avl_clk), + .avl_rst_n (~reset_status), + + .avl_rx_ready (avl_rx_ready), + .avl_rx_st (avl_rx_st), + .avl_tx_ready (avl_tx_ready), + .avl_tx_st (avl_tx_st), + + .fim_axis_rx_st (axis_rx_st), + .fim_axis_tx_st (axis_tx_st), + + .b2a_app_err_valid (b2a_app_err_valid), + .b2a_app_err_hdr (b2a_app_err_hdr), + .b2a_app_err_info (b2a_app_err_info), + .b2a_app_err_func_num (b2a_app_err_func_num), + + .chk_rx_err (chk_rx_err), + .chk_rx_err_vf_act (chk_rx_err_vf_act), + .chk_rx_err_pfn (chk_rx_err_pfn), + .chk_rx_err_vfn (chk_rx_err_vfn), + .chk_rx_err_code (chk_rx_err_code) +); + +// CSRs +pcie_csr pcie_csr ( + .csr_if (csr_if), + + // CSR input signals + .avl_clk (avl_clk), + .i_pcie_linkup (pcie_linkup), + .i_chk_rx_err (chk_rx_err), + .i_chk_rx_err_vf_act (chk_rx_err_vf_act), + .i_chk_rx_err_pfn (chk_rx_err_pfn), + .i_chk_rx_err_vfn (chk_rx_err_vfn), + .i_chk_rx_err_code (chk_rx_err_code), + + // CSR output signals + .o_pcie_linkup (pcie_p2c_sideband.pcie_linkup), + .o_chk_rx_err_code (pcie_p2c_sideband.pcie_chk_rx_err_code) +); + +pcie_flr_resync pcie_flr_resync ( + .avl_clk (avl_clk), + .avl_rst_n (~reset_status), + + .fim_clk (fim_clk), + .fim_rst_n (fim_rst_n), + + .p2f_sideband (p2f_sideband), + .f2p_sideband (f2p_sideband), + + .pcie_p2f_sideband (pcie_p2f_sideband), + .pcie_c2p_sideband (pcie_c2p_sideband) + +); +always_comb begin + pcie_p2c_sideband.flr_active_pf = pcie_p2f_sideband.flr_active_pf; + pcie_p2c_sideband.flr_rcvd_vf = pcie_p2f_sideband.flr_rcvd_vf; + pcie_p2c_sideband.flr_rcvd_pf_num = pcie_p2f_sideband.flr_rcvd_pf_num; + pcie_p2c_sideband.flr_rcvd_vf_num = pcie_p2f_sideband.flr_rcvd_vf_num; + pcie_p2c_sideband.cfg_ctl.vf0_msix_mask = pcie_p2msix_sideband.cfg_ctl.vf0_msix_mask; +end + +pcie_msix_resync pcie_msix_resync ( + .avl_clk (avl_clk), + .avl_rst_n (~reset_status), + + .fim_clk (fim_clk), + .fim_rst_n (fim_rst_n), + + .pcie_p2msix_sideband (pcie_p2msix_sideband), + + .ctl_shdw_update (ctl_shdw_update), + .ctl_shdw_pf_num (ctl_shdw_pf_num), + .ctl_shdw_vf_num (ctl_shdw_vf_num), + .ctl_shdw_cfg (ctl_shdw_cfg), + .ctl_shdw_vf_active (ctl_shdw_vf_active), + .ctl_shdw_req_all (ctl_shdw_req_all) +); + + +//-------------- +// PCIe HIP IP +//-------------- +logic [66:0] hip_test_in; +// Set test_in[0]=1 to turn on diag_fast_link_mode to speed up simulation +assign hip_test_in = 67'h1; +// FME Interface + +pcie_ep_g3x16 dut ( + .clr_st (/*Not used*/), + + // Config interface + .tl_cfg_func (tl_cfg_func), + .tl_cfg_add (tl_cfg_add), + .tl_cfg_ctl (tl_cfg_ctl), + + // Error interface + .app_err_valid (b2a_app_err_valid), + .app_err_hdr (b2a_app_err_hdr), + .app_err_info (b2a_app_err_info), + .app_err_func_num (b2a_app_err_func_num), + + // Control shadow signals +// .ctl_shdw_update (ctl_shdw_update), +// .ctl_shdw_pf_num (ctl_shdw_pf_num), +// .ctl_shdw_vf_num (ctl_shdw_vf_num), +// .ctl_shdw_cfg (ctl_shdw_cfg), +// .ctl_shdw_vf_active (ctl_shdw_vf_active), +// .ctl_shdw_req_all (ctl_shdw_req_all), + + .ctl_shdw_update (), + .ctl_shdw_pf_num (), + .ctl_shdw_vf_num (), + .ctl_shdw_cfg (), + .ctl_shdw_vf_active (), + .ctl_shdw_req_all ('0), + + .coreclkout_hip (coreclkout_hip), + .currentspeed (/*Not used*/), + + // FLR signals + .flr_pf_done (f2p_sideband.flr_completed_pf), + .flr_pf_active (p2f_sideband.flr_active_pf), + .flr_rcvd_vf (p2f_sideband.flr_rcvd_vf), + .flr_rcvd_pf_num (p2f_sideband.flr_rcvd_pf_num), + .flr_rcvd_vf_num (p2f_sideband.flr_rcvd_vf_num), + .flr_completed_vf (f2p_sideband.flr_completed_vf), + .flr_completed_pf_num (f2p_sideband.flr_completed_pf_num), + .flr_completed_vf_num (f2p_sideband.flr_completed_vf_num), + + // Simulation only parameters + .test_in (hip_test_in), +//`ifndef SIM_MODE_PIPE32 +// .simu_mode_pipe (1'b0), +// .sim_pipe_pclk_in (1'b0), +//`else +// .simu_mode_pipe (/* allow simulation setting */), +// .sim_pipe_pclk_in (/* allow simulation setting */), +//`endif +`ifndef SIM_SERIAL + .simu_mode_pipe (), + .sim_pipe_pclk_in (), +`else + .simu_mode_pipe (1'b0), + .sim_pipe_pclk_in (1'b0), +`endif // SIM_SERIAL + .sim_pipe_rate (/*Not used : sim-only*/), + .sim_ltssmstate (/*Not used*/), + .txdata0 (/*Not used : sim-only*/), + .txdata1 (/*Not used : sim-only*/), + .txdata2 (/*Not used : sim-only*/), + .txdata3 (/*Not used : sim-only*/), + .txdata4 (/*Not used : sim-only*/), + .txdata5 (/*Not used : sim-only*/), + .txdata6 (/*Not used : sim-only*/), + .txdata7 (/*Not used : sim-only*/), + .txdatak0 (/*Not used : sim-only*/), + .txdatak1 (/*Not used : sim-only*/), + .txdatak2 (/*Not used : sim-only*/), + .txdatak3 (/*Not used : sim-only*/), + .txdatak4 (/*Not used : sim-only*/), + .txdatak5 (/*Not used : sim-only*/), + .txdatak6 (/*Not used : sim-only*/), + .txdatak7 (/*Not used : sim-only*/), + .txcompl0 (/*Not used : sim-only*/), + .txcompl1 (/*Not used : sim-only*/), + .txcompl2 (/*Not used : sim-only*/), + .txcompl3 (/*Not used : sim-only*/), + .txcompl4 (/*Not used : sim-only*/), + .txcompl5 (/*Not used : sim-only*/), + .txcompl6 (/*Not used : sim-only*/), + .txcompl7 (/*Not used : sim-only*/), + .txelecidle0 (/*Not used : sim-only*/), + .txelecidle1 (/*Not used : sim-only*/), + .txelecidle2 (/*Not used : sim-only*/), + .txelecidle3 (/*Not used : sim-only*/), + .txelecidle4 (/*Not used : sim-only*/), + .txelecidle5 (/*Not used : sim-only*/), + .txelecidle6 (/*Not used : sim-only*/), + .txelecidle7 (/*Not used : sim-only*/), + .txdetectrx0 (/*Not used : sim-only*/), + .txdetectrx1 (/*Not used : sim-only*/), + .txdetectrx2 (/*Not used : sim-only*/), + .txdetectrx3 (/*Not used : sim-only*/), + .txdetectrx4 (/*Not used : sim-only*/), + .txdetectrx5 (/*Not used : sim-only*/), + .txdetectrx6 (/*Not used : sim-only*/), + .txdetectrx7 (/*Not used : sim-only*/), + .powerdown0 (/*Not used : sim-only*/), + .powerdown1 (/*Not used : sim-only*/), + .powerdown2 (/*Not used : sim-only*/), + .powerdown3 (/*Not used : sim-only*/), + .powerdown4 (/*Not used : sim-only*/), + .powerdown5 (/*Not used : sim-only*/), + .powerdown6 (/*Not used : sim-only*/), + .powerdown7 (/*Not used : sim-only*/), + .txmargin0 (/*Not used : sim-only*/), + .txmargin1 (/*Not used : sim-only*/), + .txmargin2 (/*Not used : sim-only*/), + .txmargin3 (/*Not used : sim-only*/), + .txmargin4 (/*Not used : sim-only*/), + .txmargin5 (/*Not used : sim-only*/), + .txmargin6 (/*Not used : sim-only*/), + .txmargin7 (/*Not used : sim-only*/), + .txdeemph0 (/*Not used : sim-only*/), + .txdeemph1 (/*Not used : sim-only*/), + .txdeemph2 (/*Not used : sim-only*/), + .txdeemph3 (/*Not used : sim-only*/), + .txdeemph4 (/*Not used : sim-only*/), + .txdeemph5 (/*Not used : sim-only*/), + .txdeemph6 (/*Not used : sim-only*/), + .txdeemph7 (/*Not used : sim-only*/), + .txswing0 (/*Not used : sim-only*/), + .txswing1 (/*Not used : sim-only*/), + .txswing2 (/*Not used : sim-only*/), + .txswing3 (/*Not used : sim-only*/), + .txswing4 (/*Not used : sim-only*/), + .txswing5 (/*Not used : sim-only*/), + .txswing6 (/*Not used : sim-only*/), + .txswing7 (/*Not used : sim-only*/), + .txsynchd0 (/*Not used : sim-only*/), + .txsynchd1 (/*Not used : sim-only*/), + .txsynchd2 (/*Not used : sim-only*/), + .txsynchd3 (/*Not used : sim-only*/), + .txsynchd4 (/*Not used : sim-only*/), + .txsynchd5 (/*Not used : sim-only*/), + .txsynchd6 (/*Not used : sim-only*/), + .txsynchd7 (/*Not used : sim-only*/), + .txblkst0 (/*Not used : sim-only*/), + .txblkst1 (/*Not used : sim-only*/), + .txblkst2 (/*Not used : sim-only*/), + .txblkst3 (/*Not used : sim-only*/), + .txblkst4 (/*Not used : sim-only*/), + .txblkst5 (/*Not used : sim-only*/), + .txblkst6 (/*Not used : sim-only*/), + .txblkst7 (/*Not used : sim-only*/), + .txdataskip0 (/*Not used : sim-only*/), + .txdataskip1 (/*Not used : sim-only*/), + .txdataskip2 (/*Not used : sim-only*/), + .txdataskip3 (/*Not used : sim-only*/), + .txdataskip4 (/*Not used : sim-only*/), + .txdataskip5 (/*Not used : sim-only*/), + .txdataskip6 (/*Not used : sim-only*/), + .txdataskip7 (/*Not used : sim-only*/), + .rate0 (/*Not used : sim-only*/), + .rate1 (/*Not used : sim-only*/), + .rate2 (/*Not used : sim-only*/), + .rate3 (/*Not used : sim-only*/), + .rate4 (/*Not used : sim-only*/), + .rate5 (/*Not used : sim-only*/), + .rate6 (/*Not used : sim-only*/), + .rate7 (/*Not used : sim-only*/), + .rxpolarity0 (/*Not used : sim-only*/), + .rxpolarity1 (/*Not used : sim-only*/), + .rxpolarity2 (/*Not used : sim-only*/), + .rxpolarity3 (/*Not used : sim-only*/), + .rxpolarity4 (/*Not used : sim-only*/), + .rxpolarity5 (/*Not used : sim-only*/), + .rxpolarity6 (/*Not used : sim-only*/), + .rxpolarity7 (/*Not used : sim-only*/), + .currentrxpreset0 (/*Not used : sim-only*/), + .currentrxpreset1 (/*Not used : sim-only*/), + .currentrxpreset2 (/*Not used : sim-only*/), + .currentrxpreset3 (/*Not used : sim-only*/), + .currentrxpreset4 (/*Not used : sim-only*/), + .currentrxpreset5 (/*Not used : sim-only*/), + .currentrxpreset6 (/*Not used : sim-only*/), + .currentrxpreset7 (/*Not used : sim-only*/), + .currentcoeff0 (/*Not used : sim-only*/), + .currentcoeff1 (/*Not used : sim-only*/), + .currentcoeff2 (/*Not used : sim-only*/), + .currentcoeff3 (/*Not used : sim-only*/), + .currentcoeff4 (/*Not used : sim-only*/), + .currentcoeff5 (/*Not used : sim-only*/), + .currentcoeff6 (/*Not used : sim-only*/), + .currentcoeff7 (/*Not used : sim-only*/), + .rxeqeval0 (/*Not used : sim-only*/), + .rxeqeval1 (/*Not used : sim-only*/), + .rxeqeval2 (/*Not used : sim-only*/), + .rxeqeval3 (/*Not used : sim-only*/), + .rxeqeval4 (/*Not used : sim-only*/), + .rxeqeval5 (/*Not used : sim-only*/), + .rxeqeval6 (/*Not used : sim-only*/), + .rxeqeval7 (/*Not used : sim-only*/), + .rxeqinprogress0 (/*Not used : sim-only*/), + .rxeqinprogress1 (/*Not used : sim-only*/), + .rxeqinprogress2 (/*Not used : sim-only*/), + .rxeqinprogress3 (/*Not used : sim-only*/), + .rxeqinprogress4 (/*Not used : sim-only*/), + .rxeqinprogress5 (/*Not used : sim-only*/), + .rxeqinprogress6 (/*Not used : sim-only*/), + .rxeqinprogress7 (/*Not used : sim-only*/), + .invalidreq0 (/*Not used : sim-only*/), + .invalidreq1 (/*Not used : sim-only*/), + .invalidreq2 (/*Not used : sim-only*/), + .invalidreq3 (/*Not used : sim-only*/), + .invalidreq4 (/*Not used : sim-only*/), + .invalidreq5 (/*Not used : sim-only*/), + .invalidreq6 (/*Not used : sim-only*/), + .invalidreq7 (/*Not used : sim-only*/), + .rxdata0 (/*Not used : sim-only*/), + .rxdata1 (/*Not used : sim-only*/), + .rxdata2 (/*Not used : sim-only*/), + .rxdata3 (/*Not used : sim-only*/), + .rxdata4 (/*Not used : sim-only*/), + .rxdata5 (/*Not used : sim-only*/), + .rxdata6 (/*Not used : sim-only*/), + .rxdata7 (/*Not used : sim-only*/), + .rxdatak0 (/*Not used : sim-only*/), + .rxdatak1 (/*Not used : sim-only*/), + .rxdatak2 (/*Not used : sim-only*/), + .rxdatak3 (/*Not used : sim-only*/), + .rxdatak4 (/*Not used : sim-only*/), + .rxdatak5 (/*Not used : sim-only*/), + .rxdatak6 (/*Not used : sim-only*/), + .rxdatak7 (/*Not used : sim-only*/), + .phystatus0 (/*Not used : sim-only*/), + .phystatus1 (/*Not used : sim-only*/), + .phystatus2 (/*Not used : sim-only*/), + .phystatus3 (/*Not used : sim-only*/), + .phystatus4 (/*Not used : sim-only*/), + .phystatus5 (/*Not used : sim-only*/), + .phystatus6 (/*Not used : sim-only*/), + .phystatus7 (/*Not used : sim-only*/), + .rxvalid0 (/*Not used : sim-only*/), + .rxvalid1 (/*Not used : sim-only*/), + .rxvalid2 (/*Not used : sim-only*/), + .rxvalid3 (/*Not used : sim-only*/), + .rxvalid4 (/*Not used : sim-only*/), + .rxvalid5 (/*Not used : sim-only*/), + .rxvalid6 (/*Not used : sim-only*/), + .rxvalid7 (/*Not used : sim-only*/), + .rxstatus0 (/*Not used : sim-only*/), + .rxstatus1 (/*Not used : sim-only*/), + .rxstatus2 (/*Not used : sim-only*/), + .rxstatus3 (/*Not used : sim-only*/), + .rxstatus4 (/*Not used : sim-only*/), + .rxstatus5 (/*Not used : sim-only*/), + .rxstatus6 (/*Not used : sim-only*/), + .rxstatus7 (/*Not used : sim-only*/), + .rxelecidle0 (/*Not used : sim-only*/), + .rxelecidle1 (/*Not used : sim-only*/), + .rxelecidle2 (/*Not used : sim-only*/), + .rxelecidle3 (/*Not used : sim-only*/), + .rxelecidle4 (/*Not used : sim-only*/), + .rxelecidle5 (/*Not used : sim-only*/), + .rxelecidle6 (/*Not used : sim-only*/), + .rxelecidle7 (/*Not used : sim-only*/), + .rxsynchd0 (/*Not used : sim-only*/), + .rxsynchd1 (/*Not used : sim-only*/), + .rxsynchd2 (/*Not used : sim-only*/), + .rxsynchd3 (/*Not used : sim-only*/), + .rxsynchd4 (/*Not used : sim-only*/), + .rxsynchd5 (/*Not used : sim-only*/), + .rxsynchd6 (/*Not used : sim-only*/), + .rxsynchd7 (/*Not used : sim-only*/), + .rxblkst0 (/*Not used : sim-only*/), + .rxblkst1 (/*Not used : sim-only*/), + .rxblkst2 (/*Not used : sim-only*/), + .rxblkst3 (/*Not used : sim-only*/), + .rxblkst4 (/*Not used : sim-only*/), + .rxblkst5 (/*Not used : sim-only*/), + .rxblkst6 (/*Not used : sim-only*/), + .rxblkst7 (/*Not used : sim-only*/), + .rxdataskip0 (/*Not used : sim-only*/), + .rxdataskip1 (/*Not used : sim-only*/), + .rxdataskip2 (/*Not used : sim-only*/), + .rxdataskip3 (/*Not used : sim-only*/), + .rxdataskip4 (/*Not used : sim-only*/), + .rxdataskip5 (/*Not used : sim-only*/), + .rxdataskip6 (/*Not used : sim-only*/), + .rxdataskip7 (/*Not used : sim-only*/), + .dirfeedback0 (/*Not used : sim-only*/), + .dirfeedback1 (/*Not used : sim-only*/), + .dirfeedback2 (/*Not used : sim-only*/), + .dirfeedback3 (/*Not used : sim-only*/), + .dirfeedback4 (/*Not used : sim-only*/), + .dirfeedback5 (/*Not used : sim-only*/), + .dirfeedback6 (/*Not used : sim-only*/), + .dirfeedback7 (/*Not used : sim-only*/), + .sim_pipe_mask_tx_pll_lock (/*Not used : sim-only*/), + + .reset_status (reset_status), + .serdes_pll_locked (avl_clk_enable), + .pld_core_ready (avl_clk_enable), + .pld_clk_inuse (/*Not used, use reset_status instead for S10*/), + .testin_zero (/*Not used*/), + // PCIe pins + .rx_in0 (pin_pcie_rx_p[0]), + .rx_in1 (pin_pcie_rx_p[1]), + .rx_in2 (pin_pcie_rx_p[2]), + .rx_in3 (pin_pcie_rx_p[3]), + .rx_in4 (pin_pcie_rx_p[4]), + .rx_in5 (pin_pcie_rx_p[5]), + .rx_in6 (pin_pcie_rx_p[6]), + .rx_in7 (pin_pcie_rx_p[7]), + .rx_in8 (pin_pcie_rx_p[8]), + .rx_in9 (pin_pcie_rx_p[9]), + .rx_in10 (pin_pcie_rx_p[10]), + .rx_in11 (pin_pcie_rx_p[11]), + .rx_in12 (pin_pcie_rx_p[12]), + .rx_in13 (pin_pcie_rx_p[13]), + .rx_in14 (pin_pcie_rx_p[14]), + .rx_in15 (pin_pcie_rx_p[15]), + .tx_out0 (pin_pcie_tx_p[0]), + .tx_out1 (pin_pcie_tx_p[1]), + .tx_out2 (pin_pcie_tx_p[2]), + .tx_out3 (pin_pcie_tx_p[3]), + .tx_out4 (pin_pcie_tx_p[4]), + .tx_out5 (pin_pcie_tx_p[5]), + .tx_out6 (pin_pcie_tx_p[6]), + .tx_out7 (pin_pcie_tx_p[7]), + .tx_out8 (pin_pcie_tx_p[8]), + .tx_out9 (pin_pcie_tx_p[9]), + .tx_out10 (pin_pcie_tx_p[10]), + .tx_out11 (pin_pcie_tx_p[11]), + .tx_out12 (pin_pcie_tx_p[12]), + .tx_out13 (pin_pcie_tx_p[13]), + .tx_out14 (pin_pcie_tx_p[14]), + .tx_out15 (pin_pcie_tx_p[15]), + .int_status (/*Not used*/), + .int_status_common (/*Not used*/), + .derr_cor_ext_rpl (/*Not used*/), + .derr_rpl (/*Not used*/), + .derr_cor_ext_rcv (/*Not used*/), + .derr_uncor_ext_rcv (/*Not used*/), + .rx_par_err (/*Not used*/), + .tx_par_err (/*Not used*/), + .ltssmstate (ltssmstate), + .link_up (hip_linkup), + .lane_act (/*Not used*/), + // MSI interface + .app_msi_req ('0 /*Not used, tied to 0*/), + .app_msi_ack (/*Not used*/), + .app_msi_tc ('0 /*Not used, tied to 0*/), + .app_msi_num ('0 /*Not used, tied to 0*/), + .app_int_sts ('0 /*Not used, tied to 0*/), + .app_msi_func_num ('0 /*Not used, tied to 0*/), + // PF/VF + .rx_st_vf_active (rx_st_vf_active), + .rx_st_func_num (rx_st_func_num), + .rx_st_vf_num (rx_st_vf_num), + .tx_st_vf_active (tx_st_vf_active), + // Clock and reset + .ninit_done (ninit_done), + .npor (npor), + .pin_perst (pin_pcie_in_perst_n), + .pm_linkst_in_l1 (/*Not used*/), + .pm_linkst_in_l0s (/*Not used*/), + .pm_state (/*Not used*/), + .pm_dstate (/*Not used*/), + .apps_pm_xmt_pme ('0 /*Not used, tied to 0*/), + .apps_ready_entr_l23 ('0 /*Not used, tied to 0*/), + .apps_pm_xmt_turnoff ('0 /*Not used, tied to 0*/), + .app_init_rst ('0 /*Not used, tied to 0*/), + .app_xfer_pending ('0 /*Not used, tied to 0*/), + .refclk (pin_pcie_ref_clk_p), + // Rx streaming channels + .rx_st_bar_range (rx_st_bar), + .rx_st_ready (avl_rx_ready), + .rx_st_sop (rx_st_sop), + .rx_st_eop (rx_st_eop), + .rx_st_data (rx_st_data), + .rx_st_valid (rx_st_valid), + .rx_st_empty (rx_st_empty), + // Credit interface + .tx_cdts_type (), + .tx_data_cdts_consumed (), + .tx_hdr_cdts_consumed (), + .tx_cdts_data_value (), + .tx_cpld_cdts (), + .tx_pd_cdts (), + .tx_npd_cdts (), + .tx_cplh_cdts (), + .tx_ph_cdts (), + .tx_nph_cdts (), + // Tx streaming channels + .tx_st_sop (tx_st_sop), + .tx_st_eop (tx_st_eop), + .tx_st_data (tx_st_data), + .tx_st_valid (tx_st_valid), + .tx_st_err (tx_st_err), + .tx_st_ready (avl_tx_ready) +); + +endmodule diff --git a/ipss/pcie/rtl/pcie_tx_arbiter.sv b/ipss/pcie/rtl/pcie_tx_arbiter.sv new file mode 100755 index 0000000..e8eb3cd --- /dev/null +++ b/ipss/pcie/rtl/pcie_tx_arbiter.sv @@ -0,0 +1,260 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// PCIe TX arbiter arbitrates betwen the TLP packets from MMIO AXIS-TX channel, +// MSIX AXIS-TX channel and AFU AXIS-TX channel +// +// The arbiter makes sure TLP packets which belong to the same TLP request/response +// are sent contiguously upstream. +// +//----------------------------------------------------------------------------- + +import ofs_fim_if_pkg::*; + +module pcie_tx_arbiter #( +)( + input logic clk, + input logic rst_n, + + ofs_fim_pcie_tx_axis_if.slave i_mmio_tx_st, + ofs_fim_pcie_txs_axis_if.slave i_afu_tx_st, + ofs_fim_pcie_tx_axis_if.slave i_msix_tx_st, + + ofs_fim_pcie_txs_axis_if.master o_pcie_tx_st +); + +t_axis_pcie_txs pcie_tx_q; +t_axis_pcie_tx mmio_tx_st; +t_axis_pcie_txs afu_tx_st; +t_axis_pcie_tx msix_tx_st; + +logic mmio_tx_tready_q; +logic afu_tx_tready_q; +logic msix_tx_tready_q; + +logic pcie_tx_tready; + +//************************** +// Interface assignment +//************************** +// MMIO input +assign mmio_tx_st = i_mmio_tx_st.tx; +assign i_mmio_tx_st.tready = mmio_tx_tready_q; + +// AFU input +assign afu_tx_st = i_afu_tx_st.tx; +assign i_afu_tx_st.tready = afu_tx_tready_q; + +// MSIX input, not implemented yet +assign msix_tx_st = i_msix_tx_st.tx; +assign i_msix_tx_st.tready = msix_tx_tready_q; + +// PCIe Tx output to upstream +assign o_pcie_tx_st.tx = pcie_tx_q; +assign o_pcie_tx_st.clk = clk; +assign o_pcie_tx_st.rst_n = rst_n; +assign pcie_tx_tready = o_pcie_tx_st.tready; + +// State definitions for user state machine +typedef enum logic [4:0] { + ARB_FSM_RESET, + ARB_FSM_IDLE, + ARB_FSM_MMIO, + ARB_FSM_AFU, + ARB_FSM_MSIX +} t_arbiter_state; + +(* syn_encoding = "one-hot" *) t_arbiter_state arbiter_state; + +typedef enum logic [2:0] { + ISTREAM_NONE, + ISTREAM_MMIO, + ISTREAM_AFU, + ISTREAM_MSIX +} t_input_streams; + +(* syn_encoding = "one-hot" *) t_input_streams istream_last; + +// Favor the AFU path. Allow AFU traffic while the arbiter is idle as long as +// no other ports have requests. +logic no_fim_tx_is_valid; +logic afu_tx_grant_while_idle; +logic afu_tx_is_eop; +t_arbiter_state afu_tx_state_from_idle; + +// Grant AFU traffic in idle when only AFU traffic is present +assign no_fim_tx_is_valid = ~mmio_tx_st.tvalid && ~msix_tx_st.tvalid; +assign afu_tx_grant_while_idle = pcie_tx_tready && no_fim_tx_is_valid; + +// Is the incoming AFU traffic EOP? +assign afu_tx_is_eop = ((afu_tx_st.tdata[1].valid & afu_tx_st.tdata[1].eop) || + (afu_tx_st.tdata[0].valid & afu_tx_st.tdata[0].eop & ~afu_tx_st.tdata[1].valid)); + +// Does the AFU traffic need to hold AFU arbitration now that it was granted +// during idle? +assign afu_tx_state_from_idle = + (afu_tx_grant_while_idle && afu_tx_is_eop) ? ARB_FSM_IDLE : ARB_FSM_AFU; + + +// Fair arbiter between MMIO, AFU, and MSIX interrupt streams +always_ff @(posedge clk) begin : ARB_FSM + case (arbiter_state) + // --------------------------------------------------- + ARB_FSM_RESET: + begin + arbiter_state <= ARB_FSM_RESET; + istream_last <= ISTREAM_NONE; + if (rst_n) begin + arbiter_state <= ARB_FSM_IDLE; + end + end + // --------------------------------------------------- + ARB_FSM_IDLE: + begin + arbiter_state <= ARB_FSM_IDLE; + case (istream_last) + ISTREAM_MMIO: + begin + if (afu_tx_st.tvalid) begin + arbiter_state <= afu_tx_state_from_idle; + end + else if (msix_tx_st.tvalid) begin + arbiter_state <= ARB_FSM_MSIX; + end + else if (mmio_tx_st.tvalid) begin + arbiter_state <= ARB_FSM_MMIO; + end + else begin + arbiter_state <= ARB_FSM_IDLE; + end + end + ISTREAM_AFU: + begin + if (msix_tx_st.tvalid) begin + arbiter_state <= ARB_FSM_MSIX; + end + else if (mmio_tx_st.tvalid) begin + arbiter_state <= ARB_FSM_MMIO; + end + else if (afu_tx_st.tvalid) begin + arbiter_state <= afu_tx_state_from_idle; + end + else begin + arbiter_state <= ARB_FSM_IDLE; + end + end + default: + begin + if (mmio_tx_st.tvalid) begin + arbiter_state <= ARB_FSM_MMIO; + end + else if (afu_tx_st.tvalid) begin + arbiter_state <= afu_tx_state_from_idle; + end + else if (msix_tx_st.tvalid) begin + arbiter_state <= ARB_FSM_MSIX; + end + else begin + arbiter_state <= ARB_FSM_IDLE; + end + end + endcase + end + // --------------------------------------------------- + ARB_FSM_MMIO: + begin + arbiter_state <= ARB_FSM_MMIO; + istream_last <= ISTREAM_MMIO; + if (pcie_tx_tready & mmio_tx_st.tvalid & mmio_tx_st.tdata.valid & mmio_tx_st.tdata.eop) begin + arbiter_state <= ARB_FSM_IDLE; + end + end + // --------------------------------------------------- + ARB_FSM_AFU: + begin + arbiter_state <= ARB_FSM_AFU; + istream_last <= ISTREAM_AFU; + if (pcie_tx_tready & afu_tx_st.tvalid & afu_tx_is_eop) begin + arbiter_state <= ARB_FSM_IDLE; + end + end + // --------------------------------------------------- + ARB_FSM_MSIX: + begin + arbiter_state <= ARB_FSM_MSIX; + istream_last <= ISTREAM_MSIX; + if (pcie_tx_tready & msix_tx_st.tvalid & msix_tx_st.tdata.valid & msix_tx_st.tdata.eop) begin + arbiter_state <= ARB_FSM_IDLE; + end + end + // --------------------------------------------------- + default: + begin + // something went wrong + arbiter_state <= ARB_FSM_RESET; + end + endcase // arbiter_state + + if(~rst_n) begin + arbiter_state <= ARB_FSM_RESET; + end +end : ARB_FSM + +always_comb begin + // Arbitrate + case (arbiter_state) + ARB_FSM_MMIO: + begin + afu_tx_tready_q = 1'b0; + msix_tx_tready_q = 1'b0; + mmio_tx_tready_q = pcie_tx_tready; + pcie_tx_q.tvalid = mmio_tx_st.tvalid; + pcie_tx_q.tlast = mmio_tx_st.tlast; + pcie_tx_q.tdata[0] = mmio_tx_st.tdata; + pcie_tx_q.tuser[0] = mmio_tx_st.tuser; + if (FIM_PCIE_TLP_CH > 1) begin + pcie_tx_q.tdata[1] = '0; + pcie_tx_q.tuser[1] = '0; + end + end + ARB_FSM_AFU: + begin + mmio_tx_tready_q = 1'b0; + msix_tx_tready_q = 1'b0; + afu_tx_tready_q = pcie_tx_tready; + pcie_tx_q.tvalid = afu_tx_st.tvalid; + pcie_tx_q.tlast = afu_tx_st.tlast; + pcie_tx_q.tdata = afu_tx_st.tdata; + pcie_tx_q.tuser = afu_tx_st.tuser; + end + ARB_FSM_MSIX: + begin + mmio_tx_tready_q = 1'b0; + afu_tx_tready_q = 1'b0; + msix_tx_tready_q = pcie_tx_tready; + pcie_tx_q.tvalid = msix_tx_st.tvalid; + pcie_tx_q.tlast = msix_tx_st.tlast; + pcie_tx_q.tdata[0] = msix_tx_st.tdata; + pcie_tx_q.tuser[0] = msix_tx_st.tuser; + if (FIM_PCIE_TLP_CH > 1) begin + pcie_tx_q.tdata[1] = '0; + pcie_tx_q.tuser[1] = '0; + end + end + default: + begin + mmio_tx_tready_q = 1'b0; + msix_tx_tready_q = 1'b0; + afu_tx_tready_q = afu_tx_grant_while_idle; + pcie_tx_q.tvalid = afu_tx_st.tvalid && no_fim_tx_is_valid; + pcie_tx_q.tlast = afu_tx_st.tlast; + pcie_tx_q.tdata = afu_tx_st.tdata; + pcie_tx_q.tuser = afu_tx_st.tuser; + end + endcase +end + +endmodule diff --git a/ipss/pcie/rtl/pcie_tx_bridge.sv b/ipss/pcie/rtl/pcie_tx_bridge.sv new file mode 100755 index 0000000..05f8254 --- /dev/null +++ b/ipss/pcie/rtl/pcie_tx_bridge.sv @@ -0,0 +1,152 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Functions: +// Adapt AXI4-S TX streaming interface to PCIe HIP IP AVST TX interface +// * The AVST TX interface contains two 256-bit data channels +// * The AXI4-S TX interface contains single AXI4-S channel with multiple TLP data streams +// (See fim_if_pkg.sv for details) +// +// FIM requirement: +// 1) CPL timeout checker in pcie_checker can only handles one MRd per cycle. +// Bridge or downstream TX arbiter needs to make sure only one MRd is sent to pcie_checker per cycle +// +// PCIe HIP IP requirements: +// 1) The bridge needs to check for RX buffer credit (i.e. cpl_pending_data_cnt < credit limit) before sending non-posted request (MRd) +// If there is not enough credit for non-posted request, the bridge should stop sending non-posted request +// while continue sending other TLP packets +// One possible implementation is to move non-posted requests and other TLPs into separate FIFO and arbitrate between the two FIFOs +// 2) The bridge needs to make sure no idle cycle when transmitting packets of the same TLP, except when avl_tx_ready is de-asserted. +// One possible implementation is to buffer MWr packets until EOP is received before sending the packtes to PCIe IP +// 3) The bridge can only send packets to PCIe IP 3 cycles after avl_tx_ready is asserted. +// The bridge can send packets to PCIe IP for another 3 cycles following avl_tx_ready de-assertion. +// Add 2 pipeline stages to avl_tx_ready signal in the bridge to fulfill this requirement. +// +//----------------------------------------------------------------------------- + +import ofs_fim_pcie_pkg::*; +import ofs_fim_if_pkg::*; + +module pcie_tx_bridge ( + input logic avl_clk, + input logic avl_rst_n, + output t_avst_txs avl_tx_st, + input logic avl_tx_ready, + + ofs_fim_pcie_txs_axis_if.slave axis_tx_st, + + output logic tx_mrd_valid, + output logic [10:0] tx_mrd_length, + output logic [PCIE_EP_TAG_WIDTH-1:0] tx_mrd_tag, + output logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] tx_mrd_pfn, + output logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] tx_mrd_vfn, + output logic tx_mrd_vf_act, + input logic [CPL_CREDIT_WIDTH-1:0] cpl_pending_data_cnt +); + +`ifdef PTILE + pcie_tx_bridge_ptile pcie_tx_bridge_ptile ( + .avl_clk (avl_clk), + .avl_rst_n (avl_rst_n), + .avl_tx_st (avl_tx_st), + .avl_tx_ready (avl_tx_ready), + + .axis_tx_st (axis_tx_st), + + .tx_mrd_valid (tx_mrd_valid), + .tx_mrd_length (tx_mrd_length), + .tx_mrd_tag (tx_mrd_tag), + .tx_mrd_pfn (tx_mrd_pfn), + .tx_mrd_vfn (tx_mrd_vfn), + .tx_mrd_vf_act (tx_mrd_vf_act), + + .cpl_pending_data_cnt (cpl_pending_data_cnt) + ); +`else + pcie_tx_bridge_htile pcie_tx_bridge_htile ( + .avl_clk (avl_clk), + .avl_rst_n (avl_rst_n), + .avl_tx_st (avl_tx_st), + .avl_tx_ready (avl_tx_ready), + + .axis_tx_st (axis_tx_st), + + .tx_mrd_valid (tx_mrd_valid), + .tx_mrd_length (tx_mrd_length), + .tx_mrd_tag (tx_mrd_tag), + .tx_mrd_pfn (tx_mrd_pfn), + .tx_mrd_vfn (tx_mrd_vfn), + .tx_mrd_vf_act (tx_mrd_vf_act), + + .cpl_pending_data_cnt (cpl_pending_data_cnt) + ); +`endif + + +// synthesis translate_off + +initial +begin : tx_logger + static int log_fd = $fopen("log_ofs_fim_pcie_tx_bridge.tsv", "w"); + int cycle = 0; + forever @(posedge avl_clk) begin + if (avl_rst_n) begin + if (axis_tx_st.tready && axis_tx_st.tx.tvalid) begin + log_axis_tx_st(log_fd, "axis_tx_st", cycle, axis_tx_st.tx); + end + + log_avl_tx_st(log_fd, "avl_tx_st", cycle, avl_tx_st); + + cycle = cycle + 1; + end + end +end + +task log_axis_tx_st; + input int log_fd; + input string ctx_name; + input int cycle; + input t_axis_pcie_txs tx; +begin + for (int i = 0; i < FIM_PCIE_TLP_CH; i = i + 1) + begin + if (tx.tdata[i].valid) + begin + $fwrite(log_fd, "%s:\t%t [%d] ch%0d %s\n", + ctx_name, $time, cycle, i, + ofs_fim_pcie_hdr_def::func_flit_to_string(tx.tdata[i].sop, + tx.tdata[i].eop, + tx.tdata[i].hdr, + tx.tdata[i].payload)); + $fflush(log_fd); + end + end +end +endtask // log_afu_tx_st + +task log_avl_tx_st; + input int log_fd; + input string ctx_name; + input int cycle; + input t_avst_txs tx; +begin + for (int i = 0; i < FIM_PCIE_TLP_CH; i = i + 1) + begin + if (tx[i].valid) + begin + $fwrite(log_fd, "%s:\t%t [%d] ch%0d %s\n", + ctx_name, $time, cycle, i, + ofs_fim_pcie_pkg::func_tx_to_string(tx[i])); + + $fflush(log_fd); + end + end +end +endtask // log_avl_tx_st + +// synthesis translate_on + +endmodule diff --git a/ipss/pcie/rtl/pcie_tx_bridge_cdc.sv b/ipss/pcie/rtl/pcie_tx_bridge_cdc.sv new file mode 100755 index 0000000..a6ec422 --- /dev/null +++ b/ipss/pcie/rtl/pcie_tx_bridge_cdc.sv @@ -0,0 +1,74 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Functions: +// * Clock crossing PCIe TX bridge signals from FIM clock domain to PCIe clock domain +// +//----------------------------------------------------------------------------- + +import ofs_fim_pcie_pkg::*; +import ofs_fim_if_pkg::*; + +module pcie_tx_bridge_cdc ( + input logic pcie_clk, + input logic pcie_rst_n, + + ofs_fim_pcie_txs_axis_if.slave fim_axis_tx_st, + ofs_fim_pcie_txs_axis_if.master pcie_axis_tx_st +); + +logic fim_clk; +logic fim_rst_n; + +logic fifo_wrreq; +logic fifo_rdack; +logic fifo_full; +logic fifo_rvalid; + +t_axis_pcie_txs fifo_dout; + +///////////////////////////////////////////////////////////////// + +assign fim_clk = fim_axis_tx_st.clk; +assign fim_rst_n = fim_axis_tx_st.rst_n; + +assign fim_axis_tx_st.tready = ~fifo_full; +assign fifo_rdack = pcie_axis_tx_st.tready; + +// AXIS PCIe TX TLP FIFO +fim_rdack_dcfifo +#( + .DATA_WIDTH (AXIS_PCIE_TXS_WIDTH), + .DEPTH_LOG2 (8), // depth 256 + .ALMOST_FULL_THRESHOLD (8), // assert almfull when empty slots <= 8 + .READ_ACLR_SYNC ("ON") // add aclr synchronizer on read side +) +tx_axis_dcfifo +( + .wclk (fim_clk), + .rclk (pcie_clk), + .aclr (~fim_rst_n), + .wdata (fim_axis_tx_st.tx), + .wreq (fifo_wrreq), + .rdack (fifo_rdack), + .rdata (fifo_dout), + .wfull (fifo_full), + .rvalid (fifo_rvalid) +); + +// Write incoming AVL packets to FIFO when FIFO is not full +assign fifo_wrreq = ~fifo_full && fim_axis_tx_st.tx.tvalid; + +// PCIE AXIS IF assignment +assign pcie_axis_tx_st.clk = pcie_clk; +assign pcie_axis_tx_st.rst_n = pcie_rst_n; + +always_comb begin + pcie_axis_tx_st.tx = fifo_dout; + pcie_axis_tx_st.tx.tvalid = fifo_rvalid; +end + +endmodule diff --git a/ipss/pcie/rtl/pcie_tx_bridge_htile.sv b/ipss/pcie/rtl/pcie_tx_bridge_htile.sv new file mode 100755 index 0000000..37fa88a --- /dev/null +++ b/ipss/pcie/rtl/pcie_tx_bridge_htile.sv @@ -0,0 +1,1882 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// ------- +// Functions: +// ------- +// Adapt AXI4-S TX streaming interface to PCIe HIP IP AVST TX interface +// * The AVST TX interface contains two 256-bit data channels +// * The AXI4-S TX interface contains single AXI4-S channel with multiple TLP data streams +// (See fim_if_pkg.sv for details) +// Tracks cpl_pending_data_cnt from PCIe Checker and stalls MRd requests if RX buffer credit is low +// +// ------- +// Clock domain +// ------- +// All the inputs and outputs are synchronous to input clock : avl_clk +// +//----------------------------------------------------------------------------- + +import ofs_fim_pcie_pkg::*; +import ofs_fim_if_pkg::*; + +module pcie_tx_bridge_htile ( + input logic avl_clk, + input logic avl_rst_n, // Synchronous reset + output t_avst_txs avl_tx_st, + input logic avl_tx_ready, + + ofs_fim_pcie_txs_axis_if.slave axis_tx_st, + + output logic tx_mrd_valid, + output logic [PCIE_MAX_LEN_WIDTH-1:0] tx_mrd_length, + output logic [PCIE_EP_TAG_WIDTH-1:0] tx_mrd_tag, + output logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] tx_mrd_pfn, + output logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] tx_mrd_vfn, + output logic tx_mrd_vf_act, + + input logic [CPL_CREDIT_WIDTH-1:0] cpl_pending_data_cnt +); + +import ofs_fim_pcie_hdr_def::*; + +localparam AVST_WIDTH_DW = AVST_DW/(8*4); // 256/32=8DW + +// In order to fit a max payload length TLP of 64DW + max header size of 4DW, we need space for 68DW +// One FIFO word can store up to 2 channels * 8DW per channel = 16DW +// Therefore we need 68DW/16DW = 5 FIFO words to buffer 1 max size TLP +// We want to maximize the throughput while minimizing the FIFO footprint +// At the very minimum, not considering PCIe HIP backpressure, we need to be able to store 2 full max size TLPs, making depth of 10 a minimum requirement +// Considering the latency between writes and reads as well as PCIe HIP backpressure, we want to be able to store at least 5 full max size TLPs, FIFO depth 25 +// The main bottleneck in throughput becomes when we have back-to-back SOP_EOP_NOFIT packets on both channels because H-Tile bridge logic has to backpressure upstream logic +localparam FIFO_DEPTH = 5*(ofs_fim_cfg_pkg::MAX_PAYLOAD_SIZE+4)/(ofs_fim_if_pkg::FIM_PCIE_TLP_CH*AVST_WIDTH_DW); +localparam FIFO_DEPTH_LOG2 = $clog2(FIFO_DEPTH); // allocate depth of 32 +localparam logic [FIFO_DEPTH_LOG2-1:0] FIFO_FULL_DEPTH = '1; +localparam FIFO_AFULL_THRESHOLD = FIFO_FULL_DEPTH-2; + +typedef enum {CH0, CH1, CH2} e_channel; +typedef enum {OFFSET_3DW, OFFSET_4DW, OFFSET_ERR} e_offset; + +// Per-channel packet states +typedef enum logic [6:0] { + SOP, + SOP_EOP_FIT, + SOP_EOP_NOFIT, + EOP_FIT, + EOP_NOFIT, + NUL, + CTND +} t_packet_state; + +t_packet_state packet_state [1:0]; +t_packet_state packet_state_next [1:0]; + +typedef struct packed { + logic valid; + logic [AVST_DW-1:0] data; + e_offset offset; + logic [2:0] offset_eop; + logic vf_active; +} t_tx_buffer; + +t_tx_buffer [2:0] tx_buffer; + +t_avst_txs avl_tx_st_reg, avl_tx_st_reg2; +logic [2:0] avl_tx_ready_q; +logic rx_cpl_buffer_ready; +logic tlp_map_ready; +logic sop_on_ch1, generate_sop; +logic merge_axis_despite_map_not_ready; +logic [CPL_CREDIT_WIDTH-1:0] mrd_length [1:0]; // 1DW units +e_offset offset [1:0]; +logic [1:0] packet_fit_comb, packet_fit_q; + +logic [NUM_AVST_CH-1:0][127:0] avl_tx_hdr; +logic [FIM_PCIE_TLP_CH-1:0] sop; +logic [FIM_PCIE_TLP_CH-1:0] mrd; +t_tlp_mem_req_hdr [FIM_PCIE_TLP_CH-1:0] mem_req_hdr; +logic [FIM_PCIE_TLP_CH-1:0][6:0] fmttype; + +logic [9:0] tlp_hdr_len [1:0]; +logic [9:0] tlp_pyld_len [1:0]; +logic [2:0] offset_eop [1:0]; + +logic fifo_forward_pkt; +logic [FIFO_DEPTH_LOG2:0] forward_pkt_cnt; +logic forward_pkt_cnt_incr, forward_pkt_cnt_decr; + +logic fifo_wrreq, fifo_rdack; +logic fifo_full, fifo_afull, fifo_empty; +logic fifo_rvalid; +t_avst_txs fifo_din, fifo_dout; + +logic fifo_flush_wr, fifo_flush_rd; +logic fifo_flush_wr_done, fifo_flush_rd_done; +logic [FIFO_DEPTH_LOG2-1:0] fifo_flush_cnt; + +// Process two packets at the same time since there are 2 AVST channel, we may be able to send 2 TLP on the same cycle +// Allow one MRD per cycle, checker needs 1 cycle to update cpl pending counter and activate tag +// +// CPL + MRd +// MWR + MRD +// CPL + MWr (TLP size <= 256, sop&eop) +// CPL + CPL +// MWR + MWR + +// The bridge needs to make sure no idle cycle in a multi-cycle TLP, except when tx_ready is de-asserted +// (use max-payload-size supported by the platform as the reference on when to start sending the TLP stream) +// Optional : Support breaking up the payload into multiple TLP based on max-payload-size supported by the platform (negotiated with rootport) + +// Store & Forward FIFO +fim_rdack_scfifo #( + .DATA_WIDTH (PCIE_TX_AVST_IF_WIDTH*NUM_AVST_CH), + .DEPTH_LOG2 (FIFO_DEPTH_LOG2), + .USE_EAB ("ON"), + .ALMOST_FULL_THRESHOLD (FIFO_AFULL_THRESHOLD) +) tx_avst_fifo ( + .clk (avl_clk), + .sclr (~avl_rst_n), + .wdata (fifo_din), + .wreq (fifo_wrreq), + .rdack (fifo_rdack), + .rdata (fifo_dout), + .wfull (fifo_full), // not used + .wusedw (), + .rusedw (), + .almfull (fifo_afull), + .rempty (fifo_empty), // not used + .rvalid (fifo_rvalid) +); + +// Store & forward FIFO reset flush +always_ff @(posedge avl_clk) begin : FLUSH_FIFO + if (~avl_rst_n) begin + fifo_flush_wr <= 1'b1; + fifo_flush_rd <= 1'b1; + fifo_flush_wr_done <= 1'b0; + fifo_flush_rd_done <= 1'b0; + fifo_flush_cnt <= '0; + end + else begin + // Flush write + if (fifo_flush_wr_done) begin + fifo_flush_wr <= 1'b0; + end + else if (&fifo_flush_cnt) begin + fifo_flush_wr_done <= 1'b1; + end + else begin + fifo_flush_wr <= 1'b1; + fifo_flush_cnt <= fifo_flush_cnt + 1'b1; + end + // Flush read + if (fifo_flush_rd_done) begin + fifo_flush_rd <= 1'b0; + end + else if (&fifo_flush_cnt & fifo_empty) begin + fifo_flush_rd_done <= 1'b1; + end + else begin + fifo_flush_rd <= 1'b1; + end + end +end : FLUSH_FIFO + +// Store & forward FIFO write side control +always_comb begin + fifo_din = avl_tx_st_reg2; + if (NUM_AVST_CH == 1) begin + fifo_wrreq = avl_tx_st_reg2[CH0].valid | fifo_flush_wr; + end + else begin + fifo_wrreq = avl_tx_st_reg2[CH0].valid | avl_tx_st_reg2[CH1].valid | fifo_flush_wr; + end +end + +// Store & forward FIFO read side control +always_comb begin + avl_tx_st = fifo_dout; + for (int ch=0; ch 1) begin + if (mrd[CH1]) begin + // Register MRd to checker + tx_mrd_valid <= 1'b1; + tx_mrd_length <= {~(|mem_req_hdr[CH1].dw0.length), mem_req_hdr[CH1].dw0.length}; + tx_mrd_tag <= mem_req_hdr[CH1].tag[PCIE_EP_TAG_WIDTH-1:0]; + tx_mrd_pfn <= mem_req_hdr[CH1].requester_id[0+:ofs_fim_pcie_pkg::PF_WIDTH]; + tx_mrd_vfn <= mem_req_hdr[CH1].requester_id[3+:ofs_fim_pcie_pkg::VF_WIDTH]; + tx_mrd_vf_act <= axis_pcie_txs.tuser[CH1].vf_active; + end + end + end + end + + if (~avl_rst_n) begin + tx_mrd_valid <= 1'b0; + end +end + +// track cpl_pending_data_cnt and stop sending MRd request if RX buffer credit is low +localparam logic [CPL_CREDIT_WIDTH-1:0] RX_BUFFER_LIMIT = CPL_CREDIT_DWORD; // 1DW units +logic [CPL_CREDIT_WIDTH-1:0] rx_buffer_credits; +logic [CPL_CREDIT_WIDTH-1:0] last_mrd_length; +logic [1:0] enough_credits_with_txmrd, enough_credits_without_txmrd; + +always_comb begin + rx_buffer_credits = RX_BUFFER_LIMIT - cpl_pending_data_cnt; + + mrd_length[CH0][PCIE_MAX_LEN_WIDTH-1:0] = {~(|mem_req_hdr[CH0].dw0.length), mem_req_hdr[CH0].dw0.length}; + mrd_length[CH0][CPL_CREDIT_WIDTH-1:PCIE_MAX_LEN_WIDTH] = '0; + if (NUM_AVST_CH > 1) begin + mrd_length[CH1][PCIE_MAX_LEN_WIDTH-1:0] = {~(|mem_req_hdr[CH1].dw0.length), mem_req_hdr[CH1].dw0.length}; + mrd_length[CH1][CPL_CREDIT_WIDTH-1:PCIE_MAX_LEN_WIDTH] = '0; + end + + enough_credits_with_txmrd[CH0] = ((mrd_length[CH0] > rx_buffer_credits) || + (tx_mrd_length > rx_buffer_credits) || + (last_mrd_length >= rx_buffer_credits) || + (mrd_length[CH0] > rx_buffer_credits - tx_mrd_length - last_mrd_length)) ? 1'b1 : 1'b0; + enough_credits_without_txmrd[CH0] = ((mrd_length[CH0] > rx_buffer_credits) || + (last_mrd_length >= rx_buffer_credits) || + (mrd_length[CH0] > rx_buffer_credits - last_mrd_length)) ? 1'b1 : 1'b0; + if (NUM_AVST_CH > 1) begin + enough_credits_with_txmrd[CH1] = ((mrd_length[CH1] > rx_buffer_credits) || + (tx_mrd_length > rx_buffer_credits) || + (last_mrd_length >= rx_buffer_credits) || + (mrd_length[CH1] > rx_buffer_credits - tx_mrd_length - last_mrd_length)) ? 1'b1 : 1'b0; + enough_credits_without_txmrd[CH1] = ((mrd_length[CH1] > rx_buffer_credits) || + (last_mrd_length >= rx_buffer_credits) || + (mrd_length[CH1] > rx_buffer_credits - last_mrd_length)) ? 1'b1 : 1'b0; + end +end + +always_ff @(posedge avl_clk) begin + // Capture the length of the last MRd that left 1 cycle ago for back-to-back MRd requests + if (tx_mrd_valid) begin + last_mrd_length[PCIE_MAX_LEN_WIDTH-1:0] <= tx_mrd_length; + end + else begin + last_mrd_length <= '0; + end + + // Drive rx_cpl_buffer_ready high by default + rx_cpl_buffer_ready <= 1'b1; + + // We are at most 2 cycles behind the latest copy of rx_buffer_credits when we send MRd requests back-to-back + // It takes 1 cycle to generate tx_mrd_valid after rx_cpl_buffer_ready is asserted + // It takes 1 cycle to update rx_buffer_credits after tx_mrd_valid is asserted + if (axis_pcie_txs.tvalid && axis_pcie_txs_ready) begin // Normal operation mid-stream + if (mrd[CH0]) begin // MRd on channel-0 + if (tx_mrd_valid) begin // MRd in flight during this cycle so rx_buffer_credits will decrement next cycle + if (enough_credits_with_txmrd[CH0]) begin + rx_cpl_buffer_ready <= 1'b0; + end + end + else begin // No MRd in flight during this cycle but use last_mrd_length in case MRd was sent 1 cycle ago + if (enough_credits_without_txmrd[CH0]) begin + rx_cpl_buffer_ready <= 1'b0; + end + end + end + else if ((NUM_AVST_CH > 1) && mrd[CH1]) begin // MRd on channel-1 + if (tx_mrd_valid) begin // MRd in flight during this cycle so rx_buffer_credits will decrement next cycle + if (enough_credits_with_txmrd[CH1]) begin + rx_cpl_buffer_ready <= 1'b0; + end + end + else begin // No MRd in flight during this cycle but use last_mrd_length in case MRd was sent 1 cycle ago + if (enough_credits_without_txmrd[CH1]) begin + rx_cpl_buffer_ready <= 1'b0; + end + end + end + end + else if (tx_mrd_valid) begin // MRd in flight during this cycle but RX buffer credits ran out + if (mrd[CH0]) begin // MRd on channel-0 + if (enough_credits_with_txmrd[CH0]) begin + rx_cpl_buffer_ready <= 1'b0; + end + end + else if ((NUM_AVST_CH > 1) && mrd[CH1]) begin // MRd on channel-1 + if (enough_credits_with_txmrd[CH1]) begin + rx_cpl_buffer_ready <= 1'b0; + end + end + end + else if (axis_pcie_txs.tvalid) begin // Check if next TLP is a MRd after running out of RX buffer credits + if (mrd[CH0]) begin // MRd on channel-0 + if (enough_credits_without_txmrd[CH0]) begin + rx_cpl_buffer_ready <= 1'b0; + end + else begin // Capture MRd length that we allowed to pass + last_mrd_length <= mrd_length[CH0]; + end + end + else if ((NUM_AVST_CH > 1) && mrd[CH1]) begin // MRd on channel-1 + if (enough_credits_without_txmrd[CH1]) begin + rx_cpl_buffer_ready <= 1'b0; + end + else begin // Capture MRd length that we allowed to pass + last_mrd_length <= mrd_length[CH1]; + end + end + end + + if (~avl_rst_n) begin + rx_cpl_buffer_ready <= 1'b1; + end +end + +// Expression that calculates whether a TLP header and payload fit onto AVST data bus +always_comb begin + for (int ch=0; ch AVST_WIDTH_DW - tlp_hdr_len[ch]) ? 1'b0 + : 1'b1; + end +end + +// When tlp_map_ready is false, the generated AVST packet typically comes only +// from buffered state remaining from previous AXI-S state. In some cases, +// the next incoming AXI-S payload can be merged into the buffered state while +// still not overflowing a single AVST payload. Often this is a MRd that gets +// tucked in at the end of a MWr. The resulting AVST signficantly improves +// throughput when the stream is interleaved reads and writes. (When the writes +// don't fit in their original containers.) +e_channel merge_axis_ch; +always_comb begin + if (NUM_AVST_CH == 1) begin + // Not relevant with a single outbound channel + merge_axis_despite_map_not_ready = 1'b0; + end + else begin + merge_axis_despite_map_not_ready = + // Slot available at the end of AVST generated from buffer + (packet_state_next[CH1] == NUL) && + // New AXI-S state consumes only one slot + ((packet_state[CH0] == SOP_EOP_FIT) && (packet_state[CH1] == NUL) || + (packet_state[CH0] == NUL) && (packet_state[CH1] == SOP_EOP_FIT)) && + // Not in final stage of alignment to channel-0 for TLP that started on channel-1 + (tlp_map_ready || ~sop_on_ch1); + end + + // Which channel has the payload? + merge_axis_ch = (packet_state[CH0] != NUL) ? CH0 : CH1; +end + +/* +Channel packet states: + (1) SOP + (2) SOP,EOP(fit) + (3) SOP,EOP(nofit) + (4) EOP(fit) + (5) EOP(nofit) + (6) NUL + (7) --(continuing packet) +*/ +always_ff @(posedge avl_clk) begin + for (int ch=0; ch AVST_WIDTH_DW)) begin // TLP will end on CH1 + packet_fit_q[CH1] <= packet_fit_comb[ch]; + end + else begin // TLP will end on CH0 + packet_fit_q[CH0] <= packet_fit_comb[ch]; + end + end + else begin // CH1 + if ((tlp_pyld_len[ch] % (2*AVST_WIDTH_DW) == 0) || (tlp_pyld_len[ch] % (2*AVST_WIDTH_DW) > AVST_WIDTH_DW)) begin // TLP will end on CH1 + packet_fit_q[CH0] <= packet_fit_comb[ch]; + end + else begin // TLP will end on CH1 + packet_fit_q[CH1] <= packet_fit_comb[ch]; + end + end + end + end + endcase + end + end + end + if(~avl_rst_n) begin + for (int ch=0; ch SOP ??? 1 data[0] <= buff[0]; data[1] <= {???, buff[1]}; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {NUL, SOP}: + begin + buf_two_sources(CH0, axis_pcie_txs.tdata[CH1].payload, {'0, avl_tx_hdr[CH1]}, 1'b1, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + buf_one_source(CH1, axis_pcie_txs.tdata[CH1].payload, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + clear_sop_eop_valid(CH0); + clear_sop_eop_valid(CH1); + sop_on_ch1 <= 1'b1; + generate_sop <= 1'b1; + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (9) EOP(fit) NUL 1 data[0] <= {pyld[0], buff[0]}; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {EOP_FIT, NUL}: + begin + map_two_sources(CH0, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH0].data, 1'b0, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, 1'b1, tx_buffer[CH0].vf_active); + clear_buf(CH0); + set_eop(CH0); + clear_sop_eop_valid(CH1); + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (10) EOP(nofit) NUL 1 data[0] <= {pyld[0], buff[0]}; data[1] <= pyld[0]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {EOP_NOFIT, NUL}: + begin + map_two_sources(CH0, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH0].data, 1'b0, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, 1'b0, tx_buffer[CH0].vf_active); + map_one_source_msb(CH1, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, tx_buffer[CH0].vf_active); + clear_buf(CH0); + set_valid_clear_sop_eop(CH0); + set_eop(CH1); + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (11) -- EOP(fit) 1 data[0] <= {pyld[0], buff[0]}; data[1] <= {pyld[1], pyld[0]}; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {CTND, EOP_FIT}: + begin + map_two_sources(CH0, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH0].data, 1'b0, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, 1'b0, tx_buffer[CH0].vf_active); + map_two_sources(CH1, axis_pcie_txs.tdata[CH1].payload, axis_pcie_txs.tdata[CH0].payload, 1'b0, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, 1'b1, tx_buffer[CH0].vf_active); + clear_buf(CH0); + set_valid_clear_sop_eop(CH0); + set_eop(CH1); + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (12) SOP,EOP(fit) SOP,EOP(nofit) 0 data[0] <= {pyld[0], hdr[0]}; data[1] <= '0; buff[0] <= {pyld[0], hdr[0]}; buff[1] <= pyld[1]; + // -> SOP EOP(fit) 1 data[0] <= buff[0]; data[1] <= buff[1]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {SOP_EOP_FIT, SOP_EOP_NOFIT}: + begin + map_two_sources(CH0, axis_pcie_txs.tdata[CH0].payload, {'0, avl_tx_hdr[CH0]}, 1'b1, offset[CH0], offset_eop[CH0], 1'b1, axis_pcie_txs.tuser[CH0].vf_active); + buf_two_sources(CH0, axis_pcie_txs.tdata[CH1].payload, {'0, avl_tx_hdr[CH1]}, 1'b1, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + buf_one_source(CH1, axis_pcie_txs.tdata[CH1].payload, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + set_sop_eop(CH0); + clear_sop_eop_valid(CH1); + tlp_map_ready <= 1'b0; + {packet_state_next[CH0], packet_state_next[CH1]} <= {SOP, EOP_FIT}; + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (13) SOP,EOP(nofit) SOP,EOP(fit) 0 data[0] <= {pyld[0], hdr[0]}; data[1] <= pyld[0]; buff[0] <= {pyld[1], hdr[1]}; + // -> SOP,EOP(fit) NUL 1 data[0] <= buff[0]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {SOP_EOP_NOFIT, SOP_EOP_FIT}: + begin + map_two_sources(CH0, axis_pcie_txs.tdata[CH0].payload, {'0, avl_tx_hdr[CH0]}, 1'b1, offset[CH0], offset_eop[CH0], 1'b0, axis_pcie_txs.tuser[CH0].vf_active); + map_one_source_msb(CH1, axis_pcie_txs.tdata[CH0].payload, offset[CH0], offset_eop[CH0], axis_pcie_txs.tuser[CH0].vf_active); + buf_two_sources(CH0, axis_pcie_txs.tdata[CH1].payload, {'0, avl_tx_hdr[CH1]}, 1'b1, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + set_sop(CH0); + set_eop(CH1); + tlp_map_ready <= 1'b0; + {packet_state_next[CH0], packet_state_next[CH1]} <= {SOP_EOP_FIT, NUL}; + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (14) SOP,EOP(nofit) SOP,EOP(nofit) 0 data[0] <= {pyld[0], hdr[0]}; data[1] <= pyld[0]; buff[0] <= {pyld[1], hdr[1]}; buff[1] <= pyld[1]; + // -> SOP EOP(fit) 1 data[0] <= buff[0]; data[1] <= buff[1]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {SOP_EOP_NOFIT, SOP_EOP_NOFIT}: + begin + map_two_sources(CH0, axis_pcie_txs.tdata[CH0].payload, {'0, avl_tx_hdr[CH0]}, 1'b1, offset[CH0], offset_eop[CH0], 1'b0, axis_pcie_txs.tuser[CH0].vf_active); + map_one_source_msb(CH1, axis_pcie_txs.tdata[CH0].payload, offset[CH0], offset_eop[CH0], axis_pcie_txs.tuser[CH0].vf_active); + buf_two_sources(CH0, axis_pcie_txs.tdata[CH1].payload, {'0, avl_tx_hdr[CH1]}, 1'b1, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + buf_one_source(CH1, axis_pcie_txs.tdata[CH1].payload, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + set_sop(CH0); + set_eop(CH1); + tlp_map_ready <= 1'b0; + {packet_state_next[CH0], packet_state_next[CH1]} <= {SOP, EOP_FIT}; + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (15) SOP,EOP(nofit) SOP 1 data[0] <= {pyld[0], hdr[0]}; data[1] <= pyld[0]; buff[0] <= {pyld[1], hdr[1]}; buff[1] <= pyld[1]; + // -> SOP ??? 1 data[0] <= buff[0]; data[1] <= {???, buff[1]}; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {SOP_EOP_NOFIT, SOP}: + begin + map_two_sources(CH0, axis_pcie_txs.tdata[CH0].payload, {'0, avl_tx_hdr[CH0]}, 1'b1, offset[CH0], offset_eop[CH0], 1'b0, axis_pcie_txs.tuser[CH0].vf_active); + map_one_source_msb(CH1, axis_pcie_txs.tdata[CH0].payload, offset[CH0], offset_eop[CH0], axis_pcie_txs.tuser[CH0].vf_active); + buf_two_sources(CH0, axis_pcie_txs.tdata[CH1].payload, {'0, avl_tx_hdr[CH1]}, 1'b1, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + buf_one_source(CH1, axis_pcie_txs.tdata[CH1].payload, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + set_sop(CH0); + set_eop(CH1); + sop_on_ch1 <= 1'b1; + generate_sop <= 1'b1; + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (16) EOP(nofit) SOP 1 data[0] <= {pyld[0], buff[0]}; data[1] <= pyld[0]; buff[0] <= {pyld[1], hdr[1]}; buff[1] <= pyld[1]; + // -> SOP ??? 1 data[0] <= buff[0]; data[1] <= {???, buff[1]}; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {EOP_NOFIT, SOP}: + begin + map_two_sources(CH0, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH0].data, 1'b0, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, 1'b0, tx_buffer[CH0].vf_active); + map_one_source_msb(CH1, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, tx_buffer[CH0].vf_active); + buf_two_sources(CH0, axis_pcie_txs.tdata[CH1].payload, {'0, avl_tx_hdr[CH1]}, 1'b1, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + buf_one_source(CH1, axis_pcie_txs.tdata[CH1].payload, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + set_valid_clear_sop_eop(CH0); + set_eop(CH1); + sop_on_ch1 <= 1'b1; + generate_sop <= 1'b1; + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (17) EOP(nofit) SOP,EOP(fit) 0 data[0] <= {pyld[0], buff[0]}; data[1] <= pyld[0]; buff[0] <= {pyld[1], hdr[1]}; + // -> SOP,EOP(fit) NUL 1 data[0] <= buff[0]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {EOP_NOFIT, SOP_EOP_FIT}: + begin + map_two_sources(CH0, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH0].data, 1'b0, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, 1'b0, tx_buffer[CH0].vf_active); + map_one_source_msb(CH1, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, tx_buffer[CH0].vf_active); + buf_two_sources(CH0, axis_pcie_txs.tdata[CH1].payload, {'0, avl_tx_hdr[CH1]}, 1'b1, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + set_valid_clear_sop_eop(CH0); + set_eop(CH1); + tlp_map_ready <= 1'b0; + {packet_state_next[CH0], packet_state_next[CH1]} <= {SOP_EOP_FIT, NUL}; + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (18) EOP(fit) SOP,EOP(nofit) 0 data[0] <= {pyld[0], buff[0]}; data[1] <= '0; buff[0] <= {pyld[0], hdr[0]}; buff[1] <= pyld[1]; + // -> SOP EOP(fit) 1 data[0] <= buff[0]; data[1] <= buff[1]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {EOP_FIT, SOP_EOP_NOFIT}: + begin + map_two_sources(CH0, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH0].data, 1'b0, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, 1'b1, tx_buffer[CH0].vf_active); + buf_two_sources(CH0, axis_pcie_txs.tdata[CH1].payload, {'0, avl_tx_hdr[CH1]}, 1'b1, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + buf_one_source(CH1, axis_pcie_txs.tdata[CH1].payload, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + set_eop(CH0); + clear_sop_eop_valid(CH1); + tlp_map_ready <= 1'b0; + {packet_state_next[CH0], packet_state_next[CH1]} <= {SOP, EOP_FIT}; + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (19) EOP(nofit) SOP,EOP(nofit) 0 data[0] <= {pyld[0], buff[0]}; data[1] <= pyld[0]; buff[0] <= {pyld[1], hdr[1]}; buff[1] <= pyld[1]; + // -> SOP EOP(fit) 1 data[0] <= buff[0]; data[1] <= buff[1]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {EOP_NOFIT, SOP_EOP_NOFIT}: + begin + map_two_sources(CH0, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH0].data, 1'b0, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, 1'b0, tx_buffer[CH0].vf_active); + map_one_source_msb(CH1, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, tx_buffer[CH0].vf_active); + buf_two_sources(CH0, axis_pcie_txs.tdata[CH1].payload, {'0, avl_tx_hdr[CH1]}, 1'b1, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + buf_one_source(CH1, axis_pcie_txs.tdata[CH1].payload, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + set_valid_clear_sop_eop(CH0); + set_eop(CH1); + tlp_map_ready <= 1'b0; + {packet_state_next[CH0], packet_state_next[CH1]} <= {SOP, EOP_FIT}; + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (20) SOP EOP(nofit) 0 data[0] <= {pyld[0], hdr[0]}; data[1] <= pyld[1]; buff[0] <= pyld[1]; + // -> EOP(fit) NUL 1 data[0] <= buff[0]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {SOP, EOP_NOFIT}: + begin + map_two_sources(CH0, axis_pcie_txs.tdata[CH0].payload, {'0, avl_tx_hdr[CH0]}, 1'b1, offset[CH0], offset_eop[CH0], 1'b0, axis_pcie_txs.tuser[CH0].vf_active); + map_two_sources(CH1, axis_pcie_txs.tdata[CH1].payload, axis_pcie_txs.tdata[CH0].payload, 1'b0, offset[CH0], offset_eop[CH0], 1'b0, axis_pcie_txs.tuser[CH0].vf_active); + buf_one_source(CH0, axis_pcie_txs.tdata[CH1].payload, offset[CH0], offset_eop[CH0], axis_pcie_txs.tuser[CH0].vf_active); + set_sop(CH0); + set_valid_clear_sop_eop(CH1); + tlp_map_ready <= 1'b0; + {packet_state_next[CH0], packet_state_next[CH1]} <= {EOP_FIT, NUL}; + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (21) -- EOP(nofit) 0 data[0] <= {pyld[0], buff[0]}; data[1] <= {pyld[1], pyld[0]}; buff[0] <= pyld[1]; + // -> EOP(fit) NULL 1 data[0] <= buff[0]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {CTND, EOP_NOFIT}: + begin + map_two_sources(CH0, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH0].data, 1'b0, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, 1'b0, tx_buffer[CH0].vf_active); + map_two_sources(CH1, axis_pcie_txs.tdata[CH1].payload, axis_pcie_txs.tdata[CH0].payload, 1'b0, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, 1'b0, tx_buffer[CH0].vf_active); + buf_one_source(CH0, axis_pcie_txs.tdata[CH1].payload, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, tx_buffer[CH0].vf_active); + set_valid_clear_sop_eop(CH0); + set_valid_clear_sop_eop(CH1); + tlp_map_ready <= 1'b0; + {packet_state_next[CH0], packet_state_next[CH1]} <= {EOP_FIT, NUL}; + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (22) SOP,EOP(fit) SOP 1 data[0] <= {pyld[0], hdr[0]}; data[1] <= {pyld[1], hdr[1]}; buff[0] <= pyld[1]; + // -> --(append more) ??? 1 data[0] <= {???, buff[0]}; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {SOP_EOP_FIT, SOP}: + begin + map_two_sources(CH0, axis_pcie_txs.tdata[CH0].payload, {'0, avl_tx_hdr[CH0]}, 1'b1, offset[CH0], offset_eop[CH0], 1'b1, axis_pcie_txs.tuser[CH0].vf_active); + map_two_sources(CH1, axis_pcie_txs.tdata[CH1].payload, {'0, avl_tx_hdr[CH1]}, 1'b1, offset[CH1], offset_eop[CH1], 1'b0, axis_pcie_txs.tuser[CH1].vf_active); + buf_one_source(CH0, axis_pcie_txs.tdata[CH1].payload, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + set_sop_eop(CH0); + set_sop(CH1); + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (23) SOP -- 1 data[0] <= {pyld[0], hdr[0]}; data[1] <= {pyld[1], pyld[0]}; buff[0] <= pyld[1]; continue appending buffer... + // -> --(append more) ??? 1 data[0] <= {???, buff[0]}; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {SOP, CTND}: + begin + map_two_sources(CH0, axis_pcie_txs.tdata[CH0].payload, {'0, avl_tx_hdr[CH0]}, 1'b1, offset[CH0], offset_eop[CH0], 1'b0, axis_pcie_txs.tuser[CH0].vf_active); + map_two_sources(CH1, axis_pcie_txs.tdata[CH1].payload, axis_pcie_txs.tdata[CH0].payload, 1'b0, offset[CH0], offset_eop[CH0], 1'b0, axis_pcie_txs.tuser[CH0].vf_active); + buf_one_source(CH0, axis_pcie_txs.tdata[CH1].payload, offset[CH0], offset_eop[CH0], axis_pcie_txs.tuser[CH0].vf_active); + set_sop(CH0); + set_valid_clear_sop_eop(CH1); + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (24) EOP(fit) SOP 1 data[0] <= {pyld[0], buff[0]}; data[1] <= {pyld[1], hdr[1]}; buff[0] <= pyld[1]; + // -> --(append more) ??? 1 data[0] <= {???, buff[0]}; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {EOP_FIT, SOP}: + begin + map_two_sources(CH0, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH0].data, 1'b0, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, 1'b1, tx_buffer[CH0].vf_active); + map_two_sources(CH1, axis_pcie_txs.tdata[CH1].payload, {'0, avl_tx_hdr[CH1]}, 1'b1, offset[CH1], offset_eop[CH1], 1'b0, axis_pcie_txs.tuser[CH1].vf_active); + buf_one_source(CH0, axis_pcie_txs.tdata[CH1].payload, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + set_eop(CH0); + set_sop(CH1); + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (25) -- -- 1 data[0] <= {pyld[0], buff[0]}; data[1] <= {pyld[1], pyld[0]}; buff[0] <= pyld[1]; + // -> --(append more) ??? 1 data[0] <= {???, buff[0]}; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {CTND, CTND}: + begin + map_two_sources(CH0, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH0].data, 1'b0, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, 1'b0, tx_buffer[CH0].vf_active); + map_two_sources(CH1, axis_pcie_txs.tdata[CH1].payload, axis_pcie_txs.tdata[CH0].payload, 1'b0, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, 1'b0, tx_buffer[CH0].vf_active); + buf_one_source(CH0, axis_pcie_txs.tdata[CH1].payload, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, tx_buffer[CH0].vf_active); + set_valid_clear_sop_eop(CH0); + set_valid_clear_sop_eop(CH1); + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (26) NUL NUL 1 data[0] <= '0; data[1] <= '0; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + default: + begin + // do nothing + end + endcase + end + else if (~fifo_afull && ~tlp_map_ready && ~sop_on_ch1) begin // Finish mapping buffered AXIS payload onto AVST data bus + for (int ch=0; ch(27) EOP(fit) NUL 1 data[0] <= buff[0]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {EOP_FIT, NUL}: + begin + map_one_source_msb(CH0, tx_buffer[CH0].data, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, tx_buffer[CH0].vf_active); + clear_buf(CH0); + set_eop(CH0); + // The incoming AXI-S might be data ready despite tlp_map_ready being false. + // See merge_axis_despite_map_not_ready above. + if (~axis_pcie_txs_ready) begin + clear_sop_eop_valid(CH1); + end + else begin + map_two_sources(CH1, axis_pcie_txs.tdata[merge_axis_ch].payload, {'0, avl_tx_hdr[merge_axis_ch]}, 1'b1, offset[merge_axis_ch], offset_eop[merge_axis_ch], 1'b1, axis_pcie_txs.tuser[merge_axis_ch].vf_active); + set_sop_eop(CH1); + end + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (13) SOP,EOP(nofit) SOP,EOP(fit) 0 data[0] <= {pyld[0], hdr[0]}; data[1] <= pyld[0]; buff[0] <= {pyld[1], hdr[1]}; + // (17) EOP(nofit) SOP,EOP(fit) 0 data[0] <= {pyld[0], buff[0]}; data[1] <= pyld[0]; buff[0] <= {pyld[1], hdr[1]}; + //->(28)SOP,EOP(fit) NUL 1 data[0] <= buff[0]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {SOP_EOP_FIT, NUL}: + begin + map_one_source_msb(CH0, tx_buffer[CH0].data, tx_buffer[CH0].offset, '0, tx_buffer[CH0].vf_active); // map entire payload + clear_buf(CH0); + set_sop_eop(CH0); + // The incoming AXI-S might be data ready despite tlp_map_ready being false. + // See merge_axis_despite_map_not_ready above. + if (~axis_pcie_txs_ready) begin + clear_sop_eop_valid(CH1); + end + else begin + map_two_sources(CH1, axis_pcie_txs.tdata[merge_axis_ch].payload, {'0, avl_tx_hdr[merge_axis_ch]}, 1'b1, offset[merge_axis_ch], offset_eop[merge_axis_ch], 1'b1, axis_pcie_txs.tuser[merge_axis_ch].vf_active); + set_sop_eop(CH1); + end + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (12) SOP,EOP(fit) SOP,EOP(nofit) 0 data[0] <= {pyld[0], hdr[0]}; data[1] <= '0; buff[0] <= {pyld[0], hdr[0]}; buff[1] <= pyld[1]; + // (14) SOP,EOP(nofit) SOP,EOP(nofit) 0 data[0] <= {pyld[0], hdr[0]}; data[1] <= pyld[0]; buff[0] <= {pyld[1], hdr[1]}; buff[1] <= pyld[1]; + // (19) EOP(nofit) SOP,EOP(nofit) 0 data[0] <= {pyld[0], buff[0]}; data[1] <= pyld[0]; buff[0] <= {pyld[1], hdr[1]}; buff[1] <= pyld[1]; + //->(29) SOP EOP(fit) 1 data[0] <= buff[0]; data[1] <= buff[1]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {SOP, EOP_FIT}: + begin + map_one_source_msb(CH0, tx_buffer[CH0].data, tx_buffer[CH0].offset, '0, tx_buffer[CH0].vf_active); // map entire payload + map_one_source_msb(CH1, tx_buffer[CH1].data, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, tx_buffer[CH1].vf_active); + clear_buf(CH0); + clear_buf(CH1); + set_sop(CH0); + set_eop(CH1); + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + //->(30) + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + default: + begin + // do nothing + end + endcase + end + else if (axis_pcie_txs.tvalid && axis_pcie_txs_ready && sop_on_ch1) begin // Align SOP to channel-0 + for (int ch=0; ch SOP/-- EOP(fit) + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {EOP_FIT, NUL}: + begin + map_one_source_msb(CH0, tx_buffer[CH0].data, tx_buffer[CH0].offset, '0, tx_buffer[CH0].vf_active); // map entire payload + map_two_sources(CH1, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH1].data, 1'b0, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, 1'b1, tx_buffer[CH1].vf_active); + clear_buf(CH0); + clear_buf(CH1); + if (generate_sop) + set_sop(CH0); + else + set_valid_clear_sop_eop(CH0); + set_eop(CH1); + tlp_map_ready <= 1'b1; + sop_on_ch1 <= 1'b0; + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (32) EOP(nofit) NUL 0 data[0] <= buff[0]; data[1] <= {pyld[0], buff[1]}; buff[0] <= pyld[0]; buff[1] <= '0; + // -> SOP/-- -- + // -> EOP(fit) NUL 1 data[0] <= buff[0]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {EOP_NOFIT, NUL}: + begin + map_one_source_msb(CH0, tx_buffer[CH0].data, tx_buffer[CH0].offset, '0, tx_buffer[CH0].vf_active); // map entire payload + map_two_sources(CH1, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH1].data, 1'b0, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, 1'b0, tx_buffer[CH1].vf_active); + buf_one_source(CH0, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, tx_buffer[CH1].vf_active); + clear_buf(CH1); + if (generate_sop) + set_sop(CH0); + else + set_valid_clear_sop_eop(CH0); + set_valid_clear_sop_eop(CH1); + {packet_state_next[CH0], packet_state_next[CH1]} <= {EOP_FIT, NUL}; + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (33) EOP(fit) SOP,EOP(fit) 0 data[0] <= buff[0]; data[1] <= {pyld[0], buff[1]}; buff[0] <= {pyld[1], hdr[1]}; buff[1] <= '0; + // -> SOP/-- EOP(fit) + // -> SOP,EOP(fit) NUL 1 data[0] <= buff[0]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {EOP_FIT, SOP_EOP_FIT}: + begin + map_one_source_msb(CH0, tx_buffer[CH0].data, tx_buffer[CH0].offset, '0, tx_buffer[CH0].vf_active); // map entire payload + map_two_sources(CH1, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH1].data, 1'b0, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, 1'b1, tx_buffer[CH1].vf_active); + buf_two_sources(CH0, axis_pcie_txs.tdata[CH1].payload, {'0, avl_tx_hdr[CH1]}, 1'b1, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + clear_buf(CH1); + if (generate_sop) + set_sop(CH0); + else + set_valid_clear_sop_eop(CH0); + set_eop(CH1); + {packet_state_next[CH0], packet_state_next[CH1]} <= {SOP_EOP_FIT, NUL}; + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (34) EOP(nofit) SOP,EOP(fit) 0 data[0] <= buff[0]; data[1] <= {pyld[0], buff[1]}; buff[0] <= pyld[0]; buff[1] <= {pyld[1], hdr[1]}; + // -> SOP/-- -- + // -> EOP(fit) SOP,EOP(fit) 1 data[0] <= buff[0]; data[1] <= buff[1]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {EOP_NOFIT, SOP_EOP_FIT}: + begin + map_one_source_msb(CH0, tx_buffer[CH0].data, tx_buffer[CH0].offset, '0, tx_buffer[CH0].vf_active); // map entire payload + map_two_sources(CH1, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH1].data, 1'b0, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, 1'b0, tx_buffer[CH1].vf_active); + buf_one_source(CH0, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, tx_buffer[CH1].vf_active); + buf_two_sources(CH1, axis_pcie_txs.tdata[CH1].payload, {'0, avl_tx_hdr[CH1]}, 1'b1, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + if (generate_sop) + set_sop(CH0); + else + set_valid_clear_sop_eop(CH0); + set_valid_clear_sop_eop(CH1); + {packet_state_next[CH0], packet_state_next[CH1]} <= {EOP_FIT, SOP_EOP_FIT}; + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (35) EOP(fit) SOP,EOP(nofit) 0 data[0] <= buff[0]; data[1] <= {pyld[0], buff[1]}; buff[0] <= {pyld[1], hdr[1]}; buff[1] <= pyld[1]; + // -> SOP/-- EOP(fit) + // -> SOP EOP(fit) 1 data[0] <= buff[0]; data[1] <= buff[1]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {EOP_FIT, SOP_EOP_NOFIT}: + begin + map_one_source_msb(CH0, tx_buffer[CH0].data, tx_buffer[CH0].offset, '0, tx_buffer[CH0].vf_active); // map entire payload + map_two_sources(CH1, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH1].data, 1'b0, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, 1'b1, tx_buffer[CH1].vf_active); + buf_two_sources(CH0, axis_pcie_txs.tdata[CH1].payload, {'0, avl_tx_hdr[CH1]}, 1'b1, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + buf_one_source(CH1, axis_pcie_txs.tdata[CH1].payload, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + if (generate_sop) + set_sop(CH0); + else + set_valid_clear_sop_eop(CH0); + set_eop(CH1); + {packet_state_next[CH0], packet_state_next[CH1]} <= {SOP, EOP_FIT}; + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (36) EOP(nofit) SOP,EOP(nofit) 0 data[0] <= buff[0]; data[1] <= {pyld[0], buff[1]}; buff[0] <= pyld[0]; buff[1] <= {pyld[1], hdr[1]}; buff[2] <= pyld[1]; + // -> SOP/-- -- + // -> EOP(fit) SOP 0 data[0] <= buff[0]; data[1] <= buff[1]; buff[0] <= buff[2]; buff[1] <= '0; + // -> EOP(fit) NUL 1 data[0] <= buff[0]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {EOP_NOFIT, SOP_EOP_NOFIT}: + begin + map_one_source_msb(CH0, tx_buffer[CH0].data, tx_buffer[CH0].offset, '0, tx_buffer[CH0].vf_active); // map entire payload + map_two_sources(CH1, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH1].data, 1'b0, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, 1'b0, tx_buffer[CH1].vf_active); + buf_one_source(CH0, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, tx_buffer[CH1].vf_active); + buf_two_sources(CH1, axis_pcie_txs.tdata[CH1].payload, {'0, avl_tx_hdr[CH1]}, 1'b1, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + buf_one_source(CH2, axis_pcie_txs.tdata[CH1].payload, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); // use extra buffer for this corner case + if (generate_sop) + set_sop(CH0); + else + set_valid_clear_sop_eop(CH0); + set_valid_clear_sop_eop(CH1); + {packet_state_next[CH0], packet_state_next[CH1]} <= {EOP_FIT, SOP}; + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (37) -- -- 1 data[0] <= buff[0]; data[1] <= {pyld[0], buff[1]}; buff[0] <= {pyld[1], pyld[0]};buff[1] <= pyld[1]; + // -> SOP/-- -- + // -> -- ??? 1 data[0] <= buff[0]; data[1] <= {???, buff[1]}; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {CTND, CTND}: + begin + map_one_source_msb(CH0, tx_buffer[CH0].data, tx_buffer[CH0].offset, '0, tx_buffer[CH0].vf_active); // map entire payload + map_two_sources(CH1, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH1].data, 1'b0, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, 1'b0, tx_buffer[CH1].vf_active); + buf_two_sources(CH0, axis_pcie_txs.tdata[CH1].payload, axis_pcie_txs.tdata[CH0].payload, 1'b0, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, tx_buffer[CH1].vf_active); + buf_one_source(CH1, axis_pcie_txs.tdata[CH1].payload, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, tx_buffer[CH1].vf_active); + if (generate_sop) + set_sop(CH0); + else + set_valid_clear_sop_eop(CH0); + set_valid_clear_sop_eop(CH1); + tlp_map_ready <= 1'b1; + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (38) -- EOP(fit) 0 data[0] <= buff[0]; data[1] <= {pyld[0], buff[1]}; buff[0] <= {pyld[1], pyld[0]};buff[1] <= '0; + // -> SOP/-- -- + // -> EOP(fit) NUL 1 data[0] <= buff[0]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {CTND, EOP_FIT}: + begin + map_one_source_msb(CH0, tx_buffer[CH0].data, tx_buffer[CH0].offset, '0, tx_buffer[CH0].vf_active); // map entire payload + map_two_sources(CH1, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH1].data, 1'b0, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, 1'b0, tx_buffer[CH1].vf_active); + buf_two_sources(CH0, axis_pcie_txs.tdata[CH1].payload, axis_pcie_txs.tdata[CH0].payload, 1'b0, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, tx_buffer[CH1].vf_active); + clear_buf(CH1); + if (generate_sop) + set_sop(CH0); + else + set_valid_clear_sop_eop(CH0); + set_valid_clear_sop_eop(CH1); + {packet_state_next[CH0], packet_state_next[CH1]} <= {EOP_FIT, NUL}; + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (39) -- EOP(nofit) 0 data[0] <= buff[0]; data[1] <= {pyld[0], buff[1]}; buff[0] <= {pyld[1], pyld[0]};buff[1] <= pyld[1]; + // -> SOP/-- -- + // -> -- EOP(fit) 1 data[0] <= buff[0]; data[1] <= buff[1]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {CTND, EOP_NOFIT}: + begin + map_one_source_msb(CH0, tx_buffer[CH0].data, tx_buffer[CH0].offset, '0, tx_buffer[CH0].vf_active); // map entire payload + map_two_sources(CH1, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH1].data, 1'b0, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, 1'b0, tx_buffer[CH1].vf_active); + buf_two_sources(CH0, axis_pcie_txs.tdata[CH1].payload, axis_pcie_txs.tdata[CH0].payload, 1'b0, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, tx_buffer[CH1].vf_active); + buf_one_source(CH1, axis_pcie_txs.tdata[CH1].payload, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, tx_buffer[CH1].vf_active); + if (generate_sop) + set_sop(CH0); + else + set_valid_clear_sop_eop(CH0); + set_valid_clear_sop_eop(CH1); + {packet_state_next[CH0], packet_state_next[CH1]} <= {CTND, EOP_FIT}; + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (40) EOP(fit) SOP 1 data[0] <= buff[0]; data[1] <= {pyld[0], buff[1]}; buff[0] <= {pyld[1], hdr[1]}; buff[1] <= pyld[1]; + // -> SOP/-- EOP(fit) 1 + // -> SOP ??? 1 data[0] <= buff[0]; data[1] <= {???, buff[1]}; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {EOP_FIT, SOP}: + begin + map_one_source_msb(CH0, tx_buffer[CH0].data, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, tx_buffer[CH0].vf_active); + map_two_sources(CH1, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH1].data, 1'b0, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, 1'b1, tx_buffer[CH1].vf_active); + buf_two_sources(CH0, axis_pcie_txs.tdata[CH1].payload, {'0, avl_tx_hdr[CH1]}, 1'b1, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + buf_one_source(CH1, axis_pcie_txs.tdata[CH1].payload, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + if (generate_sop) + set_sop(CH0); + else + set_valid_clear_sop_eop(CH0); + set_eop(CH1); + tlp_map_ready <= 1'b1; + generate_sop <= 1'b1; + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (41) EOP(nofit) SOP 0 data[0] <= buff[0]; data[1] <= {pyld[0], buff[1]}; buff[0] <= pyld[0]; buff[1] <= {pyld[1], hdr[1]}; buff[2] <= pyld[1]; + // -> SOP/-- -- + // -> EOP(fit) SOP 1 data[0] <= buff[0]; data[1] <= buff[1]; buff[0] <= buff[2]; + // -> --(append more) ??? 1 data[0] <= {???, buff[0]}; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {EOP_NOFIT, SOP}: + begin + map_one_source_msb(CH0, tx_buffer[CH0].data, tx_buffer[CH0].offset, '0, tx_buffer[CH0].vf_active); // map entire payload + map_two_sources(CH1, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH1].data, 1'b0, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, 1'b0, tx_buffer[CH1].vf_active); + buf_one_source(CH0, axis_pcie_txs.tdata[CH0].payload, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, tx_buffer[CH1].vf_active); + buf_two_sources(CH1, axis_pcie_txs.tdata[CH1].payload, {'0, avl_tx_hdr[CH1]}, 1'b1, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); + buf_one_source(CH2, axis_pcie_txs.tdata[CH1].payload, offset[CH1], offset_eop[CH1], axis_pcie_txs.tuser[CH1].vf_active); // use extra buffer for this corner case + if (generate_sop) + set_sop(CH0); + else + set_valid_clear_sop_eop(CH0); + set_valid_clear_sop_eop(CH1); + generate_sop <= 1'b1; + {packet_state_next[CH0], packet_state_next[CH1]} <= {EOP_FIT, SOP}; + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + //->(42) + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + default: + begin + tlp_map_ready <= 1'b1; + sop_on_ch1 <= 1'b0; + end + endcase + end + else if (~fifo_afull && ~tlp_map_ready && sop_on_ch1) begin + for (int ch=0; ch(43) EOP(fit) SOP 0 data[0] <= buff[0]; data[1] <= buff[1]; buff[0] <= buff[2]; buff[1] <= '0; + // -> EOP(fit) NUL 1 data[0] <= buff[0]; + // OR(41) EOP(nofit) SOP 0 data[0] <= buff[0]; data[1] <= {pyld[0], buff[1]}; buff[0] <= pyld[0]; buff[1] <= {pyld[1], hdr[1]}; buff[2] <= pyld[1]; + //->(43) EOP(fit) SOP 0 data[0] <= buff[0]; data[1] <= buff[1]; buff[0] <= buff[2]; buff[1] <= '0; + // -> --(append more) ??? 1 data[0] <= {???, buff[0]}; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {EOP_FIT, SOP}: + begin + map_one_source_msb(CH0, tx_buffer[CH0].data, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, tx_buffer[CH0].vf_active); + map_one_source_msb(CH1, tx_buffer[CH1].data, tx_buffer[CH1].offset, '0, tx_buffer[CH1].vf_active); // map entire payload + tx_buffer[CH0] <= tx_buffer[CH2]; // shift extra buffer into CH0 + clear_buf(CH1); + clear_buf(CH2); + set_eop(CH0); + set_sop(CH1); + if (generate_sop) begin + {packet_state_next[CH0], packet_state_next[CH1]} <= {NUL, NUL}; + end + else begin + tlp_map_ready <= 1'b0; + sop_on_ch1 <= 1'b1; + {packet_state_next[CH0], packet_state_next[CH1]} <= {EOP_FIT, NUL}; + end + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (32) EOP(nofit) NUL 0 data[0] <= buff[0]; data[1] <= {pyld[0], buff[1]}; buff[0] <= pyld[0]; buff[1] <= '0; + // (38) -- EOP(fit) 0 data[0] <= buff[0]; data[1] <= {pyld[0], buff[1]}; buff[0] <= {pyld[1], pyld[0]};buff[1] <= '0; + // (43) EOP(fit) SOP 0 data[0] <= buff[0]; data[1] <= buff[1]; buff[0] <= buff[2]; buff[1] <= '0; + //->(44) EOP(fit) NUL 1 data[0] <= buff[0]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {EOP_FIT, NUL}: + begin + map_one_source_msb(CH0, tx_buffer[CH0].data, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, tx_buffer[CH0].vf_active); + clear_buf(CH0); + set_eop(CH0); + clear_sop_eop_valid(CH1); + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (33) EOP(fit) SOP,EOP(fit) 0 data[0] <= buff[0]; data[1] <= {pyld[0], buff[1]}; buff[0] <= {pyld[1], hdr[1]}; buff[1] <= '0; + //->(45)SOP,EOP(fit) NUL 1 data[0] <= buff[0]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {SOP_EOP_FIT, NUL}: + begin + map_one_source_msb(CH0, tx_buffer[CH0].data, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, tx_buffer[CH0].vf_active); + clear_buf(CH0); + set_sop_eop(CH0); + clear_sop_eop_valid(CH1); + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (34) EOP(nofit) SOP,EOP(fit) 0 data[0] <= buff[0]; data[1] <= {pyld[0], buff[1]}; buff[0] <= pyld[0]; buff[1] <= {pyld[1], hdr[1]}; + //->(46) EOP(fit) SOP,EOP(fit) 1 data[0] <= buff[0]; data[1] <= buff[1]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {EOP_FIT, SOP_EOP_FIT}: + begin + map_one_source_msb(CH0, tx_buffer[CH0].data, tx_buffer[CH0].offset, tx_buffer[CH0].offset_eop, tx_buffer[CH0].vf_active); + map_one_source_msb(CH1, tx_buffer[CH1].data, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, tx_buffer[CH1].vf_active); + clear_buf(CH0); + clear_buf(CH1); + set_eop(CH0); + set_sop_eop(CH1); + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (35) EOP(fit) SOP,EOP(nofit) 0 data[0] <= buff[0]; data[1] <= {pyld[0], buff[1]}; buff[0] <= {pyld[1], hdr[1]}; buff[1] <= pyld[1]; + //->(47) SOP EOP(fit) 1 data[0] <= buff[0]; data[1] <= buff[1]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {SOP, EOP_FIT}: + begin + map_one_source_msb(CH0, tx_buffer[CH0].data, tx_buffer[CH0].offset, '0, tx_buffer[CH0].vf_active); // map entire payload + map_one_source_msb(CH1, tx_buffer[CH1].data, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, tx_buffer[CH1].vf_active); + clear_buf(CH0); + clear_buf(CH1); + set_sop(CH0); + set_eop(CH1); + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + // CH0 CH1 TREADY MAP + // (39) -- EOP(nofit) 0 data[0] <= buff[0]; data[1] <= {pyld[0], buff[1]}; buff[0] <= {pyld[1], pyld[0]};buff[1] <= pyld[1]; + //->(48) -- EOP(fit) 1 data[0] <= buff[0]; data[1] <= buff[1]; + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + {CTND, EOP_FIT}: + begin + map_one_source_msb(CH0, tx_buffer[CH0].data, tx_buffer[CH0].offset, '0, tx_buffer[CH0].vf_active); // map entire payload + map_one_source_msb(CH1, tx_buffer[CH1].data, tx_buffer[CH1].offset, tx_buffer[CH1].offset_eop, tx_buffer[CH1].vf_active); + clear_buf(CH0); + clear_buf(CH1); + set_valid_clear_sop_eop(CH0); + set_eop(CH1); + end + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + //->(49) + // ----------------------------------------------------------------------------------------------------------------------------------------------------- + default: + begin + // do nothing + end + endcase + end + end + + if (~avl_rst_n) begin + for (int ch=0; ch ##1 (forward_pkt_cnt > 0)) ) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, forward packet counter overflow", $time)); + + assert_forward_pkt_cnt_underflow : + assert property ( @(posedge avl_clk) disable iff (~avl_rst_n) ((forward_pkt_cnt == 0) |-> ##1 ~&forward_pkt_cnt) ) + else $fatal(0,$psprintf("%8t: %m ASSERTION_ERROR, forward packet counter underflow", $time)); +// synthesis translate_on + +//------------------------------------------- +// Tasks and Functions +//------------------------------------------- +// Reverse the DW from big endian to little endian +function automatic logic [127:0] func_to_little_endian_hdr ( + input logic [127:0] hdr +); + for (int i=0; i<=3; i=i+1) begin + func_to_little_endian_hdr[i*32+:32] = hdr[(3-i)*32+:32]; + end +endfunction + +/* Pack LSB of source0 with MSB of source1 to target data bus delimited by offset + map_two_sources(target, source0, source1, hdr_valid, offset) + - in the case of passing two same-width sources + -- map_two_sources(target=0/1, source0[256], source1[256], hdr_valid=0, offset=3DW/4DW) + - in the case of passing header with a source + -- map_two_sources(target=0/1, source0[256], {'0, hdr[128]}, hdr_valid=1, offset=3DW/4DW) +*/ +task map_two_sources; + input e_channel i_target; + input logic [AVST_DW-1:0] i_source0; + input logic [AVST_DW-1:0] i_source1; + input logic i_hdr_valid; + input e_offset i_offset; + input logic [2:0] i_offset_eop; + input logic i_eop; + input logic i_vf_active; +begin + case (i_offset) + OFFSET_3DW: + begin + if (i_hdr_valid) begin + avl_tx_st_reg[i_target].data <= {i_source0[SOP_3DW_DWORD_LEN*32-1:0], i_source1[HDR_3DW_LEN*32-1:0]}; + end + else begin + avl_tx_st_reg[i_target].data <= {i_source0[SOP_3DW_DWORD_LEN*32-1:0], i_source1[NON_SOP_DWORD_LEN*32-1:SOP_3DW_DWORD_LEN*32]}; + end + end + default: // OFFSET_4DW + begin + if (i_hdr_valid) begin + avl_tx_st_reg[i_target].data <= {i_source0[SOP_4DW_DWORD_LEN*32-1:0], i_source1[HDR_4DW_LEN*32-1:0]}; + end + else begin + avl_tx_st_reg[i_target].data <= {i_source0[SOP_4DW_DWORD_LEN*32-1:0], i_source1[NON_SOP_DWORD_LEN*32-1:SOP_4DW_DWORD_LEN*32]}; + end + end + endcase + avl_tx_st_reg[i_target].vf_active <= i_vf_active; + `ifdef SIM_MODE + if (i_eop) begin + case (i_offset_eop) + 3'h7: + begin + avl_tx_st_reg[i_target].data[NON_SOP_DWORD_LEN*32-1:7*32] <= '0; + end + 3'h6: + begin + avl_tx_st_reg[i_target].data[NON_SOP_DWORD_LEN*32-1:6*32] <= '0; + end + 3'h5: + begin + avl_tx_st_reg[i_target].data[NON_SOP_DWORD_LEN*32-1:5*32] <= '0; + end + 3'h4: + begin + avl_tx_st_reg[i_target].data[NON_SOP_DWORD_LEN*32-1:4*32] <= '0; + end + 3'h3: + begin + avl_tx_st_reg[i_target].data[NON_SOP_DWORD_LEN*32-1:3*32] <= '0; + end + 3'h2: + begin + avl_tx_st_reg[i_target].data[NON_SOP_DWORD_LEN*32-1:2*32] <= '0; + end + 3'h1: + begin + avl_tx_st_reg[i_target].data[NON_SOP_DWORD_LEN*32-1:1*32] <= '0; + end + default: + begin + // do nothing + end + endcase + end + `endif +end +endtask : map_two_sources + +// Pack MSB of source delimited by offset to LSB of target data bus +task map_one_source_msb; + input e_channel i_target; + input logic [AVST_DW-1:0] i_source; + input e_offset i_offset; + input logic [2:0] i_offset_eop; + input logic i_vf_active; +begin + avl_tx_st_reg[i_target].data <= '0; + if (i_offset == OFFSET_3DW) begin + case (i_offset_eop) + 3'h3: + begin + avl_tx_st_reg[i_target].data[3*32-1:0] <= i_source[(NON_SOP_DWORD_LEN-HDR_3DW_LEN+3)*32-1:(NON_SOP_DWORD_LEN-HDR_3DW_LEN)*32]; + end + 3'h2: + begin + avl_tx_st_reg[i_target].data[2*32-1:0] <= i_source[(NON_SOP_DWORD_LEN-HDR_3DW_LEN+2)*32-1:(NON_SOP_DWORD_LEN-HDR_3DW_LEN)*32]; + end + 3'h1: + begin + avl_tx_st_reg[i_target].data[1*32-1:0] <= i_source[(NON_SOP_DWORD_LEN-HDR_3DW_LEN+1)*32-1:(NON_SOP_DWORD_LEN-HDR_3DW_LEN)*32]; + end + default: + begin + avl_tx_st_reg[i_target].data <= i_source; + end + endcase + end + else begin // OFFSET_4DW + case (i_offset_eop) + 3'h4: + begin + avl_tx_st_reg[i_target].data[4*32-1:0] <= i_source[(NON_SOP_DWORD_LEN-HDR_4DW_LEN+4)*32-1:(NON_SOP_DWORD_LEN-HDR_4DW_LEN)*32]; + end + 3'h3: + begin + avl_tx_st_reg[i_target].data[3*32-1:0] <= i_source[(NON_SOP_DWORD_LEN-HDR_4DW_LEN+3)*32-1:(NON_SOP_DWORD_LEN-HDR_4DW_LEN)*32]; + end + 3'h2: + begin + avl_tx_st_reg[i_target].data[2*32-1:0] <= i_source[(NON_SOP_DWORD_LEN-HDR_4DW_LEN+2)*32-1:(NON_SOP_DWORD_LEN-HDR_4DW_LEN)*32]; + end + 3'h1: + begin + avl_tx_st_reg[i_target].data[1*32-1:0] <= i_source[(NON_SOP_DWORD_LEN-HDR_4DW_LEN+1)*32-1:(NON_SOP_DWORD_LEN-HDR_4DW_LEN)*32]; + end + default: + begin + avl_tx_st_reg[i_target].data <= i_source; + end + endcase + end + avl_tx_st_reg[i_target].vf_active <= i_vf_active; +end +endtask : map_one_source_msb + +/* Buffer LSB of source0 with MSB of source1 to target buffer delimited by offset + buf_two_sources(target, source0, source1, hdr_valid, offset) + - in the case of passing two same width sources + -- buf_two_sources(target=0/1, source0[256], source1[256], hdr_valid=0, offset=3DW/4DW) + - in the case of passing header with a source + -- buf_two_sources(target=0/1, source0[256], {'0, hdr[128]}, hdr_valid=1, offset=3DW/4DW) +*/ +task buf_two_sources; + input e_channel i_target; + input logic [AVST_DW-1:0] i_source0; + input logic [AVST_DW-1:0] i_source1; + input logic i_hdr_valid; + input e_offset i_offset; + input logic [2:0] i_offset_eop; + input logic i_vf_active; +begin + case (i_offset) + OFFSET_3DW: + begin + if (i_hdr_valid) begin + tx_buffer[i_target].data <= {i_source0[SOP_3DW_DWORD_LEN*32-1:0], i_source1[HDR_3DW_LEN*32-1:0]}; + end + else begin + tx_buffer[i_target].data <= {i_source0[SOP_3DW_DWORD_LEN*32-1:0], i_source1[NON_SOP_DWORD_LEN*32-1:SOP_3DW_DWORD_LEN*32]}; + end + end + default: // OFFSET_4DW + begin + if (i_hdr_valid) begin + tx_buffer[i_target].data <= {i_source0[SOP_4DW_DWORD_LEN*32-1:0], i_source1[HDR_4DW_LEN*32-1:0]}; + end + else begin + tx_buffer[i_target].data <= {i_source0[SOP_4DW_DWORD_LEN*32-1:0], i_source1[NON_SOP_DWORD_LEN*32-1:SOP_4DW_DWORD_LEN*32]}; + end + end + endcase + tx_buffer[i_target].offset <= i_offset; + tx_buffer[i_target].offset_eop <= i_offset_eop; + tx_buffer[i_target].vf_active <= i_vf_active; + tx_buffer[i_target].valid <= 1'b1; +end +endtask : buf_two_sources + +// Buffer one entire source +task buf_one_source; + input e_channel i_target; + input logic [AVST_DW-1:0] i_source; + input e_offset i_offset; + input logic [2:0] i_offset_eop; + input logic i_vf_active; +begin + tx_buffer[i_target].data <= i_source; + tx_buffer[i_target].offset <= i_offset; + tx_buffer[i_target].offset_eop <= i_offset_eop; + tx_buffer[i_target].vf_active <= i_vf_active; + tx_buffer[i_target].valid <= 1'b1; +end +endtask : buf_one_source + +// Clear buffer +task clear_buf; + input integer i_ch; +begin + tx_buffer[i_ch].data <= '0; + tx_buffer[i_ch].offset <= OFFSET_ERR; + tx_buffer[i_ch].offset_eop <= '0; + tx_buffer[i_ch].vf_active <= '0; + tx_buffer[i_ch].valid <= '0; +end +endtask : clear_buf + +// Clear SOP, EOP, and valid +task clear_sop_eop_valid; + input integer i_ch; +begin + avl_tx_st_reg[i_ch].valid <= 1'b0; + avl_tx_st_reg[i_ch].sop <= 1'b0; + avl_tx_st_reg[i_ch].eop <= 1'b0; +end +endtask : clear_sop_eop_valid + +// Set valid but clear SOP & EOP +task set_valid_clear_sop_eop; + input integer i_ch; +begin + avl_tx_st_reg[i_ch].valid <= 1'b1; + avl_tx_st_reg[i_ch].sop <= 1'b0; + avl_tx_st_reg[i_ch].eop <= 1'b0; +end +endtask : set_valid_clear_sop_eop + +// Set SOP & EOP +task set_sop_eop; + input integer i_ch; +begin + avl_tx_st_reg[i_ch].valid <= 1'b1; + avl_tx_st_reg[i_ch].sop <= 1'b1; + avl_tx_st_reg[i_ch].eop <= 1'b1; +end +endtask : set_sop_eop + +// Set SOP +task set_sop; + input integer i_ch; +begin + avl_tx_st_reg[i_ch].valid <= 1'b1; + avl_tx_st_reg[i_ch].sop <= 1'b1; + avl_tx_st_reg[i_ch].eop <= 1'b0; +end +endtask : set_sop + +// Set EOP +task set_eop; + input integer i_ch; +begin + avl_tx_st_reg[i_ch].valid <= 1'b1; + avl_tx_st_reg[i_ch].sop <= 1'b0; + avl_tx_st_reg[i_ch].eop <= 1'b1; +end +endtask : set_eop + +endmodule diff --git a/ipss/pcie/rtl/pcie_tx_bridge_ptile.sv b/ipss/pcie/rtl/pcie_tx_bridge_ptile.sv new file mode 100755 index 0000000..54b29e7 --- /dev/null +++ b/ipss/pcie/rtl/pcie_tx_bridge_ptile.sv @@ -0,0 +1,44 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// ------- +// Functions: +// ------- +// Adapt AXI4-S TX streaming interface to PCIe HIP IP AVST TX interface +// * The AVST TX interface contains two 256-bit data channels +// * The AXI4-S TX interface contains single AXI4-S channel with multiple TLP data streams +// (See fim_if_pkg.sv for details) +// +// ------- +// Clock domain +// ------- +// All the inputs and outputs are synchronous to input clock : avl_clk +// +//----------------------------------------------------------------------------- + +import ofs_fim_pcie_pkg::*; +import ofs_fim_if_pkg::*; + +module pcie_tx_bridge_ptile ( + input logic avl_clk, + input logic avl_rst_n, + output t_avst_txs avl_tx_st, + input logic avl_tx_ready, + + ofs_fim_pcie_txs_axis_if.slave axis_tx_st, + + output logic tx_mrd_valid, + output logic [10:0] tx_mrd_length, + output logic [PCIE_EP_TAG_WIDTH-1:0] tx_mrd_tag, + output logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] tx_mrd_pfn, + output logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] tx_mrd_vfn, + output logic tx_mrd_vf_act, + input logic [CPL_CREDIT_WIDTH-1:0] cpl_pending_data_cnt +); + +// Place holder for future release + +endmodule diff --git a/ipss/pcie/rtl/pcie_wrapper.sv b/ipss/pcie/rtl/pcie_wrapper.sv new file mode 100755 index 0000000..0d94b3a --- /dev/null +++ b/ipss/pcie/rtl/pcie_wrapper.sv @@ -0,0 +1,628 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Wrapper for top level module of PCIe subsystem and AXI-S adapter +// AND MSI-X table + PBA + logic + required interconnect +// +//----------------------------------------------------------------------------- + +`include "fpga_defines.vh" +import ofs_fim_if_pkg::*; +import ofs_fim_cfg_pkg::*; +import ofs_fim_pcie_hdr_def::*; +import ofs_fim_pcie_pkg::*; +import ofs_csr_pkg::*; + +module pcie_wrapper + #(parameter PCIE_RANDOM_RDY = 0 ) // For validation: Randomly deassert PCIE Tx, Rx ready + ( // + input logic fim_clk, + input logic fim_rst_n, + input logic ninit_done, + input logic npor, + output logic reset_status, + + // PCIe pins + input logic pin_pcie_ref_clk_p, + input logic pin_pcie_in_perst_n, // connected to HIP + input logic [PCIE_LANES-1:0] pin_pcie_rx_p, + output logic [PCIE_LANES-1:0] pin_pcie_tx_p, + + pcie_ss_axis_if.source axi_st_rx_if, + pcie_ss_axis_if.sink axi_st_tx_if, + + ofs_fim_axi_lite_if.slave csr_lite_if, + ofs_fim_irq_axis_if.master irq_if, + + output t_sideband_from_pcie pcie_p2c_sideband, + input t_sideband_to_pcie pcie_c2p_sideband + ); + +//AXI EA Interface Related Parameters +localparam EA_CH = 2; +localparam AXI_EA_DATA_W = 392; +localparam AXI_EA_USER_W = 22; + +// AXI-M CSR interfaces +ofs_fim_axi_mmio_if csr_if(); + +// AXI-lite conversion +axi_lite2mmio axi_lite2mmio ( +.clk (fim_clk), +.rst_n (fim_rst_n), +.lite_if(csr_lite_if), +.mmio_if(csr_if) +); + +// AXIS PCIe channels - Rx path +ofs_fim_pcie_rxs_axis_if pcie2adpt_rx_st(); + +pcie_ss_axis_if adpt2mux_rx_st(); +pcie_ss_axis_if mux2adpt_rx_st(); + +ofs_fim_pcie_rxs_axis_if adpt2adpt_rx_st(); + +// AXIS PCIe channels - Tx path +ofs_fim_pcie_txs_axis_if adpt2fltr_tx_st(); +ofs_fim_pcie_txs_axis_if fltr2msix_tx_st(); +ofs_fim_pcie_txs_axis_if fltr2arb_tx_st(); + +ofs_fim_pcie_tx_axis_if mmio2arb_tx_st(); // not used +ofs_fim_pcie_tx_axis_if msix2arb_tx_st(); +ofs_fim_pcie_txs_axis_if arb2adpt_tx_st(); + +pcie_ss_axis_if adpt2mux_tx_st(); +pcie_ss_axis_if mux2adpt_tx_st(); + +ofs_fim_pcie_txs_axis_if adpt2pcie_tx_st(); +ofs_fim_pcie_txs_axis_if pcie_aligned_tx_st(); + +// AXIS MSIX response - not used +ofs_fim_afu_irq_rsp_axis_if #(.TDATA_WIDTH (4)) msix_rsp(); + +// AXIS PCIe channels - MuX +pcie_ss_axis_if mux2bar_rx_st[4:0](); +pcie_ss_axis_if bar2mux_tx_st[4:0](); + +///////////////////////////////////////////////////////////////// +/////////////////////////// PCIE Top //////////////////////////// + +// PCIe Interface (PCIe IP + Bridge) +pcie_top pcie_top ( + .fim_clk (fim_clk), + .fim_rst_n (fim_rst_n), + .ninit_done (ninit_done), + .npor (npor), + .reset_status (reset_status), + + .pin_pcie_ref_clk_p (pin_pcie_ref_clk_p), + .pin_pcie_in_perst_n (pin_pcie_in_perst_n), // connected to HIP + .pin_pcie_rx_p (pin_pcie_rx_p), + .pin_pcie_tx_p (pin_pcie_tx_p), + + .axis_rx_st (pcie2adpt_rx_st), + .axis_tx_st (pcie_aligned_tx_st), + + .csr_if (csr_if), + .irq_if (irq_if), + + .pcie_p2c_sideband (pcie_p2c_sideband), + .pcie_c2p_sideband (pcie_c2p_sideband) +); + + + +///////////////////////////////////////////////////////////////// +/////////////////////////// PCIE MuX //////////////////////////// + +// PCIE MuX: host <-> BAR0|5 +pcie_mux_top +pcie_mux_top ( + .clk ( fim_clk ) , + .rst_n ( fim_rst_n ) , + + .ho2mx_rx_port ( adpt2mux_rx_st ) , + .mx2ho_tx_port ( mux2adpt_tx_st ) , + .mx2fn_rx_port ( mux2bar_rx_st ) , + .fn2mx_tx_port ( bar2mux_tx_st ) , + .out_fifo_err ( ) , + .out_fifo_perr ( ) + ); + +// Data path (VF = X, BAR = 0) to/from PCIE MuX +always_comb +begin + mux2bar_rx_st[0].tready = mux2adpt_rx_st.tready; + mux2adpt_rx_st.tvalid = mux2bar_rx_st[0].tvalid; + mux2adpt_rx_st.tlast = mux2bar_rx_st[0].tlast; + mux2adpt_rx_st.tuser_vendor = mux2bar_rx_st[0].tuser_vendor; + mux2adpt_rx_st.tdata = mux2bar_rx_st[0].tdata; + mux2adpt_rx_st.tkeep = mux2bar_rx_st[0].tkeep; + + adpt2mux_tx_st.tready = bar2mux_tx_st[0].tready; + bar2mux_tx_st[0].tvalid = adpt2mux_tx_st.tvalid; + bar2mux_tx_st[0].tlast = adpt2mux_tx_st.tlast; + bar2mux_tx_st[0].tuser_vendor = adpt2mux_tx_st.tuser_vendor; + bar2mux_tx_st[0].tdata = adpt2mux_tx_st.tdata; + bar2mux_tx_st[0].tkeep = adpt2mux_tx_st.tkeep; +end + +///////////////////////////////////////////////////////////////// +////////////////////////// MSI-X CSRs /////////////////////////// +logic [6:0] inp2cr_msix_pba [4:1]; +logic [31:0] inp2cr_msix_count_vector[4:1]; + +logic [63:0] cr2out_msix_addr0 [4:1]; +logic [63:0] cr2out_msix_addr1 [4:1]; +logic [63:0] cr2out_msix_addr2 [4:1]; +logic [63:0] cr2out_msix_addr3 [4:1]; +logic [63:0] cr2out_msix_addr4 [4:1]; +logic [63:0] cr2out_msix_addr5 [4:1]; +logic [63:0] cr2out_msix_addr6 [4:1]; +logic [63:0] cr2out_msix_addr7 [4:1]; +logic [63:0] cr2out_msix_ctldat0 [4:1]; +logic [63:0] cr2out_msix_ctldat1 [4:1]; +logic [63:0] cr2out_msix_ctldat2 [4:1]; +logic [63:0] cr2out_msix_ctldat3 [4:1]; +logic [63:0] cr2out_msix_ctldat4 [4:1]; +logic [63:0] cr2out_msix_ctldat5 [4:1]; +logic [63:0] cr2out_msix_ctldat6 [4:1]; +logic [63:0] cr2out_msix_ctldat7 [4:1]; +logic [63:0] cr2out_msix_pba [4:1]; + +genvar g; +generate +for ( g = 1 ; g < 5 ; g++ ) +begin + parameter MM_ADDR_WIDTH = 20; + parameter MM_DATA_WIDTH = 64; + + parameter PF_NUM = 0; + parameter VF_NUM = ( g > 1 ) ? g - 2 : 0; + parameter VF_ACTIVE = ( g > 1 ) ? 1 : 0; + + logic avmm_m2s_write; + logic avmm_m2s_read; + logic [MM_ADDR_WIDTH-1:0] avmm_m2s_address; + logic [MM_DATA_WIDTH-1:0] avmm_m2s_writedata; + logic [(MM_DATA_WIDTH>>3)-1:0] avmm_m2s_byteenable; + + logic avmm_s2m_waitrequest; + logic avmm_s2m_writeresponsevalid; + logic avmm_s2m_readdatavalid; + logic [MM_DATA_WIDTH-1:0] avmm_s2m_readdata; + + logic tlp_rd_strb; + logic [9:0] tlp_rd_tag; + logic [13:0] tlp_rd_length; + logic [15:0] tlp_rd_req_id; + logic [23:0] tlp_rd_low_addr; + + axis_rx_mmio_bridge #( + .AVMM_ADDR_WIDTH (MM_ADDR_WIDTH), + .AVMM_DATA_WIDTH (MM_DATA_WIDTH) + ) + axis_rx_mmio_bridge ( + .clk (fim_clk), + .rst_n (fim_rst_n), + + .axis_rx_if (mux2bar_rx_st[g]), + + .avmm_s2m_waitrequest (avmm_s2m_waitrequest), + .avmm_s2m_writeresponsevalid (avmm_s2m_writeresponsevalid), + .avmm_s2m_readdatavalid (avmm_s2m_readdatavalid), + + .avmm_m2s_write (avmm_m2s_write), + .avmm_m2s_read (avmm_m2s_read), + .avmm_m2s_address (avmm_m2s_address), + .avmm_m2s_writedata (avmm_m2s_writedata), + .avmm_m2s_byteenable (avmm_m2s_byteenable), + + .tlp_rd_strb (tlp_rd_strb), + .tlp_rd_tag (tlp_rd_tag), + .tlp_rd_length (tlp_rd_length), + .tlp_rd_req_id (tlp_rd_req_id), + .tlp_rd_low_addr (tlp_rd_low_addr) + ); + + axis_tx_mmio_bridge #( + .PF_NUM (PF_NUM), + .VF_NUM (VF_NUM), + .VF_ACTIVE (VF_ACTIVE), + .AVMM_DATA_WIDTH (MM_DATA_WIDTH) + ) + axis_tx_mmio_bridge ( + .clk (fim_clk), + .rst_n (fim_rst_n), + + .axis_tx_if (bar2mux_tx_st[g]), + .axis_tx_error ( ), + + .avmm_s2m_readdatavalid (avmm_s2m_readdatavalid), + .avmm_s2m_readdata (avmm_s2m_readdata), + + .tlp_rd_strb (tlp_rd_strb), + .tlp_rd_tag (tlp_rd_tag), + .tlp_rd_length (tlp_rd_length), + .tlp_rd_req_id (tlp_rd_req_id), + .tlp_rd_low_addr (tlp_rd_low_addr) + ); + + msix_csr #( + .MM_ADDR_WIDTH (MM_ADDR_WIDTH), + .MM_DATA_WIDTH (MM_DATA_WIDTH) + ) + msix_csr ( + .clk (fim_clk), + .rst_n (fim_rst_n), + + .avmm_m2s_write (avmm_m2s_write), + .avmm_m2s_read (avmm_m2s_read), + .avmm_m2s_address (avmm_m2s_address), + .avmm_m2s_writedata (avmm_m2s_writedata), + .avmm_m2s_byteenable (avmm_m2s_byteenable), + + .avmm_s2m_waitrequest (avmm_s2m_waitrequest), + .avmm_s2m_writeresponsevalid (avmm_s2m_writeresponsevalid), + .avmm_s2m_readdatavalid (avmm_s2m_readdatavalid), + .avmm_s2m_readdata (avmm_s2m_readdata), + + .inp2cr_msix_pba (inp2cr_msix_pba[g]), + .inp2cr_msix_count_vector (inp2cr_msix_count_vector[g]), + + .cr2out_msix_addr0 (cr2out_msix_addr0[g]), + .cr2out_msix_addr1 (cr2out_msix_addr1[g]), + .cr2out_msix_addr2 (cr2out_msix_addr2[g]), + .cr2out_msix_addr3 (cr2out_msix_addr3[g]), + .cr2out_msix_addr4 (cr2out_msix_addr4[g]), + .cr2out_msix_addr5 (cr2out_msix_addr5[g]), + .cr2out_msix_addr6 (cr2out_msix_addr6[g]), + .cr2out_msix_addr7 (cr2out_msix_addr7[g]), + + .cr2out_msix_ctldat0 (cr2out_msix_ctldat0[g]), + .cr2out_msix_ctldat1 (cr2out_msix_ctldat1[g]), + .cr2out_msix_ctldat2 (cr2out_msix_ctldat2[g]), + .cr2out_msix_ctldat3 (cr2out_msix_ctldat3[g]), + .cr2out_msix_ctldat4 (cr2out_msix_ctldat4[g]), + .cr2out_msix_ctldat5 (cr2out_msix_ctldat5[g]), + .cr2out_msix_ctldat6 (cr2out_msix_ctldat6[g]), + .cr2out_msix_ctldat7 (cr2out_msix_ctldat7[g]), + + .cr2out_msix_pba (cr2out_msix_pba[g]) + ); +end +endgenerate + +///////////////////////////////////////////////////////////////// +////////////////////////// MSI-X Logic ////////////////////////// + +// EA AXI channel arbiter for out-going TLPs from msix_top and AFU +pcie_tx_arbiter pcie_tx_arbiter +( + .clk (fim_clk), + .rst_n (fim_rst_n), + + .i_afu_tx_st (fltr2arb_tx_st), + .i_msix_tx_st (msix2arb_tx_st), + .i_mmio_tx_st (mmio2arb_tx_st), + .o_pcie_tx_st (arb2adpt_tx_st) +); + +// No seperate MMIO channel - drive valid +assign mmio2arb_tx_st.tx.tvalid = 1'b0; + +// Service FIM and AFU interrupt requests +msix_top msix_top ( + .clk (fim_clk), + .rst_n (fim_rst_n), + .afu_softreset (1'b0), + + .i_afu_msix_req (fltr2msix_tx_st), + .o_msix_tx_st (msix2arb_tx_st), + .o_msix_rsp (msix_rsp), + + .inp2cr_msix_pba (inp2cr_msix_pba[1]), + + .cr2out_msix_addr0 (cr2out_msix_addr0[1]), + .cr2out_msix_addr1 (cr2out_msix_addr1[1]), + .cr2out_msix_addr2 (cr2out_msix_addr2[1]), + .cr2out_msix_addr3 (cr2out_msix_addr3[1]), + .cr2out_msix_addr4 (cr2out_msix_addr4[1]), + .cr2out_msix_addr5 (cr2out_msix_addr5[1]), + .cr2out_msix_addr6 (cr2out_msix_addr6[1]), + .cr2out_msix_addr7 (cr2out_msix_addr7[1]), + .cr2out_msix_ctldat0 (cr2out_msix_ctldat0[1]), + .cr2out_msix_ctldat1 (cr2out_msix_ctldat1[1]), + .cr2out_msix_ctldat2 (cr2out_msix_ctldat2[1]), + .cr2out_msix_ctldat3 (cr2out_msix_ctldat3[1]), + .cr2out_msix_ctldat4 (cr2out_msix_ctldat4[1]), + .cr2out_msix_ctldat5 (cr2out_msix_ctldat5[1]), + .cr2out_msix_ctldat6 (cr2out_msix_ctldat6[1]), + .cr2out_msix_ctldat7 (cr2out_msix_ctldat7[1]), + .cr2out_msix_pba (cr2out_msix_pba[1]), + + .inp2cr_msix_vpba (inp2cr_msix_pba[3]), + + .cr2out_msix_vaddr0 (cr2out_msix_addr0[3]), + .cr2out_msix_vaddr1 (cr2out_msix_addr1[3]), + .cr2out_msix_vaddr2 (cr2out_msix_addr2[3]), + .cr2out_msix_vaddr3 (cr2out_msix_addr3[3]), + .cr2out_msix_vaddr4 (cr2out_msix_addr4[3]), + .cr2out_msix_vaddr5 (cr2out_msix_addr5[3]), + .cr2out_msix_vaddr6 (cr2out_msix_addr6[3]), + .cr2out_msix_vaddr7 (cr2out_msix_addr7[3]), + .cr2out_msix_vctldat0 (cr2out_msix_ctldat0[3]), + .cr2out_msix_vctldat1 (cr2out_msix_ctldat1[3]), + .cr2out_msix_vctldat2 (cr2out_msix_ctldat2[3]), + .cr2out_msix_vctldat3 (cr2out_msix_ctldat3[3]), + .cr2out_msix_vctldat4 (cr2out_msix_ctldat4[3]), + .cr2out_msix_vctldat5 (cr2out_msix_ctldat5[3]), + .cr2out_msix_vctldat6 (cr2out_msix_ctldat6[3]), + .cr2out_msix_vctldat7 (cr2out_msix_ctldat7[3]), + .cr2out_msix_vpba (cr2out_msix_pba[3]), + + .i_pcie_p2c_sideband (pcie_p2c_sideband) +); + +// VF0, VF2 MSIX not used +assign inp2cr_msix_pba[2] = '0; +assign inp2cr_msix_pba[4] = '0; + +// MSIX response is n/c - drive ready +assign msix_rsp.tready = 1'b1; + +// Filter interrupt requests from AFU TLPs and route the requests to msix_top +msix_filter msix_filter ( + .i_afu_tx (adpt2fltr_tx_st), + .o_afu_tx (fltr2arb_tx_st), + .o_msix_tx (fltr2msix_tx_st) +); + +///////////////////////////////////////////////////////////////// +////////////////////////// ADAPTER "A" ////////////////////////// + +// EA AXI RX Streaming Interface +logic axi_ea_A_rx_tready; +logic axi_ea_A_rx_tvalid; +logic axi_ea_A_rx_tlast; +logic [AXI_EA_USER_W-1:0] axi_ea_A_rx_tuser [EA_CH-1:0]; +logic [AXI_EA_DATA_W-1:0] axi_ea_A_rx_tdata [EA_CH-1:0]; + +// EA AXI TX Streaming Interface +logic axi_ea_A_tx_tready; +logic axi_ea_A_tx_tvalid; +logic axi_ea_A_tx_tlast; +logic [AXI_EA_USER_W-1:0] axi_ea_A_tx_tuser [EA_CH-1:0]; +logic [AXI_EA_DATA_W-1:0] axi_ea_A_tx_tdata [EA_CH-1:0]; +logic axi_ea_rx_en = 1 ; +logic axi_tx_st_en = 1 ; +logic [31:0] prbs = 32'h12345678 ; + +always @(posedge fim_clk) // For Validation: Generate random ready deassertions + begin // + prbs <= prbs << 1 ;// random pattern generation (PRBS_32) + prbs[0] <= prbs[31] ^ prbs[28] ;// + end + +always_comb +begin /* synthesis translate_off */ + axi_ea_rx_en = 1 ; // default: disable Rx random stall + axi_tx_st_en = 1 ; // default: disable Tx random stall + if (PCIE_RANDOM_RDY) // + begin // + axi_ea_rx_en = prbs[ 3: 0]!=4'h5 // randomly stall Rx + & prbs[ 3: 0]!=4'ha ;// + axi_tx_st_en = prbs[31:28]!=4'h2 // randomly stall Tx + & prbs[31:28]!=4'h4 ;// + end /* synthesis translate_on */ + + pcie2adpt_rx_st.tready = axi_ea_A_rx_tready & axi_ea_rx_en; + axi_ea_A_rx_tvalid = pcie2adpt_rx_st.rx.tvalid & axi_ea_rx_en; + axi_ea_A_rx_tlast = pcie2adpt_rx_st.rx.tlast; + axi_ea_A_rx_tuser[0] = pcie2adpt_rx_st.rx.tuser[0]; + axi_ea_A_rx_tuser[1] = pcie2adpt_rx_st.rx.tuser[1]; + axi_ea_A_rx_tdata[0] = pcie2adpt_rx_st.rx.tdata[0]; + axi_ea_A_rx_tdata[1] = pcie2adpt_rx_st.rx.tdata[1]; + adpt2pcie_tx_st.clk = fim_clk; + adpt2pcie_tx_st.rst_n = fim_rst_n; + axi_ea_A_tx_tready = adpt2pcie_tx_st.tready & axi_tx_st_en; + adpt2pcie_tx_st.tx.tvalid = axi_ea_A_tx_tvalid & axi_tx_st_en; + adpt2pcie_tx_st.tx.tlast = axi_ea_A_tx_tlast; + adpt2pcie_tx_st.tx.tuser[0] = axi_ea_A_tx_tuser[0][2:0]; + adpt2pcie_tx_st.tx.tuser[1] = axi_ea_A_tx_tuser[1][2:0]; + adpt2pcie_tx_st.tx.tdata[0] = axi_ea_A_tx_tdata[0]; + adpt2pcie_tx_st.tx.tdata[1] = axi_ea_A_tx_tdata[1]; +end + +// Align the TX stream to ch0 for more efficient processing by the adapter. +pcie_ch0_align_tx pcie_ch0_align_tx ( + .clk (fim_clk), + .rst_n (fim_rst_n), + + .axis_tx_st_in (adpt2pcie_tx_st), + .axis_tx_st_out (pcie_aligned_tx_st) +); + +// AXI ST EA <-> AXI ST PCIe SS +axi_s_adapter #( .PU_CPL(1), .UNIQUE_TAG_WA(0)) +axi_s_adapter_A ( + .clk (fim_clk), + .resetb (fim_rst_n), + + .axi_ea_rx_tready (axi_ea_A_rx_tready), + .axi_ea_rx_tvalid (axi_ea_A_rx_tvalid), + .axi_ea_rx_tlast (axi_ea_A_rx_tlast), + .axi_ea_rx_tuser (axi_ea_A_rx_tuser), + .axi_ea_rx_tdata (axi_ea_A_rx_tdata), + + .axi_ea_tx_tready (axi_ea_A_tx_tready), + .axi_ea_tx_tvalid (axi_ea_A_tx_tvalid), + .axi_ea_tx_tlast (axi_ea_A_tx_tlast), + .axi_ea_tx_tuser (axi_ea_A_tx_tuser), + .axi_ea_tx_tdata (axi_ea_A_tx_tdata), + + .st_rx_tready (adpt2mux_rx_st.tready), + .st_rx_tvalid (adpt2mux_rx_st.tvalid), + .st_rx_tlast (adpt2mux_rx_st.tlast), + .st_rx_tuser_vendor (adpt2mux_rx_st.tuser_vendor), + .st_rx_tdata (adpt2mux_rx_st.tdata), + .st_rx_tkeep (adpt2mux_rx_st.tkeep), + + .st_tx_tready (mux2adpt_tx_st.tready), + .st_tx_tvalid (mux2adpt_tx_st.tvalid), + .st_tx_tlast (mux2adpt_tx_st.tlast), + .st_tx_tuser_vendor (mux2adpt_tx_st.tuser_vendor), + .st_tx_tdata (mux2adpt_tx_st.tdata), + .st_tx_tkeep (mux2adpt_tx_st.tkeep) +); + +///////////////////////////////////////////////////////////////// +////////////////////////// ADAPTER "B" ////////////////////////// + +// EA AXI RX Streaming Interface +logic axi_ea_B_rx_tready; +logic axi_ea_B_rx_tvalid; +logic axi_ea_B_rx_tlast; +logic [AXI_EA_USER_W-1:0] axi_ea_B_rx_tuser [EA_CH-1:0]; +logic [AXI_EA_DATA_W-1:0] axi_ea_B_rx_tdata [EA_CH-1:0]; + +// EA AXI TX Streaming Interface +logic axi_ea_B_tx_tready; +logic axi_ea_B_tx_tvalid; +logic axi_ea_B_tx_tlast; +logic [AXI_EA_USER_W-1:0] axi_ea_B_tx_tuser [EA_CH-1:0]; +logic [AXI_EA_DATA_W-1:0] axi_ea_B_tx_tdata [EA_CH-1:0]; + +// Connecting to/from AXI S Adapter +always_comb +begin + arb2adpt_tx_st.tready = axi_ea_B_rx_tready; + axi_ea_B_rx_tvalid = arb2adpt_tx_st.tx.tvalid; + axi_ea_B_rx_tlast = arb2adpt_tx_st.tx.tlast; + axi_ea_B_rx_tuser[0] = arb2adpt_tx_st.tx.tuser[0]; + axi_ea_B_rx_tuser[1] = arb2adpt_tx_st.tx.tuser[1]; + axi_ea_B_rx_tdata[0] = arb2adpt_tx_st.tx.tdata[0]; + axi_ea_B_rx_tdata[1] = arb2adpt_tx_st.tx.tdata[1]; + + adpt2adpt_rx_st.clk = fim_clk; + adpt2adpt_rx_st.rst_n = fim_rst_n; + + axi_ea_B_tx_tready = adpt2adpt_rx_st.tready; + adpt2adpt_rx_st.rx.tvalid = axi_ea_B_tx_tvalid; + adpt2adpt_rx_st.rx.tlast = axi_ea_B_tx_tlast; + adpt2adpt_rx_st.rx.tuser[0] = axi_ea_B_tx_tuser[0][21:0]; + adpt2adpt_rx_st.rx.tuser[1] = axi_ea_B_tx_tuser[1][21:0]; + adpt2adpt_rx_st.rx.tdata[0] = axi_ea_B_tx_tdata[0]; + adpt2adpt_rx_st.rx.tdata[1] = axi_ea_B_tx_tdata[1]; +end + +// AXI ST EA <-> AXI ST PCIe SS +axi_s_adapter #( .PASSTHRU_MODE(1), .UNIQUE_TAG_WA(0)) +axi_s_adapter_B ( + .clk (fim_clk), + .resetb (fim_rst_n), + + .axi_ea_rx_tready (axi_ea_B_rx_tready), + .axi_ea_rx_tvalid (axi_ea_B_rx_tvalid), + .axi_ea_rx_tlast (axi_ea_B_rx_tlast), + .axi_ea_rx_tuser (axi_ea_B_rx_tuser), + .axi_ea_rx_tdata (axi_ea_B_rx_tdata), + + .axi_ea_tx_tready (axi_ea_B_tx_tready), + .axi_ea_tx_tvalid (axi_ea_B_tx_tvalid), + .axi_ea_tx_tlast (axi_ea_B_tx_tlast), + .axi_ea_tx_tuser (axi_ea_B_tx_tuser), + .axi_ea_tx_tdata (axi_ea_B_tx_tdata), + + .st_rx_tready (adpt2mux_tx_st.tready), + .st_rx_tvalid (adpt2mux_tx_st.tvalid), + .st_rx_tlast (adpt2mux_tx_st.tlast), + .st_rx_tuser_vendor (adpt2mux_tx_st.tuser_vendor), + .st_rx_tdata (adpt2mux_tx_st.tdata), + .st_rx_tkeep (adpt2mux_tx_st.tkeep), + + .st_tx_tready (mux2adpt_rx_st.tready), + .st_tx_tvalid (mux2adpt_rx_st.tvalid), + .st_tx_tlast (mux2adpt_rx_st.tlast), + .st_tx_tuser_vendor (mux2adpt_rx_st.tuser_vendor), + .st_tx_tdata (mux2adpt_rx_st.tdata), + .st_tx_tkeep (mux2adpt_rx_st.tkeep) +); + +///////////////////////////////////////////////////////////////// +////////////////////////// ADAPTER "C" ////////////////////////// + +// EA AXI RX Streaming Interface +logic axi_ea_C_rx_tready; +logic axi_ea_C_rx_tvalid; +logic axi_ea_C_rx_tlast; +logic [AXI_EA_USER_W-1:0] axi_ea_C_rx_tuser [EA_CH-1:0]; +logic [AXI_EA_DATA_W-1:0] axi_ea_C_rx_tdata [EA_CH-1:0]; + +// EA AXI TX Streaming Interface +logic axi_ea_C_tx_tready; +logic axi_ea_C_tx_tvalid; +logic axi_ea_C_tx_tlast; +logic [AXI_EA_USER_W-1:0] axi_ea_C_tx_tuser [EA_CH-1:0]; +logic [AXI_EA_DATA_W-1:0] axi_ea_C_tx_tdata [EA_CH-1:0]; + +// Connecting to/from AXI S Adapter +always_comb +begin + adpt2adpt_rx_st.tready = axi_ea_C_rx_tready; + axi_ea_C_rx_tvalid = adpt2adpt_rx_st.rx.tvalid; + axi_ea_C_rx_tlast = adpt2adpt_rx_st.rx.tlast; + axi_ea_C_rx_tuser[0] = adpt2adpt_rx_st.rx.tuser[0]; + axi_ea_C_rx_tuser[1] = adpt2adpt_rx_st.rx.tuser[1]; + axi_ea_C_rx_tdata[0] = adpt2adpt_rx_st.rx.tdata[0]; + axi_ea_C_rx_tdata[1] = adpt2adpt_rx_st.rx.tdata[1]; + + adpt2fltr_tx_st.clk = fim_clk; + adpt2fltr_tx_st.rst_n = fim_rst_n; + + axi_ea_C_tx_tready = adpt2fltr_tx_st.tready; + adpt2fltr_tx_st.tx.tvalid = axi_ea_C_tx_tvalid; + adpt2fltr_tx_st.tx.tlast = axi_ea_C_tx_tlast; + adpt2fltr_tx_st.tx.tuser[0] = axi_ea_C_tx_tuser[0][2:0]; + adpt2fltr_tx_st.tx.tuser[1] = axi_ea_C_tx_tuser[1][2:0]; + adpt2fltr_tx_st.tx.tdata[0] = axi_ea_C_tx_tdata[0]; + adpt2fltr_tx_st.tx.tdata[1] = axi_ea_C_tx_tdata[1]; +end + +// AXI ST EA <-> AXI ST PCIe SS +axi_s_adapter +axi_s_adapter_C ( + .clk (fim_clk), + .resetb (fim_rst_n), + + .axi_ea_rx_tready (axi_ea_C_rx_tready), + .axi_ea_rx_tvalid (axi_ea_C_rx_tvalid), + .axi_ea_rx_tlast (axi_ea_C_rx_tlast), + .axi_ea_rx_tuser (axi_ea_C_rx_tuser), + .axi_ea_rx_tdata (axi_ea_C_rx_tdata), + + .axi_ea_tx_tready (axi_ea_C_tx_tready), + .axi_ea_tx_tvalid (axi_ea_C_tx_tvalid), + .axi_ea_tx_tlast (axi_ea_C_tx_tlast), + .axi_ea_tx_tuser (axi_ea_C_tx_tuser), + .axi_ea_tx_tdata (axi_ea_C_tx_tdata), + + .st_rx_tready (axi_st_rx_if.tready), + .st_rx_tvalid (axi_st_rx_if.tvalid), + .st_rx_tlast (axi_st_rx_if.tlast), + .st_rx_tuser_vendor (axi_st_rx_if.tuser_vendor), + .st_rx_tdata (axi_st_rx_if.tdata), + .st_rx_tkeep (axi_st_rx_if.tkeep), + + .st_tx_tready (axi_st_tx_if.tready), + .st_tx_tvalid (axi_st_tx_if.tvalid), + .st_tx_tlast (axi_st_tx_if.tlast), + .st_tx_tuser_vendor (axi_st_tx_if.tuser_vendor), + .st_tx_tdata (axi_st_tx_if.tdata), + .st_tx_tkeep (axi_st_tx_if.tkeep) +); + +endmodule diff --git a/ipss/pcie/rtl/pipeline/axis_reg_irq_rsp.sv b/ipss/pcie/rtl/pipeline/axis_reg_irq_rsp.sv new file mode 100755 index 0000000..b60dff9 --- /dev/null +++ b/ipss/pcie/rtl/pipeline/axis_reg_irq_rsp.sv @@ -0,0 +1,92 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// AXIS IRQ response pipeline register +// +//----------------------------------------------------------------------------- + +import ofs_fim_if_pkg::*; + +`timescale 1 ps / 1 ps +module axis_reg_irq_rsp +#( + parameter NUM_PIPELINES = 1, // 1-N + parameter MODE = 0, // 0: skid buffer 1: simple buffer 2: bypass + parameter TREADY_RST_VAL = 0 // 0: de-assert tready during reset 1: assert tready during reset +)( + input logic s_if_clk, + input logic s_if_rst_n, + input t_axis_irq_rsp s_if, + output logic s_if_tready, + + output logic m_if_clk, + output logic m_if_rst_n, + output t_axis_irq_rsp m_if, + input logic m_if_tready +); + +localparam TDATA_WIDTH = IRQ_RSP_DW; + +// synthesis traslate_off +initial begin + if (NUM_PIPELINES < 1) begin + $display("%m: Error: AXIS pipeline length: %0d less than 1.", NUM_PIPELINES); + end +end +// synthesis trasnslate_on + +t_axis_irq_rsp [NUM_PIPELINES-1:0] pipe_s_if; +logic [NUM_PIPELINES-1:0] s_tready; + +t_axis_irq_rsp [NUM_PIPELINES-1:0] pipe_m_if; +logic [NUM_PIPELINES-1:0] m_tready; + +// Connect s_if to the slave interface on the first pipeline +assign s_if_tready = s_tready[0]; + +// Connect m_if to the master interface on the last pipeline +assign m_if_clk = s_if_clk; +assign m_if_rst_n = s_if_rst_n; +assign m_if = pipe_m_if[NUM_PIPELINES-1]; + +genvar ig; +generate + for (ig=0; ig cycles earlier +// before RX buffer becomes full, to allow cycles of packets after ready is de-asserted +assign o_tx_st_ready = ~almfull; + +// Write TLP packet into RX buffer +assign write = ~full && (tx_st[CH0].valid || tx_st[CH1].valid); + +assign full = (usedw == BUF_SIZE); +assign almfull = (usedw >= BUF_SIZE-READY_LATENCY*2-1); // *2 for two channels +assign empty = (usedw == 0); + +always_ff @(posedge clk) begin + if (~rst_n) begin + wptr <= '0; + wptr_next <= 'h1; + end else begin + if (write) begin + if (tx_st[CH0].valid && tx_st[CH1].valid) + begin + tx_buffer[wptr] <= tx_st[CH0]; + tx_buffer[wptr_next] <= tx_st[CH1]; + wptr <= wptr + 2; + wptr_next <= wptr + 3; + end else if (tx_st[CH0].valid) + begin + tx_buffer[wptr] <= tx_st[CH0]; + wptr <= wptr + 1; + wptr_next <= wptr + 2; + end else if (tx_st[CH1].valid) + begin + tx_buffer[wptr] <= tx_st[CH1]; + wptr <= wptr + 1; + wptr_next <= wptr + 2; + end + end + end +end + +assign read = ~empty && (~buf_dout_valid || read_ack); + +always_ff @(posedge clk) begin + if (~rst_n) begin + rptr <= '0; + buf_dout_valid <= 1'b0; + end else begin + if (empty && read_ack) buf_dout_valid <= 1'b0; + if (read) begin + buf_dout_valid <= 1'b1; + rptr <= rptr + 1'b1; + end + end +end + +always_ff @(posedge clk) begin + if (read) buf_dout <= tx_buffer[rptr]; +end + +always_ff @(posedge clk) begin + if (~rst_n) begin + usedw <= '0; + end else begin + if (write) begin + if (tx_st[CH0].valid && tx_st[CH1].valid) begin + usedw <= read ? (usedw + 2'h1) : (usedw + 2'h2); + end else begin + usedw <= read ? usedw : (usedw + 2'h1); + end + end else if (read) begin + usedw <= (usedw - 2'h1); + end + end +end + +// Reading from the buffer +logic cpl_ready; +logic mem_ready; + +t_tlp_cpl_hdr hdr; +logic is_cpl; + +assign cpl_ready = ~o_cpl_st.valid || i_cpl_st_ready; +assign mem_ready = ~o_mem_st.valid || i_mem_st_ready; +assign read_ack = cpl_ready && mem_ready; + +`ifdef HTILE + function automatic logic [127:0] to_big_endian ( + input logic [127:0] hdr +); + for (int i=0; i<=3; i=i+1) begin + to_big_endian[i*32+:32] = hdr[(3-i)*32+:32]; + end +endfunction + + assign hdr = to_big_endian(buf_dout.data[127:0]); +`else + assign hdr = buf_dout.hdr; +`endif + + +always_ff @(posedge clk) begin + if (~rst_n) begin + o_cpl_st <= '0; + o_mem_st <= '0; + is_cpl <= 1'b0; + end else begin + if (cpl_ready && mem_ready) begin + o_cpl_st.valid <= 1'b0; + o_mem_st.valid <= 1'b0; + if (buf_dout_valid) begin + if (buf_dout.sop) begin + if (func_is_completion(hdr.dw0.fmttype)) begin + o_cpl_st <= buf_dout; + is_cpl <= 1'b1; + end else begin + o_mem_st <= buf_dout; + is_cpl <= 1'b0; + end + end else begin + if (is_cpl) o_cpl_st <= buf_dout; + else o_mem_st <= buf_dout; + end + end + end + end +end + + +endmodule + diff --git a/sim/bfm/packet_sender.sv b/sim/bfm/packet_sender.sv new file mode 100644 index 0000000..445553c --- /dev/null +++ b/sim/bfm/packet_sender.sv @@ -0,0 +1,118 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Send packets from external TX buffer(s) to DUT. +// +//----------------------------------------------------------------------------- + +import ofs_fim_cfg_pkg::*; +import ofs_fim_if_pkg::*; +import ofs_fim_pcie_pkg::*; + +module packet_sender #( + parameter BUF_SIZE = 2, + parameter NUM_PKT_BUF = 1, // up-to 2 + + // Derived + parameter LOG2_BUF_SIZE = $clog2(BUF_SIZE) +)( + input logic clk, + input logic rst_n, + + // Packet buffer interface + input logic [NUM_PKT_BUF-1:0][LOG2_BUF_SIZE:0] i_buf_size, // Number of packets to be sent + input logic [NUM_PKT_BUF-1:0] i_send_req, // Send packet request + output logic [NUM_PKT_BUF-1:0] o_send_ack, // Send packet ack + + output logic [NUM_PKT_BUF-1:0][LOG2_BUF_SIZE-1:0] o_buf_idx, // Index to packet buffer for next packets to be sent + input t_avst_rxs [NUM_PKT_BUF-1:0] i_packet, // Next packets + + // Packet sender interface + output t_avst_rxs o_rx_st, // Sending the packet downstream to DUT + input logic i_ready +); + +localparam SEL_WIDTH = $clog2(NUM_PKT_BUF); + +logic [SEL_WIDTH-1:0] buf_sel_next, buf_sel; +logic [NUM_PKT_BUF-1:0] buf_sel_1hot; + +logic [LOG2_BUF_SIZE:0] num_tx_packet; +logic [LOG2_BUF_SIZE:0] tx_packet_cnt; + t_avst_rxs tx_packet; + +logic pkt_sender_busy; +logic pkt_sender_ack; +logic rx_ready; + +//////////////////////////////////////////////////////////////////////////////// + +assign rx_ready = i_ready; + +assign o_buf_idx = {NUM_PKT_BUF{tx_packet_cnt[LOG2_BUF_SIZE-1:0]}}; +assign o_send_ack = {NUM_PKT_BUF{pkt_sender_ack}} & buf_sel_1hot; + +always_comb begin + if (NUM_PKT_BUF > 1) begin + buf_sel_next = buf_sel; + casez ({buf_sel, i_send_req}) + 3'b0_1? : buf_sel_next = 1'b1; + 3'b0_01 : buf_sel_next = 1'b0; + 3'b1_?1 : buf_sel_next = 1'b0; + 3'b1_10 : buf_sel_next = 1'b1; + endcase + end else begin + buf_sel_next = 1'b0; + end +end + +always_comb begin + buf_sel_1hot = '0; + buf_sel_1hot[buf_sel] = 1'b1; +end + +assign tx_packet = i_packet[buf_sel]; + +always_ff @(posedge clk) begin + if (~rst_n) begin + buf_sel <= '0; + pkt_sender_busy <= '0; + pkt_sender_ack <= '0; + num_tx_packet <= '0; + tx_packet_cnt <= '0; + for (int ch=0; ch AXIS +pcie_bridge pcie_bridge ( + .fim_clk (fim_clk), + .fim_rst_n (fim_rst_n), + + .avl_clk (avl_clk), + .avl_rst_n (~reset_status), + + .avl_rx_ready (avl_rx_ready), + .avl_rx_st (avl_rx_st), + .avl_tx_ready (avl_tx_ready), + .avl_tx_st (avl_tx_st), + + .fim_axis_rx_st (axis_rx_st), + .fim_axis_tx_st (axis_tx_st), + + .b2a_app_err_valid (b2a_app_err_valid), + .b2a_app_err_hdr (b2a_app_err_hdr), + .b2a_app_err_info (b2a_app_err_info), + .b2a_app_err_func_num (b2a_app_err_func_num), + + .chk_rx_err (chk_rx_err), + .chk_rx_err_vf_act (chk_rx_err_vf_act), + .chk_rx_err_pfn (chk_rx_err_pfn), + .chk_rx_err_vfn (chk_rx_err_vfn), + .chk_rx_err_code (chk_rx_err_code) +); + +// CSRs +pcie_csr pcie_csr ( + .csr_if (csr_if), + + // CSR input signals + .avl_clk (avl_clk), + .i_pcie_linkup (pcie_linkup), + .i_chk_rx_err (chk_rx_err), + .i_chk_rx_err_vf_act (chk_rx_err_vf_act), + .i_chk_rx_err_pfn (chk_rx_err_pfn), + .i_chk_rx_err_vfn (chk_rx_err_vfn), + .i_chk_rx_err_code (chk_rx_err_code), + + // CSR output signals + .o_pcie_linkup (pcie_p2c_sideband.pcie_linkup), + .o_chk_rx_err_code (pcie_p2c_sideband.pcie_chk_rx_err_code) +); + +pcie_flr_resync pcie_flr_resync ( + .avl_clk (avl_clk), + .avl_rst_n (~reset_status), + + .fim_clk (fim_clk), + .fim_rst_n (fim_rst_n), + + .p2f_sideband (p2f_sideband), + .f2p_sideband (f2p_sideband), + + .pcie_p2f_sideband (pcie_p2f_sideband), + .pcie_c2p_sideband (pcie_c2p_sideband) + +); + +always_comb begin + pcie_p2c_sideband.flr_active_pf = pcie_p2f_sideband.flr_active_pf; + pcie_p2c_sideband.flr_rcvd_vf = pcie_p2f_sideband.flr_rcvd_vf; + pcie_p2c_sideband.flr_rcvd_pf_num = pcie_p2f_sideband.flr_rcvd_pf_num; + pcie_p2c_sideband.flr_rcvd_vf_num = pcie_p2f_sideband.flr_rcvd_vf_num; + pcie_p2c_sideband.cfg_ctl.vf0_msix_mask = pcie_p2msix_sideband.cfg_ctl.vf0_msix_mask; +end + +pcie_msix_resync pcie_msix_resync ( + .avl_clk (avl_clk), + .avl_rst_n (~reset_status), + + .fim_clk (fim_clk), + .fim_rst_n (fim_rst_n), + + .pcie_p2msix_sideband (pcie_p2msix_sideband), + + .ctl_shdw_update (ctl_shdw_update), + .ctl_shdw_pf_num (ctl_shdw_pf_num), + .ctl_shdw_vf_num (ctl_shdw_vf_num), + .ctl_shdw_cfg (ctl_shdw_cfg), + .ctl_shdw_vf_active (ctl_shdw_vf_active), + .ctl_shdw_req_all (ctl_shdw_req_all) +); + + +//----------------------- +// Main test driver and logger module +//----------------------- +tester tester ( + .avl_clk (avl_clk), + .avl_rst_n (~reset_status), + .fim_clk (fim_clk), + .fim_rst_n (fim_rst_n), + + //-------------------------------------- + // To PCIE bridge + //-------------------------------------- + // Raw RX TLP + .o_avl_rx_st (avl_rx_st), + .i_avl_rx_ready (avl_rx_ready), + .i_avl_tx_st (avl_tx_st), + .o_avl_tx_ready (avl_tx_ready), + + // Error reporting to PCIe IP + .i_b2a_app_err_valid (b2a_app_err_valid), + .i_b2a_app_err_hdr (b2a_app_err_hdr), + .i_b2a_app_err_info (b2a_app_err_info), + .i_b2a_app_err_func_num (b2a_app_err_func_num), + + // Error reporting to PCIe feature CSR + .i_chk_rx_err (chk_rx_err), + .i_chk_rx_err_vf_act (chk_rx_err_vf_act), + .i_chk_rx_err_pfn (chk_rx_err_pfn), + .i_chk_rx_err_vfn (chk_rx_err_vfn), + .i_chk_rx_err_code (chk_rx_err_code), + + .i_pcie_p2c_sideband (pcie_p2c_sideband), + .i_flr_pf_done (f2p_sideband.flr_completed_pf), + .o_flr_pf_active (p2f_sideband.flr_active_pf), + .o_flr_rcvd_vf (p2f_sideband.flr_rcvd_vf), + .o_flr_rcvd_pf_num (p2f_sideband.flr_rcvd_pf_num), + .o_flr_rcvd_vf_num (p2f_sideband.flr_rcvd_vf_num), + .i_flr_completed_vf (f2p_sideband.flr_completed_vf), + .i_flr_completed_pf_num (f2p_sideband.flr_completed_pf_num), + .i_flr_completed_vf_num (f2p_sideband.flr_completed_vf_num) +); + + +//----------------------- +// Tie off unused interface +//----------------------- +initial begin + avl_clk = 1'b0; + reset_status = 1'b1; + wait (~pin_pcie_in_perst_n); + wait (pin_pcie_in_perst_n); + + #10000ps; + reset_status = 1'b0; +end + +always #1250ps avl_clk = ~avl_clk; // 400 MHz + +endmodule diff --git a/sim/bfm/ready_gen.sv b/sim/bfm/ready_gen.sv new file mode 100755 index 0000000..f9fe7d8 --- /dev/null +++ b/sim/bfm/ready_gen.sv @@ -0,0 +1,41 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Toggle ready signal based on the selected mode +// +//----------------------------------------------------------------------------- + +module ready_gen ( + input logic clk, + input logic rst_n, + input logic en, + input logic [3:0] mode, + output logic ready +); + +always_ff @(posedge clk) begin + if (~rst_n) begin + ready <= 1'b0; + end else if (en) begin + case (mode) + 4'h0 : begin + if ($urandom_range(1,10)%2 == 0) begin + ready <= 1'b0; + end else begin + ready <= 1'b1; + end + end + default : begin + ready <= ~ready; + end + endcase + end else begin + ready <= 1'b1; + end +end + +endmodule + diff --git a/sim/bfm/shmem.sv b/sim/bfm/shmem.sv new file mode 100644 index 0000000..d43f413 --- /dev/null +++ b/sim/bfm/shmem.sv @@ -0,0 +1,443 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Shared memory BFM +// * Only DW access support, no byte access support +// +//----------------------------------------------------------------------------- +`timescale 1ps / 1ps + +import ofs_fim_cfg_pkg::*; +import ofs_fim_if_pkg::*; +import ofs_fim_pcie_pkg::*; + +import test_pcie_utils::*; + +module shmem #( + parameter MEM_ADDR_SIZE = 20, // DW + parameter TLP_BUF_SIZE = 128, // Size of the buffer storing memory read completion TLP + + // Derived parameter + parameter MEM_SIZE = (1 << MEM_ADDR_SIZE), + parameter LOG2_TLP_BUF_SIZE = $clog2(TLP_BUF_SIZE) +)( + input logic clk, + input logic rst_n, + + // Interface for DUT + input t_avst_pcie_tx mem_st, + output logic mem_st_ready, + + output logic send_req, + input logic send_ack, + output logic [LOG2_TLP_BUF_SIZE:0] num_tx_packet, + input logic [LOG2_TLP_BUF_SIZE-1:0] tx_buf_idx, + output t_avst_pcie_rx [NUM_AVST_CH-1:0] tx_packet +); + +import ofs_fim_pcie_hdr_def::*; + +// memory +logic [MEM_SIZE-1:0][31:0] mem; + +logic shmem_write = 1'b0; +logic [63:0] shmem_waddr = '0; +logic [31:0] shmem_wdata = '0; + +t_avst_pcie_rx [TLP_BUF_SIZE-1:0] tx_buffer; + +logic mem_st_read_ready; +logic mem_st_write_ready; + +//-------------------- +// DUT memory access +//-------------------- +logic [63:0] full_mem_addr; +logic [MEM_ADDR_SIZE-1:0] mem_addr, mem_addr_q; +t_tlp_mem_req_hdr mem_hdr; +logic mem_vf_active; +logic mem_rd; +logic hdr_4dw; +logic [10:0] rd_length; +logic [10:0] length, length_q; +logic [3:0] first_be, last_be; +logic zero_length_read; +logic illegal_req; +logic unsupported_addr; +logic return_cpl, return_cpl_q; + +`ifdef HTILE + assign mem_hdr = to_big_endian(mem_st.data[127:0]); + assign mem_vf_active = mem_st.vf_active; +`else + assign mem_hdr = mem_st.hdr; + assign mem_vf_active = mem_hdr.requester_id[3]; +`endif + +assign mem_rd = func_is_mrd_req(mem_hdr.dw0.fmttype); +assign hdr_4dw = func_is_addr64(mem_hdr.dw0.fmttype); +assign mem_addr = hdr_4dw ? mem_hdr.lsb_addr[2+:MEM_ADDR_SIZE] : mem_hdr.addr[2+:MEM_ADDR_SIZE]; +assign full_mem_addr = hdr_4dw ? {mem_hdr.addr, mem_hdr.lsb_addr} : {32'h0, mem_hdr.addr}; +assign length = (mem_hdr.dw0.length == 0) ? 'd1024 : mem_hdr.dw0.length; +assign first_be = mem_hdr.first_be; +assign last_be = mem_hdr.last_be; +assign zero_length_read = (~|first_be & ~|last_be); + +always_comb begin + illegal_req = 1'b0; + + if (mem_st.valid && mem_st.sop) begin + if (|first_be) begin + // check first_be=0xf (shmem only supports DW access) + if (~&first_be) begin + illegal_req = 1'b1; + $display("Error: (shmem) first_be of memory request must be 0x0 or 0xf, detected 0x%0x\n", first_be); + end + end + + if (length == 10'd1) begin + // Check last_be=0x0 when length=1DW + if (|last_be) begin + illegal_req = 1'b1; + $display("Error: (shmem) last_be of memory request must be 0x0 when length=1, detected 0x%0x\n", last_be); + end + end else begin + // check last_be=0xf (shmem only supports DW access) + if (~&last_be) begin + illegal_req = 1'b1; + $display("Error: (shmem) last_be of memory request must be 0x0 or 0xf, detected 0x%0x\n", last_be); + end + end + + // Check address >= 2^32 when header is 4DW + if (hdr_4dw && ~|mem_hdr.addr) begin + illegal_req = 1'b1; + $display("Error: (shmem) 4DW header is used for memory request to address < 2^32 (address=0x%0x)\n", {mem_hdr.addr, mem_hdr.lsb_addr}); + end + + if (illegal_req) begin + $fatal(0,$psprintf("%8t: %m Illegal/unsupported memory request is detected.", $time)); + $finish(); + end + + // Check read address < 2^(MEM_ADDR_SIZE) + return_cpl = 1'b0; + unsupported_addr = 1'b0; + if (mem_rd && (full_mem_addr[63:(MEM_ADDR_SIZE+2)] > 0)) + begin + unsupported_addr = 1'b1; + `ifdef BFM_ENABLE_UNSUPPORTED_ADDR_CPL + return_cpl = 1'b1; + unsupported_addr = 1'b0; + `endif + end + end +end + +assign mem_st_ready = mem_st_write_ready && mem_st_read_ready; +assign mem_st_write_ready = ~shmem_write; + +// Memory write +always_ff @(posedge clk) begin + if (shmem_write) begin + mem[shmem_waddr[2+:MEM_ADDR_SIZE]] <= shmem_wdata; + end + + if (~shmem_write && mem_st.valid) begin + if (mem_st.sop && ~mem_rd) begin + $display("[%t] Info: (Endpoint) Writing to shared memory (byte addr:0x%x, length=%0d)", $time, {mem_addr, 2'h0}, length); + `ifdef HTILE + if (hdr_4dw) begin + for (int i=0; i<4; i=i+1) + if (i4) ? mem_addr + 4 : '0; + length_q <= (length>4) ? length - 4 : '0; + end else begin + for (int i=0; i<5; i=i+1) + if (i5) ? mem_addr + 5 : '0; + length_q <= (length>5) ? length - 5 : '0; + end + `else + for (int i=0; i<8; i=i+1) + if (i8) ? mem_addr + 8 : '0; + length_q <= (length>8) ? length - 8 : '0; + `endif + end else if (~mem_st.sop) begin + for (int i=0; i<8; i=i+1) + if (i8) ? mem_addr_q + 8 : '0; + length_q <= (length_q>8) ? length_q - 8 : '0; + end + end +end + +// Memory read +logic prepare_mem_packet; +logic wait_mem_xfer; +logic [4095:0] cur_mem_data; +logic [MEM_ADDR_SIZE-1:0] cur_mem_addr; +logic [10:0] cur_length; +logic [15:0] cur_requester_id; +logic [7:0] cur_tag; +logic cur_vf_active; +logic zero_length_rsp; + +always_comb begin + if (tx_buf_idx == num_tx_packet-1) begin + tx_packet = {'0, tx_buffer[tx_buf_idx]}; + end else begin + tx_packet = tx_buffer[tx_buf_idx+:2]; + end +end + +always_ff @(posedge clk) begin + if (~rst_n) begin + tx_buffer <= '0; + num_tx_packet <= '0; + send_req <= 1'b0; + wait_mem_xfer <= 1'b0; + mem_st_read_ready <= 1'b0; + end else begin + if (wait_mem_xfer) begin + if (~send_ack) begin + wait_mem_xfer <= 1'b0; + tx_buffer <= '0; + num_tx_packet <= '0; + mem_st_read_ready <= 1'b1; + $display(" ** Packets sent **"); + end + end else if (send_req) begin + if (send_ack) begin + send_req <= 1'b0; + wait_mem_xfer <= 1'b1; + end + end else if (prepare_mem_packet) begin + if (return_cpl_q) begin + if (zero_length_rsp) begin + create_cpl_packet(16'h0, cur_requester_id, 12'd1, cur_tag, {cur_mem_addr[4:0], 2'b0}, cur_vf_active); + end else begin + create_cpl_packet(16'h0, cur_requester_id, (cur_length<<2), cur_tag, {cur_mem_addr[4:0], 2'b0}, cur_vf_active); + end + prepare_mem_packet <= 1'b0; + send_req <= 1'b1; + end else begin + if (cur_length > 10'd64) begin + // length, completer ID, requester ID, byte_count, tag, lower_addr, vf_active, data + create_cpld_packet(10'd64, 16'h0, cur_requester_id, (cur_length<<2), cur_tag, {cur_mem_addr[4:0], 2'b0}, cur_vf_active, cur_mem_data); + cur_length <= cur_length - 'd64; + cur_mem_addr <= cur_mem_addr + 'd64; + for (int i=0; i<64; i=i+1) begin + if (i 2) begin + $display("Warning: memory write size exceed limit, only 1DW/2DW write is supported."); + end else begin + $display("[%t] Info: (Host) writing to shared memory (byte addr:0x%x, length=%0d)", $time, shmem_waddr, size); + for (int i=0; i 0) begin + data_str = ""; + size_limit = (remain < display_size) ? remain : display_size; + // Print DWs by display size + for (int i=0; i 5) ? (cur_length-5) : 0; + end else begin + packet.data[127:0] = hdr; + for (int i=0; i<4; i=i+1) begin + if (i < cur_length) begin + packet.data[(i*32+128)+:32] = data[dw_offset*32+:32]; + end + dw_offset = dw_offset + 1; + end + packet.empty = (cur_length < 4) ? (4-cur_length) : 0; + cur_length = (cur_length > 4) ? (cur_length-4) : 0; + end + end else begin + cur_length = 0; + packet.empty = '0; + packet.data = {'0, hdr}; + end + + packet.eop = (cur_length == 0) ? 1'b1 : 1'b0; + + pkt_buf[total_packet] = packet; + total_packet += 1; + + // Multi packets TLP + packet.sop = 1'b0; + while (cur_length > 0) begin + packet.data = '0; + packet.empty = (cur_length < 8) ? (8-cur_length) : 0; + + for (int i=0; i<8; i=i+1) begin + if (i < cur_length) begin + packet.data[i*32+:32] = data[dw_offset*32+:32]; + end + dw_offset = dw_offset+1; + end + + cur_length = (cur_length > 8) ? (cur_length-8) : 0; + packet.eop = (cur_length == 0) ? 1'b1 : 1'b0; + + pkt_buf[total_packet] = packet; + total_packet += 1; + + // Add idle cycles + for (int i=0; i 8) ? (cur_length-8) : 0; + end else begin + cur_length = 0; + packet.empty = '0; + packet.data = '0; + end + + packet.eop = (cur_length == 0) ? 1'b1 : 1'b0; + + pkt_buf[total_packet] = packet; + total_packet += 1; + + // Multi packets TLP + packet.sop = 1'b0; + while (cur_length > 0) begin + packet.data = '0; + packet.empty = (cur_length < 8) ? (8-cur_length) : 0; + + for (int i=0; i<8; i=i+1) begin + if (i < cur_length) begin + packet.data[i*32+:32] = data[dw_offset*32+:32]; + end + dw_offset = dw_offset+1; + end + + cur_length = (cur_length > 8) ? (cur_length-8) : 0; + packet.eop = (cur_length == 0) ? 1'b1 : 1'b0; + + pkt_buf[total_packet] = packet; + total_packet += 1; + + // Add idle cycles + for (int i=0; i 0) ? delay_round_count - 1 : 0; + end +endfunction + +endpackage +`endif diff --git a/sim/bfm/tester.sv b/sim/bfm/tester.sv new file mode 100755 index 0000000..27b10ee --- /dev/null +++ b/sim/bfm/tester.sv @@ -0,0 +1,517 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Tester module +// +//----------------------------------------------------------------------------- +`timescale 1ps / 1ps + +`include "fpga_defines.vh" +`include "test_utils.sv" + +import ofs_fim_cfg_pkg::*; +import ofs_fim_if_pkg::*; +import ofs_fim_pcie_pkg::*; + +module tester #( + parameter MAX_TEST = 100, + parameter MEM_ADDR_SIZE = 20, // DW size + parameter TLP_BUF_SIZE = 512 +)( + input logic avl_clk, + input logic avl_rst_n, + input logic fim_clk, + input logic fim_rst_n, + + // Input RX TLP from upstream + output t_avst_rxs o_avl_rx_st, // AVST RX channels carrying Rx TLP from upstream logic + input logic i_avl_rx_ready, // Backpressure signal to upstream logic + input t_avst_txs i_avl_tx_st, + output logic o_avl_tx_ready, + + // Error sideband signals to upstream PCIe IP + input logic i_b2a_app_err_valid, // Error is detected in the incoming TLP + input logic [31:0] i_b2a_app_err_hdr, // Header of the erroneous TLP + input logic [10:0] i_b2a_app_err_info, // Info of the error + input logic [1:0] i_b2a_app_err_func_num, // Function number associated with the erroneous TLP + + // Error signals to PCIe error status registers + input logic i_chk_rx_err, // Error is detected in the incoming TLP + input logic i_chk_rx_err_vf_act, // Indicates if error is associated with PF or VF + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] i_chk_rx_err_pfn, // PF associated with the erroneous TLP + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] i_chk_rx_err_vfn, // VF associated with the erroneous TLP + input logic [31:0] i_chk_rx_err_code, // Error info + + input t_sideband_from_pcie i_pcie_p2c_sideband, + input logic [7:0] i_flr_pf_done, + output logic [7:0] o_flr_pf_active, + output logic o_flr_rcvd_vf, + output logic [2:0] o_flr_rcvd_pf_num, + output logic [10:0] o_flr_rcvd_vf_num, + input logic i_flr_completed_vf, + input logic i_flr_completed_pf_num, + input logic [1:0] i_flr_completed_vf_num +); + +import ofs_fim_pcie_hdr_def::*; + +//Timeout in 1ms +`ifdef SIM_TIMEOUT + `define TIMEOUT `SIM_TIMEOUT +`else + `define TIMEOUT 1000000000ps +`endif + +localparam LOG2_TLP_BUF_SIZE = $clog2(TLP_BUF_SIZE); +localparam MAX_NUM_VF = (1<<11); + +`ifdef RP_MAX_TAGS + localparam RP_MAX_TAGS = `RP_MAX_TAGS; +`else + localparam RP_MAX_TAGS = 64; +`endif + +localparam RP_TAG_WIDTH = $clog2(RP_MAX_TAGS); + +typedef logic [RP_TAG_WIDTH-1:0] t_tlp_rp_tag; + +typedef struct packed { + logic vf_active; + logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; +} t_id; + +typedef struct packed { + t_id requester_id; + t_id completer_id; + logic [6:0] lower_addr; +} t_req_info; + +typedef struct packed { + logic result; + logic [1024*8-1:0] name; +} t_test_info; + + +logic [31:0] test_id; +logic reset_test; +logic test_done; +logic test_result; +t_test_info [MAX_TEST-1:0] test_summary; + +//----------------------- +// Test packets buffer +//----------------------- +// This buffer stores the packets from the test cases +t_avst_pcie_rx [TLP_BUF_SIZE-1:0] tx_buffer; +t_avst_pcie_rx [NUM_AVST_CH-1:0] tx_packet; +logic [LOG2_TLP_BUF_SIZE:0] num_tx_packet; +logic [LOG2_TLP_BUF_SIZE-1:0] tx_buf_idx; + +// This buffer stores the memory read response packets +logic [LOG2_TLP_BUF_SIZE:0] num_mem_packet; +t_avst_pcie_rx [NUM_AVST_CH-1:0] mem_tx_packet; +logic [LOG2_TLP_BUF_SIZE-1:0] mem_tx_buf_idx; + +// Packet sender +logic send_test_packet, send_mem_packet; +logic send_test_ack, send_mem_ack; +t_tlp_rp_tag tester_tag; +logic [RP_MAX_TAGS-1:0] tag_active; +t_req_info [RP_MAX_TAGS-1:0] tag_req_info; + +// PCIe checker error +logic [7:0] checker_err_count; +logic [255:0][10:0] checker_err_info; +logic [255:0][1:0] checker_err_func; + +// Packet receiver +logic clear_rx_buf; + +// PCIe error code to downstream module +logic [31:0] pcie_p2c_chk_err_code; + +// FLR signals +logic assert_flr; + +logic vf_active; +logic [2:0] flr_pfn; +logic [10:0] flr_vfn; +logic [7:0][MAX_NUM_VF-1:0] flr_vf_active; + +///////////////////////////////////////////////////////////////////////// + +initial begin + test_utils::init_logfile("reg.rout"); +end + +initial begin + reset_test = 1'b0; + test_id = '0; + test_done = 1'b0; + test_result = 1'b0; + tester_tag = '0; + + tx_buffer = '0; + num_tx_packet = '0; + send_test_packet = 1'b0; + + clear_rx_buf = 1'b0; + + assert_flr = 1'b0; +end + +initial begin + fork: timeout_thread begin + // timeout thread, wait for TIMEOUT period to pass + #(`TIMEOUT); + + // The test hasn't finished within TIMEOUT Period + @(posedge avl_clk); + $display ("TIMEOUT, test_pass didn't go high in 1 ms\n"); + + disable timeout_thread; + end + + wait (test_done==1) begin + // Test summary + $display("\n********************"); + $display(" Test summary"); + $display("********************"); + for (int i=0; i < test_id; i=i+1) begin + if (test_summary[i].result) + $display(" %0s (id=%0d) - pass", test_summary[i].name, i); + else + $display(" %0s (id=%0d) - FAILED", test_summary[i].name, i); + end + + if(test_utils::get_err_count() == 0 && test_utils::get_assert_err_count() == 0) begin + $fdisplay(test_utils::get_logfile_handle(), "Test passed!"); + end else begin + if (test_utils::get_err_count() != 0) begin + $fdisplay(test_utils::get_logfile_handle(), "Test FAILED! %d errors reported.\n", test_utils::get_err_count()); + end + if (test_utils::get_assert_err_count() != 0) begin + $fdisplay(test_utils::get_logfile_handle(), "Test FAILED! %d assertion errors reported.", test_utils::get_assert_err_count()); + end + end + $display("Assertion count: %0d", test_utils::get_assert_count()); + end + + join_any + $finish(); +end + +always begin : main + #10000ps; + wait (avl_rst_n); + wait (fim_rst_n); + + //------------------------- + // Test scenarios + //------------------------- + main_test(test_result); + test_done = 1'b1; +end + +//------------------------ +// TLP packet sender +//------------------------ +always_comb begin + if (tx_buf_idx == num_tx_packet-1) begin + tx_packet = {'0, tx_buffer[tx_buf_idx]}; + end else begin + tx_packet = tx_buffer[tx_buf_idx+:2]; + end +end + +// Packet sender arbitrates between test packets interface and memory response interface +packet_sender #( + .BUF_SIZE (TLP_BUF_SIZE), + .NUM_PKT_BUF (2) +) packet_sender ( + .clk (avl_clk), + .rst_n (avl_rst_n), + + // Packet from test case + .i_buf_size ({num_mem_packet, num_tx_packet}), + .i_send_req ({send_mem_packet, send_test_packet}), + .o_send_ack ({send_mem_ack, send_test_ack}), + .o_buf_idx ({mem_tx_buf_idx, tx_buf_idx}), + .i_packet ({mem_tx_packet, tx_packet}), + + // Packet sender interface + .i_ready (i_avl_rx_ready), + .o_rx_st (o_avl_rx_st) +); + +//------------------------ +// TLP receiver +//------------------------ +t_avst_pcie_tx cpl_st; +t_avst_pcie_tx mem_st; + +logic cpl_st_ready; +logic mem_st_ready; + +packet_receiver #( + .BUF_SIZE(TLP_BUF_SIZE), + .READY_LATENCY(3) // Mimic PCIe IP ready latency +) packet_receiver ( + .clk (avl_clk), + .rst_n (avl_rst_n && ~clear_rx_buf), + + // Packet receiver interface + .i_tx_st (i_avl_tx_st), + .o_tx_st_ready (o_avl_tx_ready), + + .o_cpl_st (cpl_st), + .i_cpl_st_ready (cpl_st_ready), + + .o_mem_st (mem_st), + .i_mem_st_ready (mem_st_ready) +); + +//------------------------ +// MMIO Request/Response +//------------------------ +typedef struct packed { + logic rsp_valid; + logic [63:0] rsp_data; + logic [2:0] rsp_status; +} t_mmio_entry; + +t_mmio_entry [255:0] tester_mmio_buf; +t_mmio_entry tester_mmio_entry; + +logic tester_mmio_req_valid; +t_tlp_rp_tag tester_mmio_req_tag; +t_req_info tester_mmio_req_info; +logic tester_mmio_buf_rd; +logic [7:0] tester_mmio_buf_raddr; + +t_tlp_cpl_hdr cpl_hdr; +logic cpl_hdr_4dw; + +initial begin + tester_mmio_req_valid = 1'b0; +end + +`ifdef HTILE + assign cpl_hdr = to_big_endian(cpl_st.data[127:0]); +`else + assign cpl_hdr = cpl_st.hdr; +`endif + +assign cpl_hdr_4dw = func_is_addr64(cpl_hdr.dw0.fmttype); + +// De-assert ready when previous response wth the same tag hasn't been consumed +assign cpl_st_ready = ~tester_mmio_buf[cpl_hdr.tag].rsp_valid; + +// MMIO request +always_ff @(posedge avl_clk) begin + if (~avl_rst_n) begin + tester_mmio_buf <= '0; + tag_active <= '0; + end else begin + if (cpl_st.valid && cpl_st_ready) begin + if (tag_active[cpl_hdr.tag]) begin + if (func_unexp_cpl(cpl_hdr, tag_req_info[cpl_hdr.tag])) begin + $finish(); + end + + tester_mmio_buf[cpl_hdr.tag].rsp_valid <= 1'b1; + tag_active[cpl_hdr.tag] <= 1'b0; + end + + `ifdef HTILE + tester_mmio_buf[cpl_hdr.tag].rsp_data <= cpl_hdr_4dw ? cpl_st.data[128+:64] : cpl_st.data[96+:64]; + `else + tester_mmio_buf[cpl_hdr.tag].rsp_data <= cpl_st.data[63:0]; + `endif + + tester_mmio_buf[cpl_hdr.tag].rsp_status <= cpl_hdr.status; + end + + if (tester_mmio_req_valid) begin + tag_active[tester_mmio_req_tag] <= 1'b1; + tag_req_info[tester_mmio_req_tag] <= tester_mmio_req_info; + end + + if (tester_mmio_buf_rd) begin + tester_mmio_entry <= tester_mmio_buf[tester_mmio_buf_raddr]; + tester_mmio_buf[tester_mmio_buf_raddr].rsp_valid <= 1'b0; + end + end +end + +//------------------------ +// Shared memory +//------------------------ +shmem #( + .MEM_ADDR_SIZE (MEM_ADDR_SIZE), + .TLP_BUF_SIZE (TLP_BUF_SIZE) +) shmem ( + .clk (avl_clk), + .rst_n (avl_rst_n), + + .mem_st (mem_st), + .mem_st_ready (mem_st_ready), + + .send_req (send_mem_packet), + .send_ack (send_mem_ack), + .num_tx_packet (num_mem_packet), + .tx_buf_idx (mem_tx_buf_idx), + .tx_packet (mem_tx_packet) +); + +//------------------------ +// Checker error logging +//------------------------ +// Sticky error registers until reset +always_ff @(posedge fim_clk) begin + if (~avl_rst_n || reset_test) begin + pcie_p2c_chk_err_code <= '0; + end else begin + pcie_p2c_chk_err_code <= (pcie_p2c_chk_err_code | i_pcie_p2c_sideband.pcie_chk_rx_err_code); + end +end + +// PCIe checker error count +always_ff @(posedge avl_clk) begin + if (~avl_rst_n) begin + checker_err_count <= '0; + end else begin + if (reset_test) begin + checker_err_count <= '0; + end else if (i_b2a_app_err_valid) begin + checker_err_info[checker_err_count] <= i_b2a_app_err_info; + checker_err_func[checker_err_count] <= i_b2a_app_err_func_num; + checker_err_count <= checker_err_count + 1; + end + end +end + +// FME MMIO error count +localparam ERR_MMIO_WR_ADDR = 4'h1; +localparam ERR_MMIO_WR_LEN = 4'h2; +localparam ERR_MMIO_RD_ADDR = 4'h4; +localparam ERR_MMIO_RD_LEN = 4'h8; + +logic [7:0] mmio_err_count; +logic [255:0][3:0] mmio_err_code; +logic [3:0] fme_mmio_err_code; + +/*//assign fme_mmio_err_code = DUT.corefim.fme_top.fme_io.inp2cr_pcie0_err_code[4:1]; +assign fme_mmio_err_code = top_tb.DUT.fme_top.fme_io.inp2cr_pcie0_err_code[4:1] ; + +always_ff @(posedge fim_clk) begin + if (~fim_rst_n) begin + mmio_err_count <= '0; + end else begin + if (reset_test) begin + mmio_err_count <= '0; + end else if (|fme_mmio_err_code) begin + mmio_err_code[mmio_err_count] <= fme_mmio_err_code; + mmio_err_count <= mmio_err_count + 1; + end + end +end +*/ +// AFU access error +logic [7:0] afu_access_err_count; +logic afu_access_err; +/* +//assign afu_access_err = DUT.corefim.fme_top.i_port_access_error[0]; +assign afu_access_err = top_tb.DUT.fme_top.cr2ras_afu_access_err[0]; + +always_ff @(posedge fim_clk) begin + if (~fim_rst_n) begin + afu_access_err_count <= '0; + end else begin + if (reset_test) begin + afu_access_err_count <= '0; + end else if (afu_access_err) begin + afu_access_err_count <= afu_access_err_count + 1; + end + end +end +*/ +//------------------------ +// FLR BFM +//------------------------ +pcie_flr #( + .MAX_NUM_VF (MAX_NUM_VF) +) pcie_flr ( + .clk (avl_clk), + .rst_n (avl_rst_n), + .i_assert_flr (assert_flr), + .i_vf_active (vf_active), + .i_pf_num (flr_pfn), + .i_vf_num (flr_vfn), + .i_flr_pf_done (i_flr_pf_done), + .o_flr_pf_active (o_flr_pf_active), + .o_flr_rcvd_vf (o_flr_rcvd_vf), + .o_flr_rcvd_pf_num (o_flr_rcvd_pf_num), + .o_flr_rcvd_vf_num (o_flr_rcvd_vf_num), + .o_flr_vf_active (flr_vf_active), + .i_flr_completed_vf (i_flr_completed_vf), + .i_flr_completed_pf_num (i_flr_completed_pf_num), + .i_flr_completed_vf_num (i_flr_completed_vf_num) +); + +//-------------------- +// Funtions & Tasks +//-------------------- +function automatic bit func_unexp_cpl ( + t_tlp_cpl_hdr cpl_hdr, + t_req_info req_info +); + logic unexp_cpl; + logic vf_active; + logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + + vf_active = cpl_hdr.completer_id[3]; + pfn = cpl_hdr.completer_id[2:0]; + vfn = cpl_hdr.completer_id[15:4]; + + unexp_cpl = 1'b0; + + if (cpl_hdr.requester_id !== req_info.requester_id) begin + unexp_cpl = 1'b1; + end + + if (vf_active !== req_info.completer_id.vf_active) begin + unexp_cpl = 1'b1; + end + + if (pfn !== req_info.completer_id.pfn) begin + unexp_cpl = 1'b1; + end + + if (vfn !== req_info.completer_id.vfn) begin + unexp_cpl = 1'b1; + end + + if (unexp_cpl) begin + $display("\nError: unexpected CPL (tag=%0d)", cpl_hdr.tag); + $display(" Request (requester_id=0x%0x vf_active=%0b pfn=0x%0x vfn=0x%0x)", req_info.requester_id, req_info.completer_id.vf_active, req_info.completer_id.pfn, req_info.completer_id.vfn); + $display(" Completion (requester_id=0x%0x vf_active=%0b pfn=0x%0x vfn=0x%0x)\n", cpl_hdr.requester_id, vf_active, pfn, vfn); + $fatal(0, $psprintf("%8t: %m Unexpected CPL is received with tag=%0d", $time, cpl_hdr.tag)); + end + + return unexp_cpl; +endfunction + + +//------------------------------------------------------- +// Test cases +//------------------------------------------------------- +`include "tester_utils.sv" +`include "tester_tests.sv" + +endmodule diff --git a/sim/bfm/tester_utils.sv b/sim/bfm/tester_utils.sv new file mode 100755 index 0000000..563ef21 --- /dev/null +++ b/sim/bfm/tester_utils.sv @@ -0,0 +1,556 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Utility tasks for tester +// +//----------------------------------------------------------------------------- + +import test_pcie_utils::*; + +//----------------------- +// Tag +//---------------------- +task f_reset_tag; +begin + tester_tag = '0; +end +endtask + +// Return tag to use for MRD request +task f_get_tag; + output t_tlp_rp_tag tag; +begin + wait (~tag_active[tester_tag]); + + tag = tester_tag; + f_incr_tag(); +end +endtask + +task f_incr_tag; +begin + if (tester_tag == RP_MAX_TAGS-1) + tester_tag = t_tlp_rp_tag'(0); + else + tester_tag = tester_tag + 'd1; +end +endtask + +//----------------------- +// Shared Memory +//---------------------- +task f_shmem_write; + input logic [63:0] addr; + input logic [63:0] data; + input logic [1:0] size; +begin + shmem.f_shmem_write(addr, data, size); +end +endtask + +task f_shmem_read; + input logic [63:0] addr; + input logic [1:0] size; + output logic [63:0] data; +begin + shmem.f_shmem_read(addr, size, data); +end +endtask + +task f_shmem_display; + input logic [63:0] addr; + input int size; // DW + input int display_size; // DW (1, 2, 4) +begin + shmem.f_shmem_display(addr, size, display_size); +end +endtask + +//----------------------- +// FLR +//----------------------- +task send_flr; + input logic vf_flr; + input logic [2:0] pfn; + input logic [10:0] vfn; +begin + @(posedge avl_clk); + flr_pfn = pfn; + flr_vfn = vfn; + vf_active = vf_flr; + assert_flr = 1'b1; + @(posedge avl_clk); + assert_flr = 1'b0; + @(posedge avl_clk); + if (~vf_active) wait (o_flr_pf_active[pfn] === 1'b1); + else wait (o_flr_rcvd_vf); +end +endtask + +task wait_flr; + input logic vf_active; + input logic [2:0] pfn; + input logic [10:0] vfn; +begin + if (~vf_active) begin + $display("Waiting for PF FLR completion status (PF=%0d)", pfn); + end else begin + $display("Waiting for VF FLR completion status (PF=%0d VF=%0d)", pfn, vfn); + end + + if (~vf_active && (o_flr_pf_active[pfn] === 1'b1)) begin + wait (~o_flr_pf_active[pfn]); + $display(" **FLR on PF completed**"); + end + + if (vf_active && (flr_vf_active[pfn][vfn] === 1'b1)) begin + wait (flr_vf_active[pfn][vfn] === 1'b0); + $display(" **FLR on VF completed**"); + end +end +endtask + + +//----------------------- +// Packet +//----------------------- +// Clear packet buffer +task clear_tx_buffer; +begin + tx_buffer = '0; + num_tx_packet = '0; +end +endtask + +// Send all packets in the tester packet buffer +task f_send_test_packet; +begin +// $display(" ** Sending TLP packets **"); + @(posedge avl_clk) + send_test_packet = 1'b1; + +// $display(" ** Waiting for ack **"); + @(posedge send_test_ack); + @(posedge avl_clk); + send_test_packet = 1'b0; + clear_tx_buffer(); +end +endtask + +// Write packet into packet buffer +task write_test_packet; + input t_avst_pcie_rx [127:0] pkt_buf; + input logic [6:0] buf_size; +begin + //$display("Adding test packet size=0x%d", buf_size); + for (int i=0; i + export QUARTUS_HOME= + export QUARTUS_INSTALL_DIR=$QUARTUS_HOME + export IMPORT_IP_ROOTDIR=$QUARTUS_HOME/../ip +5) Generate the sim files. + The sim files are not checked in and are generated on the fly. These files need to be generated before a simulation can be run successfully. + In order to do this, run the following steps + a. Got to $OFS_ROOTDIR/ofs-common/scripts/common/sim + b. Run the script "sh gen_sim_files.sh " for e.g. "sh gen_sim_files.sh d5005" + + +5) **Running Test****** + Unit tests are placed under $OFS_ROOTDIR/sim/unit_test/ + For example, the DFH Walker Unit Test may be found at $OFS_ROOTDIR/sim/unit_test/dfh_walker + Under each test directory, the simulation shell script, "run_sim.sh", may be found in the subdirectory "scripts". + For example, for the DFH Walker Unit Test, the simulation script may be found at: + $OFS_ROOTDIR/sim/unit_test/dfh_walker/script/run_sim.sh + To run the simulation under for test: + VCS : sh run_sim.sh + VCSMX: sh run_sim.sh VCSMX=1 + QuestaSim: sh run_sim.sh MSIM=1 + Please refer readme under respective testcase for more info. + +*****How to Run Unit level Regressions?****** + +** usage : python regress_run.py --help + + -l, --local Run regression locally, or run it on Farm. (Default:False) + -n[N], --n_procs [N] Maximum number of processes/UVM tests to run in parallel when run locally. This has no effect on Farm run. (Default #CPUs-1: 11) + -k, --pack [{'all','dfh','fme','he_hssi','he_lb','he_mem','list'}] Test package to run during regression (Default: %(default)s)') + -s [{vcs,msim,vcsmx}], --sim [{vcs,msim,vcsmx}] Simulator used for regression test. (Default: vcs) + -g, --gen_sim_files, Generate IP simulation files. This should only be done once per repo update. (Default: %(default)s) + -e, --email_list Sends the regression results on email provided in list (Default : It will send it to regression Owner) + +1) cd $VERDIR/../sim/unit_test/scripts + +###run locally, with 8 processes, for adp platform, using package of "all" tests, using VCS, to generate IP simulation files.  +python regress_run.py -l -n 8 -k all -s vcs -g + +###Same as above, but run on Intel Farm (no --local):   +python regress_run.py --local --n_procs 8 --pack all --sim vcs -g + +###Running script using defaults: run on Farm, adp platform, using package of "all" tests, to generate IP simulation files using VCS and sends result to owner +python regress_run.py -g + +2) Results are created in individual testcase scripts dir + diff --git a/sim/scripts/afu_flist.f b/sim/scripts/afu_flist.f new file mode 100644 index 0000000..7b8c42f --- /dev/null +++ b/sim/scripts/afu_flist.f @@ -0,0 +1,11 @@ +// Copyright 2021 Intel Corporation +// SPDX-License-Identifier: MIT + +// +// Default AFU that instantiates standard device exercisers. +// No Platform Interface Manager (PIM) +// + +-F $WORKDIR/ofs-common/src/common/he_lb/files_sim.f +$WORKDIR/ofs-common/src/fpga_family/stratix10/port_gasket/afu_main_std_exerciser/fim_compile/afu_main.sv + diff --git a/sim/scripts/ip_flist_combined.f b/sim/scripts/ip_flist_combined.f new file mode 100644 index 0000000..8c12f3a --- /dev/null +++ b/sim/scripts/ip_flist_combined.f @@ -0,0 +1,96 @@ +# UART +#src/uart/ip/uart.ip + +# EMIF +ipss/mem/ip/avmm_cdc.ip +ipss/mem/ip/avmm_pipeline_bridge.ip +ipss/mem/ip/emif_ddr4_no_ecc.ip +ipss/mem/axi_bridge/ofs_ddr_axi_bridge.qsys +ipss/mem/axi_bridge/ip/ofs_ddr_axi_bridge/amm_clock.ip +ipss/mem/axi_bridge/ip/ofs_ddr_axi_bridge/amm_reset.ip +#ipss/mem/axi_bridge/ip/ofs_ddr_axi_bridge/avmm_ep.ip +#ipss/mem/axi_bridge/ip/ofs_ddr_axi_bridge/axi_ep.ip + + +# ETH +ipss/hssi/s10/ip/address_decoder/address_decode.qsys +ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_clk_csr.ip +ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_master_0.ip +ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_merlin_master_translator_0.ip +ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_mm_to_mac.ip +ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_mm_to_phy.ip +ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_rx_xcvr_clk.ip +ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_tx_xcvr_clk.ip +ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_tx_xcvr_half_clk.ip +ipss/hssi/s10/ip/mac/altera_eth_10g_mac.ip +ipss/hssi/s10/ip/phy/altera_eth_10gbaser_phy.ip +ipss/hssi/s10/ip/pll_atxpll/altera_xcvr_atx_pll_ip.ip +ipss/hssi/s10/ip/pll_mpll/pll.ip +ipss/hssi/s10/ip/xcvr_reset_controller/reset_control.ip + +# PCIE +ipss/pcie/qip/pcie_ep_g3x16.ip + +# APF +src/pd_qsys/fabric/apf.qsys +src/pd_qsys/fabric/ip/apf/apf_achk_slv.ip +src/pd_qsys/fabric/ip/apf/apf_bpf_slv.ip +src/pd_qsys/fabric/ip/apf/apf_bpf_mst.ip +src/pd_qsys/fabric/ip/apf/apf_clock_bridge.ip +src/pd_qsys/fabric/ip/apf/apf_pgsk_slv.ip +src/pd_qsys/fabric/ip/apf/apf_reset_bridge.ip +src/pd_qsys/fabric/ip/apf/apf_rsv_b_slv.ip +src/pd_qsys/fabric/ip/apf/apf_rsv_c_slv.ip +src/pd_qsys/fabric/ip/apf/apf_rsv_d_slv.ip +src/pd_qsys/fabric/ip/apf/apf_rsv_e_slv.ip +src/pd_qsys/fabric/ip/apf/apf_rsv_f_slv.ip +src/pd_qsys/fabric/ip/apf/apf_st2mm_mst.ip +src/pd_qsys/fabric/ip/apf/apf_st2mm_slv.ip + + +# BPF +src/pd_qsys/fabric/bpf.qsys +src/pd_qsys/fabric/ip/bpf/bpf_apf_mst.ip +src/pd_qsys/fabric/ip/bpf/bpf_apf_slv.ip +src/pd_qsys/fabric/ip/bpf/bpf_clock_bridge.ip +src/pd_qsys/fabric/ip/bpf/bpf_emif_slv.ip +src/pd_qsys/fabric/ip/bpf/bpf_fme_mst.ip +src/pd_qsys/fabric/ip/bpf/bpf_fme_slv.ip +src/pd_qsys/fabric/ip/bpf/bpf_hssi_slv.ip +src/pd_qsys/fabric/ip/bpf/bpf_pcie_slv.ip +src/pd_qsys/fabric/ip/bpf/bpf_pmci_slv.ip +src/pd_qsys/fabric/ip/bpf/bpf_reset_bridge.ip +src/pd_qsys/fabric/ip/bpf/bpf_rsv_5_slv.ip +src/pd_qsys/fabric/ip/bpf/bpf_rsv_6_slv.ip +src/pd_qsys/fabric/ip/bpf/bpf_rsv_7_slv.ip +src/pd_qsys/spi_bridge/spi_bridge.qsys +src/pd_qsys/spi_bridge/ip/spi_bridge/spi_bridge_clock_in.ip +src/pd_qsys/spi_bridge/ip/spi_bridge/spi_bridge_reset_in.ip +src/pd_qsys/spi_bridge/ip/spi_bridge/spi_bridge_spi_0.ip + + +# PLL +ofs-common/src/common/fme_id_rom/fme_id_rom.ip +ofs-common/src/fpga_family/stratix10/sys_pll/sys_pll.ip + +# Port Gasket +ofs-common/src/fpga_family/stratix10/pr/PR_IP.ip +ofs-common/src/fpga_family/stratix10/user_clock/qph_user_clk_iopll_s10_RF100M.ip +ofs-common/src/fpga_family/stratix10/user_clock/qph_user_clk_iopll_reconfig.ip + +# Remote STP +ofs-common/src/fpga_family/stratix10/remote_stp/ip/remote_debug_jtag_only/host_if.ip +ofs-common/src/fpga_family/stratix10/remote_stp/ip/remote_debug_jtag_only/jop_blaster.ip +ofs-common/src/fpga_family/stratix10/remote_stp/ip/remote_debug_jtag_only/remote_debug_jtag_only_clock_in.ip +ofs-common/src/fpga_family/stratix10/remote_stp/ip/remote_debug_jtag_only/remote_debug_jtag_only_reset_in.ip +ofs-common/src/fpga_family/stratix10/remote_stp/ip/remote_debug_jtag_only/sys_clk.ip +ofs-common/src/fpga_family/stratix10/remote_stp/AFU_debug/scjio_agilex.ip +ofs-common/src/fpga_family/stratix10/remote_stp/AFU_debug/config_reset_release.ip +ofs-common/src/fpga_family/stratix10/remote_stp/remote_debug_jtag_only.qsys + +ofs-common/src/fpga_family/stratix10/cfg_mon/cfg_mon.ip +ofs-common/src/fpga_family/stratix10/avst_pipeline/avst_pipeline_st_pipeline_stage_0.ip +ofs-common/src/fpga_family/stratix10/avst_pipeline/avst_pipeline_st_pipeline_stage_1.ip + +# Fifo +ofs-common/src/common/lib/fifo/sc_fifo_tx_sc_fifo.ip diff --git a/sim/scripts/ip_flist_reloc.f b/sim/scripts/ip_flist_reloc.f new file mode 100644 index 0000000..64fd518 --- /dev/null +++ b/sim/scripts/ip_flist_reloc.f @@ -0,0 +1,70 @@ +sim/scripts/qip_gen/ipss/mem/ip/avmm_cdc.ip +sim/scripts/qip_gen/ipss/mem/ip/avmm_pipeline_bridge.ip +sim/scripts/qip_gen/ipss/mem/ip/emif_ddr4_no_ecc.ip +sim/scripts/qip_gen/ipss/mem/axi_bridge/ofs_ddr_axi_bridge.qsys +sim/scripts/qip_gen/ipss/mem/axi_bridge/ip/ofs_ddr_axi_bridge/amm_clock.ip +sim/scripts/qip_gen/ipss/mem/axi_bridge/ip/ofs_ddr_axi_bridge/amm_reset.ip +sim/scripts/qip_gen/ipss/hssi/s10/ip/address_decoder/address_decode.qsys +sim/scripts/qip_gen/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_clk_csr.ip +sim/scripts/qip_gen/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_master_0.ip +sim/scripts/qip_gen/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_merlin_master_translator_0.ip +sim/scripts/qip_gen/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_mm_to_mac.ip +sim/scripts/qip_gen/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_mm_to_phy.ip +sim/scripts/qip_gen/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_rx_xcvr_clk.ip +sim/scripts/qip_gen/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_tx_xcvr_clk.ip +sim/scripts/qip_gen/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_tx_xcvr_half_clk.ip +sim/scripts/qip_gen/ipss/hssi/s10/ip/mac/altera_eth_10g_mac.ip +sim/scripts/qip_gen/ipss/hssi/s10/ip/phy/altera_eth_10gbaser_phy.ip +sim/scripts/qip_gen/ipss/hssi/s10/ip/pll_atxpll/altera_xcvr_atx_pll_ip.ip +sim/scripts/qip_gen/ipss/hssi/s10/ip/pll_mpll/pll.ip +sim/scripts/qip_gen/ipss/hssi/s10/ip/xcvr_reset_controller/reset_control.ip +sim/scripts/qip_gen/ipss/pcie/qip/pcie_ep_g3x16.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/apf.qsys +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/apf/apf_achk_slv.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/apf/apf_bpf_slv.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/apf/apf_bpf_mst.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/apf/apf_clock_bridge.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/apf/apf_pgsk_slv.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/apf/apf_reset_bridge.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/apf/apf_rsv_b_slv.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/apf/apf_rsv_c_slv.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/apf/apf_rsv_d_slv.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/apf/apf_rsv_e_slv.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/apf/apf_rsv_f_slv.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/apf/apf_st2mm_mst.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/apf/apf_st2mm_slv.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/bpf.qsys +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/bpf/bpf_apf_mst.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/bpf/bpf_apf_slv.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/bpf/bpf_clock_bridge.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/bpf/bpf_emif_slv.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/bpf/bpf_fme_mst.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/bpf/bpf_fme_slv.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/bpf/bpf_hssi_slv.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/bpf/bpf_pcie_slv.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/bpf/bpf_pmci_slv.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/bpf/bpf_reset_bridge.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/bpf/bpf_rsv_5_slv.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/bpf/bpf_rsv_6_slv.ip +sim/scripts/qip_gen/src/pd_qsys/fabric/ip/bpf/bpf_rsv_7_slv.ip +sim/scripts/qip_gen/src/pd_qsys/spi_bridge/spi_bridge.qsys +sim/scripts/qip_gen/src/pd_qsys/spi_bridge/ip/spi_bridge/spi_bridge_clock_in.ip +sim/scripts/qip_gen/src/pd_qsys/spi_bridge/ip/spi_bridge/spi_bridge_reset_in.ip +sim/scripts/qip_gen/src/pd_qsys/spi_bridge/ip/spi_bridge/spi_bridge_spi_0.ip +sim/scripts/qip_gen/ofs-common/src/common/fme_id_rom/fme_id_rom.ip +sim/scripts/qip_gen/ofs-common/src/fpga_family/stratix10/sys_pll/sys_pll.ip +sim/scripts/qip_gen/ofs-common/src/fpga_family/stratix10/pr/PR_IP.ip +sim/scripts/qip_gen/ofs-common/src/fpga_family/stratix10/user_clock/qph_user_clk_iopll_s10_RF100M.ip +sim/scripts/qip_gen/ofs-common/src/fpga_family/stratix10/user_clock/qph_user_clk_iopll_reconfig.ip +sim/scripts/qip_gen/ofs-common/src/fpga_family/stratix10/remote_stp/ip/remote_debug_jtag_only/host_if.ip +sim/scripts/qip_gen/ofs-common/src/fpga_family/stratix10/remote_stp/ip/remote_debug_jtag_only/jop_blaster.ip +sim/scripts/qip_gen/ofs-common/src/fpga_family/stratix10/remote_stp/ip/remote_debug_jtag_only/remote_debug_jtag_only_clock_in.ip +sim/scripts/qip_gen/ofs-common/src/fpga_family/stratix10/remote_stp/ip/remote_debug_jtag_only/remote_debug_jtag_only_reset_in.ip +sim/scripts/qip_gen/ofs-common/src/fpga_family/stratix10/remote_stp/ip/remote_debug_jtag_only/sys_clk.ip +sim/scripts/qip_gen/ofs-common/src/fpga_family/stratix10/remote_stp/AFU_debug/scjio_agilex.ip +sim/scripts/qip_gen/ofs-common/src/fpga_family/stratix10/remote_stp/AFU_debug/config_reset_release.ip +sim/scripts/qip_gen/ofs-common/src/fpga_family/stratix10/remote_stp/remote_debug_jtag_only.qsys +sim/scripts/qip_gen/ofs-common/src/fpga_family/stratix10/cfg_mon/cfg_mon.ip +sim/scripts/qip_gen/ofs-common/src/fpga_family/stratix10/avst_pipeline/avst_pipeline_st_pipeline_stage_0.ip +sim/scripts/qip_gen/ofs-common/src/fpga_family/stratix10/avst_pipeline/avst_pipeline_st_pipeline_stage_1.ip +sim/scripts/qip_gen/ofs-common/src/common/lib/fifo/sc_fifo_tx_sc_fifo.ip diff --git a/sim/scripts/msim_filelist.sh b/sim/scripts/msim_filelist.sh new file mode 100755 index 0000000..d4e077c --- /dev/null +++ b/sim/scripts/msim_filelist.sh @@ -0,0 +1,64 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +. $OFS_ROOTDIR/sim/scripts/msim_ip_flist.sh + +# +cp -f $OFS_ROOTDIR/ofs-common/src/common/fme_id_rom/fme_id.mif ./ +# + +LIB_FILELIST="$QUARTUS_ROOTDIR/eda/sim_lib/altera_primitives.v \ +$QUARTUS_ROOTDIR/eda/sim_lib/220model.v \ +$QUARTUS_ROOTDIR/eda/sim_lib/sgate.v \ +$QUARTUS_ROOTDIR/eda/sim_lib/altera_mf.v \ +$QUARTUS_ROOTDIR/eda/sim_lib/altera_lnsim.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/fourteennm_atoms.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/mentor/fourteennm_atoms_ncrypt.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/ct1_hssi_atoms.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/ct1_hssi_atoms_ncrypt.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/mentor/cr3v0_serdes_models_ncrypt.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/ct1_hip_atoms.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/ct1_hip_atoms_ncrypt.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/ctp_hssi_atoms.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/ctp_hssi_atoms_ncrypt.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/cta_hssi_atoms.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/cta_hssi_atoms_ncrypt.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/ctab_hssi_atoms.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/ctab_hssi_atoms_ncrypt.sv" + +INC_DIR="+incdir+$OFS_ROOTDIR/ofs-common/src/common/includes/ \ ++incdir+$OFS_ROOTDIR/src/includes/ \ ++incdir+$OFS_ROOTDIR/ipss/hssi/inc/" + + +PLAT_RTL_FILELIST="-f $OFS_ROOTDIR/sim/scripts/rtl_comb.f" + +RTL_FILELIST="$COMMON_RTL_FILELIST \ +$PLAT_RTL_FILELIST" + +MSIM_FILELIST="$INC_DIR \ +$LIB_FILELIST \ +$RTL_FILELIST \ +$QSYS_FILELIST" + + +if [ -z ${SIM_DIR} ]; +then + PIM_TEMPLATE_DIR=$OFS_ROOTDIR/sim/ip_libraries/pim_template +else + PIM_TEMPLATE_DIR=$SIM_DIR/sim/ip_libraries/pim_template +fi +echo "Setting for PIM_TEMPLATE_DIR=${PIM_TEMPLATE_DIR}" +PIM_PLATFORM_NAME=d5005 +PIM_INI_FILE=$OFS_ROOTDIR/src/top/ofs_d5005.ini +PIM_FLIST=$PIM_TEMPLATE_DIR/pim_source_files.list +AFU_FLIST=$OFS_ROOTDIR/sim/scripts/afu_flist.f + +# Configure a PIM-based AFU +# Construct the simulation build environment for the target AFU. A common +# script can be used for UVM and unit tests on all targets. The script +# will generate a simulator include file afu_with_pim/all_sim_files.list. +$OFS_ROOTDIR/ofs-common/scripts/common/sim/ofs_pim_sim_setup.sh -t "$PIM_TEMPLATE_DIR" -b "$PIM_PLATFORM_NAME" + +# Load AFU and PIM sources into simulation +BASE_AFU_SRC="-F $PIM_FLIST -F $AFU_FLIST" diff --git a/sim/scripts/qip_sim_script/.keep b/sim/scripts/qip_sim_script/.keep new file mode 100644 index 0000000..4f64fc2 --- /dev/null +++ b/sim/scripts/qip_sim_script/.keep @@ -0,0 +1 @@ +NOTE: Keep this directory in repo, but not the contents. diff --git a/sim/scripts/rtl_comb.f b/sim/scripts/rtl_comb.f new file mode 100755 index 0000000..d9121c1 --- /dev/null +++ b/sim/scripts/rtl_comb.f @@ -0,0 +1,268 @@ +$WORKDIR/src/includes/ofs_fim_cfg_pkg.sv +$WORKDIR/ipss/pcie/rtl/ofs_fim_pcie_hdr_def.sv +$WORKDIR/ofs-common/src/common/lib/mux/pf_vf_mux_pkg.sv +$WORKDIR/src/afu_top/mux/top_cfg_pkg.sv +$WORKDIR/ipss/pcie/rtl/ofs_fim_pcie_pkg.sv +$WORKDIR/ofs-common/src/common/includes/ofs_fim_axi_mmio_if.sv +$WORKDIR/ofs-common/src/common/includes/ofs_fim_axi_lite_if.sv +$WORKDIR/ofs-common/src/common/includes/ofs_csr_pkg.sv +$WORKDIR/src/includes/fpga_defines.vh +$WORKDIR/ofs-common/src/common/includes/ofs_avst_if.sv +$WORKDIR/src/includes/ofs_pcie_ss_plat_cfg_pkg.sv +$WORKDIR/ofs-common/src/common/includes/ofs_pcie_ss_cfg_pkg.sv +$WORKDIR/ofs-common/src/common/includes/pcie_ss_hdr_pkg.sv +$WORKDIR/ofs-common/src/common/includes/pcie_ss_pkg.sv +$WORKDIR/ofs-common/src/common/includes/pcie_ss_axis_if.sv +$WORKDIR/ofs-common/src/common/includes/emif_avmm_if.sv +$WORKDIR/ofs-common/src/common/includes/ofs_fim_if_pkg.sv +$WORKDIR/ofs-common/src/common/includes/ofs_fim_pwrgoodn_if.sv +$WORKDIR/ofs-common/src/common/includes/vfme_csr_io_if.sv +$WORKDIR/ofs-common/src/common/includes/port_csr_io_if.sv +$WORKDIR/ofs-common/src/common/includes/pcie_ss_axis_pkg.sv +$WORKDIR/ofs-common/src/common/lib/bridges/hf_pipe.sv +$OFS_ROOTDIR/ofs-common/src/fpga_family/agilex/pri_enc/prio_enc_w4_t1.v +$OFS_ROOTDIR/ofs-common/src/fpga_family/agilex/pri_enc/prio_enc_w4_t1_b4.v +$OFS_ROOTDIR/ofs-common/src/fpga_family/agilex/pri_enc/prio_enc_w6_t1.v +$OFS_ROOTDIR/ofs-common/src/fpga_family/agilex/pri_enc/prio_enc_w6_t1_b6.v +$OFS_ROOTDIR/ofs-common/src/fpga_family/agilex/pri_enc/prio_enc_w6_t2.v +$OFS_ROOTDIR/ofs-common/src/fpga_family/agilex/pri_enc/prio_enc_w6_t2_b60.v +$OFS_ROOTDIR/ofs-common/src/fpga_family/agilex/pri_enc/prio_enc_w6_t2_b72.v +$OFS_ROOTDIR/ofs-common/src/fpga_family/agilex/pri_enc/prio_enc_w6_t2_b84.v +$OFS_ROOTDIR/ofs-common/src/fpga_family/agilex/pri_enc/prio_enc_w8_t2.v +$OFS_ROOTDIR/ofs-common/src/fpga_family/agilex/pri_enc/prio_enc_w12_t2.v +$OFS_ROOTDIR/ofs-common/src/fpga_family/agilex/pri_enc/prio_enc_w12_t2_b12.v +$OFS_ROOTDIR/ofs-common/src/fpga_family/agilex/pri_enc/prio_enc_w12_t2_b24.v +$OFS_ROOTDIR/ofs-common/src/fpga_family/agilex/pri_enc/prio_enc_w12_t2_b36.v +$OFS_ROOTDIR/ofs-common/src/fpga_family/agilex/pri_enc/prio_enc_w12_t2_b48.v +$OFS_ROOTDIR/ofs-common/src/fpga_family/agilex/pri_enc/prio_enc_w12_t2_b60.v +$OFS_ROOTDIR/ofs-common/src/fpga_family/agilex/pri_enc/prio_enc_w12_t2_b72.v +$OFS_ROOTDIR/ofs-common/src/fpga_family/agilex/pri_enc/prio_enc_w12_t2_b84.v +$OFS_ROOTDIR/ofs-common/src/fpga_family/agilex/pri_enc/pri_enc_64_6.sv +$OFS_ROOTDIR/ofs-common/src/fpga_family/agilex/pri_enc/pri_enc_96_7.sv +$WORKDIR/ofs-common/src/common/lib/fifo/fim_rdack_scfifo.sv +$WORKDIR/ofs-common/src/common/lib/fifo/fim_rdack_dcfifo.sv +$WORKDIR/ofs-common/src/common/lib/fifo/fim_scfifo.sv +$WORKDIR/ofs-common/src/common/lib/fifo/fim_dcfifo.sv +$WORKDIR/ofs-common/src/common/lib/fifo/quartus_bfifo.sv +$WORKDIR/ofs-common/src/common/lib/fifo/bfifo.sv +$WORKDIR/ofs-common/src/common/lib/fifo/altera_ram.sv +$WORKDIR/ofs-common/src/common/lib/fifo/altera_ram_reg.sv +$WORKDIR/ofs-common/src/common/lib/fifo/bypass_fifo.v +$WORKDIR/ofs-common/src/common/lib/fifo/fifo_w_rewind.sv +$WORKDIR/ofs-common/src/common/lib/fifo/qfifo.sv +$WORKDIR/ofs-common/src/common/lib/ram/ram_1r1w.sv +$WORKDIR/ofs-common/src/common/lib/ram/gram_sdp.v +$WORKDIR/ofs-common/src/common/lib/sync/fim_cross_handshake.sv +$WORKDIR/ofs-common/src/common/lib/sync/fim_cross_strobe.sv +$WORKDIR/ofs-common/src/common/lib/sync/fim_resync.sv +$WORKDIR/ofs-common/src/common/lib/csr/ofs_fim_axi_csr_slave.sv +$WORKDIR/ofs-common/src/common/lib/bridges/axi_lite2mmio.sv +$WORKDIR/ofs-common/src/common/lib/bridges/axi_avl_st_bridge.sv +$WORKDIR/ofs-common/src/common/tag_remap/pcie_arb_local_commit.sv +$WORKDIR/ofs-common/src/common/lib/pfa/pfa_master.sv +$WORKDIR/ofs-common/src/common/lib/pfa/pfa_slave.sv +$WORKDIR/ofs-common/src/common/st2mm/st2mm_csr.sv +$WORKDIR/ofs-common/src/common/lib/bridges/avst_rx_mmio_bridge.sv +$WORKDIR/ofs-common/src/common/lib/bridges/avst_tx_mmio_bridge.sv +$WORKDIR/ofs-common/src/common/lib/bridges/avst_axil_bridge.sv +$WORKDIR/ofs-common/src/common/lib/bridges/axis_rx_mmio_bridge.sv +$WORKDIR/ofs-common/src/common/lib/bridges/axis_tx_mmio_bridge.sv +$WORKDIR/ofs-common/src/common/lib/bridges/axis_tx_msix_bridge.sv +$WORKDIR/ofs-common/src/common/lib/csr/axil_bridge_csr.sv +$WORKDIR/ofs-common/src/common/lib/csr/ofs_fim_avmm_csr_slave.sv +$WORKDIR/ofs-common/src/common/lib/csr/ofs_fim_axi_csr_slave.sv +$WORKDIR/ofs-common/src/common/lib/bridges/axis_axil_bridge.sv +$WORKDIR/ofs-common/src/common/lib/arbiter/fair_arbiter.sv +$WORKDIR/ofs-common/src/common/lib/mux/Nmux.sv +$WORKDIR/ofs-common/src/common/lib/mux/switch.sv +$WORKDIR/ofs-common/src/common/lib/mux/pf_vf_mux_top.sv +$WORKDIR/ofs-common/src/common/lib/mux/pcie_ss_axis_mux.sv +$WORKDIR/ofs-common/src/common/tag_remap/ofs_fim_tag_pool.sv +$WORKDIR/ofs-common/src/common/tag_remap/tag_remap.sv +$WORKDIR/ofs-common/src/common/lib/axis/axis_pipeline.sv +$WORKDIR/ofs-common/src/common/lib/axis/axis_register.sv +$WORKDIR/ipss/hssi/s10/includes/ofs_fim_eth_plat_if_pkg.sv +$WORKDIR/ipss/hssi/inc/ofs_fim_eth_if_pkg.sv +$WORKDIR/ofs-common/src/common/lib/bridges/axis_hssi_pr_freeze_bridge.sv +$WORKDIR/ofs-common/src/common/lib/bridges/axis_pcie_pr_freeze_bridge.sv +$WORKDIR/ofs-common/src/common/lib/axis/axis_tx_hssi_pipeline.sv +$WORKDIR/ofs-common/src/common/lib/axi/axi_read_register.sv +$WORKDIR/ofs-common/src/common/lib/axi/axi_write_register.sv +$WORKDIR/ofs-common/src/common/lib/axi/axi_register.sv +$WORKDIR/ofs-common/src/common/lib/avmm/avmm_if_reg.sv + +// HSSI ############################### +//$WORKDIR/ipss/d5005/eth/s10/includes/ofs_fim_eth_plat_if_pkg.sv +$WORKDIR/ipss/hssi/s10/lib/ofs_fim_eth_plat_clocks_noprune.sv +//$WORKDIR/ipss/d5005/eth/inc/ofs_fim_eth_if_pkg.sv +$WORKDIR/ipss/hssi/inc/ofs_fim_eth_if.sv +$WORKDIR/ipss/hssi/inc/ofs_fim_eth_avst_if_pkg.sv +$WORKDIR/ipss/hssi/inc/ofs_fim_eth_avst_if.sv +$WORKDIR/ipss/hssi/lib/bridge/ofs_fim_eth_afu_avst_to_fim_axis_bridge.sv +$WORKDIR/ipss/hssi/lib/bridge/ofs_fim_eth_sb_afu_avst_to_fim_axis_bridge.sv +$WORKDIR/ipss/hssi/lib/bridge/ofs_fim_eth_axis_connect.sv +$WORKDIR/ipss/hssi/lib/pipeline/pr_eth_axis_if_reg.sv +$WORKDIR/ipss/hssi/s10/hssi_csr_pkg.sv +$WORKDIR/ipss/hssi/s10/hssi_stats_sync.sv +$WORKDIR/ipss/hssi/s10/av_axi_st_bridge.sv +$WORKDIR/ipss/hssi/s10/altera_eth_10g_mac_base_r_wrap.sv +$WORKDIR/ipss/hssi/s10/resync.v +$WORKDIR/ipss/hssi/s10/mm_ctrl_xcvr.sv +$WORKDIR/ipss/hssi/s10/hssi_csr.sv +$WORKDIR/ipss/hssi/s10/eth_top.sv +$WORKDIR/ipss/hssi/s10/eth_ac_wrapper.sv + +// MEM ##################### +//$WORKDIR/ipss/d5005/mem/rtl/mc_ha_pkg.sv +//$WORKDIR/ipss/d5005/mem/rtl/ofs_fim_emif_if.sv +//$WORKDIR/ipss/d5005/mem/rtl/mc_emif_poison.sv +//$WORKDIR/ipss/d5005/mem/rtl/mc_rmw_shim.sv +//$WORKDIR/ipss/d5005/mem/rtl/mc_mmr_ctrl.sv +//$WORKDIR/ipss/d5005/mem/rtl/mc_channel.sv +//$WORKDIR/ipss/d5005/mem/rtl/mc_csr.sv +//$WORKDIR/ipss/d5005/mem/rtl/mc_top.sv +//$WORKDIR/ipss/d5005/mem/rtl/mem_intf.sv +//$WORKDIR/ipss/d5005/mem/qip/emif_8GB_2400/mem_wrapper.sv + +// EMIF ##################### + +$WORKDIR/ipss/mem/includes/ofs_fim_emif_afu_if.sv +$WORKDIR/ipss/mem/includes/ofs_fim_emif_cfg_pkg.sv +$WORKDIR/ipss/mem/includes/ofs_fim_emif_if.sv +$WORKDIR/ipss/mem/custom_altera_avalon_mm_bridge.sv +$WORKDIR/ipss/mem/mem_intf.sv +$WORKDIR/ipss/mem/ddr_avmm_bridge.v +$WORKDIR/ipss/mem/emif_csr.sv +$WORKDIR/ipss/mem/emif_top.sv +$WORKDIR/ipss/mem/pr_avalon_mem_if.sv +$WORKDIR/ipss/mem/avmm_chkr/avmm_chkr.sv + + + +// PCIE ############################## +$WORKDIR/ipss/pcie/rtl/ofs_fim_axis_if.sv +$WORKDIR/ipss/pcie/rtl/pcie_bridge.sv +$WORKDIR/ipss/pcie/rtl/pcie_bridge_cdc.sv +$WORKDIR/ipss/pcie/rtl/pcie_rx_bridge_cdc.sv +$WORKDIR/ipss/pcie/rtl/pcie_tx_bridge_cdc.sv +$WORKDIR/ipss/pcie/rtl/pcie_checker.sv +$WORKDIR/ipss/pcie/rtl/pipeline/axis_reg_pcie_txs.sv +$WORKDIR/ipss/pcie/rtl/pcie_rx_bridge_htile.sv +$WORKDIR/ipss/pcie/rtl/pcie_rx_bridge.sv +$WORKDIR/ipss/pcie/rtl/pcie_tx_bridge.sv +$WORKDIR/ipss/pcie/rtl/pcie_tx_bridge_htile.sv +$WORKDIR/ipss/pcie/rtl/pcie_rx_bridge_ptile.sv +$WORKDIR/ipss/pcie/rtl/pcie_tx_bridge_ptile.sv +$WORKDIR/ipss/pcie/rtl/pcie_csr.sv +$WORKDIR/ipss/pcie/rtl/pcie_flr_resync.sv +$WORKDIR/ipss/pcie/rtl/pcie_msix_resync.sv +$WORKDIR/ipss/pcie/rtl/pcie_tx_arbiter.sv +$WORKDIR/ipss/pcie/rtl/axi_s_adapter.sv +$WORKDIR/ipss/pcie/rtl/pcie_ch0_align_tx.sv +$WORKDIR/ipss/pcie/rtl/pcie_top.sv +$WORKDIR/ipss/pcie/rtl/pcie_wrapper.sv + +// SPI ############################################# +$WORKDIR/ipss/spi/spi_bridge_top.sv +$WORKDIR/ipss/spi/spi_bridge_csr.sv + +// FME ############################################# +$WORKDIR/ofs-common/src/common/fme/fme_csr_pkg.sv +$WORKDIR/ofs-common/src/common/fme/fme_csr_io_if.sv +$WORKDIR/ofs-common/src/common/fme/fme_csr.sv +$WORKDIR/ofs-common/src/common/fme/fme_top.sv + +// MSIX ############################### +$WORKDIR/src/interrupt/pcie_mux_top.sv +$WORKDIR/src/interrupt/fme_msix_table.sv +$WORKDIR/src/interrupt/msix_filter.sv +$WORKDIR/src/interrupt/msix_fme_bridge.sv +$WORKDIR/src/interrupt/msix_pba_update.sv +$WORKDIR/src/interrupt/msix_user_irq.sv +$WORKDIR/src/interrupt/msix_wrapper.sv +$WORKDIR/src/interrupt/msix_top.sv +$WORKDIR/src/interrupt/msix_csr.sv + +// AFU ############################### +$WORKDIR/ofs-common/src/common/protocol_checker/protocol_checker.sv +$WORKDIR/ofs-common/src/common/protocol_checker/prtcl_chkr_pkg.sv +$WORKDIR/ofs-common/src/common/protocol_checker/port_traffic_control.sv +$WORKDIR/ofs-common/src/common/protocol_checker/port_tx_fifo.sv +$WORKDIR/ofs-common/src/common/protocol_checker/protocol_checker_csr.sv +$WORKDIR/ofs-common/src/common/protocol_checker/afu_intf.sv +$WORKDIR/ofs-common/src/common/protocol_checker/tx_filter.sv +$WORKDIR/ofs-common/src/common/protocol_checker/mmio_handler.sv +$WORKDIR/src/afu_top/afu_top.sv + +// PORT GASKET ############################### +$WORKDIR/ofs-common/src/common/port_gasket/user_clock/includes/qph_user_clk_pkg.sv +$WORKDIR/ofs-common/src/fpga_family/stratix10/user_clock/user_clk/qph_user_clk.sv +$WORKDIR/ofs-common/src/common/port_gasket/user_clock/qph_user_clk_freq.sv +$WORKDIR/ofs-common/src/common/port_gasket/user_clock/qph_user_clk_rcfg_fsm.sv +$WORKDIR/ofs-common/src/common/port_gasket/user_clock/user_clock_resync.sv +$WORKDIR/ofs-common/src/fpga_family/stratix10/user_clock/user_clk/user_clock.sv +$WORKDIR/ofs-common/src/common/remote_stp/remote_stp_top.sv + +$WORKDIR/ofs-common/src/common/port_gasket/pr_pkg.sv +$WORKDIR/ofs-common/src/common/port_gasket/pg_csr_pkg.sv +$WORKDIR/ofs-common/src/common/port_gasket/pr_ctrl_if.sv +$WORKDIR/ofs-common/src/common/port_gasket/pr_ctrl.sv +$WORKDIR/ofs-common/src/common/port_gasket/pg_csr.sv +$WORKDIR/ofs-common/src/fpga_family/stratix10/port_gasket/pr_slot.sv + +$WORKDIR/ofs-common/src/common/port_gasket/port_reset_fsm.sv +$WORKDIR/ofs-common/src/fpga_family/stratix10/port_gasket/port_gasket.sv + +// HE HSSI ############################### +$WORKDIR/ofs-common/src/common/he_hssi/he_hssi_top.sv +$WORKDIR/ofs-common/src/common/he_hssi/common/eth_traffic_csr_pkg.sv +$WORKDIR/ofs-common/src/common/he_hssi/top_direct_green_bs/eth_traffic_pcie_tlp_to_csr.sv +$WORKDIR/ofs-common/src/common/he_hssi/top_direct_green_bs/pcie_tlp_to_csr_no_dma.sv +$WORKDIR/ofs-common/src/common/he_hssi/common/eth_traffic_csr.sv +$WORKDIR/ofs-common/src/common/he_hssi/common/multi_port_axi_traffic_ctrl.sv +$WORKDIR/ofs-common/src/common/he_hssi/common/multi_port_traffic_ctrl.sv +$WORKDIR/ofs-common/src/common/he_hssi/common/pulse_sync.sv +$WORKDIR/ofs-common/src/common/he_hssi/common/traffic_controller_wrapper.sv +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/eth_std_traffic_controller_top.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/avalon_st_loopback.sv +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/avalon_st_loopback_csr.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/avalon_st_gen.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/avalon_st_loopback.sv +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/avalon_st_loopback_csr.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/avalon_st_mon.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/avalon_st_prtmux.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/eth_std_traffic_controller_top.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/shiftreg_ctrl.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/shiftreg_data.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/crc32/avalon_st_to_crc_if_bridge.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/crc32/bit_endian_converter.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/crc32/byte_endian_converter.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/crc32/crc_checksum_aligner.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/crc32/crc_comparator.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/crc32/crc32_calculator.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/crc32/crc32_chk.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/crc32/crc32_gen.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/crc32/crc32_lib/crc_ethernet.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/crc32/crc32_lib/crc_register.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/crc32/crc32_lib/crc32_dat8.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/crc32/crc32_lib/crc32_dat16.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/crc32/crc32_lib/crc32_dat24.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/crc32/crc32_lib/crc32_dat32.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/crc32/crc32_lib/crc32_dat32_any_byte.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/crc32/crc32_lib/crc32_dat40.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/crc32/crc32_lib/crc32_dat48.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/crc32/crc32_lib/crc32_dat56.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/crc32/crc32_lib/crc32_dat64.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/crc32/crc32_lib/crc32_dat64_any_byte.v +$WORKDIR/ofs-common/src/common/he_hssi/eth_traffic_controller/crc32/crc32_lib/xor6.v +//#$WORKDIR/ofs-common/src/common/he_hssi/fifo_scfifo/ip/sc_fifo/sc_fifo_tx_sc_fifo/altera_avalon_sc_fifo_1920/sim/sc_fifo_tx_sc_fifo_altera_avalon_sc_fifo_1920_umfltxq.v +//#$WORKDIR/ofs-common/src/common/he_hssi/fifo_scfifo/ip/sc_fifo/sc_fifo_tx_sc_fifo/sim/sc_fifo_tx_sc_fifo.v +//#$WORKDIR/ofs-common/src/common/he_hssi/fifo_scfifo/ip/sc_fifo/sc_fifo_rx_sc_fifo/sim/sc_fifo_rx_sc_fifo.v +//#$WORKDIR/ofs-common/src/common/he_hssi/fifo_scfifo/sc_fifo/sim/sc_fifo.v + + +//TOP ##################### +$WORKDIR/ipss/pmci/pmci_top.sv +$WORKDIR/src/top/rst_ctrl.sv +$WORKDIR/src/top/iofs_top.sv + diff --git a/sim/scripts/vcs_filelist.sh b/sim/scripts/vcs_filelist.sh new file mode 100755 index 0000000..fb9e9f1 --- /dev/null +++ b/sim/scripts/vcs_filelist.sh @@ -0,0 +1,63 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +. $OFS_ROOTDIR/sim/scripts/ip_flist.sh + +# +cp -f $OFS_ROOTDIR/ofs-common/src/common/fme_id_rom/fme_id.mif ./ +# + +LIB_FILELIST="-v $QUARTUS_ROOTDIR/eda/sim_lib/altera_primitives.v \ +-v $QUARTUS_ROOTDIR/eda/sim_lib/220model.v \ +-v $QUARTUS_ROOTDIR/eda/sim_lib/sgate.v \ +-v $QUARTUS_ROOTDIR/eda/sim_lib/altera_mf.v \ +$QUARTUS_ROOTDIR/eda/sim_lib/altera_lnsim.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/fourteennm_atoms.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/synopsys/fourteennm_atoms_ncrypt.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/ct1_hssi_atoms.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/ct1_hssi_atoms_ncrypt.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/synopsys/cr3v0_serdes_models_ncrypt.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/ct1_hip_atoms.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/ct1_hip_atoms_ncrypt.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/ctp_hssi_atoms.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/ctp_hssi_atoms_ncrypt.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/cta_hssi_atoms.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/cta_hssi_atoms_ncrypt.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/ctab_hssi_atoms.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/ctab_hssi_atoms_ncrypt.sv" + +INC_DIR="+incdir+$OFS_ROOTDIR/ofs-common/src/common/includes/ \ ++incdir+$OFS_ROOTDIR/src/includes/ \ ++incdir+$OFS_ROOTDIR/ipss/eth/inc/" + + +PLAT_RTL_FILELIST="-f $OFS_ROOTDIR/sim/scripts/rtl_comb.f" + +RTL_FILELIST="$COMMON_RTL_FILELIST \ +$PLAT_RTL_FILELIST" + +VCS_FILELIST="$INC_DIR \ +$LIB_FILELIST \ +$QSYS_FILELIST \ +$RTL_FILELIST" + +if [ -z ${SIM_DIR} ]; +then + PIM_TEMPLATE_DIR=$OFS_ROOTDIR/sim/ip_libraries/pim_template +else + PIM_TEMPLATE_DIR=$SIM_DIR/sim/ip_libraries/pim_template +fi +echo "Setting for PIM_TEMPLATE_DIR=${PIM_TEMPLATE_DIR}" +PIM_PLATFORM_NAME=d5005 +PIM_INI_FILE=$OFS_ROOTDIR/src/top/ofs_d5005.ini +PIM_FLIST=$PIM_TEMPLATE_DIR/pim_source_files.list +AFU_FLIST=$OFS_ROOTDIR/sim/scripts/afu_flist.f + +# Configure a PIM-based AFU +# Construct the simulation build environment for the target AFU. A common +# script can be used for UVM and unit tests on all targets. The script +# will generate a simulator include file afu_with_pim/all_sim_files.list. +$OFS_ROOTDIR/ofs-common/scripts/common/sim/ofs_pim_sim_setup.sh -t "$PIM_TEMPLATE_DIR" -b "$PIM_PLATFORM_NAME" + +# Load AFU and PIM sources into simulation +BASE_AFU_SRC="-F $PIM_FLIST -F $AFU_FLIST" diff --git a/sim/scripts/ver_list.f b/sim/scripts/ver_list.f new file mode 100644 index 0000000..2982369 --- /dev/null +++ b/sim/scripts/ver_list.f @@ -0,0 +1,11 @@ ++incdir+$WORKDIR/sim/bfm +$WORKDIR/sim/bfm/test_utils.sv +$WORKDIR/sim/bfm/test_utils.sv +$WORKDIR/sim/bfm/test_pcie_utils.sv +$WORKDIR/sim/bfm/ready_gen.sv +$WORKDIR/sim/bfm/packet_sender.sv +$WORKDIR/sim/bfm/packet_receiver.sv +$WORKDIR/sim/bfm/shmem.sv +$WORKDIR/sim/bfm/pcie_flr.sv +$WORKDIR/sim/bfm/tester.sv +$WORKDIR/sim/bfm/top_tb.sv diff --git a/sim/unit_test/csr_test_sriov/msim_setup.sh b/sim/unit_test/csr_test_sriov/msim_setup.sh new file mode 100755 index 0000000..b617b8a --- /dev/null +++ b/sim/unit_test/csr_test_sriov/msim_setup.sh @@ -0,0 +1,113 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="-finish exit" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR="$TEST_SRC_DIR/../../.." +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="${TEST_DIR}/sim_msim" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for msim # +################################### +. ${SIM_DIR}/msim_filelist.sh + +################################## +### BFM related verilog source ### +################################## +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlib work +vlog -mfcu -timescale=1ns/1fs +libext+.v+.sv -lint -sv \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+HTILE \ + +define+R1_UNIT_TEST_ENV \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+MSIM_IOFS_D5005 \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $MSIM_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -work work -l msim_vlog.log -suppress 8386,7033,7061,2388,12003,2892 +#suppress 8386 : Replication operator in Conactenation Operator +#suppress 2892 : Net type of 'clk' was not explicitly declared +#suppress 7061 : Variable 'clear_tdo_bit_select' driven in an always_ff block, may not be driven by any other process +#suppress 7033 : Variable 'parser_result' driven in a combinational block, may not be driven by any other process + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + vopt $TOP_LEVEL_NAME -o opt -suppress 2732,12003,7033,3837 -l msim_vopt.log + vsim -c opt -nosva -suppress 2732,12003,7033,3837 -do "add log -r /*; run -all ; quit -f" +fi + + diff --git a/sim/unit_test/csr_test_sriov/readme.txt b/sim/unit_test/csr_test_sriov/readme.txt new file mode 100644 index 0000000..d395e08 --- /dev/null +++ b/sim/unit_test/csr_test_sriov/readme.txt @@ -0,0 +1,77 @@ +***Test Description*** +Following scenarios are covered in this test : + * test_afu_mmio – covered illegal AFU MMIO access returning all 0s + * test_mmio_addr32 – 32 bit Read/Write on FME and Port CSRs (includes access to unimplemented register space) + * test_mmio_addr64 – 64 bit Read/Write on FME and Port CSRs (includes access to unimplemented register space) + * test_vf2_flr_reset – VF2 Reset Scenario + * test_vf1_flr_reset – VF1 Reset Scenario + * test_vf0_flr_reset – VF0 Reset Scenario + * test_pf0_flr_reset – PF0 FLR reset scenario + + +Description of test modules: + * testbench/test_csr_defs.sv - Defines CSR addresses. + * testbench/tester_tests.sv - Defines all the test cases for current test. + * script/Makefile_VCS.mk - Script to run the test in VCS only + * script/Makefile.mk - Script to run the test in VCS & Questasim. MSIM_D5005=1 option to be given for Questasim else will be for VCS. + +***Running the test*** +To run the test in VCS: + 1) Make sure the shell environment is set up to run VCS/VCSMX. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Synopsys VCS simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_vcs + dve -full64 -vpd vcdplus.vpd & + +To run the test in QuestaSim: + 1) Make sure the shell environment is set up to run Questasim. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Mentor Graphics QuestaSim simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh MSIM=1 + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_msim + vsim -view vsim.wlf & diff --git a/sim/unit_test/csr_test_sriov/scripts/.synopsys_dve_serverport.txt b/sim/unit_test/csr_test_sriov/scripts/.synopsys_dve_serverport.txt new file mode 100644 index 0000000..a8996b4 --- /dev/null +++ b/sim/unit_test/csr_test_sriov/scripts/.synopsys_dve_serverport.txt @@ -0,0 +1 @@ +{{scc330082} {41221}} \ No newline at end of file diff --git a/sim/unit_test/csr_test_sriov/scripts/run_sim.sh b/sim/unit_test/csr_test_sriov/scripts/run_sim.sh new file mode 100755 index 0000000..271afc5 --- /dev/null +++ b/sim/unit_test/csr_test_sriov/scripts/run_sim.sh @@ -0,0 +1,48 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)/.." + + +VCSMX=0 +MSIM=0 +SKIP_IP_CMP=0 +TEST_DIR=$(pwd) + +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh run_sim.sh SKIP_IP_CMP=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +# Source common sim setup script + +. ${TEST_DIR}/../../scripts/sim_setup_common.sh TEST_DIR="$TEST_DIR" VCSMX=$VCSMX MSIM=$MSIM + +# Run simulation +if [ $VCSMX -eq 1 ]; then + echo "Running VCSMX simulation in $TEST_DIR/sim_vcsmx" + cd ${TEST_DIR}/sim_vcsmx && sh ${TEST_SRC_DIR}/vcsmx_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +elif [ $MSIM -eq 1 ]; then + echo "Running Questasim simulation in $TEST_DIR/sim_msim" + cd ${TEST_DIR}/sim_msim && sh ${TEST_SRC_DIR}/msim_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="-l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="" +else + echo "Running VCS simulation in $TEST_DIR/sim_vcs" + cd ${TEST_DIR}/sim_vcs && sh ${TEST_SRC_DIR}/vcs_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +fi + + diff --git a/sim/unit_test/csr_test_sriov/scripts/test_list.f b/sim/unit_test/csr_test_sriov/scripts/test_list.f new file mode 100644 index 0000000..6c421a3 --- /dev/null +++ b/sim/unit_test/csr_test_sriov/scripts/test_list.f @@ -0,0 +1 @@ +$WORKDIR/sim/unit_test/csr_test_sriov/testbench/test_csr_defs.sv diff --git a/sim/unit_test/csr_test_sriov/testbench/test_csr_defs.sv b/sim/unit_test/csr_test_sriov/testbench/test_csr_defs.sv new file mode 100644 index 0000000..40c9025 --- /dev/null +++ b/sim/unit_test/csr_test_sriov/testbench/test_csr_defs.sv @@ -0,0 +1,90 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// CSR addresses are defined for the testcase. +// +//----------------------------------------------------------------------------- +`ifndef __TEST_CSR_DEFS__ +`define __TEST_CSR_DEFS__ + +package test_csr_defs; + localparam FME_DFH = 32'h0; + localparam FME_SCRATCHPAD0 = FME_DFH + 32'h28; + + localparam PMCI_DFH = 32'h10000; + localparam PMCI_SCRATCHPAD = PMCI_DFH + 32'h28; + + localparam PCIE_DFH = 32'h20000; + localparam PCIE_SCRATCHPAD = PCIE_DFH + 32'h8; + + localparam ST2MM_DFH = 32'h80000; + localparam ST2MM_SCRATCHPAD = ST2MM_DFH + 32'h8; + + localparam PGSK_DFH = 32'h90000; + localparam PGSK_SCRATCHPAD = PGSK_DFH + 32'hb8; + + localparam HSSI_DFH = 32'h30000; + localparam HSSI_SCRATCHPAD = HSSI_DFH + 32'h38; + + localparam HE_LB_DFH = 32'h00000; + localparam HE_LB_SCRATCHPAD = HE_LB_DFH + 32'h100; + + localparam HE_HSSI_SCRATCHPAD = HE_LB_DFH + 32'h48; + + localparam PORT_CONTROL = 32'h91038; + localparam PORT_SCRATCHPAD0 = 32'h91028; //CHECK THIS + + localparam EMIF_DFH = 32'h40000; + localparam PCIE_DFH_VALUE = 64'h3000000010000020; +// localparam EMIF_DFH_VALUE = 64'h3000000010000009; + localparam EMIF_DFH_VALUE = 64'h3000000500000009; + localparam HSSI_DFH_VALUE = 64'h300000001000100f; + localparam USER_CLK_DFH_VALUE = 64'h3000000010000014; //Modified as per R1 + localparam SPI_DFH = 32'h43000; + localparam SPI_DFH_VALUE = 64'h300001000000000e; + localparam SPI_WRITEDATA = 32'h43020; + localparam HSSI_RCFG_DATA = 32'h42030; + localparam VFME_AFU_ID_L = 32'h8; + localparam VFME_AFU_ID_L_VALUE = 64'hBEE40B2B259849A9; + localparam VFME_AFU_ID_H = 32'h10; + localparam VFME_AFU_ID_H_VALUE = 64'hA8E434048329FE10; + localparam VFME_MSIX_VADDR0 = 32'h3000; + localparam USER_CLK_DFH = 32'h92000; + localparam USER_CLK_CMD_0 = 32'h20008; + + localparam USER_IRQ0_ADDR = 64'h20000; + localparam USER_IRQ1_ADDR = 64'h21000; + localparam USER_IRQ2_ADDR = 64'h22000; + localparam USER_IRQ3_ADDR = 64'h23000; + localparam USER_IRQ4_ADDR = 64'h24000; + localparam USER_IRQ5_ADDR = 64'h25000; + localparam USER_IRQ6_ADDR = 64'h26000; + + localparam USER_IRQ0_DATA = 32'hbeef_0000; + localparam USER_IRQ1_DATA = 32'hbeef_0001; + localparam USER_IRQ2_DATA = 32'hbeef_0002; + localparam USER_IRQ3_DATA = 32'hbeef_0003; + localparam USER_IRQ4_DATA = 32'hbeef_0004; + localparam USER_IRQ5_DATA = 32'hbeef_0005; + localparam USER_IRQ6_DATA = 32'hbeef_0006; +/* + localparam PCIE_DFH = 32'h10000; + localparam PCIE_SCRATCHPAD = PCIE_DFH + 32'h8; + localparam PCIE_TESTPAD = PCIE_DFH + 32'h38; + + localparam HE_LB_SCRATCHPAD = 32'h100; + + localparam HSSI_DFH = 32'h60000; + localparam HSSI_RCFG_DATA = HSSI_DFH + 32'h30; + + //localparam USER_CLK_DFH = 32'h20000; + //localparam USER_CLK_CMD_0 = 32'h20008; + +*/ + +endpackage + +`endif diff --git a/sim/unit_test/csr_test_sriov/testbench/tester_tests.sv b/sim/unit_test/csr_test_sriov/testbench/tester_tests.sv new file mode 100755 index 0000000..848ac25 --- /dev/null +++ b/sim/unit_test/csr_test_sriov/testbench/tester_tests.sv @@ -0,0 +1,934 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// This file defines all the test cases for current test. +// +// main_test() is the main entry function which the tester calls +// to execute the unit tests. +// +//----------------------------------------------------------------------------- + +import test_csr_defs::*; +import ofs_fim_pcie_pkg::*; + +//------------------- +// Test utilities +//------------------- +task incr_test_id; +begin + test_id = test_id + 1; +end +endtask + +task post_test_util; + input logic [31:0] old_test_err_count; + logic result; +begin + if (test_utils::get_err_count() > old_test_err_count) begin + result = 1'b0; + end else begin + result = 1'b1; + end + + repeat (10) + @(posedge avl_clk); + + @(posedge avl_clk); + reset_test = 1'b1; + repeat (5) + @(posedge avl_clk); + reset_test = 1'b0; + + f_reset_tag(); + + if (result) begin + $display("\nTest status: OK"); + test_summary[test_id].result = 1'b1; + end else begin + $display("\nTest status: FAILED"); + test_summary[test_id].result = 1'b0; + end + incr_test_id(); +end +endtask + +task print_test_header; + input [1024*8-1:0] test_name; +begin + $display("\n********************************************"); + $display(" Running TEST(%0d) : %0s", test_id, test_name); + $display("********************************************"); + test_summary[test_id].name = test_name; +end +endtask + +task verify_pcie_err_count; + output logic result; + input logic [7:0] exp_err; +begin + // Wait 30 clock cycles for checker error to be logged + repeat (30) + @(posedge fim_clk); + + if (checker_err_count != exp_err) + begin + result = 1'b0; + $display("Failed - expected errors: %0d, actual errors: %0d", exp_err, checker_err_count); + end else begin + result = 1'b1; + $display("Checker error count matches: %0d", checker_err_count); + end + if (~result) + test_utils::incr_err_count(); +end +endtask + +task verify_pcie_err_code; + output logic result; + input logic [31:0] exp_err_code; +begin + // Wait 10 clock cycles for checker error to be logged + repeat (10) + @(posedge fim_clk); + + if (pcie_p2c_chk_err_code != exp_err_code) + begin + result = 1'b0; + $display("Failed - error code mismatch, expected: 0x%x, actual: 0x%x", exp_err_code, pcie_p2c_chk_err_code); + end else begin + result = 1'b1; + $display("Checker error code matches: 0x%x", pcie_p2c_chk_err_code); + end + if (~result) + test_utils::incr_err_count(); +end +endtask + +task verify_mmio_err_count; + output logic result; + input logic [7:0] exp_err; +begin + // Wait 30 clock cycles for checker error to be logged + repeat (30) + @(posedge fim_clk); + + if (mmio_err_count != exp_err) + begin + result = 1'b0; + $display("Failed - expected errors: %0d, actual errors: %0d", exp_err, mmio_err_count); + end else begin + result = 1'b1; + $display("MMIO error count matches: %0d", mmio_err_count); + end + if (~result) + test_utils::incr_err_count(); +end +endtask + +task verify_mmio_err_code; + output logic result; + input logic [255:0][3:0] exp_err_code; + logic [31:0] scratch; + logic error; +begin + // Wait 10 clock cycles for checker error to be logged + repeat (10) + @(posedge fim_clk); + + result = 1'b1; + + for (int i=0; i/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcs" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +# source ${SIM_ROOTDIR}/d5005/unit_test/scripts/vcs_filelist.sh +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vcs -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + +define+R1_UNIT_TEST_ENV \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $VCS_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -top $TOP_LEVEL_NAME +error+20 -l vcs.log + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/csr_test_sriov/vcsmx_setup.sh b/sim/unit_test/csr_test_sriov/vcsmx_setup.sh new file mode 100755 index 0000000..56bde7f --- /dev/null +++ b/sim/unit_test/csr_test_sriov/vcsmx_setup.sh @@ -0,0 +1,115 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcsmx" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +# source ${SIM_ROOTDIR}/d5005/unit_test/scripts/vcs_filelist.sh +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlogan -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + +define+R1_UNIT_TEST_ENV \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $INC_DIR \ + $RTL_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC +error+1 -l vlog.log + +vcs -full64 -ntb_opts -licqueue +vcs+lic+wait \ + +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -l vcs.log $TOP_LEVEL_NAME + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/ddr_csr_test/msim_setup.sh b/sim/unit_test/ddr_csr_test/msim_setup.sh new file mode 100755 index 0000000..b617b8a --- /dev/null +++ b/sim/unit_test/ddr_csr_test/msim_setup.sh @@ -0,0 +1,113 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="-finish exit" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR="$TEST_SRC_DIR/../../.." +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="${TEST_DIR}/sim_msim" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for msim # +################################### +. ${SIM_DIR}/msim_filelist.sh + +################################## +### BFM related verilog source ### +################################## +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlib work +vlog -mfcu -timescale=1ns/1fs +libext+.v+.sv -lint -sv \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+HTILE \ + +define+R1_UNIT_TEST_ENV \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+MSIM_IOFS_D5005 \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $MSIM_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -work work -l msim_vlog.log -suppress 8386,7033,7061,2388,12003,2892 +#suppress 8386 : Replication operator in Conactenation Operator +#suppress 2892 : Net type of 'clk' was not explicitly declared +#suppress 7061 : Variable 'clear_tdo_bit_select' driven in an always_ff block, may not be driven by any other process +#suppress 7033 : Variable 'parser_result' driven in a combinational block, may not be driven by any other process + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + vopt $TOP_LEVEL_NAME -o opt -suppress 2732,12003,7033,3837 -l msim_vopt.log + vsim -c opt -nosva -suppress 2732,12003,7033,3837 -do "add log -r /*; run -all ; quit -f" +fi + + diff --git a/sim/unit_test/ddr_csr_test/readme.txt b/sim/unit_test/ddr_csr_test/readme.txt new file mode 100644 index 0000000..1ca6f35 --- /dev/null +++ b/sim/unit_test/ddr_csr_test/readme.txt @@ -0,0 +1,72 @@ +***Test Description*** +This is the unit test for EMIF CSR Registers access + +It covers the following test scenarios: + * MMIO read 32-bit address and 64-bit address (EMIF_CSR) + +Description of test modules: + * test_csr_defs.sv - Defines CSR addresses. + * tester_tests.sv - Defines all the test cases for current test. + * script/Makefile_VCS.mk - Script to run the test in VCS only + * script/Makefile.mk - Script to run the test in VCS & Questasim. MSIM_D5005=1 option to be given for Questasim else will be for VCS. + +***Running the test*** +To run the test in VCS: + 1) Make sure the shell environment is set up to run VCS/VCSMX. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Synopsys VCS simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_vcs + dve -full64 -vpd vcdplus.vpd & + +To run the test in QuestaSim: + 1) Make sure the shell environment is set up to run Questasim. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Mentor Graphics QuestaSim simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh MSIM=1 + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_msim + vsim -view vsim.wlf & diff --git a/sim/unit_test/ddr_csr_test/scripts/run_sim.sh b/sim/unit_test/ddr_csr_test/scripts/run_sim.sh new file mode 100755 index 0000000..271afc5 --- /dev/null +++ b/sim/unit_test/ddr_csr_test/scripts/run_sim.sh @@ -0,0 +1,48 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)/.." + + +VCSMX=0 +MSIM=0 +SKIP_IP_CMP=0 +TEST_DIR=$(pwd) + +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh run_sim.sh SKIP_IP_CMP=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +# Source common sim setup script + +. ${TEST_DIR}/../../scripts/sim_setup_common.sh TEST_DIR="$TEST_DIR" VCSMX=$VCSMX MSIM=$MSIM + +# Run simulation +if [ $VCSMX -eq 1 ]; then + echo "Running VCSMX simulation in $TEST_DIR/sim_vcsmx" + cd ${TEST_DIR}/sim_vcsmx && sh ${TEST_SRC_DIR}/vcsmx_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +elif [ $MSIM -eq 1 ]; then + echo "Running Questasim simulation in $TEST_DIR/sim_msim" + cd ${TEST_DIR}/sim_msim && sh ${TEST_SRC_DIR}/msim_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="-l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="" +else + echo "Running VCS simulation in $TEST_DIR/sim_vcs" + cd ${TEST_DIR}/sim_vcs && sh ${TEST_SRC_DIR}/vcs_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +fi + + diff --git a/sim/unit_test/ddr_csr_test/scripts/test_list.f b/sim/unit_test/ddr_csr_test/scripts/test_list.f new file mode 100644 index 0000000..1c023cf --- /dev/null +++ b/sim/unit_test/ddr_csr_test/scripts/test_list.f @@ -0,0 +1 @@ +$WORKDIR/sim/unit_test/ddr_csr_test/testbench/test_csr_defs.sv diff --git a/sim/unit_test/ddr_csr_test/testbench/test_csr_defs.sv b/sim/unit_test/ddr_csr_test/testbench/test_csr_defs.sv new file mode 100644 index 0000000..c4613af --- /dev/null +++ b/sim/unit_test/ddr_csr_test/testbench/test_csr_defs.sv @@ -0,0 +1,97 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// CSR addresses are defined for the testcase. +// +//----------------------------------------------------------------------------- +`ifndef __TEST_CSR_DEFS__ +`define __TEST_CSR_DEFS__ + +package test_csr_defs; + localparam FME_DFH = 32'h0; + localparam FME_SCRATCHPAD0 = FME_DFH + 32'h28; + + localparam PMCI_DFH = 32'h10000; + localparam PMCI_SCRATCHPAD = PMCI_DFH + 32'h28; + + localparam PCIE_DFH = 32'h20000; + localparam PCIE_SCRATCHPAD = PCIE_DFH + 32'h8; + + localparam ST2MM_DFH = 32'h80000; + localparam ST2MM_SCRATCHPAD = ST2MM_DFH + 32'h8; + + localparam PGSK_DFH = 32'h90000; + localparam PGSK_SCRATCHPAD = PGSK_DFH + 32'hb8; + + localparam HSSI_DFH = 32'h30000; + localparam HSSI_SCRATCHPAD = HSSI_DFH + 32'h38; + + localparam HE_LB_DFH = 32'h00000; + localparam HE_LB_SCRATCHPAD = HE_LB_DFH + 32'h100; + + localparam HE_HSSI_SCRATCHPAD = HE_LB_DFH + 32'h48; + + localparam PORT_CONTROL = 32'h91038; + + localparam EMIF_DFH = 32'h40000; //old = 32'h41000 + localparam EMIF_STAT = 32'h40008; //old = 32'h41008 + localparam EMIF_CTRL = 32'h40010; //old = 32'h41010 + localparam PCIE_DFH_VALUE = 64'h3000000010000020; + localparam EMIF_DFH_VALUE = 64'h3000000500000009; //old = 64'h3000000010000009 + localparam HSSI_DFH_VALUE = 64'h300000001000100f; + localparam USER_CLK_DFH_VALUE = 64'h3000010000000014; + localparam SPI_DFH = 32'h43000; + localparam SPI_DFH_VALUE = 64'h300001000000000e; + localparam SPI_WRITEDATA = 32'h43020; + localparam HSSI_RCFG_DATA = 32'h42030; + localparam VFME_AFU_ID_L = 32'h8; + localparam VFME_AFU_ID_L_VALUE = 64'hBEE40B2B259849A9; + localparam VFME_AFU_ID_H = 32'h10; + localparam VFME_AFU_ID_H_VALUE = 64'hA8E434048329FE10; + localparam VFME_MSIX_VADDR0 = 32'h3000; + localparam USER_CLK_DFH = 32'h20000; + localparam USER_CLK_CMD_0 = 32'h20008; + + localparam USER_IRQ0_ADDR = 64'h20000; + localparam USER_IRQ1_ADDR = 64'h21000; + localparam USER_IRQ2_ADDR = 64'h22000; + localparam USER_IRQ3_ADDR = 64'h23000; + localparam USER_IRQ4_ADDR = 64'h24000; + localparam USER_IRQ5_ADDR = 64'h25000; + localparam USER_IRQ6_ADDR = 64'h26000; + + localparam USER_IRQ0_DATA = 32'hbeef_0000; + localparam USER_IRQ1_DATA = 32'hbeef_0001; + localparam USER_IRQ2_DATA = 32'hbeef_0002; + localparam USER_IRQ3_DATA = 32'hbeef_0003; + localparam USER_IRQ4_DATA = 32'hbeef_0004; + localparam USER_IRQ5_DATA = 32'hbeef_0005; + localparam USER_IRQ6_DATA = 32'hbeef_0006; + + //Added for PCIE_CSR_TEST + localparam PCIE0_ERROR = 32'h4020; + localparam PCIE_STAT = 32'h40010; + localparam PCIE_ERROR_MASK = 32'h40018; + localparam PCIE_ERROR = 32'h40020; + localparam PCIE_UNUSED_OFFSET = 32'h40ff8; +/* + localparam PCIE_DFH = 32'h10000; + localparam PCIE_SCRATCHPAD = PCIE_DFH + 32'h8; + localparam PCIE_TESTPAD = PCIE_DFH + 32'h38; + + localparam HE_LB_SCRATCHPAD = 32'h100; + + localparam HSSI_DFH = 32'h60000; + localparam HSSI_RCFG_DATA = HSSI_DFH + 32'h30; + + //localparam USER_CLK_DFH = 32'h20000; + //localparam USER_CLK_CMD_0 = 32'h20008; + +*/ + +endpackage + +`endif diff --git a/sim/unit_test/ddr_csr_test/testbench/tester_tests.sv b/sim/unit_test/ddr_csr_test/testbench/tester_tests.sv new file mode 100755 index 0000000..2bf4129 --- /dev/null +++ b/sim/unit_test/ddr_csr_test/testbench/tester_tests.sv @@ -0,0 +1,308 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// This file defines all the test cases for current test. +// +// main_test() is the main entry function which the tester calls +// to execute the unit tests. +// +//----------------------------------------------------------------------------- + +//------------------- +// Test utilities +//------------------- +task incr_test_id; +begin + test_id = test_id + 1; +end +endtask + +task post_test_util; + input logic result; +begin + repeat (10) + @(posedge avl_clk); + + @(posedge avl_clk); + reset_test = 1'b1; + repeat (5) + @(posedge avl_clk); + reset_test = 1'b0; + + f_reset_tag(); + + if (result) begin + $display("\nTest status: OK"); + test_summary[test_id].result = 1'b1; + end else begin + $display("\nTest status: FAILED"); + test_summary[test_id].result = 1'b0; + end + incr_test_id(); +end +endtask + +task print_test_header; + input [1024*8-1:0] test_name; +begin + $display("\n********************************************"); + $display(" Running TEST(%0d) : %0s", test_id, test_name); + $display("********************************************"); + test_summary[test_id].name = test_name; +end +endtask + +task verify_pcie_err_count; + output logic result; + input logic [7:0] exp_err; +begin + // Wait 30 clock cycles for checker error to be logged + repeat (30) + @(posedge fim_clk); + + if (checker_err_count != exp_err) + begin + result = 1'b0; + $display("Failed - expected errors: %0d, actual errors: %0d", exp_err, checker_err_count); + end else begin + result = 1'b1; + $display("Checker error count matches: %0d", checker_err_count); + end + if (~result) + test_utils::incr_err_count(); +end +endtask + +task verify_pcie_err_code; + output logic result; + input logic [31:0] exp_err_code; +begin + // Wait 10 clock cycles for checker error to be logged + repeat (10) + @(posedge fim_clk); + + if (pcie_p2c_chk_err_code != exp_err_code) + begin + result = 1'b0; + $display("Failed - error code mismatch, expected: 0x%x, actual: 0x%x", exp_err_code, pcie_p2c_chk_err_code); + end else begin + result = 1'b1; + $display("Checker error code matches: 0x%x", pcie_p2c_chk_err_code); + end + if (~result) + test_utils::incr_err_count(); +end +endtask + +task verify_mmio_err_count; + output logic result; + input logic [7:0] exp_err; +begin + // Wait 30 clock cycles for checker error to be logged + repeat (30) + @(posedge fim_clk); + + if (mmio_err_count != exp_err) + begin + result = 1'b0; + $display("Failed - expected errors: %0d, actual errors: %0d", exp_err, mmio_err_count); + end else begin + result = 1'b1; + $display("MMIO error count matches: %0d", mmio_err_count); + end + if (~result) + test_utils::incr_err_count(); +end +endtask + +task verify_mmio_err_code; + output logic result; + input logic [255:0][3:0] exp_err_code; +begin + // Wait 10 clock cycles for checker error to be logged + repeat (10) + @(posedge fim_clk); + + for (int i=0; i/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcs" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +# source ${SIM_ROOTDIR}/d5005/unit_test/scripts/vcs_filelist.sh +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vcs -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $VCS_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -top $TOP_LEVEL_NAME +error+20 -l vcs.log + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/ddr_csr_test/vcsmx_setup.sh b/sim/unit_test/ddr_csr_test/vcsmx_setup.sh new file mode 100755 index 0000000..383db68 --- /dev/null +++ b/sim/unit_test/ddr_csr_test/vcsmx_setup.sh @@ -0,0 +1,114 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcsmx" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +# source ${SIM_ROOTDIR}/d5005/unit_test/scripts/vcs_filelist.sh +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlogan -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $INC_DIR \ + $RTL_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC +error+1 -l vlog.log + +vcs -full64 -ntb_opts -licqueue +vcs+lic+wait \ + +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -l vcs.log $TOP_LEVEL_NAME + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/dfh_walker/msim_setup.sh b/sim/unit_test/dfh_walker/msim_setup.sh new file mode 100755 index 0000000..b617b8a --- /dev/null +++ b/sim/unit_test/dfh_walker/msim_setup.sh @@ -0,0 +1,113 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="-finish exit" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR="$TEST_SRC_DIR/../../.." +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="${TEST_DIR}/sim_msim" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for msim # +################################### +. ${SIM_DIR}/msim_filelist.sh + +################################## +### BFM related verilog source ### +################################## +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlib work +vlog -mfcu -timescale=1ns/1fs +libext+.v+.sv -lint -sv \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+HTILE \ + +define+R1_UNIT_TEST_ENV \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+MSIM_IOFS_D5005 \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $MSIM_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -work work -l msim_vlog.log -suppress 8386,7033,7061,2388,12003,2892 +#suppress 8386 : Replication operator in Conactenation Operator +#suppress 2892 : Net type of 'clk' was not explicitly declared +#suppress 7061 : Variable 'clear_tdo_bit_select' driven in an always_ff block, may not be driven by any other process +#suppress 7033 : Variable 'parser_result' driven in a combinational block, may not be driven by any other process + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + vopt $TOP_LEVEL_NAME -o opt -suppress 2732,12003,7033,3837 -l msim_vopt.log + vsim -c opt -nosva -suppress 2732,12003,7033,3837 -do "add log -r /*; run -all ; quit -f" +fi + + diff --git a/sim/unit_test/dfh_walker/readme.txt b/sim/unit_test/dfh_walker/readme.txt new file mode 100644 index 0000000..3423a5b --- /dev/null +++ b/sim/unit_test/dfh_walker/readme.txt @@ -0,0 +1,85 @@ +***Test Description*** +This is the unit test for DFH walking scenario covering below DFHs: + * FME_DFH + * THERM_MNGM_DFH + * GLBL_PERF_DFH + * GLBL_ERROR_DFH + * SPI_DFH + * PCIE_DFH + * HSSI_DFH + * EMIF_DFH + * FME_PR_DFH + * PORT_DFH + * USER_CLOCK_DFH + * PORT_STP_DFH + * AFU_INTF_DFH + +It covers the following test scenarios: + * 64 bit MMIO read is done on all DFH registers until end of the list (EOL=1) is achieved + +Description of test modules: + * testbench/test_csr_defs.sv - Defines CSR addresses. + * testbench/tester_tests.sv - Defines all the test cases for current test. + * script/Makefile_VCS.mk - Script to run the test in VCS only + * script/Makefile.mk - Script to run the test in VCS & Questasim. MSIM_D5005=1 option to be given for Questasim else will be for VCS. + +***Running the test*** +To run the test in VCS: + 1) Make sure the shell environment is set up to run VCS/VCSMX. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Synopsys VCS simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_vcs + dve -full64 -vpd vcdplus.vpd & + +To run the test in QuestaSim: + 1) Make sure the shell environment is set up to run Questasim. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Mentor Graphics QuestaSim simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh MSIM=1 + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_msim + vsim -view vsim.wlf & diff --git a/sim/unit_test/dfh_walker/scripts/run_sim.sh b/sim/unit_test/dfh_walker/scripts/run_sim.sh new file mode 100755 index 0000000..271afc5 --- /dev/null +++ b/sim/unit_test/dfh_walker/scripts/run_sim.sh @@ -0,0 +1,48 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)/.." + + +VCSMX=0 +MSIM=0 +SKIP_IP_CMP=0 +TEST_DIR=$(pwd) + +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh run_sim.sh SKIP_IP_CMP=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +# Source common sim setup script + +. ${TEST_DIR}/../../scripts/sim_setup_common.sh TEST_DIR="$TEST_DIR" VCSMX=$VCSMX MSIM=$MSIM + +# Run simulation +if [ $VCSMX -eq 1 ]; then + echo "Running VCSMX simulation in $TEST_DIR/sim_vcsmx" + cd ${TEST_DIR}/sim_vcsmx && sh ${TEST_SRC_DIR}/vcsmx_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +elif [ $MSIM -eq 1 ]; then + echo "Running Questasim simulation in $TEST_DIR/sim_msim" + cd ${TEST_DIR}/sim_msim && sh ${TEST_SRC_DIR}/msim_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="-l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="" +else + echo "Running VCS simulation in $TEST_DIR/sim_vcs" + cd ${TEST_DIR}/sim_vcs && sh ${TEST_SRC_DIR}/vcs_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +fi + + diff --git a/sim/unit_test/dfh_walker/scripts/test_list.f b/sim/unit_test/dfh_walker/scripts/test_list.f new file mode 100644 index 0000000..300ecd0 --- /dev/null +++ b/sim/unit_test/dfh_walker/scripts/test_list.f @@ -0,0 +1 @@ +$WORKDIR/sim/unit_test/dfh_walker/testbench/test_csr_defs.sv diff --git a/sim/unit_test/dfh_walker/testbench/test_csr_defs.sv b/sim/unit_test/dfh_walker/testbench/test_csr_defs.sv new file mode 100644 index 0000000..41ce902 --- /dev/null +++ b/sim/unit_test/dfh_walker/testbench/test_csr_defs.sv @@ -0,0 +1,102 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// CSR addresses are defined for the testcase. +// +//----------------------------------------------------------------------------- +`ifndef __TEST_CSR_DEFS__ +`define __TEST_CSR_DEFS__ + +package test_csr_defs; + +typedef struct packed { + logic [3:0] feat_type; + logic [7:0] rsvd1; + logic [3:0] afu_minor_ver; + logic [6:0] rsvd0; + logic eol; + logic [23:0] nxt_dfh_offset; + logic [3:0] afu_major_ver; + logic [11:0] feat_id; + } t_dfh; + + typedef enum { + FME_DFH_IDX, + THERM_MNGM_DFH_IDX, + GLBL_PERF_DFH_IDX, + GLBL_ERROR_DFH_IDX, + SPI_DFH_IDX, + PCIE_DFH_IDX, + HSSI_DFH_IDX, + EMIF_DFH_IDX, + FME_PR_DFH_IDX, + PORT_DFH_IDX, + USER_CLOCK_DFH_IDX, + PORT_STP_DFH_IDX, + AFU_INTF_DFH_IDX, + MAX_FME_DFH_IDX + } t_fme_dfh_idx; + +// typedef enum { +// PORT_DFH_IDX, +// PORT_ERROR_DFH_IDX, +// PORT_UINT_DFH_IDX, +// PORT_STP_DFH_IDX, +// USER_CLK_DFH_IDX, +// MAX_PORT_DFH_IDX +// } t_port_dfh_idx; + + typedef logic [8*100-1:0] dfh_name; + + localparam FME_BAR = 3'h0; + localparam FME_DFH_START_OFFSET = 32'h0; + + localparam PORT_BAR = 3'h2; + localparam PORT_DFH_START_OFFSET = 32'h0; + + function automatic dfh_name[MAX_FME_DFH_IDX-1:0] get_fme_dfh_names(); + dfh_name[MAX_FME_DFH_IDX-1:0] fme_dfh_names; + + fme_dfh_names[FME_DFH_IDX] = "FME_DFH"; + fme_dfh_names[THERM_MNGM_DFH_IDX] = "THERM_MNGM_DFH"; + fme_dfh_names[GLBL_PERF_DFH_IDX] = "GLBL_PERF_DFH"; + fme_dfh_names[GLBL_ERROR_DFH_IDX] = "GLBL_ERROR_DFH"; + fme_dfh_names[SPI_DFH_IDX] = "SPI_DFH"; + fme_dfh_names[PCIE_DFH_IDX] = "PCIE_DFH"; + fme_dfh_names[HSSI_DFH_IDX] = "HSSI_DFH"; + fme_dfh_names[EMIF_DFH_IDX] = "EMIF_DFH"; + fme_dfh_names[FME_PR_DFH_IDX] = "FME_PR_DFH"; + fme_dfh_names[PORT_DFH_IDX] = "PORT_DFH"; + fme_dfh_names[USER_CLOCK_DFH_IDX] = "USER_CLOCK_DFH"; + fme_dfh_names[PORT_STP_DFH_IDX] = "PORT_STP_DFH"; + fme_dfh_names[AFU_INTF_DFH_IDX] = "AFU_INTF_DFH"; + + return fme_dfh_names; + endfunction + + function automatic [MAX_FME_DFH_IDX-1:0][63:0] get_fme_dfh_values(); + logic[MAX_FME_DFH_IDX-1:0][63:0] fme_dfh_values; + + fme_dfh_values[FME_DFH_IDX] = 64'h4000_0000_1000_0000; + fme_dfh_values[THERM_MNGM_DFH_IDX] = 64'h3_00000_002000_0001; + fme_dfh_values[GLBL_PERF_DFH_IDX] = 64'h3_00000_001000_0007; + fme_dfh_values[GLBL_ERROR_DFH_IDX] = 64'h3_00000_00C000_1004; + fme_dfh_values[SPI_DFH_IDX] = 64'h3_00000_010000_000e; + fme_dfh_values[PCIE_DFH_IDX] = 64'h3_00000_010000_0020; + fme_dfh_values[HSSI_DFH_IDX] = 64'h3_00000_010000_100f; + fme_dfh_values[EMIF_DFH_IDX] = 64'h3_00000_050000_0009; + fme_dfh_values[FME_PR_DFH_IDX] = 64'h3_00000_001000_1005; + fme_dfh_values[PORT_DFH_IDX] = 64'h4000_0000_1000_1001; + fme_dfh_values[USER_CLOCK_DFH_IDX] = 64'h3_00000_001000_0014; + fme_dfh_values[PORT_STP_DFH_IDX] = 64'h3_00000_00D000_2013; + fme_dfh_values[AFU_INTF_DFH_IDX] = 64'h3_00001_000000_2010; + + return fme_dfh_values; + endfunction + +endpackage + +`endif diff --git a/sim/unit_test/dfh_walker/testbench/tester_tests.sv b/sim/unit_test/dfh_walker/testbench/tester_tests.sv new file mode 100755 index 0000000..663cf47 --- /dev/null +++ b/sim/unit_test/dfh_walker/testbench/tester_tests.sv @@ -0,0 +1,437 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// This file defines all the test cases for current test. +// +// main_test() is the main entry function which the tester calls +// to execute the unit tests. +// +//----------------------------------------------------------------------------- + +import test_csr_defs::*; +import ofs_fim_pcie_pkg::*; + +//------------------- +// Test utilities +//------------------- +task incr_test_id; +begin + test_id = test_id + 1; +end +endtask + +task post_test_util; + input logic [31:0] old_test_err_count; + logic result; +begin + if (test_utils::get_err_count() > old_test_err_count) begin + result = 1'b0; + end else begin + result = 1'b1; + end + + repeat (10) + @(posedge avl_clk); + + @(posedge avl_clk); + reset_test = 1'b1; + repeat (5) + @(posedge avl_clk); + reset_test = 1'b0; + + f_reset_tag(); + + if (result) begin + $display("\nTest status: OK"); + test_summary[test_id].result = 1'b1; + end else begin + $display("\nTest status: FAILED"); + test_summary[test_id].result = 1'b0; + end + incr_test_id(); +end +endtask + +task print_test_header; + input [1024*8-1:0] test_name; +begin + $display("\n********************************************"); + $display(" Running TEST(%0d) : %0s", test_id, test_name); + $display("********************************************"); + test_summary[test_id].name = test_name; +end +endtask + +task verify_mmio_err_count; + output logic result; + input logic [7:0] exp_err; +begin + // Wait 30 clock cycles for checker error to be logged + repeat (30) + @(posedge fim_clk); + + if (mmio_err_count != exp_err) + begin + result = 1'b0; + $display("Failed - expected errors: %0d, actual errors: %0d", exp_err, mmio_err_count); + end else begin + result = 1'b1; + $display("MMIO error count matches: %0d", mmio_err_count); + end + if (~result) + test_utils::incr_err_count(); +end +endtask + +//------------------- +// Test cases +//------------------- +// Test 32-bit CSR access +task test_csr_access_32; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [PF_WIDTH-1:0] pfn; + input logic [VF_WIDTH-1:0] vfn; + input logic [31:0] data; + logic [31:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE32(addr_mode, addr, bar, vf_active, pfn, vfn, data); + READ32(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR write and read mismatch! write=0x%x read=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 32-bit CSR access to unused CSR region +task test_unused_csr_access_32; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [PF_WIDTH-1:0] pfn; + input logic [VF_WIDTH-1:0] vfn; + input logic [31:0] data; + logic [31:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE32(addr_mode, addr, bar, vf_active, pfn, vfn, data); + READ32(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== 32'h0) begin + $display("\nERROR: Expected 32'h0 to be returned for unused CSR region, actual:0x%x\n",scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 64-bit CSR access +task test_csr_access_64; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [PF_WIDTH-1:0] pfn; + input logic [VF_WIDTH-1:0] vfn; + input logic [63:0] data; + logic [63:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE64(addr_mode, addr, bar, vf_active, pfn, vfn, data); + READ64(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR write and read mismatch! write=0x%x read=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 32-bit CSR read access +task test_csr_read_32; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [PF_WIDTH-1:0] pfn; + input logic [VF_WIDTH-1:0] vfn; + input logic [31:0] data; + logic [31:0] scratch; + logic error; +begin + result = 1'b1; + READ32(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR read mismatch! expected=0x%x actual=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 64-bit CSR read access +task test_csr_read_64; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [PF_WIDTH-1:0] pfn; + input logic [VF_WIDTH-1:0] vfn; + input logic [63:0] data; + logic [63:0] scratch; + logic error; +begin + result = 1'b1; + READ64(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR read mismatch! expected=0x%x actual=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 64-bit CSR access to unused CSR region +task test_unused_csr_access_64; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [PF_WIDTH-1:0] pfn; + input logic [VF_WIDTH-1:0] vfn; + input logic [63:0] data; + logic [63:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE64(addr_mode, addr, bar, vf_active, pfn, vfn, data); + READ64(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== 64'h0) begin + $display("\nERROR: Expected 64'h0 to be returned for unused CSR region, actual:0x%x\n",scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test FME DFH walking +task test_fme_dfh_walking; + output logic result; + dfh_name[MAX_FME_DFH_IDX-1:0] fme_dfh_names; + logic [MAX_FME_DFH_IDX-1:0][63:0] fme_dfh_values; + t_dfh dfh; + int fme_dfh_cnt; + logic eol; + logic [63:0] scratch; + logic error; + logic [31:0] addr; + logic [31:0] old_test_err_count; +begin + print_test_header("test_fme_dfh_walking"); + + old_test_err_count = test_utils::get_err_count(); + result = 1'b1; + + //-------------------------- + // DFH Bit mapping + //-------------------------- + // [63:60]: Feature Type + // [59:52]: Reserved - 0 + // [51:48]: If AFU - AFU Minor Revision Number (else, reserved) - 0 + // [47:41]: Reserved - 0 + // [40 ]: EOL (End of DFH list) + // [39:16]: Next DFH Byte Offset + // [15:12]: If AfU, AFU Major version number (else feature #) - 0 + // [11:0 ]: Feature ID + //-------------------------- + + fme_dfh_names = get_fme_dfh_names(); + fme_dfh_values = get_fme_dfh_values(); + + fme_dfh_cnt = 0; + eol = 1'b0; + addr = FME_DFH_START_OFFSET; + + while (~eol && fme_dfh_cnt < MAX_FME_DFH_IDX) begin + READ64(ADDR32, addr, FME_BAR, 1'b0, 0, 0, scratch, error); + $fdisplay(test_utils::get_logfile_handle(), "%0s", fme_dfh_names[fme_dfh_cnt]); + $fdisplay(test_utils::get_logfile_handle(), " Address (0x%0x)", addr); + $fdisplay(test_utils::get_logfile_handle(), " DFH value (0x%0x)", scratch); + + dfh = t_dfh'(scratch); + eol = dfh.eol; + + if (scratch !== fme_dfh_values[fme_dfh_cnt]) begin + $display("\nERROR: DFH value mismatched, expected: 0x%0x actual:0x%0x\n", fme_dfh_values[fme_dfh_cnt], scratch); + test_utils::incr_err_count(); + eol = 1'b1; // error found, exit the loop + result = 1'b0; + end + + addr = addr + dfh.nxt_dfh_offset; + fme_dfh_cnt = fme_dfh_cnt + 1'b1; + end + + if (result) begin + if (eol !== 1'b1) begin + $display("\nERROR: Expect EOL bit to be set for last FME feature in the DFL (%0s), actual:'b%0b\n", fme_dfh_names[MAX_FME_DFH_IDX-1], eol); + test_utils::incr_err_count(); + result = 1'b0; + end + + if (fme_dfh_cnt !== MAX_FME_DFH_IDX) begin + $display("\nERROR: Expected %d FME features to be discovered, actual:%0d\n", MAX_FME_DFH_IDX, fme_dfh_cnt); + test_utils::incr_err_count(); + result = 1'b0; + end + end + + verify_mmio_err_count(result, 0); + post_test_util(old_test_err_count); +end +endtask + + +//Below task is commented as in EA different tasks were used to cover PORT_DFH and FME_DFH but all DFHs are covered in a single task in R1 +// Test Port DFH walking +//task test_port_dfh_walking; +// output logic result; +// dfh_name[MAX_PORT_DFH_IDX-1:0] port_dfh_names; +// logic [MAX_PORT_DFH_IDX-1:0][63:0] port_dfh_values; +// t_dfh dfh; +// int port_dfh_cnt; +// logic eol; +// logic [63:0] scratch; +// logic error; +// logic [31:0] addr; +// logic [31:0] old_test_err_count; +//begin +// print_test_header("test_port_dfh_walking"); +// +// old_test_err_count = test_utils::get_err_count(); +// result = 1'b1; +// +// //-------------------------- +// // DFH Bit mapping +// //-------------------------- +// // [63:60]: Feature Type +// // [59:52]: Reserved - 0 +// // [51:48]: If AFU - AFU Minor Revision Number (else, reserved) - 0 +// // [47:41]: Reserved - 0 +// // [40 ]: EOL (End of DFH list) +// // [39:16]: Next DFH Byte Offset +// // [15:12]: If AfU, AFU Major version number (else feature #) - 0 +// // [11:0 ]: Feature ID +// //-------------------------- +// +// port_dfh_names = get_port_dfh_names(); +// port_dfh_values = get_port_dfh_values(); +// +// port_dfh_cnt = 0; +// eol = 1'b0; +// addr = PORT_DFH_START_OFFSET; +// +// while (~eol && port_dfh_cnt < MAX_PORT_DFH_IDX) begin +// READ64(ADDR32, addr, PORT_BAR, 1'b0, 0, 0, scratch, error); +// $fdisplay(test_utils::get_logfile_handle(), "%0s", port_dfh_names[port_dfh_cnt]); +// $fdisplay(test_utils::get_logfile_handle(), " Address (0x%0x)", addr); +// $fdisplay(test_utils::get_logfile_handle(), " DFH value (0x%0x)", scratch); +// +// dfh = t_dfh'(scratch); +// eol = dfh.eol; +// +// if (scratch !== port_dfh_values[port_dfh_cnt]) begin +// $display("\nERROR: DFH value mismatched, expected: 0x%0x actual:0x%0x\n", port_dfh_values[port_dfh_cnt], scratch); +// test_utils::incr_err_count(); +// eol = 1'b1; // error found, exit the loop +// result = 1'b0; +// end +// +// addr = addr + dfh.nxt_dfh_offset; +// port_dfh_cnt = port_dfh_cnt + 1'b1; +// end +// +// if (result) begin +// if (eol !== 1'b1) begin +// $display("\nERROR: Expect EOL bit to be set for last PORT feature in the DFL (%0s), actual:'b%0b\n", port_dfh_names[MAX_PORT_DFH_IDX-1], eol); +// test_utils::incr_err_count(); +// result = 1'b0; +// end +// +// if (port_dfh_cnt !== MAX_PORT_DFH_IDX) begin +// $display("\nERROR: Expected %d PORT features to be discovered, actual:%0d\n", MAX_PORT_DFH_IDX, port_dfh_cnt); +// test_utils::incr_err_count(); +// result = 1'b0; +// end +// end +// +// verify_mmio_err_count(result, 0); +// post_test_util(old_test_err_count); +//end +//endtask + +//------------------- +// Test main entry +//------------------- +task main_test; + output logic test_result; + logic valid_csr_region; +begin + test_fme_dfh_walking (test_result); + //test_port_dfh_walking (test_result); +end +endtask + + + diff --git a/sim/unit_test/dfh_walker/vcs_setup.sh b/sim/unit_test/dfh_walker/vcs_setup.sh new file mode 100644 index 0000000..833180f --- /dev/null +++ b/sim/unit_test/dfh_walker/vcs_setup.sh @@ -0,0 +1,109 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcs" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vcs -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + +define+R1_UNIT_TEST_ENV \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $VCS_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -top $TOP_LEVEL_NAME +error+20 -l vcs.log + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/dfh_walker/vcsmx_setup.sh b/sim/unit_test/dfh_walker/vcsmx_setup.sh new file mode 100755 index 0000000..1a41216 --- /dev/null +++ b/sim/unit_test/dfh_walker/vcsmx_setup.sh @@ -0,0 +1,114 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcsmx" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlogan -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + +define+R1_UNIT_TEST_ENV \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $INC_DIR \ + $RTL_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC +error+1 -l vlog.log + +vcs -full64 -ntb_opts -licqueue +vcs+lic+wait \ + +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -l vcs.log $TOP_LEVEL_NAME + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/email_list.f b/sim/unit_test/email_list.f new file mode 100644 index 0000000..4f11f24 --- /dev/null +++ b/sim/unit_test/email_list.f @@ -0,0 +1,7 @@ +##set env varible EMAIL_LIST to this file path ## +##Add your email list here to get regression_results#### +##NOTE:-Only keep your email_list in this file remove other comments## +## add in below format## +abc@domain_name.com +xyz@doamin_name.com +pqr@domain_name.com diff --git a/sim/unit_test/fme_csr_directed/msim_filelist.sh b/sim/unit_test/fme_csr_directed/msim_filelist.sh new file mode 100755 index 0000000..7e13013 --- /dev/null +++ b/sim/unit_test/fme_csr_directed/msim_filelist.sh @@ -0,0 +1,29 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# +# + +MSIM_FILELIST="+incdir+$OFS_ROOTDIR/ofs-common/src/common/includes/ \ ++incdir+$OFS_ROOTDIR/src/includes/ \ +$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v \ +$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v \ +$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v \ +$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v \ +$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/tennm_atoms.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/mentor/tennm_atoms_ncrypt.sv \ +$THE_PLATFORM/sim/scripts/qip_gen/ofs-common/src/common/fme_id_rom/fme_id_rom/rom_1port_2020/sim/fme_id_rom_rom_1port_2020_pcw7acy.v +$THE_PLATFORM/sim/scripts/qip_gen/ofs-common/src/common/fme_id_rom/fme_id_rom/sim/fme_id_rom.v \ +$OFS_ROOTDIR/ofs-common/src/common/includes/ofs_csr_pkg.sv \ +$OFS_ROOTDIR/ipss/pcie/rtl/ofs_fim_pcie_hdr_def.sv \ +$THE_PLATFORM/src/includes/ofs_fim_cfg_pkg.sv \ +$OFS_ROOTDIR/ofs-common/src/common/lib/mux/pf_vf_mux_pkg.sv \ +$OFS_ROOTDIR/src/afu_top/mux/top_cfg_pkg.sv \ +$OFS_ROOTDIR/ipss/pcie/rtl/ofs_fim_pcie_pkg.sv \ +$OFS_ROOTDIR/ofs-common/src/common/fme/fme_csr_pkg.sv \ +$OFS_ROOTDIR/ofs-common/src/common/includes/ofs_fim_if_pkg.sv \ +$OFS_ROOTDIR/ofs-common/src/common/includes/ofs_fim_pwrgoodn_if.sv \ +$OFS_ROOTDIR/ofs-common/src/common/includes/ofs_fim_axi_mmio_if.sv \ +$OFS_ROOTDIR/ofs-common/src/common/fme/fme_csr_io_if.sv \ +$OFS_ROOTDIR/ofs-common/src/common/fme/fme_csr.sv" diff --git a/sim/unit_test/fme_csr_directed/msim_setup.sh b/sim/unit_test/fme_csr_directed/msim_setup.sh new file mode 100755 index 0000000..44f888b --- /dev/null +++ b/sim/unit_test/fme_csr_directed/msim_setup.sh @@ -0,0 +1,112 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="-finish exit" + +TOP_LEVEL_NAME="testbench_top" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +TEST_BASE_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +TOP_LEVEL_NAME="testbench_top" + +SIM_ROOTDIR="$TEST_DIR/../.." +COMMON_TESTUTIL_DIR="$TEST_DIR/../../scripts" +SIM_DIR="${TEST_DIR}/sim_msim" +THE_PLATFORM=$OFS_ROOTDIR + +TEST_TBFILES_DIR=${TEST_BASE_DIR}/testbench + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for msim # +################################### +. ${TEST_DIR}/../msim_filelist.sh + +TB_SRC="${TEST_TBFILES_DIR}/csr_transaction_class_pkg.sv \ + ${TEST_TBFILES_DIR}/test_csr_directed.sv \ + ${TEST_TBFILES_DIR}/testbench_top.sv" + +################################## +### AFU related verilog source ### +################################## +vlib work +vlog -mfcu -timescale=1ns/1fs +libext+.v+.sv -lint -sv \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+HTILE \ + +define+R1_UNIT_TEST_ENV \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+MSIM_IOFS_D5005 \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + +define+R1_UNIT_TEST_ENV \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $MSIM_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -work work -l msim_vlog.log -suppress 8386,7033,7061,2388,12003,2892 +#suppress 8386 : Replication operator in Conactenation Operator +#suppress 2892 : Net type of 'clk' was not explicitly declared +#suppress 7061 : Variable 'clear_tdo_bit_select' driven in an always_ff block, may not be driven by any other process +#suppress 7033 : Variable 'parser_result' driven in a combinational block, may not be driven by any other process + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + vopt $TOP_LEVEL_NAME -o opt -suppress 2732,12003,7033,3837 -l msim_vopt.log + vsim -c opt -nosva -suppress 2732,12003,7033,3837 -do "add log -r /*; run -all ; quit -f" +fi + + diff --git a/sim/unit_test/fme_csr_directed/readme.txt b/sim/unit_test/fme_csr_directed/readme.txt new file mode 100644 index 0000000..9c71d2c --- /dev/null +++ b/sim/unit_test/fme_csr_directed/readme.txt @@ -0,0 +1,79 @@ +***Test Description*** +This is the unit test for fme_csr. + +It covers the following test scenarios: + * MMIO reads to FME registers. + * MMIO writes to FME registers. + * Test of Register bit attributes. + * Test of update/status values read from FME inputs through FME registers. + * Test of update/control values written to FME registers and driven on FME outputs. + * Test of reads/writes outside of valid register range in valid FME Ranges. + +Description of test modules: + * testbench/testbench_top.sv - Testbench top level module where "test_csr_directed" and DUT are instantiated. + * testbench/test_csr_directed.sv - Main test module: This particular test drives directed tests to specified registers (not random). + * testbench/csr_transaction_class_pkg.v - Defines the transactor objects consumed by test module. + * script/Makefile_VCS.mk - Script to run the test in VCS only + * script/Makefile.mk - Script to run the test in VCS & Questasim. MSIM_D5005=1 option to be given for Questasim else will be for VCS. + + +***Running the test*** +To run the test in VCS: + 1) Make sure the shell environment is set up to run VCS/VCSMX. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Synopsys VCS simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_vcs + dve -full64 -vpd vcdplus.vpd & + +To run the test in QuestaSim: + 1) Make sure the shell environment is set up to run Questasim. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Mentor Graphics QuestaSim simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh MSIM=1 + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_msim + vsim -view vsim.wlf & diff --git a/sim/unit_test/fme_csr_directed/scripts/run_sim.sh b/sim/unit_test/fme_csr_directed/scripts/run_sim.sh new file mode 100755 index 0000000..271afc5 --- /dev/null +++ b/sim/unit_test/fme_csr_directed/scripts/run_sim.sh @@ -0,0 +1,48 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)/.." + + +VCSMX=0 +MSIM=0 +SKIP_IP_CMP=0 +TEST_DIR=$(pwd) + +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh run_sim.sh SKIP_IP_CMP=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +# Source common sim setup script + +. ${TEST_DIR}/../../scripts/sim_setup_common.sh TEST_DIR="$TEST_DIR" VCSMX=$VCSMX MSIM=$MSIM + +# Run simulation +if [ $VCSMX -eq 1 ]; then + echo "Running VCSMX simulation in $TEST_DIR/sim_vcsmx" + cd ${TEST_DIR}/sim_vcsmx && sh ${TEST_SRC_DIR}/vcsmx_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +elif [ $MSIM -eq 1 ]; then + echo "Running Questasim simulation in $TEST_DIR/sim_msim" + cd ${TEST_DIR}/sim_msim && sh ${TEST_SRC_DIR}/msim_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="-l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="" +else + echo "Running VCS simulation in $TEST_DIR/sim_vcs" + cd ${TEST_DIR}/sim_vcs && sh ${TEST_SRC_DIR}/vcs_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +fi + + diff --git a/sim/unit_test/fme_csr_directed/scripts/test_list.f b/sim/unit_test/fme_csr_directed/scripts/test_list.f new file mode 100644 index 0000000..440f186 --- /dev/null +++ b/sim/unit_test/fme_csr_directed/scripts/test_list.f @@ -0,0 +1,2 @@ +$WORKDIR/sim/unit_test/fme_csr_directed/testbench/csr_transaction_class_pkg.sv +$WORKDIR/sim/unit_test/fme_csr_directed/testbench/test_csr_directed.sv diff --git a/sim/unit_test/fme_csr_directed/scripts/vpd_dump.key b/sim/unit_test/fme_csr_directed/scripts/vpd_dump.key new file mode 100644 index 0000000..d9dd783 --- /dev/null +++ b/sim/unit_test/fme_csr_directed/scripts/vpd_dump.key @@ -0,0 +1,2 @@ +dump -add { testbench_top } -aggregates -depth 0 -scope "." +run diff --git a/sim/unit_test/fme_csr_directed/testbench/csr_transaction_class_pkg.sv b/sim/unit_test/fme_csr_directed/testbench/csr_transaction_class_pkg.sv new file mode 100644 index 0000000..96746bc --- /dev/null +++ b/sim/unit_test/fme_csr_directed/testbench/csr_transaction_class_pkg.sv @@ -0,0 +1,2473 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// CSR Transaction Class and Test/Check Class Package <<<<<<<<<<<<<<<<<<<<<< +// +// This file provides definitions for the transaction and test/check classes +// used as transaction and test objects during simulation. Included is an +// abstract base class for the transaction classes to help create polymorphic +// objects in the usable derived classes. +// +// The test/check classes also have an abstract base class and may be made +// polymorphic if needed, but currently there are a few changes in some of +// the derived classes that would prevent this. +// +// Also included in this package are some simple parameters and classes to be +// used as utilities and data structures by the larger classes. +// +//----------------------------------------------------------------------------- + +`ifndef __CSR_TRANSACTION_CLASS_PKG__ +`define __CSR_TRANSACTION_CLASS_PKG__ + +package csr_transaction_class_pkg; + +import ofs_csr_pkg::*; +import ofs_fim_cfg_pkg::*; + + +//------------------------------------------------------------------------------ +// Parameter and Enum Definitions for CSRs. +//------------------------------------------------------------------------------ +parameter CSR_REG_WIDTH = 64; +parameter CSR_ADDR_WIDTH = 20; +parameter CSR_FEATURE_RANGE = 32; +parameter CSR_FEATURE_NUM = 16; + +typedef enum logic [1:0] { + RESET_N = 2'b00, + PWR_GOOD_N = 2'b01, + READ = 2'b10, + WRITE = 2'b11 +} transactor_type_t; + +//------------------------------------------------------------------------------ +// CLASS DEFINITIONS +//------------------------------------------------------------------------------ +// Base Classes: BitErrorLog, BitCheckLog +//------------------------------------------------------------------------------ +// These are simple logging objects for the test classes that follow. +//------------------------------------------------------------------------------ +class BitErrorLog; + logic [63:0] bit_pos; + logic [63:0] bit_expected; + string test_name; + + + function new(); + this.bit_pos = {64{1'b0}}; + this.bit_expected = {64{1'b0}}; + this.test_name = ""; + endfunction + + + function clear(); + bit_pos = {64{1'b0}}; + bit_expected = {64{1'b0}}; + test_name = ""; + endfunction + + + function int error_count(); + int i; + logic [63:0] register; + i = 0; + register = bit_pos; + while (register > 64'd0) + begin + register = register & (register - 64'd1); // Efficient for relatively low 1's density that is expected. + i = i + 1; + end + return i; + endfunction + +endclass: BitErrorLog + + +class BitCheckLog; + logic [63:0] last_value; + time check_time; + logic [63:0] value; + string test_name; + + + function new(); + this.last_value = {64{1'b0}}; + this.check_time = $time; + this.value = {64{1'b0}}; + this.test_name = ""; + endfunction + + + function clear(); + last_value = {64{1'b0}}; + check_time = $time; + value = {64{1'b0}}; + test_name = ""; + endfunction + +endclass: BitCheckLog + + +//------------------------------------------------------------------------------ +// CLASS DEFINITIONS +//------------------------------------------------------------------------------ +// Base Class: RandData +//------------------------------------------------------------------------------ +// This is a simple random data object used by the test classes requiring +// random data. +//------------------------------------------------------------------------------ +class RandData; + rand logic [63:0] data; + + function new(); + this.data = {64{1'b0}}; + endfunction + +endclass: RandData + + +//------------------------------------------------------------------------------ +// CLASS DEFINITIONS +//------------------------------------------------------------------------------ +// Base Class: Transaction +//------------------------------------------------------------------------------ +// All Transactions are designed to use the abstract base class "Transaction". +// The method "run()" is included in base class as a pure virtual function so +// that we can use polymorphism to put transactions of different types into a +// single queue and process them all the same way using base class handles. +//------------------------------------------------------------------------------ +virtual class Transaction; // Abstract Base Class + virtual ofs_fim_pwrgoodn_if.master pgn; + virtual ofs_fim_axi_mmio_if #( + .AWID_WIDTH(MMIO_TID_WIDTH), + .AWADDR_WIDTH (MMIO_ADDR_WIDTH), + .WDATA_WIDTH(MMIO_DATA_WIDTH), + .ARID_WIDTH(MMIO_TID_WIDTH), + .ARADDR_WIDTH(MMIO_ADDR_WIDTH), + .RDATA_WIDTH(MMIO_DATA_WIDTH) + ).master axi; + transactor_type_t transactor; + static logic [6:0] count = 6'h10; + static int t_count = 0; + logic [6:0] id; + int delay; + + // Constructor + function new( + virtual ofs_fim_axi_mmio_if #( + .AWID_WIDTH(MMIO_TID_WIDTH), + .AWADDR_WIDTH (MMIO_ADDR_WIDTH), + .WDATA_WIDTH(MMIO_DATA_WIDTH), + .ARID_WIDTH(MMIO_TID_WIDTH), + .ARADDR_WIDTH(MMIO_ADDR_WIDTH), + .RDATA_WIDTH(MMIO_DATA_WIDTH) + ).master axi, + virtual ofs_fim_pwrgoodn_if.master pgn + ); + id = '0; + delay = 0; + t_count++; + this.axi = axi; + this.pgn = pgn; + endfunction + + // Pure virtual functions for polymorphism. + pure virtual function void set_delay(int delay_value); + pure virtual task run(); +endclass: Transaction + + +//------------------------------------------------------------------------------ +// Derived Class: ResetTransaction +// Inheritance..: Transaction +//------------------------------------------------------------------------------ +// This class asserts the soft reset "rst_n" for two clocks in the AXI MMIO +// interface. The length of the reset can be changed using the "set_delay" +// method function. +//------------------------------------------------------------------------------ +class ResetTransaction extends Transaction; + + // Constructor + function new( + virtual ofs_fim_axi_mmio_if #( + .AWID_WIDTH(MMIO_TID_WIDTH), + .AWADDR_WIDTH (MMIO_ADDR_WIDTH), + .WDATA_WIDTH(MMIO_DATA_WIDTH), + .ARID_WIDTH(MMIO_TID_WIDTH), + .ARADDR_WIDTH(MMIO_ADDR_WIDTH), + .RDATA_WIDTH(MMIO_DATA_WIDTH) + ).master axi, + virtual ofs_fim_pwrgoodn_if.master pgn + ); + super.new(.axi(axi), .pgn(pgn)); + this.delay = 2; + this.transactor = RESET_N; + endfunction + + + virtual function void set_delay(int delay_value); + delay = delay_value; + endfunction + + + virtual task run(); + @(posedge axi.clk); + #100ps axi.rst_n = 1'b0; + repeat (delay) @(posedge axi.clk); + #100ps axi.rst_n = 1'b1; + endtask + +endclass: ResetTransaction + + +//------------------------------------------------------------------------------ +// Derived Class: PwrResetTransaction +// Inheritance..: Transaction +//------------------------------------------------------------------------------ +// This class asserts the hard reset "rst_n" for two clocks in the PwrGoodN +// interface. The length of the reset can be changed using the "set_delay" +// method function. +//------------------------------------------------------------------------------ +class PwrResetTransaction extends Transaction; + + // Constructor + function new( + virtual ofs_fim_axi_mmio_if #( + .AWID_WIDTH(MMIO_TID_WIDTH), + .AWADDR_WIDTH (MMIO_ADDR_WIDTH), + .WDATA_WIDTH(MMIO_DATA_WIDTH), + .ARID_WIDTH(MMIO_TID_WIDTH), + .ARADDR_WIDTH(MMIO_ADDR_WIDTH), + .RDATA_WIDTH(MMIO_DATA_WIDTH) + ).master axi, + virtual ofs_fim_pwrgoodn_if.master pgn + ); + super.new(.axi(axi), .pgn(pgn)); + this.delay = 2; + this.transactor = PWR_GOOD_N; + endfunction + + + virtual function void set_delay(int delay_value); + delay = delay_value; + endfunction + + + virtual task run(); + @(posedge axi.clk); + #100ps pgn.pwr_good_n = 1'b0; + axi.rst_n = 1'b0; + repeat (delay) @(posedge axi.clk); + #100ps pgn.pwr_good_n = 1'b1; + axi.rst_n = 1'b1; + endtask + +endclass: PwrResetTransaction + + +//------------------------------------------------------------------------------ +// Derived Class: ReadTransaction +// Inheritance..: Transaction +//------------------------------------------------------------------------------ +// This class performs an AXI read based on the read address and access type. +// The access type is enum defined in "ofs_csr_pkg.sv". The values are repeated +// here for convenience: +// typedef enum logic [1:0] { +// NONE = 2'b00, +// LOWER32 = 2'b01, +// UPPER32 = 2'b10, +// FULL64 = 2'b11 +// } csr_access_type_t +//------------------------------------------------------------------------------ +class ReadTransaction extends Transaction; + logic [19:0] rd_addr; + logic [63:0] rd_data; + logic [6:0] rd_id; + logic [1:0] rd_resp; + csr_access_type_t access; + + // Constructor + function new( + virtual ofs_fim_axi_mmio_if #( + .AWID_WIDTH(MMIO_TID_WIDTH), + .AWADDR_WIDTH (MMIO_ADDR_WIDTH), + .WDATA_WIDTH(MMIO_DATA_WIDTH), + .ARID_WIDTH(MMIO_TID_WIDTH), + .ARADDR_WIDTH(MMIO_ADDR_WIDTH), + .RDATA_WIDTH(MMIO_DATA_WIDTH) + ).master axi, + virtual ofs_fim_pwrgoodn_if.master pgn, + input logic [19:0] rd_addr, + input csr_access_type_t access + ); + super.new(.axi(axi), .pgn(pgn)); + id = count++; + this.transactor = READ; + this.rd_addr = rd_addr; + this.access = access; + endfunction + + + virtual function void set_delay(int delay_value); + delay = delay_value; + endfunction + + + virtual task run(); + $timeformat(-9, 2, " ns"); + @(posedge axi.clk); + #100ps; + axi.arid = id; + axi.arlen = 8'b1; + if (access == FULL64) + begin + axi.arsize = 3'b011; + rd_addr[2:0] = 3'b000; + end + else + begin + if (access == UPPER32) + begin + axi.arsize = 3'b010; + rd_addr[2:0] = 3'b100; + end + else + begin + if (access == LOWER32) + begin + axi.arsize = 3'b010; + rd_addr[2:0] = 3'b000; + end + else + begin + axi.arsize = 3'b000; + rd_addr[2:0] = 3'b000; + end + end + end + axi.araddr = rd_addr; + axi.arburst = 2'b01; + axi.arvalid = 1'b1; + wait (axi.arready === 1'b1); + @(posedge axi.clk); + #100ps axi.arvalid = 1'b0; + axi.rready = 1'b1; + wait (axi.rvalid === 1'b1) + #100ps rd_data = axi.rdata; + rd_id = axi.rid; + //rd_resp = axi.rresp; + $cast(rd_resp, axi.rresp); + wait (axi.rvalid === 1'b0) + #100ps axi.rready = 1'b0; + if (access == FULL64) + begin + $display ( "Read 64-bit register @ address:%H_%H got data:%H_%H_%H_%H with response:%H for transaction id:%H:%H at time:%0t.", rd_addr[19:16], rd_addr[15:0], rd_data[63:48], rd_data[47:32], rd_data[31:16], rd_data[15:0], rd_resp, id, rd_id, $time); + end + else + begin + if (access == UPPER32) + begin + $display ( "Read upper 32-bit register @ address:%H_%H got data:%H_%H with response:%H for transaction id:%H:%H at time:%0t.", rd_addr[19:16], rd_addr[15:0], rd_data[63:48], rd_data[47:32], rd_resp, id, rd_id, $time); + end + else + begin + if (access == LOWER32) + begin + $display ( "Read lower 32-bit register @ address:%H_%H got data:%H_%H with response:%H for transaction id:%H:%H at time:%0t", rd_addr[19:16], rd_addr[15:0], rd_data[31:16], rd_data[15:0], rd_resp, id, rd_id, $time); + end + else + begin + end + end + end + @(posedge axi.clk); + endtask + +endclass: ReadTransaction + + +//------------------------------------------------------------------------------ +// Derived Class: ReadTransactionSilent +// Inheritance..: ReadTransaction +//------------------------------------------------------------------------------ +// This class performs an AXI read based on the read address and access type. +// The access type is enum defined in "ofs_csr_pkg.sv". The values are repeated +// here for convenience: +// typedef enum logic [1:0] { +// NONE = 2'b00, +// LOWER32 = 2'b01, +// UPPER32 = 2'b10, +// FULL64 = 2'b11 +// } csr_access_type_t +// +// This class is the same as ReadTransaction -- it just does not have the display +// messages in the "run" method so that many of these reads may be performed +// in loops without flooding the message output for normal operations. +//------------------------------------------------------------------------------ +class ReadTransactionSilent extends ReadTransaction; + + // Constructor + function new( + virtual ofs_fim_axi_mmio_if #( + .AWID_WIDTH(MMIO_TID_WIDTH), + .AWADDR_WIDTH (MMIO_ADDR_WIDTH), + .WDATA_WIDTH(MMIO_DATA_WIDTH), + .ARID_WIDTH(MMIO_TID_WIDTH), + .ARADDR_WIDTH(MMIO_ADDR_WIDTH), + .RDATA_WIDTH(MMIO_DATA_WIDTH) + ).master axi, + virtual ofs_fim_pwrgoodn_if.master pgn, + input logic [19:0] rd_addr, + input csr_access_type_t access + ); + super.new(.axi(axi), .pgn(pgn), .rd_addr(rd_addr), .access(access)); + endfunction + + + virtual task run(); + $timeformat(-9, 2, " ns"); + @(posedge axi.clk); + #100ps; + axi.arid = id; + axi.arlen = 8'b1; + if (access == FULL64) + begin + axi.arsize = 3'b011; + rd_addr[2:0] = 3'b000; + end + else + begin + if (access == UPPER32) + begin + axi.arsize = 3'b010; + rd_addr[2:0] = 3'b100; + end + else + begin + if (access == LOWER32) + begin + axi.arsize = 3'b010; + rd_addr[2:0] = 3'b000; + end + else + begin + axi.arsize = 3'b000; + rd_addr[2:0] = 3'b000; + end + end + end + axi.araddr = rd_addr; + axi.arburst = 2'b01; + axi.arvalid = 1'b1; + wait (axi.arready === 1'b1); + @(posedge axi.clk); + #100ps axi.arvalid = 1'b0; + axi.rready = 1'b1; + wait (axi.rvalid === 1'b1) + #100ps rd_data = axi.rdata; + rd_id = axi.rid; + //rd_resp = axi.rresp; + $cast(rd_resp, axi.rresp); + wait (axi.rvalid === 1'b0) + #100ps axi.rready = 1'b0; + @(posedge axi.clk); + endtask + +endclass: ReadTransactionSilent + + +//------------------------------------------------------------------------------ +// Derived Class: WriteTransaction +// Inheritance..: Transaction +//------------------------------------------------------------------------------ +// This class performs an AXI write based on the write address, write data, and +// access type. +// +// The access type is enum defined in "ofs_csr_pkg.sv". The values are repeated +// here for convenience: +// typedef enum logic [1:0] { +// NONE = 2'b00, +// LOWER32 = 2'b01, +// UPPER32 = 2'b10, +// FULL64 = 2'b11 +// } csr_access_type_t +//------------------------------------------------------------------------------ +class WriteTransaction extends Transaction; + logic [19:0] wr_addr; + logic [63:0] wr_data; + logic [6:0] wr_id; + logic [1:0] wr_resp; + csr_access_type_t access; + + // Constructor + function new( + virtual ofs_fim_axi_mmio_if #( + .AWID_WIDTH(MMIO_TID_WIDTH), + .AWADDR_WIDTH (MMIO_ADDR_WIDTH), + .WDATA_WIDTH(MMIO_DATA_WIDTH), + .ARID_WIDTH(MMIO_TID_WIDTH), + .ARADDR_WIDTH(MMIO_ADDR_WIDTH), + .RDATA_WIDTH(MMIO_DATA_WIDTH) + ).master axi, + virtual ofs_fim_pwrgoodn_if.master pgn, + input logic [19:0] wr_addr, + input logic [63:0] wr_data, + input csr_access_type_t access + ); + super.new(.axi(axi), .pgn(pgn)); + id = count++; + this.transactor = WRITE; + this.wr_addr = wr_addr; + this.wr_data = wr_data; + this.access = access; + endfunction + + + virtual function void set_delay(int delay_value); + delay = delay_value; + endfunction + + + virtual task run(); + @(posedge axi.clk); + #100ps; + axi.awid = id; + axi.awlen = 8'b1; + if (access == FULL64) + begin + axi.awsize = 3'b011; + axi.wstrb = 8'hFF; + wr_addr[2:0] = 3'b000; + end + else + begin + if (access == UPPER32) + begin + axi.awsize = 3'b010; + axi.wstrb = 8'hF0; + wr_addr[2:0] = 3'b100; + end + else + begin + if (access == LOWER32) + begin + axi.awsize = 3'b010; + axi.wstrb = 8'h0F; + wr_addr[2:0] = 3'b000; + end + else + begin + axi.awsize = 3'b000; + axi.wstrb = 8'h00; + wr_addr[2:0] = 3'b000; + end + end + end + axi.awaddr = wr_addr; + axi.awburst = 2'b01; + axi.awvalid = 1'b1; + axi.wdata = wr_data; + axi.wlast = 1'b1; + axi.wvalid = 1'b1; + wait ((axi.awready === 1'b1) || (axi.wready === 1'b1)); + @(posedge axi.clk); + if ((axi.awready === 1'b1) && (axi.wready === 1'b1)) + begin + #100ps axi.awvalid = 1'b0; + axi.wvalid = 1'b0; + axi.wlast = 1'b0; + end + else + begin + if ((axi.awready === 1'b1) && (axi.wready === 1'b0)) + begin + #100ps axi.awvalid = 1'b0; + wait (axi.wready === 1'b1); + @(posedge axi.clk); + #100ps axi.wvalid = 1'b0; + axi.wlast = 1'b0; + end + else + begin + if ((axi.awready === 1'b0) && (axi.wready === 1'b1)) + begin + #100ps axi.wvalid = 1'b0; + wait (axi.awready === 1'b1); + @(posedge axi.clk); + #100ps axi.awvalid = 1'b0; + axi.wlast = 1'b0; + end + end + end + axi.bready = 1'b1; + wait (axi.bvalid === 1'b1); + #100ps wr_id = axi.bid; + //wr_resp = axi.bresp; + $cast(wr_resp, axi.bresp); + @(posedge axi.clk); + #100ps axi.bready = 1'b0; + @(posedge axi.clk); + if (access == FULL64) + begin + $display ( "Write 64-bit register @ address:%H_%H with data:%H_%H_%H_%H got response:%H for transaction id:%H:%H at time:%0t.", wr_addr[19:16], wr_addr[15:0], wr_data[63:48], wr_data[47:32], wr_data[31:16], wr_data[15:0], wr_resp, id, wr_id, $time); + end + else + begin + if (access == UPPER32) + begin + $display ( "Write upper 32-bit register @ address:%H_%H with data:%H_%H got response:%H for transaction id:%H:%H at time:%0t.", wr_addr[19:16], wr_addr[15:0], wr_data[63:48], wr_data[47:32], wr_resp, id, wr_id, $time); + end + else + begin + if (access == LOWER32) + begin + $display ( "Write upper 32-bit register @ address:%H_%H with data:%H_%H got response:%H for transaction id:%H:%H at time:%0t.", wr_addr[19:16], wr_addr[15:0], wr_data[63:48], wr_data[47:32], wr_resp, id, wr_id, $time); + end + else + begin + end + end + end + @(posedge axi.clk); + endtask + +endclass: WriteTransaction + + +//------------------------------------------------------------------------------ +// Derived Class: WriteTransactionSilent +// Inheritance..: WriteTransaction +//------------------------------------------------------------------------------ +// This class performs an AXI write based on the write address, write data, and +// access type. +// +// The access type is enum defined in "ofs_csr_pkg.sv". The values are repeated +// here for convenience: +// typedef enum logic [1:0] { +// NONE = 2'b00, +// LOWER32 = 2'b01, +// UPPER32 = 2'b10, +// FULL64 = 2'b11 +// } csr_access_type_t +// +// This class is the same as WriteTransaction -- it just does not have the display +// messages in the "run" method so that many of these reads may be performed +// in loops without flooding the message output for normal operations. +//------------------------------------------------------------------------------ +class WriteTransactionSilent extends WriteTransaction; + + // Constructor + function new( + virtual ofs_fim_axi_mmio_if #( + .AWID_WIDTH(MMIO_TID_WIDTH), + .AWADDR_WIDTH (MMIO_ADDR_WIDTH), + .WDATA_WIDTH(MMIO_DATA_WIDTH), + .ARID_WIDTH(MMIO_TID_WIDTH), + .ARADDR_WIDTH(MMIO_ADDR_WIDTH), + .RDATA_WIDTH(MMIO_DATA_WIDTH) + ).master axi, + virtual ofs_fim_pwrgoodn_if.master pgn, + input logic [19:0] wr_addr, + input logic [63:0] wr_data, + input csr_access_type_t access + ); + super.new(.axi(axi), .pgn(pgn), .wr_addr(wr_addr), .wr_data(wr_data), .access(access)); + endfunction + + + virtual task run(); + @(posedge axi.clk); + #100ps; + axi.awid = id; + axi.awlen = 8'b1; + if (access == FULL64) + begin + axi.awsize = 3'b011; + axi.wstrb = 8'hFF; + wr_addr[2:0] = 3'b000; + end + else + begin + if (access == UPPER32) + begin + axi.awsize = 3'b010; + axi.wstrb = 8'hF0; + wr_addr[2:0] = 3'b100; + end + else + begin + if (access == LOWER32) + begin + axi.awsize = 3'b010; + axi.wstrb = 8'h0F; + wr_addr[2:0] = 3'b000; + end + else + begin + axi.awsize = 3'b000; + axi.wstrb = 8'h00; + wr_addr[2:0] = 3'b000; + end + end + end + axi.awaddr = wr_addr; + axi.awburst = 2'b01; + axi.awvalid = 1'b1; + axi.wdata = wr_data; + axi.wlast = 1'b1; + axi.wvalid = 1'b1; + wait ((axi.awready === 1'b1) || (axi.wready === 1'b1)); + @(posedge axi.clk); + if ((axi.awready === 1'b1) && (axi.wready === 1'b1)) + begin + #100ps axi.awvalid = 1'b0; + axi.wvalid = 1'b0; + axi.wlast = 1'b0; + end + else + begin + if ((axi.awready === 1'b1) && (axi.wready === 1'b0)) + begin + #100ps axi.awvalid = 1'b0; + wait (axi.wready === 1'b1); + @(posedge axi.clk); + #100ps axi.wvalid = 1'b0; + axi.wlast = 1'b0; + end + else + begin + if ((axi.awready === 1'b0) && (axi.wready === 1'b1)) + begin + #100ps axi.wvalid = 1'b0; + wait (axi.awready === 1'b1); + @(posedge axi.clk); + #100ps axi.awvalid = 1'b0; + axi.wlast = 1'b0; + end + end + end + axi.bready = 1'b1; + wait (axi.bvalid === 1'b1); + #100ps wr_id = axi.bid; + //wr_resp = axi.bresp; + $cast(wr_resp, axi.bresp); + @(posedge axi.clk); + #100ps axi.bready = 1'b0; + @(posedge axi.clk); + endtask + +endclass: WriteTransactionSilent + + +//------------------------------------------------------------------------------ +// CLASS DEFINITIONS +//------------------------------------------------------------------------------ +// Base Class: RegCheck +//------------------------------------------------------------------------------ +// All register checking tests to use the abstract base class "RegCheck". +// This base class implements all of the core elements of the check/test classes +// and sets forward a foundation for polymorphism if it is desired later. +// +// Each of the following derived classes performs a register test or enables +// a type of register test. +//------------------------------------------------------------------------------ +virtual class RegCheck; // Abstract Base Class + + virtual ofs_fim_pwrgoodn_if.master pgn; + virtual ofs_fim_axi_mmio_if #( + .AWID_WIDTH(MMIO_TID_WIDTH), + .AWADDR_WIDTH (MMIO_ADDR_WIDTH), + .WDATA_WIDTH(MMIO_DATA_WIDTH), + .ARID_WIDTH(MMIO_TID_WIDTH), + .ARADDR_WIDTH(MMIO_ADDR_WIDTH), + .RDATA_WIDTH(MMIO_DATA_WIDTH) + ).master axi; + ofs_csr_reg_generic_attr_t check_reg_attr; + string check_reg_name; + logic [19:0] reg_addr; + ofs_csr_reg_generic_t reset_reg; + ofs_csr_reg_generic_t update_reg; + Transaction tr; + ResetTransaction rt; + PwrResetTransaction prt; + ReadTransaction rdt; + ReadTransactionSilent rdst; + WriteTransaction wrt; + WriteTransactionSilent wrst; + static int check_count = 0; + static int total_bit_error_count = 0; + int tr_count; + int i; + + // Constructor + function new( + virtual ofs_fim_axi_mmio_if #( + .AWID_WIDTH(MMIO_TID_WIDTH), + .AWADDR_WIDTH (MMIO_ADDR_WIDTH), + .WDATA_WIDTH(MMIO_DATA_WIDTH), + .ARID_WIDTH(MMIO_TID_WIDTH), + .ARADDR_WIDTH(MMIO_ADDR_WIDTH), + .RDATA_WIDTH(MMIO_DATA_WIDTH) + ).master axi, + virtual ofs_fim_pwrgoodn_if.master pgn, + input ofs_csr_reg_generic_attr_t check_reg_attr, + string check_reg_name, + input logic [19:0] reg_addr, + input ofs_csr_reg_generic_t reset_reg, + input ofs_csr_reg_generic_t update_reg + ); + this.axi = axi; + this.pgn = pgn; + this.check_reg_attr = check_reg_attr; + this.check_reg_name = check_reg_name; + this.reg_addr = reg_addr; + this.reset_reg = reset_reg; + this.update_reg = update_reg; + check_count++; + this.i = 0; + endfunction + + + // Pure virtual functions to support polymorphism if this is desired later. + pure virtual task check(); + pure virtual task check_data( + input logic [63:0] write_value_passed + ); + pure virtual function BitErrorLog bit_check ( + input BitCheckLog check + ); + pure virtual function logic pass(); + pure virtual function logic fail(); + pure virtual function void report_errors( + input BitErrorLog error, + input BitCheckLog check + ); + +endclass: RegCheck + + +//------------------------------------------------------------------------------ +// Derived Class: ResetCheck +// Inheritance..: RegCheck +//------------------------------------------------------------------------------ +// This class asserts the soft reset "rst_n" and checks to make sure that the +// register resets or obeys it's "sticky" attributes if applicable. +//------------------------------------------------------------------------------ +class ResetCheck extends RegCheck; + BitErrorLog reset_error; + BitCheckLog reset_check; + logic [19:0] wr_addr; + logic [63:0] wr_data; + logic [6:0] wr_id; + logic [1:0] wr_resp; + logic [19:0] rd_addr; + logic [63:0] rd_data; + logic [6:0] rd_id; + logic [1:0] rd_resp; + csr_access_type_t access; + + // Constructor + function new( + virtual ofs_fim_axi_mmio_if #( + .AWID_WIDTH(MMIO_TID_WIDTH), + .AWADDR_WIDTH (MMIO_ADDR_WIDTH), + .WDATA_WIDTH(MMIO_DATA_WIDTH), + .ARID_WIDTH(MMIO_TID_WIDTH), + .ARADDR_WIDTH(MMIO_ADDR_WIDTH), + .RDATA_WIDTH(MMIO_DATA_WIDTH) + ).master axi, + virtual ofs_fim_pwrgoodn_if.master pgn, + input ofs_csr_reg_generic_attr_t check_reg_attr, + string check_reg_name, + input logic [19:0] reg_addr, + ref ofs_csr_reg_generic_t reset_reg, + ref ofs_csr_reg_generic_t update_reg + ); + super.new( + .axi(axi), + .pgn(pgn), + .check_reg_attr(check_reg_attr), + .check_reg_name(check_reg_name), + .reg_addr(reg_addr), + .reset_reg(reset_reg), + .update_reg(update_reg) + ); + this.wr_addr = reg_addr; + this.rd_addr = reg_addr; + this.reset_check = new(); + endfunction + + + virtual task check(); + reset_error = bit_check( + .check(reset_check) + ); + total_bit_error_count = total_bit_error_count + reset_error.error_count(); + if (|wr_data) + begin + reset_check.test_name = "soft-reset/writing ones"; + reset_error.test_name = "soft-reset/writing ones"; + end + else + begin + reset_check.test_name = "soft-reset/writing zeros"; + reset_error.test_name = "soft-reset/writing zeros"; + end + $display(""); + report_errors( + .error(reset_error), + .check(reset_check) + ); + $display(""); + tr_count = rdt.t_count; + endtask + + + virtual task write_value( + input logic [63:0] write_value_passed + ); + wr_data = write_value_passed; + wrt = new( + .axi(axi), + .pgn(pgn), + .wr_addr(wr_addr), + .wr_data(wr_data), + .access(FULL64) + ); + wrt.run(); + rdt = new( + .axi(axi), + .pgn(pgn), + .rd_addr(rd_addr), + .access(FULL64) + ); + rdt.run(); + reset_check.last_value = rdt.rd_data; + endtask + + + virtual task reset_on(); + @(posedge axi.clk); + #100ps axi.rst_n = 1'b0; + repeat (4) @(posedge axi.clk); + endtask + + + virtual function void update_reset_value( + input logic [63:0] reset_value, + input time reset_time + ); + reset_check.value = reset_value; + reset_check.check_time = reset_time; + $display("Reset 64-bit register @ address:%H_%H got data:%H_%H_%H_%H with soft reset at time:%0t.", rd_addr[19:16], rd_addr[15:0], reset_value[63:48], reset_value[47:32], reset_value[31:16], reset_value[15:0], reset_time); + endfunction + + + virtual task reset_off(); + @(posedge axi.clk); + #100ps axi.rst_n = 1'b1; + repeat (4) @(posedge axi.clk); + endtask + + + virtual task check_data( + input logic [63:0] write_value_passed + ); // Task does nothing with this class, but is kept for abstract base class compatibility. + endtask + + + virtual function BitErrorLog bit_check( + input BitCheckLog check + ); + int i; + BitErrorLog bit_checker; + bit_checker = new(); + for(i=0; i<64; i=i+1) + begin: bit_check_loop + case (check_reg_attr.data[i]) + RO: begin // All read-only bits should contain their reset/update values. + if ((check.value[i] !== reset_reg.data[i]) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = reset_reg.data[i]; + end + end + RW: begin // All RW bits should contain reset values. + if ((check.value[i] !== reset_reg.data[i]) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = reset_reg.data[i]; + end + end + RWS, RWD: begin // All sticky read-write bits should contain latest write data. + if ((check.value[i] !== check.last_value[i]) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = check.last_value[i]; + end + end + RW1C: begin // All RW1C bits should contain their reset values. + if ((check.value[i] !== reset_reg.data[i]) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = reset_reg.data[i]; + end + end + RW1CS, RW1CD: begin // All sticky Write-one-to-clear bits should retain their value. + if ((check.value[i] !== check.last_value[i]) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = check.last_value[i]; + end + end + RW1S: begin // All Write-one-to-set attributes behave the same out of reset. + if ((check.value[i] !== reset_reg.data[i]) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = reset_reg.data[i]; + end + end + RW1SS, RW1SD: begin // All Write-one-to-set attributes behave the same out of reset. + if ((check.value[i] !== check.last_value[i]) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = check.last_value[i]; + end + end + Rsvd, RsvdP: begin // These bits are don't cares. + bit_checker.bit_pos[i] = 1'b0; + bit_checker.bit_expected[i] = 1'bX; + end + RsvdZ: begin + if ((check.value[i] !== 1'b0) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = 1'b0; + end + end + endcase + end: bit_check_loop + return bit_checker; + endfunction + + + virtual function logic pass(); + return ~(|reset_error.bit_pos); + endfunction + + + virtual function logic fail(); + return (|reset_error.bit_pos); + endfunction + + + virtual function void report_errors( + input BitErrorLog error, + input BitCheckLog check + ); + int i; + $timeformat(-9, 2," ns"); + if ( (|error.bit_pos) ) + begin + $display ("ERROR: Register:%s at address:%H_%H has failed bit-level %s check with %2d bits in error at time:%0t.", check_reg_name, reg_addr[19:16], reg_addr[15:0], error.test_name, error.error_count(), check.check_time); + $display ("-------------------------------------------------------------------------------------------------------------------------------------------"); + end + else + begin + $display ("Success: Register:%s at address %H_%H has passed bit-level %s check at time:%0t.", check_reg_name, reg_addr[19:16], reg_addr[15:0], error.test_name, check.check_time); + end + for (i=0; i<64; i=i+1) + begin + if (error.bit_pos[i] == 1'b1) + begin + $display(" Bit:%2d with attribute:%-5s of register field:%H_%H_%H_%H is:%b and should be:%b", i, check_reg_attr.data[i].name, check.value[63:48], check.value[47:32], check.value[31:16], check.value[15:0], check.value[i], error.bit_expected[i]); + end + end + if ( (|error.bit_pos) ) + begin + $display ("-------------------------------------------------------------------------------------------------------------------------------------------"); + end + endfunction + +endclass: ResetCheck + + +//------------------------------------------------------------------------------ +// Derived Class: HardResetCheck +// Inheritance..: ResetCheck +//------------------------------------------------------------------------------ +// This class asserts the hard reset "pwr_good_n" as well as the AXI soft reset, +// "rst_n" and checks to make sure that the register resets or obeys it's +// "sticky" attributes if applicable. +//------------------------------------------------------------------------------ +class HardResetCheck extends ResetCheck; + + // Constructor + function new( + virtual ofs_fim_axi_mmio_if #( + .AWID_WIDTH(MMIO_TID_WIDTH), + .AWADDR_WIDTH (MMIO_ADDR_WIDTH), + .WDATA_WIDTH(MMIO_DATA_WIDTH), + .ARID_WIDTH(MMIO_TID_WIDTH), + .ARADDR_WIDTH(MMIO_ADDR_WIDTH), + .RDATA_WIDTH(MMIO_DATA_WIDTH) + ).master axi, + virtual ofs_fim_pwrgoodn_if.master pgn, + input ofs_csr_reg_generic_attr_t check_reg_attr, + string check_reg_name, + input logic [19:0] reg_addr, + ref ofs_csr_reg_generic_t reset_reg, + ref ofs_csr_reg_generic_t update_reg + ); + super.new( + .axi(axi), + .pgn(pgn), + .check_reg_attr(check_reg_attr), + .check_reg_name(check_reg_name), + .reg_addr(reg_addr), + .reset_reg(reset_reg), + .update_reg(update_reg) + ); + endfunction + + + virtual task check(); + reset_error = bit_check( + .check(reset_check) + ); + total_bit_error_count = total_bit_error_count + reset_error.error_count(); + if (|wr_data) + begin + reset_check.test_name = "hard-reset/writing ones"; + reset_error.test_name = "hard-reset/writing ones"; + end + else + begin + reset_check.test_name = "hard-reset/writing zeros"; + reset_error.test_name = "hard-reset/writing zeros"; + end + $display(""); + report_errors( + .error(reset_error), + .check(reset_check) + ); + $display(""); + tr_count = rdt.t_count; + endtask + + + virtual task reset_on(); + @(posedge axi.clk); + #100ps axi.rst_n = 1'b0; + pgn.pwr_good_n = 1'b0; + repeat (4) @(posedge axi.clk); + endtask + + + virtual function void update_reset_value( + input logic [63:0] reset_value, + input time reset_time + ); + reset_check.value = reset_value; + reset_check.check_time = reset_time; + $display("Reset 64-bit register @ address:%H_%H got data:%H_%H_%H_%H with hard reset at time:%0t.", rd_addr[19:16], rd_addr[15:0], reset_value[63:48], reset_value[47:32], reset_value[31:16], reset_value[15:0], reset_time); + endfunction + + + virtual task reset_off(); + @(posedge axi.clk); + #100ps axi.rst_n = 1'b1; + pgn.pwr_good_n = 1'b1; + repeat (4) @(posedge axi.clk); + endtask + + + virtual function BitErrorLog bit_check( + input BitCheckLog check + ); + int i; + BitErrorLog bit_checker; + bit_checker = new(); + for(i=0; i<64; i=i+1) + begin: bit_check_loop + case (check_reg_attr.data[i]) + RO: begin // All read-only bits should contain their reset/update values. + if ((check.value[i] !== reset_reg.data[i]) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = reset_reg.data[i]; + end + end + RW, RWS: begin // All RW & RWS bits should contain reset values. + if ((check.value[i] !== reset_reg.data[i]) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = reset_reg.data[i]; + end + end + RWD: begin // All hard sticky read-write bits should contain latest write data. + if ((check.value[i] !== check.last_value[i]) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = check.last_value[i]; + end + end + RW1C, RW1CS: begin // All RW1C & RW1CS bits should contain their reset values. + if ((check.value[i] !== reset_reg.data[i]) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = reset_reg.data[i]; + end + end + RW1CD: begin // All hard Write-one-to-clear bits should retain their value. + if ((check.value[i] !== check.last_value[i]) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = check.last_value[i]; + end + end + RW1S, RW1SS: begin // All RW1S & RW1SS bits should contain their reset values. + if ((check.value[i] !== reset_reg.data[i]) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = reset_reg.data[i]; + end + end + RW1SD: begin // All hard Write-one-to-set bits should retain their values. + if ((check.value[i] !== check.last_value[i]) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = check.last_value[i]; + end + end + Rsvd, RsvdP: begin // These bits are don't cares. + bit_checker.bit_pos[i] = 1'b0; + bit_checker.bit_expected[i] = 1'bX; + end + RsvdZ: begin + if ((check.value[i] !== 1'b0) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = 1'b0; + end + end + endcase + end: bit_check_loop + return bit_checker; + endfunction + + + virtual function logic pass(); + return ~(|reset_error.bit_pos); + endfunction + + + virtual function logic fail(); + return (|reset_error.bit_pos); + endfunction + +endclass: HardResetCheck + + + +//------------------------------------------------------------------------------ +// Derived Class: WriteCheck +// Inheritance..: RegCheck +//------------------------------------------------------------------------------ +// This class performs an all-ones write and an all-zeros write to a register +// and makes sure that the bits in the register retain their appropriate state +// according to their relative bit attributes. +//------------------------------------------------------------------------------ +class WriteCheck extends RegCheck; + logic [19:0] wr_addr; + logic [63:0] wr_data; + logic [6:0] wr_id; + logic [1:0] wr_resp; + logic [19:0] rd_addr; + logic [63:0] rd_data; + logic [6:0] rd_id; + logic [1:0] rd_resp; + csr_access_type_t access; + BitErrorLog write0_error; + BitErrorLog write1_error; + BitCheckLog write0_check; + BitCheckLog write1_check; + + // Constructor + function new( + virtual ofs_fim_axi_mmio_if #( + .AWID_WIDTH(MMIO_TID_WIDTH), + .AWADDR_WIDTH (MMIO_ADDR_WIDTH), + .WDATA_WIDTH(MMIO_DATA_WIDTH), + .ARID_WIDTH(MMIO_TID_WIDTH), + .ARADDR_WIDTH(MMIO_ADDR_WIDTH), + .RDATA_WIDTH(MMIO_DATA_WIDTH) + ).master axi, + virtual ofs_fim_pwrgoodn_if.master pgn, + input ofs_csr_reg_generic_attr_t check_reg_attr, + string check_reg_name, + input logic [19:0] reg_addr, + ref ofs_csr_reg_generic_t reset_reg, + ref ofs_csr_reg_generic_t update_reg + ); + super.new( + .axi(axi), + .pgn(pgn), + .check_reg_attr(check_reg_attr), + .check_reg_name(check_reg_name), + .reg_addr(reg_addr), + .reset_reg(reset_reg), + .update_reg(update_reg) + ); + this.wr_addr = reg_addr; + this.rd_addr = reg_addr; + this.write0_check = new(); + this.write1_check = new(); + endfunction + + + virtual task check(); + rdt = new( + .axi(axi), + .pgn(pgn), + .rd_addr(rd_addr), + .access(FULL64) + ); + rdt.run(); + write1_check.last_value = rdt.rd_data; + wr_data = 64'hFFFF_FFFF_FFFF_FFFF; + wrt = new( + .axi(axi), + .pgn(pgn), + .wr_addr(wr_addr), + .wr_data(wr_data), + .access(FULL64) + ); + wrt.run(); + rdt.run(); + write1_check.value = rdt.rd_data; + write1_check.check_time = $time; + write1_error = bit_check( + .check(write1_check) + ); + total_bit_error_count = total_bit_error_count + write1_error.error_count(); + write1_check.test_name = "write-one"; + write1_error.test_name = "write-one"; + $display(""); // Provide readable space before calling "report_errors()". + report_errors( + .error(write1_error), + .check(write1_check) + ); + $display(""); // Provide readable space after calling "report_errors()". + rdt.run(); + write0_check.last_value = rdt.rd_data; + wr_data = 64'h0000_0000_0000_0000; + wrt.wr_data = wr_data; + wrt.run(); + rdt.run(); + write0_check.value = rdt.rd_data; + write0_check.check_time = $time; + write0_error = bit_check( + .check(write0_check) + ); + total_bit_error_count = total_bit_error_count + write0_error.error_count(); + write0_check.test_name = "write-zero"; + write0_error.test_name = "write-zero"; + $display(""); // Provide readable space before calling "report_errors()". + report_errors( + .error(write0_error), + .check(write0_check) + ); + $display(""); // Provide readable space after calling "report_errors()". + tr_count = wrt.t_count; // Record statistic for the number of transactors used. + endtask + + + virtual task check_data( + input logic [63:0] write_value_passed + ); + wr_data = write_value_passed; + endtask + + + virtual function BitErrorLog bit_check( + input BitCheckLog check + ); + int i; + BitErrorLog bit_checker; + bit_checker = new(); + for(i=0; i<64; i=i+1) + begin: bit_check_loop + case (check_reg_attr.data[i]) + RO: begin // All read-only bits should contain their update values. + if ((check.value[i] !== update_reg.data[i]) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = update_reg.data[i]; + end + end + RW, RWS, RWD: begin // All read-write bits should contain latest write data. + if ((check.value[i] !== wr_data[i]) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = wr_data[i]; + end + end + RW1C, RW1CS, RW1CD: begin // All Write-one-to-clear attributes behave the same out of reset. + if ((wr_data[i] == 1'b1) || (check.value[i] === 1'bx)) + begin + if ((update_reg.data[i] == 1'b1) || (check.value[i] === 1'bx)) // Due to clock delay after write, register will set if update is high. + begin + if ((check.value[i] !== 1'b1) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = 1'b1; + end + end + else + begin + if ((check.value[i] !== 1'b0) || (check.value[i] === 1'bx)) // Register must clear if update is low. + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = 1'b0; + end + end + end + else + begin + if ((update_reg.data[i] == 1'b1) || (check.value[i] === 1'bx)) // Register will be set if update is high. + begin + if ((check.value[i] !== 1'b1) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = 1'b1; + end + end + else + begin + if ((check.value[i] !== check.last_value[i]) || (check.value[i] === 1'bx)) // Inactive: Register should retain last value if write bit not set. + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = check.last_value[i]; + end + end + end + end + RW1S, RW1SS, RW1SD: begin // All Write-one-to-set attributes behave the same out of reset. + if ((wr_data[i] == 1'b1) || (check.value[i] === 1'bx)) + begin + if ((update_reg.data[i] == 1'b1) || (check.value[i] === 1'bx)) // Due to clock delay after write, register will clear if update is high. + begin + if ((check.value[i] !== 1'b0) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = 1'b0; + end + end + else + begin + if ((check.value[i] !== 1'b1) || (check.value[i] === 1'bx)) // Register must set if update is low. + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = 1'b1; + end + end + end + else + begin + if ((update_reg.data[i] == 1'b1) || (check.value[i] === 1'bx)) // Register will be clear if update is high. + begin + if ((check.value[i] !== 1'b0) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = 1'b0; + end + end + else + begin + if ((check.value[i] !== check.last_value[i]) || (check.value[i] === 1'bx)) //Inactive: Register should retain last value if write bit not set. + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = check.last_value[i]; + end + end + end + end + Rsvd, RsvdP: begin // These bits are don't cares. + end + RsvdZ: begin + if ((check.value[i] !== 1'b0) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = 1'b0; + end + end + endcase + end: bit_check_loop + return bit_checker; + endfunction + + + virtual function logic pass(); + return ~((|write1_error.bit_pos) || (|write0_error.bit_pos)); + endfunction + + + virtual function logic fail(); + return ((|write1_error.bit_pos) || (|write0_error.bit_pos)); + endfunction + + + virtual function void report_errors( + input BitErrorLog error, + input BitCheckLog check + ); + int i; + $timeformat(-9, 2," ns"); + if ( (|error.bit_pos) ) + begin + $display ("ERROR: Register:%s at address:%H_%H has failed bit-level %s check with %2d bits in error at time:%0t.", check_reg_name, reg_addr[19:16], reg_addr[15:0], error.test_name, error.error_count(), check.check_time); + $display ("-------------------------------------------------------------------------------------------------------------------------------------------"); + end + else + begin + $display ("Success: Register:%s at address %H_%H has passed bit-level %s check at time:%0t.", check_reg_name, reg_addr[19:16], reg_addr[15:0], error.test_name, check.check_time); + end + for (i=0; i<64; i=i+1) + begin + if (error.bit_pos[i] == 1'b1) + begin + $display(" Bit:%2d with attribute:%-5s of register field:%H_%H_%H_%H is:%b and should be:%b", i, check_reg_attr.data[i].name, check.value[63:48], check.value[47:32], check.value[31:16], check.value[15:0], check.value[i], error.bit_expected[i]); + end + end + if ( (|error.bit_pos) ) + begin + $display ("-------------------------------------------------------------------------------------------------------------------------------------------"); + end + endfunction + +endclass: WriteCheck + + +//------------------------------------------------------------------------------ +// Derived Class: WriteOneSetClearCheck +// Inheritance..: WriteCheck +//------------------------------------------------------------------------------ +// This class performs a write to a register with a value that is passed as +// an input to the "check_data" method function and makes sure that the bits in +// the register retain their appropriate state according to their relative bit +// attributes. +// +// This Class differs from inherited WriteCheck by not using any resets and +// using a passed value to write to the register. This allows testing of +// write-one-to-clear (RW1C) and write-one-to-set (RW1S) register types from +// the main testbench which can sequence the set/clear states of the bits +// from their inputs and then monitor the effect of specific writes to these +// bits. +//------------------------------------------------------------------------------ +class WriteOneSetClearCheck extends WriteCheck; + BitErrorLog write_error; + BitCheckLog write_check; + + // Constructor + function new( + virtual ofs_fim_axi_mmio_if #( + .AWID_WIDTH(MMIO_TID_WIDTH), + .AWADDR_WIDTH (MMIO_ADDR_WIDTH), + .WDATA_WIDTH(MMIO_DATA_WIDTH), + .ARID_WIDTH(MMIO_TID_WIDTH), + .ARADDR_WIDTH(MMIO_ADDR_WIDTH), + .RDATA_WIDTH(MMIO_DATA_WIDTH) + ).master axi, + virtual ofs_fim_pwrgoodn_if.master pgn, + input ofs_csr_reg_generic_attr_t check_reg_attr, + string check_reg_name, + input logic [19:0] reg_addr, + ref ofs_csr_reg_generic_t reset_reg, + ref ofs_csr_reg_generic_t update_reg + ); + super.new( + .axi(axi), + .pgn(pgn), + .check_reg_attr(check_reg_attr), + .check_reg_name(check_reg_name), + .reg_addr(reg_addr), + .reset_reg(reset_reg), + .update_reg(update_reg) + ); + this.write_check = new(); + endfunction + + + virtual task check_data( + input logic [63:0] write_value_passed + ); + rdt = new( + .axi(axi), + .pgn(pgn), + .rd_addr(rd_addr), + .access(FULL64) + ); + rdt.run(); + write_check.last_value = rdt.rd_data; + wr_data = write_value_passed; + wrt = new( + .axi(axi), + .pgn(pgn), + .wr_addr(wr_addr), + .wr_data(wr_data), + .access(FULL64) + ); + wrt.run(); + rdt.run(); + write_check.value = rdt.rd_data; + write_check.check_time = $time; + write_error = bit_check( + .check(write_check) + ); + total_bit_error_count = total_bit_error_count + write_error.error_count(); + if (|wr_data) + begin + write_check.test_name = "write-one-sticky"; + write_error.test_name = "write-one-sticky"; + end + else + begin + write_check.test_name = "write-zero-sticky"; + write_error.test_name = "write-zero-sticky"; + end + $display(""); // Provide readable space before calling "report_errors()". + report_errors( + .error(write_error), + .check(write_check) + ); + $display(""); // Provide readable space after calling "report_errors()". + tr_count = wrt.t_count; // Record statistic for the number of transactors used. + endtask + + + virtual function BitErrorLog bit_check( + input BitCheckLog check + ); + int i; + BitErrorLog bit_checker; + bit_checker = new(); + for(i=0; i<64; i=i+1) + begin: bit_check_loop + case (check_reg_attr.data[i]) + RW1C, RW1CS, RW1CD: begin // All Write-one-to-clear attributes behave the same out of reset. + if ((wr_data[i] == 1'b1) || (check.value[i] === 1'bx)) + begin + if ((update_reg.data[i] == 1'b1) || (check.value[i] === 1'bx)) // Due to clock delay after write, register will set if update is high. + begin + if ((check.value[i] !== 1'b1) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = 1'b1; + end + end + else + begin + if ((check.value[i] !== 1'b0) || (check.value[i] === 1'bx)) // Register must clear if update is low. + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = 1'b0; + end + end + end + else + begin + if ((update_reg.data[i] == 1'b1) || (check.value[i] === 1'bx)) // Register will be set if update is high. + begin + if ((check.value[i] !== 1'b1) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = 1'b1; + end + end + else + begin + if ((check.value[i] !== check.last_value[i]) || (check.value[i] === 1'bx)) // Inactive: Register should retain last value if write bit not set. + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = check.last_value[i]; + end + end + end + end + RW1S, RW1SS, RW1SD: begin // All Write-one-to-set attributes behave the same out of reset. + if ((wr_data[i] == 1'b1) || (check.value[i] === 1'bx)) + begin + if ((update_reg.data[i] == 1'b1) || (check.value[i] === 1'bx)) // Due to clock delay after write, register will clear if update is high. + begin + if ((check.value[i] !== 1'b0) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = 1'b0; + end + end + else + begin + if ((check.value[i] !== 1'b1) || (check.value[i] === 1'bx)) // Register must set if update is low. + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = 1'b1; + end + end + end + else + begin + if ((update_reg.data[i] == 1'b1) || (check.value[i] === 1'bx)) // Register will be clear if update is high. + begin + if ((check.value[i] !== 1'b0) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = 1'b0; + end + end + else + begin + if ((check.value[i] !== check.last_value[i]) || (check.value[i] === 1'bx)) //Inactive: Register should retain last value if write bit not set. + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = check.last_value[i]; + end + end + end + end + default: begin + bit_checker.bit_pos[i] = 1'b0; + bit_checker.bit_expected[i] = 1'bX; + end + endcase + end: bit_check_loop + return bit_checker; + endfunction + + + virtual function logic pass(); + return ~(|write_error.bit_pos); + endfunction + + + virtual function logic fail(); + return (|write_error.bit_pos); + endfunction + + + virtual function void report_errors( + input BitErrorLog error, + input BitCheckLog check + ); + int i; + $timeformat(-9, 2," ns"); + if ( (|error.bit_pos) ) + begin + $display ("ERROR: Register:%s at address:%H_%H has failed bit-level %s check with %2d bits in error at time:%0t.", check_reg_name, reg_addr[19:16], reg_addr[15:0], error.test_name, error.error_count(), check.check_time); + $display ("-------------------------------------------------------------------------------------------------------------------------------------------"); + end + else + begin + $display ("Success: Register:%s at address %H_%H has passed bit-level %s check at time:%0t.", check_reg_name, reg_addr[19:16], reg_addr[15:0], error.test_name, check.check_time); + end + for (i=0; i<64; i=i+1) + begin + if (error.bit_pos[i] == 1'b1) + begin + $display(" Bit:%2d with attribute:%-5s of register field:%H_%H_%H_%H is:%b and should be:%b", i, check_reg_attr.data[i].name, check.value[63:48], check.value[47:32], check.value[31:16], check.value[15:0], check.value[i], error.bit_expected[i]); + end + end + if ( (|error.bit_pos) ) + begin + $display ("-------------------------------------------------------------------------------------------------------------------------------------------"); + end + endfunction + +endclass: WriteOneSetClearCheck + + +//------------------------------------------------------------------------------ +// Derived Class: WriteWalkingOnesZerosCheck +// Inheritance..: RegCheck +//------------------------------------------------------------------------------ +// This class performs a "walking-ones" and "walking-zeroes" write test to the +// target register and makes sure that the bits in the register retain their +// appropriate state according to their relative bit attributes. +//------------------------------------------------------------------------------ +class WriteWalkingOnesZerosCheck extends RegCheck; + logic [19:0] wr_addr; + logic [63:0] wr_data; + logic [6:0] wr_id; + logic [1:0] wr_resp; + logic [19:0] rd_addr; + logic [63:0] rd_data; + logic [6:0] rd_id; + logic [1:0] rd_resp; + csr_access_type_t access; + BitErrorLog walk_error; + BitCheckLog walk_check; + logic [63:0] shift_reg; + + Transaction tq[$]; // Transaction Queue + BitErrorLog beq[$]; // Bit Error Queue + BitCheckLog bcq[$]; // Bit Check Queue + + // Constructor + function new( + virtual ofs_fim_axi_mmio_if #( + .AWID_WIDTH(MMIO_TID_WIDTH), + .AWADDR_WIDTH (MMIO_ADDR_WIDTH), + .WDATA_WIDTH(MMIO_DATA_WIDTH), + .ARID_WIDTH(MMIO_TID_WIDTH), + .ARADDR_WIDTH(MMIO_ADDR_WIDTH), + .RDATA_WIDTH(MMIO_DATA_WIDTH) + ).master axi, + virtual ofs_fim_pwrgoodn_if.master pgn, + input ofs_csr_reg_generic_attr_t check_reg_attr, + string check_reg_name, + input logic [19:0] reg_addr, + ref ofs_csr_reg_generic_t reset_reg, + ref ofs_csr_reg_generic_t update_reg + ); + super.new( + .axi(axi), + .pgn(pgn), + .check_reg_attr(check_reg_attr), + .check_reg_name(check_reg_name), + .reg_addr(reg_addr), + .reset_reg(reset_reg), + .update_reg(update_reg) + ); + this.wr_addr = reg_addr; + this.rd_addr = reg_addr; + this.walk_check = new(); + endfunction + + + virtual task check(); + int i; + //-------------------------------------------------- + // Walking Ones Test + //-------------------------------------------------- + for (i=0; i<64; i=i+1) + begin + shift_reg = 64'h0000_0000_0000_0001 << i; + walk_check = new(); + rdst = new( + .axi(axi), + .pgn(pgn), + .rd_addr(rd_addr), + .access(FULL64) + ); + rdst.run(); + walk_check.last_value = rdst.rd_data; + wr_data = shift_reg; + wrst = new( + .axi(axi), + .pgn(pgn), + .wr_addr(wr_addr), + .wr_data(wr_data), + .access(FULL64) + ); + wrst.run(); + rdst.run(); + walk_check.value = rdst.rd_data; + walk_check.check_time = $time; + walk_error = bit_check( + .check(walk_check) + ); + total_bit_error_count = total_bit_error_count + walk_error.error_count(); + walk_check.test_name = "walking-ones"; + walk_error.test_name = "walking-ones"; + tr = rdst; + tq.push_back(tr); + tr = wrst; + tq.push_back(tr); + bcq.push_back(walk_check); + beq.push_back(walk_error); + end + report_error_queue(); + //-------------------------------------------------- + // Walking Zeros Test + //-------------------------------------------------- + for (i=0; i<64; i=i+1) + begin + shift_reg = ~(64'h0000_0000_0000_0001 << i); + walk_check = new(); + rdst = new( + .axi(axi), + .pgn(pgn), + .rd_addr(rd_addr), + .access(FULL64) + ); + rdst.run(); + walk_check.last_value = rdst.rd_data; + wr_data = shift_reg; + wrst = new( + .axi(axi), + .pgn(pgn), + .wr_addr(wr_addr), + .wr_data(wr_data), + .access(FULL64) + ); + wrst.run(); + rdst.run(); + walk_check.value = rdst.rd_data; + walk_check.check_time = $time; + walk_error = bit_check( + .check(walk_check) + ); + total_bit_error_count = total_bit_error_count + walk_error.error_count(); + walk_check.test_name = "walking-zeros"; + walk_error.test_name = "walking-zeros"; + tr = rdst; + tq.push_back(tr); + tr = wrst; + tq.push_back(tr); + bcq.push_back(walk_check); + beq.push_back(walk_error); + end + report_error_queue(); + endtask + + + virtual task check_data( + input logic [63:0] write_value_passed + ); // Task does nothing with this class, but is kept for abstract base class compatibility. + endtask + + + virtual function BitErrorLog bit_check( + input BitCheckLog check + ); + int i; + BitErrorLog bit_checker; + bit_checker = new(); + for(i=0; i<64; i=i+1) + begin: bit_check_loop + case (check_reg_attr.data[i]) + RO: begin // All read-only bits should contain their update values. + if ((check.value[i] !== update_reg.data[i]) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = update_reg.data[i]; + end + end + RW, RWS, RWD: begin // All read-write bits should contain latest write data. + if ((check.value[i] !== wr_data[i]) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = wr_data[i]; + end + end + RW1C, RW1CS, RW1CD: begin // All Write-one-to-clear attributes behave the same out of reset. + if ((wr_data[i] == 1'b1) || (check.value[i] === 1'bx)) + begin + if ((update_reg.data[i] == 1'b1) || (check.value[i] === 1'bx)) // Due to clock delay after write, register will set if update is high. + begin + if ((check.value[i] !== 1'b1) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = 1'b1; + end + end + else + begin + if ((check.value[i] !== 1'b0) || (check.value[i] === 1'bx)) // Register must clear if update is low. + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = 1'b0; + end + end + end + else + begin + if ((update_reg.data[i] == 1'b1) || (check.value[i] === 1'bx)) // Register will be set if update is high. + begin + if ((check.value[i] !== 1'b1) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = 1'b1; + end + end + else + begin + if ((check.value[i] !== check.last_value[i]) || (check.value[i] === 1'bx)) // Inactive: Register should retain last value if write bit not set. + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = check.last_value[i]; + end + end + end + end + RW1S, RW1SS, RW1SD: begin // All Write-one-to-set attributes behave the same out of reset. + if ((wr_data[i] == 1'b1) || (check.value[i] === 1'bx)) + begin + if ((update_reg.data[i] == 1'b1) || (check.value[i] === 1'bx)) // Due to clock delay after write, register will clear if update is high. + begin + if ((check.value[i] !== 1'b0) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = 1'b0; + end + end + else + begin + if ((check.value[i] !== 1'b1) || (check.value[i] === 1'bx)) // Register must set if update is low. + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = 1'b1; + end + end + end + else + begin + if ((update_reg.data[i] == 1'b1) || (check.value[i] === 1'bx)) // Register will be clear if update is high. + begin + if ((check.value[i] !== 1'b0) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = 1'b0; + end + end + else + begin + if ((check.value[i] !== check.last_value[i]) || (check.value[i] === 1'bx)) //Inactive: Register should retain last value if write bit not set. + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = check.last_value[i]; + end + end + end + end + Rsvd, RsvdP: begin // These bits are don't cares. + end + RsvdZ: begin + if ((check.value[i] !== 1'b0) || (check.value[i] === 1'bx)) + begin + bit_checker.bit_pos[i] = 1'b1; + bit_checker.bit_expected[i] = 1'b0; + end + end + endcase + end: bit_check_loop + return bit_checker; + endfunction + + + virtual function logic pass(); + int i; + logic test_passes; + test_passes = 1'b1; + for (i=0; i 0) + begin + rand_num = n; + end + else + begin + $display("WARNING: Attempt to set Random Number Run Depth to:%0d in WriteRandomCheck Oject denied. Depth remains set to: %0d", n, rand_num); + end + endfunction + + + virtual function int get_run_depth(); + return rand_num; + endfunction + + + virtual task check(); + int i; + //-------------------------------------------------- + // Perform random pattern test. + //-------------------------------------------------- + for (i=0; i +# + +VCS_FILELIST="+incdir+$OFS_ROOTDIR/ofs-common/src/common/includes/ \ ++incdir+$OFS_ROOTDIR/src/includes/ \ +-v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v \ +-v $QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v \ +-v $QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v \ +-v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v \ +$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/tennm_atoms.sv \ +$QUARTUS_ROOTDIR/eda/sim_lib/synopsys/tennm_atoms_ncrypt.sv \ +$THE_PLATFORM/sim/scripts/qip_gen/ofs-common/src/common/fme_id_rom/fme_id_rom/rom_1port_2020/sim/fme_id_rom_rom_1port_2020_pcw7acy.v +$THE_PLATFORM/sim/scripts/qip_gen/ofs-common/src/common/fme_id_rom/fme_id_rom/sim/fme_id_rom.v \ +$OFS_ROOTDIR/ofs-common/src/common/includes/ofs_csr_pkg.sv \ +$OFS_ROOTDIR/ipss/pcie/rtl/ofs_fim_pcie_hdr_def.sv \ +$THE_PLATFORM/src/includes/ofs_fim_cfg_pkg.sv \ +$OFS_ROOTDIR/ofs-common/src/common/lib/mux/pf_vf_mux_pkg.sv \ +$OFS_ROOTDIR/src/afu_top/mux/top_cfg_pkg.sv \ +$OFS_ROOTDIR/ipss/pcie/rtl/ofs_fim_pcie_pkg.sv \ +$OFS_ROOTDIR/ofs-common/src/common/fme/fme_csr_pkg.sv \ +$OFS_ROOTDIR/ofs-common/src/common/includes/ofs_fim_if_pkg.sv \ +$OFS_ROOTDIR/ofs-common/src/common/includes/ofs_fim_pwrgoodn_if.sv \ +$OFS_ROOTDIR/ofs-common/src/common/includes/ofs_fim_axi_mmio_if.sv \ +$OFS_ROOTDIR/ofs-common/src/common/fme/fme_csr_io_if.sv \ +$OFS_ROOTDIR/ofs-common/src/common/fme/fme_csr.sv" diff --git a/sim/unit_test/fme_csr_directed/vcs_setup.sh b/sim/unit_test/fme_csr_directed/vcs_setup.sh new file mode 100644 index 0000000..4092328 --- /dev/null +++ b/sim/unit_test/fme_csr_directed/vcs_setup.sh @@ -0,0 +1,107 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_BASE_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="testbench_top" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_DIR/../../scripts" +SIM_DIR="$TEST_DIR/sim_vcs" +THE_PLATFORM=$OFS_ROOTDIR + +TEST_TBFILES_DIR=${TEST_BASE_DIR}/testbench + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${TEST_DIR}/../vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## + +TB_SRC="${TEST_TBFILES_DIR}/csr_transaction_class_pkg.sv \ + ${TEST_TBFILES_DIR}/test_csr_directed.sv \ + ${TEST_TBFILES_DIR}/testbench_top.sv" + +################################## +### AFU related verilog source ### +################################## +vcs -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + +define+R1_UNIT_TEST_ENV \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $VCS_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -top $TOP_LEVEL_NAME +error+20 -l vcs.log + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/fme_csr_directed/vcsmx_setup.sh b/sim/unit_test/fme_csr_directed/vcsmx_setup.sh new file mode 100755 index 0000000..3481f6e --- /dev/null +++ b/sim/unit_test/fme_csr_directed/vcsmx_setup.sh @@ -0,0 +1,116 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="testbench_top" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcsmx" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +# source ${SIM_ROOTDIR}/d5005/unit_test/scripts/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/csr_transaction_class_pkg.sv \ + ${TEST_BASE_DIR}/testbench/test_csr_directed.sv \ + ${TEST_BASE_DIR}/testbench/testbench_top.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlogan -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + +define+R1_UNIT_TEST_ENV \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $INC_DIR \ + $RTL_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC +error+1 -l vlog.log + +vcs -full64 -ntb_opts -licqueue +vcs+lic+wait \ + +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -l vcs.log $TOP_LEVEL_NAME + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/he_hssi_kpi_test/msim_setup.sh b/sim/unit_test/he_hssi_kpi_test/msim_setup.sh new file mode 100755 index 0000000..07f885f --- /dev/null +++ b/sim/unit_test/he_hssi_kpi_test/msim_setup.sh @@ -0,0 +1,115 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="-finish exit" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR="$TEST_SRC_DIR/../../.." +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="${TEST_DIR}/sim_msim" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for msim # +################################### +. ${SIM_DIR}/msim_filelist.sh + +################################## +### BFM related verilog source ### +################################## +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +${TEST_BASE_DIR}/testbench/test_param_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlib work +vlog -mfcu -timescale=1ns/1fs +libext+.v+.sv -lint -sv \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+HTILE \ + +define+R1_UNIT_TEST_ENV \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+MSIM_IOFS_D5005 \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + +define+R1_UNIT_TEST_ENV \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $MSIM_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -work work -l msim_vlog.log -suppress 8386,7033,7061,2388,12003,2892 +#suppress 8386 : Replication operator in Conactenation Operator +#suppress 2892 : Net type of 'clk' was not explicitly declared +#suppress 7061 : Variable 'clear_tdo_bit_select' driven in an always_ff block, may not be driven by any other process +#suppress 7033 : Variable 'parser_result' driven in a combinational block, may not be driven by any other process + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + vopt $TOP_LEVEL_NAME -o opt -suppress 2732,12003,7033,3837 -l msim_vopt.log + vsim -c opt -nosva -suppress 2732,12003,7033,3837 -do "add log -r /*; run -all ; quit -f" +fi + + diff --git a/sim/unit_test/he_hssi_kpi_test/readme.txt b/sim/unit_test/he_hssi_kpi_test/readme.txt new file mode 100755 index 0000000..887e2e2 --- /dev/null +++ b/sim/unit_test/he_hssi_kpi_test/readme.txt @@ -0,0 +1,69 @@ +***Test Description*** +This is the unit test for HE_HSSI. The test uses HE-HSSI to perform tx loopback between HE-HSSI and HSSI-SS. The data path is data from He-HSSI -> HSSI SS -> tx pin -> looped back in tb -> rx pin -> HSSI SS -> HE-HSSI. After traffic flow, this test calculates latency and throughput values. + +Description of test modules: + * test_csr_defs.sv - Defines HE-HSSI CSR addresses. + * tester_tests.sv - Defines all the test cases for current test. + * script/Makefile_VCS.mk - Script to run the test in VCS only + * script/Makefile.mk - Script to run the test in VCS & Questasim. MSIM_D5005=1 option to be given for Questasim else will be for VCS. + +***Running the test*** +To run the test in VCS: + 1) Make sure the shell environment is set up to run VCS/VCSMX. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Synopsys VCS simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_vcs + dve -full64 -vpd vcdplus.vpd & + +To run the test in QuestaSim: + 1) Make sure the shell environment is set up to run Questasim. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Mentor Graphics QuestaSim simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh MSIM=1 + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_msim + vsim -view vsim.wlf & diff --git a/sim/unit_test/he_hssi_kpi_test/scripts/run_sim.sh b/sim/unit_test/he_hssi_kpi_test/scripts/run_sim.sh new file mode 100755 index 0000000..271afc5 --- /dev/null +++ b/sim/unit_test/he_hssi_kpi_test/scripts/run_sim.sh @@ -0,0 +1,48 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)/.." + + +VCSMX=0 +MSIM=0 +SKIP_IP_CMP=0 +TEST_DIR=$(pwd) + +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh run_sim.sh SKIP_IP_CMP=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +# Source common sim setup script + +. ${TEST_DIR}/../../scripts/sim_setup_common.sh TEST_DIR="$TEST_DIR" VCSMX=$VCSMX MSIM=$MSIM + +# Run simulation +if [ $VCSMX -eq 1 ]; then + echo "Running VCSMX simulation in $TEST_DIR/sim_vcsmx" + cd ${TEST_DIR}/sim_vcsmx && sh ${TEST_SRC_DIR}/vcsmx_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +elif [ $MSIM -eq 1 ]; then + echo "Running Questasim simulation in $TEST_DIR/sim_msim" + cd ${TEST_DIR}/sim_msim && sh ${TEST_SRC_DIR}/msim_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="-l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="" +else + echo "Running VCS simulation in $TEST_DIR/sim_vcs" + cd ${TEST_DIR}/sim_vcs && sh ${TEST_SRC_DIR}/vcs_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +fi + + diff --git a/sim/unit_test/he_hssi_kpi_test/scripts/test_lib.svh b/sim/unit_test/he_hssi_kpi_test/scripts/test_lib.svh new file mode 100644 index 0000000..cf1be7d --- /dev/null +++ b/sim/unit_test/he_hssi_kpi_test/scripts/test_lib.svh @@ -0,0 +1,4 @@ +// Copyright (C) 2023 Intel Corporation +// SPDX-License-Identifier: MIT + +`include ".svh" diff --git a/sim/unit_test/he_hssi_kpi_test/scripts/test_list.f b/sim/unit_test/he_hssi_kpi_test/scripts/test_list.f new file mode 100755 index 0000000..23a8f97 --- /dev/null +++ b/sim/unit_test/he_hssi_kpi_test/scripts/test_list.f @@ -0,0 +1,2 @@ +$WORKDIR/sim/unit_test/he_hssi_kpi_test/testbench/test_csr_defs.sv +$WORKDIR/sim/unit_test/he_hssi_kpi_test/testbench/test_param_defs.sv diff --git a/sim/unit_test/he_hssi_kpi_test/testbench/test_csr_defs.sv b/sim/unit_test/he_hssi_kpi_test/testbench/test_csr_defs.sv new file mode 100755 index 0000000..4eda8ae --- /dev/null +++ b/sim/unit_test/he_hssi_kpi_test/testbench/test_csr_defs.sv @@ -0,0 +1,61 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// CSR addresses are defined for the testcase. +// +//----------------------------------------------------------------------------- +`ifndef __TEST_CSR_DEFS__ +`define __TEST_CSR_DEFS__ + +package test_csr_defs; + + // ****************************************************************************************** + // CSR Address Space + // ****************************************************************************************** + localparam HSSI_BASE_ADDR = 32'h30000; + localparam HE_HSSI_BASE_ADDR = 32'h180000; + localparam PORT_CONTROL = 32'h91038; + + // ****************************************************************************************** + // HE-HSSI CSR Address + // ****************************************************************************************** + parameter TG_PKT_LEN_ADDR = 32'hE034; // 'h380D + parameter TG_DATA_PATTERN_ADDR = 32'hE008; // 'h3802 + parameter TG_NUM_PKT_ADDR = 32'hE000; // 'h3800 + parameter TG_START_XFR_ADDR = 32'hE00C; // 'h3803 + parameter TG_END_TS_ADDR = 32'hE3D0; // 'h38F4 + + parameter TM_PKT_GOOD_ADDR = 32'hE404; // 'h3901 + parameter TM_PKT_BAD_ADDR = 32'hE408; // 'h3902 + parameter TM_START_TS_ADDR = 32'hE42C; // 'h390B + parameter TM_END_TS_ADDR = 32'hE430; // 'h390C + + /* + parameter TG_PKT_LEN_TYPE_ADDR = 32'h01; + parameter TG_DATA_PATTERN_ADDR = 32'h02; + parameter TG_STOP_XFR_ADDR = 32'h04; + parameter TG_SRC_MAC_L_ADDR = 32'h05; + parameter TG_SRC_MAC_H_ADDR = 32'h06; + parameter TG_DST_MAC_L_ADDR = 32'h07; + parameter TG_DST_MAC_H_ADDR = 32'h08; + parameter TG_PKT_XFRD_ADDR = 32'h09; + parameter TG_RANDOM_SEED0_ADDR = 32'h0A; + parameter TG_RANDOM_SEED1_ADDR = 32'h0B; + parameter TG_RANDOM_SEED2_ADDR = 32'h0C; + + parameter TM_NUM_PKT_ADDR = 32'h100; + parameter TM_BYTE_CNT0_ADDR = 32'h103; + parameter TM_BYTE_CNT1_ADDR = 32'h104; + parameter TM_AVST_RX_ERR_ADDR = 32'h107; + + parameter LOOPBACK_EN_ADDR = 32'h200; + */ + + + +endpackage + +`endif diff --git a/sim/unit_test/he_hssi_kpi_test/testbench/test_param_defs.sv b/sim/unit_test/he_hssi_kpi_test/testbench/test_param_defs.sv new file mode 100755 index 0000000..eabc221 --- /dev/null +++ b/sim/unit_test/he_hssi_kpi_test/testbench/test_param_defs.sv @@ -0,0 +1,89 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Test parameters +// +//----------------------------------------------------------------------------- +`ifndef __TEST_PARAM_DEFS__ +`define __TEST_PARAM_DEFS__ + +package test_param_defs; + + // ****************************************************************************************** + // Traffic Controller Register Values + // ****************************************************************************************** + parameter TG_NUM_PKT_VAL = 32'h80; // Number of packet to be transfered + parameter TG_PKT_LEN_TYPE_VAL = 32'h0000; // 1'b0: Fixed Length; 1'b1: Random length + parameter TG_DATA_PATTERN_VAL = 32'h0001; // 1'b0: Incremental pattern; 1'b1: Random pattern + parameter TG_PKT_LEN_VAL = 32'h84; // Length of each packet to be transfered + + parameter TRAFFIC_CTRL_CMD_ADDR = 32'h30; + parameter MB_ADDRESS_OFFSET = 32'h4; + parameter MB_RDDATA_OFFSET = 32'h8; + parameter MB_WRDATA_OFFSET = 32'hC; + parameter MB_NOOP = 32'h0; + parameter MB_RD = 32'h1; + parameter MB_WR = 32'h2; + parameter RX_STATISTICS_ADDR = 32'h3000; + parameter TX_STATISTICS_ADDR = 32'h7000; + parameter HSSI_RCFG_CMD_ADDR = 32'h28; + + // ****************************************************************************************** + // MAC Stat Parameters + // ****************************************************************************************** + parameter STATISTICS_framesOK_OFFSET = 32'h008; + parameter STATISTICS_framesErr_OFFSET = 32'h010; + parameter STATISTICS_framesCRCErr_OFFSET = 32'h018; + parameter STATISTICS_octetsOK_OFFSET = 32'h020; + parameter STATISTICS_pauseMACCtrlFrames_OFFSET = 32'h028; + parameter STATISTICS_ifErrors_OFFSET = 32'h030; + parameter STATISTICS_unicastFramesOK_OFFSET = 32'h038; + parameter STATISTICS_unicastFramesErr_OFFSET = 32'h040; + parameter STATISTICS_multicastFramesOK_OFFSET = 32'h048; + parameter STATISTICS_multicastFramesErr_OFFSET = 32'h050; + parameter STATISTICS_broadcastFramesOK_OFFSET = 32'h058; + parameter STATISTICS_broadcastFramesErr_OFFSET = 32'h060; + parameter STATISTICS_etherStatsOctets_OFFSET = 32'h068; + parameter STATISTICS_etherStatsPkts_OFFSET = 32'h070; + parameter STATISTICS_etherStatsUndersizePkts_OFFSET = 32'h078; + parameter STATISTICS_etherStatsOversizePkts_OFFSET = 32'h080; + parameter STATISTICS_etherStatsPkts64Octets_OFFSET = 32'h088; + parameter STATISTICS_etherStatsPkts65to127Octets_OFFSET = 32'h090; + parameter STATISTICS_etherStatsPkts128to255Octets_OFFSET = 32'h098; + parameter STATISTICS_etherStatsPkts256to511Octets_OFFSET = 32'h0A0; + parameter STATISTICS_etherStatsPkts512to1023Octets_OFFSET = 32'h0A8; + parameter STATISTICS_etherStatPkts1024to1518Octets_OFFSET = 32'h0B0; + parameter STATISTICS_etherStatsPkts1519toXOctets_OFFSET = 32'h0B8; + parameter STATISTICS_etherStatsFragments_OFFSET = 32'h0C0; + parameter STATISTICS_etherStatsJabbers_OFFSET = 32'h0C8; + parameter STATISTICS_etherStatsCRCErr_OFFSET = 32'h0D0; + parameter STATISTICS_unicastMACCtrlFrames_OFFSET = 32'h0D8; + parameter STATISTICS_multicastMACCtrlFrames_OFFSET = 32'h0E0; + parameter STATISTICS_broadcastMACCtrlFrames_OFFSET = 32'h0E8; + + // ****************************************************************************************** + // Parameters for KPI calculation + // ****************************************************************************************** + parameter USER_CLK_FREQ_MHZ = 156.25; // User clock @ HE-HSSI in MHz + parameter SAMPLE_PERIOD_NS = (1000 / USER_CLK_FREQ_MHZ); // sample period in nanoseconds + parameter FCS_SIZE_BYTE = 4; + parameter PREAMBLE_SIZE_BYTE = 7; + parameter SFD_SIZE_BYTE = 1; + parameter IPG_SIZE_BYTE = 12; + parameter OVERHEAD_SIZE_BYTE = FCS_SIZE_BYTE + PREAMBLE_SIZE_BYTE + SFD_SIZE_BYTE + IPG_SIZE_BYTE; + parameter ETH_SPEED = 10; // in GHz + `ifdef DISABLE_HE_HSSI_CRC + parameter DATA_PKT_SIZE = TG_PKT_LEN_VAL - 8.0; + `else + parameter DATA_PKT_SIZE = TG_PKT_LEN_VAL - 4.0; + `endif + parameter TOTAL_DATA_SIZE_BIT = DATA_PKT_SIZE * TG_NUM_PKT_VAL * 8; + parameter THEORETICAL_THROUGHPUT = (DATA_PKT_SIZE / (DATA_PKT_SIZE + OVERHEAD_SIZE_BYTE)); + parameter THEORETICAL_THROUGHPUT_GBPS = THEORETICAL_THROUGHPUT * ETH_SPEED; + +endpackage + +`endif diff --git a/sim/unit_test/he_hssi_kpi_test/testbench/tester_tests.sv b/sim/unit_test/he_hssi_kpi_test/testbench/tester_tests.sv new file mode 100755 index 0000000..2997375 --- /dev/null +++ b/sim/unit_test/he_hssi_kpi_test/testbench/tester_tests.sv @@ -0,0 +1,547 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// This file defines all the test cases for current test. +// +// main_test() is the main entry function which the tester calls +// to execute the unit tests. +// +//----------------------------------------------------------------------------- + +import test_csr_defs::*; +import test_param_defs::*; + +//------------------- +// Test utilities +//------------------- +task incr_test_id; +begin + test_id = test_id + 1; +end +endtask + +task post_test_util; + input logic [31:0] old_test_err_count; + logic result; +begin + if (test_utils::get_err_count() > old_test_err_count) begin + result = 1'b0; + end else begin + result = 1'b1; + end + + repeat (10) + @(posedge avl_clk); + + @(posedge avl_clk); + reset_test = 1'b1; + repeat (5) + @(posedge avl_clk); + reset_test = 1'b0; + + f_reset_tag(); + + if (result) begin + $display("\nTest status: OK"); + test_summary[test_id].result = 1'b1; + end else begin + $display("\nTest status: FAILED"); + test_summary[test_id].result = 1'b0; + end + incr_test_id(); +end +endtask + +task print_test_header; + input [1024*8-1:0] test_name; +begin + $display("\n********************************************"); + $display(" Running TEST(%0d) : %0s", test_id, test_name); + $display("********************************************"); + test_summary[test_id].name = test_name; +end +endtask + + +//------------------- +// Test cases +//------------------- + +// Mailbox write +task write_mailbox; + input logic [31:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [31:0] cmd_ctrl_addr; // Start address of mailbox access reg + input logic [31:0] addr; //Byte address + input logic [31:0] write_data32; + + //WRITE32(addr_mode, addr, bar, vf_active, pfn, vfn, data); + begin + #5000 WRITE32(ADDR32, cmd_ctrl_addr + MB_WRDATA_OFFSET, bar, vf_active, pfn, vfn, write_data32); + #5000 WRITE32(ADDR32, cmd_ctrl_addr + MB_ADDRESS_OFFSET, bar, vf_active, pfn, vfn, addr/4); + #5000 WRITE32(ADDR32, cmd_ctrl_addr, bar, vf_active, pfn, vfn, MB_WR); + #5000 read_ack_mailbox(bar, vf_active, pfn, vfn, cmd_ctrl_addr); + #5000 WRITE32(ADDR32, cmd_ctrl_addr, bar, vf_active, pfn, vfn, MB_NOOP); + $display("INFO: Wrote MAILBOX ADDR:%x, WRITE_DATA32:%X", addr, write_data32); + end +endtask + +// Mailbox read +task read_mailbox; + input logic [64:0] cur_pf_table; + input logic [31:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [31:0] cmd_ctrl_addr; // Start address of mailbox access reg + input logic [31:0] addr; //Byte address + output logic [64:0] rd_data64; + + logic error; + + begin + #5000 WRITE32(ADDR32, cmd_ctrl_addr + MB_ADDRESS_OFFSET, bar, vf_active, pfn, vfn, addr/4); // DW address + #5000 WRITE32(ADDR32, cmd_ctrl_addr, bar, vf_active, pfn, vfn, MB_RD); // read Cmd + #5000 read_ack_mailbox(bar, vf_active, pfn, vfn, cmd_ctrl_addr); + #5000 READ64(ADDR32, cmd_ctrl_addr + MB_RDDATA_OFFSET, bar, vf_active, pfn, vfn, rd_data64, error); + if (error) begin + $display("\nERROR: Mailbox read failed.\n"); + test_utils::incr_err_count(); + end + $display("INFO: Read MAILBOX ADDR:%x, READ_DATA32:%X", addr, rd_data64); + #5000 WRITE32(ADDR32, cmd_ctrl_addr, bar, vf_active, pfn, vfn, MB_NOOP); // no op Cmd + end +endtask + + +// Mailbox ack check +task read_ack_mailbox; + input logic [31:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [31:0] cmd_ctrl_addr; // Start address of mailbox access reg + logic [31:0] scratch1; + logic [4:0] rd_attempts; + logic ack_done; + logic error; + begin + scratch1 = 32'h0; + rd_attempts = 'b0; + ack_done = 1'h0; + + //$display("JB: vfa=%h, pfn = %h, vfn = %h", vf_active, pfn, vfn); + while (~ack_done && rd_attempts<15) begin + READ32(ADDR32, cmd_ctrl_addr, bar, vf_active, pfn, vfn, scratch1, error); + ack_done = scratch1[2]; + #100000 + rd_attempts=rd_attempts+1; + end + if (error || (~ack_done)) begin + $display("\nERROR: Mailbox Ack failed.\n"); + test_utils::incr_err_count(); + end + $display("Ack status: 0x%0x",ack_done); + end +endtask + +// Wait until all packets received back +task wait_for_all_eop_done; + input logic [31:0] num_pkt; + logic [31:0] pkt_cnt; + begin + pkt_cnt = 32'h0; + while (pkt_cnt < num_pkt) begin + @(posedge top_tb.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.GenBrdg[0].axis_to_avst_bridge_inst.avst_rx_st.rx.eop) + @(posedge top_tb.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.GenBrdg[0].axis_to_avst_bridge_inst.avst_rx_st.clk) + pkt_cnt=pkt_cnt+1; + $display("INFO: Packet received: %d", pkt_cnt); + end + $display("INFO:%t - RX EOP count is %d", $time, pkt_cnt); + end +endtask + +task automatic compare_eth_stats; + input logic [63:0] cur_pf_table; + input logic [31:0] addr1; + input logic [31:0] addr2; + output logic error; + output logic [63:0] framesOK_1; + output logic [63:0] framesOK_2; + // Statistic 1 + logic [63:0] framesOK_stat1; + logic [63:0] framesErr_stat1; + logic [63:0] framesCRCErr_stat1; + logic [63:0] octetsOK_stat1; + logic [63:0] pauseMACCtrlFrames_stat1; + logic [63:0] ifErrors_stat1; + logic [63:0] unicastFramesOK_stat1; + logic [63:0] unicastFramesErr_stat1; + logic [63:0] multicastFramesOK_stat1; + logic [63:0] multicastFramesErr_stat1; + logic [63:0] broadcastFramesOK_stat1; + logic [63:0] broadcastFramesErr_stat1; + logic [63:0] etherStatsOctets_stat1; + logic [63:0] etherStatsPkts_stat1; + logic [63:0] etherStatsUndersizePkts_stat1; + logic [63:0] etherStatsOversizePkts_stat1; + logic [63:0] etherStatsPkts64Octets_stat1; + logic [63:0] etherStatsPkts65to127Octets_stat1; + logic [63:0] etherStatsPkts128to255Octets_stat1; + logic [63:0] etherStatsPkts256to511Octet_stat1; + logic [63:0] etherStatsPkts512to1023Octets_stat1; + logic [63:0] etherStatsPkts1024to1518Octets_stat1; + logic [63:0] etherStatsPkts1519OtoXOctets_stat1; + logic [63:0] etherStatsFragments_stat1; + logic [63:0] etherStatsJabbers_stat1; + logic [63:0] etherStatsCRCErr_stat1; + logic [63:0] unicastMACCtrlFrames_stat1; + logic [63:0] multicastMACCtrlFrames_stat1; + logic [63:0] broadcastMACCtrlFrames_stat1; + // Statistic 2 + logic [63:0] framesOK_stat2; + logic [63:0] framesErr_stat2; + logic [63:0] framesCRCErr_stat2; + logic [63:0] octetsOK_stat2; + logic [63:0] pauseMACCtrlFrames_stat2; + logic [63:0] ifErrors_stat2; + logic [63:0] unicastFramesOK_stat2; + logic [63:0] unicastFramesErr_stat2; + logic [63:0] multicastFramesOK_stat2; + logic [63:0] multicastFramesErr_stat2; + logic [63:0] broadcastFramesOK_stat2; + logic [63:0] broadcastFramesErr_stat2; + logic [63:0] etherStatsOctets_stat2; + logic [63:0] etherStatsPkts_stat2; + logic [63:0] etherStatsUndersizePkts_stat2; + logic [63:0] etherStatsOversizePkts_stat2; + logic [63:0] etherStatsPkts64Octets_stat2; + logic [63:0] etherStatsPkts65to127Octets_stat2; + logic [63:0] etherStatsPkts128to255Octets_stat2; + logic [63:0] etherStatsPkts256to511Octet_stat2; + logic [63:0] etherStatsPkts512to1023Octets_stat2; + logic [63:0] etherStatsPkts1024to1518Octets_stat2; + logic [63:0] etherStatsPkts1519OtoXOctets_stat2; + logic [63:0] etherStatsFragments_stat2; + logic [63:0] etherStatsJabbers_stat2; + logic [63:0] etherStatsCRCErr_stat2; + logic [63:0] unicastMACCtrlFrames_stat2; + logic [63:0] multicastMACCtrlFrames_stat2; + logic [63:0] broadcastMACCtrlFrames_stat2; + + logic error_status = 0; + + // Read Statistic 1 + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_framesOK_OFFSET, framesOK_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_framesErr_OFFSET, framesErr_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_framesCRCErr_OFFSET, framesCRCErr_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_octetsOK_OFFSET, octetsOK_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_pauseMACCtrlFrames_OFFSET, pauseMACCtrlFrames_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_ifErrors_OFFSET, ifErrors_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_unicastFramesOK_OFFSET, unicastFramesOK_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_unicastFramesErr_OFFSET, unicastFramesErr_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_multicastFramesOK_OFFSET, multicastFramesOK_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_multicastFramesErr_OFFSET, multicastFramesErr_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_broadcastFramesOK_OFFSET, broadcastFramesOK_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_broadcastFramesErr_OFFSET, broadcastFramesErr_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsOctets_OFFSET, etherStatsOctets_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsPkts_OFFSET, etherStatsPkts_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsUndersizePkts_OFFSET, etherStatsUndersizePkts_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsOversizePkts_OFFSET, etherStatsOversizePkts_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsPkts64Octets_OFFSET, etherStatsPkts64Octets_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsPkts65to127Octets_OFFSET, etherStatsPkts65to127Octets_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsPkts128to255Octets_OFFSET, etherStatsPkts128to255Octets_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsPkts256to511Octets_OFFSET, etherStatsPkts256to511Octet_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsPkts512to1023Octets_OFFSET, etherStatsPkts512to1023Octets_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatPkts1024to1518Octets_OFFSET, etherStatsPkts1024to1518Octets_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsPkts1519toXOctets_OFFSET, etherStatsPkts1519OtoXOctets_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsFragments_OFFSET, etherStatsFragments_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsJabbers_OFFSET, etherStatsJabbers_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsCRCErr_OFFSET, etherStatsCRCErr_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_unicastMACCtrlFrames_OFFSET, unicastMACCtrlFrames_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_multicastMACCtrlFrames_OFFSET, multicastMACCtrlFrames_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_broadcastMACCtrlFrames_OFFSET, broadcastMACCtrlFrames_stat1); + + // Read Statistic 2 + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_framesOK_OFFSET, framesOK_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_framesErr_OFFSET, framesErr_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_framesCRCErr_OFFSET, framesCRCErr_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_octetsOK_OFFSET, octetsOK_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_pauseMACCtrlFrames_OFFSET, pauseMACCtrlFrames_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_ifErrors_OFFSET, ifErrors_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_unicastFramesOK_OFFSET, unicastFramesOK_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_unicastFramesErr_OFFSET, unicastFramesErr_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_multicastFramesOK_OFFSET, multicastFramesOK_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_multicastFramesErr_OFFSET, multicastFramesErr_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_broadcastFramesOK_OFFSET, broadcastFramesOK_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_broadcastFramesErr_OFFSET, broadcastFramesErr_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsOctets_OFFSET, etherStatsOctets_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsPkts_OFFSET, etherStatsPkts_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsUndersizePkts_OFFSET, etherStatsUndersizePkts_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsOversizePkts_OFFSET, etherStatsOversizePkts_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsPkts64Octets_OFFSET, etherStatsPkts64Octets_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsPkts65to127Octets_OFFSET, etherStatsPkts65to127Octets_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsPkts128to255Octets_OFFSET, etherStatsPkts128to255Octets_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsPkts256to511Octets_OFFSET, etherStatsPkts256to511Octet_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsPkts512to1023Octets_OFFSET, etherStatsPkts512to1023Octets_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatPkts1024to1518Octets_OFFSET, etherStatsPkts1024to1518Octets_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsPkts1519toXOctets_OFFSET, etherStatsPkts1519OtoXOctets_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsFragments_OFFSET, etherStatsFragments_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsJabbers_OFFSET, etherStatsJabbers_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsCRCErr_OFFSET, etherStatsCRCErr_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_unicastMACCtrlFrames_OFFSET, unicastMACCtrlFrames_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_multicastMACCtrlFrames_OFFSET, multicastMACCtrlFrames_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_broadcastMACCtrlFrames_OFFSET, broadcastMACCtrlFrames_stat2); + + // Display the collected statistics of the MAC + $display("\n-------------"); + $display("TX Statistics"); + $display("-------------"); + $display("\tframesOK = %0d", framesOK_stat1); + $display("\tframesErr = %0d", framesErr_stat1); + $display("\tframesCRCErr = %0d", framesCRCErr_stat1); + $display("\toctetsOK = %0d", octetsOK_stat1); + $display("\tpauseMACCtrlFrames = %0d", pauseMACCtrlFrames_stat1); + $display("\tifErrors = %0d", ifErrors_stat1); + $display("\tunicastFramesOK = %0d", unicastFramesOK_stat1); + $display("\tunicastFramesErr = %0d", unicastFramesErr_stat1); + $display("\tmulticastFramesOK = %0d", multicastFramesOK_stat1); + $display("\tmulticastFramesErr = %0d", multicastFramesErr_stat1); + $display("\tbroadcastFramesOK = %0d", broadcastFramesOK_stat1); + $display("\tbroadcastFramesErr = %0d", broadcastFramesErr_stat1); + $display("\tetherStatsOctets = %0d", etherStatsOctets_stat1); + $display("\tetherStatsPkts = %0d", etherStatsPkts_stat1); + $display("\tetherStatsUndersizePkts = %0d", etherStatsUndersizePkts_stat1); + $display("\tetherStatsOversizePkts = %0d", etherStatsOversizePkts_stat1); + $display("\tetherStatsPkts64Octets = %0d", etherStatsPkts64Octets_stat1); + $display("\tetherStatsPkts65to127Octets = %0d", etherStatsPkts65to127Octets_stat1); + $display("\tetherStatsPkts128to255Octets = %0d", etherStatsPkts128to255Octets_stat1); + $display("\tetherStatsPkts256to511Octet = %0d", etherStatsPkts256to511Octet_stat1); + $display("\tetherStatsPkts512to1023Octets = %0d", etherStatsPkts512to1023Octets_stat1); + $display("\tetherStatsPkts1024to1518Octets = %0d", etherStatsPkts1024to1518Octets_stat1); + $display("\tetherStatsPkts1519OtoXOctets = %0d", etherStatsPkts1519OtoXOctets_stat1); + $display("\tetherStatsFragments = %0d", etherStatsFragments_stat1); + $display("\tetherStatsJabbers = %0d", etherStatsJabbers_stat1); + $display("\tetherStatsCRCErr = %0d", etherStatsCRCErr_stat1); + $display("\tunicastMACCtrlFrames = %0d", unicastMACCtrlFrames_stat1); + $display("\tmulticastMACCtrlFrames = %0d", multicastMACCtrlFrames_stat1); + $display("\tbroadcastMACCtrlFrames = %0d", broadcastMACCtrlFrames_stat1); + + $display("\n-------------"); + $display("RX Statistics"); + $display("-------------"); + $display("\tframesOK = %0d", framesOK_stat2); + $display("\tframesErr = %0d", framesErr_stat2); + $display("\tframesCRCErr = %0d", framesCRCErr_stat2); + $display("\toctetsOK = %0d", octetsOK_stat2); + $display("\tpauseMACCtrlFrames = %0d", pauseMACCtrlFrames_stat2); + $display("\tifErrors = %0d", ifErrors_stat2); + $display("\tunicastFramesOK = %0d", unicastFramesOK_stat2); + $display("\tunicastFramesErr = %0d", unicastFramesErr_stat2); + $display("\tmulticastFramesOK = %0d", multicastFramesOK_stat2); + $display("\tmulticastFramesErr = %0d", multicastFramesErr_stat2); + $display("\tbroadcastFramesOK = %0d", broadcastFramesOK_stat2); + $display("\tbroadcastFramesErr = %0d", broadcastFramesErr_stat2); + $display("\tetherStatsOctets = %0d", etherStatsOctets_stat2); + $display("\tetherStatsPkts = %0d", etherStatsPkts_stat2); + $display("\tetherStatsUndersizePkts = %0d", etherStatsUndersizePkts_stat2); + $display("\tetherStatsOversizePkts = %0d", etherStatsOversizePkts_stat2); + $display("\tetherStatsPkts64Octets = %0d", etherStatsPkts64Octets_stat2); + $display("\tetherStatsPkts65to127Octets = %0d", etherStatsPkts65to127Octets_stat2); + $display("\tetherStatsPkts128to255Octets = %0d", etherStatsPkts128to255Octets_stat2); + $display("\tetherStatsPkts256to511Octet = %0d", etherStatsPkts256to511Octet_stat2); + $display("\tetherStatsPkts512to1023Octets = %0d", etherStatsPkts512to1023Octets_stat2); + $display("\tetherStatsPkts1024to1518Octets = %0d", etherStatsPkts1024to1518Octets_stat2); + $display("\tetherStatsPkts1519OtoXOctets = %0d", etherStatsPkts1519OtoXOctets_stat2); + $display("\tetherStatsFragments = %0d", etherStatsFragments_stat2); + $display("\tetherStatsJabbers = %0d", etherStatsJabbers_stat2); + $display("\tetherStatsCRCErr = %0d", etherStatsCRCErr_stat2); + $display("\tunicastMACCtrlFrames = %0d", unicastMACCtrlFrames_stat2); + $display("\tmulticastMACCtrlFrames = %0d", multicastMACCtrlFrames_stat2); + $display("\tbroadcastMACCtrlFrames = %0d", broadcastMACCtrlFrames_stat2); + + // Check for err statistic for stat1, must be 0 + if(framesErr_stat1 != 0 || framesCRCErr_stat1 != 0 || ifErrors_stat1 != 0 || unicastFramesErr_stat1 != 0 || + multicastFramesErr_stat1 != 0 || broadcastFramesErr_stat1 != 0 || etherStatsCRCErr_stat1 != 0) begin + error_status = 1; + end + + // Check for err statistic for stat2, must be 0 + if(framesErr_stat2 != 0 || framesCRCErr_stat2 != 0 || ifErrors_stat2 != 0 || unicastFramesErr_stat2 != 0 || + multicastFramesErr_stat2 != 0 || broadcastFramesErr_stat2 != 0 || etherStatsCRCErr_stat2 != 0) begin + error_status = 1; + end + + // Compare non-err statistic between stat1 & stat2, they must be equal + if(framesOK_stat1 != framesOK_stat2 || octetsOK_stat1 != octetsOK_stat2 || pauseMACCtrlFrames_stat1 != pauseMACCtrlFrames_stat2 || + unicastFramesOK_stat1 != unicastFramesOK_stat2 || multicastFramesOK_stat1 != multicastFramesOK_stat2 || broadcastFramesOK_stat1 != broadcastFramesOK_stat2 || + etherStatsOctets_stat1 != etherStatsOctets_stat2 || etherStatsPkts_stat1 != etherStatsPkts_stat2 || etherStatsUndersizePkts_stat1 != etherStatsUndersizePkts_stat2 || + etherStatsOversizePkts_stat1 != etherStatsOversizePkts_stat2 || etherStatsPkts64Octets_stat1 != etherStatsPkts64Octets_stat2 || + etherStatsPkts65to127Octets_stat1 != etherStatsPkts65to127Octets_stat2 || etherStatsPkts128to255Octets_stat1 != etherStatsPkts128to255Octets_stat2 || + etherStatsPkts256to511Octet_stat1 != etherStatsPkts256to511Octet_stat2 || etherStatsPkts512to1023Octets_stat1 != etherStatsPkts512to1023Octets_stat2 || + etherStatsPkts1024to1518Octets_stat1 != etherStatsPkts1024to1518Octets_stat2 || etherStatsPkts1519OtoXOctets_stat1 != etherStatsPkts1519OtoXOctets_stat2 || + etherStatsFragments_stat1 != etherStatsFragments_stat2 || etherStatsJabbers_stat1 != etherStatsJabbers_stat2 || + unicastMACCtrlFrames_stat1 != unicastMACCtrlFrames_stat2 || multicastMACCtrlFrames_stat1 != multicastMACCtrlFrames_stat2 || + broadcastMACCtrlFrames_stat1 != broadcastMACCtrlFrames_stat2) begin + error_status = 1; + end + + framesOK_1 = framesOK_stat1; + framesOK_2 = framesOK_stat2; + error = error_status; + +endtask : compare_eth_stats + + +task test_traffic; + input access32; + logic [63:0] cur_pf_table; + logic [63:0] framesOK_1,framesOK_2; + static logic tx_rx_mismatch = 0; + static logic RD_MAC_STATS_EN = 1; + logic [63:0] scratch1,scratch2; + logic [31:0] scratch32; + + + begin + $display("Entering sequence!"); + #36000ns // Wait for HSSI initialization in MAC and PHY + + //Set packet length + write_mailbox(0, 1, 0, 2, HE_HSSI_BASE_ADDR+TRAFFIC_CTRL_CMD_ADDR, TG_PKT_LEN_ADDR, TG_PKT_LEN_VAL); + //Set Random payload + write_mailbox(0, 1, 0, 2, HE_HSSI_BASE_ADDR+TRAFFIC_CTRL_CMD_ADDR, TG_DATA_PATTERN_ADDR, TG_DATA_PATTERN_VAL); + //Set number of packets + write_mailbox(0, 1, 0, 2, HE_HSSI_BASE_ADDR+TRAFFIC_CTRL_CMD_ADDR, TG_NUM_PKT_ADDR, TG_NUM_PKT_VAL); // num of packets + //Set start to send packets + write_mailbox(0, 1, 0, 2, HE_HSSI_BASE_ADDR+TRAFFIC_CTRL_CMD_ADDR, TG_START_XFR_ADDR, 32'h1); + + //wait_for_all_eop_done(TG_START_XFR_ADDR); + #50000ns // To allow enough time to receive all the packets on rx. + + // Good packet received at Traffic monitor + read_mailbox(cur_pf_table, 0, 1, 0, 2, HE_HSSI_BASE_ADDR + TRAFFIC_CTRL_CMD_ADDR, TM_PKT_GOOD_ADDR, scratch1); + scratch32 = scratch1[31:0]; + if (scratch32 != TG_NUM_PKT_VAL) begin + $display("\nError: Received good packets does not match Transmitted packets!\n"); + $display("Number of Good Packets Received: \tExpected: %0d\n \tRead:%0d", TG_NUM_PKT_VAL, scratch32); + test_utils::incr_err_count(); + end else begin + $display("INFO: Number of Good Packets Received:%0d", scratch32); + end + + // Bad packet received at Traffic monitor + read_mailbox(cur_pf_table, 0, 1, 0, 2, HE_HSSI_BASE_ADDR + TRAFFIC_CTRL_CMD_ADDR, TM_PKT_BAD_ADDR, scratch1); + scratch32 = scratch1[31:0]; + if (scratch32 != 32'h0) begin + $display("\nError: Received bad packets > 0!\n"); + $display("Number of Bad Packets Received: \tExpected: %0d\n \tRead: %0d",32'h0,scratch32); + test_utils::incr_err_count(); + end else begin + $display("INFO: Number of Bad Packets Received:%0d", scratch32); + end + + // Check MAC Stats + if(RD_MAC_STATS_EN) begin + compare_eth_stats(cur_pf_table, HSSI_BASE_ADDR + TX_STATISTICS_ADDR, HSSI_BASE_ADDR + RX_STATISTICS_ADDR, tx_rx_mismatch, framesOK_1, framesOK_2); + if(tx_rx_mismatch) begin + $display("\nERROR: RX MAC statistic does not match TX MAC statistic."); + test_utils::incr_err_count(); + end + else begin + if(framesOK_1 != TG_NUM_PKT_VAL || framesOK_2 != TG_NUM_PKT_VAL) begin + $display("\nERROR: framesOK size in MAC statistic does not match FRAMESOK_SIZE defined in testcase."); + test_utils::incr_err_count(); + end + end + end + + $display("Exiting sequence!"); + end +endtask + + +// HSSI Traffic test +task traffic_test; + input logic access32; + logic [31:0] old_test_err_count; + begin + print_test_header("traffic_test"); + old_test_err_count = test_utils::get_err_count(); + + // Wait for ready before starting the test + assert_afu_reset(PORT_CONTROL); + deassert_afu_reset(PORT_CONTROL); + + test_traffic(access32); + + post_test_util(old_test_err_count); + end +endtask + +// HSSI key performance indicator test +task hssi_kpi_test; + logic [31:0] old_test_err_count; + logic [63:0] cur_pf_table; + logic [31:0] tx_end_time_stamp; + logic [31:0] rx_start_time_stamp; + logic [31:0] rx_end_time_stamp; + real tx_end_time_stamp_ns; + real rx_start_time_stamp_ns; + real rx_end_time_stamp_ns; + real latency_max_ns; + real latency_min_ns; + real total_tx_duration_ns; + real total_rx_duration_ns; + real achived_tx_throughput_gbps; + real achived_rx_throughput_gbps; + real achived_tx_throughput; + real achived_rx_throughput; + real tx_throughput_deviation_percent; + real rx_throughput_deviation_percent; + begin + print_test_header("hssi_kpi_test"); + old_test_err_count = test_utils::get_err_count(); + + // Convert time stamp register values from clock to nano seconds + read_mailbox(cur_pf_table, 0, 1, 0, 2, HE_HSSI_BASE_ADDR + TRAFFIC_CTRL_CMD_ADDR, TG_END_TS_ADDR, tx_end_time_stamp); + read_mailbox(cur_pf_table, 0, 1, 0, 2, HE_HSSI_BASE_ADDR + TRAFFIC_CTRL_CMD_ADDR, TM_START_TS_ADDR, rx_start_time_stamp); + read_mailbox(cur_pf_table, 0, 1, 0, 2, HE_HSSI_BASE_ADDR + TRAFFIC_CTRL_CMD_ADDR, TM_END_TS_ADDR, rx_end_time_stamp); + tx_end_time_stamp_ns = tx_end_time_stamp * SAMPLE_PERIOD_NS; + rx_start_time_stamp_ns = rx_start_time_stamp * SAMPLE_PERIOD_NS; + rx_end_time_stamp_ns = rx_end_time_stamp * SAMPLE_PERIOD_NS; + + // Latency calculation + latency_max_ns = rx_start_time_stamp_ns; // Latency between first packet sop of rx and tx in nanoseconds + $display("Latency between first packet sop of rx and tx : \t%0f ns",latency_max_ns); + latency_min_ns = rx_end_time_stamp_ns - tx_end_time_stamp_ns; // Latency between last packet eop of rx and tx in nanoseconds + $display("Latency between last packet eop of rx and tx : \t%0f ns",latency_min_ns); + + // Calculate Rx and Tx throughput achieved + total_tx_duration_ns = tx_end_time_stamp_ns; + total_rx_duration_ns = rx_end_time_stamp_ns - rx_start_time_stamp_ns; + achived_tx_throughput_gbps = (TOTAL_DATA_SIZE_BIT / total_tx_duration_ns); + $display("Achieve Tx throughput : \t%0f Gbps",achived_tx_throughput_gbps); + achived_rx_throughput_gbps = (TOTAL_DATA_SIZE_BIT / total_rx_duration_ns); + $display("Achieve Rx throughput : \t%0f Gbps",achived_rx_throughput_gbps); + + post_test_util(old_test_err_count); + end +endtask + +//------------------- +// Test main entry +//------------------- +task main_test; + output logic test_result; + logic valid_csr_region; +begin + traffic_test (1); // Pass 1 for 32-bit access to mailbox, 0 for 64-bit + hssi_kpi_test(); +end +endtask diff --git a/sim/unit_test/he_hssi_kpi_test/vcs_setup.sh b/sim/unit_test/he_hssi_kpi_test/vcs_setup.sh new file mode 100644 index 0000000..6d94fe8 --- /dev/null +++ b/sim/unit_test/he_hssi_kpi_test/vcs_setup.sh @@ -0,0 +1,111 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcs" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +# source ${SIM_ROOTDIR}/d5005/unit_test/scripts/vcs_filelist.sh +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +${TEST_BASE_DIR}/testbench/test_param_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vcs -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + +define+R1_UNIT_TEST_ENV \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $VCS_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -top $TOP_LEVEL_NAME +error+20 -l vcs.log + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/he_hssi_kpi_test/vcsmx_setup.sh b/sim/unit_test/he_hssi_kpi_test/vcsmx_setup.sh new file mode 100755 index 0000000..fa4488e --- /dev/null +++ b/sim/unit_test/he_hssi_kpi_test/vcsmx_setup.sh @@ -0,0 +1,116 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcsmx" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +# source ${SIM_ROOTDIR}/d5005/unit_test/scripts/vcs_filelist.sh +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +${TEST_BASE_DIR}/testbench/test_param_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlogan -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + +define+R1_UNIT_TEST_ENV \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $INC_DIR \ + $RTL_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC +error+1 -l vlog.log + +vcs -full64 -ntb_opts -licqueue +vcs+lic+wait \ + +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -l vcs.log $TOP_LEVEL_NAME + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/he_hssi_lpbk_test/msim_setup.sh b/sim/unit_test/he_hssi_lpbk_test/msim_setup.sh new file mode 100755 index 0000000..07f885f --- /dev/null +++ b/sim/unit_test/he_hssi_lpbk_test/msim_setup.sh @@ -0,0 +1,115 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="-finish exit" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR="$TEST_SRC_DIR/../../.." +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="${TEST_DIR}/sim_msim" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for msim # +################################### +. ${SIM_DIR}/msim_filelist.sh + +################################## +### BFM related verilog source ### +################################## +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +${TEST_BASE_DIR}/testbench/test_param_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlib work +vlog -mfcu -timescale=1ns/1fs +libext+.v+.sv -lint -sv \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+HTILE \ + +define+R1_UNIT_TEST_ENV \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+MSIM_IOFS_D5005 \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + +define+R1_UNIT_TEST_ENV \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $MSIM_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -work work -l msim_vlog.log -suppress 8386,7033,7061,2388,12003,2892 +#suppress 8386 : Replication operator in Conactenation Operator +#suppress 2892 : Net type of 'clk' was not explicitly declared +#suppress 7061 : Variable 'clear_tdo_bit_select' driven in an always_ff block, may not be driven by any other process +#suppress 7033 : Variable 'parser_result' driven in a combinational block, may not be driven by any other process + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + vopt $TOP_LEVEL_NAME -o opt -suppress 2732,12003,7033,3837 -l msim_vopt.log + vsim -c opt -nosva -suppress 2732,12003,7033,3837 -do "add log -r /*; run -all ; quit -f" +fi + + diff --git a/sim/unit_test/he_hssi_lpbk_test/readme.txt b/sim/unit_test/he_hssi_lpbk_test/readme.txt new file mode 100644 index 0000000..86faf7a --- /dev/null +++ b/sim/unit_test/he_hssi_lpbk_test/readme.txt @@ -0,0 +1,69 @@ +***Test Description*** +This is the unit test for HE_HSSI. The test uses HE-HSSI to perform tx loopback between HE-HSSI and HSSI-SS. + +Description of test modules: + * test_csr_defs.sv - Defines HE-HSSI CSR addresses. + * tester_tests.sv - Defines all the test cases for current test. + * script/Makefile_VCS.mk - Script to run the test in VCS only + * script/Makefile.mk - Script to run the test in VCS & Questasim. MSIM_D5005=1 option to be given for Questasim else will be for VCS. + +***Running the test*** +To run the test in VCS: + 1) Make sure the shell environment is set up to run VCS/VCSMX. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Synopsys VCS simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_vcs + dve -full64 -vpd vcdplus.vpd & + +To run the test in QuestaSim: + 1) Make sure the shell environment is set up to run Questasim. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Mentor Graphics QuestaSim simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh MSIM=1 + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_msim + vsim -view vsim.wlf & diff --git a/sim/unit_test/he_hssi_lpbk_test/scripts/run_sim.sh b/sim/unit_test/he_hssi_lpbk_test/scripts/run_sim.sh new file mode 100755 index 0000000..271afc5 --- /dev/null +++ b/sim/unit_test/he_hssi_lpbk_test/scripts/run_sim.sh @@ -0,0 +1,48 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)/.." + + +VCSMX=0 +MSIM=0 +SKIP_IP_CMP=0 +TEST_DIR=$(pwd) + +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh run_sim.sh SKIP_IP_CMP=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +# Source common sim setup script + +. ${TEST_DIR}/../../scripts/sim_setup_common.sh TEST_DIR="$TEST_DIR" VCSMX=$VCSMX MSIM=$MSIM + +# Run simulation +if [ $VCSMX -eq 1 ]; then + echo "Running VCSMX simulation in $TEST_DIR/sim_vcsmx" + cd ${TEST_DIR}/sim_vcsmx && sh ${TEST_SRC_DIR}/vcsmx_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +elif [ $MSIM -eq 1 ]; then + echo "Running Questasim simulation in $TEST_DIR/sim_msim" + cd ${TEST_DIR}/sim_msim && sh ${TEST_SRC_DIR}/msim_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="-l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="" +else + echo "Running VCS simulation in $TEST_DIR/sim_vcs" + cd ${TEST_DIR}/sim_vcs && sh ${TEST_SRC_DIR}/vcs_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +fi + + diff --git a/sim/unit_test/he_hssi_lpbk_test/scripts/test_list.f b/sim/unit_test/he_hssi_lpbk_test/scripts/test_list.f new file mode 100644 index 0000000..606df90 --- /dev/null +++ b/sim/unit_test/he_hssi_lpbk_test/scripts/test_list.f @@ -0,0 +1,2 @@ +$WORKDIR/sim/unit_test/he_hssi_lpbk_test/testbench/test_csr_defs.sv +$WORKDIR/sim/unit_test/he_hssi_lpbk_test/testbench/test_param_defs.sv diff --git a/sim/unit_test/he_hssi_lpbk_test/testbench/test_csr_defs.sv b/sim/unit_test/he_hssi_lpbk_test/testbench/test_csr_defs.sv new file mode 100644 index 0000000..eb891b5 --- /dev/null +++ b/sim/unit_test/he_hssi_lpbk_test/testbench/test_csr_defs.sv @@ -0,0 +1,58 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// CSR addresses are defined for the testcase. +// +//----------------------------------------------------------------------------- +`ifndef __TEST_CSR_DEFS__ +`define __TEST_CSR_DEFS__ + +package test_csr_defs; + + // ****************************************************************************************** + // CSR Address Space + // ****************************************************************************************** + localparam HSSI_BASE_ADDR = 32'h30000; + localparam HE_HSSI_BASE_ADDR = 32'h180000; + localparam PORT_CONTROL = 32'h91038; + + // ****************************************************************************************** + // HE-HSSI CSR Address + // ****************************************************************************************** + parameter TG_PKT_LEN_ADDR = 32'hE034; // 'h380D + parameter TG_DATA_PATTERN_ADDR = 32'hE008; // 'h3802 + parameter TG_NUM_PKT_ADDR = 32'hE000; // 'h3800 + parameter TG_START_XFR_ADDR = 32'hE00C; // 'h3803 + + parameter TM_PKT_GOOD_ADDR = 32'hE404; // 'h3901 + parameter TM_PKT_BAD_ADDR = 32'hE408; // 'h3902 + + /* + parameter TG_PKT_LEN_TYPE_ADDR = 32'h01; + parameter TG_DATA_PATTERN_ADDR = 32'h02; + parameter TG_STOP_XFR_ADDR = 32'h04; + parameter TG_SRC_MAC_L_ADDR = 32'h05; + parameter TG_SRC_MAC_H_ADDR = 32'h06; + parameter TG_DST_MAC_L_ADDR = 32'h07; + parameter TG_DST_MAC_H_ADDR = 32'h08; + parameter TG_PKT_XFRD_ADDR = 32'h09; + parameter TG_RANDOM_SEED0_ADDR = 32'h0A; + parameter TG_RANDOM_SEED1_ADDR = 32'h0B; + parameter TG_RANDOM_SEED2_ADDR = 32'h0C; + + parameter TM_NUM_PKT_ADDR = 32'h100; + parameter TM_BYTE_CNT0_ADDR = 32'h103; + parameter TM_BYTE_CNT1_ADDR = 32'h104; + parameter TM_AVST_RX_ERR_ADDR = 32'h107; + + parameter LOOPBACK_EN_ADDR = 32'h200; + */ + + + +endpackage + +`endif diff --git a/sim/unit_test/he_hssi_lpbk_test/testbench/test_param_defs.sv b/sim/unit_test/he_hssi_lpbk_test/testbench/test_param_defs.sv new file mode 100755 index 0000000..9ebfbb1 --- /dev/null +++ b/sim/unit_test/he_hssi_lpbk_test/testbench/test_param_defs.sv @@ -0,0 +1,70 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// Test parameters +// +//----------------------------------------------------------------------------- +`ifndef __TEST_PARAM_DEFS__ +`define __TEST_PARAM_DEFS__ + +package test_param_defs; + + // ****************************************************************************************** + // Traffic Controller Register Values + // ****************************************************************************************** + parameter TG_NUM_PKT_VAL = 32'h20; // Number of packet to be transfered + parameter TG_PKT_LEN_TYPE_VAL = 32'h0000; // 1'b0: Fixed Length; 1'b1: Random length + parameter TG_DATA_PATTERN_VAL = 32'h0001; // 1'b0: Incremental pattern; 1'b1: Random pattern + parameter TG_PKT_LEN_VAL = 32'h42; // Length of each packet to be transfered + + parameter TRAFFIC_CTRL_CMD_ADDR = 32'h30; + parameter MB_ADDRESS_OFFSET = 32'h4; + parameter MB_RDDATA_OFFSET = 32'h8; + parameter MB_WRDATA_OFFSET = 32'hC; + parameter MB_NOOP = 32'h0; + parameter MB_RD = 32'h1; + parameter MB_WR = 32'h2; + parameter RX_STATISTICS_ADDR = 32'h3000; + parameter TX_STATISTICS_ADDR = 32'h7000; + parameter HSSI_RCFG_CMD_ADDR = 32'h28; + + // ****************************************************************************************** + // MAC Stat Parameters + // ****************************************************************************************** + parameter STATISTICS_framesOK_OFFSET = 32'h008; + parameter STATISTICS_framesErr_OFFSET = 32'h010; + parameter STATISTICS_framesCRCErr_OFFSET = 32'h018; + parameter STATISTICS_octetsOK_OFFSET = 32'h020; + parameter STATISTICS_pauseMACCtrlFrames_OFFSET = 32'h028; + parameter STATISTICS_ifErrors_OFFSET = 32'h030; + parameter STATISTICS_unicastFramesOK_OFFSET = 32'h038; + parameter STATISTICS_unicastFramesErr_OFFSET = 32'h040; + parameter STATISTICS_multicastFramesOK_OFFSET = 32'h048; + parameter STATISTICS_multicastFramesErr_OFFSET = 32'h050; + parameter STATISTICS_broadcastFramesOK_OFFSET = 32'h058; + parameter STATISTICS_broadcastFramesErr_OFFSET = 32'h060; + parameter STATISTICS_etherStatsOctets_OFFSET = 32'h068; + parameter STATISTICS_etherStatsPkts_OFFSET = 32'h070; + parameter STATISTICS_etherStatsUndersizePkts_OFFSET = 32'h078; + parameter STATISTICS_etherStatsOversizePkts_OFFSET = 32'h080; + parameter STATISTICS_etherStatsPkts64Octets_OFFSET = 32'h088; + parameter STATISTICS_etherStatsPkts65to127Octets_OFFSET = 32'h090; + parameter STATISTICS_etherStatsPkts128to255Octets_OFFSET = 32'h098; + parameter STATISTICS_etherStatsPkts256to511Octets_OFFSET = 32'h0A0; + parameter STATISTICS_etherStatsPkts512to1023Octets_OFFSET = 32'h0A8; + parameter STATISTICS_etherStatPkts1024to1518Octets_OFFSET = 32'h0B0; + parameter STATISTICS_etherStatsPkts1519toXOctets_OFFSET = 32'h0B8; + parameter STATISTICS_etherStatsFragments_OFFSET = 32'h0C0; + parameter STATISTICS_etherStatsJabbers_OFFSET = 32'h0C8; + parameter STATISTICS_etherStatsCRCErr_OFFSET = 32'h0D0; + parameter STATISTICS_unicastMACCtrlFrames_OFFSET = 32'h0D8; + parameter STATISTICS_multicastMACCtrlFrames_OFFSET = 32'h0E0; + parameter STATISTICS_broadcastMACCtrlFrames_OFFSET = 32'h0E8; + + +endpackage + +`endif diff --git a/sim/unit_test/he_hssi_lpbk_test/testbench/tester_tests.sv b/sim/unit_test/he_hssi_lpbk_test/testbench/tester_tests.sv new file mode 100644 index 0000000..3606177 --- /dev/null +++ b/sim/unit_test/he_hssi_lpbk_test/testbench/tester_tests.sv @@ -0,0 +1,494 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// This file defines all the test cases for current test. +// +// main_test() is the main entry function which the tester calls +// to execute the unit tests. +// +//----------------------------------------------------------------------------- + +import test_csr_defs::*; +import test_param_defs::*; + +//------------------- +// Test utilities +//------------------- +task incr_test_id; +begin + test_id = test_id + 1; +end +endtask + +task post_test_util; + input logic [31:0] old_test_err_count; + logic result; +begin + if (test_utils::get_err_count() > old_test_err_count) begin + result = 1'b0; + end else begin + result = 1'b1; + end + + repeat (10) + @(posedge avl_clk); + + @(posedge avl_clk); + reset_test = 1'b1; + repeat (5) + @(posedge avl_clk); + reset_test = 1'b0; + + f_reset_tag(); + + if (result) begin + $display("\nTest status: OK"); + test_summary[test_id].result = 1'b1; + end else begin + $display("\nTest status: FAILED"); + test_summary[test_id].result = 1'b0; + end + incr_test_id(); +end +endtask + +task print_test_header; + input [1024*8-1:0] test_name; +begin + $display("\n********************************************"); + $display(" Running TEST(%0d) : %0s", test_id, test_name); + $display("********************************************"); + test_summary[test_id].name = test_name; +end +endtask + + +//------------------- +// Test cases +//------------------- + +// Mailbox write +task write_mailbox; + input logic [31:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [31:0] cmd_ctrl_addr; // Start address of mailbox access reg + input logic [31:0] addr; //Byte address + input logic [31:0] write_data32; + + //WRITE32(addr_mode, addr, bar, vf_active, pfn, vfn, data); + begin + #5000 WRITE32(ADDR32, cmd_ctrl_addr + MB_WRDATA_OFFSET, bar, vf_active, pfn, vfn, write_data32); + #5000 WRITE32(ADDR32, cmd_ctrl_addr + MB_ADDRESS_OFFSET, bar, vf_active, pfn, vfn, addr/4); + #5000 WRITE32(ADDR32, cmd_ctrl_addr, bar, vf_active, pfn, vfn, MB_WR); + #5000 read_ack_mailbox(bar, vf_active, pfn, vfn, cmd_ctrl_addr); + #5000 WRITE32(ADDR32, cmd_ctrl_addr, bar, vf_active, pfn, vfn, MB_NOOP); + $display("INFO: Wrote MAILBOX ADDR:%x, WRITE_DATA32:%X", addr, write_data32); + end +endtask + +// Mailbox read +task read_mailbox; + input logic [64:0] cur_pf_table; + input logic [31:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [31:0] cmd_ctrl_addr; // Start address of mailbox access reg + input logic [31:0] addr; //Byte address + output logic [64:0] rd_data64; + + logic error; + + begin + #5000 WRITE32(ADDR32, cmd_ctrl_addr + MB_ADDRESS_OFFSET, bar, vf_active, pfn, vfn, addr/4); // DW address + #5000 WRITE32(ADDR32, cmd_ctrl_addr, bar, vf_active, pfn, vfn, MB_RD); // read Cmd + #5000 read_ack_mailbox(bar, vf_active, pfn, vfn, cmd_ctrl_addr); + #5000 READ64(ADDR32, cmd_ctrl_addr + MB_RDDATA_OFFSET, bar, vf_active, pfn, vfn, rd_data64, error); + if (error) begin + $display("\nERROR: Mailbox read failed.\n"); + test_utils::incr_err_count(); + end + $display("INFO: Read MAILBOX ADDR:%x, READ_DATA32:%X", addr, rd_data64); + #5000 WRITE32(ADDR32, cmd_ctrl_addr, bar, vf_active, pfn, vfn, MB_NOOP); // no op Cmd + end +endtask + + +// Mailbox ack check +task read_ack_mailbox; + input logic [31:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [31:0] cmd_ctrl_addr; // Start address of mailbox access reg + logic [31:0] scratch1; + logic [4:0] rd_attempts; + logic ack_done; + logic error; + begin + scratch1 = 32'h0; + rd_attempts = 'b0; + ack_done = 1'h0; + + //$display("JB: vfa=%h, pfn = %h, vfn = %h", vf_active, pfn, vfn); + while (~ack_done && rd_attempts<15) begin + READ32(ADDR32, cmd_ctrl_addr, bar, vf_active, pfn, vfn, scratch1, error); + ack_done = scratch1[2]; + #100000 + rd_attempts=rd_attempts+1; + end + if (error || (~ack_done)) begin + $display("\nERROR: Mailbox Ack failed.\n"); + test_utils::incr_err_count(); + end + $display("Ack status: 0x%0x",ack_done); + end +endtask + +// Wait until all packets received back +task wait_for_all_eop_done; + input logic [31:0] num_pkt; + logic [31:0] pkt_cnt; + begin + pkt_cnt = 32'h0; + while (pkt_cnt < num_pkt) begin + @(posedge top_tb.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.GenBrdg[0].axis_to_avst_bridge_inst.avst_rx_st.rx.eop) + @(posedge top_tb.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.GenBrdg[0].axis_to_avst_bridge_inst.avst_rx_st.clk) + pkt_cnt=pkt_cnt+1; + $display("INFO: Packet received: %d", pkt_cnt); + end + $display("INFO:%t - RX EOP count is %d", $time, pkt_cnt); + end +endtask + +task automatic compare_eth_stats; + input logic [63:0] cur_pf_table; + input logic [31:0] addr1; + input logic [31:0] addr2; + output logic error; + output logic [63:0] framesOK_1; + output logic [63:0] framesOK_2; + // Statistic 1 + logic [63:0] framesOK_stat1; + logic [63:0] framesErr_stat1; + logic [63:0] framesCRCErr_stat1; + logic [63:0] octetsOK_stat1; + logic [63:0] pauseMACCtrlFrames_stat1; + logic [63:0] ifErrors_stat1; + logic [63:0] unicastFramesOK_stat1; + logic [63:0] unicastFramesErr_stat1; + logic [63:0] multicastFramesOK_stat1; + logic [63:0] multicastFramesErr_stat1; + logic [63:0] broadcastFramesOK_stat1; + logic [63:0] broadcastFramesErr_stat1; + logic [63:0] etherStatsOctets_stat1; + logic [63:0] etherStatsPkts_stat1; + logic [63:0] etherStatsUndersizePkts_stat1; + logic [63:0] etherStatsOversizePkts_stat1; + logic [63:0] etherStatsPkts64Octets_stat1; + logic [63:0] etherStatsPkts65to127Octets_stat1; + logic [63:0] etherStatsPkts128to255Octets_stat1; + logic [63:0] etherStatsPkts256to511Octet_stat1; + logic [63:0] etherStatsPkts512to1023Octets_stat1; + logic [63:0] etherStatsPkts1024to1518Octets_stat1; + logic [63:0] etherStatsPkts1519OtoXOctets_stat1; + logic [63:0] etherStatsFragments_stat1; + logic [63:0] etherStatsJabbers_stat1; + logic [63:0] etherStatsCRCErr_stat1; + logic [63:0] unicastMACCtrlFrames_stat1; + logic [63:0] multicastMACCtrlFrames_stat1; + logic [63:0] broadcastMACCtrlFrames_stat1; + // Statistic 2 + logic [63:0] framesOK_stat2; + logic [63:0] framesErr_stat2; + logic [63:0] framesCRCErr_stat2; + logic [63:0] octetsOK_stat2; + logic [63:0] pauseMACCtrlFrames_stat2; + logic [63:0] ifErrors_stat2; + logic [63:0] unicastFramesOK_stat2; + logic [63:0] unicastFramesErr_stat2; + logic [63:0] multicastFramesOK_stat2; + logic [63:0] multicastFramesErr_stat2; + logic [63:0] broadcastFramesOK_stat2; + logic [63:0] broadcastFramesErr_stat2; + logic [63:0] etherStatsOctets_stat2; + logic [63:0] etherStatsPkts_stat2; + logic [63:0] etherStatsUndersizePkts_stat2; + logic [63:0] etherStatsOversizePkts_stat2; + logic [63:0] etherStatsPkts64Octets_stat2; + logic [63:0] etherStatsPkts65to127Octets_stat2; + logic [63:0] etherStatsPkts128to255Octets_stat2; + logic [63:0] etherStatsPkts256to511Octet_stat2; + logic [63:0] etherStatsPkts512to1023Octets_stat2; + logic [63:0] etherStatsPkts1024to1518Octets_stat2; + logic [63:0] etherStatsPkts1519OtoXOctets_stat2; + logic [63:0] etherStatsFragments_stat2; + logic [63:0] etherStatsJabbers_stat2; + logic [63:0] etherStatsCRCErr_stat2; + logic [63:0] unicastMACCtrlFrames_stat2; + logic [63:0] multicastMACCtrlFrames_stat2; + logic [63:0] broadcastMACCtrlFrames_stat2; + + logic error_status = 0; + + // Read Statistic 1 + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_framesOK_OFFSET, framesOK_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_framesErr_OFFSET, framesErr_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_framesCRCErr_OFFSET, framesCRCErr_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_octetsOK_OFFSET, octetsOK_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_pauseMACCtrlFrames_OFFSET, pauseMACCtrlFrames_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_ifErrors_OFFSET, ifErrors_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_unicastFramesOK_OFFSET, unicastFramesOK_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_unicastFramesErr_OFFSET, unicastFramesErr_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_multicastFramesOK_OFFSET, multicastFramesOK_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_multicastFramesErr_OFFSET, multicastFramesErr_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_broadcastFramesOK_OFFSET, broadcastFramesOK_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_broadcastFramesErr_OFFSET, broadcastFramesErr_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsOctets_OFFSET, etherStatsOctets_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsPkts_OFFSET, etherStatsPkts_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsUndersizePkts_OFFSET, etherStatsUndersizePkts_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsOversizePkts_OFFSET, etherStatsOversizePkts_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsPkts64Octets_OFFSET, etherStatsPkts64Octets_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsPkts65to127Octets_OFFSET, etherStatsPkts65to127Octets_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsPkts128to255Octets_OFFSET, etherStatsPkts128to255Octets_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsPkts256to511Octets_OFFSET, etherStatsPkts256to511Octet_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsPkts512to1023Octets_OFFSET, etherStatsPkts512to1023Octets_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatPkts1024to1518Octets_OFFSET, etherStatsPkts1024to1518Octets_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsPkts1519toXOctets_OFFSET, etherStatsPkts1519OtoXOctets_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsFragments_OFFSET, etherStatsFragments_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsJabbers_OFFSET, etherStatsJabbers_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_etherStatsCRCErr_OFFSET, etherStatsCRCErr_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_unicastMACCtrlFrames_OFFSET, unicastMACCtrlFrames_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_multicastMACCtrlFrames_OFFSET, multicastMACCtrlFrames_stat1); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR, addr1 + STATISTICS_broadcastMACCtrlFrames_OFFSET, broadcastMACCtrlFrames_stat1); + + // Read Statistic 2 + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_framesOK_OFFSET, framesOK_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_framesErr_OFFSET, framesErr_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_framesCRCErr_OFFSET, framesCRCErr_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_octetsOK_OFFSET, octetsOK_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_pauseMACCtrlFrames_OFFSET, pauseMACCtrlFrames_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_ifErrors_OFFSET, ifErrors_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_unicastFramesOK_OFFSET, unicastFramesOK_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_unicastFramesErr_OFFSET, unicastFramesErr_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_multicastFramesOK_OFFSET, multicastFramesOK_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_multicastFramesErr_OFFSET, multicastFramesErr_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_broadcastFramesOK_OFFSET, broadcastFramesOK_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_broadcastFramesErr_OFFSET, broadcastFramesErr_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsOctets_OFFSET, etherStatsOctets_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsPkts_OFFSET, etherStatsPkts_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsUndersizePkts_OFFSET, etherStatsUndersizePkts_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsOversizePkts_OFFSET, etherStatsOversizePkts_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsPkts64Octets_OFFSET, etherStatsPkts64Octets_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsPkts65to127Octets_OFFSET, etherStatsPkts65to127Octets_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsPkts128to255Octets_OFFSET, etherStatsPkts128to255Octets_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsPkts256to511Octets_OFFSET, etherStatsPkts256to511Octet_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsPkts512to1023Octets_OFFSET, etherStatsPkts512to1023Octets_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatPkts1024to1518Octets_OFFSET, etherStatsPkts1024to1518Octets_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsPkts1519toXOctets_OFFSET, etherStatsPkts1519OtoXOctets_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsFragments_OFFSET, etherStatsFragments_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsJabbers_OFFSET, etherStatsJabbers_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_etherStatsCRCErr_OFFSET, etherStatsCRCErr_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_unicastMACCtrlFrames_OFFSET, unicastMACCtrlFrames_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_multicastMACCtrlFrames_OFFSET, multicastMACCtrlFrames_stat2); + read_mailbox(cur_pf_table, 0, 0, 0, 0, HSSI_BASE_ADDR + HSSI_RCFG_CMD_ADDR,addr2 + STATISTICS_broadcastMACCtrlFrames_OFFSET, broadcastMACCtrlFrames_stat2); + + // Display the collected statistics of the MAC + $display("\n-------------"); + $display("TX Statistics"); + $display("-------------"); + $display("\tframesOK = %0d", framesOK_stat1); + $display("\tframesErr = %0d", framesErr_stat1); + $display("\tframesCRCErr = %0d", framesCRCErr_stat1); + $display("\toctetsOK = %0d", octetsOK_stat1); + $display("\tpauseMACCtrlFrames = %0d", pauseMACCtrlFrames_stat1); + $display("\tifErrors = %0d", ifErrors_stat1); + $display("\tunicastFramesOK = %0d", unicastFramesOK_stat1); + $display("\tunicastFramesErr = %0d", unicastFramesErr_stat1); + $display("\tmulticastFramesOK = %0d", multicastFramesOK_stat1); + $display("\tmulticastFramesErr = %0d", multicastFramesErr_stat1); + $display("\tbroadcastFramesOK = %0d", broadcastFramesOK_stat1); + $display("\tbroadcastFramesErr = %0d", broadcastFramesErr_stat1); + $display("\tetherStatsOctets = %0d", etherStatsOctets_stat1); + $display("\tetherStatsPkts = %0d", etherStatsPkts_stat1); + $display("\tetherStatsUndersizePkts = %0d", etherStatsUndersizePkts_stat1); + $display("\tetherStatsOversizePkts = %0d", etherStatsOversizePkts_stat1); + $display("\tetherStatsPkts64Octets = %0d", etherStatsPkts64Octets_stat1); + $display("\tetherStatsPkts65to127Octets = %0d", etherStatsPkts65to127Octets_stat1); + $display("\tetherStatsPkts128to255Octets = %0d", etherStatsPkts128to255Octets_stat1); + $display("\tetherStatsPkts256to511Octet = %0d", etherStatsPkts256to511Octet_stat1); + $display("\tetherStatsPkts512to1023Octets = %0d", etherStatsPkts512to1023Octets_stat1); + $display("\tetherStatsPkts1024to1518Octets = %0d", etherStatsPkts1024to1518Octets_stat1); + $display("\tetherStatsPkts1519OtoXOctets = %0d", etherStatsPkts1519OtoXOctets_stat1); + $display("\tetherStatsFragments = %0d", etherStatsFragments_stat1); + $display("\tetherStatsJabbers = %0d", etherStatsJabbers_stat1); + $display("\tetherStatsCRCErr = %0d", etherStatsCRCErr_stat1); + $display("\tunicastMACCtrlFrames = %0d", unicastMACCtrlFrames_stat1); + $display("\tmulticastMACCtrlFrames = %0d", multicastMACCtrlFrames_stat1); + $display("\tbroadcastMACCtrlFrames = %0d", broadcastMACCtrlFrames_stat1); + + $display("\n-------------"); + $display("RX Statistics"); + $display("-------------"); + $display("\tframesOK = %0d", framesOK_stat2); + $display("\tframesErr = %0d", framesErr_stat2); + $display("\tframesCRCErr = %0d", framesCRCErr_stat2); + $display("\toctetsOK = %0d", octetsOK_stat2); + $display("\tpauseMACCtrlFrames = %0d", pauseMACCtrlFrames_stat2); + $display("\tifErrors = %0d", ifErrors_stat2); + $display("\tunicastFramesOK = %0d", unicastFramesOK_stat2); + $display("\tunicastFramesErr = %0d", unicastFramesErr_stat2); + $display("\tmulticastFramesOK = %0d", multicastFramesOK_stat2); + $display("\tmulticastFramesErr = %0d", multicastFramesErr_stat2); + $display("\tbroadcastFramesOK = %0d", broadcastFramesOK_stat2); + $display("\tbroadcastFramesErr = %0d", broadcastFramesErr_stat2); + $display("\tetherStatsOctets = %0d", etherStatsOctets_stat2); + $display("\tetherStatsPkts = %0d", etherStatsPkts_stat2); + $display("\tetherStatsUndersizePkts = %0d", etherStatsUndersizePkts_stat2); + $display("\tetherStatsOversizePkts = %0d", etherStatsOversizePkts_stat2); + $display("\tetherStatsPkts64Octets = %0d", etherStatsPkts64Octets_stat2); + $display("\tetherStatsPkts65to127Octets = %0d", etherStatsPkts65to127Octets_stat2); + $display("\tetherStatsPkts128to255Octets = %0d", etherStatsPkts128to255Octets_stat2); + $display("\tetherStatsPkts256to511Octet = %0d", etherStatsPkts256to511Octet_stat2); + $display("\tetherStatsPkts512to1023Octets = %0d", etherStatsPkts512to1023Octets_stat2); + $display("\tetherStatsPkts1024to1518Octets = %0d", etherStatsPkts1024to1518Octets_stat2); + $display("\tetherStatsPkts1519OtoXOctets = %0d", etherStatsPkts1519OtoXOctets_stat2); + $display("\tetherStatsFragments = %0d", etherStatsFragments_stat2); + $display("\tetherStatsJabbers = %0d", etherStatsJabbers_stat2); + $display("\tetherStatsCRCErr = %0d", etherStatsCRCErr_stat2); + $display("\tunicastMACCtrlFrames = %0d", unicastMACCtrlFrames_stat2); + $display("\tmulticastMACCtrlFrames = %0d", multicastMACCtrlFrames_stat2); + $display("\tbroadcastMACCtrlFrames = %0d", broadcastMACCtrlFrames_stat2); + + // Check for err statistic for stat1, must be 0 + if(framesErr_stat1 != 0 || framesCRCErr_stat1 != 0 || ifErrors_stat1 != 0 || unicastFramesErr_stat1 != 0 || + multicastFramesErr_stat1 != 0 || broadcastFramesErr_stat1 != 0 || etherStatsCRCErr_stat1 != 0) begin + error_status = 1; + end + + // Check for err statistic for stat2, must be 0 + if(framesErr_stat2 != 0 || framesCRCErr_stat2 != 0 || ifErrors_stat2 != 0 || unicastFramesErr_stat2 != 0 || + multicastFramesErr_stat2 != 0 || broadcastFramesErr_stat2 != 0 || etherStatsCRCErr_stat2 != 0) begin + error_status = 1; + end + + // Compare non-err statistic between stat1 & stat2, they must be equal + if(framesOK_stat1 != framesOK_stat2 || octetsOK_stat1 != octetsOK_stat2 || pauseMACCtrlFrames_stat1 != pauseMACCtrlFrames_stat2 || + unicastFramesOK_stat1 != unicastFramesOK_stat2 || multicastFramesOK_stat1 != multicastFramesOK_stat2 || broadcastFramesOK_stat1 != broadcastFramesOK_stat2 || + etherStatsOctets_stat1 != etherStatsOctets_stat2 || etherStatsPkts_stat1 != etherStatsPkts_stat2 || etherStatsUndersizePkts_stat1 != etherStatsUndersizePkts_stat2 || + etherStatsOversizePkts_stat1 != etherStatsOversizePkts_stat2 || etherStatsPkts64Octets_stat1 != etherStatsPkts64Octets_stat2 || + etherStatsPkts65to127Octets_stat1 != etherStatsPkts65to127Octets_stat2 || etherStatsPkts128to255Octets_stat1 != etherStatsPkts128to255Octets_stat2 || + etherStatsPkts256to511Octet_stat1 != etherStatsPkts256to511Octet_stat2 || etherStatsPkts512to1023Octets_stat1 != etherStatsPkts512to1023Octets_stat2 || + etherStatsPkts1024to1518Octets_stat1 != etherStatsPkts1024to1518Octets_stat2 || etherStatsPkts1519OtoXOctets_stat1 != etherStatsPkts1519OtoXOctets_stat2 || + etherStatsFragments_stat1 != etherStatsFragments_stat2 || etherStatsJabbers_stat1 != etherStatsJabbers_stat2 || + unicastMACCtrlFrames_stat1 != unicastMACCtrlFrames_stat2 || multicastMACCtrlFrames_stat1 != multicastMACCtrlFrames_stat2 || + broadcastMACCtrlFrames_stat1 != broadcastMACCtrlFrames_stat2) begin + error_status = 1; + end + + framesOK_1 = framesOK_stat1; + framesOK_2 = framesOK_stat2; + error = error_status; + +endtask : compare_eth_stats + +task test_traffic; + input access32; + logic [63:0] cur_pf_table; + logic [63:0] framesOK_1,framesOK_2; + static logic tx_rx_mismatch = 0; + static logic RD_MAC_STATS_EN = 1; + logic [63:0] scratch1,scratch2; + logic [31:0] scratch32; + + begin + $display("Entering sequence!"); + #36000ns // Wait for HSSI initialization in MAC and PHY + + //Set packet length + write_mailbox(0, 1, 0, 2, HE_HSSI_BASE_ADDR+TRAFFIC_CTRL_CMD_ADDR, TG_PKT_LEN_ADDR, TG_PKT_LEN_VAL); + //Set Random payload + write_mailbox(0, 1, 0, 2, HE_HSSI_BASE_ADDR+TRAFFIC_CTRL_CMD_ADDR, TG_DATA_PATTERN_ADDR, TG_DATA_PATTERN_VAL); + //Set number of packets + write_mailbox(0, 1, 0, 2, HE_HSSI_BASE_ADDR+TRAFFIC_CTRL_CMD_ADDR, TG_NUM_PKT_ADDR, TG_NUM_PKT_VAL); // num of packets + //Set start to send packets + write_mailbox(0, 1, 0, 2, HE_HSSI_BASE_ADDR+TRAFFIC_CTRL_CMD_ADDR, TG_START_XFR_ADDR, 32'h1); + + //wait_for_all_eop_done(TG_START_XFR_ADDR); + #5000ns // To allow enough time to receive all the packets on rx. + + // Good packet received at Traffic monitor + read_mailbox(cur_pf_table, 0, 1, 0, 2, HE_HSSI_BASE_ADDR + TRAFFIC_CTRL_CMD_ADDR, TM_PKT_GOOD_ADDR, scratch1); + scratch32 = scratch1[31:0]; + if (scratch32 != TG_NUM_PKT_VAL) begin + $display("\nError: Received good packets does not match Transmitted packets!\n"); + $display("Number of Good Packets Received: \tExpected: %0d\n \tRead:%0d", TG_NUM_PKT_VAL, scratch32); + test_utils::incr_err_count(); + end else begin + $display("INFO: Number of Good Packets Received:%0d", scratch32); + end + + // Bad packet received at Traffic monitor + read_mailbox(cur_pf_table, 0, 1, 0, 2, HE_HSSI_BASE_ADDR + TRAFFIC_CTRL_CMD_ADDR, TM_PKT_BAD_ADDR, scratch1); + scratch32 = scratch1[31:0]; + if (scratch32 != 32'h0) begin + $display("\nError: Received bad packets > 0!\n"); + $display("Number of Bad Packets Received: \tExpected: %0d\n \tRead: %0d",32'h0,scratch32); + test_utils::incr_err_count(); + end else begin + $display("INFO: Number of Bad Packets Received:%0d", scratch32); + end + + // Check MAC Stats + if(RD_MAC_STATS_EN) begin + compare_eth_stats(cur_pf_table, HSSI_BASE_ADDR + TX_STATISTICS_ADDR, HSSI_BASE_ADDR + RX_STATISTICS_ADDR, tx_rx_mismatch, framesOK_1, framesOK_2); + if(tx_rx_mismatch) begin + $display("\nERROR: RX MAC statistic does not match TX MAC statistic."); + test_utils::incr_err_count(); + end + else begin + if(framesOK_1 != 32 || framesOK_2 != 32) begin + $display("\nERROR: framesOK size in MAC statistic does not match FRAMESOK_SIZE defined in testcase."); + test_utils::incr_err_count(); + end + end + end + + $display("Exiting sequence!"); + end +endtask + + +// HSSI Traffic test +task traffic_test; + input logic access32; + logic [31:0] old_test_err_count; + begin + print_test_header("traffic_test"); + old_test_err_count = test_utils::get_err_count(); + + // Wait for ready before starting the test + assert_afu_reset(PORT_CONTROL); + deassert_afu_reset(PORT_CONTROL); + + test_traffic(access32); + + post_test_util(old_test_err_count); + end +endtask + +//------------------- +// Test main entry +//------------------- +task main_test; + output logic test_result; + logic valid_csr_region; +begin + traffic_test (1); // Pass 1 for 32-bit access to mailbox, 0 for 64-bit +end +endtask diff --git a/sim/unit_test/he_hssi_lpbk_test/vcs_setup.sh b/sim/unit_test/he_hssi_lpbk_test/vcs_setup.sh new file mode 100644 index 0000000..6d94fe8 --- /dev/null +++ b/sim/unit_test/he_hssi_lpbk_test/vcs_setup.sh @@ -0,0 +1,111 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcs" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +# source ${SIM_ROOTDIR}/d5005/unit_test/scripts/vcs_filelist.sh +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +${TEST_BASE_DIR}/testbench/test_param_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vcs -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + +define+R1_UNIT_TEST_ENV \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $VCS_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -top $TOP_LEVEL_NAME +error+20 -l vcs.log + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/he_hssi_lpbk_test/vcsmx_setup.sh b/sim/unit_test/he_hssi_lpbk_test/vcsmx_setup.sh new file mode 100755 index 0000000..fa4488e --- /dev/null +++ b/sim/unit_test/he_hssi_lpbk_test/vcsmx_setup.sh @@ -0,0 +1,116 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcsmx" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +# source ${SIM_ROOTDIR}/d5005/unit_test/scripts/vcs_filelist.sh +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +${TEST_BASE_DIR}/testbench/test_param_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlogan -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + +define+R1_UNIT_TEST_ENV \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $INC_DIR \ + $RTL_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC +error+1 -l vlog.log + +vcs -full64 -ntb_opts -licqueue +vcs+lic+wait \ + +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -l vcs.log $TOP_LEVEL_NAME + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/he_lb_lpbk_test/msim_setup.sh b/sim/unit_test/he_lb_lpbk_test/msim_setup.sh new file mode 100755 index 0000000..b617b8a --- /dev/null +++ b/sim/unit_test/he_lb_lpbk_test/msim_setup.sh @@ -0,0 +1,113 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="-finish exit" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR="$TEST_SRC_DIR/../../.." +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="${TEST_DIR}/sim_msim" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for msim # +################################### +. ${SIM_DIR}/msim_filelist.sh + +################################## +### BFM related verilog source ### +################################## +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlib work +vlog -mfcu -timescale=1ns/1fs +libext+.v+.sv -lint -sv \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+HTILE \ + +define+R1_UNIT_TEST_ENV \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+MSIM_IOFS_D5005 \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $MSIM_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -work work -l msim_vlog.log -suppress 8386,7033,7061,2388,12003,2892 +#suppress 8386 : Replication operator in Conactenation Operator +#suppress 2892 : Net type of 'clk' was not explicitly declared +#suppress 7061 : Variable 'clear_tdo_bit_select' driven in an always_ff block, may not be driven by any other process +#suppress 7033 : Variable 'parser_result' driven in a combinational block, may not be driven by any other process + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + vopt $TOP_LEVEL_NAME -o opt -suppress 2732,12003,7033,3837 -l msim_vopt.log + vsim -c opt -nosva -suppress 2732,12003,7033,3837 -do "add log -r /*; run -all ; quit -f" +fi + + diff --git a/sim/unit_test/he_lb_lpbk_test/readme.txt b/sim/unit_test/he_lb_lpbk_test/readme.txt new file mode 100644 index 0000000..aca4e85 --- /dev/null +++ b/sim/unit_test/he_lb_lpbk_test/readme.txt @@ -0,0 +1,69 @@ +***Test Description*** +This is the unit test for HE_LPBK. The test uses HE-LB to perform memory loopback between FIM and the host. + +Description of test modules: + * test_csr_defs.sv - Defines HE-LB CSR addresses. + * tester_tests.sv - Defines all the test cases for current test. + * script/Makefile_VCS.mk - Script to run the test in VCS only + * script/Makefile.mk - Script to run the test in VCS & Questasim. MSIM_D5005=1 option to be given for Questasim else will be for VCS. + +***Running the test*** +To run the test in VCS: + 1) Make sure the shell environment is set up to run VCS/VCSMX. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Synopsys VCS simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_vcs + dve -full64 -vpd vcdplus.vpd & + +To run the test in QuestaSim: + 1) Make sure the shell environment is set up to run Questasim. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Mentor Graphics QuestaSim simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh MSIM=1 + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_msim + vsim -view vsim.wlf & diff --git a/sim/unit_test/he_lb_lpbk_test/scripts/run_sim.sh b/sim/unit_test/he_lb_lpbk_test/scripts/run_sim.sh new file mode 100755 index 0000000..271afc5 --- /dev/null +++ b/sim/unit_test/he_lb_lpbk_test/scripts/run_sim.sh @@ -0,0 +1,48 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)/.." + + +VCSMX=0 +MSIM=0 +SKIP_IP_CMP=0 +TEST_DIR=$(pwd) + +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh run_sim.sh SKIP_IP_CMP=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +# Source common sim setup script + +. ${TEST_DIR}/../../scripts/sim_setup_common.sh TEST_DIR="$TEST_DIR" VCSMX=$VCSMX MSIM=$MSIM + +# Run simulation +if [ $VCSMX -eq 1 ]; then + echo "Running VCSMX simulation in $TEST_DIR/sim_vcsmx" + cd ${TEST_DIR}/sim_vcsmx && sh ${TEST_SRC_DIR}/vcsmx_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +elif [ $MSIM -eq 1 ]; then + echo "Running Questasim simulation in $TEST_DIR/sim_msim" + cd ${TEST_DIR}/sim_msim && sh ${TEST_SRC_DIR}/msim_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="-l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="" +else + echo "Running VCS simulation in $TEST_DIR/sim_vcs" + cd ${TEST_DIR}/sim_vcs && sh ${TEST_SRC_DIR}/vcs_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +fi + + diff --git a/sim/unit_test/he_lb_lpbk_test/scripts/test_list.f b/sim/unit_test/he_lb_lpbk_test/scripts/test_list.f new file mode 100644 index 0000000..28ba9dc --- /dev/null +++ b/sim/unit_test/he_lb_lpbk_test/scripts/test_list.f @@ -0,0 +1 @@ +$WORKDIR/sim/unit_test/he_lb_lpbk_test/testbench/test_csr_defs.sv diff --git a/sim/unit_test/he_lb_lpbk_test/testbench/test_csr_defs.sv b/sim/unit_test/he_lb_lpbk_test/testbench/test_csr_defs.sv new file mode 100644 index 0000000..fa494b4 --- /dev/null +++ b/sim/unit_test/he_lb_lpbk_test/testbench/test_csr_defs.sv @@ -0,0 +1,37 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// CSR addresses are defined for the testcase. +// +//----------------------------------------------------------------------------- +`ifndef __TEST_CSR_DEFS__ +`define __TEST_CSR_DEFS__ + +package test_csr_defs; + localparam DFH = 32'h0; + localparam ID_L = 32'h8; + localparam ID_H = 32'h10; + localparam SCRATCHPAD0 = 32'h100; + localparam SCRATCHPAD1 = 32'h104; + localparam SCRATCHPAD2 = 32'h108; + localparam DSM_BASEL = 32'h110; + localparam DSM_BASEH = 32'h114; + localparam SRC_ADDR = 32'h120; + localparam DST_ADDR = 32'h128; + localparam NUM_LINES = 32'h130; + localparam CTL = 32'h138; + localparam CFG = 32'h140; + localparam INACT_THRESH = 32'h148; + localparam INTERRUPT0 = 32'h150; + localparam SWTEST_MSG = 32'h158; + localparam STATUS0 = 32'h160; + localparam STATUS1 = 32'h168; + localparam ERROR = 32'h170; + localparam STRIDE = 32'h178; + +endpackage + +`endif diff --git a/sim/unit_test/he_lb_lpbk_test/testbench/tester_tests.sv b/sim/unit_test/he_lb_lpbk_test/testbench/tester_tests.sv new file mode 100755 index 0000000..5b96b78 --- /dev/null +++ b/sim/unit_test/he_lb_lpbk_test/testbench/tester_tests.sv @@ -0,0 +1,577 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// This file defines all the test cases for current test. +// +// main_test() is the main entry function which the tester calls +// to execute the unit tests. +// +//----------------------------------------------------------------------------- + +import test_csr_defs::*; + +//------------------- +// Test utilities +//------------------- +task incr_test_id; +begin + test_id = test_id + 1; +end +endtask + +task post_test_util; + input logic [31:0] old_test_err_count; + logic result; +begin + if (test_utils::get_err_count() > old_test_err_count) begin + result = 1'b0; + end else begin + result = 1'b1; + end + + repeat (10) + @(posedge avl_clk); + + @(posedge avl_clk); + reset_test = 1'b1; + repeat (5) + @(posedge avl_clk); + reset_test = 1'b0; + + f_reset_tag(); + + if (result) begin + $display("\nTest status: OK"); + test_summary[test_id].result = 1'b1; + end else begin + $display("\nTest status: FAILED"); + test_summary[test_id].result = 1'b0; + end + incr_test_id(); +end +endtask + +task print_test_header; + input [1024*8-1:0] test_name; +begin + $display("\n********************************************"); + $display(" Running TEST(%0d) : %0s", test_id, test_name); + $display("********************************************"); + test_summary[test_id].name = test_name; +end +endtask + +task verify_pcie_err_count; + output logic result; + input logic [7:0] exp_err; +begin + // Wait 30 clock cycles for checker error to be logged + repeat (30) + @(posedge fim_clk); + + if (checker_err_count != exp_err) + begin + result = 1'b0; + $display("Failed - expected errors: %0d, actual errors: %0d", exp_err, checker_err_count); + end else begin + result = 1'b1; + $display("Checker error count matches: %0d", checker_err_count); + end + if (~result) + test_utils::incr_err_count(); +end +endtask + +task verify_pcie_err_code; + output logic result; + input logic [31:0] exp_err_code; +begin + // Wait 10 clock cycles for checker error to be logged + repeat (10) + @(posedge fim_clk); + + if (pcie_p2c_chk_err_code != exp_err_code) + begin + result = 1'b0; + $display("Failed - error code mismatch, expected: 0x%x, actual: 0x%x", exp_err_code, pcie_p2c_chk_err_code); + end else begin + result = 1'b1; + $display("Checker error code matches: 0x%x", pcie_p2c_chk_err_code); + end + if (~result) + test_utils::incr_err_count(); +end +endtask + +//------------------- +// Test cases +//------------------- +// Test 32-bit CSR access +task test_csr_access_32; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [31:0] data; + logic [31:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE32(addr_mode, addr, bar, vf_active, pfn, vfn, data); + READ32(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR write and read mismatch! write=0x%x read=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 32-bit CSR access to unused CSR region +task test_unused_csr_access_32; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [31:0] data; + logic [31:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE32(addr_mode, addr, bar, vf_active, pfn, vfn, data); + READ32(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== 32'h0) begin + $display("\nERROR: Expected 32'h0 to be returned for unused CSR region, actual:0x%x\n",scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 64-bit CSR access +task test_csr_access_64; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [63:0] data; + logic [63:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE64(addr_mode, addr, bar, vf_active, pfn, vfn, data); + READ64(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR write and read mismatch! write=0x%x read=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 64-bit CSR read access +task test_csr_read_64; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [63:0] data; + logic [63:0] scratch; + logic error; +begin + result = 1'b1; + READ64(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR read mismatch! expected=0x%x actual=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 32-bit CSR read access +task test_csr_read_32; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [31:0] data; + logic [31:0] scratch; + logic error; +begin + result = 1'b1; + READ32(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR read mismatch! expected=0x%x actual=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 64-bit CSR access to unused CSR region +task test_unused_csr_access_64; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [63:0] data; + logic [63:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE64(addr_mode, addr, bar, vf_active, pfn, vfn, data); + READ64(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== 64'h0) begin + $display("\nERROR: Expected 64'h0 to be returned for unused CSR region, actual:0x%x\n",scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test MMIO access with 32-bit address +task test_mmio_addr32; + output logic result; +begin + print_test_header("test_mmio_addr32"); + test_mmio(result, ADDR32); +end +endtask + +// Test MMIO access with 64-bit address +task test_mmio_addr64; + output logic result; +begin + print_test_header("test_mmio_addr64"); + test_mmio(result, ADDR64); +end +endtask + +// Test memory write 32-bit address +task test_mmio; + output logic result; + input e_addr_mode addr_mode; + logic [63:0] base_addr; + logic [63:0] addr; + logic [63:0] scratch; + logic error; + logic [31:0] old_test_err_count; +begin + + old_test_err_count = test_utils::get_err_count(); + result = 1'b1; + + $display("\n---------------------"); + $display("Test CSR access to HE-LB (PF2)"); + $display("---------------------\n"); + test_csr_access_64(result, addr_mode, SCRATCHPAD0, 0, 1'b0, 3'h2, 0, 'h1111_2222_3333_4444); + test_csr_access_32(result, addr_mode, SCRATCHPAD0, 0, 1'b0, 3'h2, 0, 'haa04_04aa); + + test_unused_csr_access_32(result, addr_mode, 32'hff0, 0, 1'b0, 0, 0, 'hF00D_0001); + test_unused_csr_access_64(result, addr_mode, 32'hff0, 0, 1'b0, 0, 0, 'hF00D_0001_6464_6464); + + + post_test_util(old_test_err_count); +end +endtask + +// Memory loopback test util +task test_mem_loopback_util; + output logic result; + input logic mem_display_on; + input logic [2:0] bar; + input logic [2:0] pfn; + input logic [11:0] vfn; + input logic vf_active; + input logic [2:0] test_mode; + input logic [3:0][511:0] test_data; + input logic [63:0] src_base_addr; + input logic [63:0] dst_base_addr; + input logic [63:0] dsm_base_addr; + input logic [1:0] cl_mode; + input logic [16:0] num_cl; + + logic [31:0] src_addr; + logic [31:0] dst_addr; + logic [31:0] wdata; + logic [63:0] scratch; + logic err_src_addr; + logic err_dst_addr; +begin + result = 1'b1; + + err_src_addr = |src_base_addr[5:0]; + err_dst_addr = |dst_base_addr[5:0]; + + if (err_src_addr) begin + $display("Error: Source buffer address (0x%0x) is not aligned to cacheline boundary (64 bytes).", src_base_addr); + end + + if (err_dst_addr) begin + $display("Error: Destination buffer address (0x%0x) is not aligned to cacheline boundary (64 bytes).", dst_base_addr); + end + + result = ~(err_src_addr | err_dst_addr); + + if (~result) begin + test_utils::incr_err_count(); + end else begin + $display("\n (1) Writing test data to source buffer starting at 0x%x", src_base_addr); + for (int cl=0; cl/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcs" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +# source ${SIM_ROOTDIR}/d5005/unit_test/scripts/vcs_filelist.sh +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vcs -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $VCS_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -top $TOP_LEVEL_NAME +error+20 -l vcs.log + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/he_lb_lpbk_test/vcsmx_setup.sh b/sim/unit_test/he_lb_lpbk_test/vcsmx_setup.sh new file mode 100755 index 0000000..383db68 --- /dev/null +++ b/sim/unit_test/he_lb_lpbk_test/vcsmx_setup.sh @@ -0,0 +1,114 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcsmx" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +# source ${SIM_ROOTDIR}/d5005/unit_test/scripts/vcs_filelist.sh +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlogan -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $INC_DIR \ + $RTL_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC +error+1 -l vlog.log + +vcs -full64 -ntb_opts -licqueue +vcs+lic+wait \ + +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -l vcs.log $TOP_LEVEL_NAME + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/he_mem_lpbk_test/msim_setup.sh b/sim/unit_test/he_mem_lpbk_test/msim_setup.sh new file mode 100755 index 0000000..b617b8a --- /dev/null +++ b/sim/unit_test/he_mem_lpbk_test/msim_setup.sh @@ -0,0 +1,113 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="-finish exit" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR="$TEST_SRC_DIR/../../.." +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="${TEST_DIR}/sim_msim" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for msim # +################################### +. ${SIM_DIR}/msim_filelist.sh + +################################## +### BFM related verilog source ### +################################## +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlib work +vlog -mfcu -timescale=1ns/1fs +libext+.v+.sv -lint -sv \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+HTILE \ + +define+R1_UNIT_TEST_ENV \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+MSIM_IOFS_D5005 \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $MSIM_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -work work -l msim_vlog.log -suppress 8386,7033,7061,2388,12003,2892 +#suppress 8386 : Replication operator in Conactenation Operator +#suppress 2892 : Net type of 'clk' was not explicitly declared +#suppress 7061 : Variable 'clear_tdo_bit_select' driven in an always_ff block, may not be driven by any other process +#suppress 7033 : Variable 'parser_result' driven in a combinational block, may not be driven by any other process + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + vopt $TOP_LEVEL_NAME -o opt -suppress 2732,12003,7033,3837 -l msim_vopt.log + vsim -c opt -nosva -suppress 2732,12003,7033,3837 -do "add log -r /*; run -all ; quit -f" +fi + + diff --git a/sim/unit_test/he_mem_lpbk_test/readme.txt b/sim/unit_test/he_mem_lpbk_test/readme.txt new file mode 100644 index 0000000..066b895 --- /dev/null +++ b/sim/unit_test/he_mem_lpbk_test/readme.txt @@ -0,0 +1,69 @@ +***Test Description*** +This is the unit test for HE_LPBK. The test uses HE-MEM to perform memory loopback between FIM and the host. + +Description of test modules: + * test_csr_defs.sv - Defines HE-MEM CSR addresses. + * tester_tests.sv - Defines all the test cases for current test. + * script/Makefile_VCS.mk - Script to run the test in VCS only + * script/Makefile.mk - Script to run the test in VCS & Questasim. MSIM_D5005=1 option to be given for Questasim else will be for VCS. + +***Running the test*** +To run the test in VCS: + 1) Make sure the shell environment is set up to run VCS/VCSMX. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Synopsys VCS simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_vcs + dve -full64 -vpd vcdplus.vpd & + +To run the test in QuestaSim: + 1) Make sure the shell environment is set up to run Questasim. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Mentor Graphics QuestaSim simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh MSIM=1 + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_msim + vsim -view vsim.wlf & diff --git a/sim/unit_test/he_mem_lpbk_test/scripts/run_sim.sh b/sim/unit_test/he_mem_lpbk_test/scripts/run_sim.sh new file mode 100755 index 0000000..271afc5 --- /dev/null +++ b/sim/unit_test/he_mem_lpbk_test/scripts/run_sim.sh @@ -0,0 +1,48 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)/.." + + +VCSMX=0 +MSIM=0 +SKIP_IP_CMP=0 +TEST_DIR=$(pwd) + +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh run_sim.sh SKIP_IP_CMP=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +# Source common sim setup script + +. ${TEST_DIR}/../../scripts/sim_setup_common.sh TEST_DIR="$TEST_DIR" VCSMX=$VCSMX MSIM=$MSIM + +# Run simulation +if [ $VCSMX -eq 1 ]; then + echo "Running VCSMX simulation in $TEST_DIR/sim_vcsmx" + cd ${TEST_DIR}/sim_vcsmx && sh ${TEST_SRC_DIR}/vcsmx_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +elif [ $MSIM -eq 1 ]; then + echo "Running Questasim simulation in $TEST_DIR/sim_msim" + cd ${TEST_DIR}/sim_msim && sh ${TEST_SRC_DIR}/msim_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="-l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="" +else + echo "Running VCS simulation in $TEST_DIR/sim_vcs" + cd ${TEST_DIR}/sim_vcs && sh ${TEST_SRC_DIR}/vcs_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +fi + + diff --git a/sim/unit_test/he_mem_lpbk_test/scripts/test_list.f b/sim/unit_test/he_mem_lpbk_test/scripts/test_list.f new file mode 100644 index 0000000..0204ed8 --- /dev/null +++ b/sim/unit_test/he_mem_lpbk_test/scripts/test_list.f @@ -0,0 +1 @@ +$WORKDIR/sim/unit_test/he_mem_lpbk_test/testbench/test_csr_defs.sv diff --git a/sim/unit_test/he_mem_lpbk_test/testbench/test_csr_defs.sv b/sim/unit_test/he_mem_lpbk_test/testbench/test_csr_defs.sv new file mode 100644 index 0000000..a3797fa --- /dev/null +++ b/sim/unit_test/he_mem_lpbk_test/testbench/test_csr_defs.sv @@ -0,0 +1,39 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// CSR addresses are defined for the testcase. +// +//----------------------------------------------------------------------------- +`ifndef __TEST_CSR_DEFS__ +`define __TEST_CSR_DEFS__ + +package test_csr_defs; + localparam DFH = 32'h0; + localparam ID_L = 32'h8; + localparam ID_H = 32'h10; + localparam SCRATCHPAD0 = 32'h100; + localparam SCRATCHPAD1 = 32'h104; + localparam SCRATCHPAD2 = 32'h108; + localparam DSM_BASEL = 32'h110; + localparam DSM_BASEH = 32'h114; + localparam SRC_ADDR = 32'h120; + localparam DST_ADDR = 32'h128; + localparam NUM_LINES = 32'h130; + localparam CTL = 32'h138; + localparam CFG = 32'h140; + localparam INACT_THRESH = 32'h148; + localparam INTERRUPT0 = 32'h150; + localparam SWTEST_MSG = 32'h158; + localparam STATUS0 = 32'h160; + localparam STATUS1 = 32'h168; + localparam ERROR = 32'h170; + localparam STRIDE = 32'h178; + + localparam PORT_CONTROL = 32'h91038; + +endpackage + +`endif diff --git a/sim/unit_test/he_mem_lpbk_test/testbench/tester_tests.sv b/sim/unit_test/he_mem_lpbk_test/testbench/tester_tests.sv new file mode 100755 index 0000000..13909cd --- /dev/null +++ b/sim/unit_test/he_mem_lpbk_test/testbench/tester_tests.sv @@ -0,0 +1,574 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// This file defines all the test cases for current test. +// +// main_test() is the main entry function which the tester calls +// to execute the unit tests. +// +//----------------------------------------------------------------------------- + +import test_csr_defs::*; + +//------------------- +// Test utilities +//------------------- +task incr_test_id; +begin + test_id = test_id + 1; +end +endtask + +task post_test_util; + input logic [31:0] old_test_err_count; + logic result; +begin + if (test_utils::get_err_count() > old_test_err_count) begin + result = 1'b0; + end else begin + result = 1'b1; + end + + repeat (10) + @(posedge avl_clk); + + @(posedge avl_clk); + reset_test = 1'b1; + repeat (5) + @(posedge avl_clk); + reset_test = 1'b0; + + f_reset_tag(); + + if (result) begin + $display("\nTest status: OK"); + test_summary[test_id].result = 1'b1; + end else begin + $display("\nTest status: FAILED"); + test_summary[test_id].result = 1'b0; + end + incr_test_id(); +end +endtask + +task print_test_header; + input [1024*8-1:0] test_name; +begin + $display("\n********************************************"); + $display(" Running TEST(%0d) : %0s", test_id, test_name); + $display("********************************************"); + test_summary[test_id].name = test_name; +end +endtask + +task verify_pcie_err_count; + output logic result; + input logic [7:0] exp_err; +begin + // Wait 30 clock cycles for checker error to be logged + repeat (30) + @(posedge fim_clk); + + if (checker_err_count != exp_err) + begin + result = 1'b0; + $display("Failed - expected errors: %0d, actual errors: %0d", exp_err, checker_err_count); + end else begin + result = 1'b1; + $display("Checker error count matches: %0d", checker_err_count); + end + if (~result) + test_utils::incr_err_count(); +end +endtask + +task verify_pcie_err_code; + output logic result; + input logic [31:0] exp_err_code; +begin + // Wait 10 clock cycles for checker error to be logged + repeat (10) + @(posedge fim_clk); + + if (pcie_p2c_chk_err_code != exp_err_code) + begin + result = 1'b0; + $display("Failed - error code mismatch, expected: 0x%x, actual: 0x%x", exp_err_code, pcie_p2c_chk_err_code); + end else begin + result = 1'b1; + $display("Checker error code matches: 0x%x", pcie_p2c_chk_err_code); + end + if (~result) + test_utils::incr_err_count(); +end +endtask + +//------------------- +// Test cases +//------------------- +// Test 32-bit CSR access +task test_csr_access_32; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [31:0] data; + logic [31:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE32(addr_mode, addr, bar, vf_active, pfn, vfn, data); + READ32(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR write and read mismatch! write=0x%x read=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 32-bit CSR access to unused CSR region +task test_unused_csr_access_32; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [31:0] data; + logic [31:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE32(addr_mode, addr, bar, vf_active, pfn, vfn, data); + READ32(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== 32'h0) begin + $display("\nERROR: Expected 32'h0 to be returned for unused CSR region, actual:0x%x\n",scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 64-bit CSR access +task test_csr_access_64; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [63:0] data; + logic [63:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE64(addr_mode, addr, bar, vf_active, pfn, vfn, data); + READ64(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR write and read mismatch! write=0x%x read=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 64-bit CSR read access +task test_csr_read_64; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [63:0] data; + logic [63:0] scratch; + logic error; +begin + result = 1'b1; + READ64(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR read mismatch! expected=0x%x actual=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 32-bit CSR read access +task test_csr_read_32; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [31:0] data; + logic [31:0] scratch; + logic error; +begin + result = 1'b1; + READ32(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR read mismatch! expected=0x%x actual=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 64-bit CSR access to unused CSR region +task test_unused_csr_access_64; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [63:0] data; + logic [63:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE64(addr_mode, addr, bar, vf_active, pfn, vfn, data); + READ64(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== 64'h0) begin + $display("\nERROR: Expected 64'h0 to be returned for unused CSR region, actual:0x%x\n",scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test MMIO access with 32-bit address +task test_mmio_addr32; + output logic result; +begin + print_test_header("test_mmio_addr32"); + test_mmio(result, ADDR32); +end +endtask + +// Test MMIO access with 64-bit address +task test_mmio_addr64; + output logic result; +begin + print_test_header("test_mmio_addr64"); + test_mmio(result, ADDR64); +end +endtask + +// Test memory write 32-bit address +task test_mmio; + output logic result; + input e_addr_mode addr_mode; + logic [63:0] base_addr; + logic [63:0] addr; + logic [63:0] scratch; + logic error; + logic [31:0] old_test_err_count; +begin + + old_test_err_count = test_utils::get_err_count(); + result = 1'b1; + + $display("\n---------------------"); + $display("Test CSR access to HE-LB (PF2)"); + $display("---------------------\n"); + test_csr_access_64(result, addr_mode, SCRATCHPAD0, 0, 1'b0, 3'h2, 0, 'h1111_2222_3333_4444); + test_csr_access_32(result, addr_mode, SCRATCHPAD0, 0, 1'b0, 3'h2, 0, 'haa04_04aa); + + test_unused_csr_access_32(result, addr_mode, 32'hff0, 0, 1'b0, 0, 0, 'hF00D_0001); + test_unused_csr_access_64(result, addr_mode, 32'hff0, 0, 1'b0, 0, 0, 'hF00D_0001_6464_6464); + + + post_test_util(old_test_err_count); +end +endtask + +// Memory loopback test util +task test_mem_loopback_util; + output logic result; + input logic mem_display_on; + input logic [2:0] bar; + input logic [2:0] pfn; + input logic [11:0] vfn; + input logic vf_active; + input logic [2:0] test_mode; + input logic [3:0][511:0] test_data; + input logic [63:0] src_base_addr; + input logic [63:0] dst_base_addr; + input logic [63:0] dsm_base_addr; + input logic [1:0] cl_mode; + input logic [16:0] num_cl; + + logic [31:0] src_addr; + logic [31:0] dst_addr; + logic [31:0] wdata; + logic [63:0] scratch; + logic err_src_addr; + logic err_dst_addr; +begin + result = 1'b1; + + err_src_addr = |src_base_addr[5:0]; + err_dst_addr = |dst_base_addr[5:0]; + + if (err_src_addr) begin + $display("Error: Source buffer address (0x%0x) is not aligned to cacheline boundary (64 bytes).", src_base_addr); + end + + if (err_dst_addr) begin + $display("Error: Destination buffer address (0x%0x) is not aligned to cacheline boundary (64 bytes).", dst_base_addr); + end + + result = ~(err_src_addr | err_dst_addr); + + if (~result) begin + test_utils::incr_err_count(); + end else begin + $display("\n (1) Writing test data to source buffer starting at 0x%x", src_base_addr); + for (int cl=0; cl/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcs" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +# source ${SIM_ROOTDIR}/d5005/unit_test/scripts/vcs_filelist.sh +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vcs -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $VCS_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -top $TOP_LEVEL_NAME +error+20 -l vcs.log + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/he_mem_lpbk_test/vcsmx_setup.sh b/sim/unit_test/he_mem_lpbk_test/vcsmx_setup.sh new file mode 100755 index 0000000..383db68 --- /dev/null +++ b/sim/unit_test/he_mem_lpbk_test/vcsmx_setup.sh @@ -0,0 +1,114 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcsmx" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +# source ${SIM_ROOTDIR}/d5005/unit_test/scripts/vcs_filelist.sh +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlogan -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $INC_DIR \ + $RTL_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC +error+1 -l vlog.log + +vcs -full64 -ntb_opts -licqueue +vcs+lic+wait \ + +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -l vcs.log $TOP_LEVEL_NAME + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/mmio_test/msim_setup.sh b/sim/unit_test/mmio_test/msim_setup.sh new file mode 100755 index 0000000..aae7eeb --- /dev/null +++ b/sim/unit_test/mmio_test/msim_setup.sh @@ -0,0 +1,114 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="-finish exit" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR="$TEST_SRC_DIR/../../.." +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="${TEST_DIR}/sim_msim" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for msim # +################################### +. ${SIM_DIR}/msim_filelist.sh + +################################## +### BFM related verilog source ### +################################## +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlib work +vlog -mfcu -timescale=1ns/1fs +libext+.v+.sv -lint -sv \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+HTILE \ + +define+R1_UNIT_TEST_ENV \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+MSIM_IOFS_D5005 \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + +define+R1_UNIT_TEST_ENV \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $MSIM_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -work work -l msim_vlog.log -suppress 8386,7033,7061,2388,12003,2892 +#suppress 8386 : Replication operator in Conactenation Operator +#suppress 2892 : Net type of 'clk' was not explicitly declared +#suppress 7061 : Variable 'clear_tdo_bit_select' driven in an always_ff block, may not be driven by any other process +#suppress 7033 : Variable 'parser_result' driven in a combinational block, may not be driven by any other process + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + vopt $TOP_LEVEL_NAME -o opt -suppress 2732,12003,7033,3837 -l msim_vopt.log + vsim -c opt -nosva -suppress 2732,12003,7033,3837 -do "add log -r /*; run -all ; quit -f" +fi + + diff --git a/sim/unit_test/mmio_test/readme.txt b/sim/unit_test/mmio_test/readme.txt new file mode 100644 index 0000000..ab6cacf --- /dev/null +++ b/sim/unit_test/mmio_test/readme.txt @@ -0,0 +1,78 @@ +***Test Description*** +This is the unit test for FIM CSR access (MMIO Regions) targeting: +- PF0 (FME, SPI, PCIE, ST2MM, Port-Gasket, HSSI) +- PF0.VF0 (HE-LB) +- PF0.VF1 (HE-MEM) +- PF0.VF2 (HE-HSSI)" + +It covers the following test scenarios: + * MMIO write 32-bit address and 64-bit address (FIM and AFU) + * MMIO read 32-bit address and 64-bit address (FIM and AFU) + * Simple memory loopback test using he_lb - this is similar to simple_test_pcie except that it uses a simple pcie BFM + +Description of test modules: + * test_csr_defs.sv - Defines CSR addresses. + * tester_tests.sv - Defines all the test cases for current test. + * script/Makefile_VCS.mk - Script to run the test in VCS only + * script/Makefile.mk - Script to run the test in VCS & Questasim. MSIM_D5005=1 option to be given for Questasim else will be for VCS. + +***Running the test*** +To run the test in VCS: + 1) Make sure the shell environment is set up to run VCS/VCSMX. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Synopsys VCS simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_vcs + dve -full64 -vpd vcdplus.vpd & + +To run the test in QuestaSim: + 1) Make sure the shell environment is set up to run Questasim. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Mentor Graphics QuestaSim simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh MSIM=1 + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_msim + vsim -view vsim.wlf & diff --git a/sim/unit_test/mmio_test/scripts/run_sim.sh b/sim/unit_test/mmio_test/scripts/run_sim.sh new file mode 100755 index 0000000..271afc5 --- /dev/null +++ b/sim/unit_test/mmio_test/scripts/run_sim.sh @@ -0,0 +1,48 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)/.." + + +VCSMX=0 +MSIM=0 +SKIP_IP_CMP=0 +TEST_DIR=$(pwd) + +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh run_sim.sh SKIP_IP_CMP=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +# Source common sim setup script + +. ${TEST_DIR}/../../scripts/sim_setup_common.sh TEST_DIR="$TEST_DIR" VCSMX=$VCSMX MSIM=$MSIM + +# Run simulation +if [ $VCSMX -eq 1 ]; then + echo "Running VCSMX simulation in $TEST_DIR/sim_vcsmx" + cd ${TEST_DIR}/sim_vcsmx && sh ${TEST_SRC_DIR}/vcsmx_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +elif [ $MSIM -eq 1 ]; then + echo "Running Questasim simulation in $TEST_DIR/sim_msim" + cd ${TEST_DIR}/sim_msim && sh ${TEST_SRC_DIR}/msim_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="-l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="" +else + echo "Running VCS simulation in $TEST_DIR/sim_vcs" + cd ${TEST_DIR}/sim_vcs && sh ${TEST_SRC_DIR}/vcs_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +fi + + diff --git a/sim/unit_test/mmio_test/scripts/test_list.f b/sim/unit_test/mmio_test/scripts/test_list.f new file mode 100644 index 0000000..2dd96ff --- /dev/null +++ b/sim/unit_test/mmio_test/scripts/test_list.f @@ -0,0 +1 @@ +$WORKDIR/sim/unit_test/mmio_test/testbench/test_csr_defs.sv diff --git a/sim/unit_test/mmio_test/testbench/test_csr_defs.sv b/sim/unit_test/mmio_test/testbench/test_csr_defs.sv new file mode 100644 index 0000000..ce0b36b --- /dev/null +++ b/sim/unit_test/mmio_test/testbench/test_csr_defs.sv @@ -0,0 +1,61 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// CSR addresses are defined for the testcase. +// +//----------------------------------------------------------------------------- +`ifndef __TEST_CSR_DEFS__ +`define __TEST_CSR_DEFS__ + +package test_csr_defs; + localparam FME_DFH = 32'h0; + localparam FME_SCRATCHPAD0 = FME_DFH + 32'h28; + + localparam PMCI_DFH = 32'h10000; + localparam PMCI_SCRATCHPAD = PMCI_DFH + 32'h28; + + localparam PCIE_DFH = 32'h20000; + localparam PCIE_SCRATCHPAD = PCIE_DFH + 32'h8; + + localparam ST2MM_DFH = 32'h80000; + localparam ST2MM_SCRATCHPAD = ST2MM_DFH + 32'h8; + + localparam PGSK_DFH = 32'h90000; + localparam PGSK_SCRATCHPAD = PGSK_DFH + 32'hb8; + + localparam HSSI_DFH = 32'h30000; + localparam HSSI_SCRATCHPAD = HSSI_DFH + 32'h38; + + localparam HE_LB_DFH = 32'h00000; + localparam HE_LB_SCRATCHPAD = HE_LB_DFH + 32'h100; + + localparam HE_HSSI_SCRATCHPAD = HE_LB_DFH + 32'h48; + + localparam PORT_CONTROL = 32'h91038; + +/* + localparam PCIE_DFH = 32'h10000; + localparam PCIE_SCRATCHPAD = PCIE_DFH + 32'h8; + localparam PCIE_TESTPAD = PCIE_DFH + 32'h38; + + localparam HE_LB_SCRATCHPAD = 32'h100; + //localparam EMIF_DFH = 32'h41000; + + localparam HSSI_DFH = 32'h60000; + localparam HSSI_RCFG_DATA = HSSI_DFH + 32'h30; + + //localparam USER_CLK_DFH = 32'h20000; + //localparam USER_CLK_CMD_0 = 32'h20008; + + //localparam PCIE_DFH_VALUE = 64'h3000000010000020; + //localparam EMIF_DFH_VALUE = 64'h3000000010000009; + //localparam HSSI_DFH_VALUE = 64'h300000001000100f; + //localparam USER_CLK_DFH_VALUE = 64'h3000010000000014; +*/ + +endpackage + +`endif diff --git a/sim/unit_test/mmio_test/testbench/tester_tests.sv b/sim/unit_test/mmio_test/testbench/tester_tests.sv new file mode 100755 index 0000000..7712708 --- /dev/null +++ b/sim/unit_test/mmio_test/testbench/tester_tests.sv @@ -0,0 +1,546 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// This file defines all the test cases for current test. +// +// main_test() is the main entry function which the tester calls +// to execute the unit tests. +// +//----------------------------------------------------------------------------- + +import test_csr_defs::*; + +//------------------- +// Test utilities +//------------------- +task incr_test_id; +begin + test_id = test_id + 1; +end +endtask + +task post_test_util; + input logic [31:0] old_test_err_count; + logic result; +begin + if (test_utils::get_err_count() > old_test_err_count) begin + result = 1'b0; + end else begin + result = 1'b1; + end + + repeat (10) + @(posedge avl_clk); + + @(posedge avl_clk); + reset_test = 1'b1; + repeat (5) + @(posedge avl_clk); + reset_test = 1'b0; + + f_reset_tag(); + + if (result) begin + $display("\nTest status: OK"); + test_summary[test_id].result = 1'b1; + end else begin + $display("\nTest status: FAILED"); + test_summary[test_id].result = 1'b0; + end + incr_test_id(); +end +endtask + +task print_test_header; + input [1024*8-1:0] test_name; +begin + $display("\n********************************************"); + $display(" Running TEST(%0d) : %0s", test_id, test_name); + $display("********************************************"); + test_summary[test_id].name = test_name; +end +endtask + +task verify_pcie_err_count; + output logic result; + input logic [7:0] exp_err; +begin + // Wait 30 clock cycles for checker error to be logged + repeat (30) + @(posedge fim_clk); + + if (checker_err_count != exp_err) + begin + result = 1'b0; + $display("Failed - expected errors: %0d, actual errors: %0d", exp_err, checker_err_count); + end else begin + result = 1'b1; + $display("Checker error count matches: %0d", checker_err_count); + end + if (~result) + test_utils::incr_err_count(); +end +endtask + +task verify_pcie_err_code; + output logic result; + input logic [31:0] exp_err_code; +begin + // Wait 10 clock cycles for checker error to be logged + repeat (10) + @(posedge fim_clk); + + if (pcie_p2c_chk_err_code != exp_err_code) + begin + result = 1'b0; + $display("Failed - error code mismatch, expected: 0x%x, actual: 0x%x", exp_err_code, pcie_p2c_chk_err_code); + end else begin + result = 1'b1; + $display("Checker error code matches: 0x%x", pcie_p2c_chk_err_code); + end + if (~result) + test_utils::incr_err_count(); +end +endtask + +//------------------- +// Test cases +//------------------- +// Test 32-bit CSR access +task test_csr_access_32; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [31:0] data; + logic [31:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE32(addr_mode, addr, bar, vf_active, pfn, vfn, data); + READ32(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR write and read mismatch! write=0x%x read=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 32-bit CSR access to unused CSR region +task test_unused_csr_access_32; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [31:0] data; + logic [31:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE32(addr_mode, addr, bar, vf_active, pfn, vfn, data); + READ32(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== 32'h0) begin + $display("\nERROR: Expected 32'h0 to be returned for unused CSR region, actual:0x%x\n",scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 64-bit CSR access +task test_csr_access_64; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [63:0] data; + logic [63:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE64(addr_mode, addr, bar, vf_active, pfn, vfn, data); + READ64(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR write and read mismatch! write=0x%x read=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 64-bit CSR read access +task test_csr_read_64; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [63:0] data; + logic [63:0] scratch; + logic error; +begin + result = 1'b1; + READ64(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR read mismatch! expected=0x%x actual=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 32-bit CSR read access +task test_csr_read_32; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [31:0] data; + logic [31:0] scratch; + logic error; +begin + result = 1'b1; + READ32(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR read mismatch! expected=0x%x actual=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 64-bit CSR access to unused CSR region +task test_unused_csr_access_64; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [63:0] data; + logic [63:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE64(addr_mode, addr, bar, vf_active, pfn, vfn, data); + READ64(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== 64'h0) begin + $display("\nERROR: Expected 64'h0 to be returned for unused CSR region, actual:0x%x\n",scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test MMIO access with 32-bit address +task test_mmio_addr32; + output logic result; +begin + print_test_header("test_mmio_addr32"); + test_mmio(result, ADDR32); +end +endtask + +// Test MMIO access with 64-bit address +task test_mmio_addr64; + output logic result; +begin + print_test_header("test_mmio_addr64"); + test_mmio(result, ADDR64); +end +endtask + +// Test memory write 32-bit address +task test_mmio; + output logic result; + input e_addr_mode addr_mode; + logic [63:0] base_addr; + logic [63:0] addr; + logic [63:0] scratch; + logic error; + logic [31:0] old_test_err_count; +begin + + old_test_err_count = test_utils::get_err_count(); + result = 1'b1; + + // ----------------------------------------------------------------------------------------------------------------------------- + // (result, addr_mode, addr, bar, vf_act, pfn, vfn, data ) + // ----------------------------------------------------------------------------------------------------------------------------- + $display("\n---------------------------------------------------"); + $display("Test CSR access to FME CSR region"); + $display("---------------------------------------------------\n"); + test_csr_access_32 (result, addr_mode, FME_SCRATCHPAD0, 0, 1'b0, 0, 0, 'h1111_2222 ); + test_csr_access_32 (result, addr_mode, FME_SCRATCHPAD0+32'h4, 0, 1'b0, 0, 0, 'hAAAA_BBBB ); + test_csr_read_64 (result, addr_mode, FME_SCRATCHPAD0, 0, 1'b0, 0, 0, 'hAAAA_BBBB_1111_2222 ); + test_csr_access_64 (result, addr_mode, FME_SCRATCHPAD0, 0, 1'b0, 0, 0, 'h1111_2222_3333_4444 ); + + $display("\n---------------------------------------------------"); + $display("Test CSR access to SPI CSR region"); + $display("---------------------------------------------------\n"); + test_csr_access_32 (result, addr_mode, PMCI_SCRATCHPAD, 0, 1'b0, 0, 0, 'h1221_2112 ); + test_csr_access_32 (result, addr_mode, PMCI_SCRATCHPAD+32'h4, 0, 1'b0, 0, 0, 'hABBA_BAAB ); + test_csr_read_64 (result, addr_mode, PMCI_SCRATCHPAD, 0, 1'b0, 0, 0, 'hABBA_BAAB_1221_2112 ); + test_csr_access_64 (result, addr_mode, PMCI_SCRATCHPAD, 0, 1'b0, 0, 0, 'h1111_2222_3333_4444 ); + + $display("\n---------------------------------------------------"); + $display("Test CSR access to PCIE CSR region"); + $display("---------------------------------------------------\n"); + test_csr_access_32 (result, addr_mode, PCIE_SCRATCHPAD, 0, 1'b0, 0, 0, 'h2222_0000 ); + test_csr_access_32 (result, addr_mode, PCIE_SCRATCHPAD+32'h4, 0, 1'b0, 0, 0, 'hAAAA_CCCC ); + test_csr_read_64 (result, addr_mode, PCIE_SCRATCHPAD, 0, 1'b0, 0, 0, 'hAAAA_CCCC_2222_0000 ); + test_csr_access_64 (result, addr_mode, PCIE_SCRATCHPAD, 0, 1'b0, 0, 0, 'h1111_2222_3333_4444 ); + + $display("\n---------------------------------------------------"); + $display("Test CSR access to ST2MM CSR region"); + $display("---------------------------------------------------\n"); + test_csr_access_64 (result, addr_mode, ST2MM_SCRATCHPAD, 0, 1'b0, 0, 0, 'h1111_2222_3333_4444 ); + test_csr_access_32 (result, addr_mode, ST2MM_SCRATCHPAD, 0, 1'b0, 0, 0, 'h3333_1111 ); + + $display("\n---------------------------------------------------"); + $display("Test CSR access to Port Gasket region"); + $display("\n---------------------------------------------------"); + test_csr_access_64 (result, addr_mode, PGSK_SCRATCHPAD, 0, 1'b0, 0, 0, 'h1111_2222_3333_4444 ); + test_csr_access_32 (result, addr_mode, PGSK_SCRATCHPAD, 0, 1'b0, 0, 0, 'haa02_02aa ); + + $display("\n---------------------------------------------------"); + $display("Test CSR access to HSSI region"); + $display("\n---------------------------------------------------"); + test_csr_access_64 (result, addr_mode, HSSI_SCRATCHPAD, 0, 1'b0, 0, 0, 'h4444_2222_3333_1111 ); + test_csr_access_32 (result, addr_mode, HSSI_SCRATCHPAD, 0, 1'b0, 0, 0, 'haa02_02aa ); + + $display("\n---------------------------------------------------"); + $display("Test CSR access to HE-LB (PF0-VF0)"); + $display("\n---------------------------------------------------"); + test_csr_access_64 (result, addr_mode, HE_LB_SCRATCHPAD, 0, 1'b1, 3'h0, 0, 'h1111_3333_2222_4444 ); + test_csr_access_32 (result, addr_mode, HE_LB_SCRATCHPAD, 0, 1'b1, 3'h0, 0, 'hdead_beef ); + + $display("\n---------------------------------------------------"); + $display("Test CSR access to HE-MEM (PF0-VF1)"); + $display("\n---------------------------------------------------"); + test_csr_access_64 (result, addr_mode, HE_LB_SCRATCHPAD, 0, 1'b1, 3'h0, 1, 'h1111_3333_2222_4444 ); + test_csr_access_32 (result, addr_mode, HE_LB_SCRATCHPAD, 0, 1'b1, 3'h0, 1, 'habc0_4321 ); + + $display("\n---------------------------------------------------"); + $display("Test CSR access to HE-HSSI (PF0-VF2)"); + $display("\n---------------------------------------------------"); + test_csr_access_64 (result, addr_mode, HE_HSSI_SCRATCHPAD, 0, 1'b1, 3'h0, 2, 'h1111_2222_3333_4444 ); + test_csr_access_32 (result, addr_mode, HE_HSSI_SCRATCHPAD, 0, 1'b1, 3'h0, 2, 'haa06_06aa ); + + + post_test_util(old_test_err_count); +end +endtask + +// Test AFU MMIO read +task test_afu_mmio; + output logic result; + e_addr_mode addr_mode; + logic [31:0] addr; + logic [63:0] scratch; + logic error; + logic [31:0] old_test_err_count; + logic [4:0][31:0] unsupported_addr_vec; +begin + print_test_header("test_afu_mmio"); + old_test_err_count = test_utils::get_err_count(); + + result = 1'b1; + addr_mode = ADDR32; + + // AFU CSR + test_csr_access_32(result, addr_mode, 32'h41000, 2, 1'b0, 0, 0, 'hAFC0_0001); + test_csr_access_64(result, addr_mode, 32'h41020, 2, 1'b0, 0, 0, 'hAFC0_0003_AFC0_0002); + + // AFU unsupported address range should return 0 + unsupported_addr_vec[0] = 32'h40030; + unsupported_addr_vec[1] = 32'h41200; + unsupported_addr_vec[2] = 32'h42060; + unsupported_addr_vec[3] = 32'h43030; + unsupported_addr_vec[4] = 32'h44000; + for (int i=0; i<5; ++i) begin + addr = unsupported_addr_vec[i]; + WRITE64(addr_mode, addr, 2, 1'b0, 0, 0, 64'h1234_5678_9abc_def0); + test_csr_read_64(result, addr_mode, addr, 0, 1'b0, 0, 0, 'h0); + if (~result) begin + $display("Error: MMIO read to unsupported AFU address (addr=0x%0x) doesn't return 0.", addr); + end + end + + // Test illegal memory read returns CPL + // misaligned address + READ64(addr_mode, 32'h41001, 2, 1'b0, 0, 0, scratch, error); + if (~error) begin + $display("\nERROR: MMIO read with unaligned address did not return CPL with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end + // illegal length + CSR_READ(addr_mode, 32'h41000, 10'd16, 2, 1'b0, 0, 0, scratch, error); + if (~error) begin + $display("\nERROR: MMIO read with illegal length did not return CPL with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end + + post_test_util(old_test_err_count); +end +endtask + +// Test back-to-back MMIO write and read +task test_mmio_burst; + output logic result; + input logic valid_csr_region; + input [2:0] bar; + input logic [31:0] base_addr; + input [1024*8-1:0] test_name; + logic [31:0] addr; + logic [63:0] exp_data; + logic [63:0] scratch; + logic [1:0] status; + t_tlp_tag tag; + logic [127:0] pending_req_vec; + t_tlp_tag [127:0] pending_rd_tag_vec; + logic [127:0][31:0] pending_rd_addr_vec; + int req_cnt; + logic [31:0] old_test_err_count; +begin + print_test_header(test_name); + old_test_err_count = test_utils::get_err_count(); + result = 1'b1; + + // Stretch test MMIO write access with a burst of MMIO write + addr = base_addr; + for (int i=0; i<128; i=i+1) begin + $display("WRITE32: address=0x%x bar=%0d pfn=0 vfn=0, data=0x%x", addr, bar, (i+1)); + // addr_32, addr, length, bar, vf_active, pfn, vfn, data + create_mwr_packet(ADDR32, addr, 10'd1, bar, 1'b0, 0, 0, {32'h0, i+1}); + addr += 32'h4; + end + f_send_test_packet(); + + pending_req_vec = '0; + + // Stretch test MMIO read access with a burst of MMIO read + fork + // MMIO request + begin : mmio_read_thread + addr = base_addr; + for (int i=0; i<128; i=i+1) begin + f_get_tag(tag); + pending_req_vec[i] = 1'b1; + pending_rd_tag_vec[i] = tag; + pending_rd_addr_vec[i] = addr; + // addr_32, address, length, bar, vf_active, pfn, vfn + create_mrd_packet(tag, ADDR32, addr, 10'd1, bar, 1'b0, 0, 0); + $display("(%0d) Added MRD packet: address=0x%x bar=%0d pfn=0 vfn=0 tag=%0d", i, addr, bar, tag); + + req_cnt += 1; + addr += 32'h4; + + // Send the packets when all tags are occupied + if (req_cnt == RP_MAX_TAGS) begin + f_send_test_packet(); + wait (~|tag_active); + req_cnt = '0; + end + end + // Send the remaining packets + f_send_test_packet(); + end + + // MMIO response + begin : mmio_rsp_thread + for (int i=0; i<128; i=i+1) begin + wait (pending_req_vec[i]); + + exp_data = valid_csr_region ? {32'h0, (i+1)} : 'h0; + $display("READ64: address=0x%x bar=%0d pfn=0 vfn=0 tag=%0d\n", pending_rd_addr_vec[i], bar, pending_rd_tag_vec[i]); + read_mmio_rsp(pending_rd_tag_vec[i], scratch, status); + + if (status !== 3'h0) begin + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch[31:0] !== exp_data[31:0]) begin + $display("\nERROR: Data mismatched! expected=0x%x actual=0x%x\n", exp_data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end + end + end + join + + post_test_util(old_test_err_count); +end +endtask + + +//------------------- +// Test main entry +//------------------- +task main_test; + output logic test_result; + logic valid_csr_region; +begin + assert_afu_reset(PORT_CONTROL); + deassert_afu_reset(PORT_CONTROL); + $display("Starting mmio test .."); + test_mmio_addr32 (test_result); + test_mmio_addr64 (test_result); + +end +endtask + diff --git a/sim/unit_test/mmio_test/vcs_setup.sh b/sim/unit_test/mmio_test/vcs_setup.sh new file mode 100644 index 0000000..04c4168 --- /dev/null +++ b/sim/unit_test/mmio_test/vcs_setup.sh @@ -0,0 +1,110 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcs" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +# source ${SIM_ROOTDIR}/d5005/unit_test/scripts/vcs_filelist.sh +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vcs -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + +define+R1_UNIT_TEST_ENV \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $VCS_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -top $TOP_LEVEL_NAME +error+20 -l vcs.log + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/mmio_test/vcsmx_setup.sh b/sim/unit_test/mmio_test/vcsmx_setup.sh new file mode 100755 index 0000000..56bde7f --- /dev/null +++ b/sim/unit_test/mmio_test/vcsmx_setup.sh @@ -0,0 +1,115 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcsmx" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +# source ${SIM_ROOTDIR}/d5005/unit_test/scripts/vcs_filelist.sh +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlogan -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + +define+R1_UNIT_TEST_ENV \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $INC_DIR \ + $RTL_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC +error+1 -l vlog.log + +vcs -full64 -ntb_opts -licqueue +vcs+lic+wait \ + +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -l vcs.log $TOP_LEVEL_NAME + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/pcie_csr_test/msim_setup.sh b/sim/unit_test/pcie_csr_test/msim_setup.sh new file mode 100755 index 0000000..b617b8a --- /dev/null +++ b/sim/unit_test/pcie_csr_test/msim_setup.sh @@ -0,0 +1,113 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="-finish exit" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR="$TEST_SRC_DIR/../../.." +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="${TEST_DIR}/sim_msim" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for msim # +################################### +. ${SIM_DIR}/msim_filelist.sh + +################################## +### BFM related verilog source ### +################################## +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlib work +vlog -mfcu -timescale=1ns/1fs +libext+.v+.sv -lint -sv \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+HTILE \ + +define+R1_UNIT_TEST_ENV \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+MSIM_IOFS_D5005 \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $MSIM_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -work work -l msim_vlog.log -suppress 8386,7033,7061,2388,12003,2892 +#suppress 8386 : Replication operator in Conactenation Operator +#suppress 2892 : Net type of 'clk' was not explicitly declared +#suppress 7061 : Variable 'clear_tdo_bit_select' driven in an always_ff block, may not be driven by any other process +#suppress 7033 : Variable 'parser_result' driven in a combinational block, may not be driven by any other process + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + vopt $TOP_LEVEL_NAME -o opt -suppress 2732,12003,7033,3837 -l msim_vopt.log + vsim -c opt -nosva -suppress 2732,12003,7033,3837 -do "add log -r /*; run -all ; quit -f" +fi + + diff --git a/sim/unit_test/pcie_csr_test/readme.txt b/sim/unit_test/pcie_csr_test/readme.txt new file mode 100644 index 0000000..b637b43 --- /dev/null +++ b/sim/unit_test/pcie_csr_test/readme.txt @@ -0,0 +1,76 @@ +***Test Description*** +This is the unit test for PCIE CSR access +The PCIE CSR implements full RW,RO,RW1C registers. + +It covers the following test scenarios: + * MMIO write 32-bit address and 64-bit address (PCIE_CSR) + * MMIO read 32-bit address and 64-bit address (PCIE_CSR) + * Illegal MMIO access - write is blocked and CPL is returned for read + + +Description of test modules: + * test_csr_defs.sv - Defines CSR addresses. + * tester_tests.sv - Defines all the test cases for current test. + * script/Makefile_VCS.mk - Script to run the test in VCS only + * script/Makefile.mk - Script to run the test in VCS & Questasim. MSIM_D5005=1 option to be given for Questasim else will be for VCS. + +***Running the test*** +To run the test in VCS: + 1) Make sure the shell environment is set up to run VCS/VCSMX. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Synopsys VCS simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_vcs + dve -full64 -vpd vcdplus.vpd & + +To run the test in QuestaSim: + 1) Make sure the shell environment is set up to run Questasim. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Mentor Graphics QuestaSim simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh MSIM=1 + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_msim + vsim -view vsim.wlf & diff --git a/sim/unit_test/pcie_csr_test/scripts/run_sim.sh b/sim/unit_test/pcie_csr_test/scripts/run_sim.sh new file mode 100755 index 0000000..271afc5 --- /dev/null +++ b/sim/unit_test/pcie_csr_test/scripts/run_sim.sh @@ -0,0 +1,48 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)/.." + + +VCSMX=0 +MSIM=0 +SKIP_IP_CMP=0 +TEST_DIR=$(pwd) + +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh run_sim.sh SKIP_IP_CMP=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +# Source common sim setup script + +. ${TEST_DIR}/../../scripts/sim_setup_common.sh TEST_DIR="$TEST_DIR" VCSMX=$VCSMX MSIM=$MSIM + +# Run simulation +if [ $VCSMX -eq 1 ]; then + echo "Running VCSMX simulation in $TEST_DIR/sim_vcsmx" + cd ${TEST_DIR}/sim_vcsmx && sh ${TEST_SRC_DIR}/vcsmx_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +elif [ $MSIM -eq 1 ]; then + echo "Running Questasim simulation in $TEST_DIR/sim_msim" + cd ${TEST_DIR}/sim_msim && sh ${TEST_SRC_DIR}/msim_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="-l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="" +else + echo "Running VCS simulation in $TEST_DIR/sim_vcs" + cd ${TEST_DIR}/sim_vcs && sh ${TEST_SRC_DIR}/vcs_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +fi + + diff --git a/sim/unit_test/pcie_csr_test/scripts/test_list.f b/sim/unit_test/pcie_csr_test/scripts/test_list.f new file mode 100644 index 0000000..0c28508 --- /dev/null +++ b/sim/unit_test/pcie_csr_test/scripts/test_list.f @@ -0,0 +1 @@ +$WORKDIR/sim/unit_test/pcie_csr_test/testbench/test_csr_defs.sv diff --git a/sim/unit_test/pcie_csr_test/testbench/test_csr_defs.sv b/sim/unit_test/pcie_csr_test/testbench/test_csr_defs.sv new file mode 100644 index 0000000..681fe33 --- /dev/null +++ b/sim/unit_test/pcie_csr_test/testbench/test_csr_defs.sv @@ -0,0 +1,95 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// CSR addresses are defined for the testcase. +// +//----------------------------------------------------------------------------- +`ifndef __TEST_CSR_DEFS__ +`define __TEST_CSR_DEFS__ + +package test_csr_defs; + localparam FME_DFH = 32'h0; + localparam FME_SCRATCHPAD0 = FME_DFH + 32'h28; + + localparam PMCI_DFH = 32'h10000; + localparam PMCI_SCRATCHPAD = PMCI_DFH + 32'h28; + + localparam PCIE_DFH = 32'h20000; + localparam PCIE_SCRATCHPAD = PCIE_DFH + 32'h8; + + localparam ST2MM_DFH = 32'h80000; + localparam ST2MM_SCRATCHPAD = ST2MM_DFH + 32'h8; + + localparam PGSK_DFH = 32'h90000; + localparam PGSK_SCRATCHPAD = PGSK_DFH + 32'hb8; + + localparam HSSI_DFH = 32'h30000; + localparam HSSI_SCRATCHPAD = HSSI_DFH + 32'h38; + + localparam HE_LB_DFH = 32'h00000; + localparam HE_LB_SCRATCHPAD = HE_LB_DFH + 32'h100; + + localparam HE_HSSI_SCRATCHPAD = HE_LB_DFH + 32'h48; + + localparam PORT_CONTROL = 32'h91038; + + localparam EMIF_DFH = 32'h41000; + localparam PCIE_DFH_VALUE = 64'h3000000010000020; + localparam EMIF_DFH_VALUE = 64'h3000000010000009; + localparam HSSI_DFH_VALUE = 64'h300000001000100f; + localparam USER_CLK_DFH_VALUE = 64'h3000010000000014; + localparam SPI_DFH = 32'h43000; + localparam SPI_DFH_VALUE = 64'h300001000000000e; + localparam SPI_WRITEDATA = 32'h43020; + localparam HSSI_RCFG_DATA = 32'h42030; + localparam VFME_AFU_ID_L = 32'h8; + localparam VFME_AFU_ID_L_VALUE = 64'hBEE40B2B259849A9; + localparam VFME_AFU_ID_H = 32'h10; + localparam VFME_AFU_ID_H_VALUE = 64'hA8E434048329FE10; + localparam VFME_MSIX_VADDR0 = 32'h3000; + localparam USER_CLK_DFH = 32'h20000; + localparam USER_CLK_CMD_0 = 32'h20008; + + localparam USER_IRQ0_ADDR = 64'h20000; + localparam USER_IRQ1_ADDR = 64'h21000; + localparam USER_IRQ2_ADDR = 64'h22000; + localparam USER_IRQ3_ADDR = 64'h23000; + localparam USER_IRQ4_ADDR = 64'h24000; + localparam USER_IRQ5_ADDR = 64'h25000; + localparam USER_IRQ6_ADDR = 64'h26000; + + localparam USER_IRQ0_DATA = 32'hbeef_0000; + localparam USER_IRQ1_DATA = 32'hbeef_0001; + localparam USER_IRQ2_DATA = 32'hbeef_0002; + localparam USER_IRQ3_DATA = 32'hbeef_0003; + localparam USER_IRQ4_DATA = 32'hbeef_0004; + localparam USER_IRQ5_DATA = 32'hbeef_0005; + localparam USER_IRQ6_DATA = 32'hbeef_0006; + + //Added for PCIE_CSR_TEST + localparam PCIE0_ERROR = 32'h4020; + localparam PCIE_STAT = 32'h20010; + localparam PCIE_ERROR_MASK = 32'h20018; + localparam PCIE_ERROR = 32'h20020; + localparam PCIE_UNUSED_OFFSET = 32'h40ff8; +/* + localparam PCIE_DFH = 32'h10000; + localparam PCIE_SCRATCHPAD = PCIE_DFH + 32'h8; + localparam PCIE_TESTPAD = PCIE_DFH + 32'h38; + + localparam HE_LB_SCRATCHPAD = 32'h100; + + localparam HSSI_DFH = 32'h60000; + localparam HSSI_RCFG_DATA = HSSI_DFH + 32'h30; + + //localparam USER_CLK_DFH = 32'h20000; + //localparam USER_CLK_CMD_0 = 32'h20008; + +*/ + +endpackage + +`endif diff --git a/sim/unit_test/pcie_csr_test/testbench/tester_tests.sv b/sim/unit_test/pcie_csr_test/testbench/tester_tests.sv new file mode 100755 index 0000000..e8d0e23 --- /dev/null +++ b/sim/unit_test/pcie_csr_test/testbench/tester_tests.sv @@ -0,0 +1,369 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// This file defines all the test cases for current test. +// +// main_test() is the main entry function which the tester calls +// to execute the unit tests. +// +//----------------------------------------------------------------------------- + +import test_csr_defs::*; +import ofs_fim_pcie_pkg::*; //Added by Ashish + +//------------------- +// Test utilities +//------------------- +task incr_test_id; +begin + test_id = test_id + 1; +end +endtask + +task post_test_util; + input logic [31:0] old_test_err_count; + logic result; +begin + if (test_utils::get_err_count() > old_test_err_count) begin + result = 1'b0; + end else begin + result = 1'b1; + end + + repeat (10) + @(posedge avl_clk); + + @(posedge avl_clk); + reset_test = 1'b1; + repeat (5) + @(posedge avl_clk); + reset_test = 1'b0; + + f_reset_tag(); + + if (result) begin + $display("\nTest status: OK"); + test_summary[test_id].result = 1'b1; + end else begin + $display("\nTest status: FAILED"); + test_summary[test_id].result = 1'b0; + end + incr_test_id(); +end +endtask + +task print_test_header; + input [1024*8-1:0] test_name; +begin + $display("\n********************************************"); + $display(" Running TEST(%0d) : %0s", test_id, test_name); + $display("********************************************"); + test_summary[test_id].name = test_name; +end +endtask + +task verify_mmio_err_count; + output logic result; + input logic [7:0] exp_err; +begin + // Wait 30 clock cycles for checker error to be logged + repeat (30) + @(posedge fim_clk); + + if (mmio_err_count != exp_err) + begin + result = 1'b0; + $display("Failed - expected errors: %0d, actual errors: %0d", exp_err, mmio_err_count); + end else begin + result = 1'b1; + $display("MMIO error count matches: %0d", mmio_err_count); + end + if (~result) + test_utils::incr_err_count(); +end +endtask + +//------------------- +// Test cases +//------------------- +// Test 32-bit CSR access +task test_csr_access_32; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [PF_WIDTH-1:0] pfn; + input logic [VF_WIDTH-1:0] vfn; + input logic [31:0] data; + logic [31:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE32(addr_mode, addr, bar, vf_active, pfn, vfn, data); + READ32(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR write and read mismatch! write=0x%x read=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 32-bit CSR access to unused CSR region +task test_unused_csr_access_32; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [PF_WIDTH-1:0] pfn; + input logic [VF_WIDTH-1:0] vfn; + input logic [31:0] data; + logic [31:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE32(addr_mode, addr, bar, vf_active, pfn, vfn, data); + READ32(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== 32'h0) begin + $display("\nERROR: Expected 32'h0 to be returned for unused CSR region, actual:0x%x\n",scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 64-bit CSR access +task test_csr_access_64; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [PF_WIDTH-1:0] pfn; + input logic [VF_WIDTH-1:0] vfn; + input logic [63:0] data; + logic [63:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE64(addr_mode, addr, bar, vf_active, pfn, vfn, data); + READ64(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR write and read mismatch! write=0x%x read=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 32-bit CSR read access +task test_csr_read_32; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [PF_WIDTH-1:0] pfn; + input logic [VF_WIDTH-1:0] vfn; + input logic [31:0] data; + logic [31:0] scratch; + logic error; +begin + result = 1'b1; + READ32(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR read mismatch! expected=0x%x actual=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 64-bit CSR read access +task test_csr_read_64; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [PF_WIDTH-1:0] pfn; + input logic [VF_WIDTH-1:0] vfn; + input logic [63:0] data; + logic [63:0] scratch; + logic error; +begin + result = 1'b1; + READ64(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR read mismatch! expected=0x%x actual=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 64-bit CSR access to unused CSR region +task test_unused_csr_access_64; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [PF_WIDTH-1:0] pfn; + input logic [VF_WIDTH-1:0] vfn; + input logic [63:0] data; + logic [63:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE64(addr_mode, addr, bar, vf_active, pfn, vfn, data); + READ64(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== 64'h0) begin + $display("\nERROR: Expected 64'h0 to be returned for unused CSR region, actual:0x%x\n",scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test MMIO access with 32-bit address +task test_mmio_addr32; + output logic result; +begin + print_test_header("test_mmio_addr32"); + test_mmio(result, ADDR32); +end +endtask + +// Test MMIO access with 64-bit address +task test_mmio_addr64; + output logic result; +begin + print_test_header("test_mmio_addr64"); + test_mmio(result, ADDR64); +end +endtask + +// Test memory write 32-bit address +task test_mmio; + output logic result; + input e_addr_mode addr_mode; + logic [63:0] base_addr; + logic [63:0] addr; + logic [63:0] scratch; + logic error; + logic [31:0] old_test_err_count; +begin + old_test_err_count = test_utils::get_err_count(); + result = 1'b1; + + $display("Test CSR access"); + test_csr_access_32(result, addr_mode, PCIE_SCRATCHPAD, 0, 1'b0, 0, 0, 'h1111_2222); + test_csr_access_64(result, addr_mode, PCIE_SCRATCHPAD, 0, 1'b0, 0, 0, 'h1111_2222_3333_4444); + test_csr_access_32(result, addr_mode, PCIE_SCRATCHPAD, 0, 1'b0, 0, 0, 'hAAAA_BBBB); + test_csr_access_32(result, addr_mode, PCIE_SCRATCHPAD+3'h4, 0, 1'b0, 0, 0, 'hCCCC_DDDD); + test_csr_read_64(result, addr_mode, PCIE_SCRATCHPAD, 0, 1'b0, 0, 0, 'hCCCC_DDDD_AAAA_BBBB); + test_csr_read_64(result, addr_mode, PCIE_DFH, 0, 1'b0, 0, 0, 'h3000000100000020); + test_csr_read_64(result, addr_mode, PCIE_STAT, 0, 1'b0, 0, 0, 'h0); + + test_csr_access_64(result, addr_mode, PCIE_ERROR_MASK, 0, 1'b0, 0, 0, 'h3FF); + test_csr_access_64(result, addr_mode, PCIE_ERROR_MASK, 0, 1'b0, 0, 0, 'h0); + + $display("Test CSR access to unused CSR region"); + test_unused_csr_access_32(result, addr_mode, PCIE_UNUSED_OFFSET, 0, 1'b0, 0, 0, 'hF00D_0001); + test_unused_csr_access_64(result, addr_mode, PCIE_UNUSED_OFFSET, 0, 1'b0, 0, 0, 'hF00D_0001_6464_6464); + + verify_mmio_err_count(result, 0); + post_test_util(old_test_err_count); +end +endtask + +// Test PCIE error bits in PCIE0_ERROR register +task test_pcie_err; + output logic result; + logic [31:0] old_test_err_count; +begin + print_test_header("test_pcie_err"); + + old_test_err_count = test_utils::get_err_count(); + result = 1'b1; + + @(posedge avl_clk); +// force DUT.pcie_top.pcie_csr.i_chk_rx_err_code = 32'h1ff; + force DUT.pcie_wrapper.pcie_top.pcie_csr.i_chk_rx_err_code = 32'h1ff; + repeat (4) + @(posedge avl_clk); + // release DUT.pcie_top.pcie_csr.i_chk_rx_err_code; + release DUT.pcie_wrapper.pcie_top.pcie_csr.i_chk_rx_err_code ; + + repeat (20) + @(posedge avl_clk); + + $display("Reading PCIE_ERROR register in PCIe feature region"); + test_csr_read_32(result, ADDR32, PCIE_ERROR, 0, 1'b0, 0, 0, 32'h1ff); + +// $display("Writing Reading PCIE_ERROR register in PCIe feature region"); +// test_csr_access_32(result, ADDR32, PCIE_ERROR, 0, 1'b0, 0, 0, 32'h1ff); + +// $display("Reading PCIE0_ERROR register in FME Global Error feature region"); +// test_csr_read_32(result, ADDR32, PCIE0_ERROR, 0, 1'b0, 0, 0, 32'h1ee1); + + verify_mmio_err_count(result, 0); + post_test_util(old_test_err_count); +end +endtask + +//------------------- +// Test main entry +//------------------- +task main_test; + output logic test_result; + logic valid_csr_region; +begin + test_mmio_addr32 (test_result); + test_mmio_addr64 (test_result); + test_pcie_err (test_result); +end +endtask + + + diff --git a/sim/unit_test/pcie_csr_test/vcs_setup.sh b/sim/unit_test/pcie_csr_test/vcs_setup.sh new file mode 100644 index 0000000..57231e6 --- /dev/null +++ b/sim/unit_test/pcie_csr_test/vcs_setup.sh @@ -0,0 +1,109 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcs" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +# source ${SIM_ROOTDIR}/d5005/unit_test/scripts/vcs_filelist.sh +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vcs -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $VCS_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -top $TOP_LEVEL_NAME +error+20 -l vcs.log + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/pcie_csr_test/vcsmx_setup.sh b/sim/unit_test/pcie_csr_test/vcsmx_setup.sh new file mode 100755 index 0000000..383db68 --- /dev/null +++ b/sim/unit_test/pcie_csr_test/vcsmx_setup.sh @@ -0,0 +1,114 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcsmx" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +# source ${SIM_ROOTDIR}/d5005/unit_test/scripts/vcs_filelist.sh +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlogan -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $INC_DIR \ + $RTL_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC +error+1 -l vlog.log + +vcs -full64 -ntb_opts -licqueue +vcs+lic+wait \ + +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -l vcs.log $TOP_LEVEL_NAME + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/remote_stp_test/msim_setup.sh b/sim/unit_test/remote_stp_test/msim_setup.sh new file mode 100755 index 0000000..b617b8a --- /dev/null +++ b/sim/unit_test/remote_stp_test/msim_setup.sh @@ -0,0 +1,113 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="-finish exit" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR="$TEST_SRC_DIR/../../.." +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="${TEST_DIR}/sim_msim" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for msim # +################################### +. ${SIM_DIR}/msim_filelist.sh + +################################## +### BFM related verilog source ### +################################## +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlib work +vlog -mfcu -timescale=1ns/1fs +libext+.v+.sv -lint -sv \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+HTILE \ + +define+R1_UNIT_TEST_ENV \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+MSIM_IOFS_D5005 \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $MSIM_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -work work -l msim_vlog.log -suppress 8386,7033,7061,2388,12003,2892 +#suppress 8386 : Replication operator in Conactenation Operator +#suppress 2892 : Net type of 'clk' was not explicitly declared +#suppress 7061 : Variable 'clear_tdo_bit_select' driven in an always_ff block, may not be driven by any other process +#suppress 7033 : Variable 'parser_result' driven in a combinational block, may not be driven by any other process + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + vopt $TOP_LEVEL_NAME -o opt -suppress 2732,12003,7033,3837 -l msim_vopt.log + vsim -c opt -nosva -suppress 2732,12003,7033,3837 -do "add log -r /*; run -all ; quit -f" +fi + + diff --git a/sim/unit_test/remote_stp_test/readme.txt b/sim/unit_test/remote_stp_test/readme.txt new file mode 100644 index 0000000..c801199 --- /dev/null +++ b/sim/unit_test/remote_stp_test/readme.txt @@ -0,0 +1,72 @@ +***Test Description*** + +This is the unit test for remote stp + +It covers mmio read access to remote_stp registers + +Description of test modules: + * test_csr_defs.sv - Defines CSR addresses and values . + * tester_tests.sv - Defines all the test cases for current test. + * script/Makefile_VCS.mk - Script to run the test in VCS only + * script/Makefile.mk - Script to run the test in VCS & Questasim. MSIM_D5005=1 option to be given for Questasim else will be for VCS. + +***Running the test*** +To run the test in VCS: + 1) Make sure the shell environment is set up to run VCS/VCSMX. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Synopsys VCS simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_vcs + dve -full64 -vpd vcdplus.vpd & + +To run the test in QuestaSim: + 1) Make sure the shell environment is set up to run Questasim. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Mentor Graphics QuestaSim simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh MSIM=1 + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_msim + vsim -view vsim.wlf & diff --git a/sim/unit_test/remote_stp_test/scripts/run_sim.sh b/sim/unit_test/remote_stp_test/scripts/run_sim.sh new file mode 100755 index 0000000..271afc5 --- /dev/null +++ b/sim/unit_test/remote_stp_test/scripts/run_sim.sh @@ -0,0 +1,48 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)/.." + + +VCSMX=0 +MSIM=0 +SKIP_IP_CMP=0 +TEST_DIR=$(pwd) + +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh run_sim.sh SKIP_IP_CMP=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +# Source common sim setup script + +. ${TEST_DIR}/../../scripts/sim_setup_common.sh TEST_DIR="$TEST_DIR" VCSMX=$VCSMX MSIM=$MSIM + +# Run simulation +if [ $VCSMX -eq 1 ]; then + echo "Running VCSMX simulation in $TEST_DIR/sim_vcsmx" + cd ${TEST_DIR}/sim_vcsmx && sh ${TEST_SRC_DIR}/vcsmx_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +elif [ $MSIM -eq 1 ]; then + echo "Running Questasim simulation in $TEST_DIR/sim_msim" + cd ${TEST_DIR}/sim_msim && sh ${TEST_SRC_DIR}/msim_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="-l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="" +else + echo "Running VCS simulation in $TEST_DIR/sim_vcs" + cd ${TEST_DIR}/sim_vcs && sh ${TEST_SRC_DIR}/vcs_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +fi + + diff --git a/sim/unit_test/remote_stp_test/scripts/test_list.f b/sim/unit_test/remote_stp_test/scripts/test_list.f new file mode 100644 index 0000000..f56db8f --- /dev/null +++ b/sim/unit_test/remote_stp_test/scripts/test_list.f @@ -0,0 +1 @@ +$WORKDIR/sim/unit_test/remote_stp_test/testbench/test_csr_defs.sv diff --git a/sim/unit_test/remote_stp_test/testbench/test_csr_defs.sv b/sim/unit_test/remote_stp_test/testbench/test_csr_defs.sv new file mode 100755 index 0000000..3378217 --- /dev/null +++ b/sim/unit_test/remote_stp_test/testbench/test_csr_defs.sv @@ -0,0 +1,77 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// CSR addresses are defined for the testcase. +// +//----------------------------------------------------------------------------- +`ifndef __TEST_CSR_DEFS__ +`define __TEST_CSR_DEFS__ + +package test_csr_defs; + + // ****************************************************************************************** + // PORT Register Addresses + // ****************************************************************************************** + parameter PORT_STP_DFH_ADDR = 32'h93000; + parameter PORT_STP_STATUS_ADDR = PORT_STP_DFH_ADDR + 32'h8; + parameter PORT_STP_UNIMPLEMENTED_ADDR = PORT_STP_DFH_ADDR + 32'h10; + parameter RSTP_DBG_IP_ADDR = PORT_STP_DFH_ADDR + 32'h1000; + parameter RSTP_H2T_MEM_ADDR = PORT_STP_DFH_ADDR + 32'h2000; + parameter RSTP_T2H_MEM_ADDR = PORT_STP_DFH_ADDR + 32'h3000; + + localparam PORT_CONTROL = 32'h91038; + + + // ****************************************************************************************** + // PORT Register Default Values + // ****************************************************************************************** + parameter PORT_STP_DFH_VAL = 64'h30000000D0002013; + parameter PORT_STP_STATUS_VAL = 64'h0000000000000000; + + + // ****************************************************************************************** + // Debug Interface IP Register Offset Addresses (From RSTP_DBG_IP_ADDR) + // ****************************************************************************************** + parameter DBG_IP_RDDM_VER_ADDR = 32'h0000; //RO + parameter DBG_IP_RDDM_REV_ADDR = 32'h0004; //RO + parameter DBG_IP_CTRL_ADDR = 32'h0020; //bit0 RCoR-reset packet transit, byte1 RW-internal AVST lpbk + parameter DBG_IP_EXT_MEM_DEPTH_ADDR = 32'h0024; //RO + parameter DBG_IP_EXT_DESC_DEPTH_ADDR = 32'h002C; //RO + parameter DBG_IP_INTR_MASK_ADDR = 32'h0048; //RW ([0]- h2t, [1]- t2h) + + parameter DBG_IP_H2T_SLOT_AVAIL_ADDR = 32'h0100; //RO + parameter DBG_IP_H2T_PKT_LEN_ADDR = 32'h0108; //WO ([30:0]- length, [31]- last descriptor of packet) + parameter DBG_IP_H2T_START_LOC_ADDR = 32'h010C; //WO + parameter DBG_IP_H2T_CONNECTION_ID_ADDR = 32'h0110; //WO + parameter DBG_IP_H2T_CHANNEL_ID_ADDR = 32'h0114; //WO + + parameter DBG_IP_T2H_PKT_LEN_ADDR = 32'h0208; //RO ([30:0]- length, [31]- last descriptor of packet) + parameter DBG_IP_T2H_START_LOC_ADDR = 32'h020C; //RO + parameter DBG_IP_T2H_CONNECTION_ID_ADDR = 32'h0210; //RO + parameter DBG_IP_T2H_CHANNEL_ID_ADDR = 32'h0214; //RO + parameter DBG_IP_T2H_DESC_DONE_ADDR = 32'h0218; //WO + + parameter DBG_IP_T2H_UNIMPLEMENTED_ADDR = 32'h0300; // Not implemented + + + + // ****************************************************************************************** + // Debug Interface IP Register Values + // ****************************************************************************************** + parameter DBG_IP_RDDM_VER_VAL = 32'h5244_444D; + parameter DBG_IP_RDDM_REV_VAL = 32'h0000_0000; + parameter DBG_IP_EXT_MEM_DEPTH_VAL = 32'h0000_1000; + parameter DBG_IP_EXT_DESC_DEPTH_VAL = 32'h0000_0020; + parameter DBG_IP_H2T_SLOT_AVAIL_VAL = 32'h0000_0020; + parameter DBG_IP_T2H_PKT_LEN_VAL = 32'h0000_0000; + parameter DBG_IP_T2H_START_LOC_VAL = 32'h0000_0000; + + parameter DBG_IP_FAULT_VAL = 32'hDEAD_C0DE; + + +endpackage + +`endif diff --git a/sim/unit_test/remote_stp_test/testbench/tester_tests.sv b/sim/unit_test/remote_stp_test/testbench/tester_tests.sv new file mode 100755 index 0000000..ee11448 --- /dev/null +++ b/sim/unit_test/remote_stp_test/testbench/tester_tests.sv @@ -0,0 +1,715 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// This file defines all the test cases for current test. +// +// main_test() is the main entry function which the tester calls +// to execute the unit tests. +// +//----------------------------------------------------------------------------- + +import test_csr_defs::*; + +//------------------- +// Test utilities +//------------------- +task incr_test_id; +begin + test_id = test_id + 1; +end +endtask + +task post_test_util; + input logic [31:0] old_test_err_count; + logic result; +begin + if (test_utils::get_err_count() > old_test_err_count) begin + result = 1'b0; + end else begin + result = 1'b1; + end + + repeat (10) + @(posedge avl_clk); + + @(posedge avl_clk); + reset_test = 1'b1; + repeat (5) + @(posedge avl_clk); + reset_test = 1'b0; + + f_reset_tag(); + + if (result) begin + $display("\nTest status: OK"); + test_summary[test_id].result = 1'b1; + end else begin + $display("\nTest status: FAILED"); + test_summary[test_id].result = 1'b0; + end + incr_test_id(); +end +endtask + +task print_test_header; + input [1024*8-1:0] test_name; +begin + $display("\n********************************************"); + $display(" Running TEST(%0d) : %0s", test_id, test_name); + $display("********************************************"); + test_summary[test_id].name = test_name; +end +endtask + +task verify_mmio_err_count; + output logic result; + input logic [7:0] exp_err; +begin + // Wait 30 clock cycles for checker error to be logged + repeat (30) + @(posedge fim_clk); + + if (mmio_err_count != exp_err) + begin + result = 1'b0; + $display("Failed - expected errors: %0d, actual errors: %0d", exp_err, mmio_err_count); + end else begin + result = 1'b1; + $display("MMIO error count matches: %0d", mmio_err_count); + end + if (~result) + test_utils::incr_err_count(); +end +endtask + +//------------------- +// Test cases +//------------------- +// Test 32-bit CSR access +task test_csr_access_32; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [31:0] data; + logic [31:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE32(addr_mode, addr, bar, vf_active, pfn, vfn, data); + READ32(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR write and read mismatch! write=0x%x read=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 64-bit CSR access +task test_csr_access_64; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [63:0] data; + logic [63:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE64(addr_mode, addr, bar, vf_active, pfn, vfn, data); + READ64(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR write and read mismatch! write=0x%x read=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 64-bit CSR read access +task test_csr_read_64; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [63:0] data; + logic [63:0] scratch; + logic error; +begin + result = 1'b1; + READ64(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR read mismatch! expected=0x%x actual=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 32-bit data access with 64b address +task test_csr_access_32_addr64; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [31:0] data; + logic [31:0] scratch; + logic error; +begin + result = 1'b1; + + WRITE32(addr_mode, {32'h0000_eecc,addr}, bar, vf_active, pfn, vfn, data); + READ32(addr_mode, {32'h0000_eecc,addr}, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR write and read mismatch! write=0x%x read=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test 32-bit read access +task test_csr_read_access_32; + output logic result; + input e_addr_mode addr_mode; + input logic [31:0] addr; + input logic [2:0] bar; + input logic vf_active; + input logic [ofs_fim_pcie_pkg::PF_WIDTH-1:0] pfn; + input logic [ofs_fim_pcie_pkg::VF_WIDTH-1:0] vfn; + input logic [31:0] data; + logic [31:0] scratch; + logic error; +begin + result = 1'b1; + + READ32(addr_mode, addr, bar, vf_active, pfn, vfn, scratch, error); + + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== data) begin + $display("\nERROR: CSR write and read mismatch! write=0x%x read=0x%x\n", data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end +end +endtask + +// Test back-to-back MMIO access +task test_mmio_burst; + output logic result; + input logic valid_csr_region; + input [2:0] bar; + input logic [31:0] base_addr; + input [1024*8-1:0] test_name; + logic [31:0] addr; + logic [63:0] exp_data; + logic [63:0] scratch; + logic [1:0] status; + t_tlp_tag tag; + logic [127:0] pending_req_vec; + t_tlp_tag [127:0] pending_rd_tag_vec; + logic [127:0][31:0] pending_rd_addr_vec; + int req_cnt; + logic [31:0] old_test_err_count; +begin + print_test_header(test_name); + old_test_err_count = test_utils::get_err_count(); + result = 1'b1; + + // Stretch test MMIO write access with a burst of MMIO write + addr = base_addr; + for (int i=0; i<128; i=i+1) begin + $display("WRITE32: address=0x%x bar=%0d pfn=0 vfn=0, data=0x%x", addr, bar, (i+1)); + // addr_32, addr, length, bar, vf_active, pfn, vfn, data + create_mwr_packet(ADDR32, addr, 10'd1, bar, 1'b0, 0, 0, {32'h0, i+1}); + addr += 32'h4; + end + f_send_test_packet(); + + pending_req_vec = '0; + + // Stretch test MMIO read access with a burst of MMIO read + fork + // MMIO request + begin : mmio_read_thread + addr = base_addr; + for (int i=0; i<128; i=i+1) begin + f_get_tag(tag); + pending_req_vec[i] = 1'b1; + pending_rd_tag_vec[i] = tag; + pending_rd_addr_vec[i] = addr; + // addr_32, address, length, bar, vf_active, pfn, vfn + create_mrd_packet(tag, ADDR32, addr, 10'd1, bar, 1'b0, 0, 0); + $display("(%0d) Added MRD packet: address=0x%x bar=%0d pfn=0 vfn=0 tag=%0d", i, addr, bar, tag); + + req_cnt += 1; + addr += 32'h4; + + // Send the packets when all tags are occupied + if (req_cnt == RP_MAX_TAGS) begin + f_send_test_packet(); + wait (~|tag_active); + req_cnt = '0; + end + end + // Send the remaining packets + f_send_test_packet(); + end + + // MMIO response + begin : mmio_rsp_thread + for (int i=0; i<128; i=i+1) begin + wait (pending_req_vec[i]); + + exp_data = valid_csr_region ? {32'h0, (i+1)} : 'h0; + $display("READ64: address=0x%x bar=%0d pfn=0 vfn=0 tag=%0d\n", pending_rd_addr_vec[i], bar, pending_rd_tag_vec[i]); + read_mmio_rsp(pending_rd_tag_vec[i], scratch, status); + + if (status !== 3'h0) begin + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch[31:0] !== exp_data[31:0]) begin + $display("\nERROR: Data mismatched!address=0x%x expected=0x%x actual=0x%x\n",pending_rd_addr_vec[i], exp_data, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end + end + end + join + + if (result) verify_mmio_err_count(result, 0); + post_test_util(old_test_err_count); +end + +endtask + +// Test back-to-back MMIO read +task test_mmio_burst_rd; + output logic result; + input logic valid_csr_region; + input [2:0] bar; + input logic [31:0] base_addr; + input logic [31:0] start_value; + input int num_loc; + logic [31:0] addr; + logic [63:0] exp_data; + logic [63:0] scratch; + logic [1:0] status; + t_tlp_tag tag; + logic [127:0] pending_req_vec; + t_tlp_tag [127:0] pending_rd_tag_vec; + logic [127:0][31:0] pending_rd_addr_vec; + int req_cnt; + logic [31:0] old_test_err_count; +begin + result = 1'b1; + + pending_req_vec = '0; + + // Stretch test MMIO read access with a burst of MMIO read + fork + // MMIO request + begin : mmio_read_thread + addr = base_addr; + for (int i=0; i> 2), PKT_LEN/4 ); + + // 64- RO + CSR_READ(addr_mode, RSTP_DBG_IP_ADDR + DBG_IP_T2H_CONNECTION_ID_ADDR, 10'd02, 2, 1'b0, 0, 0, scratch, error); + if (error) begin + $display("\nERROR: Completion is returned with unsuccessful status.\n"); + test_utils::incr_err_count(); + result = 1'b0; + end else if (scratch !== {CHANNEL_ID,CONN_ID}) begin + $display("\nERROR: DFH CSR expected and read mismatch! expected=0x%x read=0x%x\n", {CHANNEL_ID,CONN_ID}, scratch); + test_utils::incr_err_count(); + result = 1'b0; + end + + //-------------------------------- + // Negative tests + //-------------------------------- + + // unimplemented PORT STP address + //READ64(addr_mode, PORT_STP_UNIMPLEMENTED_ADDR, 2, 1'b0, 0, 0, scratch, error); + //if (scratch !== 64'hdeadc0dedeadc0de) begin + // $display("\nERROR: MMIO read with unimplemented address did not return CPL with unsuccessful status.\n"); + // test_utils::incr_err_count(); + // result = 1'b0; + //end + // + //// unimplemented DGB_IP address + //test_csr_read_access_32(result, addr_mode, RSTP_DBG_IP_ADDR + DBG_IP_T2H_UNIMPLEMENTED_ADDR, 2, 1'b0, 0, 0, DBG_IP_FAULT_VAL); + + // Write to ready only register + WRITE32(addr_mode, RSTP_DBG_IP_ADDR + DBG_IP_RDDM_VER_ADDR, 2, 1'b0, 0, 0, 'hF012CE); + test_csr_read_access_32(result, addr_mode, RSTP_DBG_IP_ADDR + DBG_IP_RDDM_VER_ADDR, 2, 1'b0, 0, 0, DBG_IP_RDDM_VER_VAL); + + // Read to write only register + test_csr_read_access_32(result, addr_mode, RSTP_DBG_IP_ADDR + DBG_IP_H2T_CONNECTION_ID_ADDR, 2, 1'b0, 0, 0, DBG_IP_FAULT_VAL); + + // asserting reset in between reset + //WRITE32(addr_mode, RSTP_DBG_IP_ADDR + DBG_IP_H2T_PKT_LEN_ADDR, 2, 1'b0, 0, 0, PKT_LEN); + // WRITE32(addr_mode, RSTP_DBG_IP_ADDR + DBG_IP_H2T_START_LOC_ADDR, 2, 1'b0, 0, 0, START_LOC); + //WRITE64(addr_mode, RSTP_DBG_IP_ADDR + DBG_IP_H2T_CONNECTION_ID_ADDR, 2, 1'b0, 0, 0, {CHANNEL_ID,CONN_ID}); + // Wating till h2t memory read is initiated from dbg_if ip + //@(posedge top_tb.DUT.corefim.port.port0.remote_stp_top.remote_debug_jtag_only.intel_jop_blaster_0.intel_jop_blaster_0.st_dbg_ip_h2t_mem_read); + @(posedge top_tb.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip_h2t_mem_read); //doubt + + WRITE32(addr_mode, RSTP_DBG_IP_ADDR + DBG_IP_CTRL_ADDR, 2, 1'b0, 0, 0, CTRL_REG); + + #2500000 + // Check for last location in h2t memory is PKT_LEN away from START_LOC + //scratch = top_tb.DUT.corefim.port.port0.remote_stp_top.remote_debug_jtag_only.mm_interconnect_0.intel_jop_blaster_0_avmm_s_address; + scratch = {top_tb.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.avmm_s_address[13:0]}; //doubt + + if (scratch == LAST_LOC) begin + $display("\nERROR: H2T Last Location indicates reset note applied"); + test_utils::incr_err_count(); + result = 1'b0; + end + + // Proper after transation stopped abruptly + // WRITE32(addr_mode, RSTP_DBG_IP_ADDR + DBG_IP_H2T_PKT_LEN_ADDR, 2, 1'b0, 0, 0, PKT_LEN); + // WRITE32(addr_mode, RSTP_DBG_IP_ADDR + DBG_IP_H2T_START_LOC_ADDR, 2, 1'b0, 0, 0, START_LOC); + //WRITE64(addr_mode, RSTP_DBG_IP_ADDR + DBG_IP_H2T_CONNECTION_ID_ADDR, 2, 1'b0, 0, 0, {CHANNEL_ID,CONN_ID}); + // #200 + // test_mmio_burst_rd(result,1'b1,2, RSTP_T2H_MEM_ADDR, (START_LOC >> 2), PKT_LEN/4 ); + + + if (result) verify_mmio_err_count(result, 0); + post_test_util(old_test_err_count); + */ + + end +endtask + +// Test AFU reset +task test_afu_reset; + logic [31:0] old_test_err_count; +begin + print_test_header("test_afu_reset"); + old_test_err_count = test_utils::get_err_count(); + + // Reset AFU + assert_afu_reset(PORT_CONTROL); + deassert_afu_reset(PORT_CONTROL); + post_test_util(old_test_err_count); +end +endtask + +//------------------- +// Test main entry +//------------------- +task main_test; + output logic test_result; + logic valid_csr_region; +begin + + valid_csr_region = 1'b1; + //test_mmio_burst (test_result, valid_csr_region, 2, RSTP_H2T_MEM_ADDR, "test_h2t_mmio_burst"); + //test_mmio_burst (test_result, valid_csr_region, 2, RSTP_T2H_MEM_ADDR, "test_t2h_mmio_burst"); + test_rstp_mmio (test_result); + +end +endtask diff --git a/sim/unit_test/remote_stp_test/vcs_setup.sh b/sim/unit_test/remote_stp_test/vcs_setup.sh new file mode 100644 index 0000000..57231e6 --- /dev/null +++ b/sim/unit_test/remote_stp_test/vcs_setup.sh @@ -0,0 +1,109 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcs" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +# source ${SIM_ROOTDIR}/d5005/unit_test/scripts/vcs_filelist.sh +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vcs -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $VCS_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -top $TOP_LEVEL_NAME +error+20 -l vcs.log + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/remote_stp_test/vcsmx_setup.sh b/sim/unit_test/remote_stp_test/vcsmx_setup.sh new file mode 100755 index 0000000..383db68 --- /dev/null +++ b/sim/unit_test/remote_stp_test/vcsmx_setup.sh @@ -0,0 +1,114 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcsmx" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +# source ${SIM_ROOTDIR}/d5005/unit_test/scripts/vcs_filelist.sh +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlogan -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $INC_DIR \ + $RTL_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC +error+1 -l vlog.log + +vcs -full64 -ntb_opts -licqueue +vcs+lic+wait \ + +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -l vcs.log $TOP_LEVEL_NAME + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/scripts/regress_run.py b/sim/unit_test/scripts/regress_run.py new file mode 100644 index 0000000..61d8a64 --- /dev/null +++ b/sim/unit_test/scripts/regress_run.py @@ -0,0 +1,1001 @@ +#!/usr/bin/env python3 +# Copyright (C) 2022-2023 Intel Corporation +# SPDX-License-Identifier: MIT + +import argparse +import subprocess +import logging +import multiprocessing +import time +import datetime +import re +import os +import sys +import smtplib +import textwrap +from email.mime.text import MIMEText +from email.mime.multipart import MIMEMultipart + +class Test: + + test_count = 0 + test_count_pass = 0 + test_count_fail = 0 + + def __init__(self, name, directory, unit_test_pass, time_elapsed): + self.name = name + self.dir = directory + self.unit_test_pass = unit_test_pass + self.time_elapsed = time_elapsed + Test.test_count += 1 + if unit_test_pass: + Test.test_count_pass += 1 + else: + Test.test_count_fail += 1 + + def get_name(self): + return self.name + + def set_directory(self,directory): + self.dir = directory + + def get_directory(self): + return self.dir + + def set_unit_test_pass(self,pass_val): + if self.unit_test_pass ^ pass_val: + if pass_val: + Test.test_count_pass += 1 + Test.test_count_fail -= 1 + else: + Test.test_count_pass -= 1 + Test.test_count_fail += 1 + self.unit_test_pass = pass_val + + def unit_test_test_passed(self): + if not self.unit_test_pass: + Test.test_count_pass += 1 + Test.test_count_fail -= 1 + self.unit_test_pass = True + + def unit_test_test_failed(self): + if self.unit_test_pass: + Test.test_count_pass -= 1 + Test.test_count_fail += 1 + self.unit_test_pass = False + + def get_unit_test_pass(self): + return self.unit_test_pass + + def get_test_count(self): + return Test.test_count + + def get_test_count_passed(self): + return Test.test_count_pass + + def get_test_count_failed(self): + return Test.test_count_fail + + def set_time_elapsed(self,delta): + self.time_elapsed = delta + + def get_time_elapsed(self): + return self.time_elapsed + + def print(self): + logger.info(f"Test Object name..............: {self.name}") + logger.info(f" dir...............: {self.dir}") + logger.info(f" unit_test_pass....: {self.unit_test_pass}") + logger.info(f" time_elapsed......: {self.time_elapsed}") + + +class FarmTest(Test): + + def __init__(self, name, directory, unit_test_pass, test_info): + super().__init__(name, directory, unit_test_pass, test_info[0]) + self.arc_job_id = test_info[1] + self.arc_job_status = test_info[2] + self.arc_job_host_name = test_info[3] + self.arc_job_return_code = test_info[4] + + def get_arc_job(self): + return self.arc_job_id + + def get_arc_job_status(self): + return self.arc_job_status + + def get_arc_job_host_name(self): + return self.arc_job_host_name + + def get_arc_job_return_code(self): + return self.arc_job_return_code + + def print(self): + logger.info(f"Farm Test Object name...............: {self.name}") + logger.info(f" dir................: {self.dir}") + logger.info(f" unit_test_pass.....: {self.unit_test_pass}") + logger.info(f" time_elapsed.......: {self.time_elapsed}") + logger.info(f" arc_job_id.........: {self.arc_job_id}") + logger.info(f" arc_job_status.....: {self.arc_job_status}") + logger.info(f" arc_job_host_name..: {self.arc_job_host_name}") + logger.info(f" arc_job_return_code: {self.arc_job_return_code}") + + +def check_nfs(): + df_cmd_line = r'df -P -T .' + logger.debug(f"NFS: Commands follow:") + logger.debug(f" df: {df_cmd_line}") + check_nfs_pattern = r'\S+\s+(\w+)' + fs = 'None' + df_cmd = subprocess.Popen(df_cmd_line.split(), stdout=subprocess.PIPE, bufsize=1, universal_newlines=True) + with df_cmd.stdout: + for line in iter(df_cmd.stdout.readline, ""): + logger.debug(f"NFS: Line Check: {line}") + line_contains_pattern = re.search(check_nfs_pattern, line) + if (line_contains_pattern): + fs = line_contains_pattern.group(1) + df_cmd.wait() + command_success = df_cmd.poll() + logger.debug(f"NFS: Command Success = {command_success}") + logger.debug(f"NFS: Returning FS... = {fs}") + return fs + + +def get_rootdir(): + rootdir = os.getenv('OFS_ROOTDIR') + + if rootdir is None: + rootdir_pattern_found = 0 + rootdir = "" + rootdir_pattern = r'(/\S*)' + rootdir_cmd = subprocess.Popen(['git', 'rev-parse', '--show-toplevel'], stdout=subprocess.PIPE, bufsize=1, universal_newlines=True) + with rootdir_cmd.stdout: + for line in iter(rootdir_cmd.stdout.readline, ""): + line_contains_pattern = re.search(rootdir_pattern, line) + if (line_contains_pattern): + rootdir = line_contains_pattern.group(1) + rootdir_pattern_found = 1 + rootdir_cmd.wait() + command_success = rootdir_cmd.poll() + if (command_success == 0): + if (rootdir_pattern_found): + logger.debug(f"Git root directory search has returned successfully with return value {command_success}.") + logger.debug(f"Git root directory is: {rootdir}.") + else: + logger.error(f"ERROR: Git root directory returned is not in an absolute format.") + logger.error(f" Script {os.path.basename(__file__)} execution has been halted.") + sys.exit(1) + else: + logger.error(f"ERROR: Git root directory search has failed.") + logger.error(f" Script {os.path.basename(__file__)} execution has been halted.") + sys.exit(1) + + simdir = os.path.join(rootdir, 'sim') + if not os.path.isdir(simdir): + logger.error(f"ERROR: {simdir}/ directory not found. Check OFS_ROOTDIR environment varable.") + logger.error(f" Script {os.path.basename(__file__)} execution has been halted.") + sys.exit(1) + + return rootdir + +def get_email_list(): + email_list = os.getenv('EMAIL_LIST') + if email_list is not None: + if os.path.exists(email_list): + logger.info(f"Email list path set in shell and has value: {email_list}") + else: + logger.error(f"ERROR: OFS root directory variable $email_list is set to a location that does not exist:{email_list}") + sys.exit(1) + else: + logger.error(f"ERROR: OFS root directory variable $email_list is not set in this shell.") + sys.exit(1) + return email_list + + + +def get_last_commit(): + commit_pattern_found = 0 + commit = "" + commit_pattern = r'commit\s*(\w+)' + commit_cmd = subprocess.Popen(['git', 'log', '-n', '1'], stdout=subprocess.PIPE, bufsize=1, universal_newlines=True) + with commit_cmd.stdout: + for line in iter(commit_cmd.stdout.readline, ""): + line_contains_pattern = re.search(commit_pattern, line) + if (line_contains_pattern): + commit = line_contains_pattern.group(1) + commit_pattern_found = 1 + commit_cmd.wait() + command_success = commit_cmd.poll() + if (command_success == 0): + if (commit_pattern_found): + logger.debug(f"Git repo last commit search has returned successfully with return value {command_success}.") + logger.debug(f"Git repo last commit is: {commit}.") + else: + logger.error(f"ERROR: Git repo last commit could not be found.") + logger.error(f" Script {os.path.basename(__file__)} execution has been halted.") + sys.exit(1) + else: + logger.error(f"ERROR: Git Log command has failed.") + logger.error(f" Script {os.path.basename(__file__)} execution has been halted.") + sys.exit(1) + return commit + + +def find_files(filename, search_top_dir): + found_file_list = [] + for root_dir, dir_local, files in os.walk(search_top_dir): + if filename in files: + found_file_list.append(root_dir) + #logger.debug(f"FIND_FILES: Found: {os.path.join(root_dir,filename)}") + return found_file_list + +def generate_sim_files(): + sim_files_path=rootdir+ "/" + "ofs-common" + "/" + "scripts" + "/" + "common" + "/" + "sim" + "/" + "gen_sim_files.sh" + logger.info(f" generating sim files: {sim_files_path}") + sim_files = f"sh {sim_files_path} d5005" + files = subprocess.Popen(sim_files.split(), stdout=subprocess.DEVNULL, stderr=subprocess.STDOUT) + files.wait() + +def create_test_list(): + working_test_list = [] + filtered_test_list = [] + logger.debug(f"CTL: Package - {args.package}") + test_list_file = top_test_dir + "/list.txt" + if (args.package == "list"): + test_dir_pattern = r'^\.\/(\w+)\/scripts\/run_sim\.sh' + try: + with open(test_list_file) as file_object: + for line in file_object: + working_test_list.append(line.rstrip()) + except FileNotFoundError: + logger.error(f"ERROR: List of Unit Tests file not found: {test_list_file}") + sys.exit(1) + for test in working_test_list: + test_dir_pattern_found = re.search(test_dir_pattern,test) + if (test_dir_pattern_found): + test_dir = test_dir_pattern_found.group(1) + unit_test_script = top_test_dir + "/" + test_dir + "/" + "scripts" + "/" + "run_sim.sh" + if (os.path.exists(unit_test_script)): + logger.debug(f"CTL: Adding Test - {test_dir}") + filtered_test_list.append(test_dir) + else: + logger.error(f"ERROR: Unit Test run script not found: {unit_test_script} for test {test_dir}") + sys.exit(1) + else: + logger.error(f"ERROR: Unit Test in 'list.txt' file not in correct format: {test}") + logger.error(f" Expected regex pattern: {test_dir_pattern}") + else: + working_test_list = find_files("run_sim.sh",top_test_dir) + if (args.package == "all"): + for test in working_test_list: + test_path_split = test.split("/") + filtered_test_list.append(test_path_split[-2]) + else: + test_dir_pattern = "\/(" + args.package + r'\w+)\/scripts$' + logger.debug(f"Unit Test Search Pattern: {test_dir_pattern}") + for test in working_test_list: + logger.debug(f"Unit Test Searched..: {test}") + filtered_test_found = re.search(test_dir_pattern,test) + if (filtered_test_found): + filtered_test_list.append(filtered_test_found.group(1)) + return filtered_test_list + + +def check_positive_process_count(processes): + uint = int(processes) + if uint <= 0: + raise argparse.ArgumentTypeError(f"Number of processes: {uint} is not a positive integer.") + return uint + + +def send_email_report(): + #------------------------------------------------------------ + # Get User Info for e-mail + #------------------------------------------------------------ + whoami_pattern = r'(^\w+)' + finger_pattern = r'Name:\s*(\S+)' + whoami_command = subprocess.Popen(['whoami'], stdout=subprocess.PIPE, bufsize=1, universal_newlines=True) + with whoami_command.stdout: + for line in iter(whoami_command.stdout.readline, ""): + line_contains_name = re.search(whoami_pattern, line) + if (line_contains_name): + user_name = line_contains_name.group(1) + whoami_command.wait() + whoami_success = whoami_command.poll() + if (whoami_success == 0): + logger.debug(f"Found User Name: {user_name}") + finger_command = subprocess.Popen(['finger', user_name], stdout=subprocess.PIPE, bufsize=1, universal_newlines=True) + with finger_command.stdout: + for line in iter(finger_command.stdout.readline, ""): + line_contains_full_name = re.search(finger_pattern, line) + if (line_contains_full_name): + user_full_name = line_contains_full_name.group(1) + finger_command.wait() + finger_success = finger_command.poll() + if (finger_success == 0): + logger.debug(f"Found Full User Name: {user_full_name}") + else: + logger.debug(f"WARNING: User Name Not Found. Setting name to 'user' and full name to 'user.name'.") + user_full_name = "user.name" + else: + logger.debug(f"WARNING: User Name Not Found. Setting name to 'user' and full name to 'user.name'.") + user_name = "user" + user_full_name = "user.name" + full_name_split = user_full_name.split(".") + full_name_split_caps = [name.capitalize() for name in full_name_split] + full_name_caps = " ".join(full_name_split_caps) + logger.debug(f"Capitalized Name....: {full_name_caps}") + + #------------------------------------------------------------ + # Unit Test Case Data Header + #------------------------------------------------------------ + html_data = ''' + + + + + + + + + + + + + + + +
''' + #------------------------------------------------------------ + # Unit Test E-mail body text messages. + #------------------------------------------------------------ + html_body_text_header = ''' +

''' + html_body_text_error_header = ''' +

''' + html_body_text_ender = "

" + html_body_text_ender = "

" + html_data += html_body_text_header + html_data += f">>> Running Unit Test Regression Run Python Script: {os.path.basename(__file__)}" + html_data += html_body_text_ender + html_data += html_body_text_header + html_data += f" Simulator used for run........................: {args.simulator}" + html_data += html_body_text_ender + html_data += html_body_text_header + html_data += f" Begin running at date/time....................: {regression_run_start}" + html_data += html_body_text_ender + html_data += html_body_text_header + html_data += f" Regression run by user........................: {user_name} --> {full_name_caps}" + html_data += html_body_text_ender + html_data += html_body_text_header + html_data += f" Git Repo Root Directory is....................: {rootdir}" + html_data += html_body_text_ender + html_data += html_body_text_header + html_data += f" Git Repo Last Commit is.......................: {git_commit}" + html_data += html_body_text_ender + html_data += html_body_text_header + html_data += f" Script Location is............................: {script_dir}" + html_data += html_body_text_ender + html_data += html_body_text_header + html_data += f" Current Working Directory is..................: {current_dir}" + html_data += html_body_text_ender + html_data += html_body_text_header + html_data += f" Unit Test Package run.........................: {args.package}" + html_data += html_body_text_ender + html_data += html_body_text_header + html_data += f" Test Directory................................: {top_test_dir}" + html_data += html_body_text_ender + html_data += html_body_text_header + html_data += f" Number of Unit Tests run......................: {test_results[-1].get_test_count()}" + html_data += html_body_text_ender + html_data += html_body_text_header + html_data += f" Number of Unit Tests passing..................: {test_results[-1].get_test_count_passed()}" + html_data += html_body_text_ender + html_data += html_body_text_error_header + html_data += f" Number of Unit Tests failing..................: {test_results[-1].get_test_count_failed()}" + html_data += html_body_text_ender + html_data += html_body_text_header + html_data += f" End Unit Test regression running at date/time.: {regression_run_end}" + html_data += html_body_text_ender + html_data += html_body_text_header + html_data += f" Elapsed time for Unit Test regression run.....: {regression_run_elapsed}" + html_data += html_body_text_ender + + #------------------------------------------------------------ + # Unit Test Table Data Column Headers + #------------------------------------------------------------ + html_data += ''' + + + + + + ''' + row = 1 + for test_object in test_results: + test_name = test_object.get_name() + test_time = test_object.get_time_elapsed() + test_pass = test_object.get_unit_test_pass() + if (test_pass): + test_pass_str = "PASSED" + font_color = "rgb(256, 256, 256)" + else: + test_pass_str = "FAILED" + font_color = "rgb(255, 80, 80)" + #------------------------------------------------------------ + # Unit Test Case Table Cell + #------------------------------------------------------------ + html_data += "" + #------------------------------------------------------------ + # Table Cell #1 + #------------------------------------------------------------ + html_data += """ + """ + #------------------------------------------------------------ + # Table Cell #2 + #------------------------------------------------------------ + html_data += """ + """ + #------------------------------------------------------------ + # Table Cell #3 + #------------------------------------------------------------ + html_data += """ + + """ + row += 1 + html_data += """ +
+

Unit Test Case

+ 		+

Run Time

+ 		+

Status

+
+

" + html_data += f"{test_name}" + html_data += """

+ 		+

" + html_data += f"{test_time}" + html_data += """

+ 		+

" + html_data += f"{test_pass_str}" + html_data += """

+
+

 

+
+ + """ + #------------------------------------------------------------ + # Email set-up and sending + #------------------------------------------------------------ + server = smtplib.SMTP('localhost') + sender_email = user_name + if args.email_list: + read_file = email_list + "/email_list.f" + my_file = open(read_file, "r") + # reading the file + data = my_file.read() + # replacing end splitting the text + # when newline ('\n') is seen. + mail_into_list = data.split("\n") + my_file.close() + print(mail_into_list) + receiver_email = mail_into_list; + else: + receiver_email = user_name + + message = MIMEMultipart() + message["Subject"] = f"Unit Test Regression results - Tool:{args.simulator}, Processes:{args.max_parallel_running_process_count}, Package:{args.package}, Rootdir:{rootdir}" + message["From"] = sender_email + if args.email_list: + message["To"] = ", ".join(receiver_email) + else: + message["To"] = receiver_email + email_body = MIMEText(html_data,"html") + message.attach(email_body) + server.sendmail(sender_email, receiver_email, message.as_string()) + logger.info(f"Report Email sent to user:{user_name} --> {full_name_caps}") + server.quit() + + +def scan_test_results(test_list): + logger.debug(f"SCAN: top directory: {top_test_dir}") + if (args.simulator == 'msim'): + unit_test_fail_pattern = r'^#\s*Test FAILED!' + unit_test_pass_pattern = r'^#\s*Test passed!' + else: + unit_test_fail_pattern = r'^Test FAILED!' + unit_test_pass_pattern = r'^Test passed!' + for test in test_list: + test_name = test + sim_dir = top_test_dir + "/" + test + "/" + "scripts" + "/" + f"sim_{args.simulator}" + transcript = sim_dir + "/" + "transcript" + transcript_found = os.path.exists(transcript) + unit_test_fail = False + unit_test_pass = False + if (transcript_found): + logger.debug(f"transcript.......: {transcript}") + try: + with open(transcript) as file_object: + for line in file_object: + line = line.rstrip() + unit_test_fail_pattern_found = re.search(unit_test_fail_pattern,line) + if (unit_test_fail_pattern_found): + unit_test_fail = True + logger.debug(f"SCAN: Failure! Unit Test Simulation test:{test_name} ran with errors.") + break + unit_test_pass_pattern_found = re.search(unit_test_pass_pattern,line) + if (unit_test_pass_pattern_found): + unit_test_pass = True + logger.debug(f"SCAN: Success! Unit Test Simulation test:{test_name} ran without errors.") + break + if test_name in test_times_dict: + logger.debug(f" unit_test test time..: {test_times_dict[test_name]}") + else: + logger.debug(f" unit_test test time..: None") + if args.run_regression_locally : + test_result_object = Test(test_name, sim_dir, unit_test_pass, test_times_dict[test_name]) + else: + test_result_object = FarmTest(test_name, sim_dir, unit_test_pass, test_info_dict[test_name]) + test_results.append(test_result_object) + except FileNotFoundError: + logger.debug(f"WARNING: Simulation Log for test {test_name}: {transcript} was not found.") + else: + logger.debug(f"WARNING: Simulations Log File: {transcript} was not found.") + if (args.simulator != "msim"): # ModelSim/Questa still generates a "transcript" file, even when compilation fails. VCS does not - requiring this code. + unit_test_fail = True + unit_test_pass = False + if args.run_regression_locally : + test_result_object = Test(test_name, sim_dir, unit_test_pass, test_times_dict[test_name]) + else: + test_result_object = FarmTest(test_name, sim_dir, unit_test_pass, test_info_dict[test_name]) + test_results.append(test_result_object) + logger.debug(f"SCAN: Simulation compilation failed for test {test_name}.") + +def print_results(): + failing_tests = [] + failing_lines = [] + passing_tests = [] + passing_lines = [] + longest_line = 0 + longest_name = 0 + for test in test_results: + if test.unit_test_pass: + passing_tests.append(test) + test_name = test.get_name() + ":" + if len(test_name) > longest_name: + longest_name = len(test_name) + else: + failing_tests.append(test) + test_name = test.get_name() + ":" + if len(test_name) > longest_name: + longest_name = len(test_name) + total_tests = len(passing_tests) + len(failing_tests) + length_index_field = len(str(total_tests)) + fail_count_field = f"{len(failing_tests):>{length_index_field}}/{total_tests}" + pass_count_field = f"{len(passing_tests):>{length_index_field}}/{total_tests}" + for test in passing_tests: + test_name = test.get_name() + ":" + test_pass = "PASS" + test_time = test.get_time_elapsed() + pass_message = f" {test_name:.<{longest_name}} {test_pass} -- Time Elapsed:{test_time}" + if len(pass_message) > longest_line: + longest_line = len(pass_message) + passing_lines.append(pass_message) + for test in failing_tests: + test_name = test.get_name() + ":" + test_pass = "FAIL" + test_time = test.get_time_elapsed() + fail_message = f" {test_name:.<{longest_name}} {test_pass} -- Time Elapsed:{test_time}" + if len(fail_message) > longest_line: + longest_line = len(fail_message) + failing_lines.append(fail_message) + pass_message = f"Passing Unit Tests:{pass_count_field} " + pass_line = f"{pass_message:><{longest_line + 1}}" + logger.info(pass_line) + for line in passing_lines: + logger.info(line) + fail_message = f"Failing Unit Tests:{fail_count_field} " + fail_line = f"{fail_message:><{longest_line + 1}}" + logger.info(fail_line) + for line in failing_lines: + logger.info(line) + last_line = ">" * (longest_line + 1) + logger.info(last_line) + + + +def sim_process(index, test, test_dir_top, simulator): + sim_elapsed = datetime.timedelta(seconds = 0) + total_processes = len(list_of_tests)-1 + length_index_field = len(str(total_processes)) + index_string = f"{index:>{length_index_field}}/{total_processes}" + sim_start = datetime.datetime.now() + test_name_extracted = test.rstrip() + test = test.replace('\n', '') + test_dir = test_dir_top + '/' + test + '/' + "scripts" + test_file = test_dir_top + '/' + test + "/" + "scripts" + "/" + "run_sim.sh" + logger.info(f" Process {index_string} for test <{test_name_extracted:.<{longest_test_name}}> date/time started....: {sim_start}") + logger.info(f" Test Dir : {test_dir}") + if (os.path.exists(test_file)): + os.chdir(test_dir) + if (simulator == 'vcs'): + sim_command_line = f"sh run_sim.sh" + elif (simulator == 'vcsmx'): + sim_command_line = f"sh run_sim.sh VCSMX=1" + else: + sim_command_line = f"sh run_sim.sh MSIM=1" + sim = subprocess.Popen(sim_command_line.split(), stdout=subprocess.DEVNULL, stderr=subprocess.STDOUT) + sim.wait() + sim_result = sim.poll() + sim_end = datetime.datetime.now() + sim_elapsed = sim_end - sim_start + if sim_result == 0: + logger.debug(f" Simulation has returned normally for test <{test_name_extracted}> with return value {sim_result}.") + else: + logger.warning(f"WARNING: Simulation has returned abnormally for test <{test_name_extracted}> with return value {sim_result}.") + logger.info(f" Process {index_string} for test <{test_name_extracted:.<{longest_test_name}}> date/time completed..: {sim_end}") + logger.info(f" Process {index_string} for test <{test_name_extracted:.<{longest_test_name}}> time elapsed.........: {sim_elapsed}") + queue.put((test_name_extracted, sim_elapsed)) + else: + logger.warning(f"WARNING: Unit Test {test_file} could not be found.") + + +def sim_farm_process(index, test, test_dir_top, simulator): + arc_submit_return = r'(\w+)' + arc_submit_return_found = False + arc_job_pattern = r'id\s*:\s*(\w+)' + arc_job_status_pattern = r'status\s*:\s*(\w+)' + arc_job_start_time_pattern = r'set_running_at\s*:\s*(\w+)' + arc_job_finish_time_pattern = r'set_done_at\s*:\s*(\w+)' + arc_job_host_name_pattern = r'host\s*:\s*(\w+)' + arc_job_return_code_pattern = r'return_code\s*:\s*(\w+)' + sim_elapsed = datetime.timedelta(seconds = 0) + total_processes = len(list_of_tests)-1 + length_index_field = len(str(total_processes)) + index_string = f"{index:>{length_index_field}}/{total_processes}" + sim_start = datetime.datetime.now() + test_name_extracted = test.replace('\n', '') + test = test.replace('\n', '') + test_dir = test_dir_top + '/' + test + '/' + "scripts" + test_file = test_dir_top + '/' + test + "/" + "scripts" + "/" + "run_sim.sh" + logger.info(f" Farm process {index_string} for test <{test_name_extracted:.<{longest_test_name}}> date/time started....: {sim_start}") + if (os.path.exists(test_file)): + os.chdir(test_dir) + if (simulator == 'vcs'): + arc_submit_command_line = f"arc submit -PE flow/sw/bigmem mem=20000 -- sh run_sim.sh" + elif (simulator == 'vcsmx'): + arc_submit_command_line = f"arc submit -PE flow/sw/bigmem mem=20000 -- sh run_sim.sh VCSMX=1" + else: + arc_submit_command_line = f"arc submit -PE flow/sw/bigmem mem=20000 -- sh run_sim.sh MSIM=1" + arc_submit = subprocess.Popen(arc_submit_command_line.split(), stdout=subprocess.PIPE, bufsize=1, universal_newlines=True) + with arc_submit.stdout: + for line in iter(arc_submit.stdout.readline, ""): + line_contains_arc_submit_return_pattern = re.search(arc_submit_return, line) + if (line_contains_arc_submit_return_pattern): + arc_submit_return_id = line_contains_arc_submit_return_pattern.group(1) + arc_submit_return_found = True + arc_submit.wait() + arc_submit_result = arc_submit.poll() + if (arc_submit_result == 0) and arc_submit_return_found: + logger.debug(f" Farm job via ARC submit has returned normally for test <{test_name_extracted}> with return value {arc_submit_result} and ARC Job ID:{arc_submit_return_id}") + arc_job_done = False + arc_job_status = "None" + arc_job_last_status = "None" + arc_job_command_line = f"arc job {arc_submit_return_id}" + while not arc_job_done: + arc_job = subprocess.Popen(arc_job_command_line.split(), stdout=subprocess.PIPE, bufsize=1, universal_newlines=True) + with arc_job.stdout: + for line in iter(arc_job.stdout.readline, ""): + line_contains_arc_job_pattern = re.search(arc_job_pattern, line) + line_contains_arc_job_status_pattern = re.search(arc_job_status_pattern, line) + line_contains_arc_job_start_time_pattern = re.search(arc_job_start_time_pattern, line) + line_contains_arc_job_finish_time_pattern = re.search(arc_job_finish_time_pattern, line) + line_contains_arc_job_host_name_pattern = re.search(arc_job_host_name_pattern, line) + line_contains_arc_job_return_code_pattern = re.search(arc_job_return_code_pattern, line) + if (line_contains_arc_job_pattern): + arc_job_id = line_contains_arc_job_pattern.group(1) + if (line_contains_arc_job_status_pattern): + arc_job_last_status = arc_job_status + arc_job_status = line_contains_arc_job_status_pattern.group(1) + if (arc_job_status != arc_job_last_status): + logger.info(f" Farm process {index_string} for test <{test_name_extracted:.<{longest_test_name}}> process_status.......: {arc_job_status}") + if (arc_job_status == "done") or (arc_job_status == "error"): + arc_job_done = True + if (line_contains_arc_job_start_time_pattern): + arc_job_start_time = line_contains_arc_job_start_time_pattern.group(1) + if (line_contains_arc_job_finish_time_pattern): + arc_job_finish_time = line_contains_arc_job_finish_time_pattern.group(1) + arc_job_done = True + if (line_contains_arc_job_host_name_pattern): + arc_job_host_name = line_contains_arc_job_host_name_pattern.group(1) + if (line_contains_arc_job_return_code_pattern): + arc_job_return_code = line_contains_arc_job_return_code_pattern.group(1) + arc_job.wait() + arc_job_result = arc_job.poll() + time.sleep(1) + sim_end = datetime.datetime.now() + sim_elapsed = sim_end - sim_start + logger.info(f" Farm process {index_string} for test <{test_name_extracted:.<{longest_test_name}}> date/time completed..: {sim_end}") + logger.info(f" Farm process {index_string} for test <{test_name_extracted:.<{longest_test_name}}> time elapsed.........: {sim_elapsed}") + queue.put((test_name_extracted, sim_elapsed, arc_job_id, arc_job_status, arc_job_host_name, arc_job_return_code)) + else: + if (arc_submit_result != 0): + logger.warning(f"WARNING: ARC submit has returned abnormally for test <{test_name_extracted}> with return value {arc_submit_result}.") + if not arc_submit_return_found: + logger.warning(f"WARNING: ARC submit has failed to provide a job ID normally for test <{test_name_extracted}>.") + else: + logger.warning(f"WARNING: Unit Test {test_file} could not be found.") + + +if __name__ == "__main__": + test_times_dict = {} + test_info_dict = {} + test_results = [] + regression_run_start = datetime.datetime.now() + format = "%(asctime)s: %(message)s" + logger = logging.getLogger() + logger.setLevel(logging.INFO) + #logger.setLevel(logging.DEBUG) + formatter = logging.Formatter(format) + stdout_handler = logging.StreamHandler(sys.stdout) + stdout_handler.setLevel(logging.INFO) + #stdout_handler.setLevel(logging.DEBUG) + stdout_handler.setFormatter(formatter) + file_handler = logging.FileHandler('regression.log') + file_handler.setLevel(logging.INFO) + #file_handler.setLevel(logging.DEBUG) + file_handler.setFormatter(formatter) + logger.addHandler(file_handler) + logger.addHandler(stdout_handler) + parser = argparse.ArgumentParser( + formatter_class=argparse.RawDescriptionHelpFormatter, + description=textwrap.dedent('''Unit Test Simulation Regression Test Runner'''), + epilog=textwrap.dedent('''\ + Example: below performs a Unit Test regression, run locally, with 8 processes, using package of "all" tests, using VCS. + python regress_run.py -l -n 8 -k all -s vcs + Same as above using long-form args: + python regress_run.py --local --n_procs 8 --pack all --sim vcs + Same as above, but run on Intel Farm (no --local): + python regress_run.py --pack all --sim vcs + Running script using defaults: run on Farm, using package of "all" tests, using VCS: + python regress_run.py''')) + parser.add_argument('-l', '--local', dest='run_regression_locally', action='store_true', help='Run regression locally, or run it on Farm. (Default: %(default)s)') + parser.add_argument('-n', '--n_procs', dest='max_parallel_running_process_count', type=check_positive_process_count, metavar='N', nargs='?', default=multiprocessing.cpu_count()-1, help='Maximum number of processes/tests to run in parallel when run locally. This has no effect on Farm run. (Default #CPUs-1: %(default)s)') + parser.add_argument('-k', '--pack', dest='package', type=str, nargs='?', default='all', choices=['all','dfh','fme','he_hssi','he_lb','he_mem','list'], help='Test package to run during regression. The "list" option will look for a text file named "list.txt" in the "unit_test" directory for a text list of tests to run (top directory names). (Default: %(default)s)') + parser.add_argument('-s', '--sim', dest='simulator', type=str, nargs='?', default='vcs', choices=['vcs','msim','vcsmx'], help='Simulator used for regression test. (Default: %(default)s)') + parser.add_argument('-g', '--gen_sim_files', dest='gen_sim_files', action='store_true', help='Generate IP simulation files. This should only be done once per repo update. (Default: %(default)s)') + parser.add_argument('-e', '--email_list', dest='email_list', action='store_true', help='To send mail to multiple receipients') + args = parser.parse_args() + logger.info(f">>> Running Unit Test Regression Run Python Script: {os.path.basename(__file__)}") + logger.info(f" Begin running at date/time..............: {regression_run_start}") + logger.info(f" Simulator used for run..................: {args.simulator}") + rootdir = get_rootdir() + logger.info(f" Repo Root Directory is..: {rootdir}") + if args.email_list: + email_list = get_email_list() + git_commit = get_last_commit() + logger.info(f" Git Repo Last Commit is.....: {git_commit}") + script_dir = os.path.dirname(os.path.realpath(__file__)) + logger.info(f" Script Location is..........: {script_dir}") + top_test_dir = rootdir + "/sim/unit_test" + current_dir = os.getcwd() + logger.info(f" Current Working Directory is: {current_dir}") + if(os.path.exists(top_test_dir)): + logger.info(f" Test Directory..............: {top_test_dir}") + else: + logger.error(f"ERROR: Test Directory NOT found...: {top_test_dir}") + logger.error(f" Script {os.path.basename(__file__)} execution has been halted.") + sys.exit(1) + if args.run_regression_locally: + logger.info(f" File System for Local Run...: {check_nfs().upper()}") + else: + if (check_nfs() == 'nfs'): + logger.info(f" File System for Farm Run....: {check_nfs().upper()}") + else: + logger.error(f"ERROR: Farm Regression Runs must be run from an NFS file system. Current file system is: {check_nfs().upper()}") + sys.exit(1) + if args.gen_sim_files: + generate_sim_files() + list_of_tests = create_test_list() + logger.info(f" List of Tests to Run ({len(list_of_tests)})..: >>>>") + longest_test_name = 0 + for test in list_of_tests: + logger.info(f" {test}") + if (len(test)>longest_test_name): + longest_test_name = len(test) + total_processes_to_run = len(list_of_tests) + if (total_processes_to_run > 0): + if args.run_regression_locally: + logger.info(f" Beginning Test Regression with {total_processes_to_run} processes.") + logger.info(f" Parallel Running Process Count limited to {args.max_parallel_running_process_count} processes.") + queue = multiprocessing.Queue() + pool = multiprocessing.Pool(args.max_parallel_running_process_count) + test_items = [pool.apply_async(sim_process, (i, list_of_tests[i], top_test_dir, args.simulator)) for i in range(total_processes_to_run)] + logger.info(f"Unit Test Pool Launch Completed.") + for item in test_items: + item.get() + while not queue.empty(): + time_tuple = queue.get() + test = time_tuple[0] + time = time_tuple[1] + #logger.debug(f"Time tuple : {time_tuple}") + #logger.debug(f"Test.......: {test}") + #logger.debug(f"Time.......: {time}") + test_times_dict[test] = time + logger.info(f"Unit Test Processing Completed. Total of {total_processes_to_run} processes run.") + else: + logger.info(f" Beginning Farm Test Regression with {total_processes_to_run} processes.") + queue = multiprocessing.Queue() + pool = multiprocessing.Pool(total_processes_to_run) + test_items = [pool.apply_async(sim_farm_process, (i, list_of_tests[i], top_test_dir, args.simulator)) for i in range(total_processes_to_run)] + logger.info(f"Unit Test Farm Test Pool Launch Completed.") + for item in test_items: + item.get() + while not queue.empty(): + info_tuple = queue.get() + test = info_tuple[0] + info = info_tuple[1:] + #logger.debug(f"Info tuple : {info_tuple}") + #logger.debug(f"Test.......: {test}") + #logger.debug(f"Info.......: {info}") + test_info_dict[test] = info + logger.info(f"Unit Test Farm Test Processing Completed. Total of {total_processes_to_run} processes run.") + scan_test_results(list_of_tests) + length_count_field = len(str(test_results[0].get_test_count())) + logger.info(f" Number of Unit test results captured: {test_results[-1].get_test_count():>{length_count_field}}") + logger.info(f" Number of Unit test results passing.: {test_results[-1].get_test_count_passed():>{length_count_field}}") + logger.info(f" Number of Unit test results failing.: {test_results[-1].get_test_count_failed():>{length_count_field}}") + for test_object in test_results: + test_object.print() + print_results() + regression_run_end = datetime.datetime.now() + regression_run_elapsed = regression_run_end - regression_run_start + logger.info(f" Number of Unit test results captured: {test_results[-1].get_test_count():>{length_count_field}}") + logger.info(f" Number of Unit test results passing.: {test_results[-1].get_test_count_passed():>{length_count_field}}") + logger.info(f" Number of Unit test results failing.: {test_results[-1].get_test_count_failed():>{length_count_field}}") + logger.info(f" End Unit regression running at date/time................: {regression_run_end}") + logger.info(f" Elapsed time for Unit regression run....................: {regression_run_elapsed}") + send_email_report() + else: + logger.info(f"Number of Unit Tests is less than or equal to zero -- there is nothing to do.") + diff --git a/sim/unit_test/scripts/sim_setup_common.sh b/sim/unit_test/scripts/sim_setup_common.sh new file mode 100755 index 0000000..af0bccf --- /dev/null +++ b/sim/unit_test/scripts/sim_setup_common.sh @@ -0,0 +1,87 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +SCRIPT_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +VCSMX=0 +MSIM=0 +TEST_DIR="" + +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh run_sim.sh SKIP_IP_CMP=1 +# ---------------------------------------- +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +if [ $VCSMX -eq 1 ]; then + SIM_DIR=${TEST_DIR}/sim_vcsmx +elif [ $MSIM -eq 1 ]; then + SIM_DIR=${TEST_DIR}/sim_msim +else + SIM_DIR=${TEST_DIR}/sim_vcs +fi +echo "entering sim_setup_common.sh: SIM_DIR: $SIM_DIR" + +IP_LIB_DIR=$TEST_DIR +IP_SIM_SCRIPT_DIR="$OFS_ROOTDIR/sim/scripts/qip_sim_script" + +# ---------------------------------------- +# Clean up +# ---------------------------------------- +rm -rf $SIM_DIR + +# ---------------------------------------- +# Simulation setup +# ---------------------------------------- +mkdir $SIM_DIR + +if [ $VCSMX -eq 1 ]; then + # IP library compilation + if [ $SKIP_IP_CMP -eq 0 ]; then + if [ -d "$IP_LIB_DIR/ip_libraries" ]; then + rm -rf "$IP_LIB_DIR/ip_libraries" + fi + + mkdir -p $IP_LIB_DIR/ip_libraries + cp -f $IP_SIM_SCRIPT_DIR/synopsys/vcsmx/synopsys_sim.setup $IP_LIB_DIR/ip_libraries + cd $IP_LIB_DIR/ip_libraries && $IP_SIM_SCRIPT_DIR/synopsys/vcsmx/vcsmx_setup.sh SKIP_SIM=1 QSYS_SIMDIR=$IP_SIM_SCRIPT_DIR QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final" + fi + + # Simulation setup + echo WORK \> DEFAULT > $SIM_DIR/synopsys_sim.setup + echo DEFAULT \: worklib >> $SIM_DIR/synopsys_sim.setup + mkdir $SIM_DIR/worklib + rsync -avz --checksum --ignore-times ${IP_LIB_DIR}/ip_libraries/* $SIM_DIR +fi + +if [ $MSIM -eq 1 ]; then + cp ${IP_SIM_SCRIPT_DIR}/../msim_filelist.sh $SIM_DIR +else + cp ${IP_SIM_SCRIPT_DIR}/../vcs_filelist.sh $SIM_DIR +fi +cp ${IP_SIM_SCRIPT_DIR}/../rtl_comb.f $SIM_DIR + + +if [ $MSIM -eq 1 ]; then + sed -i 's/PLAT_RTL_FILELIST=.*/PLAT_RTL_FILELIST="-f .\/rtl_comb.f"/' ${SIM_DIR}/msim_filelist.sh +else + sed -i 's/PLAT_RTL_FILELIST=.*/PLAT_RTL_FILELIST="-f .\/rtl_comb.f"/' ${SIM_DIR}/vcs_filelist.sh +fi +sed -i 's,'.*\/pcie_top.sv',$OFS_ROOTDIR/sim/bfm/pcie_top.sv,' ${SIM_DIR}/rtl_comb.f + +echo "sim_setup_common: done!" diff --git a/sim/unit_test/scripts/vcs_filelist.sh b/sim/unit_test/scripts/vcs_filelist.sh new file mode 100755 index 0000000..4b87123 --- /dev/null +++ b/sim/unit_test/scripts/vcs_filelist.sh @@ -0,0 +1,23 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +SCRIPT_NAME=$BASH_SOURCE +SCRIPT_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +BFM_DIR="$(readlink -f ${SCRIPT_DIR})/../../bfm" +WORK_DIR="$(readlink -f ${SCRIPT_DIR})/../../../.." +BFM_SRC="+incdir+$BFM_DIR \ ++incdir+$WORK_DIR/sim/d5005/ip_libraries/pim_template/hw/lib/build/platform/ofs_plat_if/rtl \ ++incdir+$WORK_DIR/src/he_lb \ ++incdir+$WORK_DIR/src/fims/d5005/includes \ ++incdir+$WORK_DIR/src/shells/d5005/includes \ ++incdir+$SCRIPT_DIR/testbench \ +$BFM_DIR/test_utils.sv \ +$BFM_DIR/test_pcie_utils.sv \ +$BFM_DIR/ready_gen.sv \ +$BFM_DIR/packet_sender.sv \ +$BFM_DIR/packet_receiver.sv \ +$BFM_DIR/shmem.sv \ +$BFM_DIR/pcie_flr.sv \ +$BFM_DIR/tester.sv \ +$BFM_DIR/top_tb.sv" diff --git a/sim/unit_test/spi_basic_test/msim_setup.sh b/sim/unit_test/spi_basic_test/msim_setup.sh new file mode 100755 index 0000000..aae7eeb --- /dev/null +++ b/sim/unit_test/spi_basic_test/msim_setup.sh @@ -0,0 +1,114 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="-finish exit" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR="$TEST_SRC_DIR/../../.." +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="${TEST_DIR}/sim_msim" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for msim # +################################### +. ${SIM_DIR}/msim_filelist.sh + +################################## +### BFM related verilog source ### +################################## +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlib work +vlog -mfcu -timescale=1ns/1fs +libext+.v+.sv -lint -sv \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+HTILE \ + +define+R1_UNIT_TEST_ENV \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+MSIM_IOFS_D5005 \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + +define+R1_UNIT_TEST_ENV \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $MSIM_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -work work -l msim_vlog.log -suppress 8386,7033,7061,2388,12003,2892 +#suppress 8386 : Replication operator in Conactenation Operator +#suppress 2892 : Net type of 'clk' was not explicitly declared +#suppress 7061 : Variable 'clear_tdo_bit_select' driven in an always_ff block, may not be driven by any other process +#suppress 7033 : Variable 'parser_result' driven in a combinational block, may not be driven by any other process + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + vopt $TOP_LEVEL_NAME -o opt -suppress 2732,12003,7033,3837 -l msim_vopt.log + vsim -c opt -nosva -suppress 2732,12003,7033,3837 -do "add log -r /*; run -all ; quit -f" +fi + + diff --git a/sim/unit_test/spi_basic_test/readme.txt b/sim/unit_test/spi_basic_test/readme.txt new file mode 100644 index 0000000..8578345 --- /dev/null +++ b/sim/unit_test/spi_basic_test/readme.txt @@ -0,0 +1,76 @@ +***Test Description*** + - Tests basic SPI CSR access. + - Tests the SPI Bridges ability to loop-back SPI_MOSI to SPI_MISO. + - Makes sure un-used registers in the SP return non "X" values + +It covers the following test scenarios: + * Finding the SPI DFH by doing a DFH Walk (BAR0) + * Testing basic spi cfg accesses on SPI_WRITEDATA and SPI_READDATA registers + * Checking the SPI Bridge Loopback scenario by connection SPI_MOSI to SPI_MISO + +Description of test modules: + * test_csr_defs.sv - Defines CSR addresses. + * tester_tests.sv - Defines all the test cases for current test. + * script/Makefile_VCS.mk - Script to run the test in VCS only + * script/Makefile.mk - Script to run the test in VCS & Questasim. MSIM_D5005=1 option to be given for Questasim else will be for VCS. + +***Running the test*** +To run the test in VCS: + 1) Make sure the shell environment is set up to run VCS/VCSMX. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Synopsys VCS simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_vcs + dve -full64 -vpd vcdplus.vpd & + +To run the test in QuestaSim: + 1) Make sure the shell environment is set up to run Questasim. + + 2) IP Simulation Model Generation + The script required to compile the Quartus IPs is located here: $OFS_ROOTDIR/ofs-common/scripts/common/sim/gen_sim_files.sh + To compile all IPs: + cd $OFS_ROOTDIR/ofs-common/scripts/common/sim + sh gen_sim_files.sh d5005 + The IPs are generated here..................: $OFS_ROOTDIR/sim/scripts/qip_gen + The IP simulation filelist is generated here: $OFS_ROOTDIR/sim/scripts/ip_flist.f + Once the IPs are generated, they can be used for any unit test. + + 3) RTL & Test Bench Compile Setup + The RTL file list for unit_test is located here: $OFS_ROOTDIR/sim/scripts/rtl_comb.f + The directory: $OFS_ROOTDIR/sim/scripts contains most of the important files outside of the test directories. + Again, the directory: $OFS_ROOTDIR/sim/scripts/qip_gen contains the directories of the compiled IP. + The common Bus-Functional Models used by the Unit Tests are contained in the directories: + - $OFS_ROOTDIR/sim/bfm + - $OFS_ROOTDIR/sim/rp_bfm + + 4) Simulation + Simulations are run in the $OFS_ROOTDIR/sim/unit_test//scripts directory. + To run a Mentor Graphics QuestaSim simulation: + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts + sh run_sim.sh MSIM=1 + + 5) View Waveform + cd $OFS_ROOTDIR/sim/unit_test//script/sim/unit_test//scripts/sim_msim + vsim -view vsim.wlf & diff --git a/sim/unit_test/spi_basic_test/scripts/run_sim.sh b/sim/unit_test/spi_basic_test/scripts/run_sim.sh new file mode 100755 index 0000000..271afc5 --- /dev/null +++ b/sim/unit_test/spi_basic_test/scripts/run_sim.sh @@ -0,0 +1,48 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)/.." + + +VCSMX=0 +MSIM=0 +SKIP_IP_CMP=0 +TEST_DIR=$(pwd) + +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh run_sim.sh SKIP_IP_CMP=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +# Source common sim setup script + +. ${TEST_DIR}/../../scripts/sim_setup_common.sh TEST_DIR="$TEST_DIR" VCSMX=$VCSMX MSIM=$MSIM + +# Run simulation +if [ $VCSMX -eq 1 ]; then + echo "Running VCSMX simulation in $TEST_DIR/sim_vcsmx" + cd ${TEST_DIR}/sim_vcsmx && sh ${TEST_SRC_DIR}/vcsmx_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +elif [ $MSIM -eq 1 ]; then + echo "Running Questasim simulation in $TEST_DIR/sim_msim" + cd ${TEST_DIR}/sim_msim && sh ${TEST_SRC_DIR}/msim_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="-l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="" +else + echo "Running VCS simulation in $TEST_DIR/sim_vcs" + cd ${TEST_DIR}/sim_vcs && sh ${TEST_SRC_DIR}/vcs_setup.sh OFS_ROOTDIR="$OFS_ROOTDIR" TEST_DIR="$TEST_DIR" USER_DEFINED_SIM_OPTIONS="+vcs\ -l\ ./transcript" USER_DEFINED_ELAB_OPTIONS="-debug_acc+pp+dmptf\ -debug_region+cell+encrypt" +fi + + diff --git a/sim/unit_test/spi_basic_test/scripts/test_list.f b/sim/unit_test/spi_basic_test/scripts/test_list.f new file mode 100644 index 0000000..3740dcc --- /dev/null +++ b/sim/unit_test/spi_basic_test/scripts/test_list.f @@ -0,0 +1 @@ +$WORKDIR/sim/unit_test/spi_basic_test/testbench/test_csr_defs.sv diff --git a/sim/unit_test/spi_basic_test/testbench/test_csr_defs.sv b/sim/unit_test/spi_basic_test/testbench/test_csr_defs.sv new file mode 100644 index 0000000..1a95d07 --- /dev/null +++ b/sim/unit_test/spi_basic_test/testbench/test_csr_defs.sv @@ -0,0 +1,107 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// CSR addresses are defined for the testcase. +// +//----------------------------------------------------------------------------- +`ifndef __TEST_CSR_DEFS__ +`define __TEST_CSR_DEFS__ + +package test_csr_defs; + localparam FME_DFH = 32'h0; + localparam FME_SCRATCHPAD0 = FME_DFH + 32'h28; + + localparam PMCI_DFH = 32'h10000; + localparam PMCI_SCRATCHPAD = PMCI_DFH + 32'h28; + + localparam PCIE_DFH = 32'h20000; + localparam PCIE_SCRATCHPAD = PCIE_DFH + 32'h8; + + localparam ST2MM_DFH = 32'h80000; + localparam ST2MM_SCRATCHPAD = ST2MM_DFH + 32'h8; + + localparam PGSK_DFH = 32'h90000; + localparam PGSK_SCRATCHPAD = PGSK_DFH + 32'hb8; + + localparam HSSI_DFH = 32'h30000; + localparam HSSI_SCRATCHPAD = HSSI_DFH + 32'h38; + + localparam HE_LB_DFH = 32'h00000; + localparam HE_LB_SCRATCHPAD = HE_LB_DFH + 32'h100; + + localparam HE_HSSI_SCRATCHPAD = HE_LB_DFH + 32'h48; + + localparam PORT_CONTROL = 32'h91038; + + localparam EMIF_DFH = 32'h41000; + localparam PCIE_DFH_VALUE = 64'h3000000010000020; + localparam EMIF_DFH_VALUE = 64'h3000000010000009; + localparam HSSI_DFH_VALUE = 64'h300000001000100f; + localparam USER_CLK_DFH_VALUE = 64'h3000010000000014; + localparam SPI_DFH = 32'h43000; + localparam SPI_DFH_VALUE = 64'h300001000000000e; + //localparam SPI_WRITEDATA = 32'h43020; + localparam HSSI_RCFG_DATA = 32'h42030; + localparam VFME_AFU_ID_L = 32'h8; + localparam VFME_AFU_ID_L_VALUE = 64'hBEE40B2B259849A9; + localparam VFME_AFU_ID_H = 32'h10; + localparam VFME_AFU_ID_H_VALUE = 64'hA8E434048329FE10; + localparam VFME_MSIX_VADDR0 = 32'h3000; + localparam USER_CLK_DFH = 32'h20000; + localparam USER_CLK_CMD_0 = 32'h20008; + + localparam USER_IRQ0_ADDR = 64'h20000; + localparam USER_IRQ1_ADDR = 64'h21000; + localparam USER_IRQ2_ADDR = 64'h22000; + localparam USER_IRQ3_ADDR = 64'h23000; + localparam USER_IRQ4_ADDR = 64'h24000; + localparam USER_IRQ5_ADDR = 64'h25000; + localparam USER_IRQ6_ADDR = 64'h26000; + + localparam USER_IRQ0_DATA = 32'hbeef_0000; + localparam USER_IRQ1_DATA = 32'hbeef_0001; + localparam USER_IRQ2_DATA = 32'hbeef_0002; + localparam USER_IRQ3_DATA = 32'hbeef_0003; + localparam USER_IRQ4_DATA = 32'hbeef_0004; + localparam USER_IRQ5_DATA = 32'hbeef_0005; + localparam USER_IRQ6_DATA = 32'hbeef_0006; + + //Added for PCIE_CSR_TEST + localparam PCIE0_ERROR = 32'h4020; + localparam PCIE_STAT = 32'h40010; + localparam PCIE_ERROR_MASK = 32'h40018; + localparam PCIE_ERROR = 32'h40020; + localparam PCIE_UNUSED_OFFSET = 32'h40ff8; + + //Added for SPI BASIC TEST + localparam SPI_CONTROL_ADDR = 6'h10; + localparam SPI_READDATA = 6'h18; + localparam SPI_WRITEDATA = 6'h20; + localparam SPI_BRIDGE_RXDATA = 3'h0; + localparam SPI_BRIDGE_TXDATA = 3'h1; + localparam SPI_BRIDGE_STATUS = 3'h2; + localparam SPI_BRIDGE_CONTROL = 3'h3; + localparam SPI_BRIDGE_RESERVED = 3'h4; + localparam SPI_BRIDGE_SLAVESELECT = 3'h5; + localparam SPI_BRIDGE_EOPVALUE = 3'h6; +/* + localparam PCIE_DFH = 32'h10000; + localparam PCIE_SCRATCHPAD = PCIE_DFH + 32'h8; + localparam PCIE_TESTPAD = PCIE_DFH + 32'h38; + + localparam HE_LB_SCRATCHPAD = 32'h100; + + localparam HSSI_DFH = 32'h60000; + localparam HSSI_RCFG_DATA = HSSI_DFH + 32'h30; + + //localparam USER_CLK_DFH = 32'h20000; + //localparam USER_CLK_CMD_0 = 32'h20008; + +*/ + +endpackage + +`endif diff --git a/sim/unit_test/spi_basic_test/testbench/tester_tests.sv b/sim/unit_test/spi_basic_test/testbench/tester_tests.sv new file mode 100755 index 0000000..eb45b4e --- /dev/null +++ b/sim/unit_test/spi_basic_test/testbench/tester_tests.sv @@ -0,0 +1,366 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// This file defines all the test cases for current test. +// +// main_test() is the main entry function which the tester calls +// to execute the unit tests. +// +//----------------------------------------------------------------------------- + +//------------------- +// Test utilities +//------------------- + +import test_csr_defs::*; +import ofs_fim_pcie_pkg::*; //Added by Ashish +integer err_count = 0; //Added by Ashish +logic [7:0] exp_err = 0; +reg [31:0] spi_offset = 0; + +task incr_test_id; + begin + test_id = test_id + 1; + end +endtask + +task post_test_util; + input logic result; + begin + repeat (10) + @(posedge avl_clk); + + @(posedge avl_clk); + reset_test = 1'b1; + repeat (5) + @(posedge avl_clk); + reset_test = 1'b0; + + f_reset_tag(); + + if (result) begin + $display("\nTest status: OK"); + test_summary[test_id].result = 1'b1; + end else begin + $display("\nTest status: FAILED"); + test_summary[test_id].result = 1'b0; + end + incr_test_id(); + end +endtask + +task print_test_header; + input [1024*8-1:0] test_name; + begin + $display("\n********************************************"); + $display(" Running TEST(%0d) : %0s", test_id, test_name); + $display("********************************************"); + test_summary[test_id].name = test_name; + end +endtask + +task verify_err_count; + output logic result; + input logic [7:0] exp_err; + begin + // Wait 30 clock cycles for checker error to be logged + repeat (30) + @(posedge fim_clk); + + if (err_count != exp_err) + begin + result = 1'b0; + $display("Failed - expected errors: %0d, actual errors: %0d", exp_err, err_count); + end else begin + result = 1'b1; + $display("MMIO error count matches: %0d", err_count); + end + if (~result) + test_utils::incr_err_count(); + end +endtask + +task verify_mmio_err_count; + output logic result; + input logic [7:0] exp_err; + begin + // Wait 30 clock cycles for checker error to be logged + repeat (30) + @(posedge fim_clk); + + if (mmio_err_count != exp_err) + begin + result = 1'b0; + $display("Failed - expected errors: %0d, actual errors: %0d", exp_err, mmio_err_count); + end else begin + result = 1'b1; + $display("MMIO error count matches: %0d", mmio_err_count); + end + if (~result) + test_utils::incr_err_count(); + end +endtask + +//------------------- +// Test main entry +//------------------- +task main_test; + output logic test_result; + + logic valid_csr_region; + logic [31:0] addr; + static logic [2:0] bar = 0; + static logic vf_active = 0; + static logic [PF_WIDTH-1:0] pfn = 0; + static logic [VF_WIDTH-1:0] vfn = 0; + logic error; + logic [63:0] scratch; + static logic eol = 0; + + reg [63:0] rd_data64; + reg [63:0] wr_data64; + reg [31:0] rd_data32; + reg [31:0] wr_data32; + reg rrdy; + reg trdy; + reg [31:0] timer_count; + reg done; + reg [31:0] dfh_list_count; + reg [31:0] addr_sfp; + + begin : main + // ######################################### + // Look for the SPI DFH by doing a DFH walk. + // ######################################### + print_test_header("SPI_DFH_identify"); + //SPI DFH = 0x43000 + //HSSI DFH = 0x42000 + //EMIF DFH = 0x41000 + //PCIE DFH = 0x40000 + + //Decode of DFH, 64'h3_00_0_01_000000_0_00E: + //4’h3 [63:60]: Feature Type + //8’h0 [59:52]: Reserved + //4’h0 [51:48]: If AFU - AFU Minor Revision Number (else, reserved) + //7’h00 [47:41]: Reserved + //1’h1 [40 ]: EOL (End of DFH list) + //24’h000000 [39:16]: Next DFH Byte Offset + //4’h0 [15:12]: If AfU, AFU Major version number (else feature #) + //12’h00E [11:0 ]: Feature ID + + $display("T:%8d INFO: TEST_PROGRAM Finding the SPI DFH by doing a DFH Walk (BAR0)", $time); + addr = 32'h0; + done = 0; + dfh_list_count = 0; + + while (!(done)) begin + READ64(ADDR64, addr, bar, vf_active, pfn, vfn, rd_data64, error); + if ((rd_data64[11:0] === 12'h00E) & (rd_data64[63:60] === 4'h3)) begin + spi_offset = addr; + end + if (rd_data64[40]) begin + done = 1; + $display("T:%8d INFO: TEST_PROGRAM 0x%08X -> EOL (%016X).", $time, addr, rd_data64); + $display("T:%8d INFO: TEST_PROGRAM Found End Of List (EOL) at :0x%X.", $time, addr); + end else if (rd_data64[39:16] === 24'h0) begin + done = 1; + $display("T:%8d ERROR: TEST_PROGRAM 0x%08X -> Ptr 0 EOL (%016X).", $time, addr, rd_data64); + $display("T:%8d ERROR: TEST_PROGRAM Found next pointer zero at :0x%X.", $time, addr); + test_utils::incr_err_count(); + end else begin + addr_sfp = addr; + addr = addr + rd_data64[39:16]; + $display("T:%8d INFO: TEST_PROGRAM 0x%08X -> 0x%08X (%016X)", $time, addr_sfp, addr, rd_data64); + dfh_list_count = dfh_list_count + 1; + if (dfh_list_count > 1000) begin + $display("T:%8d ERROR: TEST_PROGRAM Did not find \"EOL\" after 1000 walks", $time,); + test_utils::incr_err_count(); + done = 1; + end + end // else: !if(rd_data64[39:16] === 24'h0) + end // while (!(done)) + + if (spi_offset) begin + $display("T:%8d INFO: TEST_PROGRAM The SPI DFH was found at offset:0x%X", $time, spi_offset); + end else begin + $display("T:%8d ERROR: TEST_PROGRAM SPI DFH was not found", $time); + test_utils::incr_err_count(); + end + + verify_err_count(test_result, exp_err); + post_test_util(test_result); + exp_err = test_utils::get_err_count(); + + // ####################################### + // Test basic spi cfg accesses. + // ####################################### + print_test_header("spi_cfg_accesses"); + addr = spi_offset + SPI_WRITEDATA; + READ64(ADDR64, addr, bar, vf_active, pfn, vfn, rd_data64, error); + $display("T:%8d INFO: TEST_PROGRAM %m ADDR:%X, RD_DATA64:%X", $time, addr, rd_data64); + if (error) begin + $display("T:%8d ERROR: TEST_PROGRAM %m Completion is returned with unsuccessful status.", $time); + test_utils::incr_err_count(); + end + + $display("T:%8d INFO: TEST_PROGRAM %m Begin Loop", $time); + repeat (10) begin + wr_data64 = {$urandom, $urandom}; + WRITE64(ADDR64, addr, bar, vf_active, pfn, vfn, wr_data64); + $display("T:%8d INFO: TEST_PROGRAM %m Writing: ADDR:%X, WR_DATA64:%X", $time, addr, wr_data64); + + READ64(ADDR64, addr, bar, vf_active, pfn, vfn, rd_data64, error); + $display("T:%8d INFO: TEST_PROGRAM %m ADDR:%X, RD_DATA64:%X", $time, addr, rd_data64); + if (error) begin + $display("T:%8d ERROR: TEST_PROGRAM %m Completion is returned with unsuccessful status.", $time); + test_utils::incr_err_count(); + end + if ({32'h0, wr_data64[31:0]} !== rd_data64) begin + $display("T:%8d ERROR: TEST_PROGRAM %m addr:%X, EXPECTED:%X RECEIVED:%X", $time, addr, {32'h0, wr_data64[31:0]}, rd_data64); + test_utils::incr_err_count(); + end + end + verify_err_count(test_result, exp_err); + post_test_util(test_result); + exp_err = test_utils::get_err_count(); + + // ================================================== + print_test_header("spi_cfg_accesses_r_w_32_a2_low"); + addr = spi_offset + SPI_CONTROL_ADDR; + repeat (10) begin + wr_data64 = {$urandom, $urandom}; + wr_data64 = {wr_data64[63:10], 2'h0, wr_data64[7:0]}; // lets not do any actual SPI bridge registyer accesses. + WRITE32(ADDR64, addr, bar, vf_active, pfn, vfn, wr_data64); + $display("T:%8d INFO: TEST_PROGRAM %m Writing: ADDR:%X, WR_DATA64:%X", $time, addr, wr_data64); + + WRITE32(ADDR64, addr+4, bar, vf_active, pfn, vfn, {$urandom, $urandom}); + $display("T:%8d INFO: TEST_PROGRAM %m Writing to upper32 bits to make sure lower32 bits are not affected.", $time); + + READ32(ADDR64, addr, bar, vf_active, pfn, vfn, rd_data64, error); + $display("T:%8d INFO: TEST_PROGRAM %m ADDR:%X, RD_DATA64:%X", $time, addr, rd_data64); + if (error) begin + $display("T:%8d ERROR: TEST_PROGRAM %m Completion is returned with unsuccessful status.", $time); + test_utils::incr_err_count(); + end + if ({61'h0, wr_data64[2:0]} !== rd_data64) begin + $display("T:%8d ERROR: TEST_PROGRAM %m addr:%X, EXPECTED:%X RECEIVED:%X", $time, addr, {54'h0, wr_data64[9:8], 5'h0, wr_data64[2:0]}, rd_data64); + test_utils::incr_err_count(); + end + end + verify_err_count(test_result, exp_err); + post_test_util(test_result); + exp_err = test_utils::get_err_count(); + + // ================================================== + print_test_header("spi_cfg_accesses_r_w_32_a2_high"); + addr = spi_offset + SPI_READDATA + 32'h4; + repeat (10) begin + wr_data64 = {$urandom, $urandom}; + WRITE32(ADDR64, addr, bar, vf_active, pfn, vfn, wr_data64); + $display("T:%8d INFO: TEST_PROGRAM %m Writing: ADDR:%X, WR_DATA64:%X", $time, addr, wr_data64); + + WRITE32(ADDR64, addr-4, bar, vf_active, pfn, vfn, {$urandom, $urandom}); + $display("T:%8d INFO: TEST_PROGRAM %m Writing to lower32 bits to make sure upper32 bits are not affected.", $time); + + READ32(ADDR64, addr, bar, vf_active, pfn, vfn, rd_data64, error); + $display("T:%8d INFO: TEST_PROGRAM %m ADDR:%X, RD_DATA64:%X", $time, addr, rd_data64); + if (error) begin + $display("T:%8d ERROR: TEST_PROGRAM %m Completion is returned with unsuccessful status.", $time); + test_utils::incr_err_count(); + end + if ({63'h0, wr_data64[0]} !== rd_data64) begin + $display("T:%8d ERROR: TEST_PROGRAM %m addr:%X, EXPECTED:%X RECEIVED:%X", $time, addr, {63'h0, wr_data64[0]}, rd_data64); + test_utils::incr_err_count(); + end + end + verify_err_count(test_result, exp_err); + post_test_util(test_result); + exp_err = test_utils::get_err_count(); + + // ####################################### + // Test a SPI register exchange... + // ####################################### + print_test_header("spi_bridge_loopback"); + wr_data32 = 32'h5555AAAA; + repeat (20) begin + $display("T:%8d INFO: TEST_PROGRAM %m Testing wr_data32 of:%X", $time, wr_data32); + write_spi(SPI_BRIDGE_TXDATA, wr_data32); + + // spin on RRDY set... + timer_count = 0; + rrdy = 0; + while ((rrdy === 0) & (timer_count < 50)) begin + read_spi(SPI_BRIDGE_STATUS, rd_data32); + rrdy = rd_data32[7]; + timer_count = timer_count + 1; + $display("T:%8d INFO: TEST_PROGRAM %m rrdy:%d, rd_data32:%X", $time, rrdy, rd_data32); + end + if (timer_count >= 50) begin + $display("T:%8d ERROR: TEST_PROGRAM %m Timeout waiting for rrdy", $time); + test_utils::incr_err_count(); + end + + read_spi(SPI_BRIDGE_RXDATA, rd_data32); + $display("T:%8d INFO: TEST_PROGRAM %m rd_data32 from spi register exchange: ADDR:%X, RD_DATA32:%X", $time, 3'h0, rd_data32); + if (wr_data32 !== rd_data32) begin + $display("T:%8d ERROR: TEST_PROGRAM %m EXPECTED:%X RECEIVED:%X", $time, wr_data32, rd_data32); + test_utils::incr_err_count(); + end + wr_data32 = $urandom; + end // repeat (20) + verify_err_count(test_result, exp_err); + post_test_util(test_result); + exp_err = test_utils::get_err_count(); + + // ####################################### + // Test spi unused cfg_space. + // ####################################### + print_test_header("spi_unused_cfg_space"); + addr = spi_offset + SPI_DFH; + while (addr < spi_offset + 32'h100) begin + READ64(ADDR64, addr, bar, vf_active, pfn, vfn, rd_data64, error); + $display("T:%8d INFO: TEST_PROGRAM %m ADDR:%X, RD_DATA64:%X error:%d", $time, addr, rd_data64, error); + addr = addr + 8; + if (^rd_data64 === 1'bx) begin + $display("T:%8d ERROR: TEST_PROGRAM %m X's read back from SPI cfg space", $time); + test_utils::incr_err_count(); + end + end + + verify_err_count(test_result, exp_err); + post_test_util(test_result); + exp_err = test_utils::get_err_count(); + end +endtask + + +task write_spi; + input [2:0] addr; + input [31:0] write_data32; + + begin + WRITE64(ADDR64, spi_offset + SPI_WRITEDATA, 0, 0, 0, 0, write_data32); + WRITE64(ADDR64, spi_offset + SPI_CONTROL_ADDR, 0, 0, 0, 0, {56'h1, 5'h0, addr}); + //$display("T:%8d INFO: TEST_PROGRAM %m Wrote SPI ADDR:%x, WRITE_DATA32:%X", $time, addr, write_data32); + end +endtask // write_spi + +task read_spi; + input [2:0] addr; + output [31:0] rd_data32; + + reg error; + + begin + WRITE64(ADDR64, spi_offset + SPI_CONTROL_ADDR, 0, 0, 0, 0, {56'h2, 5'h0, addr}); + READ64 (ADDR64, spi_offset + SPI_READDATA, 0, 0, 0, 0, rd_data32, error); + if (error) begin + $display("T:%8d ERROR: TEST_PROGRAM %m read_spi: Completion is returned with unsuccessful status.", $time); + test_utils::incr_err_count(); + end + //$display("T:%8d INFO: TEST_PROGRAM %m Read SPI ADDR:%x, RD_DATA32:%X", $time, addr, rd_data32); + end +endtask // write_spi diff --git a/sim/unit_test/spi_basic_test/vcs_setup.sh b/sim/unit_test/spi_basic_test/vcs_setup.sh new file mode 100644 index 0000000..04c4168 --- /dev/null +++ b/sim/unit_test/spi_basic_test/vcs_setup.sh @@ -0,0 +1,110 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcs" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +# source ${SIM_ROOTDIR}/d5005/unit_test/scripts/vcs_filelist.sh +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vcs -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + +define+R1_UNIT_TEST_ENV \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $VCS_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC -top $TOP_LEVEL_NAME +error+20 -l vcs.log + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/sim/unit_test/spi_basic_test/vcsmx_setup.sh b/sim/unit_test/spi_basic_test/vcsmx_setup.sh new file mode 100755 index 0000000..56bde7f --- /dev/null +++ b/sim/unit_test/spi_basic_test/vcsmx_setup.sh @@ -0,0 +1,115 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if test -n "$BASH" ; then SCRIPT_NAME=$BASH_SOURCE +elif test -n "$TMOUT"; then SCRIPT_NAME=${.sh.file} +elif test -n "$ZSH_NAME" ; then SCRIPT_NAME=${(%):-%x} +elif test ${0##*/} = dash; then x=$(lsof -p $$ -Fn0 | tail -1); SCRIPT_NAME=${x#n} +else SCRIPT_NAME=$0 +fi + +TEST_SRC_DIR="$(cd "$(dirname -- "$SCRIPT_NAME")" 2>/dev/null && pwd -P)" + +# initialize variables +OFS_ROOTDIR="" +QUARTUS_INSTALL_DIR=$QUARTUS_ROOTDIR +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="+vcs+finish+100" + +TOP_LEVEL_NAME="top_tb" +# ---------------------------------------- +# overwrite variables - DO NOT MODIFY! +# This block evaluates each command line argument, typically used for +# overwriting variables. An example usage: +# sh _setup.sh SKIP_SIM=1 +for expression in "$@"; do + eval $expression + if [ $? -ne 0 ]; then + echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2 + exit $? + fi +done + +SIM_ROOTDIR=$TEST_SRC_DIR/../.. +COMMON_TESTUTIL_DIR="$TEST_SRC_DIR/../scripts" +SIM_DIR="$TEST_DIR/sim_vcsmx" + +#----------------------------------------- +# Test will be picked up from base fim by default +# Point this to TEST_SRC_DIR if test path is local fim, and not base fim +TEST_BASE_DIR=$TEST_SRC_DIR + +# ---------------------------------------- +# initialize simulation properties - DO NOT MODIFY! +ELAB_OPTIONS="" +SIM_OPTIONS="" +if [[ `vcs -platform` != *"amd64"* ]]; then + : +else + : +fi + +################################### +# Source the BBS filelist for vcs # +################################### +. ${SIM_DIR}/vcs_filelist.sh + +################################## +### BFM related verilog source ### +################################## +# source ${SIM_ROOTDIR}/d5005/unit_test/scripts/vcs_filelist.sh +. $COMMON_TESTUTIL_DIR/vcs_filelist.sh + +TB_SRC="${TEST_BASE_DIR}/testbench/test_csr_defs.sv \ +$BFM_SRC" + +################################## +### AFU related verilog source ### +################################## +vlogan -lca -timescale=1ns/1fs -full64 -sverilog +vcs+lic+wait +systemverilogext+.v+.sv -ntb_opts dtm \ + -ignore unique_checks -error=noMPD +lint=TFIPC-L \ + +define+IGNORE_DF_SIM_EXIT \ + +define+SIM_MODE \ + +define+VCD_ON \ + +define+SIM_SERIAL \ + +define+SIMULATION_MODE \ + +define+MMIO_TIMEOUT_IN_CYCLES=1024 \ + +define+SVT_PCIE_ENABLE_GEN3+GEN3 \ + +define+define+__ALTERA_STD__METASTABLE_SIM \ + +define+BASE_AFU="dummy_afu" \ + +define+SVT_AXI_MAX_TDATA_WIDTH=784 \ + +define+SVT_AXI_MAX_TUSER_WIDTH=44 \ + +define+SIM_PCIE_CPL_TIMEOUT \ + +define+SIM_PCIE_CPL_TIMEOUT_CYCLES="26'd12500000" \ + +define+SIM_MODE \ + +define+VCS_S10 +define+RP_MAX_TAGS=64 \ + +define+INCLUDE_DDR4 \ + +define+INCLUDE_SPI_BRIDGE \ + +define+INCLUDE_USER_CLOCK \ + +define+INCLUDE_HSSI \ + +define+SIM_USE_PCIE_DUMMY_CSR \ + +define+R1_UNIT_TEST_ENV \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ + +incdir+./ \ + +incdir+$TEST_BASE_DIR/testbench \ + $INC_DIR \ + $RTL_FILELIST \ + $BASE_AFU_SRC \ + $TB_SRC +error+1 -l vlog.log + +vcs -full64 -ntb_opts -licqueue +vcs+lic+wait \ + +lint=TFIPC-L \ + -ignore initializer_driver_checks \ + $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -l vcs.log $TOP_LEVEL_NAME + +# ---------------------------------------- +# simulate +# parse transcript to remove redundant comment block (fb:435978) +if [ $SKIP_SIM -eq 0 ]; then + ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS -l transcript +fi + + diff --git a/src/README.md b/src/README.md new file mode 100644 index 0000000..7f30b56 --- /dev/null +++ b/src/README.md @@ -0,0 +1,36 @@ +# D5005 Source Code Directory + +This directory contains the source code specific to the D5005 FIM. The complete set of source code needed to build the D5005 FIM will include code from the following: + - The D5005 Source Code Directory (this directory) (***.***) + - The OFS-Common directory (***../ofs-common***) + - The D5005 IP Subsystem directory (***../ipss***) + - More information may be found in the D5005 top-level README file at: +* [D5005 Repo Main README](../README.md) Contains the top-level description for the directories in the D5005 repository. + +## Directories + +### Accelerated Functional Unit (AFU) Top (***./afu\_top***) + - Resources in this directory support the AFU top level which joins the user's accelerated function/application and the FPGA Interface Manager (FIM). + - Contains: + - Control and Status Register (CSR) definitions are contained in the top directory which has full-register definitions, bit-field definitions, and individual-bit definitions where applicable. + - AFU top-level RTL is contained in the top directory. + - MUX configuration package is contained in the subdirectory ***./afu\_top/mux***. +### Includes (***./includes***) + - Parameter definitions and packages used for the D5005 FIM configuration reside in this directory. +### Platform Designer (PD) Qsys (***./pd\_qsys***) + - D5005-specific subsystems created with Platform Designer exist in this directory. + - Contains: + - Bus Connection Fabric (***./pd\_qsys/fabric***) + - This is the connection fabric stitching together the various memory-mapped resources inside the FIM. + - SPI Bridge (***./pd\_qsys/spi\_bridge***) + - This is the SPI bridge used primarily to connect the Board Management Controller (BMC) with the resources inside the FPGA. + - Please consult the following README file for more detailed information: +* [Platform Designer/Qsys Contents Detailed README](pd_qsys/readme.txt) Contains detailed information on the directory structure as well as the instructions for configuring and generating the memory-mapped bus fabric: + - AFU Peripheral Fabric (APF) + - Board Peripheral Fabric (BPF) +### Top-level RTL and Resource (***./top***) + - This directory contains the top-level RTL which provides the overall structure of the FIM. + - Also included is the reset controller for the FIM. + - Please see the following README: +* [Top-level README](top/readme.txt) Contains detailed information on the directory structure and the contents of these directories. + diff --git a/src/afu_top/AFU_INTF_CSR.xls b/src/afu_top/AFU_INTF_CSR.xls new file mode 100755 index 0000000..fc3c9b0 Binary files /dev/null and b/src/afu_top/AFU_INTF_CSR.xls differ diff --git a/src/afu_top/afu_top.sv b/src/afu_top/afu_top.sv new file mode 100755 index 0000000..b4ad6bf --- /dev/null +++ b/src/afu_top/afu_top.sv @@ -0,0 +1,1038 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// AFU top wrapper +// + +`ifdef INCLUDE_HE_HSSI + import ofs_fim_eth_if_pkg::MAX_NUM_ETH_CHANNELS; +`endif + +import top_cfg_pkg::*; + +module afu_top( + input refclk, + input clk, + input clk_div2, + input clk_100, + + input rst_n, + input pwr_good_clk_n, + input rst_n_div2, + input rst_n_100, + input [NUM_PORT-1:0] func_rst_n, + output logic pr_parity_error, + + ofs_fim_axi_lite_if.master apf_bpf_slv_if, + ofs_fim_axi_lite_if.slave apf_bpf_mst_if, + + `ifdef INCLUDE_HE_HSSI + ofs_fim_hssi_ss_tx_axis_if.client hssi_ss_st_tx [MAX_NUM_ETH_CHANNELS-1:0], + ofs_fim_hssi_ss_rx_axis_if.client hssi_ss_st_rx [MAX_NUM_ETH_CHANNELS-1:0], + ofs_fim_hssi_fc_if.client hssi_fc [MAX_NUM_ETH_CHANNELS-1:0], + `ifdef INCLUDE_PTP + ofs_fim_hssi_ptp_tx_tod_if.client hssi_ptp_tx_tod [MAX_NUM_ETH_CHANNELS-1:0], + ofs_fim_hssi_ptp_rx_tod_if.client hssi_ptp_rx_tod [MAX_NUM_ETH_CHANNELS-1:0], + ofs_fim_hssi_ptp_tx_egrts_if.client hssi_ptp_tx_egrts [MAX_NUM_ETH_CHANNELS-1:0], + ofs_fim_hssi_ptp_rx_ingrts_if.client hssi_ptp_rx_ingrts [MAX_NUM_ETH_CHANNELS-1:0], + input logic i_ehip_clk_806, + input logic i_ehip_clk_403, + input logic i_ehip_pll_locked, + `endif + input logic [MAX_NUM_ETH_CHANNELS-1:0] i_hssi_clk_pll, + `endif + + pcie_ss_axis_if.sink pcie_ss_axis_rx, + pcie_ss_axis_if.source pcie_ss_axis_tx, + ofs_fim_emif_avmm_if.user afu_mem_if [NUM_MEM_CH] + +); + +//------------------------------------- +// Preserve clocks +//------------------------------------- + +// Make sure all clocks are consumed, in case AFUs don't use them, +// to avoid Quartus problems. + (* noprune *) logic clk_div2_q1, clk_div2_q2; + + always_ff @(posedge clk_div2) begin + clk_div2_q1 <= clk_div2_q2; + clk_div2_q2 <= !clk_div2_q1; + end + +//------------------------------------- +// Internal signals +//------------------------------------- + + pcie_ss_axis_if ho2mx_rx_remap (); // AXI stream interfaces + pcie_ss_axis_if mx2ho_tx_remap (); // + pcie_ss_axis_if ho2mx_rx_port (); // AXI stream interfaces + pcie_ss_axis_if mx2ho_tx_port (); // + pcie_ss_axis_if mx2fn_rx_a_port [NUM_PORT-1:0](); // A ports (PCIe SS RX traffic) + pcie_ss_axis_if mx2fn_rx_b_port [NUM_PORT-1:0](); // B PF/VF AFU side (local write completions) + pcie_ss_axis_if fn2mx_tx_a_port [NUM_PORT-1:0](); // A ports (first tree of AFU TX ports) + pcie_ss_axis_if fn2mx_tx_b_port [NUM_PORT-1:0](); // B ports (second tree of AFU TX ports) + + pcie_ss_axis_if mx2ho_tx_ab [2](); // Host side of both A and B PF/VF TX MUXes + pcie_ss_axis_if arb2ho_tx_port (); // A/B arbiter to local commit generator + pcie_ss_axis_if arb2mx_rx_b (); // A/B arbiter local write commits to AFU + + pcie_ss_axis_if afu_rx_a_port [PG_AFU_NUM_PORTS-1:0](); // A AFU PCIe RX ports + pcie_ss_axis_if afu_rx_b_port [PG_AFU_NUM_PORTS-1:0](); // A AFU PCIe RX ports + pcie_ss_axis_if afu_tx_a_port [PG_AFU_NUM_PORTS-1:0](); // A AFU PCIe TX ports + pcie_ss_axis_if afu_tx_b_port [PG_AFU_NUM_PORTS-1:0](); // B AFU PCIe TX ports + logic afu_rst_n [PG_AFU_NUM_PORTS-1:0]; // Port-specific soft reset + // AXI4-lite interfaces + + ofs_fim_axi_lite_if #(.AWADDR_WIDTH(20),.ARADDR_WIDTH(TOTAL_BAR_SIZE))apf_st2mm_mst_if ();// + ofs_fim_axi_lite_if #(.AWADDR_WIDTH(16),.ARADDR_WIDTH( 16)) apf_st2mm_slv_if ();// + ofs_fim_axi_lite_if #(.AWADDR_WIDTH(16),.ARADDR_WIDTH( 16)) apf_pgsk_slv_if ();// + ofs_fim_axi_lite_if #(.AWADDR_WIDTH(16),.ARADDR_WIDTH( 16)) apf_achk_slv_if ();// + ofs_fim_axi_lite_if #(.AWADDR_WIDTH(16),.ARADDR_WIDTH( 16)) apf_rsv_b_slv_if ();// + ofs_fim_axi_lite_if #(.AWADDR_WIDTH(16),.ARADDR_WIDTH( 16)) apf_rsv_c_slv_if ();// + ofs_fim_axi_lite_if #(.AWADDR_WIDTH(16),.ARADDR_WIDTH( 16)) apf_rsv_d_slv_if ();// + ofs_fim_axi_lite_if #(.AWADDR_WIDTH(16),.ARADDR_WIDTH( 16)) apf_rsv_e_slv_if ();// + ofs_fim_axi_lite_if #(.AWADDR_WIDTH(16),.ARADDR_WIDTH( 16)) apf_rsv_f_slv_if ();// + + logic [1:0] pf_vf_fifo_err; + logic [1:0] pf_vf_fifo_perr; + + logic sel_mmio_rsp; + logic read_flush_done; + logic port_softreset_n; + logic afu_softreset; + logic afu_softreset_dlyd; + + + logic rstn_a /* synthesis preserve_syn_only */ ; + logic rstn_b /* synthesis preserve_syn_only */ ; + +// +// Macros for mapping port defintions to PF/VF resets. We use macros instead +// of functions to avoid problems with continuous assignment. +// Get the VF function level reset if VF is active for the function. +// If VF is not active, return a constant: not in reset. +`define GET_FUNC_VF_RST_N(PF, VF, VF_ACTIVE) ((VF_ACTIVE != 0) ? func_rst_n[VF+1] : 1'b1) + +// Construct the full reset for a function, combining PF and VF resets. +`define GET_FUNC_RST_N(PF, VF, VF_ACTIVE) (func_rst_n[0] & `GET_FUNC_VF_RST_N(PF, VF, VF_ACTIVE)) + +//--------------------------------------------------------------------------------------- + +// Modules instances +//--------------------------------------------------------------------------------------- +// A reset stage is added to reduce timing impact on reset tree when PC was added +always @(posedge clk) begin + rstn_a <= rst_n; + rstn_b <= rst_n; + afu_softreset_dlyd <= afu_softreset; +end + +// +// The protocol checker expects TXREQ ports, which this FIM does not have. +// Create some dummy interfaces. +// +pcie_ss_axis_if + #( + .DATA_W (pcie_ss_hdr_pkg::HDR_WIDTH), + .USER_W (ofs_fim_cfg_pkg::PCIE_TUSER_WIDTH) + ) + pcie_ss_axis_txreq_dummy(.clk(clk), .rst_n(rst_n)); + +pcie_ss_axis_if + #( + .DATA_W (pcie_ss_hdr_pkg::HDR_WIDTH), + .USER_W (ofs_fim_cfg_pkg::PCIE_TUSER_WIDTH) + ) + mx2ho_txreq_port_dummy(.clk(clk), .rst_n(rst_n)); + +assign pcie_ss_axis_txreq_dummy.tready = 1'b1; +assign mx2ho_txreq_port_dummy.tvalid = 1'b0; + +afu_intf #( + .ENABLE (1'b1), + .PCIE_EP_MAX_TAGS (ofs_fim_pcie_pkg::PCIE_EP_MAX_TAGS) +) +afu_intf_inst +( + .clk ( clk ), + .rst_n ( rstn_a ), + + .clk_csr ( clk ), // use normal clock for CSR clock in D5005 + .rst_n_csr ( rstn_a ), + .pwr_good_csr_clk_n ( pwr_good_clk_n ), + + .i_afu_softreset ( afu_softreset_dlyd ), + + .o_sel_mmio_rsp ( sel_mmio_rsp ), + .o_read_flush_done ( read_flush_done ), + + .h2a_axis_rx ( pcie_ss_axis_rx ), + .a2h_axis_tx ( pcie_ss_axis_tx ), + .a2h_axis_txreq ( pcie_ss_axis_txreq_dummy ), + + .afu_axis_rx ( ho2mx_rx_port ), + .afu_axis_tx ( mx2ho_tx_port ), + .afu_axis_txreq ( mx2ho_txreq_port_dummy ), + + .csr_if ( apf_achk_slv_if ) +); + + // d5005 PCIe SS emulation does not indicate the dynamic extended tag + // configuration. We assume the interface is configured for 8 bit tags. + pcie_ss_axis_pkg::t_pcie_tag_mode tag_mode; + always_comb + begin + tag_mode = '0; + tag_mode.tag_8bit = 1'b1; + end + + tag_remap #( // + .REMAP ( 1 ) // Enable/Disable Tag Remap function + ) // + tag_remap ( // + .clk ( clk ) ,// clock + .rst_n ( rstn_b ) ,// reset + // + .ho2mx_rx_port ( ho2mx_rx_port ) ,// axis interface to host (PCIE) + .mx2ho_tx_port ( mx2ho_tx_port ) ,// + .ho2mx_rx_remap ( ho2mx_rx_remap ) ,// axis interface to pf_vf_mux + .mx2ho_tx_remap ( mx2ho_tx_remap ) ,// + .tag_mode ( tag_mode ) // + ) ;// + + // + // There are two independent TX PF/VF MUX trees, labeled "A" and "B". + // Both an A and a B port are passed to each AFU. AFUs can either send + // all requests to the primary A port or partition requests across + // both A and B ports. A typical high-performance AFU will send + // read requests to the B port and everything else to the A port, + // giving the arbiter here freedom to keep both the host TX and RX + // channels busy. + // + // Here, the A and B TX trees have been multiplexed down to a single + // channel for A and another for B. The A/B multiplexer merges them + // into a single TX stream that will be passed to the tag remapper. + // + pcie_ss_axis_mux #( + .NUM_CH ( 2 ) + ) + mx2ho_tx_ab_mux + ( + .clk ( clk ), + .rst_n ( rstn_b ), + + .sink ( mx2ho_tx_ab ), + .source ( arb2ho_tx_port ) + ); + + // Generate local commits for writes that have passed A/B MUX + // arbitration. This way AFUs can know when writes on A and reads + // on B have been committed to a fixed order. + pcie_arb_local_commit local_commit + ( + .clk ( clk ), + .rst_n ( rstn_b ), + + .sink ( arb2ho_tx_port ), + .source ( mx2ho_tx_remap ), + .commit ( arb2mx_rx_b ) + ); + + // Primary PF/VF MUX ("A" ports). Map individual TX A ports from + // AFUs down to a single, merged A channel. The RX port from host + // to FPGA is demultiplexed and individual connections are forwarded + // to AFUs. + pf_vf_mux_top #( + .MUX_NAME("A"), + .NUM_PORT(top_cfg_pkg::NUM_PORT), + .NUM_RTABLE_ENTRIES(top_cfg_pkg::NUM_RTABLE_ENTRIES), + .PFVF_ROUTING_TABLE(top_cfg_pkg::PFVF_ROUTING_TABLE) + ) + pf_vf_mux_a ( + .clk ( clk ), + .rst_n ( rstn_b ), + + .ho2mx_rx_port ( ho2mx_rx_remap ), + .mx2ho_tx_port ( mx2ho_tx_ab[0] ), + .mx2fn_rx_port ( mx2fn_rx_a_port ), + .fn2mx_tx_port ( fn2mx_tx_a_port ), + .out_fifo_err ( pf_vf_fifo_err[0] ), + .out_fifo_perr ( pf_vf_fifo_perr[0] ) + ); + + // Secondary PF/VF MUX ("B" ports). Only TX is implemented, since a + // single RX stream is sufficient. The RX input to the MUX is tied off. + // AFU B TX ports are multiplexed into a single TX B channel that is + // passed to the A/B MUX above. + pf_vf_mux_top #( + .MUX_NAME("B"), + .NUM_PORT(top_cfg_pkg::NUM_PORT), + .NUM_RTABLE_ENTRIES(top_cfg_pkg::NUM_RTABLE_ENTRIES), + .PFVF_ROUTING_TABLE(top_cfg_pkg::PFVF_ROUTING_TABLE) + ) + pf_vf_mux_b ( + .clk ( clk ), + .rst_n ( rstn_b ), + + .ho2mx_rx_port ( arb2mx_rx_b ), + .mx2ho_tx_port ( mx2ho_tx_ab[1] ), + .mx2fn_rx_port ( mx2fn_rx_b_port ), + .fn2mx_tx_port ( fn2mx_tx_b_port ), + .out_fifo_err ( pf_vf_fifo_err[1] ), + .out_fifo_perr ( pf_vf_fifo_perr[1] ) + ); + + +axis_axil_bridge #( + .PF_NUM ( CFG_PF ), + .VF_NUM ( CFG_VF ), + .VF_ACTIVE ( CFG_VA ), + .MM_ADDR_WIDTH ( TOTAL_BAR_SIZE ) + ) +axis_axil_bridge ( + .clk ( clk ), + .rst_n ( rstn_b ), + .flrst_n ( `GET_FUNC_RST_N(CFG_PF,CFG_VF,CFG_VA)), + .axis_rx_if ( mx2fn_rx_a_port[CFG_PID] ), + .axis_tx_if ( fn2mx_tx_a_port[CFG_PID] ), + + .axi_m_if ( apf_st2mm_mst_if ), + .axi_s_if ( apf_st2mm_slv_if ) + ); + +// Configuration does not use the TX B port +assign fn2mx_tx_b_port[CFG_PID].tvalid = 1'b0; +assign mx2fn_rx_b_port[CFG_PID].tready = 1'b1; + +`ifdef ERROR_INJ + +he_lb_err_top #( + .PF_ID ( HLB_PF ), + .VF_ID ( HLB_VF ), + .VF_ACTIVE ( HLB_VA ), + .SPLIT_RSP ( 1 ) + ) +he_lb_err_inst( + .clk ( clk ), + .rst_n ( rstn_b & `GET_FUNC_RST_N(HLB_PF,HLB_VF,HLB_VA) ), + .axi_rx_a_if( mx2fn_rx_a_port[HLB_PID] ), + .axi_rx_b_if( mx2fn_rx_b_port[HLB_PID] ), + .axi_tx_a_if( fn2mx_tx_a_port[HLB_PID] ), + .axi_tx_b_if( fn2mx_tx_b_port[HLB_PID] ) + ); + +`else +he_lb_top #( + .PF_ID ( HLB_PF ), + .VF_ID ( HLB_VF ), + .VF_ACTIVE ( HLB_VA ) + ) +he_lb_inst( + .clk ( clk ), + .rst_n ( rstn_b & `GET_FUNC_RST_N(HLB_PF,HLB_VF,HLB_VA) ), + .axi_rx_a_if( mx2fn_rx_a_port[HLB_PID] ), + .axi_rx_b_if( mx2fn_rx_b_port[HLB_PID] ), + .axi_tx_a_if( fn2mx_tx_a_port[HLB_PID] ), + .axi_tx_b_if( fn2mx_tx_b_port[HLB_PID] ) + ); +`endif + +//---------------------------------------------------------------- +// Port Gasket +//---------------------------------------------------------------- + +// Map the PF/VF association of AFU ports to the parameters that will be +// passed to the port gasket. +typedef pcie_ss_hdr_pkg::ReqHdr_pf_vf_info_t[PG_AFU_NUM_PORTS-1:0] t_afu_pf_vf_map; +function automatic t_afu_pf_vf_map gen_afu_pf_vf_map(); + t_afu_pf_vf_map map; + + for (int p = 0; p < PG_AFU_NUM_PORTS; p = p + 1) begin + map[p].pf_num = PG_AFU_PORTS_PF_NUM[p]; + map[p].vf_num = PG_AFU_PORTS_VF_NUM[p]; + map[p].vf_active = PG_AFU_PORTS_VF_ACTIVE[p]; + end + + return map; +endfunction // gen_afu_pf_vf_map + +localparam pcie_ss_hdr_pkg::ReqHdr_pf_vf_info_t[PG_AFU_NUM_PORTS-1:0] PORT_PF_VF_INFO = + gen_afu_pf_vf_map(); + +// +// Map TLP ports from the PF/VF MUXes to the vector of ports that is +// passed through the port gasket to afu_main(). +// +generate + for (genvar p = 0; p < PG_AFU_NUM_PORTS; p = p + 1) + begin : afp + assign afu_rst_n[p] = `GET_FUNC_RST_N(PG_AFU_PORTS_PF_NUM[p],PG_AFU_PORTS_VF_NUM[p],PG_AFU_PORTS_VF_ACTIVE[p]); + + assign mx2fn_rx_a_port[PG_AFU_MUX_PID[p]].tready = afu_rx_a_port[p].tready; + assign afu_rx_a_port[p].tvalid = mx2fn_rx_a_port[PG_AFU_MUX_PID[p]].tvalid; + assign afu_rx_a_port[p].tlast = mx2fn_rx_a_port[PG_AFU_MUX_PID[p]].tlast; + assign afu_rx_a_port[p].tuser_vendor = mx2fn_rx_a_port[PG_AFU_MUX_PID[p]].tuser_vendor; + assign afu_rx_a_port[p].tdata = mx2fn_rx_a_port[PG_AFU_MUX_PID[p]].tdata; + assign afu_rx_a_port[p].tkeep = mx2fn_rx_a_port[PG_AFU_MUX_PID[p]].tkeep; + + assign mx2fn_rx_b_port[PG_AFU_MUX_PID[p]].tready = afu_rx_b_port[p].tready; + assign afu_rx_b_port[p].tvalid = mx2fn_rx_b_port[PG_AFU_MUX_PID[p]].tvalid; + assign afu_rx_b_port[p].tlast = mx2fn_rx_b_port[PG_AFU_MUX_PID[p]].tlast; + assign afu_rx_b_port[p].tuser_vendor = mx2fn_rx_b_port[PG_AFU_MUX_PID[p]].tuser_vendor; + assign afu_rx_b_port[p].tdata = mx2fn_rx_b_port[PG_AFU_MUX_PID[p]].tdata; + assign afu_rx_b_port[p].tkeep = mx2fn_rx_b_port[PG_AFU_MUX_PID[p]].tkeep; + + assign afu_tx_a_port[p].tready = fn2mx_tx_a_port[PG_AFU_MUX_PID[p]].tready; + assign fn2mx_tx_a_port[PG_AFU_MUX_PID[p]].tvalid = afu_tx_a_port[p].tvalid; + assign fn2mx_tx_a_port[PG_AFU_MUX_PID[p]].tlast = afu_tx_a_port[p].tlast; + assign fn2mx_tx_a_port[PG_AFU_MUX_PID[p]].tuser_vendor = afu_tx_a_port[p].tuser_vendor; + assign fn2mx_tx_a_port[PG_AFU_MUX_PID[p]].tdata = afu_tx_a_port[p].tdata; + assign fn2mx_tx_a_port[PG_AFU_MUX_PID[p]].tkeep = afu_tx_a_port[p].tkeep; + + assign afu_tx_b_port[p].tready = fn2mx_tx_b_port[PG_AFU_MUX_PID[p]].tready; + assign fn2mx_tx_b_port[PG_AFU_MUX_PID[p]].tvalid = afu_tx_b_port[p].tvalid; + assign fn2mx_tx_b_port[PG_AFU_MUX_PID[p]].tlast = afu_tx_b_port[p].tlast; + assign fn2mx_tx_b_port[PG_AFU_MUX_PID[p]].tuser_vendor = afu_tx_b_port[p].tuser_vendor; + assign fn2mx_tx_b_port[PG_AFU_MUX_PID[p]].tdata = afu_tx_b_port[p].tdata; + assign fn2mx_tx_b_port[PG_AFU_MUX_PID[p]].tkeep = afu_tx_b_port[p].tkeep; + end +endgenerate + +port_gasket #( + .PG_NUM_PORTS(PG_AFU_NUM_PORTS), + .PORT_PF_VF_INFO(PORT_PF_VF_INFO), + .NUM_MEM_CH(NUM_MEM_CH), + .END_OF_LIST (1'b0), + .NEXT_DFH_OFFSET(24'h01_0000) + ) +port_gasket( + .refclk ( refclk ), + .clk_2x ( clk ), + .clk_1x ( clk_div2 ), + .clk_100 ( clk_100 ), + .clk_div4 ( clk ), //FUTURE_IMPROVEMENT + + .rst_n_2x ( rstn_b ), + .rst_n_1x ( rst_n_div2 ), + .rst_n_100 ( rst_n_100 ), + .port_rst_n ( afu_rst_n ), + + .i_sel_mmio_rsp ( sel_mmio_rsp ), + .i_read_flush_done ( read_flush_done ), + .o_port_softreset_n ( port_softreset_n ), + .o_afu_softreset ( afu_softreset ), + .o_pr_parity_error (pr_parity_error ), // Partial Reconfiguration FIFO Parity Error Indication from PR Controller. + + .axi_tx_a_if ( afu_tx_a_port ), + .axi_rx_a_if ( afu_rx_a_port ), + .axi_tx_b_if ( afu_tx_b_port ), + .axi_rx_b_if ( afu_rx_b_port ), + + `ifdef INCLUDE_HE_HSSI + .hssi_ss_st_tx ( hssi_ss_st_tx), + .hssi_ss_st_rx ( hssi_ss_st_rx), + .hssi_fc ( hssi_fc), + `ifdef INCLUDE_PTP + .hssi_ptp_tx_tod ( hssi_ptp_tx_tod ), + .hssi_ptp_rx_tod ( hssi_ptp_rx_tod ), + .hssi_ptp_tx_egrts ( hssi_ptp_tx_egrts ), + .hssi_ptp_rx_ingrts ( hssi_ptp_rx_ingrts ), + `endif + .i_hssi_clk_pll (i_hssi_clk_pll ), + `endif + .axi_s_if ( apf_pgsk_slv_if ), + .afu_mem_if ( afu_mem_if ) +); + +// AFU Peripheral Fabric +apf apf( + .clk_clk (clk ), + .rst_n_reset_n (rstn_b ), + + .apf_st2mm_mst_awaddr (apf_st2mm_mst_if.awaddr ), + .apf_st2mm_mst_awprot (apf_st2mm_mst_if.awprot ), + .apf_st2mm_mst_awvalid (apf_st2mm_mst_if.awvalid), + .apf_st2mm_mst_awready (apf_st2mm_mst_if.awready), + .apf_st2mm_mst_wdata (apf_st2mm_mst_if.wdata ), + .apf_st2mm_mst_wstrb (apf_st2mm_mst_if.wstrb ), + .apf_st2mm_mst_wvalid (apf_st2mm_mst_if.wvalid ), + .apf_st2mm_mst_wready (apf_st2mm_mst_if.wready ), + .apf_st2mm_mst_bresp (apf_st2mm_mst_if.bresp ), + .apf_st2mm_mst_bvalid (apf_st2mm_mst_if.bvalid ), + .apf_st2mm_mst_bready (apf_st2mm_mst_if.bready ), + .apf_st2mm_mst_araddr (apf_st2mm_mst_if.araddr ), + .apf_st2mm_mst_arprot (apf_st2mm_mst_if.arprot ), + .apf_st2mm_mst_arvalid (apf_st2mm_mst_if.arvalid), + .apf_st2mm_mst_arready (apf_st2mm_mst_if.arready), + .apf_st2mm_mst_rdata (apf_st2mm_mst_if.rdata ), + .apf_st2mm_mst_rresp (apf_st2mm_mst_if.rresp ), + .apf_st2mm_mst_rvalid (apf_st2mm_mst_if.rvalid ), + .apf_st2mm_mst_rready (apf_st2mm_mst_if.rready ), + + .apf_st2mm_slv_awaddr (apf_st2mm_slv_if.awaddr ), + .apf_st2mm_slv_awprot (apf_st2mm_slv_if.awprot ), + .apf_st2mm_slv_awvalid (apf_st2mm_slv_if.awvalid), + .apf_st2mm_slv_awready (apf_st2mm_slv_if.awready), + .apf_st2mm_slv_wdata (apf_st2mm_slv_if.wdata ), + .apf_st2mm_slv_wstrb (apf_st2mm_slv_if.wstrb ), + .apf_st2mm_slv_wvalid (apf_st2mm_slv_if.wvalid ), + .apf_st2mm_slv_wready (apf_st2mm_slv_if.wready ), + .apf_st2mm_slv_bresp (apf_st2mm_slv_if.bresp ), + .apf_st2mm_slv_bvalid (apf_st2mm_slv_if.bvalid ), + .apf_st2mm_slv_bready (apf_st2mm_slv_if.bready ), + .apf_st2mm_slv_araddr (apf_st2mm_slv_if.araddr ), + .apf_st2mm_slv_arprot (apf_st2mm_slv_if.arprot ), + .apf_st2mm_slv_arvalid (apf_st2mm_slv_if.arvalid), + .apf_st2mm_slv_arready (apf_st2mm_slv_if.arready), + .apf_st2mm_slv_rdata (apf_st2mm_slv_if.rdata ), + .apf_st2mm_slv_rresp (apf_st2mm_slv_if.rresp ), + .apf_st2mm_slv_rvalid (apf_st2mm_slv_if.rvalid ), + .apf_st2mm_slv_rready (apf_st2mm_slv_if.rready ), + + .apf_pgsk_slv_awaddr (apf_pgsk_slv_if.awaddr ), + .apf_pgsk_slv_awprot (apf_pgsk_slv_if.awprot ), + .apf_pgsk_slv_awvalid (apf_pgsk_slv_if.awvalid ), + .apf_pgsk_slv_awready (apf_pgsk_slv_if.awready ), + .apf_pgsk_slv_wdata (apf_pgsk_slv_if.wdata ), + .apf_pgsk_slv_wstrb (apf_pgsk_slv_if.wstrb ), + .apf_pgsk_slv_wvalid (apf_pgsk_slv_if.wvalid ), + .apf_pgsk_slv_wready (apf_pgsk_slv_if.wready ), + .apf_pgsk_slv_bresp (apf_pgsk_slv_if.bresp ), + .apf_pgsk_slv_bvalid (apf_pgsk_slv_if.bvalid ), + .apf_pgsk_slv_bready (apf_pgsk_slv_if.bready ), + .apf_pgsk_slv_araddr (apf_pgsk_slv_if.araddr ), + .apf_pgsk_slv_arprot (apf_pgsk_slv_if.arprot ), + .apf_pgsk_slv_arvalid (apf_pgsk_slv_if.arvalid ), + .apf_pgsk_slv_arready (apf_pgsk_slv_if.arready ), + .apf_pgsk_slv_rdata (apf_pgsk_slv_if.rdata ), + .apf_pgsk_slv_rresp (apf_pgsk_slv_if.rresp ), + .apf_pgsk_slv_rvalid (apf_pgsk_slv_if.rvalid ), + .apf_pgsk_slv_rready (apf_pgsk_slv_if.rready ), + + .apf_achk_slv_awaddr (apf_achk_slv_if.awaddr ), + .apf_achk_slv_awprot (apf_achk_slv_if.awprot ), + .apf_achk_slv_awvalid (apf_achk_slv_if.awvalid ), + .apf_achk_slv_awready (apf_achk_slv_if.awready ), + .apf_achk_slv_wdata (apf_achk_slv_if.wdata ), + .apf_achk_slv_wstrb (apf_achk_slv_if.wstrb ), + .apf_achk_slv_wvalid (apf_achk_slv_if.wvalid ), + .apf_achk_slv_wready (apf_achk_slv_if.wready ), + .apf_achk_slv_bresp (apf_achk_slv_if.bresp ), + .apf_achk_slv_bvalid (apf_achk_slv_if.bvalid ), + .apf_achk_slv_bready (apf_achk_slv_if.bready ), + .apf_achk_slv_araddr (apf_achk_slv_if.araddr ), + .apf_achk_slv_arprot (apf_achk_slv_if.arprot ), + .apf_achk_slv_arvalid (apf_achk_slv_if.arvalid ), + .apf_achk_slv_arready (apf_achk_slv_if.arready ), + .apf_achk_slv_rdata (apf_achk_slv_if.rdata ), + .apf_achk_slv_rresp (apf_achk_slv_if.rresp ), + .apf_achk_slv_rvalid (apf_achk_slv_if.rvalid ), + .apf_achk_slv_rready (apf_achk_slv_if.rready ), + + .apf_rsv_b_slv_awaddr (apf_rsv_b_slv_if.awaddr ), + .apf_rsv_b_slv_awprot (apf_rsv_b_slv_if.awprot ), + .apf_rsv_b_slv_awvalid (apf_rsv_b_slv_if.awvalid), + .apf_rsv_b_slv_awready (apf_rsv_b_slv_if.awready), + .apf_rsv_b_slv_wdata (apf_rsv_b_slv_if.wdata ), + .apf_rsv_b_slv_wstrb (apf_rsv_b_slv_if.wstrb ), + .apf_rsv_b_slv_wvalid (apf_rsv_b_slv_if.wvalid ), + .apf_rsv_b_slv_wready (apf_rsv_b_slv_if.wready ), + .apf_rsv_b_slv_bresp (apf_rsv_b_slv_if.bresp ), + .apf_rsv_b_slv_bvalid (apf_rsv_b_slv_if.bvalid ), + .apf_rsv_b_slv_bready (apf_rsv_b_slv_if.bready ), + .apf_rsv_b_slv_araddr (apf_rsv_b_slv_if.araddr ), + .apf_rsv_b_slv_arprot (apf_rsv_b_slv_if.arprot ), + .apf_rsv_b_slv_arvalid (apf_rsv_b_slv_if.arvalid), + .apf_rsv_b_slv_arready (apf_rsv_b_slv_if.arready), + .apf_rsv_b_slv_rdata (apf_rsv_b_slv_if.rdata ), + .apf_rsv_b_slv_rresp (apf_rsv_b_slv_if.rresp ), + .apf_rsv_b_slv_rvalid (apf_rsv_b_slv_if.rvalid ), + .apf_rsv_b_slv_rready (apf_rsv_b_slv_if.rready ), + + .apf_rsv_c_slv_awaddr (apf_rsv_c_slv_if.awaddr ), + .apf_rsv_c_slv_awprot (apf_rsv_c_slv_if.awprot ), + .apf_rsv_c_slv_awvalid (apf_rsv_c_slv_if.awvalid), + .apf_rsv_c_slv_awready (apf_rsv_c_slv_if.awready), + .apf_rsv_c_slv_wdata (apf_rsv_c_slv_if.wdata ), + .apf_rsv_c_slv_wstrb (apf_rsv_c_slv_if.wstrb ), + .apf_rsv_c_slv_wvalid (apf_rsv_c_slv_if.wvalid ), + .apf_rsv_c_slv_wready (apf_rsv_c_slv_if.wready ), + .apf_rsv_c_slv_bresp (apf_rsv_c_slv_if.bresp ), + .apf_rsv_c_slv_bvalid (apf_rsv_c_slv_if.bvalid ), + .apf_rsv_c_slv_bready (apf_rsv_c_slv_if.bready ), + .apf_rsv_c_slv_araddr (apf_rsv_c_slv_if.araddr ), + .apf_rsv_c_slv_arprot (apf_rsv_c_slv_if.arprot ), + .apf_rsv_c_slv_arvalid (apf_rsv_c_slv_if.arvalid), + .apf_rsv_c_slv_arready (apf_rsv_c_slv_if.arready), + .apf_rsv_c_slv_rdata (apf_rsv_c_slv_if.rdata ), + .apf_rsv_c_slv_rresp (apf_rsv_c_slv_if.rresp ), + .apf_rsv_c_slv_rvalid (apf_rsv_c_slv_if.rvalid ), + .apf_rsv_c_slv_rready (apf_rsv_c_slv_if.rready ), + + .apf_rsv_d_slv_awaddr (apf_rsv_d_slv_if.awaddr ), + .apf_rsv_d_slv_awprot (apf_rsv_d_slv_if.awprot ), + .apf_rsv_d_slv_awvalid (apf_rsv_d_slv_if.awvalid), + .apf_rsv_d_slv_awready (apf_rsv_d_slv_if.awready), + .apf_rsv_d_slv_wdata (apf_rsv_d_slv_if.wdata ), + .apf_rsv_d_slv_wstrb (apf_rsv_d_slv_if.wstrb ), + .apf_rsv_d_slv_wvalid (apf_rsv_d_slv_if.wvalid ), + .apf_rsv_d_slv_wready (apf_rsv_d_slv_if.wready ), + .apf_rsv_d_slv_bresp (apf_rsv_d_slv_if.bresp ), + .apf_rsv_d_slv_bvalid (apf_rsv_d_slv_if.bvalid ), + .apf_rsv_d_slv_bready (apf_rsv_d_slv_if.bready ), + .apf_rsv_d_slv_araddr (apf_rsv_d_slv_if.araddr ), + .apf_rsv_d_slv_arprot (apf_rsv_d_slv_if.arprot ), + .apf_rsv_d_slv_arvalid (apf_rsv_d_slv_if.arvalid), + .apf_rsv_d_slv_arready (apf_rsv_d_slv_if.arready), + .apf_rsv_d_slv_rdata (apf_rsv_d_slv_if.rdata ), + .apf_rsv_d_slv_rresp (apf_rsv_d_slv_if.rresp ), + .apf_rsv_d_slv_rvalid (apf_rsv_d_slv_if.rvalid ), + .apf_rsv_d_slv_rready (apf_rsv_d_slv_if.rready ), + + .apf_rsv_e_slv_awaddr (apf_rsv_e_slv_if.awaddr ), + .apf_rsv_e_slv_awprot (apf_rsv_e_slv_if.awprot ), + .apf_rsv_e_slv_awvalid (apf_rsv_e_slv_if.awvalid), + .apf_rsv_e_slv_awready (apf_rsv_e_slv_if.awready), + .apf_rsv_e_slv_wdata (apf_rsv_e_slv_if.wdata ), + .apf_rsv_e_slv_wstrb (apf_rsv_e_slv_if.wstrb ), + .apf_rsv_e_slv_wvalid (apf_rsv_e_slv_if.wvalid ), + .apf_rsv_e_slv_wready (apf_rsv_e_slv_if.wready ), + .apf_rsv_e_slv_bresp (apf_rsv_e_slv_if.bresp ), + .apf_rsv_e_slv_bvalid (apf_rsv_e_slv_if.bvalid ), + .apf_rsv_e_slv_bready (apf_rsv_e_slv_if.bready ), + .apf_rsv_e_slv_araddr (apf_rsv_e_slv_if.araddr ), + .apf_rsv_e_slv_arprot (apf_rsv_e_slv_if.arprot ), + .apf_rsv_e_slv_arvalid (apf_rsv_e_slv_if.arvalid), + .apf_rsv_e_slv_arready (apf_rsv_e_slv_if.arready), + .apf_rsv_e_slv_rdata (apf_rsv_e_slv_if.rdata ), + .apf_rsv_e_slv_rresp (apf_rsv_e_slv_if.rresp ), + .apf_rsv_e_slv_rvalid (apf_rsv_e_slv_if.rvalid ), + .apf_rsv_e_slv_rready (apf_rsv_e_slv_if.rready ), + + .apf_rsv_f_slv_awaddr (apf_rsv_f_slv_if.awaddr ), + .apf_rsv_f_slv_awprot (apf_rsv_f_slv_if.awprot ), + .apf_rsv_f_slv_awvalid (apf_rsv_f_slv_if.awvalid), + .apf_rsv_f_slv_awready (apf_rsv_f_slv_if.awready), + .apf_rsv_f_slv_wdata (apf_rsv_f_slv_if.wdata ), + .apf_rsv_f_slv_wstrb (apf_rsv_f_slv_if.wstrb ), + .apf_rsv_f_slv_wvalid (apf_rsv_f_slv_if.wvalid ), + .apf_rsv_f_slv_wready (apf_rsv_f_slv_if.wready ), + .apf_rsv_f_slv_bresp (apf_rsv_f_slv_if.bresp ), + .apf_rsv_f_slv_bvalid (apf_rsv_f_slv_if.bvalid ), + .apf_rsv_f_slv_bready (apf_rsv_f_slv_if.bready ), + .apf_rsv_f_slv_araddr (apf_rsv_f_slv_if.araddr ), + .apf_rsv_f_slv_arprot (apf_rsv_f_slv_if.arprot ), + .apf_rsv_f_slv_arvalid (apf_rsv_f_slv_if.arvalid), + .apf_rsv_f_slv_arready (apf_rsv_f_slv_if.arready), + .apf_rsv_f_slv_rdata (apf_rsv_f_slv_if.rdata ), + .apf_rsv_f_slv_rresp (apf_rsv_f_slv_if.rresp ), + .apf_rsv_f_slv_rvalid (apf_rsv_f_slv_if.rvalid ), + .apf_rsv_f_slv_rready (apf_rsv_f_slv_if.rready ), + + .apf_bpf_slv_awaddr (apf_bpf_slv_if.awaddr ), + .apf_bpf_slv_awprot (apf_bpf_slv_if.awprot ), + .apf_bpf_slv_awvalid (apf_bpf_slv_if.awvalid ), + .apf_bpf_slv_awready (apf_bpf_slv_if.awready ), + .apf_bpf_slv_wdata (apf_bpf_slv_if.wdata ), + .apf_bpf_slv_wstrb (apf_bpf_slv_if.wstrb ), + .apf_bpf_slv_wvalid (apf_bpf_slv_if.wvalid ), + .apf_bpf_slv_wready (apf_bpf_slv_if.wready ), + .apf_bpf_slv_bresp (apf_bpf_slv_if.bresp ), + .apf_bpf_slv_bvalid (apf_bpf_slv_if.bvalid ), + .apf_bpf_slv_bready (apf_bpf_slv_if.bready ), + .apf_bpf_slv_araddr (apf_bpf_slv_if.araddr ), + .apf_bpf_slv_arprot (apf_bpf_slv_if.arprot ), + .apf_bpf_slv_arvalid (apf_bpf_slv_if.arvalid ), + .apf_bpf_slv_arready (apf_bpf_slv_if.arready ), + .apf_bpf_slv_rdata (apf_bpf_slv_if.rdata ), + .apf_bpf_slv_rresp (apf_bpf_slv_if.rresp ), + .apf_bpf_slv_rvalid (apf_bpf_slv_if.rvalid ), + .apf_bpf_slv_rready (apf_bpf_slv_if.rready ), + + .apf_bpf_mst_awaddr (apf_bpf_mst_if.awaddr ), + .apf_bpf_mst_awprot (apf_bpf_mst_if.awprot ), + .apf_bpf_mst_awvalid (apf_bpf_mst_if.awvalid ), + .apf_bpf_mst_awready (apf_bpf_mst_if.awready ), + .apf_bpf_mst_wdata (apf_bpf_mst_if.wdata ), + .apf_bpf_mst_wstrb (apf_bpf_mst_if.wstrb ), + .apf_bpf_mst_wvalid (apf_bpf_mst_if.wvalid ), + .apf_bpf_mst_wready (apf_bpf_mst_if.wready ), + .apf_bpf_mst_bresp (apf_bpf_mst_if.bresp ), + .apf_bpf_mst_bvalid (apf_bpf_mst_if.bvalid ), + .apf_bpf_mst_bready (apf_bpf_mst_if.bready ), + .apf_bpf_mst_araddr (apf_bpf_mst_if.araddr ), + .apf_bpf_mst_arprot (apf_bpf_mst_if.arprot ), + .apf_bpf_mst_arvalid (apf_bpf_mst_if.arvalid ), + .apf_bpf_mst_arready (apf_bpf_mst_if.arready ), + .apf_bpf_mst_rdata (apf_bpf_mst_if.rdata ), + .apf_bpf_mst_rresp (apf_bpf_mst_if.rresp ), + .apf_bpf_mst_rvalid (apf_bpf_mst_if.rvalid ), + .apf_bpf_mst_rready (apf_bpf_mst_if.rready ) + ); + + // Reserved address response + /* apf_dummy_slv + apf_achk_slv ( + .clk (clk), + .dummy_slv_if (apf_achk_slv_if) + ); +*/ + apf_dummy_slv + apf_rsv_b_slv ( + .clk (clk), + .dummy_slv_if (apf_rsv_b_slv_if) + ); + + apf_dummy_slv + apf_rsv_c_slv ( + .clk (clk), + .dummy_slv_if (apf_rsv_c_slv_if) + ); + + apf_dummy_slv + apf_rsv_d_slv ( + .clk (clk), + .dummy_slv_if (apf_rsv_d_slv_if) + ); + + apf_dummy_slv + apf_rsv_e_slv ( + .clk (clk), + .dummy_slv_if (apf_rsv_e_slv_if) + ); + + apf_dummy_slv + apf_rsv_f_slv ( + .clk (clk), + .dummy_slv_if (apf_rsv_f_slv_if) + ); +/* +always_comb +begin + apf_rsv_b_slv_if.awready = 1; + apf_rsv_b_slv_if.wready = 1; + apf_rsv_b_slv_if.bresp = 0; + apf_rsv_b_slv_if.arready = 1; + apf_rsv_b_slv_if.rdata = 0; + apf_rsv_b_slv_if.rresp = 0; + + apf_rsv_c_slv_if.awready = 1; + apf_rsv_c_slv_if.wready = 1; + apf_rsv_c_slv_if.bresp = 0; + apf_rsv_c_slv_if.arready = 1; + apf_rsv_c_slv_if.rdata = 0; + apf_rsv_c_slv_if.rresp = 0; + + apf_rsv_d_slv_if.awready = 1; + apf_rsv_d_slv_if.wready = 1; + apf_rsv_d_slv_if.bresp = 0; + apf_rsv_d_slv_if.arready = 1; + apf_rsv_d_slv_if.rdata = 0; + apf_rsv_d_slv_if.rresp = 0; + + apf_rsv_e_slv_if.awready = 1; + apf_rsv_e_slv_if.wready = 1; + apf_rsv_e_slv_if.bresp = 0; + apf_rsv_e_slv_if.arready = 1; + apf_rsv_e_slv_if.rdata = 0; + apf_rsv_e_slv_if.rresp = 0; + + apf_rsv_f_slv_if.awready = 1; + apf_rsv_f_slv_if.wready = 1; + apf_rsv_f_slv_if.bresp = 0; + apf_rsv_f_slv_if.arready = 1; + apf_rsv_f_slv_if.rdata = 0; + apf_rsv_f_slv_if.rresp = 0; + +end + +always_ff @ ( posedge clk ) +begin // DUMMY address response + apf_rsv_b_slv_if.bvalid <= apf_rsv_b_slv_if.awvalid; + apf_rsv_b_slv_if.rvalid <= apf_rsv_b_slv_if.arvalid; + apf_rsv_c_slv_if.bvalid <= apf_rsv_c_slv_if.awvalid; + apf_rsv_c_slv_if.rvalid <= apf_rsv_c_slv_if.arvalid; + apf_rsv_d_slv_if.bvalid <= apf_rsv_d_slv_if.awvalid; + apf_rsv_d_slv_if.rvalid <= apf_rsv_d_slv_if.arvalid; + apf_rsv_e_slv_if.bvalid <= apf_rsv_e_slv_if.awvalid; + apf_rsv_e_slv_if.rvalid <= apf_rsv_e_slv_if.arvalid; + apf_rsv_f_slv_if.bvalid <= apf_rsv_f_slv_if.awvalid; + apf_rsv_f_slv_if.rvalid <= apf_rsv_f_slv_if.arvalid; +end +*/ +// --------------------------------------------------------------------------- +// Display Debug Messages +// --------------------------------------------------------------------------- +always @ (posedge clk) +begin + `ifdef AFU_MSG + + /* synthesis translate_off */ + + if(pcie_ss_axis_rx.tvalid & pcie_ss_axis_rx.tready) + pcie_ss_pkg::display_cycle("AFU_TOP_RX", 1'b1, (rx_sop_init | rx_sop_valid), pcie_ss_axis_rx.tlast, pcie_ss_axis_rx.tdata); + + if(pcie_ss_axis_tx.tvalid & pcie_ss_axis_tx.tready) + pcie_ss_pkg::display_cycle("AFU_TOP_TX", 1'b0, tx_sop_valid, pcie_ss_axis_tx.tlast, pcie_ss_axis_tx.tdata); + + /* synthesis translate_on */ + + `endif //AFU_MSG + +end + `ifdef DEBUG_APF + + reg [25:0] DEBUG_st2mm_mst_awaddr /* synthesis noprune */ ; + reg [ 2:0] DEBUG_st2mm_mst_awprot /* synthesis noprune */ ; + reg DEBUG_st2mm_mst_awvalid /* synthesis noprune */ ; + reg DEBUG_st2mm_mst_awready /* synthesis noprune */ ; + reg [25:0] DEBUG_st2mm_mst_araddr /* synthesis noprune */ ; + reg [ 2:0] DEBUG_st2mm_mst_arprot /* synthesis noprune */ ; + reg DEBUG_st2mm_mst_arvalid /* synthesis noprune */ ; + reg DEBUG_st2mm_mst_arready /* synthesis noprune */ ; + reg [ 7:0] DEBUG_st2mm_mst_wstrb /* synthesis noprune */ ; + reg DEBUG_st2mm_mst_wvalid /* synthesis noprune */ ; + reg DEBUG_st2mm_mst_wready /* synthesis noprune */ ; + reg [ 1:0] DEBUG_st2mm_mst_rresp /* synthesis noprune */ ; + reg DEBUG_st2mm_mst_rvalid /* synthesis noprune */ ; + reg DEBUG_st2mm_mst_rready /* synthesis noprune */ ; + reg [ 1:0] DEBUG_st2mm_mst_bresp /* synthesis noprune */ ; + reg DEBUG_st2mm_mst_bvalid /* synthesis noprune */ ; + reg DEBUG_st2mm_mst_bready /* synthesis noprune */ ; + + reg [25:0] DEBUG_st2mm_slv_awaddr /* synthesis noprune */ ; + reg [ 2:0] DEBUG_st2mm_slv_awprot /* synthesis noprune */ ; + reg DEBUG_st2mm_slv_awvalid /* synthesis noprune */ ; + reg DEBUG_st2mm_slv_awready /* synthesis noprune */ ; + reg [25:0] DEBUG_st2mm_slv_araddr /* synthesis noprune */ ; + reg [ 2:0] DEBUG_st2mm_slv_arprot /* synthesis noprune */ ; + reg DEBUG_st2mm_slv_arvalid /* synthesis noprune */ ; + reg DEBUG_st2mm_slv_arready /* synthesis noprune */ ; + reg [ 7:0] DEBUG_st2mm_slv_wstrb /* synthesis noprune */ ; + reg DEBUG_st2mm_slv_wvalid /* synthesis noprune */ ; + reg DEBUG_st2mm_slv_wready /* synthesis noprune */ ; + reg [ 1:0] DEBUG_st2mm_slv_rresp /* synthesis noprune */ ; + reg DEBUG_st2mm_slv_rvalid /* synthesis noprune */ ; + reg DEBUG_st2mm_slv_rready /* synthesis noprune */ ; + reg [ 1:0] DEBUG_st2mm_slv_bresp /* synthesis noprune */ ; + reg DEBUG_st2mm_slv_bvalid /* synthesis noprune */ ; + reg DEBUG_st2mm_slv_bready /* synthesis noprune */ ; + + reg [25:0] DEBUG_bpf_slv_awaddr /* synthesis noprune */ ; + reg [ 2:0] DEBUG_bpf_slv_awprot /* synthesis noprune */ ; + reg DEBUG_bpf_slv_awvalid /* synthesis noprune */ ; + reg DEBUG_bpf_slv_awready /* synthesis noprune */ ; + reg [25:0] DEBUG_bpf_slv_araddr /* synthesis noprune */ ; + reg [ 2:0] DEBUG_bpf_slv_arprot /* synthesis noprune */ ; + reg DEBUG_bpf_slv_arvalid /* synthesis noprune */ ; + reg DEBUG_bpf_slv_arready /* synthesis noprune */ ; + reg [ 7:0] DEBUG_bpf_slv_wstrb /* synthesis noprune */ ; + reg DEBUG_bpf_slv_wvalid /* synthesis noprune */ ; + reg DEBUG_bpf_slv_wready /* synthesis noprune */ ; + reg [ 1:0] DEBUG_bpf_slv_rresp /* synthesis noprune */ ; + reg DEBUG_bpf_slv_rvalid /* synthesis noprune */ ; + reg DEBUG_bpf_slv_rready /* synthesis noprune */ ; + reg [ 1:0] DEBUG_bpf_slv_bresp /* synthesis noprune */ ; + reg DEBUG_bpf_slv_bvalid /* synthesis noprune */ ; + reg DEBUG_bpf_slv_bready /* synthesis noprune */ ; + + reg [25:0] DEBUG_pgsk_slv_awaddr /* synthesis noprune */ ; + reg [ 2:0] DEBUG_pgsk_slv_awprot /* synthesis noprune */ ; + reg DEBUG_pgsk_slv_awvalid /* synthesis noprune */ ; + reg DEBUG_pgsk_slv_awready /* synthesis noprune */ ; + reg [25:0] DEBUG_pgsk_slv_araddr /* synthesis noprune */ ; + reg [ 2:0] DEBUG_pgsk_slv_arprot /* synthesis noprune */ ; + reg DEBUG_pgsk_slv_arvalid /* synthesis noprune */ ; + reg DEBUG_pgsk_slv_arready /* synthesis noprune */ ; + reg [ 7:0] DEBUG_pgsk_slv_wstrb /* synthesis noprune */ ; + reg DEBUG_pgsk_slv_wvalid /* synthesis noprune */ ; + reg DEBUG_pgsk_slv_wready /* synthesis noprune */ ; + reg [ 1:0] DEBUG_pgsk_slv_rresp /* synthesis noprune */ ; + reg DEBUG_pgsk_slv_rvalid /* synthesis noprune */ ; + reg DEBUG_pgsk_slv_rready /* synthesis noprune */ ; + reg [ 1:0] DEBUG_pgsk_slv_bresp /* synthesis noprune */ ; + reg DEBUG_pgsk_slv_bvalid /* synthesis noprune */ ; + reg DEBUG_pgsk_slv_bready /* synthesis noprune */ ; + + reg [25:0] DEBUG_achk_slv_awaddr /* synthesis noprune */ ; + reg [ 2:0] DEBUG_achk_slv_awprot /* synthesis noprune */ ; + reg DEBUG_achk_slv_awvalid /* synthesis noprune */ ; + reg DEBUG_achk_slv_awready /* synthesis noprune */ ; + reg [25:0] DEBUG_achk_slv_araddr /* synthesis noprune */ ; + reg [ 2:0] DEBUG_achk_slv_arprot /* synthesis noprune */ ; + reg DEBUG_achk_slv_arvalid /* synthesis noprune */ ; + reg DEBUG_achk_slv_arready /* synthesis noprune */ ; + reg [ 7:0] DEBUG_achk_slv_wstrb /* synthesis noprune */ ; + reg DEBUG_achk_slv_wvalid /* synthesis noprune */ ; + reg DEBUG_achk_slv_wready /* synthesis noprune */ ; + reg [ 1:0] DEBUG_achk_slv_rresp /* synthesis noprune */ ; + reg DEBUG_achk_slv_rvalid /* synthesis noprune */ ; + reg DEBUG_achk_slv_rready /* synthesis noprune */ ; + reg [ 1:0] DEBUG_achk_slv_bresp /* synthesis noprune */ ; + reg DEBUG_achk_slv_bvalid /* synthesis noprune */ ; + reg DEBUG_achk_slv_bready /* synthesis noprune */ ; + + reg DEBUG_rsv_b_slv_wvalid /* synthesis noprune */ ; + reg DEBUG_rsv_b_slv_wready /* synthesis noprune */ ; + reg DEBUG_rsv_b_slv_rvalid /* synthesis noprune */ ; + reg DEBUG_rsv_b_slv_rready /* synthesis noprune */ ; + reg DEBUG_rsv_c_slv_wvalid /* synthesis noprune */ ; + reg DEBUG_rsv_c_slv_wready /* synthesis noprune */ ; + reg DEBUG_rsv_c_slv_rvalid /* synthesis noprune */ ; + reg DEBUG_rsv_c_slv_rready /* synthesis noprune */ ; + reg DEBUG_rsv_d_slv_wvalid /* synthesis noprune */ ; + reg DEBUG_rsv_d_slv_wready /* synthesis noprune */ ; + reg DEBUG_rsv_d_slv_rvalid /* synthesis noprune */ ; + reg DEBUG_rsv_d_slv_rready /* synthesis noprune */ ; + reg DEBUG_rsv_e_slv_wvalid /* synthesis noprune */ ; + reg DEBUG_rsv_e_slv_wready /* synthesis noprune */ ; + reg DEBUG_rsv_e_slv_rvalid /* synthesis noprune */ ; + reg DEBUG_rsv_e_slv_rready /* synthesis noprune */ ; + reg DEBUG_rsv_f_slv_wvalid /* synthesis noprune */ ; + reg DEBUG_rsv_f_slv_wready /* synthesis noprune */ ; + reg DEBUG_rsv_f_slv_rvalid /* synthesis noprune */ ; + reg DEBUG_rsv_f_slv_rready /* synthesis noprune */ ; + + always @ (posedge clk) + begin + DEBUG_st2mm_mst_awaddr <= apf_st2mm_mst_if.awaddr ; + DEBUG_st2mm_mst_awprot <= apf_st2mm_mst_if.awprot ; + DEBUG_st2mm_mst_awvalid <= apf_st2mm_mst_if.awvalid ; + DEBUG_st2mm_mst_awready <= apf_st2mm_mst_if.awready ; + DEBUG_st2mm_mst_araddr <= apf_st2mm_mst_if.araddr ; + DEBUG_st2mm_mst_arprot <= apf_st2mm_mst_if.arprot ; + DEBUG_st2mm_mst_arvalid <= apf_st2mm_mst_if.arvalid ; + DEBUG_st2mm_mst_arready <= apf_st2mm_mst_if.arready ; + DEBUG_st2mm_mst_wstrb <= apf_st2mm_mst_if.wstrb ; + DEBUG_st2mm_mst_wvalid <= apf_st2mm_mst_if.wvalid ; + DEBUG_st2mm_mst_wready <= apf_st2mm_mst_if.wready ; + DEBUG_st2mm_mst_rresp <= apf_st2mm_mst_if.rresp ; + DEBUG_st2mm_mst_rvalid <= apf_st2mm_mst_if.rvalid ; + DEBUG_st2mm_mst_rready <= apf_st2mm_mst_if.rready ; + DEBUG_st2mm_mst_bresp <= apf_st2mm_mst_if.bresp ; + DEBUG_st2mm_mst_bvalid <= apf_st2mm_mst_if.bvalid ; + DEBUG_st2mm_mst_bready <= apf_st2mm_mst_if.bready ; + + DEBUG_st2mm_slv_awaddr <= apf_st2mm_slv_if.awaddr ; + DEBUG_st2mm_slv_awprot <= apf_st2mm_slv_if.awprot ; + DEBUG_st2mm_slv_awvalid <= apf_st2mm_slv_if.awvalid ; + DEBUG_st2mm_slv_awready <= apf_st2mm_slv_if.awready ; + DEBUG_st2mm_slv_araddr <= apf_st2mm_slv_if.araddr ; + DEBUG_st2mm_slv_arprot <= apf_st2mm_slv_if.arprot ; + DEBUG_st2mm_slv_arvalid <= apf_st2mm_slv_if.arvalid ; + DEBUG_st2mm_slv_arready <= apf_st2mm_slv_if.arready ; + DEBUG_st2mm_slv_wstrb <= apf_st2mm_slv_if.wstrb ; + DEBUG_st2mm_slv_wvalid <= apf_st2mm_slv_if.wvalid ; + DEBUG_st2mm_slv_wready <= apf_st2mm_slv_if.wready ; + DEBUG_st2mm_slv_rresp <= apf_st2mm_slv_if.rresp ; + DEBUG_st2mm_slv_rvalid <= apf_st2mm_slv_if.rvalid ; + DEBUG_st2mm_slv_rready <= apf_st2mm_slv_if.rready ; + DEBUG_st2mm_slv_bresp <= apf_st2mm_slv_if.bresp ; + DEBUG_st2mm_slv_bvalid <= apf_st2mm_slv_if.bvalid ; + DEBUG_st2mm_slv_bready <= apf_st2mm_slv_if.bready ; + + DEBUG_bpf_slv_awaddr <= apf_bpf_slv_if.awaddr ; + DEBUG_bpf_slv_awprot <= apf_bpf_slv_if.awprot ; + DEBUG_bpf_slv_awvalid <= apf_bpf_slv_if.awvalid ; + DEBUG_bpf_slv_awready <= apf_bpf_slv_if.awready ; + DEBUG_bpf_slv_araddr <= apf_bpf_slv_if.araddr ; + DEBUG_bpf_slv_arprot <= apf_bpf_slv_if.arprot ; + DEBUG_bpf_slv_arvalid <= apf_bpf_slv_if.arvalid ; + DEBUG_bpf_slv_arready <= apf_bpf_slv_if.arready ; + DEBUG_bpf_slv_wstrb <= apf_bpf_slv_if.wstrb ; + DEBUG_bpf_slv_wvalid <= apf_bpf_slv_if.wvalid ; + DEBUG_bpf_slv_wready <= apf_bpf_slv_if.wready ; + DEBUG_bpf_slv_rresp <= apf_bpf_slv_if.rresp ; + DEBUG_bpf_slv_rvalid <= apf_bpf_slv_if.rvalid ; + DEBUG_bpf_slv_rready <= apf_bpf_slv_if.rready ; + DEBUG_bpf_slv_bresp <= apf_bpf_slv_if.bresp ; + DEBUG_bpf_slv_bvalid <= apf_bpf_slv_if.bvalid ; + DEBUG_bpf_slv_bready <= apf_bpf_slv_if.bready ; + + DEBUG_pgsk_slv_awaddr <= apf_pgsk_slv_if.awaddr ; + DEBUG_pgsk_slv_awprot <= apf_pgsk_slv_if.awprot ; + DEBUG_pgsk_slv_awvalid <= apf_pgsk_slv_if.awvalid ; + DEBUG_pgsk_slv_awready <= apf_pgsk_slv_if.awready ; + DEBUG_pgsk_slv_araddr <= apf_pgsk_slv_if.araddr ; + DEBUG_pgsk_slv_arprot <= apf_pgsk_slv_if.arprot ; + DEBUG_pgsk_slv_arvalid <= apf_pgsk_slv_if.arvalid ; + DEBUG_pgsk_slv_arready <= apf_pgsk_slv_if.arready ; + DEBUG_pgsk_slv_wstrb <= apf_pgsk_slv_if.wstrb ; + DEBUG_pgsk_slv_wvalid <= apf_pgsk_slv_if.wvalid ; + DEBUG_pgsk_slv_wready <= apf_pgsk_slv_if.wready ; + DEBUG_pgsk_slv_rresp <= apf_pgsk_slv_if.rresp ; + DEBUG_pgsk_slv_rvalid <= apf_pgsk_slv_if.rvalid ; + DEBUG_pgsk_slv_rready <= apf_pgsk_slv_if.rready ; + DEBUG_pgsk_slv_bresp <= apf_pgsk_slv_if.bresp ; + DEBUG_pgsk_slv_bvalid <= apf_pgsk_slv_if.bvalid ; + DEBUG_pgsk_slv_bready <= apf_pgsk_slv_if.bready ; + + DEBUG_achk_slv_awaddr <= apf_achk_slv_if.awaddr ; + DEBUG_achk_slv_awprot <= apf_achk_slv_if.awprot ; + DEBUG_achk_slv_awvalid <= apf_achk_slv_if.awvalid ; + DEBUG_achk_slv_awready <= apf_achk_slv_if.awready ; + DEBUG_achk_slv_araddr <= apf_achk_slv_if.araddr ; + DEBUG_achk_slv_arprot <= apf_achk_slv_if.arprot ; + DEBUG_achk_slv_arvalid <= apf_achk_slv_if.arvalid ; + DEBUG_achk_slv_arready <= apf_achk_slv_if.arready ; + DEBUG_achk_slv_wstrb <= apf_achk_slv_if.wstrb ; + DEBUG_achk_slv_wvalid <= apf_achk_slv_if.wvalid ; + DEBUG_achk_slv_wready <= apf_achk_slv_if.wready ; + DEBUG_achk_slv_rresp <= apf_achk_slv_if.rresp ; + DEBUG_achk_slv_rvalid <= apf_achk_slv_if.rvalid ; + DEBUG_achk_slv_rready <= apf_achk_slv_if.rready ; + DEBUG_achk_slv_bresp <= apf_achk_slv_if.bresp ; + DEBUG_achk_slv_bvalid <= apf_achk_slv_if.bvalid ; + DEBUG_achk_slv_bready <= apf_achk_slv_if.bready ; + + DEBUG_rsv_b_slv_wvalid <= apf_rsv_b_slv_if.wvalid ; + DEBUG_rsv_b_slv_wready <= apf_rsv_b_slv_if.wready ; + DEBUG_rsv_b_slv_rvalid <= apf_rsv_b_slv_if.rvalid ; + DEBUG_rsv_b_slv_rready <= apf_rsv_b_slv_if.rready ; + DEBUG_rsv_c_slv_wvalid <= apf_rsv_c_slv_if.wvalid ; + DEBUG_rsv_c_slv_wready <= apf_rsv_c_slv_if.wready ; + DEBUG_rsv_c_slv_rvalid <= apf_rsv_c_slv_if.rvalid ; + DEBUG_rsv_c_slv_rready <= apf_rsv_c_slv_if.rready ; + DEBUG_rsv_d_slv_wvalid <= apf_rsv_d_slv_if.wvalid ; + DEBUG_rsv_d_slv_wready <= apf_rsv_d_slv_if.wready ; + DEBUG_rsv_d_slv_rvalid <= apf_rsv_d_slv_if.rvalid ; + DEBUG_rsv_d_slv_rready <= apf_rsv_d_slv_if.rready ; + DEBUG_rsv_e_slv_wvalid <= apf_rsv_e_slv_if.wvalid ; + DEBUG_rsv_e_slv_wready <= apf_rsv_e_slv_if.wready ; + DEBUG_rsv_e_slv_rvalid <= apf_rsv_e_slv_if.rvalid ; + DEBUG_rsv_e_slv_rready <= apf_rsv_e_slv_if.rready ; + DEBUG_rsv_f_slv_wvalid <= apf_rsv_f_slv_if.wvalid ; + DEBUG_rsv_f_slv_wready <= apf_rsv_f_slv_if.wready ; + DEBUG_rsv_f_slv_rvalid <= apf_rsv_f_slv_if.rvalid ; + DEBUG_rsv_f_slv_rready <= apf_rsv_f_slv_if.rready ; + end + + `endif +endmodule + +module apf_dummy_slv ( + input clk, + ofs_fim_axi_lite_if.slave dummy_slv_if +); + + always_comb + begin + dummy_slv_if.awready = 1; + dummy_slv_if.wready = 1; + dummy_slv_if.bresp = 0; + dummy_slv_if.arready = 1; + dummy_slv_if.rdata = 0; + dummy_slv_if.rresp = 0; + end + + always_ff @ ( posedge clk ) + begin // DUMMY address response + dummy_slv_if.bvalid <= dummy_slv_if.awvalid; + dummy_slv_if.rvalid <= dummy_slv_if.arvalid; + end + +endmodule diff --git a/src/afu_top/mux/top_cfg_pkg.sv b/src/afu_top/mux/top_cfg_pkg.sv new file mode 100755 index 0000000..6753c13 --- /dev/null +++ b/src/afu_top/mux/top_cfg_pkg.sv @@ -0,0 +1,188 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// This package defines the parameters used in top level module +// +//----------------------------------------------------------------------------- +`ifndef __TOP_CFG_PKG_SV__ +`define __TOP_CFG_PKG_SV__ + +`include "fpga_defines.vh" + +package top_cfg_pkg; + +enum { + PCIE_CSR_ID, + SPI_CSR_ID + `ifdef INCLUDE_DDR4 + ,EMIF_CSR_ID + `endif + `ifdef INCLUDE_HSSI + ,HSSI_CSR_ID + `endif + `ifdef INCLUDE_USER_CLOCK + ,USER_CLOCK_CSR_ID + `endif + ,MAX_CSR_ID +} csr_id; + +localparam EXT_CSR_SLAVES = MAX_CSR_ID; +localparam EXT_FME_IRQ_IFS = MAX_CSR_ID; +localparam EXT_PORT0_IRQ_IFS = MAX_CSR_ID; + +// FME CSR memory size in 4KB unit +// The array index follows csr_id enum index, e.g. PCIe CSR is located at index 0 +localparam bit [EXT_CSR_SLAVES-1:0][63:0] EXT_FME_CSR_MEM_SIZE = { + `ifdef INCLUDE_USER_CLOCK + 64'h0, // User Clock FME CSR + `endif + `ifdef INCLUDE_SPI_BRIDGE + 64'h1, // SPI Bridge FME CSR + `endif + `ifdef INCLUDE_HSSI + 64'h1, // HSSI FME CSR + `endif + `ifdef INCLUDE_DDR4 + 64'h1, // EMIF FME CSR + `endif + 64'h1 // PCIe FME CSR (PCIE_CSR_ID = 0) +}; + +// Port CSR memory size in 4KB unit +// The array index follows csr_id enum index, e.g. PCIe CSR is located at index 0 +localparam bit [EXT_CSR_SLAVES-1:0][63:0] EXT_PORT0_CSR_MEM_SIZE = { + `ifdef INCLUDE_USER_CLOCK + 64'h1, // User Clock Port CSR + `endif + `ifdef INCLUDE_SPI_BRIDGE + 64'h0, // SPI Bridge Port CSR + `endif + `ifdef INCLUDE_HSSI + 64'h0, // HSSI Port CSR + `endif + `ifdef INCLUDE_DDR4 + 64'h0, // EMIF Port CSR + `endif + 64'h0 // PCIe Port CSR (PCIE_CSR_ID = 0) +}; + +// CSR slave priority (0/1), 0:higher priority 1:lower priority +// The array index follows csr_id enum index, e.g. PCIe CSR is located at index 0 +localparam bit [EXT_CSR_SLAVES-1:0][63:0] EXT_CSR_PRIORITY = { + `ifdef INCLUDE_USER_CLOCK + 64'h0, // User Clock CSR + `endif + `ifdef INCLUDE_SPI_BRIDGE + 64'h0, // SPI Bridge CSR + `endif + `ifdef INCLUDE_HSSI + 64'h0, // HSSI CSR + `endif + `ifdef INCLUDE_DDR4 + 64'h0, // EMIF CSR + `endif + 64'h0 // PCIe CSR +}; + +//---------------------------------------------------------------------------------//-------------------------------------- +// Simulation Display Message Options // +//---------------------------------------------------------------------------------//-------------------------------------- + `define MUX_MSG // Enable PF/VF_MUX Tracker Message + // `define HE_LB_MSG // Enable HE Loopback Tracker Message + // `define HSSI_MSG // Enable HSSI Tracker Message + // `define PR_MSG // Enable PR Tracker Message +//---------------------------------------------------------------------------------//-------------------------------------- +// FPGA Component Inclusion // +//---------------------------------------------------------------------------------//-------------------------------------- + // `define INCLUDE_HSSI // Instantiate HSSI IP + // `define INCLUDE_DDR4 // Instantiate DDR4 IP + // `define INCLUDE_PCIE // Instantiate PCIE IP + // `define INCLUDE_SPI_BRIDGE // Instantiate SPI Bridge IP + // `define INCLUDE_USER_CLOCK // Instantiate User Clock +//---------------------------------------------------------------------------------//-------------------------------------- +// FPGA Debug Singaltaps // +//---------------------------------------------------------------------------------//-------------------------------------- + `define DEBUG_MUX // Add PF/VF Mux Debug Signals + `define DEBUG_APF // Add APF CSR Debug Signals + // `define DEBUG_BPF // Add BPF CSR Debug Signals + // `define DEBUG_PCIE // Add PCIE Debug Signals + // `define DEBUG_HSSI // Add HSSI Debug Signals + // `define DEBUG_MEM // Add EMIF/MEM Debug Signals +//========================================================================================================================= +// OFS Configuration Parameters +//========================================================================================================================= + parameter NUM_MEM_CH = 4 ,// Number of Memory/DDR Channel + NUM_HOST = 1 ,// Number of Host/Upstream Ports + NUM_PORT = 4 ,// Number of Functions/Downstream Ports + DATA_WIDTH = 512 ,// Data Width of Interface + TOTAL_BAR_SIZE = 20 ,// Total Space for APF/BPF BARs (2^N) + //------------+-------------+-------------+-----------------+ //-------------------------------------- + // VF Active | PF # | VF # | Mux Port Map | // PF/VF Mapping Parameters + //------------+-------------+-------------+-----------------+ //-------------------------------------- + CFG_VA = 0 , CFG_PF = 0 , CFG_VF = 0 , CFG_PID = 3 , // Configuration Register Block + HLB_VA = 1 , HLB_PF = 0 , HLB_VF = 0 , HLB_PID = 0 , // HE Loopback Engine + PRG_VA = 1 , PRG_PF = 0 , PRG_VF = 1 , PRG_PID = 1 , // Partial Reconfiguration Gasket + HSI_VA = 1 , HSI_PF = 0 , HSI_VF = 2 , HSI_PID = 2 ; // HSSI interface + +//========================================================================================================================= +// PF/VF Mux Routing Table +//========================================================================================================================= + +localparam NUM_RTABLE_ENTRIES = 5; +localparam pf_vf_mux_pkg::t_pfvf_rtable_entry PFVF_ROUTING_TABLE[NUM_RTABLE_ENTRIES] = '{ + '{ pfvf_port:HLB_PID, pf:HLB_PF, vf:HLB_VF, vf_active:HLB_VA }, + '{ pfvf_port:PRG_PID, pf:PRG_PF, vf:PRG_VF, vf_active:PRG_VA }, + '{ pfvf_port:HSI_PID, pf:HSI_PF, vf:HSI_VF, vf_active:HSI_VA }, + '{ pfvf_port:CFG_PID, pf:-1, vf:-1, vf_active:0 }, + '{ pfvf_port:CFG_PID, pf:-1, vf:-1, vf_active:1 } + }; + + +localparam NID_WIDTH = $clog2(NUM_PORT) ,// ID field width for targeting mux ports + MID_WIDTH = $clog2(NUM_HOST) ;// ID field width for targeting host ports + + //-------------------------------+----------------------------+ //====================================== + // Device CSR BAR Base Address | Device CSR BAR Size (2^N) | // APF/BPF BAR Base Address & Size + //-------------------------------+----------------------------+ //======================================= + parameter FME_BASE = 'h000000 , FME_SIZE = 16 , // FME BAR + PMCI_BASE = 'h010000 , PMCI_SIZE = 16 , // PMCI BAR + PCIE_BASE = 'h020000 , PCIE_SIZE = 16 , // PCIE BAR + HSSI_BASE = 'h030000 , HSSI_SIZE = 16 , // HSSI BAR + EMIF_BASE = 'h040000 , EMIF_SIZE = 16 , // EMIF BAR + RSV_5_BASE = 'h050000 , RSV_5_SIZE = 16 , // RSV_5 Reserved Space + RSV_6_BASE = 'h060000 , RSV_6_SIZE = 16 , // RSV_6 Reserved Space + RSV_7_BASE = 'h070000 , RSV_7_SIZE = 16 , // RSV_7 Reserved Space + ST2MM_BASE = 'h080000 , ST2MM_SIZE = 16 , // RST2MM BAR + PGSK_BASE = 'h090000 , PGSK_SIZE = 16 , // PR Gasket BAR + ACHK_BASE = 'h0a0000 , ACHK_SIZE = 16 , // AFU Checker BAR + RSV_b_BASE = 'h0b0000 , RSV_b_SIZE = 16 , // RSV_b Reserved Space + RSV_c_BASE = 'h0c0000 , RSV_c_SIZE = 16 , // RSV_c Reserved Space + RSV_d_BASE = 'h0d0000 , RSV_d_SIZE = 16 , // RSV_d Reserved Space + RSV_e_BASE = 'h0e0000 , RSV_e_SIZE = 16 , // RSV_e Reserved Space + RSV_f_BASE = 'h0f0000 , RSV_f_SIZE = 16 ; // RSV_f Reserved Space + + + // + // A subset of the multiplexed PF/VF ports are passed through the port + // gasket to afu_main(). The following arrays indicate the PF/VF numbers + // associated with an equal-sized array of AXI TLP interfaces passed + // to afu_main(). + // + + // Number of PCIe ports passed to afu_main() + localparam PG_AFU_NUM_PORTS = 2; + + // Mux port ID of each AFU port (index 0 on the left) + localparam int PG_AFU_MUX_PID[PG_AFU_NUM_PORTS] = '{ PRG_PID, HSI_PID }; + + // PF/VF mapping for each port + localparam logic [10:0] PG_AFU_PORTS_VF_NUM[PG_AFU_NUM_PORTS] = '{ PRG_VF, HSI_VF }; + localparam logic PG_AFU_PORTS_VF_ACTIVE[PG_AFU_NUM_PORTS] = '{ PRG_VA, HSI_VA }; + localparam logic [2:0] PG_AFU_PORTS_PF_NUM[PG_AFU_NUM_PORTS] = '{ PRG_PF, HSI_PF }; + +endpackage : top_cfg_pkg + +`endif // __TOP_CFG_PKG_SV__ diff --git a/src/includes/fpga_defines.vh b/src/includes/fpga_defines.vh new file mode 100644 index 0000000..90c1f4b --- /dev/null +++ b/src/includes/fpga_defines.vh @@ -0,0 +1,29 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +`ifndef fpga_defines +`define fpga_defines + + //-------------------------------------------------------------------- + // Technology + //-------------------------------------------------------------------- + `define FAMILY "Stratix 10" // Targeted Device Family + `define DEVICE_FAMILY_IS_S10 + `define HTILE + `define INCLUDE_MSIX + `define INCLUDE_REMOTE_STP + + //-------------------------------------------------------------------- + // HEs + //-------------------------------------------------------------------- + `define INCLUDE_HSSI + `define INCLUDE_HE_HSSI + + //-------------------------------------------------------------------- + // Simulation + //-------------------------------------------------------------------- + `define CYCLE_MSG // TX/RX Messages on host AXI-ST Interface + //`define R1_UNIT_TEST_ENV // Temporary define needed for unit level tests + // with Intel BFM. Deals with a diff in + // completer ID field in axi_s_adapter. +`endif diff --git a/src/includes/ofs_fim_cfg_pkg.sv b/src/includes/ofs_fim_cfg_pkg.sv new file mode 100755 index 0000000..7a6259a --- /dev/null +++ b/src/includes/ofs_fim_cfg_pkg.sv @@ -0,0 +1,103 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// This package defines the global parameters of CoreFIM +// +//---------------------------------------------------------------------------- +`ifndef __OFS_FIM_CFG_PKG_SV__ +`define __OFS_FIM_CFG_PKG_SV__ + +package ofs_fim_cfg_pkg; + +localparam PORTS = 1; + +//***************** +// PCIe host parameters +//***************** +localparam NUM_PCIE_HOST = 1; +localparam PCIE_HOST_WIDTH = $clog2(NUM_PCIE_HOST); + +localparam PCIE_RP_MAX_TAGS = 64; +localparam PCIE_RP_TAG_WIDTH = $clog2(PCIE_RP_MAX_TAGS); + +localparam PCIE_TDATA_WIDTH = 512; +localparam PCIE_TUSER_WIDTH = 10; + +localparam FIM_NUM_PF = 2; +localparam FIM_NUM_VF = 4; +localparam FIM_PF_WIDTH = (FIM_NUM_PF < 2) ? 1 : $clog2(FIM_NUM_PF); +localparam FIM_VF_WIDTH = (FIM_NUM_VF < 2) ? 1 : $clog2(FIM_NUM_VF); + +localparam FIM_NUM_MMIO_BAR = 1; // FME, Port + +localparam MAX_PAYLOAD_SIZE = 64; +localparam MAX_RD_REQ_SIZE = 64; + +//***************** +// MMIO parameters +//***************** +localparam MMIO_TID_WIDTH = PCIE_HOST_WIDTH + PCIE_RP_TAG_WIDTH; // Matches PCIe TLP tag width +localparam MMIO_DATA_WIDTH = 64; + +localparam MMIO_REGION_WIDTH = $clog2(FIM_NUM_MMIO_BAR); // Number of bits to encode MMIO region (e.g. FME, Port) +localparam FEAT_ADDR_WIDTH = 20; // Feature address width for MMIO region +localparam MMIO_ADDR_WIDTH = MMIO_REGION_WIDTH + FEAT_ADDR_WIDTH; // Full MMIO address width + +localparam FME_FEAT_ADDR_WIDTH = 20; // Feature address width for FME MMIO region +localparam VFME_FEAT_ADDR_WIDTH = 14; // Feature address width for VFME MMIO region +localparam PORT_FEAT_ADDR_WIDTH = 19; // Feature address width for Port MMIO region (not including AFU) + +localparam FEAT_REGION_UNIT_WIDTH = 12; // 4KB block unit +localparam FEAT_REGION_ADDR_START = 12; // 4KB block unit +localparam FEAT_REGION_WIDTH = FEAT_ADDR_WIDTH - FEAT_REGION_UNIT_WIDTH; // Number of bits to address 4KB feature region within a MMIO region +localparam VFME_FEAT_REGION_WIDTH = VFME_FEAT_ADDR_WIDTH - FEAT_REGION_UNIT_WIDTH; // Number of bits to address 4KB feature region within vFME MMIO region + + +// CSR region +enum logic [MMIO_REGION_WIDTH-1:0] { + FME_MMIO_REGION, + PORT_MMIO_REGION +} e_mmio_region; + +// CoreFIM FME address range (0x0 - 0x3FFFF) +localparam FME_FEAT_REGION_START = 'h0; +//External FME address range (0x40000 - 0x7FFFF) +localparam EXT_FME_FEAT_REGION_START = 'h40; + +// Address range: CoreFIM Port0 (0x0 - 0x1FFFF), External Port0 (0x20000 - 0x3FFFF) +localparam PORT_FEAT_REGION_START = 'h0; +localparam EXT_PORT_FEAT_REGION_START = 'h20; + +// Address range: AFU (Port 0) (0x40000 - 0xBFFFF) +localparam AFU_FEAT_REGION_START = 'h40; + +// FME and Port function number +localparam FME_PF_NUM = 3'd0; +localparam VFME_VF_NUM = 13'd0; +localparam bit [PORTS-1:0][2:0] PORT_PF_NUM = {3'd0}; +localparam bit [PORTS-1:0][2:0] PORT_VF_NUM = {3'd0}; + +// FME and Port function BAR +localparam FME_PF_BAR = 3'd0; // BAR 0 +localparam VFME_BAR = 3'd4; // BAR 4 +localparam bit [PORTS-1:0][2:0] PORT_PF_BAR = {3'd2}; +localparam bit [PORTS-1:0][2:0] PORT_VF_BAR = {3'd0}; + + +//MSIX +`ifdef NUM_AFUS +localparam NUM_AFUS = 2; +`else +localparam NUM_AFUS = 1; +`endif +localparam LNUM_AFUS = NUM_AFUS>1?$clog2(NUM_AFUS):1'h1; +localparam NUM_AFU_INTERRUPTS = 7; +localparam L_NUM_AFU_INTERRUPTS = $clog2(NUM_AFU_INTERRUPTS); + + +endpackage + +`endif // __OFS_FIM_CFG_PKG_SV__ diff --git a/src/includes/ofs_pcie_ss_plat_cfg.vh b/src/includes/ofs_pcie_ss_plat_cfg.vh new file mode 100644 index 0000000..f924434 --- /dev/null +++ b/src/includes/ofs_pcie_ss_plat_cfg.vh @@ -0,0 +1,19 @@ +// Copyright 2021 Intel Corporation +// SPDX-License-Identifier: MIT + +// +// Platform-specific OFS R1 configuration of the PCIe subsystem. +// +// This file exists mainly to associate a version tag with the values in +// ofs_pcie_ss_plat_cfg_pkg::. The version tag makes it easier to manage +// varation among platforms when importing the platform-specific configuration +// into the platform-independent ofs_pcie_ss_cfg_pkg::. +// + +`ifndef __OFS_PCIE_SS_PLAT_CFG_VH__ +`define __OFS_PCIE_SS_PLAT_CFG_VH__ 1 + +`define OFS_PCIE_SS_PLAT_CFG_R1 1 +`define OFS_PCIE_SS_PLAT_CFG_V1 1 + +`endif // __OFS_PCIE_SS_PLAT_CFG_VH__ diff --git a/src/includes/ofs_pcie_ss_plat_cfg_pkg.sv b/src/includes/ofs_pcie_ss_plat_cfg_pkg.sv new file mode 100644 index 0000000..35ce0e4 --- /dev/null +++ b/src/includes/ofs_pcie_ss_plat_cfg_pkg.sv @@ -0,0 +1,40 @@ +// Copyright 2021 Intel Corporation +// SPDX-License-Identifier: MIT + + +// +// Platform-specific OFS R1 configuration of the PCIe subsystem. +// +// This is the platform-specific PCIe configuration package. It is imported +// by the platform-independent ofs_pcie_ss_cfg_pkg::. +// +// In general, code SHOULD NOT import this file. Instead, import +// ofs_pcie_ss_cfg_pkg::, which imports this file and enforces a common +// configuration across all platforms. +// + +`include "ofs_pcie_ss_plat_cfg.vh" + +package ofs_pcie_ss_plat_cfg_pkg; + + // + // Descriptions of these fields can be found in the platform-independent + // parent: ofs_pcie_ss_cfg_pkg.sv + // + + localparam TDATA_WIDTH = ofs_fim_cfg_pkg::PCIE_TDATA_WIDTH; + localparam TUSER_VENDOR_WIDTH = ofs_fim_cfg_pkg::PCIE_TUSER_WIDTH; + + localparam MAX_RD_REQ_BYTES = ofs_fim_cfg_pkg::MAX_RD_REQ_SIZE * 4; + localparam MAX_WR_PAYLOAD_BYTES = ofs_fim_cfg_pkg::MAX_PAYLOAD_SIZE * 4; + + localparam NUM_OF_SOP = 1; + localparam NUM_OF_SEG = 1; + + localparam PCIE_EP_MAX_TAGS = 128; + localparam PCIE_RP_MAX_TAGS = ofs_fim_cfg_pkg::PCIE_RP_MAX_TAGS; + localparam PCIE_TILE_MAX_TAGS = 128; + + localparam NUM_OF_STREAMS = 1; + +endpackage // ofs_pcie_ss_plat_cfg_pkg diff --git a/src/interrupt/fme_msix_table.sv b/src/interrupt/fme_msix_table.sv new file mode 100755 index 0000000..72fded5 --- /dev/null +++ b/src/interrupt/fme_msix_table.sv @@ -0,0 +1,132 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// FME_MSIX_TABLE +// *Implments the MSI-X entry look up table for PF MSI-X inputs and implments the +// vfme_csr for VF interrupts. +// *Also implments the sclr for FME RW1C and negedge detection for FME RO regs +//----------------------------------------------------------------------------- +import ofs_fim_if_pkg::*; +import ofs_fim_cfg_pkg::*; +import ofs_fim_pcie_hdr_def::*; + +module fme_msix_table ( + input clk, + input rst_n, + // dcp Interrupt signals + input i_intr_valid, + input [L_NUM_AFU_INTERRUPTS-1:0] i_intr_id, + input i_vintr_valid, + input [L_NUM_AFU_INTERRUPTS-1:0] i_vintr_id, + + output logic [95:0] o_msix_table_entry, + output logic o_intr_val, + output logic [L_NUM_AFU_INTERRUPTS:0] o_intr_id, + + output [NUM_AFU_INTERRUPTS -1:0] pf_mask_vector, + output [NUM_AFU_INTERRUPTS -3:0] vf_mask_vector, + // MSIX Table Entries + input logic [63:0] cr2out_msix_addr0, + input logic [63:0] cr2out_msix_addr1, + input logic [63:0] cr2out_msix_addr2, + input logic [63:0] cr2out_msix_addr3, + input logic [63:0] cr2out_msix_addr4, + input logic [63:0] cr2out_msix_addr5, + input logic [63:0] cr2out_msix_addr6, + input logic [63:0] cr2out_msix_addr7, + input logic [63:0] cr2out_msix_ctldat0, + input logic [63:0] cr2out_msix_ctldat1, + input logic [63:0] cr2out_msix_ctldat2, + input logic [63:0] cr2out_msix_ctldat3, + input logic [63:0] cr2out_msix_ctldat4, + input logic [63:0] cr2out_msix_ctldat5, + input logic [63:0] cr2out_msix_ctldat6, + input logic [63:0] cr2out_msix_ctldat7, + // MSIX Virtual FME Signals + input logic [63:0] cr2out_msix_vaddr0, + input logic [63:0] cr2out_msix_vaddr1, + input logic [63:0] cr2out_msix_vaddr2, + input logic [63:0] cr2out_msix_vaddr3, + input logic [63:0] cr2out_msix_vaddr4, + input logic [63:0] cr2out_msix_vctldat0, + input logic [63:0] cr2out_msix_vctldat1, + input logic [63:0] cr2out_msix_vctldat2, + input logic [63:0] cr2out_msix_vctldat3, + input logic [63:0] cr2out_msix_vctldat4 +); + + logic [95:0] o_msix_vtable_entry, o_msix_ptable_entry; + logic i_intr_valid_sync, i_vintr_valid_sync; + logic [L_NUM_AFU_INTERRUPTS-1:0] i_intr_id_sync, i_vintr_id_sync; + logic vf_id_sel; + + //----------------------------------------------------------------------------- + // MSI-X data selection + //----------------------------------------------------------------------------- + //dcp:msix + always @(posedge clk) begin + if (!rst_n) begin + i_intr_valid_sync <= 0; + i_intr_id_sync <= 0; + o_msix_ptable_entry <= 96'd0; + end else begin + case(i_intr_id) + 3'd0: o_msix_ptable_entry <= {cr2out_msix_ctldat0[31:0], cr2out_msix_addr0}; // afu - intr0 + 3'd1: o_msix_ptable_entry <= {cr2out_msix_ctldat1[31:0], cr2out_msix_addr1}; // afu - intr1 + 3'd2: o_msix_ptable_entry <= {cr2out_msix_ctldat2[31:0], cr2out_msix_addr2}; // afu - intr2 + 3'd3: o_msix_ptable_entry <= {cr2out_msix_ctldat3[31:0], cr2out_msix_addr3}; // afu - intr3 + 3'd4: o_msix_ptable_entry <= {cr2out_msix_ctldat4[31:0], cr2out_msix_addr4}; // port- intr4 + 3'd6: o_msix_ptable_entry <= {cr2out_msix_ctldat6[31:0], cr2out_msix_addr6}; // FME - intr6 + default: o_msix_ptable_entry <= 96'd0; + endcase + i_intr_valid_sync <= i_intr_valid; + i_intr_id_sync <= i_intr_id; + end + end + + always @(posedge clk) begin + if (!rst_n) begin + vf_id_sel <= 0; + o_intr_id <= 0; + o_intr_val <= 0; + o_msix_table_entry <= 0; + end else begin + vf_id_sel <= i_intr_valid && (i_intr_id !='h6); + o_intr_id <= {vf_id_sel, vf_id_sel ? i_vintr_id_sync : i_intr_id_sync}; + o_intr_val <= i_intr_valid_sync | i_vintr_valid_sync; + o_msix_table_entry <= (i_vintr_valid_sync && (i_intr_id_sync !='h6)) ? o_msix_vtable_entry : o_msix_ptable_entry; + end + end + + assign pf_mask_vector = { cr2out_msix_ctldat6[32], + cr2out_msix_ctldat5[32], + cr2out_msix_ctldat4[32], + cr2out_msix_ctldat3[32], + cr2out_msix_ctldat2[32], + cr2out_msix_ctldat1[32], + cr2out_msix_ctldat0[32] + }; + + + assign vf_mask_vector = { cr2out_msix_vctldat4[32], + cr2out_msix_vctldat3[32], + cr2out_msix_vctldat2[32], + cr2out_msix_vctldat1[32], + cr2out_msix_vctldat0[32] + }; + always_ff @(posedge clk) begin + case(i_vintr_id) + 3'd0: o_msix_vtable_entry <= {cr2out_msix_vctldat0[31:0], cr2out_msix_vaddr0}; // afu - intr0 + 3'd1: o_msix_vtable_entry <= {cr2out_msix_vctldat1[31:0], cr2out_msix_vaddr1}; // afu - intr1 + 3'd2: o_msix_vtable_entry <= {cr2out_msix_vctldat2[31:0], cr2out_msix_vaddr2}; // afu - intr2 + 3'd3: o_msix_vtable_entry <= {cr2out_msix_vctldat3[31:0], cr2out_msix_vaddr3}; // afu - intr3 + 3'd4: o_msix_vtable_entry <= {cr2out_msix_vctldat4[31:0], cr2out_msix_vaddr4}; // port- intr4 + default:o_msix_vtable_entry <= 96'd0; + endcase + i_vintr_valid_sync <= i_vintr_valid; + i_vintr_id_sync <= i_vintr_id; + end +endmodule diff --git a/src/interrupt/msix_csr.sv b/src/interrupt/msix_csr.sv new file mode 100755 index 0000000..ad47e7b --- /dev/null +++ b/src/interrupt/msix_csr.sv @@ -0,0 +1,496 @@ +// Copyright 2021 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// MSIX Table + PBA +//----------------------------------------------------------------------------- + + + +module msix_csr #( + parameter MM_ADDR_WIDTH = 20, + parameter MM_DATA_WIDTH = 64 +)( + input clk, + input rst_n, + + input logic avmm_m2s_write, + input logic avmm_m2s_read, + input logic [MM_ADDR_WIDTH-1:0] avmm_m2s_address, + input logic [MM_DATA_WIDTH-1:0] avmm_m2s_writedata, + input logic [(MM_DATA_WIDTH>>3)-1:0] avmm_m2s_byteenable, + + output logic avmm_s2m_waitrequest, + output logic avmm_s2m_writeresponsevalid, + output logic avmm_s2m_readdatavalid, + output logic [MM_DATA_WIDTH-1:0] avmm_s2m_readdata, + + input logic [6:0] inp2cr_msix_pba, + input logic [31:0] inp2cr_msix_count_vector, + + output logic [63:0] cr2out_msix_addr0, + output logic [63:0] cr2out_msix_addr1, + output logic [63:0] cr2out_msix_addr2, + output logic [63:0] cr2out_msix_addr3, + output logic [63:0] cr2out_msix_addr4, + output logic [63:0] cr2out_msix_addr5, + output logic [63:0] cr2out_msix_addr6, + output logic [63:0] cr2out_msix_addr7, + output logic [63:0] cr2out_msix_ctldat0, + output logic [63:0] cr2out_msix_ctldat1, + output logic [63:0] cr2out_msix_ctldat2, + output logic [63:0] cr2out_msix_ctldat3, + output logic [63:0] cr2out_msix_ctldat4, + output logic [63:0] cr2out_msix_ctldat5, + output logic [63:0] cr2out_msix_ctldat6, + output logic [63:0] cr2out_msix_ctldat7, + output logic [63:0] cr2out_msix_pba +); +import ofs_fim_cfg_pkg::*; +import ofs_fim_if_pkg::*; +import ofs_csr_pkg::*; +import fme_csr_pkg::*; +//---------------------------------------------------------------------------- +// Local parameters. +//---------------------------------------------------------------------------- +localparam CSR_FEATURE_NUM = 2; +localparam CSR_FEATURE_REG_NUM = 23; + +localparam MSIX_ADDR0 = 20'h0_3000; +localparam MSIX_CTLDAT0 = 20'h0_3008; +localparam MSIX_ADDR1 = 20'h0_3010; +localparam MSIX_CTLDAT1 = 20'h0_3018; +localparam MSIX_ADDR2 = 20'h0_3020; +localparam MSIX_CTLDAT2 = 20'h0_3028; +localparam MSIX_ADDR3 = 20'h0_3030; +localparam MSIX_CTLDAT3 = 20'h0_3038; +localparam MSIX_ADDR4 = 20'h0_3040; +localparam MSIX_CTLDAT4 = 20'h0_3048; +localparam MSIX_ADDR5 = 20'h0_3050; +localparam MSIX_CTLDAT5 = 20'h0_3058; +localparam MSIX_ADDR6 = 20'h0_3060; +localparam MSIX_CTLDAT6 = 20'h0_3068; +localparam MSIX_ADDR7 = 20'h0_3070; +localparam MSIX_CTLDAT7 = 20'h0_3078; +localparam MSIX_PBA = 20'h0_2000; +localparam MSIX_COUNT_CSR = 20'h0_2008; + +//---------------------------------------------------------------------------- +// SIGNAL DEFINITIONS +//---------------------------------------------------------------------------- +ofs_csr_hw_state_t hw_state; // Hardware state during CSR updates +csr_access_type_t write_type, write_type_reg; + +logic [CSR_REG_WIDTH-1:0] data_reg; +logic write_reg; + +//---------------------------------------------------------------------------- +// CSR registers are implemented in a two dimensional array according to the +// features and the number of registers per feature. This allows the most +// flexibility addressing the registers as well as using the least resources. +//---------------------------------------------------------------------------- +//....[63:0 packed width].....reg[10:0 - #Features ][22:0 - #Regs in Feature] <<= Unpacked dimensions. +logic [CSR_REG_WIDTH-1:0] csr_reg[CSR_FEATURE_NUM-1:0][CSR_FEATURE_REG_NUM-1:0]; // CSR Registers +logic csr_write[CSR_FEATURE_NUM-1:0][CSR_FEATURE_REG_NUM-1:0]; // Arrayed like the CSR registers + +//--------------------------------------------------------------------------------- +// Define the register bit attributes for each of the CSRs +//--------------------------------------------------------------------------------- +fme_csr_msix_addr_attr_t msix_addr0_attr; +assign msix_addr0_attr.msix_addr.msg_addr_upp = {32{RW}}; +assign msix_addr0_attr.msix_addr.msg_addr_low = {32{RW}}; +fme_csr_msix_ctldat_attr_t msix_ctldat0_attr; +assign msix_ctldat0_attr.msix_ctldat.msg_control = {32{RW}}; +assign msix_ctldat0_attr.msix_ctldat.msg_data = {32{RW}}; +fme_csr_msix_addr_attr_t msix_addr1_attr; +assign msix_addr1_attr.msix_addr.msg_addr_upp = {32{RW}}; +assign msix_addr1_attr.msix_addr.msg_addr_low = {32{RW}}; +fme_csr_msix_ctldat_attr_t msix_ctldat1_attr; +assign msix_ctldat1_attr.msix_ctldat.msg_control = {32{RW}}; +assign msix_ctldat1_attr.msix_ctldat.msg_data = {32{RW}}; +fme_csr_msix_addr_attr_t msix_addr2_attr; +assign msix_addr2_attr.msix_addr.msg_addr_upp = {32{RW}}; +assign msix_addr2_attr.msix_addr.msg_addr_low = {32{RW}}; +fme_csr_msix_ctldat_attr_t msix_ctldat2_attr; +assign msix_ctldat2_attr.msix_ctldat.msg_control = {32{RW}}; +assign msix_ctldat2_attr.msix_ctldat.msg_data = {32{RW}}; +fme_csr_msix_addr_attr_t msix_addr3_attr; +assign msix_addr3_attr.msix_addr.msg_addr_upp = {32{RW}}; +assign msix_addr3_attr.msix_addr.msg_addr_low = {32{RW}}; +fme_csr_msix_ctldat_attr_t msix_ctldat3_attr; +assign msix_ctldat3_attr.msix_ctldat.msg_control = {32{RW}}; +assign msix_ctldat3_attr.msix_ctldat.msg_data = {32{RW}}; +fme_csr_msix_addr_attr_t msix_addr4_attr; +assign msix_addr4_attr.msix_addr.msg_addr_upp = {32{RW}}; +assign msix_addr4_attr.msix_addr.msg_addr_low = {32{RW}}; +fme_csr_msix_ctldat_attr_t msix_ctldat4_attr; +assign msix_ctldat4_attr.msix_ctldat.msg_control = {32{RW}}; +assign msix_ctldat4_attr.msix_ctldat.msg_data = {32{RW}}; +fme_csr_msix_addr_attr_t msix_addr5_attr; +assign msix_addr5_attr.msix_addr.msg_addr_upp = {32{RW}}; +assign msix_addr5_attr.msix_addr.msg_addr_low = {32{RW}}; +fme_csr_msix_ctldat_attr_t msix_ctldat5_attr; +assign msix_ctldat5_attr.msix_ctldat.msg_control = {32{RW}}; +assign msix_ctldat5_attr.msix_ctldat.msg_data = {32{RW}}; +fme_csr_msix_addr_attr_t msix_addr6_attr; +assign msix_addr6_attr.msix_addr.msg_addr_upp = {32{RW}}; +assign msix_addr6_attr.msix_addr.msg_addr_low = {32{RW}}; +fme_csr_msix_ctldat_attr_t msix_ctldat6_attr; +assign msix_ctldat6_attr.msix_ctldat.msg_control = {32{RW}}; +assign msix_ctldat6_attr.msix_ctldat.msg_data = {32{RW}}; +fme_csr_msix_addr_attr_t msix_addr7_attr; +assign msix_addr7_attr.msix_addr.msg_addr_upp = {32{RW}}; +assign msix_addr7_attr.msix_addr.msg_addr_low = {32{RW}}; +fme_csr_msix_ctldat_attr_t msix_ctldat7_attr; +assign msix_ctldat7_attr.msix_ctldat.msg_control = {32{RW}}; +assign msix_ctldat7_attr.msix_ctldat.msg_data = {32{RW}}; +fme_csr_msix_pba_attr_t msix_pba_attr; +assign msix_pba_attr.msix_pba.reserved7 = {57{RsvdZ}}; +assign msix_pba_attr.msix_pba.msix_pba = {7{RO}}; +fme_csr_msix_count_csr_attr_t msix_count_csr_attr; +assign msix_count_csr_attr.msix_count_csr.reserved32 = {32{RsvdZ}}; +assign msix_count_csr_attr.msix_count_csr.afu_2_sync_fifo_msix_count = {8{RO}}; +assign msix_count_csr_attr.msix_count_csr.sync_fifo_2_msix_count = {8{RO}}; +assign msix_count_csr_attr.msix_count_csr.msix_2_cdc_msix_count = {8{RO}}; +assign msix_count_csr_attr.msix_count_csr.cdc_2_avl_msix_count = {8{RO}}; + +//---------------------------------------------------------------------------- +// Assignment/Update Overlays: +// These structure overlays help map out the fields for the status register +// "update" inputs used by the function "update_reg" to determine the +// next values stored in the FME status CSRs. +//---------------------------------------------------------------------------- +fme_csr_msix_addr_t fme_csr_msix_addr0_reset, fme_csr_msix_addr0_update, fme_csr_msix_addr1_reset, fme_csr_msix_addr1_update, fme_csr_msix_addr2_reset, fme_csr_msix_addr2_update, fme_csr_msix_addr3_reset, fme_csr_msix_addr3_update, fme_csr_msix_addr4_reset, fme_csr_msix_addr4_update, fme_csr_msix_addr5_reset, fme_csr_msix_addr5_update, fme_csr_msix_addr6_reset, fme_csr_msix_addr6_update, fme_csr_msix_addr7_reset, fme_csr_msix_addr7_update; +fme_csr_msix_ctldat_t fme_csr_msix_ctldat0_reset, fme_csr_msix_ctldat0_update, fme_csr_msix_ctldat1_reset, fme_csr_msix_ctldat1_update, fme_csr_msix_ctldat2_reset, fme_csr_msix_ctldat2_update, fme_csr_msix_ctldat3_reset, fme_csr_msix_ctldat3_update, fme_csr_msix_ctldat4_reset, fme_csr_msix_ctldat4_update, fme_csr_msix_ctldat5_reset, fme_csr_msix_ctldat5_update, fme_csr_msix_ctldat6_reset, fme_csr_msix_ctldat6_update, fme_csr_msix_ctldat7_reset, fme_csr_msix_ctldat7_update; +fme_csr_msix_pba_t fme_csr_msix_pba_reset, fme_csr_msix_pba_update; +fme_csr_msix_count_csr_t fme_csr_msix_count_csr_reset, fme_csr_msix_count_csr_update; + +//---------------------------------------------------------------------------- +// Breakout Overlays: +// These structure overlays Help break out the CSR control register +// outputs to their destinations. +//---------------------------------------------------------------------------- +fme_csr_msix_addr_t fme_csr_msix_addr0, fme_csr_msix_addr1, fme_csr_msix_addr2, fme_csr_msix_addr3, fme_csr_msix_addr4, fme_csr_msix_addr5, fme_csr_msix_addr6, fme_csr_msix_addr7; +fme_csr_msix_ctldat_t fme_csr_msix_ctldat0, fme_csr_msix_ctldat1, fme_csr_msix_ctldat2, fme_csr_msix_ctldat3, fme_csr_msix_ctldat4, fme_csr_msix_ctldat5, fme_csr_msix_ctldat6, fme_csr_msix_ctldat7; +fme_csr_msix_pba_t fme_csr_msix_pba; + +//---------------------------------------------------------------------------- +// Register Reset/Update Structure Overlays. +//---------------------------------------------------------------------------- +assign fme_csr_msix_addr0_reset.data = 64'h0000_0000_0000_0000; +assign fme_csr_msix_addr0_update.data = 64'h0000_0000_0000_0000; +assign fme_csr_msix_addr1_reset.data = 64'h0000_0000_0000_0000; +assign fme_csr_msix_addr1_update.data = 64'h0000_0000_0000_0000; +assign fme_csr_msix_addr2_reset.data = 64'h0000_0000_0000_0000; +assign fme_csr_msix_addr2_update.data = 64'h0000_0000_0000_0000; +assign fme_csr_msix_addr3_reset.data = 64'h0000_0000_0000_0000; +assign fme_csr_msix_addr3_update.data = 64'h0000_0000_0000_0000; +assign fme_csr_msix_addr4_reset.data = 64'h0000_0000_0000_0000; +assign fme_csr_msix_addr4_update.data = 64'h0000_0000_0000_0000; +assign fme_csr_msix_addr5_reset.data = 64'h0000_0000_0000_0000; +assign fme_csr_msix_addr5_update.data = 64'h0000_0000_0000_0000; +assign fme_csr_msix_addr6_reset.data = 64'h0000_0000_0000_0000; +assign fme_csr_msix_addr6_update.data = 64'h0000_0000_0000_0000; +assign fme_csr_msix_addr7_reset.data = 64'h0000_0000_0000_0000; +assign fme_csr_msix_addr7_update.data = 64'h0000_0000_0000_0000; +assign fme_csr_msix_ctldat0_reset.data = 64'h0000_0001_0000_0000; +assign fme_csr_msix_ctldat0_update.data = 64'h0000_0001_0000_0000; +assign fme_csr_msix_ctldat1_reset.data = 64'h0000_0001_0000_0000; +assign fme_csr_msix_ctldat1_update.data = 64'h0000_0001_0000_0000; +assign fme_csr_msix_ctldat2_reset.data = 64'h0000_0001_0000_0000; +assign fme_csr_msix_ctldat2_update.data = 64'h0000_0001_0000_0000; +assign fme_csr_msix_ctldat3_reset.data = 64'h0000_0001_0000_0000; +assign fme_csr_msix_ctldat3_update.data = 64'h0000_0001_0000_0000; +assign fme_csr_msix_ctldat4_reset.data = 64'h0000_0001_0000_0000; +assign fme_csr_msix_ctldat4_update.data = 64'h0000_0001_0000_0000; +assign fme_csr_msix_ctldat5_reset.data = 64'h0000_0001_0000_0000; +assign fme_csr_msix_ctldat5_update.data = 64'h0000_0001_0000_0000; +assign fme_csr_msix_ctldat6_reset.data = 64'h0000_0001_0000_0000; +assign fme_csr_msix_ctldat6_update.data = 64'h0000_0001_0000_0000; +assign fme_csr_msix_ctldat7_reset.data = 64'h0000_0001_0000_0000; +assign fme_csr_msix_ctldat7_update.data = 64'h0000_0001_0000_0000; +assign fme_csr_msix_pba_reset.data = fme_csr_msix_pba_update.data; +assign fme_csr_msix_pba_update.msix_pba.reserved7 = {57{1'b0}}; +assign fme_csr_msix_pba_update.msix_pba.msix_pba = inp2cr_msix_pba[6:0]; +assign fme_csr_msix_count_csr_reset.data = fme_csr_msix_count_csr_update.data; +assign fme_csr_msix_count_csr_update.msix_count_csr.reserved32 = {32{1'b0}}; +assign fme_csr_msix_count_csr_update.msix_count_csr.afu_2_sync_fifo_msix_count = inp2cr_msix_count_vector[31:24]; +assign fme_csr_msix_count_csr_update.msix_count_csr.sync_fifo_2_msix_count = inp2cr_msix_count_vector[23:16]; +assign fme_csr_msix_count_csr_update.msix_count_csr.msix_2_cdc_msix_count = inp2cr_msix_count_vector[15:8]; +assign fme_csr_msix_count_csr_update.msix_count_csr.cdc_2_avl_msix_count = inp2cr_msix_count_vector[ 7:0]; + +//---------------------------------------------------------------------------- +// Register Output Breakout Structure Overlays/Maps. +//---------------------------------------------------------------------------- +assign fme_csr_msix_addr0.data = csr_reg[MSIX_ADDR0 [12]][MSIX_ADDR0 [7:3]]; +assign fme_csr_msix_addr1.data = csr_reg[MSIX_ADDR1 [12]][MSIX_ADDR1 [7:3]]; +assign fme_csr_msix_addr2.data = csr_reg[MSIX_ADDR2 [12]][MSIX_ADDR2 [7:3]]; +assign fme_csr_msix_addr3.data = csr_reg[MSIX_ADDR3 [12]][MSIX_ADDR3 [7:3]]; +assign fme_csr_msix_addr4.data = csr_reg[MSIX_ADDR4 [12]][MSIX_ADDR4 [7:3]]; +assign fme_csr_msix_addr5.data = csr_reg[MSIX_ADDR5 [12]][MSIX_ADDR5 [7:3]]; +assign fme_csr_msix_addr6.data = csr_reg[MSIX_ADDR6 [12]][MSIX_ADDR6 [7:3]]; +assign fme_csr_msix_addr7.data = csr_reg[MSIX_ADDR7 [12]][MSIX_ADDR7 [7:3]]; +assign fme_csr_msix_ctldat0.data = csr_reg[MSIX_CTLDAT0 [12]][MSIX_CTLDAT0 [7:3]]; +assign fme_csr_msix_ctldat1.data = csr_reg[MSIX_CTLDAT1 [12]][MSIX_CTLDAT1 [7:3]]; +assign fme_csr_msix_ctldat2.data = csr_reg[MSIX_CTLDAT2 [12]][MSIX_CTLDAT2 [7:3]]; +assign fme_csr_msix_ctldat3.data = csr_reg[MSIX_CTLDAT3 [12]][MSIX_CTLDAT3 [7:3]]; +assign fme_csr_msix_ctldat4.data = csr_reg[MSIX_CTLDAT4 [12]][MSIX_CTLDAT4 [7:3]]; +assign fme_csr_msix_ctldat5.data = csr_reg[MSIX_CTLDAT5 [12]][MSIX_CTLDAT5 [7:3]]; +assign fme_csr_msix_ctldat6.data = csr_reg[MSIX_CTLDAT6 [12]][MSIX_CTLDAT6 [7:3]]; +assign fme_csr_msix_ctldat7.data = csr_reg[MSIX_CTLDAT7 [12]][MSIX_CTLDAT7 [7:3]]; +assign fme_csr_msix_pba.data = csr_reg[MSIX_PBA [12]][MSIX_PBA [7:3]]; + +//---------------------------------------------------------------------------- +// FME Outputs into the FME Interface for distribution. +//---------------------------------------------------------------------------- +assign cr2out_msix_addr0 = fme_csr_msix_addr0.data; +assign cr2out_msix_addr1 = fme_csr_msix_addr1.data; +assign cr2out_msix_addr2 = fme_csr_msix_addr2.data; +assign cr2out_msix_addr3 = fme_csr_msix_addr3.data; +assign cr2out_msix_addr4 = fme_csr_msix_addr4.data; +assign cr2out_msix_addr5 = fme_csr_msix_addr5.data; +assign cr2out_msix_addr6 = fme_csr_msix_addr6.data; +assign cr2out_msix_addr7 = fme_csr_msix_addr7.data; +assign cr2out_msix_ctldat0 = fme_csr_msix_ctldat0.data; +assign cr2out_msix_ctldat1 = fme_csr_msix_ctldat1.data; +assign cr2out_msix_ctldat2 = fme_csr_msix_ctldat2.data; +assign cr2out_msix_ctldat3 = fme_csr_msix_ctldat3.data; +assign cr2out_msix_ctldat4 = fme_csr_msix_ctldat4.data; +assign cr2out_msix_ctldat5 = fme_csr_msix_ctldat5.data; +assign cr2out_msix_ctldat6 = fme_csr_msix_ctldat6.data; +assign cr2out_msix_ctldat7 = fme_csr_msix_ctldat7.data; +assign cr2out_msix_pba = fme_csr_msix_pba.data; + +//---------------------------------------------------------------------------- +// HW State is a data struct used to pass the resets, write data, and write +// type to the CSR "update_reg" function. +//---------------------------------------------------------------------------- +assign hw_state.reset_n = rst_n; +assign hw_state.pwr_good_n = 1'b1; +assign hw_state.wr_data.data = data_reg; +assign hw_state.write_type = write_type_reg; + +//---------------------------------------------------------------------------- +// Combinatorial logic to define what type of write is occurring: +// 1.) UPPER32 = Upper 32 bits of register from lower 32 bits of the write +// data bus. +// 2.) LOWER32 = Lower 32 bits of register from lower 32 bits of the write +// data bus. +// 3.) FULL64 = All 64 bits of the register from all 64 bits of the write +// data bus. +// 4.) NONE = No write will be performed on register. +// Logic must be careful to detect simultaneous awvalid and wvalid OR awvalid +// leading wvalid. A write address with bit #2 set decides whether 32-bit +// write is to upper or lower word. +//---------------------------------------------------------------------------- +always_comb +begin + write_type = ( !avmm_m2s_write ) ? NONE : + ( &avmm_m2s_byteenable ) ? FULL64 : + ( !avmm_m2s_address[2] ) ? LOWER32 : + UPPER32; +end + +//---------------------------------------------------------------------------- +// Sequential logic to capture some transaction-qualifying signals during +// writes on the write-data bus. Values are sampled on the transition into +// "DATA" states in the write state machine. +//---------------------------------------------------------------------------- +always_ff @ ( posedge clk ) +begin + if ( !rst_n ) + begin + write_type_reg <= NONE; + write_reg <= 1'b0; + data_reg <= {64{1'b0}}; + csr_write <= '{default:0}; + end + else + begin + write_type_reg <= write_type; + write_reg <= avmm_m2s_write; + data_reg <= avmm_m2s_writedata; + + csr_write <= '{default:0}; + csr_write + [ avmm_m2s_address[12] ] + [ avmm_m2s_address[7:3] ] <= avmm_m2s_write; + end +end + +//---------------------------------------------------------------------------- +// Register Update Logic using "update_reg" function in "ofs_csr_pkg.sv" +// SystemVerilog package. Function inputs are "named" for ease of +// understanding the use. +// - Register bit attributes are set in array input above. Attribute +// functions are defined in SAS. +// - Reset Value is appied at reset except for RO, *D, and Rsvd{Z}. +// - Update Value is used as status bit updates for RO, RW1C*, and RW1S*. +// - Current Value is used to determine next register value. This must be +// done due to scoping rules using SystemVerilog package. +// - "Write" is the decoded write signal for that particular register. +// - State is a hardware state structure to pass input signals to +// "update_reg" function. See just above. +//---------------------------------------------------------------------------- +always_ff @ ( posedge clk ) +begin + + csr_reg[MSIX_ADDR0[12]][MSIX_ADDR0[7:3]] <= update_reg(.attr(msix_addr0_attr.data), + .reg_reset_val( fme_csr_msix_addr0_reset.data), + .reg_update_val(fme_csr_msix_addr0_update.data), + .reg_current_val(csr_reg[MSIX_ADDR0[12]][MSIX_ADDR0[7:3]]), + .write( csr_write[MSIX_ADDR0[12]][MSIX_ADDR0[7:3]]), + .state(hw_state) + ); + + csr_reg[MSIX_ADDR1[12]][MSIX_ADDR1[7:3]] <= update_reg(.attr(msix_addr1_attr.data), + .reg_reset_val( fme_csr_msix_addr1_reset.data), + .reg_update_val(fme_csr_msix_addr1_update.data), + .reg_current_val(csr_reg[MSIX_ADDR1[12]][MSIX_ADDR1[7:3]]), + .write( csr_write[MSIX_ADDR1[12]][MSIX_ADDR1[7:3]]), + .state(hw_state) + ); + + csr_reg[MSIX_ADDR2[12]][MSIX_ADDR2[7:3]] <= update_reg(.attr(msix_addr2_attr.data), + .reg_reset_val( fme_csr_msix_addr2_reset.data), + .reg_update_val(fme_csr_msix_addr2_update.data), + .reg_current_val(csr_reg[MSIX_ADDR2[12]][MSIX_ADDR2[7:3]]), + .write( csr_write[MSIX_ADDR2[12]][MSIX_ADDR2[7:3]]), + .state(hw_state) + ); + + csr_reg[MSIX_ADDR3[12]][MSIX_ADDR3[7:3]] <= update_reg(.attr(msix_addr3_attr.data), + .reg_reset_val( fme_csr_msix_addr3_reset.data), + .reg_update_val(fme_csr_msix_addr3_update.data), + .reg_current_val(csr_reg[MSIX_ADDR3[12]][MSIX_ADDR3[7:3]]), + .write( csr_write[MSIX_ADDR3[12]][MSIX_ADDR3[7:3]]), + .state(hw_state) + ); + + csr_reg[MSIX_ADDR4[12]][MSIX_ADDR4[7:3]] <= update_reg(.attr(msix_addr4_attr.data), + .reg_reset_val( fme_csr_msix_addr4_reset.data), + .reg_update_val(fme_csr_msix_addr4_update.data), + .reg_current_val(csr_reg[MSIX_ADDR4[12]][MSIX_ADDR4[7:3]]), + .write( csr_write[MSIX_ADDR4[12]][MSIX_ADDR4[7:3]]), + .state(hw_state) + ); + + csr_reg[MSIX_ADDR5[12]][MSIX_ADDR5[7:3]] <= update_reg(.attr(msix_addr5_attr.data), + .reg_reset_val( fme_csr_msix_addr5_reset.data), + .reg_update_val(fme_csr_msix_addr5_update.data), + .reg_current_val(csr_reg[MSIX_ADDR5[12]][MSIX_ADDR5[7:3]]), + .write( csr_write[MSIX_ADDR5[12]][MSIX_ADDR5[7:3]]), + .state(hw_state) + ); + + csr_reg[MSIX_ADDR6[12]][MSIX_ADDR6[7:3]] <= update_reg(.attr(msix_addr6_attr.data), + .reg_reset_val( fme_csr_msix_addr6_reset.data), + .reg_update_val(fme_csr_msix_addr6_update.data), + .reg_current_val(csr_reg[MSIX_ADDR6[12]][MSIX_ADDR6[7:3]]), + .write( csr_write[MSIX_ADDR6[12]][MSIX_ADDR6[7:3]]), + .state(hw_state) + ); + + csr_reg[MSIX_ADDR7[12]][MSIX_ADDR7[7:3]] <= update_reg(.attr(msix_addr7_attr.data), + .reg_reset_val( fme_csr_msix_addr7_reset.data), + .reg_update_val(fme_csr_msix_addr7_update.data), + .reg_current_val(csr_reg[MSIX_ADDR7[12]][MSIX_ADDR7[7:3]]), + .write( csr_write[MSIX_ADDR7[12]][MSIX_ADDR7[7:3]]), + .state(hw_state) + ); + + csr_reg[MSIX_CTLDAT0[12]][MSIX_CTLDAT0[7:3]] <= update_reg(.attr(msix_ctldat0_attr.data), + .reg_reset_val( fme_csr_msix_ctldat0_reset.data), + .reg_update_val(fme_csr_msix_ctldat0_update.data), + .reg_current_val(csr_reg[MSIX_CTLDAT0[12]][MSIX_CTLDAT0[7:3]]), + .write( csr_write[MSIX_CTLDAT0[12]][MSIX_CTLDAT0[7:3]]), + .state(hw_state) + ); + + csr_reg[MSIX_CTLDAT1[12]][MSIX_CTLDAT1[7:3]] <= update_reg(.attr(msix_ctldat1_attr.data), + .reg_reset_val( fme_csr_msix_ctldat1_reset.data), + .reg_update_val(fme_csr_msix_ctldat1_update.data), + .reg_current_val(csr_reg[MSIX_CTLDAT1[12]][MSIX_CTLDAT1[7:3]]), + .write( csr_write[MSIX_CTLDAT1[12]][MSIX_CTLDAT1[7:3]]), + .state(hw_state) + ); + + csr_reg[MSIX_CTLDAT2[12]][MSIX_CTLDAT2[7:3]] <= update_reg(.attr(msix_ctldat2_attr.data), + .reg_reset_val( fme_csr_msix_ctldat2_reset.data), + .reg_update_val(fme_csr_msix_ctldat2_update.data), + .reg_current_val(csr_reg[MSIX_CTLDAT2[12]][MSIX_CTLDAT2[7:3]]), + .write( csr_write[MSIX_CTLDAT2[12]][MSIX_CTLDAT2[7:3]]), + .state(hw_state) + ); + + csr_reg[MSIX_CTLDAT3[12]][MSIX_CTLDAT3[7:3]] <= update_reg(.attr(msix_ctldat3_attr.data), + .reg_reset_val( fme_csr_msix_ctldat3_reset.data), + .reg_update_val(fme_csr_msix_ctldat3_update.data), + .reg_current_val(csr_reg[MSIX_CTLDAT3[12]][MSIX_CTLDAT3[7:3]]), + .write( csr_write[MSIX_CTLDAT3[12]][MSIX_CTLDAT3[7:3]]), + .state(hw_state) + ); + + csr_reg[MSIX_CTLDAT4[12]][MSIX_CTLDAT4[7:3]] <= update_reg(.attr(msix_ctldat4_attr.data), + .reg_reset_val( fme_csr_msix_ctldat4_reset.data), + .reg_update_val(fme_csr_msix_ctldat4_update.data), + .reg_current_val(csr_reg[MSIX_CTLDAT4[12]][MSIX_CTLDAT4[7:3]]), + .write( csr_write[MSIX_CTLDAT4[12]][MSIX_CTLDAT4[7:3]]), + .state(hw_state) + ); + + csr_reg[MSIX_CTLDAT5[12]][MSIX_CTLDAT5[7:3]] <= update_reg(.attr(msix_ctldat5_attr.data), + .reg_reset_val( fme_csr_msix_ctldat5_reset.data), + .reg_update_val(fme_csr_msix_ctldat5_update.data), + .reg_current_val(csr_reg[MSIX_CTLDAT5[12]][MSIX_CTLDAT5[7:3]]), + .write( csr_write[MSIX_CTLDAT5[12]][MSIX_CTLDAT5[7:3]]), + .state(hw_state) + ); + + csr_reg[MSIX_CTLDAT6[12]][MSIX_CTLDAT6[7:3]] <= update_reg(.attr(msix_ctldat6_attr.data), + .reg_reset_val( fme_csr_msix_ctldat6_reset.data), + .reg_update_val(fme_csr_msix_ctldat6_update.data), + .reg_current_val(csr_reg[MSIX_CTLDAT6[12]][MSIX_CTLDAT6[7:3]]), + .write( csr_write[MSIX_CTLDAT6[12]][MSIX_CTLDAT6[7:3]]), + .state(hw_state) + ); + + csr_reg[MSIX_CTLDAT7[12]][MSIX_CTLDAT7[7:3]] <= update_reg(.attr(msix_ctldat7_attr.data), + .reg_reset_val( fme_csr_msix_ctldat7_reset.data), + .reg_update_val(fme_csr_msix_ctldat7_update.data), + .reg_current_val(csr_reg[MSIX_CTLDAT7[12]][MSIX_CTLDAT7[7:3]]), + .write( csr_write[MSIX_CTLDAT7[12]][MSIX_CTLDAT7[7:3]]), + .state(hw_state) + ); + + csr_reg[MSIX_PBA[12]][MSIX_PBA[7:3]] <= update_reg(.attr(msix_pba_attr.data), + .reg_reset_val( fme_csr_msix_pba_reset.data), + .reg_update_val(fme_csr_msix_pba_update.data), + .reg_current_val(csr_reg[MSIX_PBA[12]][MSIX_PBA[7:3]]), + .write( csr_write[MSIX_PBA[12]][MSIX_PBA[7:3]]), + .state(hw_state) + ); + + csr_reg[MSIX_COUNT_CSR[12]][MSIX_COUNT_CSR[7:3]] <= update_reg(.attr(msix_count_csr_attr.data), + .reg_reset_val( fme_csr_msix_count_csr_reset.data), + .reg_update_val(fme_csr_msix_count_csr_update.data), + .reg_current_val(csr_reg[MSIX_COUNT_CSR[12]][MSIX_COUNT_CSR[7:3]]), + .write( csr_write[MSIX_COUNT_CSR[12]][MSIX_COUNT_CSR[7:3]]), + .state(hw_state) + ); +end + +always_ff @ ( posedge clk ) +begin + avmm_s2m_readdata <= csr_reg[ avmm_m2s_address[12] ][ avmm_m2s_address[7:3] ]; + avmm_s2m_readdatavalid <= avmm_m2s_read; +end + +always_ff @ ( posedge clk ) +begin + avmm_s2m_waitrequest <= 1'b0; + avmm_s2m_writeresponsevalid <= write_reg; +end + +endmodule diff --git a/src/interrupt/msix_filter.sv b/src/interrupt/msix_filter.sv new file mode 100755 index 0000000..65529d7 --- /dev/null +++ b/src/interrupt/msix_filter.sv @@ -0,0 +1,83 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// * Filter AFU interrupts from the incoming AFU TLP packets on i_afu_tx and +// forward AFU interrupts to MSIX module on o_msix_tx +// +//----------------------------------------------------------------------------- + +import ofs_fim_cfg_pkg::*; +import ofs_fim_if_pkg::*; + +module msix_filter ( + ofs_fim_pcie_txs_axis_if.slave i_afu_tx, + ofs_fim_pcie_txs_axis_if.master o_afu_tx, + ofs_fim_pcie_txs_axis_if.master o_msix_tx +); + +//------------------- +// Internal wires +//------------------- + wire clk; + wire rst_n; + + t_axis_pcie_txs afu_tx; + t_axis_pcie_txs up_afu_tx; + t_axis_pcie_txs up_msix_tx; + + logic up_afu_tx_tready; + logic up_msix_tx_tready; + + logic [FIM_PCIE_TLP_CH-1:0] up_afu_valid; + logic [FIM_PCIE_TLP_CH-1:0] up_msix_valid; + logic [FIM_PCIE_TLP_CH-1:0] is_msix; + logic [FIM_PCIE_TLP_CH-1:0] is_afu_packet; + + logic upstream_afu_ready; + logic upstream_msix_ready; + logic upstream_ready; + +//----------------------------------------------------------------------------- + // Interface assignment + assign clk = i_afu_tx.clk; + assign rst_n = i_afu_tx.rst_n; + assign afu_tx = i_afu_tx.tx; + assign i_afu_tx.tready = upstream_ready; + + assign o_afu_tx.tx = up_afu_tx; + assign o_afu_tx.clk = clk; + assign o_afu_tx.rst_n = rst_n; + assign up_afu_tx_tready = o_afu_tx.tready; + + assign o_msix_tx.tx = up_msix_tx; + assign o_msix_tx.clk = clk; + assign o_msix_tx.rst_n = rst_n; + assign up_msix_tx_tready = o_msix_tx.tready; + + + // Upstream ready to take packets + assign upstream_msix_ready = (~up_msix_tx.tvalid | up_msix_tx_tready); + assign upstream_afu_ready = (~up_afu_tx.tvalid | up_afu_tx_tready); + assign upstream_ready = (upstream_msix_ready && upstream_afu_ready); + + always_comb begin + up_afu_tx = afu_tx; + up_msix_tx = afu_tx; + + for (int ch=0; ch out + if(pf_mask_vector[i] || pf_msix_mask) begin + inp2cr_msix_pba[i] <= pf_monitor_wire[i]; + pf_irq_monitor[i] <= 'b0; + end + else begin + inp2cr_msix_pba[i] <= (pba_sclr[i] | pf_priority_wire [i])?'b0: cr2out_msix_pba[i]; + pf_irq_monitor[i] <= pf_monitor_wire[i]; + end + end + end + inp2cr_msix_pba[63:7] <= 'b0; + end + + //Edge detection for valid signal + always@(posedge clk) begin + if (~rst_n) begin + pf_irq_sync1 <= 0; + end else begin + pf_irq_sync1 <= pf_irq_monitor; + end + end + + always@(posedge clk) begin + for(int i = 0; i < NUM_AFU_INTERRUPTS; i++) + pf_irq_edge_vector[i] <= pf_irq_sync1[i] & ~pf_irq_monitor[i]; + end + + //Output intr id & intr valid + always @(posedge clk) begin + if(~rst_n) begin + o_intr_id <= '0; + o_intr_valid <= '0; + o_intr_id_sync1 <= '0; + o_intr_id_sync2 <= '0; + end + else begin + casez(pf_irq_monitor) + 7'b1??????: o_intr_id_sync1 <= 3'd6; + 7'b??1????: o_intr_id_sync1 <= 3'd4; + 7'b???1???: o_intr_id_sync1 <= 3'd3; + 7'b????1??: o_intr_id_sync1 <= 3'd2; + 7'b?????1?: o_intr_id_sync1 <= 3'd1; + 7'b??????1: o_intr_id_sync1 <= 3'd0; + default : o_intr_id_sync1 <= 3'd0; + endcase + o_intr_valid <= |pf_irq_edge_vector; + o_intr_id_sync2 <= o_intr_id_sync1; + o_intr_id <= o_intr_id_sync2; + end + end + + logic [NUM_AFU_INTERRUPTS-3:0] vf_monitor_wire; + logic [NUM_AFU_INTERRUPTS-3:0] vf_priority_wire; + logic [NUM_AFU_INTERRUPTS-3:0] vf_irq_monitor; + logic [NUM_AFU_INTERRUPTS-3:0] vf_irq_sync1; + logic [NUM_AFU_INTERRUPTS-3:0] vf_irq_edge_vector; // detect falling edge + logic [L_NUM_AFU_INTERRUPTS-1:0] o_vintr_id_sync1,o_vintr_id_sync2; + + //VF space + //Monitors when the inputs change or when irq occurs + always_comb begin + for (int i=0; i<(NUM_AFU_INTERRUPTS-2); i=i+1) begin + vf_monitor_wire[i] = ((cr2out_msix_vpba[i] | vf_irq_vector[i]) & ~pba_sclr[i]); + end + end + + //Updates the pba table about the type of interupt occured. Interrupts are serviced based on priority table. + always_comb begin + casez(vf_monitor_wire) + 5'b1????:vf_priority_wire = 5'h10; + 5'b?1???:vf_priority_wire = 5'h08; + 5'b??1??:vf_priority_wire = 5'h04; + 5'b???1?:vf_priority_wire = 5'h02; + 5'b????1:vf_priority_wire = 5'h01; + default :vf_priority_wire = 5'h00; + endcase + end + + //Send interrupt vector if not masked + always @(posedge clk) begin + if(~rst_n) begin + inp2cr_msix_vpba <= 'b0; + vf_irq_monitor <= 'b0; + end + else begin + for (int i=0; i<(NUM_AFU_INTERRUPTS-2); i=i+1) begin + // Assert IRQ for 2 CC due to FME CSR in-> out + if(vf_mask_vector[i] || vf_msix_mask) begin + inp2cr_msix_vpba[i] <= vf_monitor_wire[i]; + vf_irq_monitor[i] <= 'b0; + end + else begin + inp2cr_msix_vpba[i] <= (pba_sclr[i] | vf_priority_wire [i])?'b0: cr2out_msix_vpba[i]; + vf_irq_monitor[i] <= vf_monitor_wire[i]; + end + end + end + inp2cr_msix_vpba[63:7] <= 'b0; + end + + //Edge detection for valid signal + always@(posedge clk) begin + if (~rst_n) begin + vf_irq_sync1 <= 0; + end else begin + vf_irq_sync1 <= vf_irq_monitor; + end + end + + always@(posedge clk) begin + for(int i = 0; i < (NUM_AFU_INTERRUPTS-2); i++) + vf_irq_edge_vector[i] <= vf_irq_sync1[i] & ~vf_irq_monitor[i]; + end + + //Output intr id & intr valid + always @(posedge clk) begin + if(~rst_n) begin + o_vintr_id <= '0; + o_vintr_id_sync1 <= '0; + o_vintr_id_sync2 <= '0; + o_vintr_valid <= '0; + end + else begin + casez(vf_irq_monitor) + 5'b1????: o_vintr_id_sync1 <= 3'd4; + 5'b?1???: o_vintr_id_sync1 <= 3'd3; + 5'b??1??: o_vintr_id_sync1 <= 3'd2; + 5'b???1?: o_vintr_id_sync1 <= 3'd1; + 5'b????1: o_vintr_id_sync1 <= 3'd0; + default : o_vintr_id_sync1 <= 3'd0; + endcase + o_vintr_valid <= |vf_irq_edge_vector; + o_vintr_id_sync2 <= o_vintr_id_sync1; + o_vintr_id <= o_vintr_id_sync2; + end + end + endmodule diff --git a/src/interrupt/msix_top.sv b/src/interrupt/msix_top.sv new file mode 100755 index 0000000..6bafb2d --- /dev/null +++ b/src/interrupt/msix_top.sv @@ -0,0 +1,421 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// MSIX top level module +// * Receive AFU interrupt requests on i_afu_msix_req +// * Send out PCIe interrupt TLP for FME/Port interrupts and AFU interrupts +// +//----------------------------------------------------------------------------- + +import ofs_fim_if_pkg::*; +import ofs_fim_cfg_pkg::*; +import ofs_fim_pcie_hdr_def::*; + + +module msix_top + # ( parameter VF_NUM = 1 ) +( + // AFU interrupt interface (incoming AFU interrupt requests) + ofs_fim_pcie_txs_axis_if.slave i_afu_msix_req, + + // MSIX TX channel interface (outgoing PCIe interrupt TLP packets) + ofs_fim_pcie_tx_axis_if.master o_msix_tx_st, + + // AFU interrupt response interface + ofs_fim_afu_irq_rsp_axis_if.master o_msix_rsp, + + //FME to MSIX signals +// fme_csr_io_if msix_fme_io, +// vfme_csr_io_if.interrupt msix_vfme_io, +// port_csr_io_if msix_port_io, + + //MSIX table + PBA + output logic [6:0] inp2cr_msix_pba, + + input logic [63:0] cr2out_msix_addr0, + input logic [63:0] cr2out_msix_addr1, + input logic [63:0] cr2out_msix_addr2, + input logic [63:0] cr2out_msix_addr3, + input logic [63:0] cr2out_msix_addr4, + input logic [63:0] cr2out_msix_addr5, + input logic [63:0] cr2out_msix_addr6, + input logic [63:0] cr2out_msix_addr7, + input logic [63:0] cr2out_msix_ctldat0, + input logic [63:0] cr2out_msix_ctldat1, + input logic [63:0] cr2out_msix_ctldat2, + input logic [63:0] cr2out_msix_ctldat3, + input logic [63:0] cr2out_msix_ctldat4, + input logic [63:0] cr2out_msix_ctldat5, + input logic [63:0] cr2out_msix_ctldat6, + input logic [63:0] cr2out_msix_ctldat7, + input logic [63:0] cr2out_msix_pba, + + output logic [6:0] inp2cr_msix_vpba, + + input logic [63:0] cr2out_msix_vaddr0, + input logic [63:0] cr2out_msix_vaddr1, + input logic [63:0] cr2out_msix_vaddr2, + input logic [63:0] cr2out_msix_vaddr3, + input logic [63:0] cr2out_msix_vaddr4, + input logic [63:0] cr2out_msix_vaddr5, + input logic [63:0] cr2out_msix_vaddr6, + input logic [63:0] cr2out_msix_vaddr7, + input logic [63:0] cr2out_msix_vctldat0, + input logic [63:0] cr2out_msix_vctldat1, + input logic [63:0] cr2out_msix_vctldat2, + input logic [63:0] cr2out_msix_vctldat3, + input logic [63:0] cr2out_msix_vctldat4, + input logic [63:0] cr2out_msix_vctldat5, + input logic [63:0] cr2out_msix_vctldat6, + input logic [63:0] cr2out_msix_vctldat7, + input logic [63:0] cr2out_msix_vpba, + + //PCIE sideband signals + input t_sideband_from_pcie i_pcie_p2c_sideband, + output t_sideband_to_pcie o_pcie_c2p_sideband, + + //Port access control +// input logic [PORTS-1:0] i_port_access_ctrl, + + input clk, + input rst_n, + input logic afu_softreset + ); + + localparam [7:0] PCIE_FMTTYPE_MEM_WRITE32 = 8'h40, + PCIE_FMTTYPE_MEM_WRITE64 = 8'h60; + + logic o_intr_valid,o_vintr_valid; + logic [L_NUM_AFU_INTERRUPTS-1:0] o_intr_id, o_vintr_id; + logic [95:0] i_msix_table_entry; + logic [L_NUM_AFU_INTERRUPTS:0] i_intr_id; + logic i_intr_val; + logic fme_irq; + logic [NUM_AFU_INTERRUPTS -1:0] pf_mask_vector; + logic [NUM_AFU_INTERRUPTS -3:0] vf_mask_vector; + logic [PORTS-1:0] vf_active; + logic [PORTS-1:0] vf_active_reg; + + logic afu_msix_req_tready; + logic afu_irq_valid; + logic afu_irq; + logic msix_mask,rsp_ack; + logic pf_user_irq,vf_user_irq; + logic user_irq_valid; // *NEW* + logic [3:0] user_irq_in, user_irq_out; + logic [FIM_NUM_PF-1:0] a2c_msix_en_pf; + logic [FIM_NUM_PF-1:0] a2c_msix_fn_mask_pf; + logic vf_msix_mask; + logic port_irq_in; + logic cr2out_port_error_clear; + logic [3:0] mask_vector; +/* + //MSIX Table signals + logic [63:0] inp2cr_msix_pba,inp2cr_msix_vpba; + logic [63:0] cr2out_msix_pba,cr2out_msix_vpba; + logic [63:0] cr2out_msix_addr0, cr2out_msix_addr1, cr2out_msix_addr2, cr2out_msix_addr3; + logic [63:0] cr2out_msix_addr4, cr2out_msix_addr5, cr2out_msix_addr6, cr2out_msix_addr7; + logic [63:0] cr2out_msix_ctldat0, cr2out_msix_ctldat1, cr2out_msix_ctldat2, cr2out_msix_ctldat3; + logic [63:0] cr2out_msix_ctldat4, cr2out_msix_ctldat5, cr2out_msix_ctldat6, cr2out_msix_ctldat7; + logic [63:0] cr2out_msix_vaddr0, cr2out_msix_vaddr1, cr2out_msix_vaddr2, cr2out_msix_vaddr3, cr2out_msix_vaddr4; + logic [63:0] cr2out_msix_vctldat0, cr2out_msix_vctldat1, cr2out_msix_vctldat2, cr2out_msix_vctldat3, cr2out_msix_vctldat4; +*/ + + // MSI-X to PCIe + logic [63:0] o_msix_addr; + logic o_msix_valid; + logic [31:0] o_msix_data; + + logic i_msix_st_tready; + logic [16:0] addr_64b; + + t_axis_pcie_txs mwr_packet; + t_axis_pcie_tx tx_st, tx_st_q; + t_axis_irq_rsp pf_irq_rsp, vf_irq_rsp; + t_tlp_mem_req_hdr [1:0] mwr_hdr; + t_sideband_from_pcie pcie_p2c_sideband; + + localparam DATA_WIDTH = $bits(i_pcie_p2c_sideband.cfg_ctl); + + //Sync pcie sideband signals to msix clk + fim_resync # ( + .WIDTH(DATA_WIDTH), + .NO_CUT(0) ) + sync ( + .clk (clk), + .reset (~rst_n), + .d (i_pcie_p2c_sideband.cfg_ctl), + .q (pcie_p2c_sideband.cfg_ctl) + ); + + assign i_msix_st_tready = o_msix_tx_st.tready; + assign i_afu_msix_req.tready = afu_msix_req_tready; + assign afu_irq = i_afu_msix_req.tx.tdata[0].valid ? + i_afu_msix_req.tx.tuser[0].afu_irq : + i_afu_msix_req.tx.tuser[1].afu_irq; + assign afu_irq_valid = i_afu_msix_req.tx.tvalid; + assign user_irq_in = i_afu_msix_req.tx.tdata[0].valid ? + i_afu_msix_req.tx.tdata[0].hdr[19:16] : + i_afu_msix_req.tx.tdata[1].hdr[19:16]; + + //PCIE Sideband signals + assign a2c_msix_fn_mask_pf = pcie_p2c_sideband.cfg_ctl.msix_pf_mask_en; + assign a2c_msix_en_pf = pcie_p2c_sideband.cfg_ctl.msix_enable; + assign vf_msix_mask = pcie_p2c_sideband.cfg_ctl.vf0_msix_mask; +/* + //FME to MSIX Signals + assign cr2out_msix_pba = msix_fme_io.cr2out_msix_pba; + assign cr2out_msix_addr0 = msix_fme_io.cr2out_msix_addr0; + assign cr2out_msix_addr1 = msix_fme_io.cr2out_msix_addr1; + assign cr2out_msix_addr2 = msix_fme_io.cr2out_msix_addr2; + assign cr2out_msix_addr3 = msix_fme_io.cr2out_msix_addr3; + assign cr2out_msix_addr4 = msix_fme_io.cr2out_msix_addr4; + assign cr2out_msix_addr5 = msix_fme_io.cr2out_msix_addr5; + assign cr2out_msix_addr6 = msix_fme_io.cr2out_msix_addr6; + assign cr2out_msix_addr7 = msix_fme_io.cr2out_msix_addr7; + assign cr2out_msix_ctldat0 = msix_fme_io.cr2out_msix_ctldat0; + assign cr2out_msix_ctldat1 = msix_fme_io.cr2out_msix_ctldat1; + assign cr2out_msix_ctldat2 = msix_fme_io.cr2out_msix_ctldat2; + assign cr2out_msix_ctldat3 = msix_fme_io.cr2out_msix_ctldat3; + assign cr2out_msix_ctldat4 = msix_fme_io.cr2out_msix_ctldat4; + assign cr2out_msix_ctldat5 = msix_fme_io.cr2out_msix_ctldat5; + assign cr2out_msix_ctldat6 = msix_fme_io.cr2out_msix_ctldat6; + assign cr2out_msix_ctldat7 = msix_fme_io.cr2out_msix_ctldat7; + +*/ + assign fme_irq = i_afu_msix_req.tx.tvalid && + ( ( i_afu_msix_req.tx.tdata[0].hdr[19:16] == 4'h6 ) + && i_afu_msix_req.tx.tdata[0].valid ) || + ( ( i_afu_msix_req.tx.tdata[1].hdr[19:16] == 4'h6 ) + && i_afu_msix_req.tx.tdata[1].valid ); // *NEW* + + //Port to MSIX + assign port_irq_in = i_afu_msix_req.tx.tvalid && // WAS |msix_port_io.cr2out_port_error; + ( ( i_afu_msix_req.tx.tdata[0].hdr[19:16] == 4'h4 ) + && i_afu_msix_req.tx.tdata[0].valid ) || + ( ( i_afu_msix_req.tx.tdata[1].hdr[19:16] == 4'h4 ) + && i_afu_msix_req.tx.tdata[1].valid ); + + assign cr2out_port_error_clear = 1'b0; // WAS msix_port_io.cr2out_port_error_clear; + assign vf_active = i_afu_msix_req.tx.tdata[0].valid ? // WAS i_port_access_ctrl; + i_afu_msix_req.tx.tuser[0].vf_active : + i_afu_msix_req.tx.tdata[1].valid ? + i_afu_msix_req.tx.tuser[1].vf_active : + vf_active_reg; + + // Register to hold vf_active until next valid + always_ff @ ( posedge clk ) + vf_active_reg <= vf_active; + + //MSIX to FME and vFME Signals + //assign msix_fme_io.inp2cr_msix_pba = inp2cr_msix_pba; + //assign msix_vfme_io.inp2cr_msix_vpba = inp2cr_msix_vpba; +/* + //vFME to MSIX Signals + assign cr2out_msix_vpba = msix_vfme_io.cr2out_msix_vpba; + assign cr2out_msix_vaddr0 = msix_vfme_io.cr2out_msix_vaddr0; + assign cr2out_msix_vaddr1 = msix_vfme_io.cr2out_msix_vaddr1; + assign cr2out_msix_vaddr2 = msix_vfme_io.cr2out_msix_vaddr2; + assign cr2out_msix_vaddr3 = msix_vfme_io.cr2out_msix_vaddr3; + assign cr2out_msix_vaddr4 = msix_vfme_io.cr2out_msix_vaddr4; + assign cr2out_msix_vctldat0 = msix_vfme_io.cr2out_msix_vctldat0; + assign cr2out_msix_vctldat1 = msix_vfme_io.cr2out_msix_vctldat1; + assign cr2out_msix_vctldat2 = msix_vfme_io.cr2out_msix_vctldat2; + assign cr2out_msix_vctldat3 = msix_vfme_io.cr2out_msix_vctldat3; + assign cr2out_msix_vctldat4 = msix_vfme_io.cr2out_msix_vctldat4; +*/ + assign pf_user_irq = ((o_intr_id == 4'h0 || o_intr_id == 4'h1 ||o_intr_id == 4'h2 ||o_intr_id == 4'h3) && o_intr_valid)? 'b1 :'b0; + assign vf_user_irq = ((o_vintr_id == 4'h0 || o_vintr_id == 4'h1 ||o_vintr_id == 4'h2 ||o_vintr_id == 4'h3) && o_vintr_valid) ? 'b1:'b0; + assign mask_vector = vf_active [0] ? vf_mask_vector[3:0] : pf_mask_vector[3:0]; + assign msix_mask = vf_active [0] ? vf_msix_mask : a2c_msix_fn_mask_pf; + + //Interface assignment + assign o_msix_tx_st.tx = tx_st; + assign o_msix_tx_st.clk = clk; + assign o_msix_tx_st.rst_n = rst_n; + + //Response Interface + assign o_msix_rsp.clk = clk; + assign o_msix_rsp.rst_n = rst_n; + assign o_msix_rsp.tvalid = vf_active[0] ? vf_irq_rsp.tvalid : pf_irq_rsp.tvalid; + assign o_msix_rsp.tdata = vf_active[0] ? vf_irq_rsp.tdata : pf_irq_rsp.tdata; + + assign rsp_ack = o_msix_rsp.tvalid && o_msix_rsp.tready; + + assign addr_64b = |o_msix_addr[48:32]; + + // MWR packet + always_comb begin + mwr_hdr[0] = '0; + mwr_hdr[0].dw0.fmttype = addr_64b ? PCIE_FMTTYPE_MEM_WRITE64: PCIE_FMTTYPE_MEM_WRITE32; + mwr_hdr[0].dw0.length = 10'd1; + mwr_hdr[0].first_be = 4'hf; + mwr_hdr[0].last_be = 4'h0; + mwr_hdr[0].addr = addr_64b ? o_msix_addr[63:32]: o_msix_addr[31:0]; + mwr_hdr[0].lsb_addr = addr_64b ? o_msix_addr[31:0]: '0; + mwr_hdr[0].requester_id = vf_active[0] ? {VF_NUM,4'd0} : '0; + + mwr_packet = '0; + mwr_packet.tdata[0].hdr = mwr_hdr[0]; + mwr_packet.tdata[0].payload = o_msix_data; + mwr_packet.tdata[0].valid = 1'b1; + mwr_packet.tdata[0].eop = 1'b1; + mwr_packet.tdata[0].sop = 1'b1; + mwr_packet.tuser[0].afu_irq = 1'b0; + mwr_packet.tuser[0].vf_active = vf_active[0] ? 1'b1:1'b0; + end + + //MSIX to AFU Response for PF User IRQ + always_ff @(posedge clk) begin + if(~rst_n) begin + pf_irq_rsp.tvalid <= '0; + pf_irq_rsp.tdata <= '0; + end else if(!pf_irq_rsp.tvalid || o_msix_rsp.tready) begin + pf_irq_rsp.tvalid <= '0; + pf_irq_rsp.tdata <= '0; + if(pf_user_irq) begin + pf_irq_rsp.tvalid <= 1'b1; + pf_irq_rsp.tdata <= '0; + pf_irq_rsp.tdata[19:16] <= o_intr_id; + end else begin + pf_irq_rsp.tvalid <= '0; + pf_irq_rsp.tdata <= '0; + end + end + end + + //MSIX to AFU Response for VF User IRQ + always_ff @(posedge clk) begin + if(~rst_n) begin + vf_irq_rsp.tvalid <= '0; + vf_irq_rsp.tdata <= '0; + end else if(!vf_irq_rsp.tvalid || o_msix_rsp.tready) begin + vf_irq_rsp.tvalid <= '0; + vf_irq_rsp.tdata <= '0; + if(vf_user_irq) begin + vf_irq_rsp.tvalid <= 1'b1; + vf_irq_rsp.tdata <= '0; + vf_irq_rsp.tdata[19:16] <= o_vintr_id; + end else begin + vf_irq_rsp.tvalid <= '0; + vf_irq_rsp.tdata <= '0; + end + end + end + + always_comb begin + tx_st.tvalid = o_msix_valid; + tx_st.tdata = mwr_packet.tdata[0]; + tx_st.tuser = mwr_packet.tuser[0]; + tx_st.tlast = o_msix_valid; + tx_st.tdata.sop = o_msix_valid; + tx_st.tdata.eop = o_msix_valid; + tx_st.tdata.valid = o_msix_valid; + end + + //Module Instantiation + msix_wrapper msix_wrapper_inst( + .clk (clk), + .rst_n (rst_n), + .o_msix_addr (o_msix_addr), + .o_msix_valid (o_msix_valid), + .o_msix_data (o_msix_data), + + .a2c_msix_en_pf (a2c_msix_en_pf), + .a2c_msix_fn_mask_pf (a2c_msix_fn_mask_pf), + .vf_msix_mask (vf_msix_mask), + + .o_intr_valid (o_intr_valid), + .o_intr_id (o_intr_id), + .o_vintr_valid (o_vintr_valid), + .o_vintr_id (o_vintr_id), + + .i_msix_st_tready (i_msix_st_tready), + .i_msix_table_entry (i_msix_table_entry), + .i_intr_id (i_intr_id), + .i_intr_val (i_intr_val), + + .fme_irq (fme_irq), + .port_irq_in (port_irq_in), + .user_irq (user_irq_out), + .vf_active (vf_active), + + .pf_mask_vector (pf_mask_vector), + .vf_mask_vector (vf_mask_vector), + .pba_sclr ({1'b0,1'b0, + cr2out_port_error_clear, + {4{afu_softreset}}}), + + .inp2cr_msix_pba (inp2cr_msix_pba), + .cr2out_msix_pba (cr2out_msix_pba), + .inp2cr_msix_vpba (inp2cr_msix_vpba), + .cr2out_msix_vpba (cr2out_msix_vpba) + ); + + //User IRQ valid - *NEW* + assign user_irq_valid = i_afu_msix_req.tx.tvalid && + ( ( i_afu_msix_req.tx.tdata[0].hdr[19:16] < 4'h4 ) + && i_afu_msix_req.tx.tdata[0].valid ) || + ( ( i_afu_msix_req.tx.tdata[1].hdr[19:16] < 4'h4 ) + && i_afu_msix_req.tx.tdata[1].valid ); + + //User IRQ -> vector + msix_user_irq msix_user_irq_inst ( + .clk (clk), + .rst_n (rst_n), + .i_afu_irq (afu_irq), + .i_msix_mask (msix_mask), + .i_mask_vector (mask_vector), + .i_rsp_ack (rsp_ack), + .o_afu_msix_req_tready (afu_msix_req_tready), + .i_afu_irq_valid (user_irq_valid), // WAS (afu_irq_valid), + .i_user_irq (user_irq_in), + .user_irq_out (user_irq_out) + ); + + //FME MSIX Table + fme_msix_table fme_msix_table( + .clk (clk), + .rst_n (rst_n), + .cr2out_msix_addr0 (cr2out_msix_addr0), + .cr2out_msix_ctldat0 (cr2out_msix_ctldat0), + .cr2out_msix_addr1 (cr2out_msix_addr1), + .cr2out_msix_ctldat1 (cr2out_msix_ctldat1), + .cr2out_msix_addr2 (cr2out_msix_addr2), + .cr2out_msix_ctldat2 (cr2out_msix_ctldat2), + .cr2out_msix_addr3 (cr2out_msix_addr3), + .cr2out_msix_ctldat3 (cr2out_msix_ctldat3), + .cr2out_msix_addr4 (cr2out_msix_addr4), + .cr2out_msix_ctldat4 (cr2out_msix_ctldat4), + .cr2out_msix_addr5 (cr2out_msix_addr5), + .cr2out_msix_ctldat5 (cr2out_msix_ctldat5), + .cr2out_msix_addr6 (cr2out_msix_addr6), + .cr2out_msix_ctldat6 (cr2out_msix_ctldat6), + .cr2out_msix_addr7 (cr2out_msix_addr7), + .cr2out_msix_ctldat7 (cr2out_msix_ctldat7), + .cr2out_msix_vaddr0 (cr2out_msix_vaddr0), + .cr2out_msix_vctldat0 (cr2out_msix_vctldat0), + .cr2out_msix_vaddr1 (cr2out_msix_vaddr1), + .cr2out_msix_vctldat1 (cr2out_msix_vctldat1), + .cr2out_msix_vaddr2 (cr2out_msix_vaddr2), + .cr2out_msix_vctldat2 (cr2out_msix_vctldat2), + .cr2out_msix_vaddr3 (cr2out_msix_vaddr3), + .cr2out_msix_vctldat3 (cr2out_msix_vctldat3), + .cr2out_msix_vaddr4 (cr2out_msix_vaddr4), + .cr2out_msix_vctldat4 (cr2out_msix_vctldat4), + //MSI-X + .pf_mask_vector (pf_mask_vector), + .vf_mask_vector (vf_mask_vector), + .i_vintr_id (o_vintr_id), + .i_vintr_valid (o_vintr_valid), + .i_intr_id (o_intr_id), + .i_intr_valid (o_intr_valid), + .o_msix_table_entry (i_msix_table_entry), + .o_intr_id (i_intr_id), + .o_intr_val (i_intr_val) + ); + +endmodule diff --git a/src/interrupt/msix_user_irq.sv b/src/interrupt/msix_user_irq.sv new file mode 100755 index 0000000..3b158fe --- /dev/null +++ b/src/interrupt/msix_user_irq.sv @@ -0,0 +1,143 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// MSIX User IRQ module +// * This module handles user_irq generation +//----------------------------------------------------------------------------- + +import ofs_fim_if_pkg::*; +import ofs_fim_cfg_pkg::*; +import ofs_fim_pcie_hdr_def::*; + +module msix_user_irq ( + input clk, + input rst_n, + input logic [3:0] i_user_irq, + input i_afu_irq, + input i_afu_irq_valid, + input i_rsp_ack, + input i_msix_mask, + input [3:0] i_mask_vector, + + output o_afu_msix_req_tready, + output logic [3:0] user_irq_out +); + + logic [3:0] user_irq, user_irq_sync, user_irq_edge; + logic fifo_rd,fifo_wr; + logic [3:0] fifo_out; + logic fifo_full, fifo_empty, fifo_out_valid, w_ready; + logic msix_ack; + logic [3:0] mask_bit; + + localparam IRQ_WIDTH = $size(i_user_irq); + localparam DATA_WIDTH = IRQ_WIDTH; + + //Back pressure logic to AFU + assign o_afu_msix_req_tready = ~fifo_full; + + always_comb begin + for (int irq=0; irq>>>>>>>>>>>>>>>",$time); + if (rst_n & out_q_perr) $display("T=%e <<<<<<<<<<<<<<>>>>>>>>>>>>>",$time); + + `ifdef CYCLE_MSG + if(ho2mx_rx_port.tvalid & ho2mx_rx_port.tready) + casex(M_TID) + 0: display_cycle("HLB", 1'b1, M_in_sop[0][0],ho2mx_rx_port.tlast, ho2mx_rx_port.tdata); + 1: display_cycle("PRG", 1'b1, M_in_sop[0][1],ho2mx_rx_port.tlast, ho2mx_rx_port.tdata); + 2: display_cycle("HSS", 1'b1, M_in_sop[0][2],ho2mx_rx_port.tlast, ho2mx_rx_port.tdata); + default: display_cycle("CFG", 1'b1, M_in_sop[0][3],ho2mx_rx_port.tlast, ho2mx_rx_port.tdata); + endcase + if(|(N_in_valid & N_ready)) + casex (N_ready) + 4'b0001: display_cycle("HLB", 1'b0, N_in_sop[0] ,N_in_eop[0], N_in_data[0]); + 4'b001x: display_cycle("PRG", 1'b0, N_in_sop[1] ,N_in_eop[1], N_in_data[1]); + 4'b01xx: display_cycle("HSS", 1'b0, N_in_sop[2] ,N_in_eop[2], N_in_data[2]); + default: display_cycle("CFG", 1'b0, N_in_sop[3] ,N_in_eop[3], N_in_data[3]); + endcase + `endif */ + /* synthesis translate_on */ + + end // + //---------------------------------------------------------------------------------------------------------------------------------------------------------- + // pv/vf mapping encoding function + //---------------------------------------------------------------------------------------------------------------------------------------------------------- + function [ NID_WIDTH:0] M_TID_map ;// Function: M port pf/vf maping to N port + input [VFPF_WIDTH:0] M_vf_pf ;// Input: M port{vf_act[14], vf[13:3], pf[2:0] } + input [ BAR_WIDTH:0] M_bar ;// + begin + casex({M_vf_pf[14], M_vf_pf[4:3], M_bar[2:0]}) /* synthesis parallel_case */ + { 1'b1, 2'd2, 3'd4 } : M_TID_map = 4 ;// VF2 BAR4 + { 1'b1, 2'd1, 3'd4 } : M_TID_map = 3 ;// VF1 BAR4 + { 1'b1, 2'd0, 3'd4 } : M_TID_map = 2 ;// VF0 BAR4 + { 1'b0, 2'bxx, 3'd4 } : M_TID_map = 1 ;// PF0 BAR4 + default : M_TID_map = 0 ;// + endcase // // +// casex({M_vf_pf[14], M_vf_pf[1:0], M_vf_pf[4:3]}) /* synthesis parallel_case */ +// { HLB_VA , HLB_PF[1:0], HLB_VF[1:0]}: M_TID_map = HLB_PID ;// +// { PRG_VA , PRG_PF[1:0], PRG_VF[1:0]}: M_TID_map = PRG_PID ;// +// { HSI_VA , HSI_PF[1:0], HSI_VF[1:0]}: M_TID_map = HSI_PID ;// +// default : M_TID_map = CFG_PID ;// +// endcase // + end // + endfunction // + //---------------------------------------------------------------------------------------------------------------------------------------------------------- + // port data port ready port valid/sop interface // interface to switch port mapping + //---------------------------------------------------------------------------------------------------------------------------------------------------------- + axi_port_map_pcie M0 (M_in_data [0], M_ready [0], M_sop [0], ho2mx_rx_port ,// in M[0] port + M_out_data[0], M_out_ready[0], M_out_valid[0], mx2ho_tx_port ) ;// out + // + axi_port_map_pcie N0 (N_in_data [0], N_ready [0], N_sop [0], fn2mx_tx_port[0] ,// in N[0] port + N_out_data[0], N_out_ready[0], N_out_valid[0], mx2fn_rx_port[0]) ;// out + axi_port_map_pcie N1 (N_in_data [1], N_ready [1], N_sop [1], fn2mx_tx_port[1] ,// in N[1] port + N_out_data[1], N_out_ready[1], N_out_valid[1], mx2fn_rx_port[1]) ;// out + axi_port_map_pcie N2 (N_in_data [2], N_ready [2], N_sop [2], fn2mx_tx_port[2] ,// in N[2] port + N_out_data[2], N_out_ready[2], N_out_valid[2], mx2fn_rx_port[2]) ;// out + axi_port_map_pcie N3 (N_in_data [3], N_ready [3], N_sop [3], fn2mx_tx_port[3] ,// in N[3] port + N_out_data[3], N_out_ready[3], N_out_valid[3], mx2fn_rx_port[3]) ;// out + axi_port_map_pcie N4 (N_in_data [4], N_ready [4], N_sop [4], fn2mx_tx_port[4] ,// in N[4] port + N_out_data[4], N_out_ready[4], N_out_valid[4], mx2fn_rx_port[4]) ;// out + // + switch # ( // M X N switch with output FIFO + .WIDTH ( WIDTH ) ,// Port Data Width + .M ( M ) ,// Number of M Ports + .N ( N ) ,// Number of N Ports + .DEPTH ( DEPTH ) // FIFO Depth=2**DEPTH + ) // + switch ( // ----------- input ----------------------------------- + M_in_data ,// Mux M to N ports data in + M_in_sop ,// Mux M to N ports end of packet + M_in_eop ,// Mux M to N ports end of packet + M_in_valid ,// Mux M to N ports data in valid + M_out_ready ,// Mux M to N ports data out ready from next stage logic + N_in_data ,// Mux N to M data in + N_in_sop ,// Mux N to M data in end of packet + N_in_eop ,// Mux N to M data in end of packet + N_in_valid ,// Mux N to M data in valid + N_out_ready ,// Mux N to M data out ready from next stage logic + rst_n ,// reset low active + clk ,// clock + //---------- output ---------------------------------- + M_in_ready ,// Mux M to N ready + M_out_valid ,// Mux M to N out valid + M_out_data ,// Mux M to N data out + N_in_ready ,// Mux N to M ready + N_out_valid ,// Mux N to M out valid + N_out_data ,// Mux N to M data out + out_q_err ,// N/M out_q FIFO error + out_q_perr // N/M out_q FIFO error + ) ;// +endmodule // +//============================================================================================================================================================== +// Port Mapping of AXI to switch port +//============================================================================================================================================================== +module axi_port_map_pcie #( + parameter D_WIDTH = DATA_WIDTH ,// Port Data Width + parameter M = 1 ,// Number of Host/Upstream ports + parameter N = 2 ,// Number of Function/Downstream ports + parameter USER_WIDTH = 10 ,// USER field width + parameter ERR_WIDTH = 10 ,// ERROR field width + parameter DEPTH = 2 ,// out_q fifo depth = 2**DEPTH + //-------------- AVST----------------------- + parameter DATA_LSB = 0 ,// if.data bit position of data LSB + parameter DATA_MSB = D_WIDTH - 1 ,// if.data bit position of data MSB + parameter VALID = DATA_MSB + 1 ,// if.data bit position of valid bit + parameter END = VALID + 1 ,// if.data bit position of end of pakcet + parameter START = END + 1 ,// if.data bit position of start of pakcet (for internal logic) + parameter ERR_LSB = START + 1 ,// if.data bit position of error LSB + parameter ERR_MSB = START + ERR_WIDTH ,// if.data bit position of error MSB + parameter EMPTY_LSB = ERR_MSB + 1 ,// if.data bit position of empty LSB + parameter EMPTY_MSB = ERR_MSB + $clog2(D_WIDTH/8) ,// if.data bit position of empty MSB + //------------- AXI ------------------------ + // DATA_LSB = 0 ,// if.data bit position of data LSB + // DATA_MSB = D_WIDTH - 1 ,// if.data bit position of data MSB + // VALID = DATA_MSB + 1 ,// if.data bit position of valid bit + parameter LAST = VALID + 1 ,// if.data bit position of last + // START = LAST + 1 ,// if.data bit position of start of pakcet + parameter USER_LSB = START + 1 ,// if.data bit position of user LSB + parameter USER_MSB = START + USER_WIDTH ,// if.data bit position of user MSB + parameter KEEP_LSB = USER_MSB + 1 ,// if.data bit position of keep LSB + parameter KEEP_MSB = USER_MSB + D_WIDTH/8 ,// if.data bit position of keep MSB + parameter WIDTH = KEEP_MSB + 1 // if.data width + )( // + output [WIDTH-1:0] in_port_data ,// switch port in data + input in_port_ready ,// switch port in ready + input in_port_sop ,// swtich port in sop (header valid) + pcie_ss_axis_if.sink in_interface ,// axi in interface + input [WIDTH-1:0] out_port_data ,// switch port out data + output out_port_ready ,// switch port out ready + input out_port_valid ,// switch port out valid + pcie_ss_axis_if.source out_interface // axi out interface + ) ;// map interface signals to port data bits + assign in_port_data [KEEP_MSB:KEEP_LSB] = in_interface.tkeep ;// only valid, ready, and last/eop are used for handshake + assign in_port_data [USER_MSB:USER_LSB] = in_interface.tuser_vendor ;// + assign in_port_data [START ] = in_port_sop ;// + assign in_port_data [LAST ] = in_interface.tlast ;// + assign in_port_data [VALID ] = in_interface.tvalid ;// + assign in_port_data [DATA_MSB:DATA_LSB] = in_interface.tdata ;// + assign in_interface.tready = in_port_ready ;// + // + assign out_interface.tkeep = out_port_data[KEEP_MSB:KEEP_LSB] ;// + assign out_interface.tuser_vendor = out_port_data[USER_MSB:USER_LSB] ;// + assign out_interface.tlast = out_port_data[LAST] ;// + assign out_interface.tvalid = out_port_valid ;// + assign out_interface.tdata = out_port_data[DATA_MSB:DATA_LSB] ;// + assign out_port_ready = out_interface.tready ;// +endmodule + // +//============================================================================================================================================================== +// Port Mapping of AVST to AXI switch port +//============================================================================================================================================================== +module avst_port_map #( + parameter D_WIDTH = DATA_WIDTH ,// Port Data Width + parameter M = 1 ,// Number of Host/Upstream ports + parameter N = 2 ,// Number of Function/Downstream ports + parameter USER_WIDTH = 10 ,// USER field width + parameter ERR_WIDTH = 10 ,// ERROR field width + parameter DEPTH = 2 ,// out_q fifo depth = 2**DEPTH + //-------------- AVST----------------------- + parameter DATA_LSB = 0 ,// if.data bit position of data LSB + parameter DATA_MSB = D_WIDTH - 1 ,// if.data bit position of data MSB + parameter VALID = DATA_MSB + 1 ,// if.data bit position of valid bit + parameter END = VALID + 1 ,// if.data bit position of end of pakcet + parameter START = END + 1 ,// if.data bit position of start of pakcet (for internal logic) + parameter ERR_LSB = START + 1 ,// if.data bit position of error LSB + parameter ERR_MSB = START + ERR_WIDTH ,// if.data bit position of error MSB + parameter EMPTY_LSB = ERR_MSB + 1 ,// if.data bit position of empty LSB + parameter EMPTY_MSB = ERR_MSB + $clog2(D_WIDTH/8) ,// if.data bit position of empty MSB + //------------- AXI ------------------------ + // DATA_LSB = 0 ,// if.data bit position of data LSB + // DATA_MSB = D_WIDTH - 1 ,// if.data bit position of data MSB + // VALID = DATA_MSB + 1 ,// if.data bit position of valid bit + parameter LAST = VALID + 1 ,// if.data bit position of last + // START = LAST + 1 ,// if.data bit position of start of pakcet + parameter USER_LSB = START + 1 ,// if.data bit position of user LSB + parameter USER_MSB = START + USER_WIDTH ,// if.data bit position of user MSB + parameter KEEP_LSB = USER_MSB + 1 ,// if.data bit position of keep LSB + parameter KEEP_MSB = USER_MSB + D_WIDTH/8 ,// if.data bit position of keep MSB + parameter WIDTH = KEEP_MSB + 1 // if.data width + )( // + output [WIDTH-1:0] in_port_data ,// switch port in data + input in_port_ready ,// switch port in ready + input in_port_sop ,// swtich port in sop (header valid) + ofs_avst_if.sink in_interface ,// avst in interface + input [WIDTH-1:0] out_port_data ,// switch port out data + output out_port_ready ,// switch port out ready + input out_port_valid ,// switch port out valid + ofs_avst_if.source out_interface // avst out interface + ) ;// + // + assign in_port_data [KEEP_MSB:KEEP_LSB] = empty_2_keep(in_interface.empty) ;// map interface signals to port data bits + assign in_port_data [USER_MSB:USER_LSB] = in_interface.error ;// only valid, ready, and last/eop are used for handshake + assign in_port_data [START ] = in_port_sop ;// + assign in_port_data [LAST ] = in_interface.eop ;// + assign in_port_data [VALID ] = in_interface.valid ;// + assign in_port_data [DATA_MSB:DATA_LSB] = in_interface.data ;// + assign in_interface.ready = in_port_ready ;// + // + assign out_interface.empty = keep_2_empty( out_port_data[KEEP_MSB:KEEP_LSB]);// + assign out_interface.error = out_port_data[USER_MSB:USER_LSB] ;// + assign out_interface.sop = out_port_data[START] ;// + assign out_interface.eop = out_port_data[LAST] ;// + assign out_interface.valid = out_port_valid ;// + assign out_interface.data = out_port_data[DATA_MSB:DATA_LSB] ;// + assign out_port_ready = out_interface.ready ;// + //------------------------------------------------------------------------------------------------------------------------------------------------------ + function [ D_WIDTH/8-1:0] empty_2_keep ;// Function: convert avst empty to axi keep + input [$clog2(D_WIDTH/8) :0] empty ;// Input: avst empty field + integer k ;// + empty_2_keep = ~0 ;// default to all 1s + for (k=1; k<=empty; k++) empty_2_keep[D_WIDTH/8-k] = 0 ;// set 0 top down until reach empty value + endfunction // + //------------------------------------------------------------------------------------------------------------------------------------------------------ + function [$clog2(D_WIDTH/8) :0] keep_2_empty ;// Function: convert axi keep to avst empty + input [ D_WIDTH/8-1:0] keep ;// Input: axi keep field + integer k ;// + keep_2_empty = 0 ;// default empty to 0 + for (k=1; k + + + Altera Corporation + apf + apf + 1.0 + + + + $${FILENAME} + $${FILENAME} + 1.0 + + + System + QsysPro + + + + + board + Board + Unknown + + + bonusData + bonusData + bonusData +{ + element $system + { + } + element apf_achk_slv + { + datum _sortIndex + { + value = "7"; + type = "int"; + } + } + element apf_bpf_mst + { + datum _sortIndex + { + value = "2"; + type = "int"; + } + } + element apf_bpf_slv + { + datum _sortIndex + { + value = "3"; + type = "int"; + } + } + element apf_clock_bridge + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } + element apf_pgsk_slv + { + datum _sortIndex + { + value = "6"; + type = "int"; + } + } + element apf_reset_bridge + { + datum _sortIndex + { + value = "1"; + type = "int"; + } + } + element apf_rsv_b_slv + { + datum _sortIndex + { + value = "8"; + type = "int"; + } + } + element apf_rsv_c_slv + { + datum _sortIndex + { + value = "9"; + type = "int"; + } + } + element apf_rsv_d_slv + { + datum _sortIndex + { + value = "10"; + type = "int"; + } + } + element apf_rsv_e_slv + { + datum _sortIndex + { + value = "11"; + type = "int"; + } + } + element apf_rsv_f_slv + { + datum _sortIndex + { + value = "12"; + type = "int"; + } + } + element apf_st2mm_mst + { + datum _sortIndex + { + value = "4"; + type = "int"; + } + } + element apf_st2mm_slv + { + datum _sortIndex + { + value = "5"; + type = "int"; + } + } +} + + + + designId + designId + + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + fabricMode + fabricMode + QSYS + + + generateLegacySim + generateLegacySim + false + + + generationId + Generation Id + 0 + + + globalResetBus + Global reset + false + + + hdlLanguage + hdlLanguage + VERILOG + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + + + + sopcBorderPoints + Use SOPC Builder port naming + false + + + systemHash + systemHash + 0 + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + systemScripts + systemScripts + + + + testBenchDutName + Use Test Bench Naming Pattern + + + + timeStamp + timeStamp + 0 + + + useTestBenchNamingPattern + Use Test Bench Naming Pattern + false + + + + + + + + + Altera Corporation + apf_achk_slv + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>axi4lite_shim</className> + <version>1.0</version> + <displayName>axi4lite_shim</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>apf_achk_slv</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>apf_achk_slv</fileSetName> + <fileSetFixedName>apf_achk_slv</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_achk_slv</fileSetName> + <fileSetFixedName>apf_achk_slv</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_achk_slv</fileSetName> + <fileSetFixedName>apf_achk_slv</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_achk_slv</fileSetName> + <fileSetFixedName>apf_achk_slv</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/apf/apf_achk_slv.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + apf_bpf_mst + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>axi4lite_shim</className> + <version>1.0</version> + <displayName>axi4lite_shim</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>apf_bpf_mst</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>apf_bpf_mst</fileSetName> + <fileSetFixedName>apf_bpf_mst</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_bpf_mst</fileSetName> + <fileSetFixedName>apf_bpf_mst</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_bpf_mst</fileSetName> + <fileSetFixedName>apf_bpf_mst</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_bpf_mst</fileSetName> + <fileSetFixedName>apf_bpf_mst</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/apf/apf_bpf_mst.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + apf_bpf_slv + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>axi4lite_shim</className> + <version>1.0</version> + <displayName>axi4lite_shim</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>apf_bpf_slv</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>apf_bpf_slv</fileSetName> + <fileSetFixedName>apf_bpf_slv</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_bpf_slv</fileSetName> + <fileSetFixedName>apf_bpf_slv</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_bpf_slv</fileSetName> + <fileSetFixedName>apf_bpf_slv</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_bpf_slv</fileSetName> + <fileSetFixedName>apf_bpf_slv</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/apf/apf_bpf_slv.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + apf_clock_bridge + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>in_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>in_clk</value> + </entry> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>false</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_clock_bridge</className> + <version>19.2.0</version> + <displayName>Clock Bridge Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>DERIVED_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>in_clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>in_clk</key> + <value> + <connectionPointName>in_clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>out_clk</key> + <value> + <connectionPointName>out_clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>in_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>in_clk</value> + </entry> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>false</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>apf_clock_bridge</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>apf_clock_bridge</fileSetName> + <fileSetFixedName>apf_clock_bridge</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_clock_bridge</fileSetName> + <fileSetFixedName>apf_clock_bridge</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_clock_bridge</fileSetName> + <fileSetFixedName>apf_clock_bridge</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_clock_bridge</fileSetName> + <fileSetFixedName>apf_clock_bridge</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/apf/apf_clock_bridge.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + apf_pgsk_slv + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>axi4lite_shim</className> + <version>1.0</version> + <displayName>axi4lite_shim</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>apf_pgsk_slv</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>apf_pgsk_slv</fileSetName> + <fileSetFixedName>apf_pgsk_slv</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_pgsk_slv</fileSetName> + <fileSetFixedName>apf_pgsk_slv</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_pgsk_slv</fileSetName> + <fileSetFixedName>apf_pgsk_slv</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_pgsk_slv</fileSetName> + <fileSetFixedName>apf_pgsk_slv</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/apf/apf_pgsk_slv.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + apf_reset_bridge + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_reset_n</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_reset_bridge</className> + <version>19.2.0</version> + <displayName>Reset Bridge Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_CLK_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>-1</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_reset_n</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>apf_reset_bridge</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>apf_reset_bridge</fileSetName> + <fileSetFixedName>apf_reset_bridge</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_reset_bridge</fileSetName> + <fileSetFixedName>apf_reset_bridge</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_reset_bridge</fileSetName> + <fileSetFixedName>apf_reset_bridge</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_reset_bridge</fileSetName> + <fileSetFixedName>apf_reset_bridge</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/apf/apf_reset_bridge.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + apf_rsv_b_slv + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>axi4lite_shim</className> + <version>1.0</version> + <displayName>axi4lite_shim</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>apf_rsv_b_slv</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>apf_rsv_b_slv</fileSetName> + <fileSetFixedName>apf_rsv_b_slv</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_rsv_b_slv</fileSetName> + <fileSetFixedName>apf_rsv_b_slv</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_rsv_b_slv</fileSetName> + <fileSetFixedName>apf_rsv_b_slv</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_rsv_b_slv</fileSetName> + <fileSetFixedName>apf_rsv_b_slv</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/apf/apf_rsv_b_slv.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + apf_rsv_c_slv + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>axi4lite_shim</className> + <version>1.0</version> + <displayName>axi4lite_shim</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>apf_rsv_c_slv</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>apf_rsv_c_slv</fileSetName> + <fileSetFixedName>apf_rsv_c_slv</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_rsv_c_slv</fileSetName> + <fileSetFixedName>apf_rsv_c_slv</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_rsv_c_slv</fileSetName> + <fileSetFixedName>apf_rsv_c_slv</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_rsv_c_slv</fileSetName> + <fileSetFixedName>apf_rsv_c_slv</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/apf/apf_rsv_c_slv.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + apf_rsv_d_slv + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>axi4lite_shim</className> + <version>1.0</version> + <displayName>axi4lite_shim</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>apf_rsv_d_slv</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>apf_rsv_d_slv</fileSetName> + <fileSetFixedName>apf_rsv_d_slv</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_rsv_d_slv</fileSetName> + <fileSetFixedName>apf_rsv_d_slv</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_rsv_d_slv</fileSetName> + <fileSetFixedName>apf_rsv_d_slv</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_rsv_d_slv</fileSetName> + <fileSetFixedName>apf_rsv_d_slv</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/apf/apf_rsv_d_slv.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + apf_rsv_e_slv + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>axi4lite_shim</className> + <version>1.0</version> + <displayName>axi4lite_shim</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>apf_rsv_e_slv</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>apf_rsv_e_slv</fileSetName> + <fileSetFixedName>apf_rsv_e_slv</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_rsv_e_slv</fileSetName> + <fileSetFixedName>apf_rsv_e_slv</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_rsv_e_slv</fileSetName> + <fileSetFixedName>apf_rsv_e_slv</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_rsv_e_slv</fileSetName> + <fileSetFixedName>apf_rsv_e_slv</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/apf/apf_rsv_e_slv.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + apf_rsv_f_slv + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>axi4lite_shim</className> + <version>1.0</version> + <displayName>axi4lite_shim</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>apf_rsv_f_slv</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>apf_rsv_f_slv</fileSetName> + <fileSetFixedName>apf_rsv_f_slv</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_rsv_f_slv</fileSetName> + <fileSetFixedName>apf_rsv_f_slv</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_rsv_f_slv</fileSetName> + <fileSetFixedName>apf_rsv_f_slv</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_rsv_f_slv</fileSetName> + <fileSetFixedName>apf_rsv_f_slv</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/apf/apf_rsv_f_slv.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + apf_st2mm_mst + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>axi4lite_shim</className> + <version>1.0</version> + <displayName>axi4lite_shim</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>apf_st2mm_mst</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>apf_st2mm_mst</fileSetName> + <fileSetFixedName>apf_st2mm_mst</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_st2mm_mst</fileSetName> + <fileSetFixedName>apf_st2mm_mst</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_st2mm_mst</fileSetName> + <fileSetFixedName>apf_st2mm_mst</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_st2mm_mst</fileSetName> + <fileSetFixedName>apf_st2mm_mst</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/apf/apf_st2mm_mst.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + apf_st2mm_slv + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>axi4lite_shim</className> + <version>1.0</version> + <displayName>axi4lite_shim</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>apf_st2mm_slv</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>apf_st2mm_slv</fileSetName> + <fileSetFixedName>apf_st2mm_slv</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_st2mm_slv</fileSetName> + <fileSetFixedName>apf_st2mm_slv</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_st2mm_slv</fileSetName> + <fileSetFixedName>apf_st2mm_slv</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>apf_st2mm_slv</fileSetName> + <fileSetFixedName>apf_st2mm_slv</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/apf/apf_st2mm_slv.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Intel Corporation + addressMap + addressMap + 1.0 + + + apf_achk_slv.altera_axi4lite_master + + + + + apf_st2mm_slv.altera_axi4lite_slave + + + + apf_bpf_mst.altera_axi4lite_master + + + + 0x0000_0000 + + + + + apf_bpf_slv.altera_axi4lite_master + + + + + apf_pgsk_slv.altera_axi4lite_master + + + + + apf_rsv_b_slv.altera_axi4lite_master + + + + + apf_rsv_c_slv.altera_axi4lite_master + + + + + apf_rsv_d_slv.altera_axi4lite_master + + + + + apf_rsv_e_slv.altera_axi4lite_master + + + + + apf_rsv_f_slv.altera_axi4lite_master + + + + + apf_bpf_slv.altera_axi4lite_slave + + + + apf_st2mm_slv.altera_axi4lite_slave + + + + apf_pgsk_slv.altera_axi4lite_slave + + + + apf_achk_slv.altera_axi4lite_slave + + + + apf_rsv_b_slv.altera_axi4lite_slave + + + + apf_rsv_c_slv.altera_axi4lite_slave + + + + apf_rsv_d_slv.altera_axi4lite_slave + + + + apf_rsv_e_slv.altera_axi4lite_slave + + + + apf_rsv_f_slv.altera_axi4lite_slave + + + + apf_st2mm_mst.altera_axi4lite_master + + + + 0x0000_0000 + + + + + apf_st2mm_slv.altera_axi4lite_master + + + + + + + apf_bpf_mst.altera_axi4lite_master + + + apf_st2mm_slv.altera_axi4lite_slave + 0x0000_0000 + 0x0001_0000 + + + + + apf_st2mm_mst.altera_axi4lite_master + + + apf_bpf_slv.altera_axi4lite_slave + 0x0000_0000 + 0x0008_0000 + + + apf_st2mm_slv.altera_axi4lite_slave + 0x0008_0000 + 0x0001_0000 + + + apf_pgsk_slv.altera_axi4lite_slave + 0x0009_0000 + 0x0001_0000 + + + apf_achk_slv.altera_axi4lite_slave + 0x000a_0000 + 0x0001_0000 + + + apf_rsv_b_slv.altera_axi4lite_slave + 0x000b_0000 + 0x0001_0000 + + + apf_rsv_c_slv.altera_axi4lite_slave + 0x000c_0000 + 0x0001_0000 + + + apf_rsv_d_slv.altera_axi4lite_slave + 0x000d_0000 + 0x0001_0000 + + + apf_rsv_e_slv.altera_axi4lite_slave + 0x000e_0000 + 0x0001_0000 + + + apf_rsv_f_slv.altera_axi4lite_slave + 0x000f_0000 + 0x0001_0000 + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/apf.qsys.legacy b/src/pd_qsys/fabric/apf.qsys.legacy new file mode 100644 index 0000000..effc079 --- /dev/null +++ b/src/pd_qsys/fabric/apf.qsys.legacy @@ -0,0 +1,13219 @@ + + + + + + + + + + + + + + + + + + + + + + + clk + + clk + + + CLOCK_RATE + + + + + + +]]> + + + + + + + + + + + + + + + + + + + + + + + + clock + clock + false + + + clk + clk + Input + 1 + 0 + STD_LOGIC + 0 + + + + + + + + + clockRate + 0 + + + externallyDriven + false + + + ptfSchematicName + + + + + + reset + reset + false + + + rst_n + reset_n + Input + 1 + 0 + STD_LOGIC + 0 + + + + + + + + + associatedClock + clock + + + synchronousEdges + DEASSERT + + + + + + altera_axi4lite_slave + axi4lite + false + + + s_awaddr + awaddr + Input + 16 + 0 + STD_LOGIC_VECTOR + 0 + + + s_awprot + awprot + Input + 3 + 0 + STD_LOGIC_VECTOR + 0 + + + s_awvalid + awvalid + Input + 1 + 0 + STD_LOGIC + 0 + + + s_awready + awready + Output + 1 + 0 + STD_LOGIC + 0 + + + s_wdata + wdata + Input + 64 + 0 + STD_LOGIC_VECTOR + 0 + + + s_wstrb + wstrb + Input + 8 + 0 + STD_LOGIC_VECTOR + 0 + + + s_wvalid + wvalid + Input + 1 + 0 + STD_LOGIC + 0 + + + s_wready + wready + Output + 1 + 0 + STD_LOGIC + 0 + + + s_bresp + bresp + Output + 2 + 0 + STD_LOGIC_VECTOR + 0 + + + s_bvalid + bvalid + Output + 1 + 0 + STD_LOGIC + 0 + + + s_bready + bready + Input + 1 + 0 + STD_LOGIC + 0 + + + s_araddr + araddr + Input + 16 + 0 + STD_LOGIC_VECTOR + 0 + + + s_arprot + arprot + Input + 3 + 0 + STD_LOGIC_VECTOR + 0 + + + s_arvalid + arvalid + Input + 1 + 0 + STD_LOGIC + 0 + + + s_arready + arready + Output + 1 + 0 + STD_LOGIC + 0 + + + s_rdata + rdata + Output + 64 + 0 + STD_LOGIC_VECTOR + 0 + + + s_rresp + rresp + Output + 2 + 0 + STD_LOGIC_VECTOR + 0 + + + s_rvalid + rvalid + Output + 1 + 0 + STD_LOGIC + 0 + + + s_rready + rready + Input + 1 + 0 + STD_LOGIC + 0 + + + + + + + + + associatedClock + clock + + + associatedReset + reset + + + trustzoneAware + true + + + maximumOutstandingReads + 16 + + + maximumOutstandingWrites + 16 + + + maximumOutstandingTransactions + 16 + + + readAcceptanceCapability + 16 + + + writeAcceptanceCapability + 16 + + + combinedAcceptanceCapability + 16 + + + readDataReorderingDepth + 1 + + + bridgesToMaster + + + + + + altera_axi4lite_master + axi4lite + true + + + m_awaddr + awaddr + Output + 16 + 0 + STD_LOGIC_VECTOR + 0 + + + m_awprot + awprot + Output + 3 + 0 + STD_LOGIC_VECTOR + 0 + + + m_awvalid + awvalid + Output + 1 + 0 + STD_LOGIC + 0 + + + m_awready + awready + Input + 1 + 0 + STD_LOGIC + 0 + + + m_wdata + wdata + Output + 64 + 0 + STD_LOGIC_VECTOR + 0 + + + m_wstrb + wstrb + Output + 8 + 0 + STD_LOGIC_VECTOR + 0 + + + m_wvalid + wvalid + Output + 1 + 0 + STD_LOGIC + 0 + + + m_wready + wready + Input + 1 + 0 + STD_LOGIC + 0 + + + m_bresp + bresp + Input + 2 + 0 + STD_LOGIC_VECTOR + 0 + + + m_bvalid + bvalid + Input + 1 + 0 + STD_LOGIC + 0 + + + m_bready + bready + Output + 1 + 0 + STD_LOGIC + 0 + + + m_araddr + araddr + Output + 16 + 0 + STD_LOGIC_VECTOR + 0 + + + m_arprot + arprot + Output + 3 + 0 + STD_LOGIC_VECTOR + 0 + + + m_arvalid + arvalid + Output + 1 + 0 + STD_LOGIC + 0 + + + m_arready + arready + Input + 1 + 0 + STD_LOGIC + 0 + + + m_rdata + rdata + Input + 64 + 0 + STD_LOGIC_VECTOR + 0 + + + m_rresp + rresp + Input + 2 + 0 + STD_LOGIC_VECTOR + 0 + + + m_rvalid + rvalid + Input + 1 + 0 + STD_LOGIC + 0 + + + m_rready + rready + Output + 1 + 0 + STD_LOGIC + 0 + + + + + + + + + associatedClock + clock + + + associatedReset + reset + + + trustzoneAware + true + + + maximumOutstandingReads + 16 + + + maximumOutstandingWrites + 16 + + + maximumOutstandingTransactions + 16 + + + readIssuingCapability + 16 + + + writeIssuingCapability + 16 + + + combinedIssuingCapability + 16 + + + enableConcurrentSubordinateAccess + 0 + + + noRepeatedIdsBetweenSubordinates + 0 + + + + + + + + axi4lite_shim + 1.0 + axi4lite_shim + + + + + + + +]]> + + + + clock + clock + false + + + clk + clk + Input + 1 + 0 + STD_LOGIC + 0 + + + + + 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+ + + + + + + + + diff --git a/src/pd_qsys/fabric/apf.tcl b/src/pd_qsys/fabric/apf.tcl new file mode 100644 index 0000000..a17a4de --- /dev/null +++ b/src/pd_qsys/fabric/apf.tcl @@ -0,0 +1,1287 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +package require -exact qsys 18.0 + + # create the system + create_system apf + set_project_property DEVICE 1SX280HN2F43E2VG + set_project_property DEVICE_FAMILY Stratix10 + set_project_property HIDE_FROM_IP_CATALOG {false} + set_use_testbench_naming_pattern 0 {} + + + # add the components + add_component apf_clock_bridge ip/apf/apf_clock_bridge.ip altera_clock_bridge apf_clock_bridge + load_component apf_clock_bridge + set_component_parameter_value EXPLICIT_CLOCK_RATE {0.0} + set_component_parameter_value NUM_CLOCK_OUTPUTS {1} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation apf_clock_bridge + remove_instantiation_interfaces_and_ports + add_instantiation_interface in_clk clock INPUT + set_instantiation_interface_parameter_value in_clk clockRate {0} + set_instantiation_interface_parameter_value in_clk externallyDriven {false} + set_instantiation_interface_parameter_value in_clk ptfSchematicName {} + add_instantiation_interface_port in_clk in_clk clk 1 STD_LOGIC Input + add_instantiation_interface out_clk clock OUTPUT + set_instantiation_interface_parameter_value out_clk associatedDirectClock {in_clk} + set_instantiation_interface_parameter_value out_clk clockRate {0} + set_instantiation_interface_parameter_value out_clk clockRateKnown {false} + set_instantiation_interface_parameter_value out_clk externallyDriven {false} + set_instantiation_interface_parameter_value out_clk ptfSchematicName {} + set_instantiation_interface_sysinfo_parameter_value out_clk clock_rate {0} + add_instantiation_interface_port out_clk out_clk clk 1 STD_LOGIC Output + save_instantiation + + add_component apf_reset_bridge ip/apf/apf_reset_bridge.ip altera_reset_bridge apf_reset_bridge + load_component apf_reset_bridge + set_component_parameter_value ACTIVE_LOW_RESET {1} + set_component_parameter_value NUM_RESET_OUTPUTS {1} + set_component_parameter_value SYNCHRONOUS_EDGES {deassert} + set_component_parameter_value SYNC_RESET {0} + set_component_parameter_value USE_RESET_REQUEST {0} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation apf_reset_bridge + remove_instantiation_interfaces_and_ports + add_instantiation_interface clk clock INPUT + set_instantiation_interface_parameter_value clk clockRate {0} + set_instantiation_interface_parameter_value clk externallyDriven {false} + set_instantiation_interface_parameter_value clk ptfSchematicName {} + add_instantiation_interface_port clk clk clk 1 STD_LOGIC Input + add_instantiation_interface in_reset reset INPUT + set_instantiation_interface_parameter_value in_reset associatedClock {clk} + set_instantiation_interface_parameter_value in_reset synchronousEdges {DEASSERT} + add_instantiation_interface_port in_reset in_reset_n reset_n 1 STD_LOGIC Input + add_instantiation_interface out_reset reset OUTPUT + set_instantiation_interface_parameter_value out_reset associatedClock {clk} + set_instantiation_interface_parameter_value out_reset associatedDirectReset {in_reset} + set_instantiation_interface_parameter_value out_reset associatedResetSinks {in_reset} + set_instantiation_interface_parameter_value out_reset synchronousEdges {DEASSERT} + add_instantiation_interface_port out_reset out_reset_n reset_n 1 STD_LOGIC Output + save_instantiation + + # add the connections + add_connection apf_clock_bridge.out_clk/apf_reset_bridge.clk + set_connection_parameter_value apf_clock_bridge.out_clk/apf_reset_bridge.clk clockDomainSysInfo {-1} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_reset_bridge.clk clockRateSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_reset_bridge.clk clockResetSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_reset_bridge.clk resetDomainSysInfo {-1} + + # add the exports + set_interface_property clk EXPORT_OF apf_clock_bridge.in_clk + set_interface_property rst_n EXPORT_OF apf_reset_bridge.in_reset + add_component apf_bpf_mst ip/apf/apf_bpf_mst.ip axi4lite_shim apf_bpf_mst 1.0 + load_component apf_bpf_mst + set_component_parameter_value AW {20} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation apf_bpf_mst + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr 20 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr 20 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {16/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr 20 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr 20 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + + add_connection apf_clock_bridge.out_clk/apf_bpf_mst.clock + set_connection_parameter_value apf_clock_bridge.out_clk/apf_bpf_mst.clock clockDomainSysInfo {-1} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_bpf_mst.clock clockRateSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_bpf_mst.clock clockResetSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_bpf_mst.clock resetDomainSysInfo {-1} + add_connection apf_reset_bridge.out_reset/apf_bpf_mst.reset + set_connection_parameter_value apf_reset_bridge.out_reset/apf_bpf_mst.reset clockDomainSysInfo {-1} + set_connection_parameter_value apf_reset_bridge.out_reset/apf_bpf_mst.reset clockResetSysInfo {} + set_connection_parameter_value apf_reset_bridge.out_reset/apf_bpf_mst.reset resetDomainSysInfo {-1} + set_interface_property apf_bpf_mst EXPORT_OF apf_bpf_mst.altera_axi4lite_slave + add_component apf_bpf_slv ip/apf/apf_bpf_slv.ip axi4lite_shim apf_bpf_slv 1.0 + load_component apf_bpf_slv + set_component_parameter_value AW {19} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation apf_bpf_slv + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {16/4} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr 19 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr 19 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {16/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr 19 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr 19 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + + add_connection apf_clock_bridge.out_clk/apf_bpf_slv.clock + set_connection_parameter_value apf_clock_bridge.out_clk/apf_bpf_slv.clock clockDomainSysInfo {-1} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_bpf_slv.clock clockRateSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_bpf_slv.clock clockResetSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_bpf_slv.clock resetDomainSysInfo {-1} + add_connection apf_reset_bridge.out_reset/apf_bpf_slv.reset + set_connection_parameter_value apf_reset_bridge.out_reset/apf_bpf_slv.reset clockDomainSysInfo {-1} + set_connection_parameter_value apf_reset_bridge.out_reset/apf_bpf_slv.reset clockResetSysInfo {} + set_connection_parameter_value apf_reset_bridge.out_reset/apf_bpf_slv.reset resetDomainSysInfo {-1} + set_interface_property apf_bpf_slv EXPORT_OF apf_bpf_slv.altera_axi4lite_master + add_component apf_st2mm_mst ip/apf/apf_st2mm_mst.ip axi4lite_shim apf_st2mm_mst 1.0 + load_component apf_st2mm_mst + set_component_parameter_value AW {20} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation apf_st2mm_mst + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr 20 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr 20 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {16/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr 20 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr 20 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + + add_connection apf_clock_bridge.out_clk/apf_st2mm_mst.clock + set_connection_parameter_value apf_clock_bridge.out_clk/apf_st2mm_mst.clock clockDomainSysInfo {-1} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_st2mm_mst.clock clockRateSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_st2mm_mst.clock clockResetSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_st2mm_mst.clock resetDomainSysInfo {-1} + add_connection apf_reset_bridge.out_reset/apf_st2mm_mst.reset + set_connection_parameter_value apf_reset_bridge.out_reset/apf_st2mm_mst.reset clockDomainSysInfo {-1} + set_connection_parameter_value apf_reset_bridge.out_reset/apf_st2mm_mst.reset clockResetSysInfo {} + set_connection_parameter_value apf_reset_bridge.out_reset/apf_st2mm_mst.reset resetDomainSysInfo {-1} + set_interface_property apf_st2mm_mst EXPORT_OF apf_st2mm_mst.altera_axi4lite_slave + add_component apf_st2mm_slv ip/apf/apf_st2mm_slv.ip axi4lite_shim apf_st2mm_slv 1.0 + load_component apf_st2mm_slv + set_component_parameter_value AW {16} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation apf_st2mm_slv + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {16/4} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {16/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + + add_component apf_pgsk_slv ip/apf/apf_pgsk_slv.ip axi4lite_shim apf_pgsk_slv 1.0 + load_component apf_pgsk_slv + set_component_parameter_value AW {16} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation apf_pgsk_slv + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {16/4} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {16/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + + add_component apf_achk_slv ip/apf/apf_achk_slv.ip axi4lite_shim apf_achk_slv 1.0 + load_component apf_achk_slv + set_component_parameter_value AW {16} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation apf_achk_slv + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {16/4} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {16/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + + add_component apf_rsv_b_slv ip/apf/apf_rsv_b_slv.ip axi4lite_shim apf_rsv_b_slv 1.0 + load_component apf_rsv_b_slv + set_component_parameter_value AW {16} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation apf_rsv_b_slv + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {16/4} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {16/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + + add_component apf_rsv_c_slv ip/apf/apf_rsv_c_slv.ip axi4lite_shim apf_rsv_c_slv 1.0 + load_component apf_rsv_c_slv + set_component_parameter_value AW {16} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation apf_rsv_c_slv + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {16/4} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {16/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + + add_component apf_rsv_d_slv ip/apf/apf_rsv_d_slv.ip axi4lite_shim apf_rsv_d_slv 1.0 + load_component apf_rsv_d_slv + set_component_parameter_value AW {16} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation apf_rsv_d_slv + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {16/4} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {16/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + + add_component apf_rsv_e_slv ip/apf/apf_rsv_e_slv.ip axi4lite_shim apf_rsv_e_slv 1.0 + load_component apf_rsv_e_slv + set_component_parameter_value AW {16} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation apf_rsv_e_slv + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {16/4} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {16/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + + add_component apf_rsv_f_slv ip/apf/apf_rsv_f_slv.ip axi4lite_shim apf_rsv_f_slv 1.0 + load_component apf_rsv_f_slv + set_component_parameter_value AW {16} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation apf_rsv_f_slv + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {16/4} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {16/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + + add_connection apf_st2mm_mst.altera_axi4lite_master/apf_bpf_slv.altera_axi4lite_slave + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_bpf_slv.altera_axi4lite_slave addressMapSysInfo {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_bpf_slv.altera_axi4lite_slave addressWidthSysInfo {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_bpf_slv.altera_axi4lite_slave arbitrationPriority {1} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_bpf_slv.altera_axi4lite_slave baseAddress {0} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_bpf_slv.altera_axi4lite_slave defaultConnection {0} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_bpf_slv.altera_axi4lite_slave domainAlias {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_bpf_slv.altera_axi4lite_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_bpf_slv.altera_axi4lite_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_bpf_slv.altera_axi4lite_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_bpf_slv.altera_axi4lite_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_bpf_slv.altera_axi4lite_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_bpf_slv.altera_axi4lite_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_bpf_slv.altera_axi4lite_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_bpf_slv.altera_axi4lite_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_bpf_slv.altera_axi4lite_slave qsys_mm.syncResets {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_bpf_slv.altera_axi4lite_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_bpf_slv.altera_axi4lite_slave slaveDataWidthSysInfo {-1} + + add_connection apf_bpf_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave + set_connection_parameter_value apf_bpf_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave addressMapSysInfo {} + set_connection_parameter_value apf_bpf_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave addressWidthSysInfo {} + set_connection_parameter_value apf_bpf_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave arbitrationPriority {1} + set_connection_parameter_value apf_bpf_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave baseAddress {0} + set_connection_parameter_value apf_bpf_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave defaultConnection {0} + set_connection_parameter_value apf_bpf_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave domainAlias {} + set_connection_parameter_value apf_bpf_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value apf_bpf_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value apf_bpf_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value apf_bpf_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value apf_bpf_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value apf_bpf_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value apf_bpf_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value apf_bpf_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value apf_bpf_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave qsys_mm.syncResets {FALSE} + set_connection_parameter_value apf_bpf_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value apf_bpf_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave slaveDataWidthSysInfo {-1} + + add_connection apf_clock_bridge.out_clk/apf_st2mm_slv.clock + set_connection_parameter_value apf_clock_bridge.out_clk/apf_st2mm_slv.clock clockDomainSysInfo {-1} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_st2mm_slv.clock clockRateSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_st2mm_slv.clock clockResetSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_st2mm_slv.clock resetDomainSysInfo {-1} + add_connection apf_reset_bridge.out_reset/apf_st2mm_slv.reset + set_connection_parameter_value apf_reset_bridge.out_reset/apf_st2mm_slv.reset clockDomainSysInfo {-1} + set_connection_parameter_value apf_reset_bridge.out_reset/apf_st2mm_slv.reset clockResetSysInfo {} + set_connection_parameter_value apf_reset_bridge.out_reset/apf_st2mm_slv.reset resetDomainSysInfo {-1} + add_connection apf_st2mm_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave addressMapSysInfo {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave addressWidthSysInfo {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave arbitrationPriority {1} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave baseAddress {0x080000} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave defaultConnection {0} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave domainAlias {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave qsys_mm.syncResets {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_st2mm_slv.altera_axi4lite_slave slaveDataWidthSysInfo {-1} + + add_connection apf_clock_bridge.out_clk/apf_pgsk_slv.clock + set_connection_parameter_value apf_clock_bridge.out_clk/apf_pgsk_slv.clock clockDomainSysInfo {-1} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_pgsk_slv.clock clockRateSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_pgsk_slv.clock clockResetSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_pgsk_slv.clock resetDomainSysInfo {-1} + add_connection apf_reset_bridge.out_reset/apf_pgsk_slv.reset + set_connection_parameter_value apf_reset_bridge.out_reset/apf_pgsk_slv.reset clockDomainSysInfo {-1} + set_connection_parameter_value apf_reset_bridge.out_reset/apf_pgsk_slv.reset clockResetSysInfo {} + set_connection_parameter_value apf_reset_bridge.out_reset/apf_pgsk_slv.reset resetDomainSysInfo {-1} + add_connection apf_st2mm_mst.altera_axi4lite_master/apf_pgsk_slv.altera_axi4lite_slave + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_pgsk_slv.altera_axi4lite_slave addressMapSysInfo {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_pgsk_slv.altera_axi4lite_slave addressWidthSysInfo {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_pgsk_slv.altera_axi4lite_slave arbitrationPriority {1} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_pgsk_slv.altera_axi4lite_slave baseAddress {0x090000} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_pgsk_slv.altera_axi4lite_slave defaultConnection {0} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_pgsk_slv.altera_axi4lite_slave domainAlias {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_pgsk_slv.altera_axi4lite_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_pgsk_slv.altera_axi4lite_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_pgsk_slv.altera_axi4lite_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_pgsk_slv.altera_axi4lite_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_pgsk_slv.altera_axi4lite_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_pgsk_slv.altera_axi4lite_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_pgsk_slv.altera_axi4lite_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_pgsk_slv.altera_axi4lite_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_pgsk_slv.altera_axi4lite_slave qsys_mm.syncResets {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_pgsk_slv.altera_axi4lite_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_pgsk_slv.altera_axi4lite_slave slaveDataWidthSysInfo {-1} + + add_connection apf_clock_bridge.out_clk/apf_achk_slv.clock + set_connection_parameter_value apf_clock_bridge.out_clk/apf_achk_slv.clock clockDomainSysInfo {-1} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_achk_slv.clock clockRateSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_achk_slv.clock clockResetSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_achk_slv.clock resetDomainSysInfo {-1} + add_connection apf_reset_bridge.out_reset/apf_achk_slv.reset + set_connection_parameter_value apf_reset_bridge.out_reset/apf_achk_slv.reset clockDomainSysInfo {-1} + set_connection_parameter_value apf_reset_bridge.out_reset/apf_achk_slv.reset clockResetSysInfo {} + set_connection_parameter_value apf_reset_bridge.out_reset/apf_achk_slv.reset resetDomainSysInfo {-1} + add_connection apf_st2mm_mst.altera_axi4lite_master/apf_achk_slv.altera_axi4lite_slave + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_achk_slv.altera_axi4lite_slave addressMapSysInfo {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_achk_slv.altera_axi4lite_slave addressWidthSysInfo {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_achk_slv.altera_axi4lite_slave arbitrationPriority {1} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_achk_slv.altera_axi4lite_slave baseAddress {0x0a0000} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_achk_slv.altera_axi4lite_slave defaultConnection {0} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_achk_slv.altera_axi4lite_slave domainAlias {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_achk_slv.altera_axi4lite_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_achk_slv.altera_axi4lite_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_achk_slv.altera_axi4lite_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_achk_slv.altera_axi4lite_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_achk_slv.altera_axi4lite_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_achk_slv.altera_axi4lite_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_achk_slv.altera_axi4lite_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_achk_slv.altera_axi4lite_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_achk_slv.altera_axi4lite_slave qsys_mm.syncResets {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_achk_slv.altera_axi4lite_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_achk_slv.altera_axi4lite_slave slaveDataWidthSysInfo {-1} + + add_connection apf_clock_bridge.out_clk/apf_rsv_b_slv.clock + set_connection_parameter_value apf_clock_bridge.out_clk/apf_rsv_b_slv.clock clockDomainSysInfo {-1} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_rsv_b_slv.clock clockRateSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_rsv_b_slv.clock clockResetSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_rsv_b_slv.clock resetDomainSysInfo {-1} + add_connection apf_reset_bridge.out_reset/apf_rsv_b_slv.reset + set_connection_parameter_value apf_reset_bridge.out_reset/apf_rsv_b_slv.reset clockDomainSysInfo {-1} + set_connection_parameter_value apf_reset_bridge.out_reset/apf_rsv_b_slv.reset clockResetSysInfo {} + set_connection_parameter_value apf_reset_bridge.out_reset/apf_rsv_b_slv.reset resetDomainSysInfo {-1} + add_connection apf_st2mm_mst.altera_axi4lite_master/apf_rsv_b_slv.altera_axi4lite_slave + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_b_slv.altera_axi4lite_slave addressMapSysInfo {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_b_slv.altera_axi4lite_slave addressWidthSysInfo {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_b_slv.altera_axi4lite_slave arbitrationPriority {1} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_b_slv.altera_axi4lite_slave baseAddress {0x0b0000} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_b_slv.altera_axi4lite_slave defaultConnection {0} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_b_slv.altera_axi4lite_slave domainAlias {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_b_slv.altera_axi4lite_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_b_slv.altera_axi4lite_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_b_slv.altera_axi4lite_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_b_slv.altera_axi4lite_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_b_slv.altera_axi4lite_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_b_slv.altera_axi4lite_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_b_slv.altera_axi4lite_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_b_slv.altera_axi4lite_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_b_slv.altera_axi4lite_slave qsys_mm.syncResets {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_b_slv.altera_axi4lite_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_b_slv.altera_axi4lite_slave slaveDataWidthSysInfo {-1} + + add_connection apf_clock_bridge.out_clk/apf_rsv_c_slv.clock + set_connection_parameter_value apf_clock_bridge.out_clk/apf_rsv_c_slv.clock clockDomainSysInfo {-1} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_rsv_c_slv.clock clockRateSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_rsv_c_slv.clock clockResetSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_rsv_c_slv.clock resetDomainSysInfo {-1} + add_connection apf_reset_bridge.out_reset/apf_rsv_c_slv.reset + set_connection_parameter_value apf_reset_bridge.out_reset/apf_rsv_c_slv.reset clockDomainSysInfo {-1} + set_connection_parameter_value apf_reset_bridge.out_reset/apf_rsv_c_slv.reset clockResetSysInfo {} + set_connection_parameter_value apf_reset_bridge.out_reset/apf_rsv_c_slv.reset resetDomainSysInfo {-1} + add_connection apf_st2mm_mst.altera_axi4lite_master/apf_rsv_c_slv.altera_axi4lite_slave + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_c_slv.altera_axi4lite_slave addressMapSysInfo {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_c_slv.altera_axi4lite_slave addressWidthSysInfo {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_c_slv.altera_axi4lite_slave arbitrationPriority {1} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_c_slv.altera_axi4lite_slave baseAddress {0x0c0000} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_c_slv.altera_axi4lite_slave defaultConnection {0} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_c_slv.altera_axi4lite_slave domainAlias {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_c_slv.altera_axi4lite_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_c_slv.altera_axi4lite_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_c_slv.altera_axi4lite_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_c_slv.altera_axi4lite_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_c_slv.altera_axi4lite_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_c_slv.altera_axi4lite_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_c_slv.altera_axi4lite_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_c_slv.altera_axi4lite_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_c_slv.altera_axi4lite_slave qsys_mm.syncResets {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_c_slv.altera_axi4lite_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_c_slv.altera_axi4lite_slave slaveDataWidthSysInfo {-1} + + add_connection apf_clock_bridge.out_clk/apf_rsv_d_slv.clock + set_connection_parameter_value apf_clock_bridge.out_clk/apf_rsv_d_slv.clock clockDomainSysInfo {-1} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_rsv_d_slv.clock clockRateSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_rsv_d_slv.clock clockResetSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_rsv_d_slv.clock resetDomainSysInfo {-1} + add_connection apf_reset_bridge.out_reset/apf_rsv_d_slv.reset + set_connection_parameter_value apf_reset_bridge.out_reset/apf_rsv_d_slv.reset clockDomainSysInfo {-1} + set_connection_parameter_value apf_reset_bridge.out_reset/apf_rsv_d_slv.reset clockResetSysInfo {} + set_connection_parameter_value apf_reset_bridge.out_reset/apf_rsv_d_slv.reset resetDomainSysInfo {-1} + add_connection apf_st2mm_mst.altera_axi4lite_master/apf_rsv_d_slv.altera_axi4lite_slave + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_d_slv.altera_axi4lite_slave addressMapSysInfo {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_d_slv.altera_axi4lite_slave addressWidthSysInfo {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_d_slv.altera_axi4lite_slave arbitrationPriority {1} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_d_slv.altera_axi4lite_slave baseAddress {0x0d0000} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_d_slv.altera_axi4lite_slave defaultConnection {0} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_d_slv.altera_axi4lite_slave domainAlias {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_d_slv.altera_axi4lite_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_d_slv.altera_axi4lite_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_d_slv.altera_axi4lite_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_d_slv.altera_axi4lite_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_d_slv.altera_axi4lite_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_d_slv.altera_axi4lite_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_d_slv.altera_axi4lite_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_d_slv.altera_axi4lite_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_d_slv.altera_axi4lite_slave qsys_mm.syncResets {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_d_slv.altera_axi4lite_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_d_slv.altera_axi4lite_slave slaveDataWidthSysInfo {-1} + + add_connection apf_clock_bridge.out_clk/apf_rsv_e_slv.clock + set_connection_parameter_value apf_clock_bridge.out_clk/apf_rsv_e_slv.clock clockDomainSysInfo {-1} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_rsv_e_slv.clock clockRateSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_rsv_e_slv.clock clockResetSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_rsv_e_slv.clock resetDomainSysInfo {-1} + add_connection apf_reset_bridge.out_reset/apf_rsv_e_slv.reset + set_connection_parameter_value apf_reset_bridge.out_reset/apf_rsv_e_slv.reset clockDomainSysInfo {-1} + set_connection_parameter_value apf_reset_bridge.out_reset/apf_rsv_e_slv.reset clockResetSysInfo {} + set_connection_parameter_value apf_reset_bridge.out_reset/apf_rsv_e_slv.reset resetDomainSysInfo {-1} + add_connection apf_st2mm_mst.altera_axi4lite_master/apf_rsv_e_slv.altera_axi4lite_slave + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_e_slv.altera_axi4lite_slave addressMapSysInfo {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_e_slv.altera_axi4lite_slave addressWidthSysInfo {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_e_slv.altera_axi4lite_slave arbitrationPriority {1} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_e_slv.altera_axi4lite_slave baseAddress {0x0e0000} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_e_slv.altera_axi4lite_slave defaultConnection {0} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_e_slv.altera_axi4lite_slave domainAlias {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_e_slv.altera_axi4lite_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_e_slv.altera_axi4lite_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_e_slv.altera_axi4lite_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_e_slv.altera_axi4lite_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_e_slv.altera_axi4lite_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_e_slv.altera_axi4lite_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_e_slv.altera_axi4lite_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_e_slv.altera_axi4lite_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_e_slv.altera_axi4lite_slave qsys_mm.syncResets {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_e_slv.altera_axi4lite_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_e_slv.altera_axi4lite_slave slaveDataWidthSysInfo {-1} + + add_connection apf_clock_bridge.out_clk/apf_rsv_f_slv.clock + set_connection_parameter_value apf_clock_bridge.out_clk/apf_rsv_f_slv.clock clockDomainSysInfo {-1} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_rsv_f_slv.clock clockRateSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_rsv_f_slv.clock clockResetSysInfo {} + set_connection_parameter_value apf_clock_bridge.out_clk/apf_rsv_f_slv.clock resetDomainSysInfo {-1} + add_connection apf_reset_bridge.out_reset/apf_rsv_f_slv.reset + set_connection_parameter_value apf_reset_bridge.out_reset/apf_rsv_f_slv.reset clockDomainSysInfo {-1} + set_connection_parameter_value apf_reset_bridge.out_reset/apf_rsv_f_slv.reset clockResetSysInfo {} + set_connection_parameter_value apf_reset_bridge.out_reset/apf_rsv_f_slv.reset resetDomainSysInfo {-1} + add_connection apf_st2mm_mst.altera_axi4lite_master/apf_rsv_f_slv.altera_axi4lite_slave + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_f_slv.altera_axi4lite_slave addressMapSysInfo {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_f_slv.altera_axi4lite_slave addressWidthSysInfo {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_f_slv.altera_axi4lite_slave arbitrationPriority {1} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_f_slv.altera_axi4lite_slave baseAddress {0x0f0000} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_f_slv.altera_axi4lite_slave defaultConnection {0} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_f_slv.altera_axi4lite_slave domainAlias {} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_f_slv.altera_axi4lite_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_f_slv.altera_axi4lite_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_f_slv.altera_axi4lite_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_f_slv.altera_axi4lite_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_f_slv.altera_axi4lite_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_f_slv.altera_axi4lite_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_f_slv.altera_axi4lite_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_f_slv.altera_axi4lite_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_f_slv.altera_axi4lite_slave qsys_mm.syncResets {FALSE} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_f_slv.altera_axi4lite_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value apf_st2mm_mst.altera_axi4lite_master/apf_rsv_f_slv.altera_axi4lite_slave slaveDataWidthSysInfo {-1} + + set_interface_property apf_st2mm_slv EXPORT_OF apf_st2mm_slv.altera_axi4lite_master + set_interface_property apf_pgsk_slv EXPORT_OF apf_pgsk_slv.altera_axi4lite_master + set_interface_property apf_achk_slv EXPORT_OF apf_achk_slv.altera_axi4lite_master + set_interface_property apf_rsv_b_slv EXPORT_OF apf_rsv_b_slv.altera_axi4lite_master + set_interface_property apf_rsv_c_slv EXPORT_OF apf_rsv_c_slv.altera_axi4lite_master + set_interface_property apf_rsv_d_slv EXPORT_OF apf_rsv_d_slv.altera_axi4lite_master + set_interface_property apf_rsv_e_slv EXPORT_OF apf_rsv_e_slv.altera_axi4lite_master + set_interface_property apf_rsv_f_slv EXPORT_OF apf_rsv_f_slv.altera_axi4lite_master + + # set the the module properties + set_module_property FILE {apf.qsys} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {apf} + + # save the system + sync_sysinfo_parameters + save_system apf + diff --git a/src/pd_qsys/fabric/axi4lite_shim_hw.tcl b/src/pd_qsys/fabric/axi4lite_shim_hw.tcl new file mode 100755 index 0000000..8e2813c --- /dev/null +++ b/src/pd_qsys/fabric/axi4lite_shim_hw.tcl @@ -0,0 +1,220 @@ +# Copyright (C) 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# TCL File Generated by Component Editor 19.4 +# Fri Oct 02 12:06:37 PDT 2020 +# DO NOT MODIFY + + +# +# axi4lite_shim "axi4lite_shim" v1.0 +# 2020.10.02.12:06:37 +# +# + +# +# request TCL package from ACDS 19.4 +# +package require -exact qsys 19.4 + + +# +# module axi4lite_shim +# +set_module_property DESCRIPTION "" +set_module_property NAME axi4lite_shim +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME axi4lite_shim +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false +set_module_property LOAD_ELABORATION_LIMIT 0 + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL axi4lite_shim +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file axi4lite_shim.sv SYSTEM_VERILOG PATH $env(WORKDIR)/ofs-common/src/common/lib/axi4lite/axi4lite_shim.sv TOP_LEVEL_FILE + +add_fileset SIM_VERILOG SIM_VERILOG "" "" +set_fileset_property SIM_VERILOG TOP_LEVEL axi4lite_shim +set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file axi4lite_shim.sv SYSTEM_VERILOG PATH $env(WORKDIR)/ofs-common/src/common/lib/axi4lite/axi4lite_shim.sv TOP_LEVEL_FILE + + +# +# parameters +# +add_parameter AW INTEGER 18 +set_parameter_property AW DEFAULT_VALUE 18 +set_parameter_property AW DISPLAY_NAME AW +set_parameter_property AW UNITS None +set_parameter_property AW HDL_PARAMETER true +add_parameter DW INTEGER 64 +set_parameter_property DW DEFAULT_VALUE 64 +set_parameter_property DW DISPLAY_NAME DW +set_parameter_property DW UNITS None +set_parameter_property DW HDL_PARAMETER true + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" +set_interface_property clock IPXACT_REGISTER_MAP_VARIABLES "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" +set_interface_property reset IPXACT_REGISTER_MAP_VARIABLES "" + +add_interface_port reset rst_n reset_n Input 1 + + +# +# connection point altera_axi4lite_slave +# +add_interface altera_axi4lite_slave axi4lite end +set_interface_property altera_axi4lite_slave associatedClock clock +set_interface_property altera_axi4lite_slave associatedReset reset +set_interface_property altera_axi4lite_slave readAcceptanceCapability 1 +set_interface_property altera_axi4lite_slave writeAcceptanceCapability 1 +set_interface_property altera_axi4lite_slave combinedAcceptanceCapability 1 +set_interface_property altera_axi4lite_slave bridgesToMaster "" +set_interface_property altera_axi4lite_slave ENABLED true +set_interface_property altera_axi4lite_slave EXPORT_OF "" +set_interface_property altera_axi4lite_slave PORT_NAME_MAP "" +set_interface_property altera_axi4lite_slave CMSIS_SVD_VARIABLES "" +set_interface_property altera_axi4lite_slave SVD_ADDRESS_GROUP "" +set_interface_property altera_axi4lite_slave IPXACT_REGISTER_MAP_VARIABLES "" + +add_interface_port altera_axi4lite_slave s_awaddr awaddr Input "((AW - 1)) - (0) + 1" +add_interface_port altera_axi4lite_slave s_awprot awprot Input 3 +add_interface_port altera_axi4lite_slave s_awvalid awvalid Input 1 +add_interface_port altera_axi4lite_slave s_awready awready Output 1 +add_interface_port altera_axi4lite_slave s_wdata wdata Input "((DW - 1)) - (0) + 1" +add_interface_port altera_axi4lite_slave s_wstrb wstrb Input 8 +add_interface_port altera_axi4lite_slave s_wvalid wvalid Input 1 +add_interface_port altera_axi4lite_slave s_wready wready Output 1 +add_interface_port altera_axi4lite_slave s_bresp bresp Output 2 +add_interface_port altera_axi4lite_slave s_bvalid bvalid Output 1 +add_interface_port altera_axi4lite_slave s_bready bready Input 1 +add_interface_port altera_axi4lite_slave s_araddr araddr Input "((AW - 1)) - (0) + 1" +add_interface_port altera_axi4lite_slave s_arprot arprot Input 3 +add_interface_port altera_axi4lite_slave s_arvalid arvalid Input 1 +add_interface_port altera_axi4lite_slave s_arready arready Output 1 +add_interface_port altera_axi4lite_slave s_rdata rdata Output "((DW - 1)) - (0) + 1" +add_interface_port altera_axi4lite_slave s_rresp rresp Output 2 +add_interface_port altera_axi4lite_slave s_rvalid rvalid Output 1 +add_interface_port altera_axi4lite_slave s_rready rready Input 1 + + +# +# connection point altera_axi4lite_master +# +add_interface altera_axi4lite_master axi4lite start +set_interface_property altera_axi4lite_master associatedClock clock +set_interface_property altera_axi4lite_master associatedReset reset +set_interface_property altera_axi4lite_master readIssuingCapability 1 +set_interface_property altera_axi4lite_master writeIssuingCapability 1 +set_interface_property altera_axi4lite_master combinedIssuingCapability 1 +set_interface_property altera_axi4lite_master ENABLED true +set_interface_property altera_axi4lite_master EXPORT_OF "" +set_interface_property altera_axi4lite_master PORT_NAME_MAP "" +set_interface_property altera_axi4lite_master CMSIS_SVD_VARIABLES "" +set_interface_property altera_axi4lite_master SVD_ADDRESS_GROUP "" +set_interface_property altera_axi4lite_master IPXACT_REGISTER_MAP_VARIABLES "" + +add_interface_port altera_axi4lite_master m_awaddr awaddr Output "((AW - 1)) - (0) + 1" +add_interface_port altera_axi4lite_master m_awprot awprot Output 3 +add_interface_port altera_axi4lite_master m_awvalid awvalid Output 1 +add_interface_port altera_axi4lite_master m_awready awready Input 1 +add_interface_port altera_axi4lite_master m_wdata wdata Output "((DW - 1)) - (0) + 1" +add_interface_port altera_axi4lite_master m_wstrb wstrb Output 8 +add_interface_port altera_axi4lite_master m_wvalid wvalid Output 1 +add_interface_port altera_axi4lite_master m_wready wready Input 1 +add_interface_port altera_axi4lite_master m_bresp bresp Input 2 +add_interface_port altera_axi4lite_master m_bvalid bvalid Input 1 +add_interface_port altera_axi4lite_master m_bready bready Output 1 +add_interface_port altera_axi4lite_master m_araddr araddr Output "((AW - 1)) - (0) + 1" +add_interface_port altera_axi4lite_master m_arprot arprot Output 3 +add_interface_port altera_axi4lite_master m_arvalid arvalid Output 1 +add_interface_port altera_axi4lite_master m_arready arready Input 1 +add_interface_port altera_axi4lite_master m_rdata rdata Input "((DW - 1)) - (0) + 1" +add_interface_port altera_axi4lite_master m_rresp rresp Input 2 +add_interface_port altera_axi4lite_master m_rvalid rvalid Input 1 +add_interface_port altera_axi4lite_master m_rready rready Output 1 + +# +# from altera_axi_bridge_hw.tcl +# +add_parameter WRITE_ISSUING_CAPABILITY INTEGER 16 "Write Issuing Capability" +set_parameter_property WRITE_ISSUING_CAPABILITY DEFAULT_VALUE 1 +set_parameter_property WRITE_ISSUING_CAPABILITY DISPLAY_NAME "Write Issuing Capability" +set_parameter_property WRITE_ISSUING_CAPABILITY WIDTH "" +set_parameter_property WRITE_ISSUING_CAPABILITY UNITS None +set_parameter_property WRITE_ISSUING_CAPABILITY DESCRIPTION "Write Issuing Capability" +set_parameter_property WRITE_ISSUING_CAPABILITY AFFECTS_GENERATION false +set_parameter_property WRITE_ISSUING_CAPABILITY HDL_PARAMETER false + +add_parameter READ_ISSUING_CAPABILITY INTEGER 16 "Read Issuing Capability" +set_parameter_property READ_ISSUING_CAPABILITY DEFAULT_VALUE 512 +set_parameter_property READ_ISSUING_CAPABILITY DISPLAY_NAME "Read Issuing Capability" +set_parameter_property READ_ISSUING_CAPABILITY WIDTH "" +set_parameter_property READ_ISSUING_CAPABILITY UNITS None +set_parameter_property READ_ISSUING_CAPABILITY DESCRIPTION "Read Issuing Capability" +set_parameter_property READ_ISSUING_CAPABILITY AFFECTS_GENERATION false +set_parameter_property READ_ISSUING_CAPABILITY HDL_PARAMETER false + +add_parameter COMBINED_ISSUING_CAPABILITY INTEGER 16 "Combined Issuing Capability" +set_parameter_property COMBINED_ISSUING_CAPABILITY DEFAULT_VALUE 512 +set_parameter_property COMBINED_ISSUING_CAPABILITY DISPLAY_NAME "Combined Issuing Capability" +set_parameter_property COMBINED_ISSUING_CAPABILITY WIDTH "" +set_parameter_property COMBINED_ISSUING_CAPABILITY UNITS None +set_parameter_property COMBINED_ISSUING_CAPABILITY DESCRIPTION "Combined Issuing Capability" +set_parameter_property COMBINED_ISSUING_CAPABILITY AFFECTS_GENERATION false +set_parameter_property COMBINED_ISSUING_CAPABILITY HDL_PARAMETER false + +proc elaborate {} { + + # Read master interface properties + set write_issuing_capability [ get_parameter_value WRITE_ISSUING_CAPABILITY ] + set read_issuing_capability [ get_parameter_value READ_ISSUING_CAPABILITY ] + set combined_issuing_capability [ get_parameter_value COMBINED_ISSUING_CAPABILITY ] + + # set porperties + set_interface_property $master_name writeIssuingCapability $write_issuing_capability + set_interface_property $master_name readIssuingCapability $read_issuing_capability + set_interface_property $master_name combinedIssuingCapability $combined_issuing_capability +} diff --git a/src/pd_qsys/fabric/bpf.qpf b/src/pd_qsys/fabric/bpf.qpf new file mode 100644 index 0000000..a2d2bcc --- /dev/null +++ b/src/pd_qsys/fabric/bpf.qpf @@ -0,0 +1,17 @@ +# Copyright 2022 Intel Corporation +# SPDX-License-Identifier: MIT + +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 22.1.0 Build 174 03/30/2022 SC Pro Edition +# Date created = 03:59:33 September 20, 2022 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "22.1" +DATE = "03:59:33 September 20, 2022" + +# Revisions + +PROJECT_REVISION = "bpf" diff --git a/src/pd_qsys/fabric/bpf.qsf b/src/pd_qsys/fabric/bpf.qsf new file mode 100644 index 0000000..d90306e --- /dev/null +++ b/src/pd_qsys/fabric/bpf.qsf @@ -0,0 +1,23 @@ +# Copyright (C) 2022 Intel Corporation +# SPDX-License-Identifier: MIT + +set_global_assignment -name TOP_LEVEL_ENTITY bpf +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 22.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "03:59:33 SEPTEMBER 20, 2022" +set_global_assignment -name LAST_QUARTUS_VERSION "22.1.0 Pro Edition" +set_global_assignment -name FAMILY "Stratix 10" +set_global_assignment -name DEVICE 1SX280HN2F43E2VG +set_global_assignment -name IP_FILE ip/bpf/bpf_clock_bridge.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_reset_bridge.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_apf_mst.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_apf_slv.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_fme_mst.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_fme_slv.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_pmci_slv.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_pcie_slv.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_hssi_slv.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_emif_slv.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_rsv_5_slv.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_rsv_6_slv.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_rsv_7_slv.ip +set_global_assignment -name QSYS_FILE bpf.qsys diff --git a/src/pd_qsys/fabric/bpf.qsys b/src/pd_qsys/fabric/bpf.qsys new file mode 100644 index 0000000..f3f6a58 --- /dev/null +++ b/src/pd_qsys/fabric/bpf.qsys @@ -0,0 +1,13785 @@ + + + + Altera Corporation + bpf + bpf + 1.0 + + + + $${FILENAME} + $${FILENAME} + 1.0 + + + System + QsysPro + + + + + board + Board + Unknown + + + bonusData + bonusData + bonusData +{ + element $system + { + } + element bpf_apf_mst + { + datum _sortIndex + { + value = "2"; + type = "int"; + } + } + element bpf_apf_slv + { + datum _sortIndex + { + value = "3"; + type = "int"; + } + } + element bpf_clock_bridge + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } + element bpf_emif_slv + { + datum _sortIndex + { + value = "9"; + type = "int"; + } + } + element bpf_fme_mst + { + datum _sortIndex + { + value = "4"; + type = "int"; + } + } + element bpf_fme_slv + { + datum _sortIndex + { + value = "5"; + type = "int"; + } + } + element bpf_hssi_slv + { + datum _sortIndex + { + value = "8"; + type = "int"; + } + } + element bpf_pcie_slv + { + datum _sortIndex + { + value = "7"; + type = "int"; + } + } + element bpf_pmci_slv + { + datum _sortIndex + { + value = "6"; + type = "int"; + } + } + element bpf_reset_bridge + { + datum _sortIndex + { + value = "1"; + type = "int"; + } + } + element bpf_rsv_5_slv + { + datum _sortIndex + { + value = "10"; + type = "int"; + } + } + element bpf_rsv_6_slv + { + datum _sortIndex + { + value = "11"; + type = "int"; + } + } + element bpf_rsv_7_slv + { + datum _sortIndex + { + value = "12"; + type = "int"; + } + } +} + + + + designId + designId + + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + fabricMode + fabricMode + QSYS + + + generateLegacySim + generateLegacySim + false + + + generationId + Generation Id + 0 + + + globalResetBus + Global reset + false + + + hdlLanguage + hdlLanguage + VERILOG + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + + + + sopcBorderPoints + Use SOPC Builder port naming + false + + + systemHash + systemHash + 0 + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + systemScripts + systemScripts + + + + testBenchDutName + Use Test Bench Naming Pattern + + + + timeStamp + timeStamp + 0 + + + useTestBenchNamingPattern + Use Test Bench Naming Pattern + false + + + + + + + + + Altera Corporation + bpf_apf_mst + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>axi4lite_shim</className> + <version>1.0</version> + <displayName>axi4lite_shim</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>bpf_apf_mst</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>QUARTUS_SYNTH</fileSetName> + <fileSetFixedName>bpf_apf_mst</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VERILOG</fileSetName> + <fileSetFixedName>bpf_apf_mst</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VHDL</fileSetName> + <fileSetFixedName>bpf_apf_mst</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>CDC</fileSetName> + <fileSetFixedName>bpf_apf_mst</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/bpf/bpf_apf_mst.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + bpf_apf_slv + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>axi4lite_shim</className> + <version>1.0</version> + <displayName>axi4lite_shim</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>bpf_apf_slv</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>QUARTUS_SYNTH</fileSetName> + <fileSetFixedName>bpf_apf_slv</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VERILOG</fileSetName> + <fileSetFixedName>bpf_apf_slv</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VHDL</fileSetName> + <fileSetFixedName>bpf_apf_slv</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>CDC</fileSetName> + <fileSetFixedName>bpf_apf_slv</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/bpf/bpf_apf_slv.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + bpf_clock_bridge + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>in_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>in_clk</value> + </entry> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>false</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_clock_bridge</className> + <version>19.2.0</version> + <displayName>Clock Bridge Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>DERIVED_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>in_clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>in_clk</key> + <value> + <connectionPointName>in_clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>out_clk</key> + <value> + <connectionPointName>out_clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>in_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>in_clk</value> + </entry> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>false</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>bpf_clock_bridge</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>QUARTUS_SYNTH</fileSetName> + <fileSetFixedName>bpf_clock_bridge</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VERILOG</fileSetName> + <fileSetFixedName>bpf_clock_bridge</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VHDL</fileSetName> + <fileSetFixedName>bpf_clock_bridge</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>CDC</fileSetName> + <fileSetFixedName>bpf_clock_bridge</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/bpf/bpf_clock_bridge.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + bpf_emif_slv + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>axi4lite_shim</className> + <version>1.0</version> + <displayName>axi4lite_shim</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>bpf_emif_slv</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>QUARTUS_SYNTH</fileSetName> + <fileSetFixedName>bpf_emif_slv</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VERILOG</fileSetName> + <fileSetFixedName>bpf_emif_slv</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VHDL</fileSetName> + <fileSetFixedName>bpf_emif_slv</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>CDC</fileSetName> + <fileSetFixedName>bpf_emif_slv</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/bpf/bpf_emif_slv.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + bpf_fme_mst + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>axi4lite_shim</className> + <version>1.0</version> + <displayName>axi4lite_shim</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>bpf_fme_mst</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>QUARTUS_SYNTH</fileSetName> + <fileSetFixedName>bpf_fme_mst</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VERILOG</fileSetName> + <fileSetFixedName>bpf_fme_mst</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VHDL</fileSetName> + <fileSetFixedName>bpf_fme_mst</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>CDC</fileSetName> + <fileSetFixedName>bpf_fme_mst</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/bpf/bpf_fme_mst.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + bpf_fme_slv + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>axi4lite_shim</className> + <version>1.0</version> + <displayName>axi4lite_shim</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>bpf_fme_slv</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>QUARTUS_SYNTH</fileSetName> + <fileSetFixedName>bpf_fme_slv</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VERILOG</fileSetName> + <fileSetFixedName>bpf_fme_slv</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VHDL</fileSetName> + <fileSetFixedName>bpf_fme_slv</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>CDC</fileSetName> + <fileSetFixedName>bpf_fme_slv</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/bpf/bpf_fme_slv.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + bpf_hssi_slv + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>axi4lite_shim</className> + <version>1.0</version> + <displayName>axi4lite_shim</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>bpf_hssi_slv</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>QUARTUS_SYNTH</fileSetName> + <fileSetFixedName>bpf_hssi_slv</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VERILOG</fileSetName> + <fileSetFixedName>bpf_hssi_slv</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VHDL</fileSetName> + <fileSetFixedName>bpf_hssi_slv</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>CDC</fileSetName> + <fileSetFixedName>bpf_hssi_slv</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/bpf/bpf_hssi_slv.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + bpf_pcie_slv + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>axi4lite_shim</className> + <version>1.0</version> + <displayName>axi4lite_shim</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>bpf_pcie_slv</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>QUARTUS_SYNTH</fileSetName> + <fileSetFixedName>bpf_pcie_slv</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VERILOG</fileSetName> + <fileSetFixedName>bpf_pcie_slv</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VHDL</fileSetName> + <fileSetFixedName>bpf_pcie_slv</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>CDC</fileSetName> + <fileSetFixedName>bpf_pcie_slv</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/bpf/bpf_pcie_slv.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + bpf_pmci_slv + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>axi4lite_shim</className> + <version>1.0</version> + <displayName>axi4lite_shim</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>bpf_pmci_slv</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>QUARTUS_SYNTH</fileSetName> + <fileSetFixedName>bpf_pmci_slv</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VERILOG</fileSetName> + <fileSetFixedName>bpf_pmci_slv</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VHDL</fileSetName> + <fileSetFixedName>bpf_pmci_slv</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>CDC</fileSetName> + <fileSetFixedName>bpf_pmci_slv</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/bpf/bpf_pmci_slv.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + bpf_reset_bridge + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_reset_n</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_reset_bridge</className> + <version>19.2.0</version> + <displayName>Reset Bridge Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_CLK_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>-1</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_reset_n</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>bpf_reset_bridge</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>QUARTUS_SYNTH</fileSetName> + <fileSetFixedName>bpf_reset_bridge</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VERILOG</fileSetName> + <fileSetFixedName>bpf_reset_bridge</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VHDL</fileSetName> + <fileSetFixedName>bpf_reset_bridge</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>CDC</fileSetName> + <fileSetFixedName>bpf_reset_bridge</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/bpf/bpf_reset_bridge.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + bpf_rsv_5_slv + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>axi4lite_shim</className> + <version>1.0</version> + <displayName>axi4lite_shim</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>bpf_rsv_5_slv</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>QUARTUS_SYNTH</fileSetName> + <fileSetFixedName>bpf_rsv_5_slv</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VERILOG</fileSetName> + <fileSetFixedName>bpf_rsv_5_slv</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VHDL</fileSetName> + <fileSetFixedName>bpf_rsv_5_slv</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>CDC</fileSetName> + <fileSetFixedName>bpf_rsv_5_slv</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/bpf/bpf_rsv_5_slv.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + bpf_rsv_6_slv + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>axi4lite_shim</className> + <version>1.0</version> + <displayName>axi4lite_shim</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>bpf_rsv_6_slv</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>QUARTUS_SYNTH</fileSetName> + <fileSetFixedName>bpf_rsv_6_slv</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VERILOG</fileSetName> + <fileSetFixedName>bpf_rsv_6_slv</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VHDL</fileSetName> + <fileSetFixedName>bpf_rsv_6_slv</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>CDC</fileSetName> + <fileSetFixedName>bpf_rsv_6_slv</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/bpf/bpf_rsv_6_slv.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + bpf_rsv_7_slv + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>16</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>16</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>16</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>16</value> + </entry> + <entry> + <key>enableConcurrentSubordinateAccess</key> + <value>0</value> + </entry> + <entry> + <key>noRepeatedIdsBetweenSubordinates</key> + <value>0</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>axi4lite_shim</className> + <version>1.0</version> + <displayName>axi4lite_shim</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors/> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos/> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>bpf_rsv_7_slv</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>QUARTUS_SYNTH</fileSetName> + <fileSetFixedName>bpf_rsv_7_slv</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VERILOG</fileSetName> + <fileSetFixedName>bpf_rsv_7_slv</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>SIM_VHDL</fileSetName> + <fileSetFixedName>bpf_rsv_7_slv</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>CDC</fileSetName> + <fileSetFixedName>bpf_rsv_7_slv</fileSetFixedName> + <fileSetKind>CDC</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + <hdlParameterDescriptorDefinitionList/> + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/bpf/bpf_rsv_7_slv.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Intel Corporation + addressMap + addressMap + 1.0 + + + bpf_fme_slv.altera_axi4lite_slave + + + + bpf_pmci_slv.altera_axi4lite_slave + + + + bpf_pcie_slv.altera_axi4lite_slave + + + + bpf_hssi_slv.altera_axi4lite_slave + + + + bpf_emif_slv.altera_axi4lite_slave + + + + bpf_rsv_5_slv.altera_axi4lite_slave + + + + bpf_rsv_6_slv.altera_axi4lite_slave + + + + bpf_rsv_7_slv.altera_axi4lite_slave + + + + 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bpf_rsv_5_slv.altera_axi4lite_slave + 0x0005_0000 + 0x0001_0000 + + + bpf_rsv_6_slv.altera_axi4lite_slave + 0x0006_0000 + 0x0001_0000 + + + bpf_rsv_7_slv.altera_axi4lite_slave + 0x0007_0000 + 0x0001_0000 + + + + + bpf_fme_mst.altera_axi4lite_master + + + bpf_apf_slv.altera_axi4lite_slave + 0x0000_0000 + 0x0010_0000 + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/bpf.qsys.legacy b/src/pd_qsys/fabric/bpf.qsys.legacy new file mode 100644 index 0000000..0fa62a4 --- /dev/null +++ b/src/pd_qsys/fabric/bpf.qsys.legacy @@ -0,0 +1,13194 @@ + + + + + + + + + + + + + + + + + + + + + + + clk + + clk + + + CLOCK_RATE + + + + + + +]]> + + + + + + + + + + + + + + + + + + + + + + + + clock + clock + false + + + clk + clk + Input + 1 + 0 + STD_LOGIC + 0 + + + + + + + + + clockRate + 0 + + + externallyDriven + false + + + ptfSchematicName + + + + + + reset + reset + false + + + rst_n + reset_n + Input + 1 + 0 + STD_LOGIC + 0 + + + + + + + + + associatedClock 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/pd_qsys/fabric/bpf.tcl b/src/pd_qsys/fabric/bpf.tcl new file mode 100644 index 0000000..1ec2993 --- /dev/null +++ b/src/pd_qsys/fabric/bpf.tcl @@ -0,0 +1,1268 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +package require -exact qsys 18.0 + + # create the system + create_system bpf + set_project_property DEVICE 1SX280HN2F43E2VG + set_project_property DEVICE_FAMILY Stratix10 + set_project_property HIDE_FROM_IP_CATALOG {false} + set_use_testbench_naming_pattern 0 {} + + + # add the components + add_component bpf_clock_bridge ip/bpf/bpf_clock_bridge.ip altera_clock_bridge bpf_clock_bridge + load_component bpf_clock_bridge + set_component_parameter_value EXPLICIT_CLOCK_RATE {0.0} + set_component_parameter_value NUM_CLOCK_OUTPUTS {1} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation bpf_clock_bridge + remove_instantiation_interfaces_and_ports + add_instantiation_interface in_clk clock INPUT + set_instantiation_interface_parameter_value in_clk clockRate {0} + set_instantiation_interface_parameter_value in_clk externallyDriven {false} + set_instantiation_interface_parameter_value in_clk ptfSchematicName {} + add_instantiation_interface_port in_clk in_clk clk 1 STD_LOGIC Input + add_instantiation_interface out_clk clock OUTPUT + set_instantiation_interface_parameter_value out_clk associatedDirectClock {in_clk} + set_instantiation_interface_parameter_value out_clk clockRate {0} + set_instantiation_interface_parameter_value out_clk clockRateKnown {false} + set_instantiation_interface_parameter_value out_clk externallyDriven {false} + set_instantiation_interface_parameter_value out_clk ptfSchematicName {} + set_instantiation_interface_sysinfo_parameter_value out_clk clock_rate {0} + add_instantiation_interface_port out_clk out_clk clk 1 STD_LOGIC Output + save_instantiation + + add_component bpf_reset_bridge ip/bpf/bpf_reset_bridge.ip altera_reset_bridge bpf_reset_bridge + load_component bpf_reset_bridge + set_component_parameter_value ACTIVE_LOW_RESET {1} + set_component_parameter_value NUM_RESET_OUTPUTS {1} + set_component_parameter_value SYNCHRONOUS_EDGES {deassert} + set_component_parameter_value SYNC_RESET {0} + set_component_parameter_value USE_RESET_REQUEST {0} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation bpf_reset_bridge + remove_instantiation_interfaces_and_ports + add_instantiation_interface clk clock INPUT + set_instantiation_interface_parameter_value clk clockRate {0} + set_instantiation_interface_parameter_value clk externallyDriven {false} + set_instantiation_interface_parameter_value clk ptfSchematicName {} + add_instantiation_interface_port clk clk clk 1 STD_LOGIC Input + add_instantiation_interface in_reset reset INPUT + set_instantiation_interface_parameter_value in_reset associatedClock {clk} + set_instantiation_interface_parameter_value in_reset synchronousEdges {DEASSERT} + add_instantiation_interface_port in_reset in_reset_n reset_n 1 STD_LOGIC Input + add_instantiation_interface out_reset reset OUTPUT + set_instantiation_interface_parameter_value out_reset associatedClock {clk} + set_instantiation_interface_parameter_value out_reset associatedDirectReset {in_reset} + set_instantiation_interface_parameter_value out_reset associatedResetSinks {in_reset} + set_instantiation_interface_parameter_value out_reset synchronousEdges {DEASSERT} + add_instantiation_interface_port out_reset out_reset_n reset_n 1 STD_LOGIC Output + save_instantiation + + # add the connections + add_connection bpf_clock_bridge.out_clk/bpf_reset_bridge.clk + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_reset_bridge.clk clockDomainSysInfo {-1} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_reset_bridge.clk clockRateSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_reset_bridge.clk clockResetSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_reset_bridge.clk resetDomainSysInfo {-1} + + # add the exports + set_interface_property clk EXPORT_OF bpf_clock_bridge.in_clk + set_interface_property rst_n EXPORT_OF bpf_reset_bridge.in_reset + add_component bpf_apf_mst ip/bpf/bpf_apf_mst.ip axi4lite_shim bpf_apf_mst 1.0 + load_component bpf_apf_mst + set_component_parameter_value AW {19} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation bpf_apf_mst + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr 19 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr 19 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {16/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr 19 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr 19 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + + add_connection bpf_clock_bridge.out_clk/bpf_apf_mst.clock + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_apf_mst.clock clockDomainSysInfo {-1} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_apf_mst.clock clockRateSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_apf_mst.clock clockResetSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_apf_mst.clock resetDomainSysInfo {-1} + add_connection bpf_reset_bridge.out_reset/bpf_apf_mst.reset + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_apf_mst.reset clockDomainSysInfo {-1} + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_apf_mst.reset clockResetSysInfo {} + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_apf_mst.reset resetDomainSysInfo {-1} + add_component bpf_apf_slv ip/bpf/bpf_apf_slv.ip axi4lite_shim bpf_apf_slv 1.0 + load_component bpf_apf_slv + set_component_parameter_value AW {20} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation bpf_apf_slv + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {16/4} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr 20 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr 20 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {16/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr 20 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr 20 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + + add_connection bpf_clock_bridge.out_clk/bpf_apf_slv.clock + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_apf_slv.clock clockDomainSysInfo {-1} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_apf_slv.clock clockRateSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_apf_slv.clock clockResetSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_apf_slv.clock resetDomainSysInfo {-1} + add_connection bpf_reset_bridge.out_reset/bpf_apf_slv.reset + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_apf_slv.reset clockDomainSysInfo {-1} + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_apf_slv.reset clockResetSysInfo {} + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_apf_slv.reset resetDomainSysInfo {-1} + add_component bpf_fme_mst ip/bpf/bpf_fme_mst.ip axi4lite_shim bpf_fme_mst 1.0 + load_component bpf_fme_mst + set_component_parameter_value AW {20} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation bpf_fme_mst + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr 20 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr 20 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {16/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr 20 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr 20 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + + add_component bpf_fme_slv ip/bpf/bpf_fme_slv.ip axi4lite_shim bpf_fme_slv 1.0 + load_component bpf_fme_slv + set_component_parameter_value AW {16} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation bpf_fme_slv + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {16/4} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {16/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + + add_component bpf_pmci_slv ip/bpf/bpf_pmci_slv.ip axi4lite_shim bpf_pmci_slv 1.0 + load_component bpf_pmci_slv + set_component_parameter_value AW {16} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation bpf_pmci_slv + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {16/4} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {16/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + + add_component bpf_pcie_slv ip/bpf/bpf_pcie_slv.ip axi4lite_shim bpf_pcie_slv 1.0 + load_component bpf_pcie_slv + set_component_parameter_value AW {16} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation bpf_pcie_slv + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {16/4} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {16/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + + add_component bpf_hssi_slv ip/bpf/bpf_hssi_slv.ip axi4lite_shim bpf_hssi_slv 1.0 + load_component bpf_hssi_slv + set_component_parameter_value AW {16} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation bpf_hssi_slv + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {16/4} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {16/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + + add_component bpf_emif_slv ip/bpf/bpf_emif_slv.ip axi4lite_shim bpf_emif_slv 1.0 + load_component bpf_emif_slv + set_component_parameter_value AW {16} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation bpf_emif_slv + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {16/4} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {16/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + + add_component bpf_rsv_5_slv ip/bpf/bpf_rsv_5_slv.ip axi4lite_shim bpf_rsv_5_slv 1.0 + load_component bpf_rsv_5_slv + set_component_parameter_value AW {16} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation bpf_rsv_5_slv + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {16/4} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {16/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + + add_component bpf_rsv_6_slv ip/bpf/bpf_rsv_6_slv.ip axi4lite_shim bpf_rsv_6_slv 1.0 + load_component bpf_rsv_6_slv + set_component_parameter_value AW {16} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation bpf_rsv_6_slv + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {16/4} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {16/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + + add_component bpf_rsv_7_slv ip/bpf/bpf_rsv_7_slv.ip axi4lite_shim bpf_rsv_7_slv 1.0 + load_component bpf_rsv_7_slv + set_component_parameter_value AW {16} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {16} + set_component_parameter_value READ_ISSUING_CAPABILITY {16} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {16/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation bpf_rsv_7_slv + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {16/4} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {16} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {16/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {16} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {16/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + + add_connection bpf_clock_bridge.out_clk/bpf_fme_slv.clock + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_fme_slv.clock clockDomainSysInfo {-1} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_fme_slv.clock clockRateSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_fme_slv.clock clockResetSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_fme_slv.clock resetDomainSysInfo {-1} + add_connection bpf_reset_bridge.out_reset/bpf_fme_slv.reset + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_fme_slv.reset clockDomainSysInfo {-1} + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_fme_slv.reset clockResetSysInfo {} + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_fme_slv.reset resetDomainSysInfo {-1} + add_connection bpf_apf_mst.altera_axi4lite_master/bpf_fme_slv.altera_axi4lite_slave + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_fme_slv.altera_axi4lite_slave addressMapSysInfo {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_fme_slv.altera_axi4lite_slave addressWidthSysInfo {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_fme_slv.altera_axi4lite_slave arbitrationPriority {1} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_fme_slv.altera_axi4lite_slave baseAddress {0x000000} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_fme_slv.altera_axi4lite_slave defaultConnection {0} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_fme_slv.altera_axi4lite_slave domainAlias {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_fme_slv.altera_axi4lite_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_fme_slv.altera_axi4lite_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_fme_slv.altera_axi4lite_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_fme_slv.altera_axi4lite_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_fme_slv.altera_axi4lite_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_fme_slv.altera_axi4lite_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_fme_slv.altera_axi4lite_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_fme_slv.altera_axi4lite_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_fme_slv.altera_axi4lite_slave qsys_mm.syncResets {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_fme_slv.altera_axi4lite_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_fme_slv.altera_axi4lite_slave slaveDataWidthSysInfo {-1} + + add_connection bpf_clock_bridge.out_clk/bpf_pmci_slv.clock + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_pmci_slv.clock clockDomainSysInfo {-1} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_pmci_slv.clock clockRateSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_pmci_slv.clock clockResetSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_pmci_slv.clock resetDomainSysInfo {-1} + add_connection bpf_reset_bridge.out_reset/bpf_pmci_slv.reset + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_pmci_slv.reset clockDomainSysInfo {-1} + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_pmci_slv.reset clockResetSysInfo {} + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_pmci_slv.reset resetDomainSysInfo {-1} + add_connection bpf_apf_mst.altera_axi4lite_master/bpf_pmci_slv.altera_axi4lite_slave + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pmci_slv.altera_axi4lite_slave addressMapSysInfo {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pmci_slv.altera_axi4lite_slave addressWidthSysInfo {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pmci_slv.altera_axi4lite_slave arbitrationPriority {1} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pmci_slv.altera_axi4lite_slave baseAddress {0x010000} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pmci_slv.altera_axi4lite_slave defaultConnection {0} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pmci_slv.altera_axi4lite_slave domainAlias {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pmci_slv.altera_axi4lite_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pmci_slv.altera_axi4lite_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pmci_slv.altera_axi4lite_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pmci_slv.altera_axi4lite_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pmci_slv.altera_axi4lite_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pmci_slv.altera_axi4lite_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pmci_slv.altera_axi4lite_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pmci_slv.altera_axi4lite_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pmci_slv.altera_axi4lite_slave qsys_mm.syncResets {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pmci_slv.altera_axi4lite_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pmci_slv.altera_axi4lite_slave slaveDataWidthSysInfo {-1} + + add_connection bpf_clock_bridge.out_clk/bpf_pcie_slv.clock + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_pcie_slv.clock clockDomainSysInfo {-1} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_pcie_slv.clock clockRateSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_pcie_slv.clock clockResetSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_pcie_slv.clock resetDomainSysInfo {-1} + add_connection bpf_reset_bridge.out_reset/bpf_pcie_slv.reset + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_pcie_slv.reset clockDomainSysInfo {-1} + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_pcie_slv.reset clockResetSysInfo {} + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_pcie_slv.reset resetDomainSysInfo {-1} + add_connection bpf_apf_mst.altera_axi4lite_master/bpf_pcie_slv.altera_axi4lite_slave + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pcie_slv.altera_axi4lite_slave addressMapSysInfo {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pcie_slv.altera_axi4lite_slave addressWidthSysInfo {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pcie_slv.altera_axi4lite_slave arbitrationPriority {1} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pcie_slv.altera_axi4lite_slave baseAddress {0x020000} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pcie_slv.altera_axi4lite_slave defaultConnection {0} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pcie_slv.altera_axi4lite_slave domainAlias {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pcie_slv.altera_axi4lite_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pcie_slv.altera_axi4lite_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pcie_slv.altera_axi4lite_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pcie_slv.altera_axi4lite_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pcie_slv.altera_axi4lite_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pcie_slv.altera_axi4lite_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pcie_slv.altera_axi4lite_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pcie_slv.altera_axi4lite_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pcie_slv.altera_axi4lite_slave qsys_mm.syncResets {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pcie_slv.altera_axi4lite_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_pcie_slv.altera_axi4lite_slave slaveDataWidthSysInfo {-1} + + add_connection bpf_clock_bridge.out_clk/bpf_hssi_slv.clock + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_hssi_slv.clock clockDomainSysInfo {-1} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_hssi_slv.clock clockRateSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_hssi_slv.clock clockResetSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_hssi_slv.clock resetDomainSysInfo {-1} + add_connection bpf_reset_bridge.out_reset/bpf_hssi_slv.reset + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_hssi_slv.reset clockDomainSysInfo {-1} + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_hssi_slv.reset clockResetSysInfo {} + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_hssi_slv.reset resetDomainSysInfo {-1} + add_connection bpf_apf_mst.altera_axi4lite_master/bpf_hssi_slv.altera_axi4lite_slave + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_hssi_slv.altera_axi4lite_slave addressMapSysInfo {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_hssi_slv.altera_axi4lite_slave addressWidthSysInfo {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_hssi_slv.altera_axi4lite_slave arbitrationPriority {1} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_hssi_slv.altera_axi4lite_slave baseAddress {0x030000} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_hssi_slv.altera_axi4lite_slave defaultConnection {0} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_hssi_slv.altera_axi4lite_slave domainAlias {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_hssi_slv.altera_axi4lite_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_hssi_slv.altera_axi4lite_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_hssi_slv.altera_axi4lite_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_hssi_slv.altera_axi4lite_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_hssi_slv.altera_axi4lite_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_hssi_slv.altera_axi4lite_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_hssi_slv.altera_axi4lite_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_hssi_slv.altera_axi4lite_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_hssi_slv.altera_axi4lite_slave qsys_mm.syncResets {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_hssi_slv.altera_axi4lite_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_hssi_slv.altera_axi4lite_slave slaveDataWidthSysInfo {-1} + + add_connection bpf_clock_bridge.out_clk/bpf_emif_slv.clock + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_emif_slv.clock clockDomainSysInfo {-1} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_emif_slv.clock clockRateSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_emif_slv.clock clockResetSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_emif_slv.clock resetDomainSysInfo {-1} + add_connection bpf_reset_bridge.out_reset/bpf_emif_slv.reset + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_emif_slv.reset clockDomainSysInfo {-1} + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_emif_slv.reset clockResetSysInfo {} + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_emif_slv.reset resetDomainSysInfo {-1} + add_connection bpf_apf_mst.altera_axi4lite_master/bpf_emif_slv.altera_axi4lite_slave + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_emif_slv.altera_axi4lite_slave addressMapSysInfo {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_emif_slv.altera_axi4lite_slave addressWidthSysInfo {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_emif_slv.altera_axi4lite_slave arbitrationPriority {1} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_emif_slv.altera_axi4lite_slave baseAddress {0x040000} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_emif_slv.altera_axi4lite_slave defaultConnection {0} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_emif_slv.altera_axi4lite_slave domainAlias {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_emif_slv.altera_axi4lite_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_emif_slv.altera_axi4lite_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_emif_slv.altera_axi4lite_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_emif_slv.altera_axi4lite_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_emif_slv.altera_axi4lite_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_emif_slv.altera_axi4lite_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_emif_slv.altera_axi4lite_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_emif_slv.altera_axi4lite_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_emif_slv.altera_axi4lite_slave qsys_mm.syncResets {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_emif_slv.altera_axi4lite_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_emif_slv.altera_axi4lite_slave slaveDataWidthSysInfo {-1} + + add_connection bpf_clock_bridge.out_clk/bpf_rsv_5_slv.clock + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_rsv_5_slv.clock clockDomainSysInfo {-1} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_rsv_5_slv.clock clockRateSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_rsv_5_slv.clock clockResetSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_rsv_5_slv.clock resetDomainSysInfo {-1} + add_connection bpf_reset_bridge.out_reset/bpf_rsv_5_slv.reset + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_rsv_5_slv.reset clockDomainSysInfo {-1} + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_rsv_5_slv.reset clockResetSysInfo {} + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_rsv_5_slv.reset resetDomainSysInfo {-1} + add_connection bpf_apf_mst.altera_axi4lite_master/bpf_rsv_5_slv.altera_axi4lite_slave + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_5_slv.altera_axi4lite_slave addressMapSysInfo {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_5_slv.altera_axi4lite_slave addressWidthSysInfo {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_5_slv.altera_axi4lite_slave arbitrationPriority {1} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_5_slv.altera_axi4lite_slave baseAddress {0x050000} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_5_slv.altera_axi4lite_slave defaultConnection {0} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_5_slv.altera_axi4lite_slave domainAlias {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_5_slv.altera_axi4lite_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_5_slv.altera_axi4lite_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_5_slv.altera_axi4lite_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_5_slv.altera_axi4lite_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_5_slv.altera_axi4lite_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_5_slv.altera_axi4lite_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_5_slv.altera_axi4lite_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_5_slv.altera_axi4lite_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_5_slv.altera_axi4lite_slave qsys_mm.syncResets {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_5_slv.altera_axi4lite_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_5_slv.altera_axi4lite_slave slaveDataWidthSysInfo {-1} + + add_connection bpf_clock_bridge.out_clk/bpf_rsv_6_slv.clock + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_rsv_6_slv.clock clockDomainSysInfo {-1} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_rsv_6_slv.clock clockRateSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_rsv_6_slv.clock clockResetSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_rsv_6_slv.clock resetDomainSysInfo {-1} + add_connection bpf_reset_bridge.out_reset/bpf_rsv_6_slv.reset + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_rsv_6_slv.reset clockDomainSysInfo {-1} + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_rsv_6_slv.reset clockResetSysInfo {} + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_rsv_6_slv.reset resetDomainSysInfo {-1} + add_connection bpf_apf_mst.altera_axi4lite_master/bpf_rsv_6_slv.altera_axi4lite_slave + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_6_slv.altera_axi4lite_slave addressMapSysInfo {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_6_slv.altera_axi4lite_slave addressWidthSysInfo {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_6_slv.altera_axi4lite_slave arbitrationPriority {1} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_6_slv.altera_axi4lite_slave baseAddress {0x060000} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_6_slv.altera_axi4lite_slave defaultConnection {0} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_6_slv.altera_axi4lite_slave domainAlias {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_6_slv.altera_axi4lite_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_6_slv.altera_axi4lite_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_6_slv.altera_axi4lite_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_6_slv.altera_axi4lite_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_6_slv.altera_axi4lite_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_6_slv.altera_axi4lite_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_6_slv.altera_axi4lite_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_6_slv.altera_axi4lite_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_6_slv.altera_axi4lite_slave qsys_mm.syncResets {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_6_slv.altera_axi4lite_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_6_slv.altera_axi4lite_slave slaveDataWidthSysInfo {-1} + + add_connection bpf_clock_bridge.out_clk/bpf_rsv_7_slv.clock + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_rsv_7_slv.clock clockDomainSysInfo {-1} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_rsv_7_slv.clock clockRateSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_rsv_7_slv.clock clockResetSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_rsv_7_slv.clock resetDomainSysInfo {-1} + add_connection bpf_reset_bridge.out_reset/bpf_rsv_7_slv.reset + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_rsv_7_slv.reset clockDomainSysInfo {-1} + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_rsv_7_slv.reset clockResetSysInfo {} + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_rsv_7_slv.reset resetDomainSysInfo {-1} + add_connection bpf_apf_mst.altera_axi4lite_master/bpf_rsv_7_slv.altera_axi4lite_slave + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_7_slv.altera_axi4lite_slave addressMapSysInfo {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_7_slv.altera_axi4lite_slave addressWidthSysInfo {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_7_slv.altera_axi4lite_slave arbitrationPriority {1} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_7_slv.altera_axi4lite_slave baseAddress {0x070000} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_7_slv.altera_axi4lite_slave defaultConnection {0} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_7_slv.altera_axi4lite_slave domainAlias {} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_7_slv.altera_axi4lite_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_7_slv.altera_axi4lite_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_7_slv.altera_axi4lite_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_7_slv.altera_axi4lite_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_7_slv.altera_axi4lite_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_7_slv.altera_axi4lite_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_7_slv.altera_axi4lite_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_7_slv.altera_axi4lite_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_7_slv.altera_axi4lite_slave qsys_mm.syncResets {FALSE} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_7_slv.altera_axi4lite_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value bpf_apf_mst.altera_axi4lite_master/bpf_rsv_7_slv.altera_axi4lite_slave slaveDataWidthSysInfo {-1} + + add_connection bpf_clock_bridge.out_clk/bpf_fme_mst.clock + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_fme_mst.clock clockDomainSysInfo {-1} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_fme_mst.clock clockRateSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_fme_mst.clock clockResetSysInfo {} + set_connection_parameter_value bpf_clock_bridge.out_clk/bpf_fme_mst.clock resetDomainSysInfo {-1} + add_connection bpf_reset_bridge.out_reset/bpf_fme_mst.reset + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_fme_mst.reset clockDomainSysInfo {-1} + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_fme_mst.reset clockResetSysInfo {} + set_connection_parameter_value bpf_reset_bridge.out_reset/bpf_fme_mst.reset resetDomainSysInfo {-1} + add_connection bpf_fme_mst.altera_axi4lite_master/bpf_apf_slv.altera_axi4lite_slave + set_connection_parameter_value bpf_fme_mst.altera_axi4lite_master/bpf_apf_slv.altera_axi4lite_slave addressMapSysInfo {} + set_connection_parameter_value bpf_fme_mst.altera_axi4lite_master/bpf_apf_slv.altera_axi4lite_slave addressWidthSysInfo {} + set_connection_parameter_value bpf_fme_mst.altera_axi4lite_master/bpf_apf_slv.altera_axi4lite_slave arbitrationPriority {1} + set_connection_parameter_value bpf_fme_mst.altera_axi4lite_master/bpf_apf_slv.altera_axi4lite_slave baseAddress {0x000000} + set_connection_parameter_value bpf_fme_mst.altera_axi4lite_master/bpf_apf_slv.altera_axi4lite_slave defaultConnection {0} + set_connection_parameter_value bpf_fme_mst.altera_axi4lite_master/bpf_apf_slv.altera_axi4lite_slave domainAlias {} + set_connection_parameter_value bpf_fme_mst.altera_axi4lite_master/bpf_apf_slv.altera_axi4lite_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value bpf_fme_mst.altera_axi4lite_master/bpf_apf_slv.altera_axi4lite_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value bpf_fme_mst.altera_axi4lite_master/bpf_apf_slv.altera_axi4lite_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value bpf_fme_mst.altera_axi4lite_master/bpf_apf_slv.altera_axi4lite_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value bpf_fme_mst.altera_axi4lite_master/bpf_apf_slv.altera_axi4lite_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value bpf_fme_mst.altera_axi4lite_master/bpf_apf_slv.altera_axi4lite_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value bpf_fme_mst.altera_axi4lite_master/bpf_apf_slv.altera_axi4lite_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value bpf_fme_mst.altera_axi4lite_master/bpf_apf_slv.altera_axi4lite_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value bpf_fme_mst.altera_axi4lite_master/bpf_apf_slv.altera_axi4lite_slave qsys_mm.syncResets {FALSE} + set_connection_parameter_value bpf_fme_mst.altera_axi4lite_master/bpf_apf_slv.altera_axi4lite_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value bpf_fme_mst.altera_axi4lite_master/bpf_apf_slv.altera_axi4lite_slave slaveDataWidthSysInfo {-1} + + set_interface_property bpf_fme_mst EXPORT_OF bpf_fme_mst.altera_axi4lite_slave + set_interface_property bpf_fme_slv EXPORT_OF bpf_fme_slv.altera_axi4lite_master + set_interface_property bpf_pmci_slv EXPORT_OF bpf_pmci_slv.altera_axi4lite_master + set_interface_property bpf_pcie_slv EXPORT_OF bpf_pcie_slv.altera_axi4lite_master + set_interface_property bpf_hssi_slv EXPORT_OF bpf_hssi_slv.altera_axi4lite_master + set_interface_property bpf_emif_slv EXPORT_OF bpf_emif_slv.altera_axi4lite_master + set_interface_property bpf_rsv_5_slv EXPORT_OF bpf_rsv_5_slv.altera_axi4lite_master + set_interface_property bpf_rsv_6_slv EXPORT_OF bpf_rsv_6_slv.altera_axi4lite_master + set_interface_property bpf_rsv_7_slv EXPORT_OF bpf_rsv_7_slv.altera_axi4lite_master + set_interface_property bpf_apf_slv EXPORT_OF bpf_apf_slv.altera_axi4lite_master + set_interface_property bpf_apf_mst EXPORT_OF bpf_apf_mst.altera_axi4lite_slave + + # set the the module properties + set_module_property FILE {bpf.qsys} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {bpf} + + # save the system + sync_sysinfo_parameters + save_system bpf + diff --git a/src/pd_qsys/fabric/dfl2tcl.pl b/src/pd_qsys/fabric/dfl2tcl.pl new file mode 100755 index 0000000..9fc54f2 --- /dev/null +++ b/src/pd_qsys/fabric/dfl2tcl.pl @@ -0,0 +1,683 @@ +#!/usr/bin/env perl +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# Description +#----------------------------------------------------------------------------- +# +# script to generate tcl files for APF/BPF fabric +# +# Date: Oct/2020 +# +# This script generates apf.qsys and bpf.qsys based on dfl.txt in gen_fabric.sh directory +# * apf.qsys - AXI4-lite AFU Peripheral Qsys interconnect fabric +# * bpf.qsys - AXI4-lite Board Peripheral Qsys interconnect fabric +# +# Header fields in dfl.txt +# * REGISTER_NAME : DFH register name +# * FABRIC : {BPF-SLV, BPF-MST, BPF-BID, APF-SLV, APF-MST, APF-BID} +# * BPF-SLV : Device feature is a BPF slave +# * BPF-MST : Device feature is a BPF master +# * BPF-BID : Device feature is a BPF master and slave +# * APF-SLV : Device feature is a APF slave +# * APF-MST : Device feature is a APF master +# * APF-BID : Device feature is a APF master and slave +# * BASE ADDRESS : Device feature base address +# * ADDRESS WIDTH : Device feature address width +# +# Currently only 1 master and 1 slave interface is supported per device feature +# +#-------------------------------------------------------------------------------------------------------- +# | A +# V APF | +# apf_st2mm_mst apf_st2mm_slv +# ___________________|_______________ ___________________|______________ +# | | | | | | +# apf_dev_slv0 ... apf_dev_slv apf_bpf_slv apf_dev_mst0 ... apf_dev_mstN apf_bpf_mst +# | | +# | | +#........................................|..............................................|................. +# | | +# | | +# bpf_apf_mst bpf_apf_slv +# BPF __________|_________ __________|_________ +# | | | | +# bpf_dev_slv0 ... bpf_dev_slvN bpf_dev_mst0 ... bpf_dev_mstN +# + use strict; + use warnings; + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +# Check for right command-line arguments +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + my $num_cmdargs = @ARGV; + die "ERROR: An incorrect number of arguments was specified.\nUsage: $0 \n" if ($num_cmdargs < 3); + my $dfl_file = $ARGV[0]; + my $family = $ARGV[1]; + my $device = $ARGV[2]; + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +# Define/initialize variables +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + # These lists will hold the information for mst/slv: [name, address width] + my @apf_mst; + my @apf_slv; + my @bpf_mst; + my @bpf_slv; + my $line; + my $idx; + my $idy; + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +# Read iofs_dfl.txt -- construct master and slave list apf_mst, apf_slv, bpf_mst, bpf_slv +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + open (IN_FILE, "< $dfl_file") || die "Can't open $dfl_file file!\n"; + open (PKG_FILE, "> fpga_bars.pkg") || die "Can't open fpga_bars.pkg file!\n"; + + # skips 1st line which is a header comment + $line = ; + + # read ./iofs_dfl.txt + while ($line = ) + { + my @dfh_info; + my $device; + my $fabric; + my $interf; + my $base_addr; + my $addr_width; + + # gets the device info: [name, fab/intf, base address, address width] + @dfh_info = split(/\s+/, $line); + + # removes DFH suffix and converts to lower-case + $device = lc($dfh_info[0]); + + # splits the fabric name and interface type + $dfh_info[1] =~ "-"; + $fabric = lc($`); + $interf = lc($'); + + # gets base address and address width + $base_addr = $dfh_info[2]; + $addr_width = $dfh_info[3]; + print " parameter $dfh_info[0]_BASE \t = $base_addr; \t parameter $dfh_info[0]_SIZE \t= $addr_width\t; \n"; + print PKG_FILE " parameter $dfh_info[0]_BASE \t = $base_addr; \t parameter $dfh_info[0]_SIZE \t= $addr_width\t; \n"; + + # construct master and slave array variables + if ($fabric eq "apf") + { + if ($interf eq "mst") + { + push(@apf_mst, [$device, $base_addr, $addr_width]); + } + elsif ($interf eq "slv") + { + push(@apf_slv, [$device, $base_addr, $addr_width]); + } + else + { + push(@apf_mst, [$device, $base_addr, $addr_width]); + push(@apf_slv, [$device, $base_addr, $addr_width]); + } + } + else + { + if ($interf eq "mst") + { + push(@bpf_mst, [$device, $base_addr, $addr_width]); + } + elsif ($interf eq "slv") + { + push(@bpf_slv, [$device, $base_addr, $addr_width]); + } + else + { + push(@bpf_mst, [$device, $base_addr, $addr_width]); + push(@bpf_slv, [$device, $base_addr, $addr_width]); + } + } + } + close PKG_FILE; + close IN_FILE; + print "\n"; + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +# Creates the Qsys tcl file for the Board Peripheral Fabric (BPF) +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + open (TCL_FILE, "> bpf.tcl") || die "Can't open bpf.tcl file!\n"; + print_HEADER("bpf"); + + # add clock and reset for bpf fabric + inst_clk_rst ("bpf"); + conn_clk_rst ("bpf"); + exp_clk_rst ("bpf"); + + # instantiate interfaces between apf and bpf fabrics + + inst_mst_if ("apf" , "bpf" , 19 ); # instantiate bpf_apf_master + conn_dev_clkrst("apf" , "bpf" , "mst"); + inst_slv_if ("apf" , "bpf" , 20 ); # instantiate bpf_apf_slave + conn_dev_clkrst("apf" , "bpf" , "slv"); + + # enumerate bpf devices + for $idx (0 .. $#bpf_mst) + { + inst_mst_if($bpf_mst[$idx][0], "bpf", 20); + } + for $idx (0 .. $#bpf_slv) + { + inst_slv_if($bpf_slv[$idx][0], "bpf", $bpf_slv[$idx][2]); + } + + # add connections to clkrst for bpf devices + # add connections to bpf master to device slace, and device master to bpf slave + + for $idx (0 .. $#bpf_slv) + { + conn_dev_clkrst($bpf_slv[$idx][0], "bpf", "slv"); + conn_slv_dev ($bpf_slv[$idx][0], "bpf", "apf", $bpf_slv[$idx][1]); + } + for $idx (0 .. $#bpf_mst) + { + conn_dev_clkrst($bpf_mst[$idx][0], "bpf", "mst" ); + conn_mst_dev ($bpf_mst[$idx][0], "bpf", "apf", $bpf_mst[$idx][1]); + } + + # export external bpf interfaces to be connected by RTL + for $idx (0 .. $#bpf_mst) + { + exp_dev_if($bpf_mst[$idx][0], "bpf", "mst" ); + } + for $idx (0 .. $#bpf_slv) + { + exp_dev_if($bpf_slv[$idx][0], "bpf", "slv" ); + } + exp_dev_if ("apf", "bpf", "slv"); + exp_dev_if ("apf", "bpf", "mst"); + + print_FOOTER("bpf"); + close TCL_FILE; + +##++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +## Creates the Qsys tcl file for the AFU Peripheral Fabric (APF) +##++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + open (TCL_FILE, "> apf.tcl") || die "Can't open apf.tcl file!\n"; + print_HEADER("apf"); + + # add clock and reset for bpf fabric + inst_clk_rst ("apf"); + conn_clk_rst ("apf"); + exp_clk_rst ("apf"); + + # instantiate interfaces between apf and bpf fabrics + inst_mst_if ("bpf", "apf", 21); + conn_dev_clkrst("bpf", "apf", "mst"); + exp_dev_if ("bpf", "apf", "mst"); + + inst_slv_if ("bpf", "apf", 19); + conn_dev_clkrst("bpf", "apf", "slv"); + exp_dev_if ("bpf", "apf", "slv"); + + # instantiate interfaces st2mm master + inst_mst_if ("st2mm", "apf", 21); + conn_dev_clkrst("st2mm", "apf", "mst"); + exp_dev_if ("st2mm", "apf", "mst"); + + # instantiate outgoing soc_2_host port on apf (a[21]==0, forward to host) + inst_slv_if ("soc_2_host", "apf", 20); + conn_dev_clkrst("soc_2_host", "apf", "slv"); + exp_dev_if ("soc_2_host", "apf", "slv"); + + # instantiate incoming host_2_soc port (a[21]==1, forwarded by host) + inst_mst_if ("host_2_soc", "apf", 20); + conn_dev_clkrst("host_2_soc", "apf", "mst"); + exp_dev_if ("host_2_soc", "apf", "mst"); + + # enumerate/instantiate apf devices + + for $idx (0 .. $#apf_slv) + { + inst_slv_if($apf_slv[$idx][0], "apf", $apf_slv[$idx][2]); + } + for $idx (0 .. $#apf_mst) + { + inst_mst_if($apf_mst[$idx][0], "apf", $apf_mst[$idx][2]); + } + + # connect apf/bpf link to st2mm + conn_slv_dev ("bpf", "apf", "st2mm" , 0x000000); + conn_mst_dev ("bpf", "apf", "st2mm" , 0x000000); + conn_slv_dev ("bpf", "apf", "soc_2_host", 0x100000); + conn_mst_dev ("bpf", "apf", "host_2_soc", 0x000000); + + # add connections to clkrst for each instance + # add connections to apf master to device slace, and device master to apf slave + + for $idx (0 .. $#apf_slv) + { + conn_dev_clkrst($apf_slv[$idx][0], "apf", "slv"); + conn_slv_dev ($apf_slv[$idx][0], "apf", "st2mm", $apf_slv[$idx][1]); + conn_slv_dev ($apf_slv[$idx][0], "apf", "host_2_soc", $apf_slv[$idx][1]); + } + for $idx (0 .. $#apf_mst) + { + conn_dev_clkrst($apf_mst[$idx][0], "apf", "mst" ); + conn_mst_dev ($apf_mst[$idx][0], "apf", "st2mm", 0x0); + } + + # export external apf interfaces to be connected by RTL + for $idx (0 .. $#apf_mst) + { + exp_dev_if($apf_mst[$idx][0], "apf", "mst" ); + } + for $idx (0 .. $#apf_slv) + { + exp_dev_if($apf_slv[$idx][0], "apf", "slv" ); + } + print_FOOTER("apf"); + close TCL_FILE; + + exit 0; + +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +# tasks that includes the associated tcl snippets +#++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +# This function prints the TCL file header lines +sub print_HEADER +{ + my $fab = shift(@_); + print TCL_FILE "package require -exact qsys 18.0 + + # create the system + create_system $fab + set_project_property DEVICE $device + set_project_property DEVICE_FAMILY $family + set_project_property HIDE_FROM_IP_CATALOG {false} + set_use_testbench_naming_pattern 0 {} + + + # add the components"; +} + +# This function instantiates the CLK and RST bridges +sub inst_clk_rst +{ + my $fab = shift(@_); + print TCL_FILE " + add_component ${fab}_clock_bridge ip/${fab}/${fab}_clock_bridge.ip altera_clock_bridge ${fab}_clock_bridge + load_component ${fab}_clock_bridge + set_component_parameter_value EXPLICIT_CLOCK_RATE {0.0} + set_component_parameter_value NUM_CLOCK_OUTPUTS {1} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation ${fab}_clock_bridge + remove_instantiation_interfaces_and_ports + add_instantiation_interface in_clk clock INPUT + set_instantiation_interface_parameter_value in_clk clockRate {0} + set_instantiation_interface_parameter_value in_clk externallyDriven {false} + set_instantiation_interface_parameter_value in_clk ptfSchematicName {} + add_instantiation_interface_port in_clk in_clk clk 1 STD_LOGIC Input + add_instantiation_interface out_clk clock OUTPUT + set_instantiation_interface_parameter_value out_clk associatedDirectClock {in_clk} + set_instantiation_interface_parameter_value out_clk clockRate {0} + set_instantiation_interface_parameter_value out_clk clockRateKnown {false} + set_instantiation_interface_parameter_value out_clk externallyDriven {false} + set_instantiation_interface_parameter_value out_clk ptfSchematicName {} + set_instantiation_interface_sysinfo_parameter_value out_clk clock_rate {0} + add_instantiation_interface_port out_clk out_clk clk 1 STD_LOGIC Output + save_instantiation + + add_component ${fab}_reset_bridge ip/${fab}/${fab}_reset_bridge.ip altera_reset_bridge ${fab}_reset_bridge + load_component ${fab}_reset_bridge + set_component_parameter_value ACTIVE_LOW_RESET {1} + set_component_parameter_value NUM_RESET_OUTPUTS {1} + set_component_parameter_value SYNCHRONOUS_EDGES {deassert} + set_component_parameter_value SYNC_RESET {0} + set_component_parameter_value USE_RESET_REQUEST {0} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation ${fab}_reset_bridge + remove_instantiation_interfaces_and_ports + add_instantiation_interface clk clock INPUT + set_instantiation_interface_parameter_value clk clockRate {0} + set_instantiation_interface_parameter_value clk externallyDriven {false} + set_instantiation_interface_parameter_value clk ptfSchematicName {} + add_instantiation_interface_port clk clk clk 1 STD_LOGIC Input + add_instantiation_interface in_reset reset INPUT + set_instantiation_interface_parameter_value in_reset associatedClock {clk} + set_instantiation_interface_parameter_value in_reset synchronousEdges {DEASSERT} + add_instantiation_interface_port in_reset in_reset_n reset_n 1 STD_LOGIC Input + add_instantiation_interface out_reset reset OUTPUT + set_instantiation_interface_parameter_value out_reset associatedClock {clk} + set_instantiation_interface_parameter_value out_reset associatedDirectReset {in_reset} + set_instantiation_interface_parameter_value out_reset associatedResetSinks {in_reset} + set_instantiation_interface_parameter_value out_reset synchronousEdges {DEASSERT} + add_instantiation_interface_port out_reset out_reset_n reset_n 1 STD_LOGIC Output + save_instantiation + "; +} + +# This function instantiates a SLV interface for a peripheral device +sub inst_slv_if +{ + my $dev = shift(@_); + my $fab = shift(@_); + my $aw = shift(@_); + my $cap = 16 ; + + print TCL_FILE " + add_component ${fab}_${dev}_slv ip/${fab}/${fab}_${dev}_slv.ip axi4lite_shim ${fab}_${dev}_slv 1.0 + load_component ${fab}_${dev}_slv + set_component_parameter_value AW {$aw} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {$cap} + set_component_parameter_value READ_ISSUING_CAPABILITY {$cap} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {$cap/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation ${fab}_${dev}_slv + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {$cap} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {$cap} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {$cap} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {$cap/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {$cap} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {$cap/4} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr $aw STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr $aw STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {$cap} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {$cap} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {$cap} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {$cap/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {$cap} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {$cap/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr $aw STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr $aw STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + "; +} + +# This function instantiates a MST interface for a peripheral device +sub inst_mst_if +{ + my $dev = shift(@_); + my $fab = shift(@_); + my $aw = shift(@_); + my $cap = 16 ; + + print TCL_FILE " + add_component ${fab}_${dev}_mst ip/${fab}/${fab}_${dev}_mst.ip axi4lite_shim ${fab}_${dev}_mst 1.0 + load_component ${fab}_${dev}_mst + set_component_parameter_value AW {$aw} + set_component_parameter_value DW {64} + set_component_parameter_value COMBINED_ISSUING_CAPABILITY {$cap} + set_component_parameter_value READ_ISSUING_CAPABILITY {$cap} + set_component_parameter_value WRITE_ISSUING_CAPABILITY {$cap/4} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation ${fab}_${dev}_mst + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_slave axi4lite INPUT + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_slave associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_slave bridgesToMaster {} + set_instantiation_interface_parameter_value altera_axi4lite_slave combinedAcceptanceCapability {$cap} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingReads {$cap} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingTransactions {$cap} + set_instantiation_interface_parameter_value altera_axi4lite_slave maximumOutstandingWrites {$cap/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readAcceptanceCapability {$cap} + set_instantiation_interface_parameter_value altera_axi4lite_slave writeAcceptanceCapability {$cap/4} + set_instantiation_interface_parameter_value altera_axi4lite_slave readDataReorderingDepth {1} + set_instantiation_interface_parameter_value altera_axi4lite_slave trustzoneAware {true} + add_instantiation_interface_port altera_axi4lite_slave s_awaddr awaddr $aw STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_wdata wdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wstrb wstrb 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_wvalid wvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_araddr araddr $aw STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_slave s_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_slave s_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rdata rdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_slave s_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_slave s_rready rready 1 STD_LOGIC Input + add_instantiation_interface altera_axi4lite_master axi4lite OUTPUT + set_instantiation_interface_parameter_value altera_axi4lite_master associatedClock {clock} + set_instantiation_interface_parameter_value altera_axi4lite_master associatedReset {reset} + set_instantiation_interface_parameter_value altera_axi4lite_master combinedIssuingCapability {$cap} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingReads {$cap} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingTransactions {$cap} + set_instantiation_interface_parameter_value altera_axi4lite_master maximumOutstandingWrites {$cap/4} + set_instantiation_interface_parameter_value altera_axi4lite_master readIssuingCapability {$cap} + set_instantiation_interface_parameter_value altera_axi4lite_master trustzoneAware {true} + set_instantiation_interface_parameter_value altera_axi4lite_master writeIssuingCapability {$cap/4} + add_instantiation_interface_port altera_axi4lite_master m_awaddr awaddr $aw STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_wdata wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wstrb wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_araddr araddr $aw STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port altera_axi4lite_master m_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port altera_axi4lite_master m_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rdata rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port altera_axi4lite_master m_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port altera_axi4lite_master m_rready rready 1 STD_LOGIC Output + save_instantiation + "; +} + +# This function adds the connections between CLK bridge and RST bridge +sub conn_clk_rst +{ + my $fab = shift(@_); + + # Connecting the CLK to the RST bridge + print TCL_FILE " + # add the connections + add_connection ${fab}_clock_bridge.out_clk/${fab}_reset_bridge.clk + set_connection_parameter_value ${fab}_clock_bridge.out_clk/${fab}_reset_bridge.clk clockDomainSysInfo {-1} + set_connection_parameter_value ${fab}_clock_bridge.out_clk/${fab}_reset_bridge.clk clockRateSysInfo {} + set_connection_parameter_value ${fab}_clock_bridge.out_clk/${fab}_reset_bridge.clk clockResetSysInfo {} + set_connection_parameter_value ${fab}_clock_bridge.out_clk/${fab}_reset_bridge.clk resetDomainSysInfo {-1} + "; +} + +sub conn_dev_clkrst +{ + my $dev = shift(@_); + my $fab = shift(@_); + my $itf = shift(@_); + + # Connection to CLK and RST bridges + print TCL_FILE " + add_connection ${fab}_clock_bridge.out_clk/${fab}_${dev}_${itf}.clock + set_connection_parameter_value ${fab}_clock_bridge.out_clk/${fab}_${dev}_${itf}.clock clockDomainSysInfo {-1} + set_connection_parameter_value ${fab}_clock_bridge.out_clk/${fab}_${dev}_${itf}.clock clockRateSysInfo {} + set_connection_parameter_value ${fab}_clock_bridge.out_clk/${fab}_${dev}_${itf}.clock clockResetSysInfo {} + set_connection_parameter_value ${fab}_clock_bridge.out_clk/${fab}_${dev}_${itf}.clock resetDomainSysInfo {-1} + add_connection ${fab}_reset_bridge.out_reset/${fab}_${dev}_${itf}.reset + set_connection_parameter_value ${fab}_reset_bridge.out_reset/${fab}_${dev}_${itf}.reset clockDomainSysInfo {-1} + set_connection_parameter_value ${fab}_reset_bridge.out_reset/${fab}_${dev}_${itf}.reset clockResetSysInfo {} + set_connection_parameter_value ${fab}_reset_bridge.out_reset/${fab}_${dev}_${itf}.reset resetDomainSysInfo {-1}"; +} + +sub conn_slv_dev +{ + my $dev = shift(@_); + my $fab = shift(@_); + my $mst = shift(@_); + my $addr = shift(@_); + + # Connection to the default APF<->BPF interface + print TCL_FILE " + add_connection ${fab}_${mst}_mst.altera_axi4lite_master/${fab}_${dev}_slv.altera_axi4lite_slave + set_connection_parameter_value ${fab}_${mst}_mst.altera_axi4lite_master/${fab}_${dev}_slv.altera_axi4lite_slave addressMapSysInfo {} + set_connection_parameter_value ${fab}_${mst}_mst.altera_axi4lite_master/${fab}_${dev}_slv.altera_axi4lite_slave addressWidthSysInfo {} + set_connection_parameter_value ${fab}_${mst}_mst.altera_axi4lite_master/${fab}_${dev}_slv.altera_axi4lite_slave arbitrationPriority {1} + set_connection_parameter_value ${fab}_${mst}_mst.altera_axi4lite_master/${fab}_${dev}_slv.altera_axi4lite_slave baseAddress {$addr} + set_connection_parameter_value ${fab}_${mst}_mst.altera_axi4lite_master/${fab}_${dev}_slv.altera_axi4lite_slave defaultConnection {0} + set_connection_parameter_value ${fab}_${mst}_mst.altera_axi4lite_master/${fab}_${dev}_slv.altera_axi4lite_slave domainAlias {} + set_connection_parameter_value ${fab}_${mst}_mst.altera_axi4lite_master/${fab}_${dev}_slv.altera_axi4lite_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value ${fab}_${mst}_mst.altera_axi4lite_master/${fab}_${dev}_slv.altera_axi4lite_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value ${fab}_${mst}_mst.altera_axi4lite_master/${fab}_${dev}_slv.altera_axi4lite_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value ${fab}_${mst}_mst.altera_axi4lite_master/${fab}_${dev}_slv.altera_axi4lite_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value ${fab}_${mst}_mst.altera_axi4lite_master/${fab}_${dev}_slv.altera_axi4lite_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value ${fab}_${mst}_mst.altera_axi4lite_master/${fab}_${dev}_slv.altera_axi4lite_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value ${fab}_${mst}_mst.altera_axi4lite_master/${fab}_${dev}_slv.altera_axi4lite_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value ${fab}_${mst}_mst.altera_axi4lite_master/${fab}_${dev}_slv.altera_axi4lite_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value ${fab}_${mst}_mst.altera_axi4lite_master/${fab}_${dev}_slv.altera_axi4lite_slave qsys_mm.syncResets {FALSE} + set_connection_parameter_value ${fab}_${mst}_mst.altera_axi4lite_master/${fab}_${dev}_slv.altera_axi4lite_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value ${fab}_${mst}_mst.altera_axi4lite_master/${fab}_${dev}_slv.altera_axi4lite_slave slaveDataWidthSysInfo {-1} + "; +} + +sub conn_mst_dev +{ + my $dev = shift(@_); + my $fab = shift(@_); + my $slv = shift(@_); + my $addr = shift(@_); + + # Connection to the default APF<->BPF interface + print TCL_FILE " + add_connection ${fab}_${dev}_mst.altera_axi4lite_master/${fab}_${slv}_slv.altera_axi4lite_slave + set_connection_parameter_value ${fab}_${dev}_mst.altera_axi4lite_master/${fab}_${slv}_slv.altera_axi4lite_slave addressMapSysInfo {} + set_connection_parameter_value ${fab}_${dev}_mst.altera_axi4lite_master/${fab}_${slv}_slv.altera_axi4lite_slave addressWidthSysInfo {} + set_connection_parameter_value ${fab}_${dev}_mst.altera_axi4lite_master/${fab}_${slv}_slv.altera_axi4lite_slave arbitrationPriority {1} + set_connection_parameter_value ${fab}_${dev}_mst.altera_axi4lite_master/${fab}_${slv}_slv.altera_axi4lite_slave baseAddress {$addr} + set_connection_parameter_value ${fab}_${dev}_mst.altera_axi4lite_master/${fab}_${slv}_slv.altera_axi4lite_slave defaultConnection {0} + set_connection_parameter_value ${fab}_${dev}_mst.altera_axi4lite_master/${fab}_${slv}_slv.altera_axi4lite_slave domainAlias {} + set_connection_parameter_value ${fab}_${dev}_mst.altera_axi4lite_master/${fab}_${slv}_slv.altera_axi4lite_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value ${fab}_${dev}_mst.altera_axi4lite_master/${fab}_${slv}_slv.altera_axi4lite_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value ${fab}_${dev}_mst.altera_axi4lite_master/${fab}_${slv}_slv.altera_axi4lite_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value ${fab}_${dev}_mst.altera_axi4lite_master/${fab}_${slv}_slv.altera_axi4lite_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value ${fab}_${dev}_mst.altera_axi4lite_master/${fab}_${slv}_slv.altera_axi4lite_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value ${fab}_${dev}_mst.altera_axi4lite_master/${fab}_${slv}_slv.altera_axi4lite_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value ${fab}_${dev}_mst.altera_axi4lite_master/${fab}_${slv}_slv.altera_axi4lite_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value ${fab}_${dev}_mst.altera_axi4lite_master/${fab}_${slv}_slv.altera_axi4lite_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value ${fab}_${dev}_mst.altera_axi4lite_master/${fab}_${slv}_slv.altera_axi4lite_slave qsys_mm.syncResets {FALSE} + set_connection_parameter_value ${fab}_${dev}_mst.altera_axi4lite_master/${fab}_${slv}_slv.altera_axi4lite_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value ${fab}_${dev}_mst.altera_axi4lite_master/${fab}_${slv}_slv.altera_axi4lite_slave slaveDataWidthSysInfo {-1} + "; +} + +sub exp_clk_rst +{ + my $fab = shift(@_); + + print TCL_FILE " + # add the exports + set_interface_property clk EXPORT_OF ${fab}_clock_bridge.in_clk + set_interface_property rst_n EXPORT_OF ${fab}_reset_bridge.in_reset"; +} + +sub exp_dev_if +{ + my $dev = shift(@_); + my $fab = shift(@_); + my $itf = shift(@_); + + my $dir = ""; + $dir = "master" if ($itf eq "slv"); + $dir = "slave" if ($itf eq "mst"); + + print TCL_FILE " + set_interface_property ${fab}_${dev}_${itf} EXPORT_OF ${fab}_${dev}_${itf}.altera_axi4lite_${dir}"; +} + +# This function prints the TCL file footer lines +sub print_FOOTER +{ + my $dev = shift(@_); + print TCL_FILE " + + # set the the module properties + set_module_property FILE {$dev.qsys} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {$dev} + + # save the system + sync_sysinfo_parameters + save_system $dev + "; +} + diff --git a/src/pd_qsys/fabric/fpga_bars.pkg b/src/pd_qsys/fabric/fpga_bars.pkg new file mode 100644 index 0000000..61e6351 --- /dev/null +++ b/src/pd_qsys/fabric/fpga_bars.pkg @@ -0,0 +1,17 @@ + parameter FME_BASE = 0x000000; parameter FME_SIZE = 20 ; + parameter FME_BASE = 0x000000; parameter FME_SIZE = 16 ; + parameter PMCI_BASE = 0x010000; parameter PMCI_SIZE = 16 ; + parameter PCIE_BASE = 0x020000; parameter PCIE_SIZE = 16 ; + parameter HSSI_BASE = 0x030000; parameter HSSI_SIZE = 16 ; + parameter EMIF_BASE = 0x040000; parameter EMIF_SIZE = 16 ; + parameter RSV_5_BASE = 0x050000; parameter RSV_5_SIZE = 16 ; + parameter RSV_6_BASE = 0x060000; parameter RSV_6_SIZE = 16 ; + parameter RSV_7_BASE = 0x070000; parameter RSV_7_SIZE = 16 ; + parameter ST2MM_BASE = 0x080000; parameter ST2MM_SIZE = 16 ; + parameter PGSK_BASE = 0x090000; parameter PGSK_SIZE = 16 ; + parameter ACHK_BASE = 0x0a0000; parameter ACHK_SIZE = 16 ; + parameter RSV_b_BASE = 0x0b0000; parameter RSV_b_SIZE = 16 ; + parameter RSV_c_BASE = 0x0c0000; parameter RSV_c_SIZE = 16 ; + parameter RSV_d_BASE = 0x0d0000; parameter RSV_d_SIZE = 16 ; + parameter RSV_e_BASE = 0x0e0000; parameter RSV_e_SIZE = 16 ; + parameter RSV_f_BASE = 0x0f0000; parameter RSV_f_SIZE = 16 ; diff --git a/src/pd_qsys/fabric/gen_fabrics.sh b/src/pd_qsys/fabric/gen_fabrics.sh new file mode 100755 index 0000000..be69574 --- /dev/null +++ b/src/pd_qsys/fabric/gen_fabrics.sh @@ -0,0 +1,29 @@ +#!/bin/bash +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# Description +#----------------------------------------------------------------------------- +# commands collection to generate APF/BPF fabric +# + SCRIPT_DIR="$(cd "$(dirname -- "${BASH_SOURCE[0]}")" 2>/dev/null && pwd -P)" + set PROJECT=d5005 + + # Clean up old generated files + rm -rf apf* bpf* ip* *ipx *qpf *qsf + + # Generate BPF/APF Qsys scripts using dfl.txt as input + $SCRIPT_DIR/dfl2tcl.pl iofs_dfl.txt "Stratix10" "1SX280HN2F43E2VG" + + # Create apf.qsys interconnect fabric + $QUARTUS_HOME/sopc_builder/bin/qsys-script --new-quartus-project=$PROJECT --script=apf.tcl + + # Create bpf.qsys interconnect fabric + $QUARTUS_HOME/sopc_builder/bin/qsys-script -qpf=$PROJECT --script=bpf.tcl + + # Generate apf.qsys + $QUARTUS_HOME/sopc_builder/bin/qsys-generate -syn=VERILOG -sim=VERILOG -qpf=$PROJECT apf.qsys + + # Generate bpf.qsys + $QUARTUS_HOME/sopc_builder/bin/qsys-generate -syn=VERILOG -sim=VERILOG -qpf=$PROJECT bpf.qsys + diff --git a/src/pd_qsys/fabric/hdk.qpf b/src/pd_qsys/fabric/hdk.qpf new file mode 100644 index 0000000..dd934e6 --- /dev/null +++ b/src/pd_qsys/fabric/hdk.qpf @@ -0,0 +1,17 @@ +# Copyright 2022 Intel Corporation +# SPDX-License-Identifier: MIT + +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 21.1.0 Build 169 03/24/2021 SC Pro Edition +# Date created = 09:26:21 June 01, 2021 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "21.1" +DATE = "09:26:21 June 01, 2021" + +# Revisions + +PROJECT_REVISION = "hdk" diff --git a/src/pd_qsys/fabric/hdk.qsf b/src/pd_qsys/fabric/hdk.qsf new file mode 100644 index 0000000..0117e4b --- /dev/null +++ b/src/pd_qsys/fabric/hdk.qsf @@ -0,0 +1,37 @@ +# Copyright (C) 2022 Intel Corporation +# SPDX-License-Identifier: MIT + +set_global_assignment -name TOP_LEVEL_ENTITY hdk +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:26:21 JUNE 01, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "22.1.0 Pro Edition" +set_global_assignment -name FAMILY "Stratix 10" +set_global_assignment -name DEVICE 1SX280HN2F43E2VG +set_global_assignment -name IP_FILE ip/apf/apf_clock_bridge.ip +set_global_assignment -name IP_FILE ip/apf/apf_reset_bridge.ip +set_global_assignment -name IP_FILE ip/apf/apf_bpf_mst.ip +set_global_assignment -name IP_FILE ip/apf/apf_bpf_slv.ip +set_global_assignment -name IP_FILE ip/apf/apf_st2mm_mst.ip +set_global_assignment -name IP_FILE ip/apf/apf_st2mm_slv.ip +set_global_assignment -name IP_FILE ip/apf/apf_pgsk_slv.ip +set_global_assignment -name IP_FILE ip/apf/apf_achk_slv.ip +set_global_assignment -name IP_FILE ip/apf/apf_rsv_b_slv.ip +set_global_assignment -name IP_FILE ip/apf/apf_rsv_c_slv.ip +set_global_assignment -name IP_FILE ip/apf/apf_rsv_d_slv.ip +set_global_assignment -name IP_FILE ip/apf/apf_rsv_e_slv.ip +set_global_assignment -name IP_FILE ip/apf/apf_rsv_f_slv.ip +set_global_assignment -name QSYS_FILE apf.qsys +set_global_assignment -name IP_FILE ip/bpf/bpf_clock_bridge.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_reset_bridge.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_apf_mst.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_apf_slv.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_fme_mst.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_fme_slv.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_pmci_slv.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_pcie_slv.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_hssi_slv.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_emif_slv.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_rsv_5_slv.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_rsv_6_slv.ip +set_global_assignment -name IP_FILE ip/bpf/bpf_rsv_7_slv.ip +set_global_assignment -name QSYS_FILE bpf.qsys diff --git a/src/pd_qsys/fabric/iofs_dfl.txt b/src/pd_qsys/fabric/iofs_dfl.txt new file mode 100755 index 0000000..35c3f8f --- /dev/null +++ b/src/pd_qsys/fabric/iofs_dfl.txt @@ -0,0 +1,18 @@ +REGISTER FABRIC BASE_ADDR BAR_SIZE=2^N +FME BPF-MST 0x000000 20 +FME BPF-SLV 0x000000 16 +PMCI BPF-SLV 0x010000 16 +PCIE BPF-SLV 0x020000 16 +HSSI BPF-SLV 0x030000 16 +EMIF BPF-SLV 0x040000 16 +RSV_5 BPF-SLV 0x050000 16 +RSV_6 BPF-SLV 0x060000 16 +RSV_7 BPF-SLV 0x070000 16 +ST2MM APF-SLV 0x080000 16 +PGSK APF-SLV 0x090000 16 +ACHK APF-SLV 0x0a0000 16 +RSV_b APF-SLV 0x0b0000 16 +RSV_c APF-SLV 0x0c0000 16 +RSV_d APF-SLV 0x0d0000 16 +RSV_e APF-SLV 0x0e0000 16 +RSV_f APF-SLV 0x0f0000 16 diff --git a/src/pd_qsys/fabric/ip/apf/apf_achk_slv.ip b/src/pd_qsys/fabric/ip/apf/apf_achk_slv.ip new file mode 100644 index 0000000..c6781b9 --- /dev/null +++ b/src/pd_qsys/fabric/ip/apf/apf_achk_slv.ip @@ -0,0 +1,1800 @@ + + + + Altera Corporation + apf_achk_slv + apf_achk_slv + 1.0 + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + altera_axi4lite_slave + + + + + + + + awaddr + + + s_awaddr + + + + + awprot + + + s_awprot + + + + + awvalid + + + s_awvalid + + + + + awready + + + s_awready + + + + + wdata + + + s_wdata + + + + + wstrb + + + s_wstrb + + + + + wvalid + + + s_wvalid + + + + + wready + + + s_wready + + + + + bresp + + + s_bresp + + + + + bvalid + + + s_bvalid + + + + + bready + + + s_bready + + + + + araddr + + + s_araddr + + + + + arprot + + + s_arprot + + + + + arvalid + + + s_arvalid + + + + + arready + + + s_arready + + + + + rdata + + + s_rdata + + + + + rresp + + + s_rresp + + + + + rvalid + + + s_rvalid + + + + + rready + + + s_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readAcceptanceCapability + Read acceptance capability + 1 + + + writeAcceptanceCapability + Write acceptance capability + 1 + + + combinedAcceptanceCapability + Combined acceptance capability + 1 + + + readDataReorderingDepth + Read data reordering depth + 1 + + + bridgesToMaster + bridgesToMaster + + + + + + altera_axi4lite_master + + + + + + + + awaddr + + + m_awaddr + + + + + awprot + + + m_awprot + + + + + awvalid + + + m_awvalid + + + + + awready + + + m_awready + + + + + wdata + + + m_wdata + + + + + wstrb + + + m_wstrb + + + + + wvalid + + + m_wvalid + + + + + wready + + + m_wready + + + + + bresp + + + m_bresp + + + + + bvalid + + + m_bvalid + + + + + bready + + + m_bready + + + + + araddr + + + m_araddr + + + + + arprot + + + m_arprot + + + + + arvalid + + + m_arvalid + + + + + arready + + + m_arready + + + + + rdata + + + m_rdata + + + + + rresp + + + m_rresp + + + + + rvalid + + + m_rvalid + + + + + rready + + + m_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readIssuingCapability + Read issuing capability + 1 + + + writeIssuingCapability + Write issuing capability + 1 + + + combinedIssuingCapability + Combined issuing capability + 1 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + noRepeatedIdsBetweenSubordinates + noRepeatedIdsBetweenSubordinates + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + axi4lite_shim + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awaddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awvalid + + in + + + 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Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element apf_achk_slv + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/apf/apf_bpf_mst.ip b/src/pd_qsys/fabric/ip/apf/apf_bpf_mst.ip new file mode 100644 index 0000000..561d7bb --- /dev/null +++ b/src/pd_qsys/fabric/ip/apf/apf_bpf_mst.ip @@ -0,0 +1,1800 @@ + + + + Altera Corporation + apf_bpf_mst + apf_bpf_mst + 1.0 + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + altera_axi4lite_slave + + + + + + + + awaddr + + + s_awaddr + + + + + awprot + + + s_awprot + + + + + awvalid + + + s_awvalid + + + + + awready + + + s_awready + + + + + wdata + + + s_wdata + + + + + wstrb + + + s_wstrb + + + + + wvalid + + + s_wvalid + + + + + wready + + + s_wready + + + + + bresp + + + s_bresp + + + + + bvalid + + + s_bvalid + + + + + bready + + + s_bready + + + + + araddr + + + s_araddr + + + + + arprot + + + s_arprot + + + + + arvalid + + + s_arvalid + + + + + arready + + + s_arready + + + + + rdata + + + s_rdata + + + + + rresp + + + s_rresp + + + + + rvalid + + + s_rvalid + + + + + rready + + + s_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + 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+ <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + 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+ + s_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readAcceptanceCapability + Read acceptance capability + 1 + + + writeAcceptanceCapability + Write acceptance capability + 1 + + + combinedAcceptanceCapability + Combined acceptance capability + 1 + + + readDataReorderingDepth + Read data reordering depth + 1 + + + bridgesToMaster + bridgesToMaster + + + + + + altera_axi4lite_master + + + + + + + + awaddr + + + m_awaddr + + + + + awprot + + + m_awprot + + + + + awvalid + + + m_awvalid + + + + + awready + + + m_awready + + + + + wdata + + + m_wdata + + + + + wstrb + + + m_wstrb + + + + + wvalid + + + m_wvalid + + + + + wready + + + m_wready + + + + + bresp + + + m_bresp + + + + + bvalid + + + m_bvalid + + + + + bready + + + m_bready + + + + + araddr + + + m_araddr + + + + + arprot + + + m_arprot + + + + + arvalid + + + m_arvalid + + + + + arready + + + m_arready + + + + + rdata + + + m_rdata + + + + + rresp + + + m_rresp + + + + + rvalid + + + m_rvalid + + + + + rready + + + m_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readIssuingCapability + Read issuing capability + 1 + + + writeIssuingCapability + Write issuing capability + 1 + + + combinedIssuingCapability + Combined issuing capability + 1 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + noRepeatedIdsBetweenSubordinates + noRepeatedIdsBetweenSubordinates + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + axi4lite_shim + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awaddr + + in + + + 0 + 18 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wstrb + + in + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_bvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_araddr + + in + + + 0 + 18 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_arready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_rdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_rresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_rvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_rready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awaddr + + out + + + 0 + 18 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_wdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_wstrb + + out + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_wvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_wready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_bvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_araddr + + out + + + 0 + 18 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_arready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Altera Corporation + apf_bpf_slv + axi4lite_shim + 1.0 + + + + + AW + AW + 19 + + + DW + DW + 64 + + + WRITE_ISSUING_CAPABILITY + Write Issuing Capability + 16 + + + READ_ISSUING_CAPABILITY + Read Issuing Capability + 16 + + + COMBINED_ISSUING_CAPABILITY + Combined Issuing Capability + 16 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element apf_bpf_slv + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/apf/apf_clock_bridge.ip b/src/pd_qsys/fabric/ip/apf/apf_clock_bridge.ip new file mode 100644 index 0000000..47cf59d --- /dev/null +++ b/src/pd_qsys/fabric/ip/apf/apf_clock_bridge.ip @@ -0,0 +1,346 @@ + + + + Intel Corporation + apf_clock_bridge + apf_clock_bridge + 19.2.0 + + + in_clk + + + + + + + + clk + + + in_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + out_clk + + + + + + + + clk + + + out_clk + + + + + + + + + associatedDirectClock + Associated direct clock + in_clk + + + clockRate + Clock rate + 0 + + + clockRateKnown + Clock rate known + false + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_clock_bridge + + QUARTUS_SYNTH + + + + + + in_clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + out_clk + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + apf_clock_bridge + altera_clock_bridge + 19.2.0 + + + + + DERIVED_CLOCK_RATE + Derived clock rate + 0 + + + EXPLICIT_CLOCK_RATE + Explicit clock rate + 0 + + + NUM_CLOCK_OUTPUTS + Number of Clock Outputs + 1 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element apf_clock_bridge + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>in_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>in_clk</value> + </entry> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>false</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>in_clk</key> + <value> + <connectionPointName>in_clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>out_clk</key> + <value> + <connectionPointName>out_clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/apf/apf_host_2_soc_mst.ip b/src/pd_qsys/fabric/ip/apf/apf_host_2_soc_mst.ip new file mode 100644 index 0000000..0a04e7a --- /dev/null +++ b/src/pd_qsys/fabric/ip/apf/apf_host_2_soc_mst.ip @@ -0,0 +1,1798 @@ + + + + Altera Corporation + apf_host_2_soc_mst + apf_host_2_soc_mst + 1.0 + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + altera_axi4lite_slave + + + + + + + + awaddr + + + s_awaddr + + + + + awprot + + + s_awprot + + + + + awvalid + + + s_awvalid + + + + + awready + + + s_awready + + + + + wdata + + + s_wdata + + + + + wstrb + + + s_wstrb + + + + + wvalid + + + s_wvalid + + + + + wready + + + s_wready + + + + + bresp + + + s_bresp + + + + + bvalid + + + s_bvalid + + + + + bready + + + s_bready + + + + + araddr + + + s_araddr + + + + + arprot + + + s_arprot + + + + + arvalid + + + s_arvalid + + + + + arready + + + s_arready + + + + + rdata + + + s_rdata + + + + + rresp + + + s_rresp + + + + + rvalid + + + s_rvalid + + + + + rready + + + s_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readAcceptanceCapability + Read acceptance capability + 1 + + + writeAcceptanceCapability + Write acceptance capability + 1 + + + combinedAcceptanceCapability + Combined acceptance capability + 1 + + + readDataReorderingDepth + Read data reordering depth + 1 + + + bridgesToMaster + bridgesToMaster + + + + + + altera_axi4lite_master + + + + + + + + awaddr + + + m_awaddr + + + + + awprot + + + m_awprot + + + + + awvalid + + + m_awvalid + + + + + awready + + + m_awready + + + + + wdata + + + m_wdata + + + + + wstrb + + + m_wstrb + + + + + wvalid + + + m_wvalid + + + + + wready + + + m_wready + + + + + bresp + + + m_bresp + + + + + bvalid + + + m_bvalid + + + + + bready + + + m_bready + + + + + araddr + + + m_araddr + + + + + arprot + + + m_arprot + + + + + arvalid + + + m_arvalid + + + + + arready + + + m_arready + + + + + rdata + + + m_rdata + + + + + rresp + + + m_rresp + + + + + rvalid + + + m_rvalid + + + + + rready + + + m_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readIssuingCapability + Read issuing capability + 1 + + + writeIssuingCapability + Write issuing capability + 1 + + + combinedIssuingCapability + Combined issuing capability + 1 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + axi4lite_shim + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awaddr + + in + + + 0 + 19 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wstrb + + in + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_bvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_araddr + + in + + + 0 + 19 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_arready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_rdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_rresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_rvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_rready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awaddr + + out + + + 0 + 19 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_wdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_wstrb + + out + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_wvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_wready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_bvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_araddr + + out + + + 0 + 19 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_arready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Altera Corporation + apf_host_2_soc_mst + axi4lite_shim + 1.0 + + + + + AW + AW + 20 + + + DW + DW + 64 + + + WRITE_ISSUING_CAPABILITY + Write Issuing Capability + 16 + + + READ_ISSUING_CAPABILITY + Read Issuing Capability + 16 + + + COMBINED_ISSUING_CAPABILITY + Combined Issuing Capability + 16 + + + + + + + board + Board + Unknown + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element $system + { + datum _originalDeviceFamily + { + value = "Stratix 10"; + type = "String"; + } + } + element apf_host_2_soc_mst + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/apf/apf_pgsk_slv.ip b/src/pd_qsys/fabric/ip/apf/apf_pgsk_slv.ip new file mode 100644 index 0000000..0eaa2a0 --- /dev/null +++ b/src/pd_qsys/fabric/ip/apf/apf_pgsk_slv.ip @@ -0,0 +1,1800 @@ + + + + Altera Corporation + apf_pgsk_slv + apf_pgsk_slv + 1.0 + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + altera_axi4lite_slave + + + + + + + + awaddr + + + s_awaddr + + + + + awprot + + + s_awprot + + + + + awvalid + + + s_awvalid + + + + + awready + + + s_awready + + + + + wdata + + + s_wdata + + + + + wstrb + + + s_wstrb + + + + + wvalid + + + s_wvalid + + + + + wready + + + s_wready + + + + + bresp + + + s_bresp + + + + + bvalid + + + s_bvalid + + + + + bready + + + s_bready + + + + + araddr + + + s_araddr + + + + + arprot + + + s_arprot + + + + + arvalid + + + s_arvalid + + + + + arready + + + s_arready + + + + + rdata + + + s_rdata + + + + + rresp + + + s_rresp + + + + + rvalid + + + s_rvalid + + + + + rready + + + s_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readAcceptanceCapability + Read acceptance capability + 1 + + + writeAcceptanceCapability + Write acceptance capability + 1 + + + combinedAcceptanceCapability + Combined acceptance capability + 1 + + + readDataReorderingDepth + Read data reordering depth + 1 + + + bridgesToMaster + bridgesToMaster + + + + + + altera_axi4lite_master + + + + + + + + awaddr + + + m_awaddr + + + + + awprot + + + m_awprot + + + + + awvalid + + + m_awvalid + + + + + awready + + + m_awready + + + + + wdata + + + m_wdata + + + + + wstrb + + + m_wstrb + + + + + wvalid + + + m_wvalid + + + + + wready + + + m_wready + + + + + bresp + + + m_bresp + + + + + bvalid + + + m_bvalid + + + + + bready + + + m_bready + + + + + araddr + + + m_araddr + + + + + arprot + + + m_arprot + + + + + arvalid + + + m_arvalid + + + + + arready + + + m_arready + + + + + rdata + + + m_rdata + + + + + rresp + + + m_rresp + + + + + rvalid + + + m_rvalid + + + + + rready + + + m_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readIssuingCapability + Read issuing capability + 1 + + + writeIssuingCapability + Write issuing capability + 1 + + + combinedIssuingCapability + Combined issuing capability + 1 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + noRepeatedIdsBetweenSubordinates + noRepeatedIdsBetweenSubordinates + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + axi4lite_shim + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awaddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wdata + + in 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s_rready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awaddr + + out + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_wdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_wstrb + + out + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_wvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_wready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_bvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_araddr + + out + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_arready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Altera Corporation + apf_pgsk_slv + axi4lite_shim + 1.0 + + + + + AW + AW + 16 + + + DW + DW + 64 + + + WRITE_ISSUING_CAPABILITY + Write Issuing Capability + 16 + + + READ_ISSUING_CAPABILITY + Read Issuing Capability + 16 + + + COMBINED_ISSUING_CAPABILITY + Combined Issuing Capability + 16 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element apf_pgsk_slv + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/apf/apf_reset_bridge.ip b/src/pd_qsys/fabric/ip/apf/apf_reset_bridge.ip new file mode 100644 index 0000000..163b003 --- /dev/null +++ b/src/pd_qsys/fabric/ip/apf/apf_reset_bridge.ip @@ -0,0 +1,418 @@ + + + + Intel Corporation + apf_reset_bridge + apf_reset_bridge + 19.2.0 + + + clk + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + in_reset + + + + + + + + reset_n + + + in_reset_n + + + + + + + + + associatedClock + Associated clock + clk + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + out_reset + + + + + + + + reset_n + + + out_reset_n + + + + + + + + + associatedClock + Associated clock + clk + + + associatedDirectReset + Associated direct reset + in_reset + + + associatedResetSinks + Associated reset sinks + in_reset + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_reset_bridge + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + in_reset_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + out_reset_n + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + apf_reset_bridge + altera_reset_bridge + 19.2.0 + + + + + ACTIVE_LOW_RESET + Active low reset + 1 + + + SYNCHRONOUS_EDGES + Synchronous edges + deassert + + + NUM_RESET_OUTPUTS + Number of reset outputs + 1 + + + USE_RESET_REQUEST + Use reset request signal + 0 + + + SYNC_RESET + Use synchronous resets + 0 + + + AUTO_CLK_CLOCK_RATE + Auto CLOCK_RATE + -1 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element apf_reset_bridge + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_reset_n</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>-1</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/apf/apf_rsv_b_slv.ip b/src/pd_qsys/fabric/ip/apf/apf_rsv_b_slv.ip new file mode 100644 index 0000000..3b63f03 --- /dev/null +++ b/src/pd_qsys/fabric/ip/apf/apf_rsv_b_slv.ip @@ -0,0 +1,1800 @@ + + + + Altera Corporation + apf_rsv_b_slv + apf_rsv_b_slv + 1.0 + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + altera_axi4lite_slave + + + + + + + + awaddr + + + s_awaddr + + + + + awprot + + + s_awprot + + + + + awvalid + + + s_awvalid + + + + + awready + + + s_awready + + + + + wdata + + + s_wdata + + + + + wstrb + + + s_wstrb + + + + + wvalid + + + s_wvalid + + + + + wready + + + s_wready + + + + + bresp + + + s_bresp + + + + + bvalid + + + s_bvalid + + + + + bready + + + s_bready + + + + + araddr + + + s_araddr + + + + + arprot + + + s_arprot + + + + + arvalid + + + s_arvalid + + + + + arready + + + s_arready + + + + + rdata + + + s_rdata + + + + + rresp + + + s_rresp + + + + + rvalid + + + s_rvalid + + + + + rready + + + s_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readAcceptanceCapability + Read acceptance capability + 1 + + + writeAcceptanceCapability + Write acceptance capability + 1 + + + combinedAcceptanceCapability + Combined acceptance capability + 1 + + + readDataReorderingDepth + Read data reordering depth + 1 + + + bridgesToMaster + bridgesToMaster + + + + + + altera_axi4lite_master + + + + + + + + awaddr + + + m_awaddr + + + + + awprot + + + m_awprot + + + + + awvalid + + + m_awvalid + + + + + awready + + + m_awready + + + + + wdata + + + m_wdata + + + + + wstrb + + + m_wstrb + + + + + wvalid + + + m_wvalid + + + + + wready + + + m_wready + + + + + bresp + + + m_bresp + + + + + bvalid + + + m_bvalid + + + + + bready + + + m_bready + + + + + araddr + + + m_araddr + + + + + arprot + + + m_arprot + + + + + arvalid + + + m_arvalid + + + + + arready + + + m_arready + + + + + rdata + + + m_rdata + + + + + rresp + + + m_rresp + + + + + rvalid + + + m_rvalid + + + + + rready + + + m_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readIssuingCapability + Read issuing capability + 1 + + + writeIssuingCapability + Write issuing capability + 1 + + + combinedIssuingCapability + Combined issuing capability + 1 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + noRepeatedIdsBetweenSubordinates + noRepeatedIdsBetweenSubordinates + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + axi4lite_shim + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awaddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wstrb + + in + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_bvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_araddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_arready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_rdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_rresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_rvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_rready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awaddr + + out + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_wdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_wstrb + + out + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_wvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_wready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_bvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_araddr + + out + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_arready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Altera Corporation + apf_rsv_b_slv + axi4lite_shim + 1.0 + + + + + AW + AW + 16 + + + DW + DW + 64 + + + WRITE_ISSUING_CAPABILITY + Write Issuing Capability + 16 + + + READ_ISSUING_CAPABILITY + Read Issuing Capability + 16 + + + COMBINED_ISSUING_CAPABILITY + Combined Issuing Capability + 16 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element apf_rsv_b_slv + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/apf/apf_rsv_c_slv.ip b/src/pd_qsys/fabric/ip/apf/apf_rsv_c_slv.ip new file mode 100644 index 0000000..d1dcbfa --- /dev/null +++ b/src/pd_qsys/fabric/ip/apf/apf_rsv_c_slv.ip @@ -0,0 +1,1800 @@ + + + + Altera Corporation + apf_rsv_c_slv + apf_rsv_c_slv + 1.0 + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + altera_axi4lite_slave + + + + + + + + awaddr + + + s_awaddr + + + + + awprot + + + s_awprot + + + + + awvalid + + + s_awvalid + + + + + awready + + + s_awready + + + + + wdata + + + s_wdata + + + + + wstrb + + + s_wstrb + + + + + wvalid + + + s_wvalid + + + + + wready + + + s_wready + + + + + bresp + + + s_bresp + + + + + bvalid + + + s_bvalid + + + + + bready + + + s_bready + + + + + araddr + + + s_araddr + + + + + arprot + + + s_arprot + + + + + arvalid + + + s_arvalid + + + + + arready + + + s_arready + + + + + rdata + + + s_rdata + + + + + rresp + + + s_rresp + + + + + rvalid + + + s_rvalid + + + + + rready + + + s_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readAcceptanceCapability + Read acceptance capability + 1 + + + writeAcceptanceCapability + Write acceptance capability + 1 + + + combinedAcceptanceCapability + Combined acceptance capability + 1 + + + readDataReorderingDepth + Read data reordering depth + 1 + + + bridgesToMaster + bridgesToMaster + + + + + + altera_axi4lite_master + + + + + + + + awaddr + + + m_awaddr + + + + + awprot + + + m_awprot + + + + + awvalid + + + m_awvalid + + + + + awready + + + m_awready + + + + + wdata + + + m_wdata + + + + + wstrb + + + m_wstrb + + + + + wvalid + + + m_wvalid + + + + + wready + + + m_wready + + + + + bresp + + + m_bresp + + + + + bvalid + + + m_bvalid + + + + + bready + + + m_bready + + + + + araddr + + + m_araddr + + + + + arprot + + + m_arprot + + + + + arvalid + + + m_arvalid + + + + + arready + + + m_arready + + + + + rdata + + + m_rdata + + + + + rresp + + + m_rresp + + + + + rvalid + + + m_rvalid + + + + + rready + + + m_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readIssuingCapability + Read issuing capability + 1 + + + writeIssuingCapability + Write issuing capability + 1 + + + combinedIssuingCapability + Combined issuing capability + 1 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + noRepeatedIdsBetweenSubordinates + noRepeatedIdsBetweenSubordinates + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + axi4lite_shim + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awaddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wstrb + + in + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_bvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_araddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_arready + + out + + + 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in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_araddr + + out + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_arready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Altera Corporation + apf_rsv_c_slv + axi4lite_shim + 1.0 + + + + + AW + AW + 16 + + + DW + DW + 64 + + + WRITE_ISSUING_CAPABILITY + Write Issuing Capability + 16 + + + READ_ISSUING_CAPABILITY + Read Issuing Capability + 16 + + + COMBINED_ISSUING_CAPABILITY + Combined Issuing Capability + 16 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element apf_rsv_c_slv + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/apf/apf_rsv_d_slv.ip b/src/pd_qsys/fabric/ip/apf/apf_rsv_d_slv.ip new file mode 100644 index 0000000..0395628 --- /dev/null +++ b/src/pd_qsys/fabric/ip/apf/apf_rsv_d_slv.ip @@ -0,0 +1,1800 @@ + + + + Altera Corporation + apf_rsv_d_slv + apf_rsv_d_slv + 1.0 + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + altera_axi4lite_slave + + + + + + + + awaddr + + + s_awaddr + + + + + awprot + + + s_awprot + + + + + awvalid + + + s_awvalid + + + + + awready + + + s_awready + + + + + wdata + + + s_wdata + + + + + wstrb + + + s_wstrb + + + + + wvalid + + + s_wvalid + + + + + wready + + + s_wready + + + + + bresp + + + s_bresp + + + + + bvalid + + + s_bvalid + + + + + bready + + + s_bready + + + + + araddr + + + s_araddr + + + + + arprot + + + s_arprot + + + + + arvalid + + + s_arvalid + + + + + arready + + + s_arready + + + + + rdata + + + s_rdata + + + + + rresp + + + s_rresp + + + + + rvalid + + + s_rvalid + + + + + rready + + + s_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readAcceptanceCapability + Read acceptance capability + 1 + + + writeAcceptanceCapability + Write acceptance capability + 1 + + + combinedAcceptanceCapability + Combined acceptance capability + 1 + + + readDataReorderingDepth + Read data reordering depth + 1 + + + bridgesToMaster + bridgesToMaster + + + + + + altera_axi4lite_master + + + + + + + + awaddr + + + m_awaddr + + + + + awprot + + + m_awprot + + + + + awvalid + + + m_awvalid + + + + + awready + + + m_awready + + + + + wdata + + + m_wdata + + + + + wstrb + + + m_wstrb + + + + + wvalid + + + m_wvalid + + + + + wready + + + m_wready + + + + + bresp + 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noRepeatedIdsBetweenSubordinates + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + axi4lite_shim + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awaddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wstrb + + in + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_bvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + 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+ + + + + + + + Altera Corporation + apf_rsv_d_slv + axi4lite_shim + 1.0 + + + + + AW + AW + 16 + + + DW + DW + 64 + + + WRITE_ISSUING_CAPABILITY + Write Issuing Capability + 16 + + + READ_ISSUING_CAPABILITY + Read Issuing Capability + 16 + + + COMBINED_ISSUING_CAPABILITY + Combined Issuing Capability + 16 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element apf_rsv_d_slv + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/apf/apf_rsv_e_slv.ip b/src/pd_qsys/fabric/ip/apf/apf_rsv_e_slv.ip new file mode 100644 index 0000000..348a3ca --- /dev/null +++ b/src/pd_qsys/fabric/ip/apf/apf_rsv_e_slv.ip @@ -0,0 +1,1800 @@ + + + + Altera Corporation + apf_rsv_e_slv + apf_rsv_e_slv + 1.0 + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + altera_axi4lite_slave + + + + + + + + awaddr + + + s_awaddr + + + + + awprot + + + s_awprot + + + + + awvalid + + + s_awvalid + + + + + awready + + + s_awready + + + + + wdata + + + s_wdata + + + + + wstrb + + + s_wstrb + + + + + wvalid + + + s_wvalid + + + + + wready + + + s_wready + + + + + bresp + + + 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readIssuingCapability + Read issuing capability + 1 + + + writeIssuingCapability + Write issuing capability + 1 + + + combinedIssuingCapability + Combined issuing capability + 1 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + noRepeatedIdsBetweenSubordinates + noRepeatedIdsBetweenSubordinates + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + axi4lite_shim + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awaddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wstrb + + in + + + 0 + 7 + + + + + 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Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/apf/apf_rsv_f_slv.ip b/src/pd_qsys/fabric/ip/apf/apf_rsv_f_slv.ip new file mode 100644 index 0000000..daad617 --- /dev/null +++ b/src/pd_qsys/fabric/ip/apf/apf_rsv_f_slv.ip @@ -0,0 +1,1800 @@ + + + + Altera Corporation + apf_rsv_f_slv + apf_rsv_f_slv + 1.0 + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + altera_axi4lite_slave + + + + + + + + awaddr + + + s_awaddr + + + + + awprot + + + s_awprot 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acceptance capability + 1 + + + combinedAcceptanceCapability + Combined acceptance capability + 1 + + + readDataReorderingDepth + Read data reordering depth + 1 + + + bridgesToMaster + bridgesToMaster + + + + + + altera_axi4lite_master + + + + + + + + awaddr + + + m_awaddr + + + + + awprot + + + m_awprot + + + + + awvalid + + + m_awvalid + + + + + awready + + + m_awready + + + + + wdata + + + m_wdata + + + + + wstrb + + + m_wstrb + + + + + wvalid + + + m_wvalid + + + + + wready + + + m_wready + + + + + bresp + + + m_bresp + + + + + bvalid + + + m_bvalid + + + + + bready + + + m_bready + + + + + araddr + + + m_araddr + + + + + arprot + + + m_arprot + + + + + arvalid + + + m_arvalid + + + + + arready + + + m_arready + + + + + rdata + + + m_rdata + + + + + rresp + + + m_rresp + + + + + rvalid + + + m_rvalid + + + + + rready + + + m_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readIssuingCapability + Read issuing capability + 1 + + + writeIssuingCapability + Write issuing capability + 1 + + + combinedIssuingCapability + Combined issuing capability + 1 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + noRepeatedIdsBetweenSubordinates + noRepeatedIdsBetweenSubordinates + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + axi4lite_shim + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awaddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awvalid + + in + + + STD_LOGIC + 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STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_arready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Altera Corporation + apf_rsv_f_slv + axi4lite_shim + 1.0 + + + + + AW + AW + 16 + + + DW + DW + 64 + + + WRITE_ISSUING_CAPABILITY + Write Issuing Capability + 16 + + + READ_ISSUING_CAPABILITY + Read Issuing Capability + 16 + + + COMBINED_ISSUING_CAPABILITY + Combined Issuing Capability + 16 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element apf_rsv_f_slv + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/apf/apf_soc_2_host_slv.ip b/src/pd_qsys/fabric/ip/apf/apf_soc_2_host_slv.ip new file mode 100644 index 0000000..57b188a --- /dev/null +++ b/src/pd_qsys/fabric/ip/apf/apf_soc_2_host_slv.ip @@ -0,0 +1,1798 @@ + + + + Altera Corporation + apf_soc_2_host_slv + apf_soc_2_host_slv + 1.0 + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + altera_axi4lite_slave + + + + + + + + awaddr + + + s_awaddr + + + + + awprot + + + s_awprot + + + + + awvalid + + + s_awvalid + + + + + awready + + + s_awready + + + + + wdata + + + s_wdata + + + + + wstrb + + + s_wstrb + + + + + wvalid + + + s_wvalid + + + + + wready + + + s_wready + + + + + bresp + + + s_bresp + + + + + bvalid + + + s_bvalid + + + + + bready + + + s_bready + + + + + araddr + + + s_araddr + + + + + arprot + + + s_arprot + + + + + arvalid + + + s_arvalid + + + + + arready + + + s_arready + + + + + rdata + + + s_rdata + + + + + rresp + + + s_rresp + + + + + rvalid + + + s_rvalid + + + + + rready + + + s_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readAcceptanceCapability + Read acceptance capability + 1 + + + writeAcceptanceCapability + Write acceptance capability + 1 + + + combinedAcceptanceCapability + Combined acceptance capability + 1 + + + readDataReorderingDepth + Read data reordering depth + 1 + + + bridgesToMaster + bridgesToMaster + + + + + + altera_axi4lite_master + + + + + + + + awaddr + + + m_awaddr + + + + + awprot + + + m_awprot + + + + + awvalid + + + m_awvalid + + + + + awready + + + m_awready + + + + + wdata + + + m_wdata + + + + + wstrb + + + m_wstrb + + + + + wvalid + + + m_wvalid + + + + + wready + + + m_wready + + + + + bresp + + + m_bresp + + + + + bvalid + + + m_bvalid + + + + + bready + + + m_bready + + + + + araddr + + + m_araddr + + + + + arprot + + + m_arprot + + + + + arvalid + + + m_arvalid + + + + + arready + + + m_arready + + + + + rdata + + + m_rdata + + + + + rresp + + + m_rresp + + + + + rvalid + + + m_rvalid + + + + + rready + + + m_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readIssuingCapability + Read issuing capability + 1 + + + writeIssuingCapability + Write issuing capability + 1 + + + combinedIssuingCapability + Combined issuing capability + 1 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + axi4lite_shim + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awaddr + + in + + + 0 + 19 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wstrb + + in + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_bvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_araddr + + in + + + 0 + 19 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_arready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_rdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_rresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_rvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_rready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awaddr + + out + + + 0 + 19 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_wdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_wstrb + + out + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_wvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_wready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_bvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_araddr + + out + + + 0 + 19 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_arready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Altera Corporation + apf_soc_2_host_slv + axi4lite_shim + 1.0 + + + + + AW + AW + 20 + + + DW + DW + 64 + + + WRITE_ISSUING_CAPABILITY + Write Issuing Capability + 16 + + + READ_ISSUING_CAPABILITY + Read Issuing Capability + 16 + + + COMBINED_ISSUING_CAPABILITY + Combined Issuing Capability + 16 + + + + + + + board + Board + Unknown + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element $system + { + datum _originalDeviceFamily + { + value = "Stratix 10"; + type = "String"; + } + } + element apf_soc_2_host_slv + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/apf/apf_st2mm_mst.ip b/src/pd_qsys/fabric/ip/apf/apf_st2mm_mst.ip new file mode 100644 index 0000000..53a93dd --- /dev/null +++ b/src/pd_qsys/fabric/ip/apf/apf_st2mm_mst.ip @@ -0,0 +1,1800 @@ + + + + Altera Corporation + apf_st2mm_mst + apf_st2mm_mst + 1.0 + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + altera_axi4lite_slave + + + + + + + + awaddr + + + s_awaddr + + + + + awprot + + + s_awprot + + + + + awvalid + + + s_awvalid + + + + + awready + + + s_awready + + + + + wdata + + + s_wdata + + + + + wstrb + + + s_wstrb + + + + + wvalid + + + s_wvalid + + + + + wready + + + s_wready + + + + + bresp + + + s_bresp + + + + + bvalid + + + s_bvalid + + + + + bready + + + s_bready + + + + + araddr + + + s_araddr + + + + + arprot + + + s_arprot + + + + + arvalid + + + s_arvalid + + + + + arready + + + s_arready + + + + + rdata + + + s_rdata + + + + + rresp + + + s_rresp + + + + + rvalid + + + s_rvalid + + + + + rready + + + s_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readAcceptanceCapability + Read acceptance capability + 1 + + + writeAcceptanceCapability + Write acceptance capability + 1 + + + combinedAcceptanceCapability + Combined acceptance capability + 1 + + + readDataReorderingDepth + Read data reordering depth + 1 + + + bridgesToMaster + bridgesToMaster + + + + + + altera_axi4lite_master + + + + + + + + awaddr + + + m_awaddr + + + + + awprot + + + m_awprot + + + + + awvalid + + + m_awvalid + + + + + awready + + + m_awready + + + + + wdata + + + m_wdata + + + + + wstrb + + + m_wstrb + + + + + wvalid + + + m_wvalid + + + + + wready + + + m_wready + + + + + bresp + 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noRepeatedIdsBetweenSubordinates + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + axi4lite_shim + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awaddr + + in + + + 0 + 19 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wstrb + + in + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_bvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + 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+ + + + + + + + Altera Corporation + apf_st2mm_mst + axi4lite_shim + 1.0 + + + + + AW + AW + 20 + + + DW + DW + 64 + + + WRITE_ISSUING_CAPABILITY + Write Issuing Capability + 16 + + + READ_ISSUING_CAPABILITY + Read Issuing Capability + 16 + + + COMBINED_ISSUING_CAPABILITY + Combined Issuing Capability + 16 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element apf_st2mm_mst + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/apf/apf_st2mm_slv.ip b/src/pd_qsys/fabric/ip/apf/apf_st2mm_slv.ip new file mode 100644 index 0000000..8f8847a --- /dev/null +++ b/src/pd_qsys/fabric/ip/apf/apf_st2mm_slv.ip @@ -0,0 +1,1800 @@ + + + + Altera Corporation + apf_st2mm_slv + apf_st2mm_slv + 1.0 + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + altera_axi4lite_slave + + + + + + + + awaddr + + + s_awaddr + + + + + awprot + + + s_awprot + + + + + awvalid + + + s_awvalid + + + + + awready + + + s_awready + + + + + wdata + + + s_wdata + + + + + wstrb + + + s_wstrb + + + + + wvalid + + + s_wvalid + + + + + wready + + + s_wready + + + + + bresp + + + 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readIssuingCapability + Read issuing capability + 1 + + + writeIssuingCapability + Write issuing capability + 1 + + + combinedIssuingCapability + Combined issuing capability + 1 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + noRepeatedIdsBetweenSubordinates + noRepeatedIdsBetweenSubordinates + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + axi4lite_shim + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awaddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wstrb + + in + + + 0 + 7 + + + + + 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Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/bpf/bpf_apf_mst.ip b/src/pd_qsys/fabric/ip/bpf/bpf_apf_mst.ip new file mode 100644 index 0000000..380ac2e --- /dev/null +++ b/src/pd_qsys/fabric/ip/bpf/bpf_apf_mst.ip @@ -0,0 +1,1800 @@ + + + + Altera Corporation + bpf_apf_mst + bpf_apf_mst + 1.0 + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + altera_axi4lite_slave + + + + + + + + awaddr + + + s_awaddr + + + + + awprot + + + s_awprot + + + + + awvalid + + + s_awvalid + + + + + awready + + + s_awready + + + + + wdata + + + s_wdata + + + + + wstrb + + + s_wstrb + + + + + wvalid + + + s_wvalid + + + + + wready + + + s_wready + + + + + bresp + + + s_bresp + + + + + bvalid + + + s_bvalid + + + + + bready + + + s_bready + + + + + araddr + + + s_araddr + + + + + arprot + + + s_arprot + + + + + arvalid + + + s_arvalid + + + + + arready + + + s_arready + + + + + rdata + + + s_rdata + + + + + rresp + + + s_rresp + + + + + rvalid + + + s_rvalid + + + + + rready + + + s_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readAcceptanceCapability + Read acceptance capability + 1 + + + writeAcceptanceCapability + Write acceptance capability + 1 + + + combinedAcceptanceCapability + Combined acceptance capability + 1 + + + readDataReorderingDepth + Read data reordering depth + 1 + + + bridgesToMaster + bridgesToMaster + + + + + + altera_axi4lite_master + + + + + + + + awaddr + + + m_awaddr + + + + + awprot + + + m_awprot + + + + + awvalid + + + m_awvalid + + + + + awready + + + m_awready + + + + + wdata + + + m_wdata + + + + + wstrb + + + m_wstrb + + + + + wvalid + + + m_wvalid + + + + + wready + + + m_wready + + + + + bresp + + + m_bresp + + + + + bvalid + + + m_bvalid + + + + + bready + + + m_bready + + + + + araddr + + + m_araddr + + + + + arprot + + + m_arprot + + + + + arvalid + + + m_arvalid + + + + + arready + + + m_arready + + + + + rdata + + + m_rdata + + + + + rresp + + + m_rresp + + + + + rvalid + + + m_rvalid + + + + + rready + + + m_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readIssuingCapability + Read issuing capability + 1 + + + writeIssuingCapability + Write issuing capability + 1 + + + combinedIssuingCapability + Combined issuing capability + 1 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + noRepeatedIdsBetweenSubordinates + noRepeatedIdsBetweenSubordinates + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + axi4lite_shim + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awaddr + + in + + + 0 + 18 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wstrb + + in + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_bvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_araddr + + in + + + 0 + 18 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_arready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_rdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_rresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_rvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_rready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awaddr + + out + + + 0 + 18 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_wdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_wstrb + + out + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_wvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_wready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_bvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_araddr + + out + + + 0 + 18 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_arready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Altera Corporation + bpf_apf_mst + axi4lite_shim + 1.0 + + + + + AW + AW + 19 + + + DW + DW + 64 + + + WRITE_ISSUING_CAPABILITY + Write Issuing Capability + 16 + + + READ_ISSUING_CAPABILITY + Read Issuing Capability + 16 + + + COMBINED_ISSUING_CAPABILITY + Combined Issuing Capability + 16 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element bpf_apf_mst + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>19</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/bpf/bpf_apf_slv.ip b/src/pd_qsys/fabric/ip/bpf/bpf_apf_slv.ip new file mode 100644 index 0000000..9daf257 --- /dev/null +++ b/src/pd_qsys/fabric/ip/bpf/bpf_apf_slv.ip @@ -0,0 +1,1800 @@ + + + + Altera Corporation + bpf_apf_slv + bpf_apf_slv + 1.0 + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + 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COMBINED_ISSUING_CAPABILITY + Combined Issuing Capability + 16 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element bpf_apf_slv + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/bpf/bpf_clock_bridge.ip b/src/pd_qsys/fabric/ip/bpf/bpf_clock_bridge.ip new file mode 100644 index 0000000..ecaa8ab --- /dev/null +++ b/src/pd_qsys/fabric/ip/bpf/bpf_clock_bridge.ip @@ -0,0 +1,346 @@ + + + + Intel Corporation + bpf_clock_bridge + bpf_clock_bridge + 19.2.0 + + + in_clk + + + + + + + + clk + + + in_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + out_clk + + + + + + + + clk + + + out_clk + + + + + + + + + associatedDirectClock + Associated direct clock + in_clk + + + clockRate + Clock rate + 0 + + + clockRateKnown + Clock rate known + false + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_clock_bridge + + QUARTUS_SYNTH + + + + + + in_clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + out_clk + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + bpf_clock_bridge + altera_clock_bridge + 19.2.0 + + + + + DERIVED_CLOCK_RATE + Derived clock rate + 0 + + + EXPLICIT_CLOCK_RATE + Explicit clock rate + 0 + + + NUM_CLOCK_OUTPUTS + Number of Clock Outputs + 1 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element bpf_clock_bridge + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>in_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>in_clk</value> + </entry> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>false</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>in_clk</key> + <value> + <connectionPointName>in_clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>out_clk</key> + <value> + <connectionPointName>out_clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/bpf/bpf_emif_slv.ip b/src/pd_qsys/fabric/ip/bpf/bpf_emif_slv.ip new file mode 100644 index 0000000..cde3383 --- /dev/null +++ b/src/pd_qsys/fabric/ip/bpf/bpf_emif_slv.ip @@ -0,0 +1,1800 @@ + + + + Altera Corporation + bpf_emif_slv + bpf_emif_slv + 1.0 + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + altera_axi4lite_slave + + + + + + + + awaddr + + + s_awaddr + + + + + awprot + + + s_awprot + + + + + awvalid + + + s_awvalid + + + + + awready + + + s_awready + + + + + wdata + + + s_wdata + + + + + wstrb + + + s_wstrb + + + + + wvalid + + + s_wvalid + + + + + wready + + + s_wready + + + + + bresp + + + s_bresp + + + + + bvalid + + + s_bvalid + + + + + bready + + + s_bready + + + + + araddr + + + s_araddr + + + + + arprot + + + s_arprot + + + + + arvalid + + + s_arvalid + + + + + arready + + + s_arready + + + + + rdata + + + s_rdata + + + + + rresp + + + s_rresp + + + + + rvalid + + + s_rvalid + + + + + rready + + + s_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readAcceptanceCapability + Read acceptance capability + 1 + + + writeAcceptanceCapability + Write acceptance capability + 1 + + + combinedAcceptanceCapability + Combined acceptance capability + 1 + + + readDataReorderingDepth + Read data reordering depth + 1 + + + bridgesToMaster + bridgesToMaster + + + + + + altera_axi4lite_master + + + + + + + + awaddr + + + m_awaddr + + + + + awprot + + + m_awprot + + + + + awvalid + + + m_awvalid + + + + + awready + + + m_awready + + + + + wdata + + + m_wdata + + + + + wstrb + + + m_wstrb + + + + + wvalid + + + m_wvalid + + + + + wready + + + m_wready + + + + + bresp + + + m_bresp + + + + + bvalid + + + m_bvalid + + + + + bready + + + m_bready + + + + + araddr + + + m_araddr + + + + + arprot + + + m_arprot + + + + + arvalid + + + m_arvalid + + + + + arready + + + m_arready + + + + + rdata + + + m_rdata + + + + + rresp + + + m_rresp + + + + + rvalid + + + m_rvalid + + + + + rready + + + m_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readIssuingCapability + Read issuing capability + 1 + + + writeIssuingCapability + Write issuing capability + 1 + + + combinedIssuingCapability + Combined issuing capability + 1 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + noRepeatedIdsBetweenSubordinates + noRepeatedIdsBetweenSubordinates + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + axi4lite_shim + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awaddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wstrb + + in + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_bvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_araddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_arready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_rdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_rresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_rvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_rready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awaddr + + out + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_wdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_wstrb + + out + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_wvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_wready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_bvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_araddr + + out + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_arready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Altera Corporation + bpf_emif_slv + axi4lite_shim + 1.0 + + + + + AW + AW + 16 + + + DW + DW + 64 + + + WRITE_ISSUING_CAPABILITY + Write Issuing Capability + 16 + + + READ_ISSUING_CAPABILITY + Read Issuing Capability + 16 + + + COMBINED_ISSUING_CAPABILITY + Combined Issuing Capability + 16 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element bpf_emif_slv + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/bpf/bpf_fme_mst.ip b/src/pd_qsys/fabric/ip/bpf/bpf_fme_mst.ip new file mode 100644 index 0000000..d31e489 --- /dev/null +++ b/src/pd_qsys/fabric/ip/bpf/bpf_fme_mst.ip @@ -0,0 +1,1800 @@ + + + + Altera Corporation + bpf_fme_mst + bpf_fme_mst + 1.0 + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + altera_axi4lite_slave + + + + + + + + awaddr + + + s_awaddr + + + + + awprot + + + s_awprot + + + + + awvalid + + + s_awvalid + + + + + awready + + + s_awready + + + + + wdata + + + s_wdata + + + + + wstrb + + + s_wstrb + + + + + wvalid + + + s_wvalid + + + + + wready + + + s_wready + + + + + bresp + + + s_bresp + + + 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readIssuingCapability + Read issuing capability + 1 + + + writeIssuingCapability + Write issuing capability + 1 + + + combinedIssuingCapability + Combined issuing capability + 1 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + noRepeatedIdsBetweenSubordinates + noRepeatedIdsBetweenSubordinates + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + axi4lite_shim + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awaddr + + in + + + 0 + 19 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wstrb + + in + + + 0 + 7 + + + + + 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from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>20</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/bpf/bpf_fme_slv.ip b/src/pd_qsys/fabric/ip/bpf/bpf_fme_slv.ip new file mode 100644 index 0000000..14dcdd4 --- /dev/null +++ b/src/pd_qsys/fabric/ip/bpf/bpf_fme_slv.ip @@ -0,0 +1,1800 @@ + + + + Altera Corporation + bpf_fme_slv + bpf_fme_slv + 1.0 + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + altera_axi4lite_slave + + + + + + + + awaddr + + + s_awaddr + + + + + awprot + + + s_awprot + + + + + awvalid + + + s_awvalid + + + + + awready + + + s_awready + + + + + wdata + + + s_wdata + + + + + wstrb + + + s_wstrb + + + + + wvalid + + + s_wvalid + + + + + wready + + + s_wready + + + + + bresp + + + s_bresp + + + + + bvalid + + + s_bvalid + + + + + bready + + + s_bready + + + + + araddr + + + s_araddr + + + + + arprot + + + s_arprot + + + + + arvalid + + + s_arvalid + + + + + arready + + + s_arready + + + + + rdata + + + s_rdata + + + + + rresp + + + s_rresp + + + + + rvalid + + + s_rvalid + + + + + rready + + + s_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readAcceptanceCapability + Read acceptance capability + 1 + + + writeAcceptanceCapability + Write acceptance capability + 1 + + + combinedAcceptanceCapability + Combined acceptance capability + 1 + + + readDataReorderingDepth + Read data reordering depth + 1 + + + bridgesToMaster + bridgesToMaster + + + + + + altera_axi4lite_master + + + + + + + + awaddr + + + m_awaddr + + + + + awprot + + + m_awprot + + + + + awvalid + + + m_awvalid + + + + + awready + + + m_awready + + + + + wdata + + + m_wdata + + + + + wstrb + + + m_wstrb + + + + + wvalid + + + m_wvalid + + + + + wready + + + m_wready + + + + + bresp + + + m_bresp + + + + + bvalid + + + m_bvalid + + + + + bready + + + m_bready + + + + + araddr + + + m_araddr + + + + + arprot + + + m_arprot + + + + + arvalid + + + m_arvalid + + + + + arready + + + m_arready + + + + + rdata + + + m_rdata + + + + + rresp + + + m_rresp + + + + + rvalid + + + m_rvalid + + + + + rready + + + m_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readIssuingCapability + Read issuing capability + 1 + + + writeIssuingCapability + Write issuing capability + 1 + + + combinedIssuingCapability + Combined issuing capability + 1 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + noRepeatedIdsBetweenSubordinates + noRepeatedIdsBetweenSubordinates + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + axi4lite_shim + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awaddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wstrb + + in + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_bvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_araddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_arready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_rdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_rresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_rvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_rready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awaddr + + out + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_wdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_wstrb + + out + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_wvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_wready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_bvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_araddr + + out + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_arready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Altera Corporation + bpf_fme_slv + axi4lite_shim + 1.0 + + + + + AW + AW + 16 + + + DW + DW + 64 + + + WRITE_ISSUING_CAPABILITY + Write Issuing Capability + 16 + + + READ_ISSUING_CAPABILITY + Read Issuing Capability + 16 + + + COMBINED_ISSUING_CAPABILITY + Combined Issuing Capability + 16 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element bpf_fme_slv + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/bpf/bpf_hssi_slv.ip b/src/pd_qsys/fabric/ip/bpf/bpf_hssi_slv.ip new file mode 100644 index 0000000..796b870 --- /dev/null +++ b/src/pd_qsys/fabric/ip/bpf/bpf_hssi_slv.ip @@ -0,0 +1,1800 @@ + + + + Altera Corporation + bpf_hssi_slv + bpf_hssi_slv + 1.0 + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + altera_axi4lite_slave + + + + + + + + awaddr + + + s_awaddr + + + + + awprot + + + s_awprot + + + + + awvalid + + + s_awvalid + + + + + awready + + + s_awready + + + + + wdata + + + s_wdata + + + + + wstrb + + + s_wstrb + + + + + wvalid + + + s_wvalid + + + + + wready + + + s_wready + + + + + bresp + + + s_bresp + + + + + bvalid + + + s_bvalid + + + + + bready + + + s_bready + + + + + araddr + + + s_araddr + + + + + arprot + + + s_arprot + + + + + arvalid + + + s_arvalid + + + + + arready + + + s_arready + + + + + rdata + + + s_rdata + + + + + rresp + + + s_rresp + + + + + rvalid + + + s_rvalid + + + + + rready + + + s_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readAcceptanceCapability + Read acceptance capability + 1 + + + writeAcceptanceCapability + Write acceptance capability + 1 + + + combinedAcceptanceCapability + Combined acceptance capability + 1 + + + readDataReorderingDepth + Read data reordering depth + 1 + + + bridgesToMaster + bridgesToMaster + + + + + + altera_axi4lite_master + + + + + + + + awaddr + + + m_awaddr + + + + + awprot + + + m_awprot + + + + + awvalid + + + m_awvalid + + + + + awready + + + m_awready + + + + + wdata + + + m_wdata + + + + + wstrb + + + m_wstrb + + + + + wvalid + + + m_wvalid + + + + + wready + + + m_wready + + + + + bresp + + + m_bresp + + + + + bvalid + + + m_bvalid + + + + + bready + + + m_bready + + + + + araddr + + + m_araddr + + + + + arprot + + + m_arprot + + + + + arvalid + + + m_arvalid + + + + + arready + + + m_arready + + + + + rdata + + + m_rdata + + + + + rresp + + + m_rresp + + + + + rvalid + + + m_rvalid + + + + + rready + + + m_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readIssuingCapability + Read issuing capability + 1 + + + writeIssuingCapability + Write issuing capability + 1 + + + combinedIssuingCapability + Combined issuing capability + 1 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + noRepeatedIdsBetweenSubordinates + noRepeatedIdsBetweenSubordinates + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + axi4lite_shim + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awaddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wstrb + + in + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_bvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_araddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_arready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_rdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_rresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_rvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_rready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awaddr + + out + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_wdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_wstrb + + out + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_wvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_wready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_bvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_araddr + + out + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_arready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Altera Corporation + bpf_hssi_slv + axi4lite_shim + 1.0 + + + + + AW + AW + 16 + + + DW + DW + 64 + + + WRITE_ISSUING_CAPABILITY + Write Issuing Capability + 16 + + + READ_ISSUING_CAPABILITY + Read Issuing Capability + 16 + + + COMBINED_ISSUING_CAPABILITY + Combined Issuing Capability + 16 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element bpf_hssi_slv + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/bpf/bpf_pcie_slv.ip b/src/pd_qsys/fabric/ip/bpf/bpf_pcie_slv.ip new file mode 100644 index 0000000..9116482 --- /dev/null +++ b/src/pd_qsys/fabric/ip/bpf/bpf_pcie_slv.ip @@ -0,0 +1,1800 @@ + + + + Altera Corporation + bpf_pcie_slv + bpf_pcie_slv + 1.0 + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + altera_axi4lite_slave + + + + + + + + awaddr + + + s_awaddr + + + + + awprot + + + s_awprot + + + + + awvalid + + + s_awvalid + + + + + awready + + + s_awready + + + + + wdata + + + s_wdata + + + + + wstrb + + + s_wstrb + + + + + wvalid + + + s_wvalid + + + + + wready + + + s_wready + + + + + bresp + + + s_bresp + + + + + bvalid + + + s_bvalid + + + + + bready + + + s_bready + + + + + araddr + + + s_araddr + + + + + arprot + + + s_arprot + + + + + arvalid + + + s_arvalid + + + + + arready + + + s_arready + + + + + rdata + + + s_rdata + + + + + rresp + + + s_rresp + + + + + rvalid + + + s_rvalid + + + + + rready + + + s_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readAcceptanceCapability + Read acceptance capability + 1 + + + writeAcceptanceCapability + Write acceptance capability + 1 + + + combinedAcceptanceCapability + Combined acceptance capability + 1 + + + readDataReorderingDepth + Read data reordering depth + 1 + + + bridgesToMaster + bridgesToMaster + + + + + + altera_axi4lite_master + + + + + + + + awaddr + + + m_awaddr + + + + + awprot + + + m_awprot + + + + + awvalid + + + m_awvalid + + + + + awready + + + m_awready + + + + + wdata + + + m_wdata + + + + + wstrb + + + m_wstrb + + + + + wvalid + + + m_wvalid + + + + + wready + + + m_wready + + + + + bresp + + + m_bresp + + + + + bvalid + + + m_bvalid + + + + + bready + + + m_bready + + + + + araddr + + + m_araddr + + + + + arprot + + + m_arprot + + + + + arvalid + + + m_arvalid + + + + + arready + + + m_arready + + + + + rdata + + + m_rdata + + + + + rresp + + + m_rresp + + + + + rvalid + + + m_rvalid + + + + + rready + + + m_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readIssuingCapability + Read issuing capability + 1 + + + writeIssuingCapability + Write issuing capability + 1 + + + combinedIssuingCapability + Combined issuing capability + 1 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + noRepeatedIdsBetweenSubordinates + noRepeatedIdsBetweenSubordinates + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + axi4lite_shim + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awaddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wstrb + + in + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_bvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_araddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_arready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_rdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_rresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_rvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_rready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awaddr + + out + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_wdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_wstrb + + out + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_wvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_wready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_bvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_araddr + + out + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_arready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Altera Corporation + bpf_pcie_slv + axi4lite_shim + 1.0 + + + + + AW + AW + 16 + + + DW + DW + 64 + + + WRITE_ISSUING_CAPABILITY + Write Issuing Capability + 16 + + + READ_ISSUING_CAPABILITY + Read Issuing Capability + 16 + + + COMBINED_ISSUING_CAPABILITY + Combined Issuing Capability + 16 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element bpf_pcie_slv + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/bpf/bpf_pmci_slv.ip b/src/pd_qsys/fabric/ip/bpf/bpf_pmci_slv.ip new file mode 100644 index 0000000..172d338 --- /dev/null +++ b/src/pd_qsys/fabric/ip/bpf/bpf_pmci_slv.ip @@ -0,0 +1,1800 @@ + + + + Altera Corporation + bpf_pmci_slv + bpf_pmci_slv + 1.0 + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + altera_axi4lite_slave + + + + + + + + awaddr + + + s_awaddr + + + + + awprot + + + s_awprot + + + + + awvalid + + + s_awvalid + + + + + awready + + + s_awready + + + + + wdata + + + s_wdata + + + + + wstrb + + + s_wstrb + + + + + wvalid + + + s_wvalid + + + + + wready + + + s_wready + + + + + bresp + + + s_bresp + + + + + bvalid + + + s_bvalid + + + + + bready + + + s_bready + + + + + araddr + + + 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+ 1 + + + combinedIssuingCapability + Combined issuing capability + 1 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + noRepeatedIdsBetweenSubordinates + noRepeatedIdsBetweenSubordinates + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + axi4lite_shim + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awaddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wstrb + + in + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + 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<interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/bpf/bpf_reset_bridge.ip b/src/pd_qsys/fabric/ip/bpf/bpf_reset_bridge.ip new file mode 100644 index 0000000..c9a6fd7 --- /dev/null +++ b/src/pd_qsys/fabric/ip/bpf/bpf_reset_bridge.ip @@ -0,0 +1,418 @@ + + + + Intel Corporation + bpf_reset_bridge + bpf_reset_bridge + 19.2.0 + + + clk + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + in_reset + + + + + + + + reset_n + + + in_reset_n + + + + + + + + + associatedClock + Associated clock + clk + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + out_reset + + + + + + + + reset_n + + + out_reset_n + + + + + + + + + associatedClock + Associated clock + clk + + + associatedDirectReset + Associated direct reset + in_reset + + + associatedResetSinks + Associated reset sinks + in_reset + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_reset_bridge + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + in_reset_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + out_reset_n + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + bpf_reset_bridge + altera_reset_bridge + 19.2.0 + + + + + ACTIVE_LOW_RESET + Active low reset + 1 + + + SYNCHRONOUS_EDGES + Synchronous edges + deassert + + + NUM_RESET_OUTPUTS + Number of reset outputs + 1 + + + USE_RESET_REQUEST + Use reset request signal + 0 + + + SYNC_RESET + Use synchronous resets + 0 + + + AUTO_CLK_CLOCK_RATE + Auto CLOCK_RATE + -1 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element bpf_reset_bridge + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_reset_n</name> + <role>reset_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>-1</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/bpf/bpf_rsv_5_slv.ip b/src/pd_qsys/fabric/ip/bpf/bpf_rsv_5_slv.ip new file mode 100644 index 0000000..7a9548f --- /dev/null +++ b/src/pd_qsys/fabric/ip/bpf/bpf_rsv_5_slv.ip @@ -0,0 +1,1800 @@ + + + + Altera Corporation + bpf_rsv_5_slv + bpf_rsv_5_slv + 1.0 + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + altera_axi4lite_slave + + + + + + + + awaddr + + + s_awaddr + + + + + awprot + + + s_awprot + + + + + awvalid + + + s_awvalid + + + + + awready + + + s_awready + + + + + wdata + + + s_wdata + + + + + wstrb + + + s_wstrb + + + + + wvalid + + + s_wvalid + + + + + wready + + + s_wready + + + + + bresp + + + s_bresp + + + + + bvalid + + + s_bvalid + + + + + bready + + + s_bready + + + + + araddr + + + s_araddr + + + + + arprot + + + s_arprot + + + + + arvalid + + + s_arvalid + + + + + arready + + + s_arready + + + + + rdata + + + s_rdata + + + + + rresp + + + s_rresp + + + + + rvalid + + + s_rvalid + + + + + rready + + + s_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readAcceptanceCapability + Read acceptance capability + 1 + + + writeAcceptanceCapability + Write acceptance capability + 1 + + + combinedAcceptanceCapability + Combined acceptance capability + 1 + + + readDataReorderingDepth + Read data reordering depth + 1 + + + bridgesToMaster + bridgesToMaster + + + + + + altera_axi4lite_master + + + + + + + + awaddr + + + m_awaddr + + + + + awprot + + + m_awprot + + + + + awvalid + + + m_awvalid + + + + + awready + + + m_awready + + + + + wdata + + + m_wdata + + + + + wstrb + + + m_wstrb + + + + + wvalid + + + m_wvalid + + + + + wready + + + m_wready + + + + + bresp + + + m_bresp + + + + + bvalid + + + m_bvalid + + + + + bready + + + m_bready + + + + + araddr + + + m_araddr + + + + + arprot + + + m_arprot + + + + + arvalid + + + m_arvalid + + + + + arready + + + m_arready + + + + + rdata + + + m_rdata + + + + + rresp + + + m_rresp + + + + + rvalid + + + m_rvalid + + + + + rready + + + m_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readIssuingCapability + Read issuing capability + 1 + + + writeIssuingCapability + Write issuing capability + 1 + + + combinedIssuingCapability + Combined issuing capability + 1 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + noRepeatedIdsBetweenSubordinates + noRepeatedIdsBetweenSubordinates + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + axi4lite_shim + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awaddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wstrb + + in + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_bvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_araddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_arready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_rdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_rresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_rvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_rready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awaddr + + out + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awvalid + + out + + + STD_LOGIC + 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<terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + 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<terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/fabric/ip/bpf/bpf_rsv_7_slv.ip b/src/pd_qsys/fabric/ip/bpf/bpf_rsv_7_slv.ip new file mode 100644 index 0000000..5d616b8 --- /dev/null +++ b/src/pd_qsys/fabric/ip/bpf/bpf_rsv_7_slv.ip @@ -0,0 +1,1800 @@ + + + + Altera Corporation + bpf_rsv_7_slv + bpf_rsv_7_slv + 1.0 + + + clock + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + rst_n + + + + + + + + + associatedClock + Associated clock + clock + + + synchronousEdges + Synchronous edges + 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+ 1 + + + readAcceptanceCapability + Read acceptance capability + 1 + + + writeAcceptanceCapability + Write acceptance capability + 1 + + + combinedAcceptanceCapability + Combined acceptance capability + 1 + + + readDataReorderingDepth + Read data reordering depth + 1 + + + bridgesToMaster + bridgesToMaster + + + + + + altera_axi4lite_master + + + + + + + + awaddr + + + m_awaddr + + + + + awprot + + + m_awprot + + + + + awvalid + + + m_awvalid + + + + + awready + + + m_awready + + + + + wdata + + + m_wdata + + + + + wstrb + + + m_wstrb + + + + + wvalid + + + m_wvalid + + + + + wready + + + m_wready + + + + + bresp + + + m_bresp + + + + + bvalid + + + m_bvalid + + + + + bready + + + m_bready + + + + + araddr + + + m_araddr + + + + + arprot + + + m_arprot + + + + + arvalid + + + m_arvalid + + + + + arready + + + m_arready + + + + + rdata + + + m_rdata + + + + + rresp + + + m_rresp + + + + + rvalid + + + m_rvalid + + + + + rready + + + m_rready + + + + + + + + + associatedClock + Associated clock + clock + + + associatedReset + Associated reset + reset + + + trustzoneAware + trustzoneAware + true + + + maximumOutstandingReads + maximumOutstandingReads + 1 + + + maximumOutstandingWrites + maximumOutstandingWrites + 1 + + + maximumOutstandingTransactions + maximumOutstandingTransactions + 1 + + + readIssuingCapability + Read issuing capability + 1 + + + writeIssuingCapability + Write issuing capability + 1 + + + combinedIssuingCapability + Combined issuing capability + 1 + + + enableConcurrentSubordinateAccess + enableConcurrentSubordinateAccess + 0 + + + noRepeatedIdsBetweenSubordinates + noRepeatedIdsBetweenSubordinates + 0 + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + axi4lite_shim + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + rst_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awaddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_awvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_awready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wstrb + + in + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_wvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_wready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_bvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_bready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_araddr + + in + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arprot + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_arvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_arready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_rdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_rresp + + out + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + s_rvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + s_rready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awaddr + + out + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_awvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_awready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_wdata + + out + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_wstrb + + out + + + 0 + 7 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_wvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_wready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_bvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_bready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_araddr + + out + + + 0 + 15 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arprot + + out + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_arvalid + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_arready + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rdata + + in + + + 0 + 63 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rresp + + in + + + 0 + 1 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + m_rvalid + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + m_rready + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Altera Corporation + bpf_rsv_7_slv + axi4lite_shim + 1.0 + + + + + AW + AW + 16 + + + DW + DW + 64 + + + WRITE_ISSUING_CAPABILITY + Write Issuing Capability + 16 + + + READ_ISSUING_CAPABILITY + Read Issuing Capability + 16 + + + COMBINED_ISSUING_CAPABILITY + Combined Issuing Capability + 16 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element bpf_rsv_7_slv + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clock</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>rst_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_slave</name> + <type>axi4lite</type> + <isStart>false</isStart> + <ports> + <port> + <name>s_awaddr</name> + <role>awaddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awprot</name> + <role>awprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awvalid</name> + <role>awvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_awready</name> + <role>awready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wdata</name> + <role>wdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wstrb</name> + <role>wstrb</role> + <direction>Input</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wvalid</name> + <role>wvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_wready</name> + <role>wready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bresp</name> + <role>bresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bvalid</name> + <role>bvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_bready</name> + <role>bready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_araddr</name> + <role>araddr</role> + <direction>Input</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arprot</name> + <role>arprot</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arvalid</name> + <role>arvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_arready</name> + <role>arready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rdata</name> + <role>rdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rresp</name> + <role>rresp</role> + <direction>Output</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rvalid</name> + <role>rvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>s_rready</name> + <role>rready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedAcceptanceCapability</key> + <value>1</value> + </entry> + <entry> + <key>readDataReorderingDepth</key> + <value>1</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>altera_axi4lite_master</name> + <type>axi4lite</type> + <isStart>true</isStart> + <ports> + <port> + <name>m_awaddr</name> + <role>awaddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awprot</name> + <role>awprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awvalid</name> + <role>awvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_awready</name> + <role>awready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wdata</name> + <role>wdata</role> + <direction>Output</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wstrb</name> + <role>wstrb</role> + <direction>Output</direction> + <width>8</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wvalid</name> + <role>wvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_wready</name> + <role>wready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bresp</name> + <role>bresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bvalid</name> + <role>bvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_bready</name> + <role>bready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_araddr</name> + <role>araddr</role> + <direction>Output</direction> + <width>16</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arprot</name> + <role>arprot</role> + <direction>Output</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arvalid</name> + <role>arvalid</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_arready</name> + <role>arready</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rdata</name> + <role>rdata</role> + <direction>Input</direction> + <width>64</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rresp</name> + <role>rresp</role> + <direction>Input</direction> + <width>2</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rvalid</name> + <role>rvalid</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>m_rready</name> + <role>rready</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clock</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>trustzoneAware</key> + <value>true</value> + </entry> + <entry> + <key>maximumOutstandingReads</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingWrites</key> + <value>1</value> + </entry> + <entry> + <key>maximumOutstandingTransactions</key> + <value>1</value> + </entry> + <entry> + <key>readIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>writeIssuingCapability</key> + <value>1</value> + </entry> + <entry> + <key>combinedIssuingCapability</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/readme.txt b/src/pd_qsys/readme.txt new file mode 100644 index 0000000..1638698 --- /dev/null +++ b/src/pd_qsys/readme.txt @@ -0,0 +1,48 @@ +Folder Structure: + +-- fabric // Contains AFU Peripheral Fabric (APF) & Board Peripheral Fabric (BPF) Qsys interconnect fabric +| |-- apf // Quartus generated APF interconnect fabric output products (Dont Touch) +| |-- apf.qsys // Quartus generated APF interconnect fabric (Dont Touch) +| |-- apf.tcl // APF Subsystem generation script, generated as part of the flow (Dont Touch) +| |-- axi4lite_shim_hw.tcl // AXI Lite bridhe HW TCL Script used to export AXI Lite interface in QSYS +| |-- bpf // Quartus generated BPF interconnect fabric output products (Dont Touch) +| |-- bpf.qsys // Quartus generated BPF interconnect fabric (Dont Touch) +| |-- bpf.tcl // BPF Subsystem generation script, generated as part of the flow (Dont Touch) +| |-- fpga_bars.pkg // APF & BPF BAR parameters package, This is a script generated file (Dont Touch) +| |-- gen_fabrics.sh // QSYS Generation bash script. See the usage below. +| |-- hdk.qpf // Quartus project file +| |-- hdk.qsf // Quartus project setting file +| |-- iofs_dfl.txt // APF & QPF Configuration setting. This file is input to QSYS bash script. Modify this file if user need a change in interconnect fabric +| |-- ip // Quartus Generated IPs +| `-- qdb // Not used +`-- spi_bridge // Avalon MM slave to SPI master bridge to enable the communication with the MAX10 BMC + |-- ip // Qsys generated IPs & output products + |-- spi_bridge // Qsys generated output products + `-- spi_bridge.qsys // AVMM slave to SPI Bridge. This is manually generated interconnect fabric. + + +APF/BPF Qsys Interconect fabric generation using Bash script: + + 1. Initial Setup + + cd to ./fabric/ + Update iofs_dfl.txt with your required setting + Header fields in iofs_dfl.txt are interpreted as below . + * REGISTER_NAME : DFH register name + * FABRIC : {BPF-SLV, BPF-MST, BPF-BID, APF-SLV, APF-MST, APF-BID} + * BPF-SLV : Device feature is a BPF slave + * BPF-MST : Device feature is a BPF master + * BPF-BID : Device feature is a BPF master and slave + * APF-SLV : Device feature is a APF slave + * APF-MST : Device feature is a APF master + * APF-BID : Device feature is a APF master and slave + * BASE ADDRESS : Device feature base address + * ADDRESS WIDTH : Device feature address width + Currently only 1 master and 1 slave interface is supported per device feature + + 2. Run gen_fabrics.sh + + Script will use iofs_sfl.txt as the input, generating the TCL files for the APF & BPF fabric, and finally generate the Quartus output for both. + If no errors are encountered, the script will complete with a message "Finished: Platform Designer system generation" + Following files will be generated as part of APF Fabric: apf.qsys,apf,apf.tcl,fpga_bars.pkg + Following files will be generated as part of BPF Fabric: bpf.qsys,bpf,bpf.tcl,fpga_bars.pkg diff --git a/src/pd_qsys/spi_bridge/ip/spi_bridge/spi_bridge_clock_in.ip b/src/pd_qsys/spi_bridge/ip/spi_bridge/spi_bridge_clock_in.ip new file mode 100644 index 0000000..5348abc --- /dev/null +++ b/src/pd_qsys/spi_bridge/ip/spi_bridge/spi_bridge_clock_in.ip @@ -0,0 +1,344 @@ + + + + Intel Corporation + spi_bridge_clock_in + clock_in + 19.2.0 + + + in_clk + + + + + + + + clk + + + in_clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + out_clk + + + + + + + + clk + + + out_clk + + + + + + + + + associatedDirectClock + Associated direct clock + in_clk + + + clockRate + Clock rate + 125000000 + + + clockRateKnown + Clock rate known + true + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_clock_bridge + + QUARTUS_SYNTH + + + + + + in_clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + out_clk + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + spi_bridge_clock_in + altera_clock_bridge + 19.2.0 + + + + + DERIVED_CLOCK_RATE + Derived clock rate + 0 + + + EXPLICIT_CLOCK_RATE + Explicit clock rate + 125000000 + + + NUM_CLOCK_OUTPUTS + Number of Clock Outputs + 1 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element clock_in + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>in_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>in_clk</value> + </entry> + <entry> + <key>clockRate</key> + <value>125000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>in_clk</key> + <value> + <connectionPointName>in_clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>out_clk</key> + <value> + <connectionPointName>out_clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>125000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/spi_bridge/ip/spi_bridge/spi_bridge_reset_in.ip b/src/pd_qsys/spi_bridge/ip/spi_bridge/spi_bridge_reset_in.ip new file mode 100644 index 0000000..64e57ee --- /dev/null +++ b/src/pd_qsys/spi_bridge/ip/spi_bridge/spi_bridge_reset_in.ip @@ -0,0 +1,415 @@ + + + + Intel Corporation + spi_bridge_reset_in + reset_in + 19.2.0 + + + clk + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + in_reset + + + + + + + + reset + + + in_reset + + + + + + + + + associatedClock + Associated clock + clk + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + out_reset + + + + + + + + reset + + + out_reset + + + + + + + + + associatedClock + Associated clock + clk + + + associatedDirectReset + Associated direct reset + in_reset + + + associatedResetSinks + Associated reset sinks + in_reset + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_reset_bridge + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + in_reset + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + out_reset + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + spi_bridge_reset_in + altera_reset_bridge + 19.2.0 + + + + + ACTIVE_LOW_RESET + Active low reset + 0 + + + SYNCHRONOUS_EDGES + Synchronous edges + deassert + + + NUM_RESET_OUTPUTS + Number of reset outputs + 1 + + + USE_RESET_REQUEST + Use reset request signal + 0 + + + SYNC_RESET + Use synchronous resets + 0 + + + AUTO_CLK_CLOCK_RATE + Auto CLOCK_RATE + 125000000 + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element reset_in + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_reset</name> + <role>reset</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>125000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/spi_bridge/ip/spi_bridge/spi_bridge_spi_0.ip b/src/pd_qsys/spi_bridge/ip/spi_bridge/spi_bridge_spi_0.ip new file mode 100644 index 0000000..6cfab4e --- /dev/null +++ b/src/pd_qsys/spi_bridge/ip/spi_bridge/spi_bridge_spi_0.ip @@ -0,0 +1,1538 @@ + + + + Intel Corporation + spi_bridge_spi_0 + spi_0 + 19.2.2 + + + clk + + + + + + + + clk + + + clk + + + + + + + + + clockRate + Clock rate + 0 + + + externallyDriven + Externally driven + false + + + ptfSchematicName + PTF schematic name + + + + + + reset + + + + + + + + reset_n + + + reset_n + + + + + + + + + associatedClock + Associated clock + clk + + + synchronousEdges + Synchronous edges + DEASSERT + + + + + spi_control_port + + + + + + + + writedata + + + data_from_cpu + + + + + readdata + + + data_to_cpu + + + + + address + + + mem_addr + + + + + read_n + + + read_n + + + + + chipselect + + + spi_select + + + + + write_n + + + write_n + + + + + + + + + addressAlignment + Agent addressing + NATIVE + + + addressGroup + Address group + 0 + + + addressSpan + Address span + 8 + + + addressUnits + Address units + WORDS + + + alwaysBurstMaxBurst + Always burst maximum burst + false + + + associatedClock + Associated clock + clk + + + associatedReset + Associated reset + reset + + + bitsPerSymbol + Bits per symbol + 8 + + + bridgedAddressOffset + Bridged Address Offset + 0 + + + bridgesToMaster + Bridges to host + + + + burstOnBurstBoundariesOnly + Burst on burst boundaries only + false + + + burstcountUnits + Burstcount units + WORDS + + + constantBurstBehavior + Constant burst behavior + false + + + explicitAddressSpan + Explicit address span + 0 + + + holdTime + Hold + 0 + + + interleaveBursts + Interleave bursts + false + + + isBigEndian + Big endian + false + + + isFlash + Flash memory + false + + + isMemoryDevice + Memory device + false + + + isNonVolatileStorage + Non-volatile storage + false + + + linewrapBursts + Linewrap bursts + false + + + maximumPendingReadTransactions + Maximum pending read transactions + 0 + + + maximumPendingWriteTransactions + Maximum pending write transactions + 0 + + + minimumReadLatency + minimumReadLatency + 1 + + + minimumResponseLatency + Minimum response latency + 1 + + + minimumUninterruptedRunLength + Minimum uninterrupted run length + 1 + + + prSafe + Partial Reconfiguration Safe + false + + + printableDevice + Can receive stdout/stderr + false + + + readLatency + Read latency + 0 + + + readWaitStates + Read wait states + 1 + + + readWaitTime + Read wait + 1 + + + registerIncomingSignals + Register incoming signals + false + + + registerOutgoingSignals + Register outgoing signals + false + + + setupTime + Setup + 0 + + + timingUnits + Timing units + Cycles + + + transparentBridge + Transparent bridge + false + + + waitrequestAllowance + Waitrequest allowance + 0 + + + wellBehavedWaitrequest + Well-behaved waitrequest + false + + + writeLatency + Write latency + 0 + + + writeWaitStates + Write wait states + 1 + + + writeWaitTime + Write wait + 1 + + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + + + + + irq + + + + + + + + irq + + + irq + + + + + + + + + associatedAddressablePoint + Associated addressable interface + spi_bridge_spi_0.spi_control_port + + + associatedClock + Associated clock + clk + + + associatedReset + Associated reset + reset + + + bridgedReceiverOffset + Bridged receiver offset + 0 + + + bridgesToReceiver + Bridges to receiver + + + + irqScheme + Interrupt scheme + NONE + + + + + external + + + + + + + + MISO + + + MISO + + + + + MOSI + + + MOSI + + + + + SCLK + + + SCLK + + + + + SS_n + + + SS_n + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_avalon_spi + + QUARTUS_SYNTH + + + + + + clk + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + reset_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + data_from_cpu + + in + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + data_to_cpu + + out + + + 0 + 31 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + mem_addr + + in + + + 0 + 2 + + + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + read_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + spi_select + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + write_n + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + irq + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + MISO + + in + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + MOSI + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + SCLK + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + SS_n + + out + + + STD_LOGIC + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + spi_bridge_spi_0 + altera_avalon_spi + 19.2.2 + + + + + clockPhase + Clock phase + 1 + + + clockPolarity + Clock polarity + 0 + + + dataWidth + Width + 32 + + + disableAvalonFlowControl + Disable flow control on Avalon slave interface + false + + + insertDelayBetweenSlaveSelectAndSClk + Specify delay + false + + + insertSync + Insert Synchronizers + false + + + lsbOrderedFirst + Shift direction + false + + + masterSPI + Type + true + + + numberOfSlaves + Number of select (SS_n) signals (one for each slave) + 1 + + + syncRegDepth + Depth + 2 + + + targetClockRate + SPI clock (SCLK) rate + 12500000 + + + targetSlaveSelectToSClkDelay + Target delay + 0.0 + + + avalonSpec + avalonSpec + 2.0 + + + inputClockRate + inputClockRate + 125000000 + + + + + + + embeddedsw.CMacro.CLOCKMULT + 1 + + + embeddedsw.CMacro.CLOCKPHASE + 1 + + + embeddedsw.CMacro.CLOCKPOLARITY + 0 + + + embeddedsw.CMacro.CLOCKUNITS + "Hz" + + + embeddedsw.CMacro.DATABITS + 32 + + + embeddedsw.CMacro.DATAWIDTH + 32 + + + embeddedsw.CMacro.DELAYMULT + "1.0E-9" + + + embeddedsw.CMacro.DELAYUNITS + "ns" + + + embeddedsw.CMacro.EXTRADELAY + 0 + + + embeddedsw.CMacro.INSERT_SYNC + 0 + + + embeddedsw.CMacro.ISMASTER + 1 + + + embeddedsw.CMacro.LSBFIRST + 0 + + + embeddedsw.CMacro.NUMSLAVES + 1 + + + embeddedsw.CMacro.PREFIX + "spi_" + + + embeddedsw.CMacro.SYNC_REG_DEPTH + 2 + + + embeddedsw.CMacro.TARGETCLOCK + 12500000u + + + embeddedsw.CMacro.TARGETSSDELAY + "0.0" + + + embeddedsw.dts.compatible + altr,spi-1.0 + + + embeddedsw.dts.group + spi + + + embeddedsw.dts.name + spi + + + embeddedsw.dts.vendor + altr + + + + + + + board + Board + default + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element spi_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + <boundaryDefinition> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>spi_control_port</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>data_from_cpu</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>data_to_cpu</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>mem_addr</name> + <role>address</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + </port> + <port> + <name>read_n</name> + <role>read_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>spi_select</name> + <role>chipselect</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>write_n</name> + <role>write_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>NATIVE</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + <cmsisInfo> + <cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt; +&lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"&gt; + &lt;peripherals&gt; + &lt;peripheral&gt; + &lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt; + &lt;name&gt;altera_avalon_spi&lt;/name&gt; + &lt;registers&gt; + &lt;register&gt; + &lt;access&gt;read-only&lt;/access&gt; + &lt;addressOffset&gt;0x0&lt;/addressOffset&gt; + &lt;displayName&gt;rxdata&lt;/displayName&gt; + &lt;name&gt;rxdata&lt;/name&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;resetValue&gt;0x00000000&lt;/resetValue&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;access&gt;write-only&lt;/access&gt; + &lt;addressOffset&gt;0x1&lt;/addressOffset&gt; + &lt;displayName&gt;txdata&lt;/displayName&gt; + &lt;name&gt;txdata&lt;/name&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;resetValue&gt;0x00000000&lt;/resetValue&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;addressOffset&gt;0x2&lt;/addressOffset&gt; + &lt;displayName&gt;status&lt;/displayName&gt; + &lt;name&gt;status&lt;/name&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;resetValue&gt;0x00000000&lt;/resetValue&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;fields&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[3:3]&lt;/bitRange&gt; + &lt;description&gt;The ROE bit is set to 1 if new data is received while the rxdata register is full (that is, while the&lt;/description&gt; + &lt;name&gt;ROE&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[4:4]&lt;/bitRange&gt; + &lt;description&gt;The TOE bit is set to 1 if new data is written to the txdata register while it is still full (that is,&lt;/description&gt; + &lt;name&gt;TOE&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[5:5]&lt;/bitRange&gt; + &lt;description&gt;In master mode, the TMT bit is set to 0 when a transaction is in progress and set to 1 when the&lt;/description&gt; + &lt;name&gt;TMT&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[6:6]&lt;/bitRange&gt; + &lt;description&gt;The TRDY bit is set to 1 when the txdata register is empty.&lt;/description&gt; + &lt;name&gt;TRDY&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[7:7]&lt;/bitRange&gt; + &lt;description&gt;The RRDY bit is set to 1 when the rxdata register is full.&lt;/description&gt; + &lt;name&gt;RRDY&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[8:8]&lt;/bitRange&gt; + &lt;description&gt;The E bit is the logical OR of the TOE and ROE bits. Tis is a convenience for the programmer to&lt;/description&gt; + &lt;name&gt;E&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[9:9]&lt;/bitRange&gt; + &lt;description&gt;The EOP bit is set when the End of Packet condition is detected. Te End of Packet condition is&lt;/description&gt; + &lt;name&gt;EOP&lt;/name&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;addressOffset&gt;0x3&lt;/addressOffset&gt; + &lt;displayName&gt;control&lt;/displayName&gt; + &lt;name&gt;control&lt;/name&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;resetValue&gt;0x00000000&lt;/resetValue&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;fields&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[3:3]&lt;/bitRange&gt; + &lt;description&gt;Setting IROE to 1 enables interrupts for receive-overrun errors.&lt;/description&gt; + &lt;name&gt;IROE&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[4:4]&lt;/bitRange&gt; + &lt;description&gt;Setting ITOE to 1 enables interrupts for transmitter-overrun errors&lt;/description&gt; + &lt;name&gt;ITOE&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[6:6]&lt;/bitRange&gt; + &lt;description&gt;Setting ITRDY to 1 enables interrupts for the transmitter ready condition.&lt;/description&gt; + &lt;name&gt;ITRDY&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[7:7]&lt;/bitRange&gt; + &lt;description&gt;Setting IRRDY to 1 enables interrupts for the receiver ready condition.&lt;/description&gt; + &lt;name&gt;IRRDY&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[8:8]&lt;/bitRange&gt; + &lt;description&gt;Setting IE to 1 enables interrupts for any error condition&lt;/description&gt; + &lt;name&gt;IE&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[9:9]&lt;/bitRange&gt; + &lt;description&gt;Setting IEOP to 1 enables interrupts for the End of Packet condition.&lt;/description&gt; + &lt;name&gt;IEOP&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[10:10]&lt;/bitRange&gt; + &lt;description&gt;Setting SSO to 1 forces the SPI core to drive its ss_n outputs, regardless of whether a serial&lt;/description&gt; + &lt;name&gt;SSO&lt;/name&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;addressOffset&gt;0x5&lt;/addressOffset&gt; + &lt;displayName&gt;slaveselect&lt;/displayName&gt; + &lt;name&gt;slaveselect&lt;/name&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;resetValue&gt;0x00000000&lt;/resetValue&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;addressOffset&gt;0x6&lt;/addressOffset&gt; + &lt;displayName&gt;eop_value&lt;/displayName&gt; + &lt;name&gt;eop_value&lt;/name&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;resetValue&gt;0x00000000&lt;/resetValue&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;/register&gt; + &lt;/registers&gt; + &lt;/peripheral&gt; + &lt;/peripherals&gt; +&lt;/device&gt;</cmsisSrcFileContents> + <addressGroup></addressGroup> + <cmsisVars/> + </cmsisInfo> + </interface> + <interface> + <name>irq</name> + <type>interrupt</type> + <isStart>false</isStart> + <ports> + <port> + <name>irq</name> + <role>irq</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedAddressablePoint</key> + <value>spi_bridge_spi_0.spi_control_port</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bridgedReceiverOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToReceiver</key> + </entry> + <entry> + <key>irqScheme</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>external</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>MISO</name> + <role>MISO</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>MOSI</name> + <role>MOSI</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>SCLK</name> + <role>SCLK</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + <port> + <name>SS_n</name> + <role>SS_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>125000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>spi_control_port</key> + <value> + <connectionPointName>spi_control_port</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='spi_control_port' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>5</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/src/pd_qsys/spi_bridge/spi_bridge.qsys b/src/pd_qsys/spi_bridge/spi_bridge.qsys new file mode 100644 index 0000000..a4b7c24 --- /dev/null +++ b/src/pd_qsys/spi_bridge/spi_bridge.qsys @@ -0,0 +1,1527 @@ + + + + Altera Corporation + spi_bridge + spi_bridge + 1.0 + + + + $${FILENAME} + $${FILENAME} + 1.0 + + + System + QsysPro + + + + + board + Board + default + + + bonusData + bonusData + bonusData +{ + element $system + { + } + element clock_in + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } + element reset_in + { + datum _sortIndex + { + value = "1"; + type = "int"; + } + } + element spi_0 + { + datum _sortIndex + { + value = "2"; + type = "int"; + } + } +} + + + + designId + designId + + + + device + Device + 1SX280HN2F43E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + fabricMode + fabricMode + QSYS + + + generateLegacySim + generateLegacySim + false + + + generationId + Generation Id + 0 + + + globalResetBus + Global reset + false + + + hdlLanguage + hdlLanguage + VERILOG + + + hideFromIPCatalog + Hide from IP Catalog + false + + + lockedInterfaceDefinition + lockedInterfaceDefinition + + + + sopcBorderPoints + Use SOPC Builder port naming + false + + + systemHash + systemHash + 0 + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + <entry> + <key>spi_0_spi_control_port</key> + <value> + <connectionPointName>spi_0_spi_control_port</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='spi_0.spi_control_port' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>5</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> +</systemInfosDefinition> + + + systemScripts + systemScripts + + + + testBenchDutName + Use Test Bench Naming Pattern + + + + timeStamp + timeStamp + 0 + + + useTestBenchNamingPattern + Use Test Bench Naming Pattern + false + + + + + + + + + Altera Corporation + clock_in + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>in_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>in_clk</value> + </entry> + <entry> + <key>clockRate</key> + <value>125000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_clock_bridge</className> + <version>18.1</version> + <displayName>Clock Bridge Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>DERIVED_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>in_clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>in_clk</key> + <value> + <connectionPointName>in_clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>0</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>out_clk</key> + <value> + <connectionPointName>out_clk</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>125000000</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + <boundaryDefinition> + <interfaces> + <interface> + <name>in_clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_clk</name> + <type>clock</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_clk</name> + <role>clk</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedDirectClock</key> + <value>in_clk</value> + </entry> + <entry> + <key>clockRate</key> + <value>125000000</value> + </entry> + <entry> + <key>clockRateKnown</key> + <value>true</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> +</boundaryDefinition> + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>spi_bridge_clock_in</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>spi_bridge_clock_in</fileSetName> + <fileSetFixedName>spi_bridge_clock_in</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>spi_bridge_clock_in</fileSetName> + <fileSetFixedName>spi_bridge_clock_in</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>spi_bridge_clock_in</fileSetName> + <fileSetFixedName>spi_bridge_clock_in</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/spi_bridge/spi_bridge_clock_in.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + reset_in + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>in_reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>in_reset</name> + <role>reset</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>out_reset</name> + <type>reset</type> + <isStart>true</isStart> + <ports> + <port> + <name>out_reset</name> + <role>reset</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedDirectReset</key> + <value>in_reset</value> + </entry> + <entry> + <key>associatedResetSinks</key> + <value>in_reset</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_reset_bridge</className> + <version>18.1</version> + <displayName>Reset Bridge Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue>-1</parameterDefaultValue> + <parameterName>AUTO_CLK_CLOCK_RATE</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>125000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>spi_bridge_reset_in</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>spi_bridge_reset_in</fileSetName> + <fileSetFixedName>spi_bridge_reset_in</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>spi_bridge_reset_in</fileSetName> + <fileSetFixedName>spi_bridge_reset_in</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>spi_bridge_reset_in</fileSetName> + <fileSetFixedName>spi_bridge_reset_in</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/spi_bridge/spi_bridge_reset_in.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap/> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + Altera Corporation + spi_0 + altera_generic_component + 1.0 + + + + + componentDefinition + Component definition + <componentDefinition> + <boundary> + <interfaces> + <interface> + <name>clk</name> + <type>clock</type> + <isStart>false</isStart> + <ports> + <port> + <name>clk</name> + <role>clk</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>clockRate</key> + <value>0</value> + </entry> + <entry> + <key>externallyDriven</key> + <value>false</value> + </entry> + <entry> + <key>ptfSchematicName</key> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>external</name> + <type>conduit</type> + <isStart>false</isStart> + <ports> + <port> + <name>MISO</name> + <role>MISO</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>MOSI</name> + <role>MOSI</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>SCLK</name> + <role>SCLK</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>SS_n</name> + <role>SS_n</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + </entry> + <entry> + <key>associatedReset</key> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>irq</name> + <type>interrupt</type> + <isStart>false</isStart> + <ports> + <port> + <name>irq</name> + <role>irq</role> + <direction>Output</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedAddressablePoint</key> + <value>spi_0.spi_control_port</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bridgedReceiverOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToReceiver</key> + </entry> + <entry> + <key>irqScheme</key> + <value>NONE</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>reset</name> + <type>reset</type> + <isStart>false</isStart> + <ports> + <port> + <name>reset_n</name> + <role>reset_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap/> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>synchronousEdges</key> + <value>DEASSERT</value> + </entry> + </parameterValueMap> + </parameters> + </interface> + <interface> + <name>spi_control_port</name> + <type>avalon</type> + <isStart>false</isStart> + <ports> + <port> + <name>data_from_cpu</name> + <role>writedata</role> + <direction>Input</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>data_to_cpu</name> + <role>readdata</role> + <direction>Output</direction> + <width>32</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>mem_addr</name> + <role>address</role> + <direction>Input</direction> + <width>3</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC_VECTOR</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>read_n</name> + <role>read_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>spi_select</name> + <role>chipselect</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + <port> + <name>write_n</name> + <role>write_n</role> + <direction>Input</direction> + <width>1</width> + <lowerBound>0</lowerBound> + <vhdlType>STD_LOGIC</vhdlType> + <terminationValue>0</terminationValue> + </port> + </ports> + <assignments> + <assignmentValueMap> + <entry> + <key>embeddedsw.configuration.isFlash</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isMemoryDevice</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isNonVolatileStorage</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.configuration.isPrintableDevice</key> + <value>0</value> + </entry> + </assignmentValueMap> + </assignments> + <parameters> + <parameterValueMap> + <entry> + <key>addressAlignment</key> + <value>NATIVE</value> + </entry> + <entry> + <key>addressGroup</key> + <value>0</value> + </entry> + <entry> + <key>addressSpan</key> + <value>8</value> + </entry> + <entry> + <key>addressUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>alwaysBurstMaxBurst</key> + <value>false</value> + </entry> + <entry> + <key>associatedClock</key> + <value>clk</value> + </entry> + <entry> + <key>associatedReset</key> + <value>reset</value> + </entry> + <entry> + <key>bitsPerSymbol</key> + <value>8</value> + </entry> + <entry> + <key>bridgedAddressOffset</key> + <value>0</value> + </entry> + <entry> + <key>bridgesToMaster</key> + </entry> + <entry> + <key>burstOnBurstBoundariesOnly</key> + <value>false</value> + </entry> + <entry> + <key>burstcountUnits</key> + <value>WORDS</value> + </entry> + <entry> + <key>constantBurstBehavior</key> + <value>false</value> + </entry> + <entry> + <key>explicitAddressSpan</key> + <value>0</value> + </entry> + <entry> + <key>holdTime</key> + <value>0</value> + </entry> + <entry> + <key>interleaveBursts</key> + <value>false</value> + </entry> + <entry> + <key>isBigEndian</key> + <value>false</value> + </entry> + <entry> + <key>isFlash</key> + <value>false</value> + </entry> + <entry> + <key>isMemoryDevice</key> + <value>false</value> + </entry> + <entry> + <key>isNonVolatileStorage</key> + <value>false</value> + </entry> + <entry> + <key>linewrapBursts</key> + <value>false</value> + </entry> + <entry> + <key>maximumPendingReadTransactions</key> + <value>0</value> + </entry> + <entry> + <key>maximumPendingWriteTransactions</key> + <value>0</value> + </entry> + <entry> + <key>minimumReadLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumResponseLatency</key> + <value>1</value> + </entry> + <entry> + <key>minimumUninterruptedRunLength</key> + <value>1</value> + </entry> + <entry> + <key>prSafe</key> + <value>false</value> + </entry> + <entry> + <key>printableDevice</key> + <value>false</value> + </entry> + <entry> + <key>readLatency</key> + <value>0</value> + </entry> + <entry> + <key>readWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>readWaitTime</key> + <value>1</value> + </entry> + <entry> + <key>registerIncomingSignals</key> + <value>false</value> + </entry> + <entry> + <key>registerOutgoingSignals</key> + <value>false</value> + </entry> + <entry> + <key>setupTime</key> + <value>0</value> + </entry> + <entry> + <key>timingUnits</key> + <value>Cycles</value> + </entry> + <entry> + <key>transparentBridge</key> + <value>false</value> + </entry> + <entry> + <key>waitrequestAllowance</key> + <value>0</value> + </entry> + <entry> + <key>wellBehavedWaitrequest</key> + <value>false</value> + </entry> + <entry> + <key>writeLatency</key> + <value>0</value> + </entry> + <entry> + <key>writeWaitStates</key> + <value>1</value> + </entry> + <entry> + <key>writeWaitTime</key> + <value>1</value> + </entry> + </parameterValueMap> + </parameters> + <cmsisInfo> + <cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt; +&lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"&gt; + &lt;peripherals&gt; + &lt;peripheral&gt; + &lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt; + &lt;name&gt;altera_avalon_spi&lt;/name&gt; + &lt;registers&gt; + &lt;register&gt; + &lt;access&gt;read-only&lt;/access&gt; + &lt;addressOffset&gt;0x0&lt;/addressOffset&gt; + &lt;displayName&gt;rxdata&lt;/displayName&gt; + &lt;name&gt;rxdata&lt;/name&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;resetValue&gt;0x00000000&lt;/resetValue&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;access&gt;write-only&lt;/access&gt; + &lt;addressOffset&gt;0x1&lt;/addressOffset&gt; + &lt;displayName&gt;txdata&lt;/displayName&gt; + &lt;name&gt;txdata&lt;/name&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;resetValue&gt;0x00000000&lt;/resetValue&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;addressOffset&gt;0x2&lt;/addressOffset&gt; + &lt;displayName&gt;status&lt;/displayName&gt; + &lt;name&gt;status&lt;/name&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;resetValue&gt;0x00000000&lt;/resetValue&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;fields&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[3:3]&lt;/bitRange&gt; + &lt;description&gt;The ROE bit is set to 1 if new data is received while the rxdata register is full (that is, while the&lt;/description&gt; + &lt;name&gt;ROE&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[4:4]&lt;/bitRange&gt; + &lt;description&gt;The TOE bit is set to 1 if new data is written to the txdata register while it is still full (that is,&lt;/description&gt; + &lt;name&gt;TOE&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[5:5]&lt;/bitRange&gt; + &lt;description&gt;In master mode, the TMT bit is set to 0 when a transaction is in progress and set to 1 when the&lt;/description&gt; + &lt;name&gt;TMT&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[6:6]&lt;/bitRange&gt; + &lt;description&gt;The TRDY bit is set to 1 when the txdata register is empty.&lt;/description&gt; + &lt;name&gt;TRDY&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[7:7]&lt;/bitRange&gt; + &lt;description&gt;The RRDY bit is set to 1 when the rxdata register is full.&lt;/description&gt; + &lt;name&gt;RRDY&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[8:8]&lt;/bitRange&gt; + &lt;description&gt;The E bit is the logical OR of the TOE and ROE bits. Tis is a convenience for the programmer to&lt;/description&gt; + &lt;name&gt;E&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[9:9]&lt;/bitRange&gt; + &lt;description&gt;The EOP bit is set when the End of Packet condition is detected. Te End of Packet condition is&lt;/description&gt; + &lt;name&gt;EOP&lt;/name&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;addressOffset&gt;0x3&lt;/addressOffset&gt; + &lt;displayName&gt;control&lt;/displayName&gt; + &lt;name&gt;control&lt;/name&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;resetValue&gt;0x00000000&lt;/resetValue&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;fields&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[3:3]&lt;/bitRange&gt; + &lt;description&gt;Setting IROE to 1 enables interrupts for receive-overrun errors.&lt;/description&gt; + &lt;name&gt;IROE&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[4:4]&lt;/bitRange&gt; + &lt;description&gt;Setting ITOE to 1 enables interrupts for transmitter-overrun errors&lt;/description&gt; + &lt;name&gt;ITOE&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[6:6]&lt;/bitRange&gt; + &lt;description&gt;Setting ITRDY to 1 enables interrupts for the transmitter ready condition.&lt;/description&gt; + &lt;name&gt;ITRDY&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[7:7]&lt;/bitRange&gt; + &lt;description&gt;Setting IRRDY to 1 enables interrupts for the receiver ready condition.&lt;/description&gt; + &lt;name&gt;IRRDY&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[8:8]&lt;/bitRange&gt; + &lt;description&gt;Setting IE to 1 enables interrupts for any error condition&lt;/description&gt; + &lt;name&gt;IE&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[9:9]&lt;/bitRange&gt; + &lt;description&gt;Setting IEOP to 1 enables interrupts for the End of Packet condition.&lt;/description&gt; + &lt;name&gt;IEOP&lt;/name&gt; + &lt;/field&gt; + &lt;field&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;bitRange&gt;[10:10]&lt;/bitRange&gt; + &lt;description&gt;Setting SSO to 1 forces the SPI core to drive its ss_n outputs, regardless of whether a serial&lt;/description&gt; + &lt;name&gt;SSO&lt;/name&gt; + &lt;/field&gt; + &lt;/fields&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;addressOffset&gt;0x5&lt;/addressOffset&gt; + &lt;displayName&gt;slaveselect&lt;/displayName&gt; + &lt;name&gt;slaveselect&lt;/name&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;resetValue&gt;0x00000000&lt;/resetValue&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;/register&gt; + &lt;register&gt; + &lt;access&gt;read-write&lt;/access&gt; + &lt;addressOffset&gt;0x6&lt;/addressOffset&gt; + &lt;displayName&gt;eop_value&lt;/displayName&gt; + &lt;name&gt;eop_value&lt;/name&gt; + &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; + &lt;resetValue&gt;0x00000000&lt;/resetValue&gt; + &lt;size&gt;32&lt;/size&gt; + &lt;/register&gt; + &lt;/registers&gt; + &lt;/peripheral&gt; + &lt;/peripherals&gt; +&lt;/device&gt;</cmsisSrcFileContents> + <addressGroup></addressGroup> + <cmsisVars/> + </cmsisInfo> + </interface> + </interfaces> + </boundary> + <originalModuleInfo> + <className>altera_avalon_spi</className> + <version>18.1</version> + <displayName>SPI (3 Wire Serial) Intel FPGA IP</displayName> + </originalModuleInfo> + <systemInfoParameterDescriptors> + <descriptors> + <descriptor> + <parameterDefaultValue></parameterDefaultValue> + <parameterName>avalonSpec</parameterName> + <parameterType>java.lang.String</parameterType> + <systemInfotype>AVALON_SPEC</systemInfotype> + </descriptor> + <descriptor> + <parameterDefaultValue>0</parameterDefaultValue> + <parameterName>inputClockRate</parameterName> + <parameterType>java.lang.Long</parameterType> + <systemInfoArgs>clk</systemInfoArgs> + <systemInfotype>CLOCK_RATE</systemInfotype> + </descriptor> + </descriptors> + </systemInfoParameterDescriptors> + <systemInfos> + <connPtSystemInfos> + <entry> + <key>clk</key> + <value> + <connectionPointName>clk</connectionPointName> + <suppliedSystemInfos/> + <consumedSystemInfos> + <entry> + <key>CLOCK_RATE</key> + <value>125000000</value> + </entry> + </consumedSystemInfos> + </value> + </entry> + <entry> + <key>spi_control_port</key> + <value> + <connectionPointName>spi_control_port</connectionPointName> + <suppliedSystemInfos> + <entry> + <key>ADDRESS_MAP</key> + <value>&lt;address-map&gt;&lt;slave name='spi_control_port' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value> + </entry> + <entry> + <key>ADDRESS_WIDTH</key> + <value>5</value> + </entry> + <entry> + <key>MAX_SLAVE_DATA_WIDTH</key> + <value>32</value> + </entry> + </suppliedSystemInfos> + <consumedSystemInfos/> + </value> + </entry> + </connPtSystemInfos> + </systemInfos> +</componentDefinition> + + + defaultBoundary + Default boundary + + + + generationInfoDefinition + Generation Behavior + <generationInfoDefinition> + <hdlLibraryName>spi_bridge_spi_0</hdlLibraryName> + <fileSets> + <fileSet> + <fileSetName>spi_bridge_spi_0</fileSetName> + <fileSetFixedName>spi_bridge_spi_0</fileSetFixedName> + <fileSetKind>QUARTUS_SYNTH</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>spi_bridge_spi_0</fileSetName> + <fileSetFixedName>spi_bridge_spi_0</fileSetFixedName> + <fileSetKind>SIM_VERILOG</fileSetKind> + <fileSetFiles/> + </fileSet> + <fileSet> + <fileSetName>spi_bridge_spi_0</fileSetName> + <fileSetFixedName>spi_bridge_spi_0</fileSetFixedName> + <fileSetKind>SIM_VHDL</fileSetKind> + <fileSetFiles/> + </fileSet> + </fileSets> +</generationInfoDefinition> + + + hdlParameters + HDL Parameters + + + + hlsFile + HLS file + + + + logicalView + Logical view + ip/spi_bridge/spi_bridge_spi_0.ip + + + moduleAssignmentDefinition + Module Assignments + <assignmentDefinition> + <assignmentValueMap> + <entry> + <key>embeddedsw.CMacro.CLOCKMULT</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.CLOCKPHASE</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.CLOCKPOLARITY</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.CLOCKUNITS</key> + <value>"Hz"</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DATABITS</key> + <value>32</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DATAWIDTH</key> + <value>32</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DELAYMULT</key> + <value>"1.0E-9"</value> + </entry> + <entry> + <key>embeddedsw.CMacro.DELAYUNITS</key> + <value>"ns"</value> + </entry> + <entry> + <key>embeddedsw.CMacro.EXTRADELAY</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.INSERT_SYNC</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.ISMASTER</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.LSBFIRST</key> + <value>0</value> + </entry> + <entry> + <key>embeddedsw.CMacro.NUMSLAVES</key> + <value>1</value> + </entry> + <entry> + <key>embeddedsw.CMacro.PREFIX</key> + <value>"spi_"</value> + </entry> + <entry> + <key>embeddedsw.CMacro.SYNC_REG_DEPTH</key> + <value>2</value> + </entry> + <entry> + <key>embeddedsw.CMacro.TARGETCLOCK</key> + <value>12500000u</value> + </entry> + <entry> + <key>embeddedsw.CMacro.TARGETSSDELAY</key> + <value>"0.0"</value> + </entry> + <entry> + <key>embeddedsw.dts.compatible</key> + <value>altr,spi-1.0</value> + </entry> + <entry> + <key>embeddedsw.dts.group</key> + <value>spi</value> + </entry> + <entry> + <key>embeddedsw.dts.name</key> + <value>spi</value> + </entry> + <entry> + <key>embeddedsw.dts.vendor</key> + <value>altr</value> + </entry> + </assignmentValueMap> +</assignmentDefinition> + + + svInterfaceDefinition + System Verilog Interface definition + + + + + + + + + + + + + + + + + + + + + + + + + + Intel Corporation + addressMap + addressMap + 1.0 + + + + + + false + false + + \ No newline at end of file diff --git a/src/top/iofs_top.sv b/src/top/iofs_top.sv new file mode 100755 index 0000000..21ba248 --- /dev/null +++ b/src/top/iofs_top.sv @@ -0,0 +1,912 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// IOFS top wrapper + + `include "fpga_defines.vh" + import top_cfg_pkg::* ; + import ofs_fim_cfg_pkg::* ; + import ofs_fim_if_pkg::* ; + import ofs_fim_pcie_pkg::* ; +`ifdef INCLUDE_HSSI import ofs_fim_eth_if_pkg::* ;`endif + +//----------------------------------------------------------------------------- +// Module ports +//----------------------------------------------------------------------------- + +module iofs_top ( + input SYS_RefClk ,// System Reference Clock (100MHz) + input PCIE_RefClk ,// PCIe clock + input PCIE_Rst_n ,// PCIe reset + input [ofs_fim_pcie_pkg::PCIE_LANES-1:0] PCIE_Rx ,// PCIe RX interface + output [ofs_fim_pcie_pkg::PCIE_LANES-1:0] PCIE_Tx ,// PCIe TX interface + output SPI_sclk ,// SPI clock + output SPI_cs_l ,// SPI chip select (active-low) + output SPI_mosi ,// SPI data output + input SPI_miso ,// SPI data input + + ofs_fim_emif_mem_if.emif ddr4_mem [NUM_MEM_CH-1:0] // EMIF DDR4 x72 RDIMM (x8) + + `ifdef INCLUDE_HSSI , + output qsfp_3v0_port_en ,// QSFP port controller enable + input wire qsfp_3v0_port_int_n ,// QSFP port controller interrupt driven pre-fetch + input qsfp0_644_53125_clk ,// QSFP0 644.53125 Ethernet reference clock + input qsfp1_644_53125_clk ,// QSFP1 644.53125 Ethernet reference clock + output [3:0] qsfp0_tx_serial ,// QSFP0 TX serial data + input [3:0] qsfp0_rx_serial ,// QSFP0 RX serial data + output [3:0] qsfp1_tx_serial ,// QSFP1 TX serial data + input [3:0] qsfp1_rx_serial // QSFP1 RX serial data + `endif + ); + +//----------------------------------------------------------------------------- +// Internal signals +//----------------------------------------------------------------------------- + +// clock signals +logic clk_1x; +logic clk_div2; +logic clk_100M; + +// reset signals +logic pll_locked; +logic ninit_done; +logic npor; +logic pcie_reset_status; +logic rst_n_1x; +logic rst_n_div2; +logic rst_n_100M; +logic [3:0] pf0_flrst_n; +logic pwr_good_clk_n; + + +// PCIe sideband signals +t_sideband_from_pcie p2c_sideband; +t_sideband_to_pcie c2p_sideband; + +// AXI CSR interfaces +ofs_fim_axi_mmio_if #( + .AWID_WIDTH (ofs_fim_cfg_pkg::MMIO_TID_WIDTH), + .AWADDR_WIDTH (ofs_fim_cfg_pkg::MMIO_ADDR_WIDTH), + .WDATA_WIDTH (ofs_fim_cfg_pkg::MMIO_DATA_WIDTH), + .ARID_WIDTH (ofs_fim_cfg_pkg::MMIO_TID_WIDTH), + .ARADDR_WIDTH (ofs_fim_cfg_pkg::MMIO_ADDR_WIDTH), + .RDATA_WIDTH (ofs_fim_cfg_pkg::MMIO_DATA_WIDTH) +) +ext_csr_if [EXT_CSR_SLAVES-1:0](); + +// AXI4-lite interfaces +ofs_fim_axi_lite_if #(.AWADDR_WIDTH(19), .ARADDR_WIDTH(19)) bpf_apf_mst_if (); +ofs_fim_axi_lite_if #(.AWADDR_WIDTH(20), .ARADDR_WIDTH(20)) bpf_apf_slv_if (); +ofs_fim_axi_lite_if #(.AWADDR_WIDTH(20), .ARADDR_WIDTH(20)) bpf_fme_mst_if (); +ofs_fim_axi_lite_if #(.AWADDR_WIDTH(16), .ARADDR_WIDTH(16)) bpf_fme_slv_if (); +ofs_fim_axi_lite_if #(.AWADDR_WIDTH(16), .ARADDR_WIDTH(16)) bpf_pmci_slv_if (); +ofs_fim_axi_lite_if #(.AWADDR_WIDTH(16), .ARADDR_WIDTH(16)) bpf_pcie_slv_if (); +ofs_fim_axi_lite_if #(.AWADDR_WIDTH(16), .ARADDR_WIDTH(16)) bpf_emif_slv_if (); +ofs_fim_axi_lite_if #(.AWADDR_WIDTH(16), .ARADDR_WIDTH(16)) bpf_hssi_slv_if (); +ofs_fim_axi_lite_if #(.AWADDR_WIDTH(16), .ARADDR_WIDTH(16)) bpf_rsv_5_slv_if(); +ofs_fim_axi_lite_if #(.AWADDR_WIDTH(16), .ARADDR_WIDTH(16)) bpf_rsv_6_slv_if(); +ofs_fim_axi_lite_if #(.AWADDR_WIDTH(16), .ARADDR_WIDTH(16)) bpf_rsv_7_slv_if(); + +// AXIS IRQ interfaces +ofs_fim_irq_axis_if ext_fme_irq_if [EXT_FME_IRQ_IFS-1:0](); + +// AXIS PCIe channels (IOFS EA PCIe Subsystem) +ofs_fim_pcie_rxs_axis_if pcie_rx_st(); +ofs_fim_pcie_txs_axis_if pcie_tx_st(); + +// AXIS PCIe Subsystem Interface +pcie_ss_axis_if pcie_ss_axis_rx_if(.clk (clk_1x), .rst_n(rst_n_1x)); +pcie_ss_axis_if pcie_ss_axis_tx_if(.clk (clk_1x), .rst_n(rst_n_1x)); + +// AVST interface +ofs_fim_axi_lite_if m_afu_lite(); +ofs_fim_axi_lite_if s_afu_lite(); + +//AFU EMIF AVMM IF +ofs_fim_emif_avmm_if ddr4_avmm [NUM_MEM_CH] (); + + +//----------------------------------------------------------------------------- +// Resets - Split for timing +// synthesis preserve_syn_only - Prevents removal of registers during synthesis. +// This settings does not affect retiming or other optimizations in the Fitter. +//----------------------------------------------------------------------------- +logic rst_n_a_1x /* synthesis preserve_syn_only */ ; +logic rst_n_b_1x /* synthesis preserve_syn_only */ ; +logic rst_n_c_1x /* synthesis preserve_syn_only */ ; +logic rst_n_d_1x /* synthesis preserve_syn_only */ ; +logic rst_n_e_1x /* synthesis preserve_syn_only */ ; +logic rst_n_f_1x /* synthesis preserve_syn_only */ ; +logic rst_n_g_1x /* synthesis preserve_syn_only */ ; + +always @ (posedge clk_1x) +begin + rst_n_a_1x <= rst_n_1x; + rst_n_b_1x <= rst_n_1x; + rst_n_c_1x <= rst_n_1x; + rst_n_d_1x <= rst_n_1x; + rst_n_e_1x <= rst_n_1x; + rst_n_f_1x <= rst_n_1x; + rst_n_g_1x <= rst_n_1x; +end + +//----------------------------------------------------------------------------- +// Modules instances +//----------------------------------------------------------------------------- + + +//******************************* +//******************************* + + +wire [7:0] tx_serial; +wire [7:0] rx_serial; +wire ss_app_st_p0_rx_tvalid; +wire [63:0] ss_app_st_p0_rx_tdata; +wire [7:0] ss_app_st_p0_rx_tkeep; +wire ss_app_st_p0_rx_tlast; +wire [1:0] ss_app_st_p0_rx_tuser_client; +ofs_fim_hssi_ss_tx_axis_if hssi_ss_st_tx[MAX_NUM_ETH_CHANNELS-1:0](); +ofs_fim_hssi_ss_rx_axis_if hssi_ss_st_rx[MAX_NUM_ETH_CHANNELS-1:0](); +ofs_fim_hssi_fc_if hssi_fc[MAX_NUM_ETH_CHANNELS-1:0](); +logic [MAX_NUM_ETH_CHANNELS-1:0] hssi_clk_pll; + +`ifdef INCLUDE_HSSI +// Enable QSFP port controller +assign qsfp_3v0_port_en = 1'b1; +assign qsfp1_tx_serial = tx_serial[3:0]; +assign qsfp0_tx_serial = tx_serial[7:4]; +assign rx_serial = {qsfp0_rx_serial, qsfp1_rx_serial} ; + +eth_ac_wrapper eth_ac_wrapper ( + .clk_csr (clk_1x), + .rst_n_csr (rst_n_a_1x), + .clk_100M (clk_100M), + .rst_n_100M (rst_n_100M), + .csr_lite_if (bpf_hssi_slv_if), + .hssi_ss_st_tx (hssi_ss_st_tx), + .hssi_ss_st_rx (hssi_ss_st_rx), + + .hssi_fc (hssi_fc), + + .tx_serial (tx_serial), + .tx_serial_n (), + .rx_serial (rx_serial), + + .subsystem_cold_rst_n (rst_n_a_1x), + .i_clk_ref ({qsfp0_644_53125_clk,qsfp1_644_53125_clk}), + .o_hssi_clk_pll (hssi_clk_pll) +); + +`endif + +//******************************* +// System PLL +//******************************* + + sys_pll + sys_pll( + .rst (ninit_done ), + .refclk (SYS_RefClk ), + .locked (pll_locked ), + .outclk_0 (clk_1x ), + .outclk_1 (clk_div2 ), + .outclk_2 (clk_100M ) + ); + +//******************************* +// Reset controller +//******************************* + rst_ctrl + rst_ctrl( + .clk_1x (clk_1x ), + .clk_div2 (clk_div2 ), + .clk_100M (clk_100M ), + .pll_locked (pll_locked ), + .pcie_reset_n (PCIE_Rst_n ), + .pcie_reset_status (pcie_reset_status ), + + .ninit_done (ninit_done ), + .npor (npor ), + .pwr_good_clk_n (pwr_good_clk_n ), // power good reset synchronous to clk_1x + .rst_n_1x (rst_n_1x ), // system reset synchronous to clk_1x + .rst_n_div2 (rst_n_div2 ), // system reset synchronous to clk_div2 + .rst_n_100M (rst_n_100M ), // system reset synchronous to clk_100M + + .p2c_sideband (p2c_sideband ), + .c2p_sideband (c2p_sideband ), + .pf0_flrst_n (pf0_flrst_n ), + .pf1_flrst_n () + ); + +//******************************* +// PCIe Subsystem +//******************************* + + pcie_wrapper #(.PCIE_RANDOM_RDY (1) ) + pcie_wrapper ( + .fim_clk (clk_1x ), + .fim_rst_n (rst_n_b_1x ), + .ninit_done (ninit_done ), + .npor (npor ), + .reset_status (pcie_reset_status ), + .pin_pcie_ref_clk_p (PCIE_RefClk ), + .pin_pcie_in_perst_n(PCIE_Rst_n ), // connected to HIP + .pin_pcie_rx_p (PCIE_Rx ), + .pin_pcie_tx_p (PCIE_Tx ), + .axi_st_rx_if (pcie_ss_axis_rx_if ), + .axi_st_tx_if (pcie_ss_axis_tx_if ), + .csr_lite_if (bpf_pcie_slv_if ), + .irq_if (ext_fme_irq_if[PCIE_CSR_ID]), + .pcie_p2c_sideband (p2c_sideband ), + .pcie_c2p_sideband (c2p_sideband ) + ); + + +//******************************* +// PMCI Subsystem +//******************************* + + pmci_top + pmci_top( + .clk_1x (clk_1x ), + .clk_div2 (clk_div2 ), + + .rst_n_1x (rst_n_c_1x ), + .rst_n_div2 (rst_n_div2 ), + + .csr_lite_if (bpf_pmci_slv_if ), + .spi_miso (SPI_miso ), + .spi_mosi (SPI_mosi ), + .spi_s_clk (SPI_sclk ), + .spi_cs_l (SPI_cs_l ) + ); + +//******************************* +// FME +//******************************* + + fme_top + fme_top( + .clk (clk_1x ), + .rst_n (rst_n_d_1x ), + .pwr_good_n (ninit_done ), + + .axi_lite_m_if (bpf_fme_mst_if ), + .axi_lite_s_if (bpf_fme_slv_if ) + ); + +//******************************* +// AFU +//******************************* + + afu_top + afu_top( + .refclk (SYS_RefClk ), + .clk (clk_1x ), + .clk_div2 (clk_div2 ), + .clk_100 (clk_100M ), + + .rst_n (rst_n_e_1x ), + .pwr_good_clk_n (pwr_good_clk_n ), // power good reset synchronous to clk_1x + .rst_n_div2 (rst_n_div2 ), + .rst_n_100 (rst_n_100M ), + .func_rst_n (pf0_flrst_n ), + + .apf_bpf_slv_if (bpf_apf_mst_if ), + .apf_bpf_mst_if (bpf_apf_slv_if ), + + `ifdef INCLUDE_HE_HSSI + .hssi_ss_st_tx ( hssi_ss_st_tx ), + .hssi_ss_st_rx ( hssi_ss_st_rx ), + .hssi_fc ( hssi_fc ), + `ifdef INCLUDE_PTP + .hssi_ptp_tx_tod ( hssi_ptp_tx_tod ), + .hssi_ptp_rx_tod ( hssi_ptp_rx_tod ), + .hssi_ptp_tx_egrts ( hssi_ptp_tx_egrts ), + .hssi_ptp_rx_ingrts ( hssi_ptp_rx_ingrts ), + `endif + .i_hssi_clk_pll ( hssi_clk_pll ), + `endif + + .pcie_ss_axis_rx (pcie_ss_axis_rx_if ), + .pcie_ss_axis_tx (pcie_ss_axis_tx_if ), + .afu_mem_if (ddr4_avmm ) + ); + +//******************************* +// BPF +//******************************* + + bpf + bpf ( + .clk_clk (clk_1x ), + .rst_n_reset_n (rst_n_f_1x ), + + .bpf_apf_mst_awaddr (bpf_apf_mst_if.awaddr ), + .bpf_apf_mst_awprot (bpf_apf_mst_if.awprot ), + .bpf_apf_mst_awvalid (bpf_apf_mst_if.awvalid ), + .bpf_apf_mst_awready (bpf_apf_mst_if.awready ), + .bpf_apf_mst_wdata (bpf_apf_mst_if.wdata ), + .bpf_apf_mst_wstrb (bpf_apf_mst_if.wstrb ), + .bpf_apf_mst_wvalid (bpf_apf_mst_if.wvalid ), + .bpf_apf_mst_wready (bpf_apf_mst_if.wready ), + .bpf_apf_mst_bresp (bpf_apf_mst_if.bresp ), + .bpf_apf_mst_bvalid (bpf_apf_mst_if.bvalid ), + .bpf_apf_mst_bready (bpf_apf_mst_if.bready ), + .bpf_apf_mst_araddr (bpf_apf_mst_if.araddr ), + .bpf_apf_mst_arprot (bpf_apf_mst_if.arprot ), + .bpf_apf_mst_arvalid (bpf_apf_mst_if.arvalid ), + .bpf_apf_mst_arready (bpf_apf_mst_if.arready ), + .bpf_apf_mst_rdata (bpf_apf_mst_if.rdata ), + .bpf_apf_mst_rresp (bpf_apf_mst_if.rresp ), + .bpf_apf_mst_rvalid (bpf_apf_mst_if.rvalid ), + .bpf_apf_mst_rready (bpf_apf_mst_if.rready ), + + .bpf_fme_slv_awaddr (bpf_fme_slv_if.awaddr ), + .bpf_fme_slv_awprot (bpf_fme_slv_if.awprot ), + .bpf_fme_slv_awvalid (bpf_fme_slv_if.awvalid ), + .bpf_fme_slv_awready (bpf_fme_slv_if.awready ), + .bpf_fme_slv_wdata (bpf_fme_slv_if.wdata ), + .bpf_fme_slv_wstrb (bpf_fme_slv_if.wstrb ), + .bpf_fme_slv_wvalid (bpf_fme_slv_if.wvalid ), + .bpf_fme_slv_wready (bpf_fme_slv_if.wready ), + .bpf_fme_slv_bresp (bpf_fme_slv_if.bresp ), + .bpf_fme_slv_bvalid (bpf_fme_slv_if.bvalid ), + .bpf_fme_slv_bready (bpf_fme_slv_if.bready ), + .bpf_fme_slv_araddr (bpf_fme_slv_if.araddr ), + .bpf_fme_slv_arprot (bpf_fme_slv_if.arprot ), + .bpf_fme_slv_arvalid (bpf_fme_slv_if.arvalid ), + .bpf_fme_slv_arready (bpf_fme_slv_if.arready ), + .bpf_fme_slv_rdata (bpf_fme_slv_if.rdata ), + .bpf_fme_slv_rresp (bpf_fme_slv_if.rresp ), + .bpf_fme_slv_rvalid (bpf_fme_slv_if.rvalid ), + .bpf_fme_slv_rready (bpf_fme_slv_if.rready ), + + .bpf_pcie_slv_awaddr (bpf_pcie_slv_if.awaddr ), + .bpf_pcie_slv_awprot (bpf_pcie_slv_if.awprot ), + .bpf_pcie_slv_awvalid (bpf_pcie_slv_if.awvalid), + .bpf_pcie_slv_awready (bpf_pcie_slv_if.awready), + .bpf_pcie_slv_wdata (bpf_pcie_slv_if.wdata ), + .bpf_pcie_slv_wstrb (bpf_pcie_slv_if.wstrb ), + .bpf_pcie_slv_wvalid (bpf_pcie_slv_if.wvalid ), + .bpf_pcie_slv_wready (bpf_pcie_slv_if.wready ), + .bpf_pcie_slv_bresp (bpf_pcie_slv_if.bresp ), + .bpf_pcie_slv_bvalid (bpf_pcie_slv_if.bvalid ), + .bpf_pcie_slv_bready (bpf_pcie_slv_if.bready ), + .bpf_pcie_slv_araddr (bpf_pcie_slv_if.araddr ), + .bpf_pcie_slv_arprot (bpf_pcie_slv_if.arprot ), + .bpf_pcie_slv_arvalid (bpf_pcie_slv_if.arvalid), + .bpf_pcie_slv_arready (bpf_pcie_slv_if.arready), + .bpf_pcie_slv_rdata (bpf_pcie_slv_if.rdata ), + .bpf_pcie_slv_rresp (bpf_pcie_slv_if.rresp ), + .bpf_pcie_slv_rvalid (bpf_pcie_slv_if.rvalid ), + .bpf_pcie_slv_rready (bpf_pcie_slv_if.rready ), + + .bpf_pmci_slv_awaddr (bpf_pmci_slv_if.awaddr ), + .bpf_pmci_slv_awprot (bpf_pmci_slv_if.awprot ), + .bpf_pmci_slv_awvalid (bpf_pmci_slv_if.awvalid), + .bpf_pmci_slv_awready (bpf_pmci_slv_if.awready), + .bpf_pmci_slv_wdata (bpf_pmci_slv_if.wdata ), + .bpf_pmci_slv_wstrb (bpf_pmci_slv_if.wstrb ), + .bpf_pmci_slv_wvalid (bpf_pmci_slv_if.wvalid ), + .bpf_pmci_slv_wready (bpf_pmci_slv_if.wready ), + .bpf_pmci_slv_bresp (bpf_pmci_slv_if.bresp ), + .bpf_pmci_slv_bvalid (bpf_pmci_slv_if.bvalid ), + .bpf_pmci_slv_bready (bpf_pmci_slv_if.bready ), + .bpf_pmci_slv_araddr (bpf_pmci_slv_if.araddr ), + .bpf_pmci_slv_arprot (bpf_pmci_slv_if.arprot ), + .bpf_pmci_slv_arvalid (bpf_pmci_slv_if.arvalid), + .bpf_pmci_slv_arready (bpf_pmci_slv_if.arready), + .bpf_pmci_slv_rdata (bpf_pmci_slv_if.rdata ), + .bpf_pmci_slv_rresp (bpf_pmci_slv_if.rresp ), + .bpf_pmci_slv_rvalid (bpf_pmci_slv_if.rvalid ), + .bpf_pmci_slv_rready (bpf_pmci_slv_if.rready ), + + .bpf_emif_slv_awaddr (bpf_emif_slv_if.awaddr ), + .bpf_emif_slv_awprot (bpf_emif_slv_if.awprot ), + .bpf_emif_slv_awvalid (bpf_emif_slv_if.awvalid), + .bpf_emif_slv_awready (bpf_emif_slv_if.awready), + .bpf_emif_slv_wdata (bpf_emif_slv_if.wdata ), + .bpf_emif_slv_wstrb (bpf_emif_slv_if.wstrb ), + .bpf_emif_slv_wvalid (bpf_emif_slv_if.wvalid ), + .bpf_emif_slv_wready (bpf_emif_slv_if.wready ), + .bpf_emif_slv_bresp (bpf_emif_slv_if.bresp ), + .bpf_emif_slv_bvalid (bpf_emif_slv_if.bvalid ), + .bpf_emif_slv_bready (bpf_emif_slv_if.bready ), + .bpf_emif_slv_araddr (bpf_emif_slv_if.araddr ), + .bpf_emif_slv_arprot (bpf_emif_slv_if.arprot ), + .bpf_emif_slv_arvalid (bpf_emif_slv_if.arvalid), + .bpf_emif_slv_arready (bpf_emif_slv_if.arready), + .bpf_emif_slv_rdata (bpf_emif_slv_if.rdata ), + .bpf_emif_slv_rresp (bpf_emif_slv_if.rresp ), + .bpf_emif_slv_rvalid (bpf_emif_slv_if.rvalid ), + .bpf_emif_slv_rready (bpf_emif_slv_if.rready ), + + .bpf_hssi_slv_awaddr (bpf_hssi_slv_if.awaddr ), + .bpf_hssi_slv_awprot (bpf_hssi_slv_if.awprot ), + .bpf_hssi_slv_awvalid (bpf_hssi_slv_if.awvalid), + .bpf_hssi_slv_awready (bpf_hssi_slv_if.awready), + .bpf_hssi_slv_wdata (bpf_hssi_slv_if.wdata ), + .bpf_hssi_slv_wstrb (bpf_hssi_slv_if.wstrb ), + .bpf_hssi_slv_wvalid (bpf_hssi_slv_if.wvalid ), + .bpf_hssi_slv_wready (bpf_hssi_slv_if.wready ), + .bpf_hssi_slv_bresp (bpf_hssi_slv_if.bresp ), + .bpf_hssi_slv_bvalid (bpf_hssi_slv_if.bvalid ), + .bpf_hssi_slv_bready (bpf_hssi_slv_if.bready ), + .bpf_hssi_slv_araddr (bpf_hssi_slv_if.araddr ), + .bpf_hssi_slv_arprot (bpf_hssi_slv_if.arprot ), + .bpf_hssi_slv_arvalid (bpf_hssi_slv_if.arvalid), + .bpf_hssi_slv_arready (bpf_hssi_slv_if.arready), + .bpf_hssi_slv_rdata (bpf_hssi_slv_if.rdata ), + .bpf_hssi_slv_rresp (bpf_hssi_slv_if.rresp ), + .bpf_hssi_slv_rvalid (bpf_hssi_slv_if.rvalid ), + .bpf_hssi_slv_rready (bpf_hssi_slv_if.rready ), + + .bpf_rsv_5_slv_awaddr (bpf_rsv_5_slv_if.awaddr ), + .bpf_rsv_5_slv_awprot (bpf_rsv_5_slv_if.awprot ), + .bpf_rsv_5_slv_awvalid(bpf_rsv_5_slv_if.awvalid), + .bpf_rsv_5_slv_awready(bpf_rsv_5_slv_if.awready), + .bpf_rsv_5_slv_wdata (bpf_rsv_5_slv_if.wdata ), + .bpf_rsv_5_slv_wstrb (bpf_rsv_5_slv_if.wstrb ), + .bpf_rsv_5_slv_wvalid (bpf_rsv_5_slv_if.wvalid ), + .bpf_rsv_5_slv_wready (bpf_rsv_5_slv_if.wready ), + .bpf_rsv_5_slv_bresp (bpf_rsv_5_slv_if.bresp ), + .bpf_rsv_5_slv_bvalid (bpf_rsv_5_slv_if.bvalid ), + .bpf_rsv_5_slv_bready (bpf_rsv_5_slv_if.bready ), + .bpf_rsv_5_slv_araddr (bpf_rsv_5_slv_if.araddr ), + .bpf_rsv_5_slv_arprot (bpf_rsv_5_slv_if.arprot ), + .bpf_rsv_5_slv_arvalid(bpf_rsv_5_slv_if.arvalid), + .bpf_rsv_5_slv_arready(bpf_rsv_5_slv_if.arready), + .bpf_rsv_5_slv_rdata (bpf_rsv_5_slv_if.rdata ), + .bpf_rsv_5_slv_rresp (bpf_rsv_5_slv_if.rresp ), + .bpf_rsv_5_slv_rvalid (bpf_rsv_5_slv_if.rvalid ), + .bpf_rsv_5_slv_rready (bpf_rsv_5_slv_if.rready ), + + .bpf_rsv_6_slv_awaddr (bpf_rsv_6_slv_if.awaddr ), + .bpf_rsv_6_slv_awprot (bpf_rsv_6_slv_if.awprot ), + .bpf_rsv_6_slv_awvalid(bpf_rsv_6_slv_if.awvalid), + .bpf_rsv_6_slv_awready(bpf_rsv_6_slv_if.awready), + .bpf_rsv_6_slv_wdata (bpf_rsv_6_slv_if.wdata ), + .bpf_rsv_6_slv_wstrb (bpf_rsv_6_slv_if.wstrb ), + .bpf_rsv_6_slv_wvalid (bpf_rsv_6_slv_if.wvalid ), + .bpf_rsv_6_slv_wready (bpf_rsv_6_slv_if.wready ), + .bpf_rsv_6_slv_bresp (bpf_rsv_6_slv_if.bresp ), + .bpf_rsv_6_slv_bvalid (bpf_rsv_6_slv_if.bvalid ), + .bpf_rsv_6_slv_bready (bpf_rsv_6_slv_if.bready ), + .bpf_rsv_6_slv_araddr (bpf_rsv_6_slv_if.araddr ), + .bpf_rsv_6_slv_arprot (bpf_rsv_6_slv_if.arprot ), + .bpf_rsv_6_slv_arvalid(bpf_rsv_6_slv_if.arvalid), + .bpf_rsv_6_slv_arready(bpf_rsv_6_slv_if.arready), + .bpf_rsv_6_slv_rdata (bpf_rsv_6_slv_if.rdata ), + .bpf_rsv_6_slv_rresp (bpf_rsv_6_slv_if.rresp ), + .bpf_rsv_6_slv_rvalid (bpf_rsv_6_slv_if.rvalid ), + .bpf_rsv_6_slv_rready (bpf_rsv_6_slv_if.rready ), + + .bpf_rsv_7_slv_awaddr (bpf_rsv_7_slv_if.awaddr ), + .bpf_rsv_7_slv_awprot (bpf_rsv_7_slv_if.awprot ), + .bpf_rsv_7_slv_awvalid(bpf_rsv_7_slv_if.awvalid), + .bpf_rsv_7_slv_awready(bpf_rsv_7_slv_if.awready), + .bpf_rsv_7_slv_wdata (bpf_rsv_7_slv_if.wdata ), + .bpf_rsv_7_slv_wstrb (bpf_rsv_7_slv_if.wstrb ), + .bpf_rsv_7_slv_wvalid (bpf_rsv_7_slv_if.wvalid ), + .bpf_rsv_7_slv_wready (bpf_rsv_7_slv_if.wready ), + .bpf_rsv_7_slv_bresp (bpf_rsv_7_slv_if.bresp ), + .bpf_rsv_7_slv_bvalid (bpf_rsv_7_slv_if.bvalid ), + .bpf_rsv_7_slv_bready (bpf_rsv_7_slv_if.bready ), + .bpf_rsv_7_slv_araddr (bpf_rsv_7_slv_if.araddr ), + .bpf_rsv_7_slv_arprot (bpf_rsv_7_slv_if.arprot ), + .bpf_rsv_7_slv_arvalid(bpf_rsv_7_slv_if.arvalid), + .bpf_rsv_7_slv_arready(bpf_rsv_7_slv_if.arready), + .bpf_rsv_7_slv_rdata (bpf_rsv_7_slv_if.rdata ), + .bpf_rsv_7_slv_rresp (bpf_rsv_7_slv_if.rresp ), + .bpf_rsv_7_slv_rvalid (bpf_rsv_7_slv_if.rvalid ), + .bpf_rsv_7_slv_rready (bpf_rsv_7_slv_if.rready ), + + .bpf_apf_slv_awaddr (bpf_apf_slv_if.awaddr ), + .bpf_apf_slv_awprot (bpf_apf_slv_if.awprot ), + .bpf_apf_slv_awvalid (bpf_apf_slv_if.awvalid ), + .bpf_apf_slv_awready (bpf_apf_slv_if.awready ), + .bpf_apf_slv_wdata (bpf_apf_slv_if.wdata ), + .bpf_apf_slv_wstrb (bpf_apf_slv_if.wstrb ), + .bpf_apf_slv_wvalid (bpf_apf_slv_if.wvalid ), + .bpf_apf_slv_wready (bpf_apf_slv_if.wready ), + .bpf_apf_slv_bresp (bpf_apf_slv_if.bresp ), + .bpf_apf_slv_bvalid (bpf_apf_slv_if.bvalid ), + .bpf_apf_slv_bready (bpf_apf_slv_if.bready ), + .bpf_apf_slv_araddr (bpf_apf_slv_if.araddr ), + .bpf_apf_slv_arprot (bpf_apf_slv_if.arprot ), + .bpf_apf_slv_arvalid (bpf_apf_slv_if.arvalid ), + .bpf_apf_slv_arready (bpf_apf_slv_if.arready ), + .bpf_apf_slv_rdata (bpf_apf_slv_if.rdata ), + .bpf_apf_slv_rresp (bpf_apf_slv_if.rresp ), + .bpf_apf_slv_rvalid (bpf_apf_slv_if.rvalid ), + .bpf_apf_slv_rready (bpf_apf_slv_if.rready ), + + .bpf_fme_mst_awaddr (bpf_fme_mst_if.awaddr ), + .bpf_fme_mst_awprot (bpf_fme_mst_if.awprot ), + .bpf_fme_mst_awvalid (bpf_fme_mst_if.awvalid ), + .bpf_fme_mst_awready (bpf_fme_mst_if.awready ), + .bpf_fme_mst_wdata (bpf_fme_mst_if.wdata ), + .bpf_fme_mst_wstrb (bpf_fme_mst_if.wstrb ), + .bpf_fme_mst_wvalid (bpf_fme_mst_if.wvalid ), + .bpf_fme_mst_wready (bpf_fme_mst_if.wready ), + .bpf_fme_mst_bresp (bpf_fme_mst_if.bresp ), + .bpf_fme_mst_bvalid (bpf_fme_mst_if.bvalid ), + .bpf_fme_mst_bready (bpf_fme_mst_if.bready ), + .bpf_fme_mst_araddr (bpf_fme_mst_if.araddr ), + .bpf_fme_mst_arprot (bpf_fme_mst_if.arprot ), + .bpf_fme_mst_arvalid (bpf_fme_mst_if.arvalid ), + .bpf_fme_mst_arready (bpf_fme_mst_if.arready ), + .bpf_fme_mst_rdata (bpf_fme_mst_if.rdata ), + .bpf_fme_mst_rresp (bpf_fme_mst_if.rresp ), + .bpf_fme_mst_rvalid (bpf_fme_mst_if.rvalid ), + .bpf_fme_mst_rready (bpf_fme_mst_if.rready ) + ); + + // Reserved address response + bpf_dummy_slv + bpf_rsv_5_slv ( + .clk (clk_1x), + .dummy_slv_if (bpf_rsv_5_slv_if) + ); + + bpf_dummy_slv + bpf_rsv_6_slv ( + .clk (clk_1x), + .dummy_slv_if (bpf_rsv_6_slv_if) + ); + + bpf_dummy_slv + bpf_rsv_7_slv ( + .clk (clk_1x), + .dummy_slv_if (bpf_rsv_7_slv_if) + ); + + `ifdef DEBUG_BPF + + reg [25:0] DEBUG_apf_mst_awaddr /* synthesis noprune */ ; + reg [ 2:0] DEBUG_apf_mst_awprot /* synthesis noprune */ ; + reg DEBUG_apf_mst_awvalid /* synthesis noprune */ ; + reg DEBUG_apf_mst_awready /* synthesis noprune */ ; + reg [25:0] DEBUG_apf_mst_araddr /* synthesis noprune */ ; + reg [ 2:0] DEBUG_apf_mst_arprot /* synthesis noprune */ ; + reg DEBUG_apf_mst_arvalid /* synthesis noprune */ ; + reg DEBUG_apf_mst_arready /* synthesis noprune */ ; + reg [ 7:0] DEBUG_apf_mst_wstrb /* synthesis noprune */ ; + reg DEBUG_apf_mst_wvalid /* synthesis noprune */ ; + reg DEBUG_apf_mst_wready /* synthesis noprune */ ; + reg [ 1:0] DEBUG_apf_mst_rresp /* synthesis noprune */ ; + reg DEBUG_apf_mst_rvalid /* synthesis noprune */ ; + reg DEBUG_apf_mst_rready /* synthesis noprune */ ; + reg [ 1:0] DEBUG_apf_mst_bresp /* synthesis noprune */ ; + reg DEBUG_apf_mst_bvalid /* synthesis noprune */ ; + reg DEBUG_apf_mst_bready /* synthesis noprune */ ; + + reg [25:0] DEBUG_fme_slv_awaddr /* synthesis noprune */ ; + reg [ 2:0] DEBUG_fme_slv_awprot /* synthesis noprune */ ; + reg DEBUG_fme_slv_awvalid /* synthesis noprune */ ; + reg DEBUG_fme_slv_awready /* synthesis noprune */ ; + reg [25:0] DEBUG_fme_slv_araddr /* synthesis noprune */ ; + reg [ 2:0] DEBUG_fme_slv_arprot /* synthesis noprune */ ; + reg DEBUG_fme_slv_arvalid /* synthesis noprune */ ; + reg DEBUG_fme_slv_arready /* synthesis noprune */ ; + reg [ 7:0] DEBUG_fme_slv_wstrb /* synthesis noprune */ ; + reg DEBUG_fme_slv_wvalid /* synthesis noprune */ ; + reg DEBUG_fme_slv_wready /* synthesis noprune */ ; + reg [ 1:0] DEBUG_fme_slv_rresp /* synthesis noprune */ ; + reg DEBUG_fme_slv_rvalid /* synthesis noprune */ ; + reg DEBUG_fme_slv_rready /* synthesis noprune */ ; + reg [ 1:0] DEBUG_fme_slv_bresp /* synthesis noprune */ ; + reg DEBUG_fme_slv_bvalid /* synthesis noprune */ ; + reg DEBUG_fme_slv_bready /* synthesis noprune */ ; + + reg [25:0] DEBUG_pcie_slv_awaddr /* synthesis noprune */ ; + reg [ 2:0] DEBUG_pcie_slv_awprot /* synthesis noprune */ ; + reg DEBUG_pcie_slv_awvalid /* synthesis noprune */ ; + reg DEBUG_pcie_slv_awready /* synthesis noprune */ ; + reg [25:0] DEBUG_pcie_slv_araddr /* synthesis noprune */ ; + reg [ 2:0] DEBUG_pcie_slv_arprot /* synthesis noprune */ ; + reg DEBUG_pcie_slv_arvalid /* synthesis noprune */ ; + reg DEBUG_pcie_slv_arready /* synthesis noprune */ ; + reg [ 7:0] DEBUG_pcie_slv_wstrb /* synthesis noprune */ ; + reg DEBUG_pcie_slv_wvalid /* synthesis noprune */ ; + reg DEBUG_pcie_slv_wready /* synthesis noprune */ ; + reg [ 1:0] DEBUG_pcie_slv_rresp /* synthesis noprune */ ; + reg DEBUG_pcie_slv_rvalid /* synthesis noprune */ ; + reg DEBUG_pcie_slv_rready /* synthesis noprune */ ; + reg [ 1:0] DEBUG_pcie_slv_bresp /* synthesis noprune */ ; + reg DEBUG_pcie_slv_bvalid /* synthesis noprune */ ; + reg DEBUG_pcie_slv_bready /* synthesis noprune */ ; + + reg [25:0] DEBUG_pmci_slv_awaddr /* synthesis noprune */ ; + reg [ 2:0] DEBUG_pmci_slv_awprot /* synthesis noprune */ ; + reg DEBUG_pmci_slv_awvalid /* synthesis noprune */ ; + reg DEBUG_pmci_slv_awready /* synthesis noprune */ ; + reg [25:0] DEBUG_pmci_slv_araddr /* synthesis noprune */ ; + reg [ 2:0] DEBUG_pmci_slv_arprot /* synthesis noprune */ ; + reg DEBUG_pmci_slv_arvalid /* synthesis noprune */ ; + reg DEBUG_pmci_slv_arready /* synthesis noprune */ ; + reg [ 7:0] DEBUG_pmci_slv_wstrb /* synthesis noprune */ ; + reg DEBUG_pmci_slv_wvalid /* synthesis noprune */ ; + reg DEBUG_pmci_slv_wready /* synthesis noprune */ ; + reg [ 1:0] DEBUG_pmci_slv_rresp /* synthesis noprune */ ; + reg DEBUG_pmci_slv_rvalid /* synthesis noprune */ ; + reg DEBUG_pmci_slv_rready /* synthesis noprune */ ; + reg [ 1:0] DEBUG_pmci_slv_bresp /* synthesis noprune */ ; + reg DEBUG_pmci_slv_bvalid /* synthesis noprune */ ; + reg DEBUG_pmci_slv_bready /* synthesis noprune */ ; + + reg [25:0] DEBUG_emif_slv_awaddr /* synthesis noprune */ ; + reg [ 2:0] DEBUG_emif_slv_awprot /* synthesis noprune */ ; + reg DEBUG_emif_slv_awvalid /* synthesis noprune */ ; + reg DEBUG_emif_slv_awready /* synthesis noprune */ ; + reg [25:0] DEBUG_emif_slv_araddr /* synthesis noprune */ ; + reg [ 2:0] DEBUG_emif_slv_arprot /* synthesis noprune */ ; + reg DEBUG_emif_slv_arvalid /* synthesis noprune */ ; + reg DEBUG_emif_slv_arready /* synthesis noprune */ ; + reg [ 7:0] DEBUG_emif_slv_wstrb /* synthesis noprune */ ; + reg DEBUG_emif_slv_wvalid /* synthesis noprune */ ; + reg DEBUG_emif_slv_wready /* synthesis noprune */ ; + reg [ 1:0] DEBUG_emif_slv_rresp /* synthesis noprune */ ; + reg DEBUG_emif_slv_rvalid /* synthesis noprune */ ; + reg DEBUG_emif_slv_rready /* synthesis noprune */ ; + reg [ 1:0] DEBUG_emif_slv_bresp /* synthesis noprune */ ; + reg DEBUG_emif_slv_bvalid /* synthesis noprune */ ; + reg DEBUG_emif_slv_bready /* synthesis noprune */ ; + + reg [25:0] DEBUG_hssi_slv_awaddr /* synthesis noprune */ ; + reg [ 2:0] DEBUG_hssi_slv_awprot /* synthesis noprune */ ; + reg DEBUG_hssi_slv_awvalid /* synthesis noprune */ ; + reg DEBUG_hssi_slv_awready /* synthesis noprune */ ; + reg [25:0] DEBUG_hssi_slv_araddr /* synthesis noprune */ ; + reg [ 2:0] DEBUG_hssi_slv_arprot /* synthesis noprune */ ; + reg DEBUG_hssi_slv_arvalid /* synthesis noprune */ ; + reg DEBUG_hssi_slv_arready /* synthesis noprune */ ; + reg [ 7:0] DEBUG_hssi_slv_wstrb /* synthesis noprune */ ; + reg DEBUG_hssi_slv_wvalid /* synthesis noprune */ ; + reg DEBUG_hssi_slv_wready /* synthesis noprune */ ; + reg [ 1:0] DEBUG_hssi_slv_rresp /* synthesis noprune */ ; + reg DEBUG_hssi_slv_rvalid /* synthesis noprune */ ; + reg DEBUG_hssi_slv_rready /* synthesis noprune */ ; + reg [ 1:0] DEBUG_hssi_slv_bresp /* synthesis noprune */ ; + reg DEBUG_hssi_slv_bvalid /* synthesis noprune */ ; + reg DEBUG_hssi_slv_bready /* synthesis noprune */ ; + + reg DEBUG_rsv_5_slv_wvalid /* synthesis noprune */ ; + reg DEBUG_rsv_5_slv_wready /* synthesis noprune */ ; + reg DEBUG_rsv_5_slv_rvalid /* synthesis noprune */ ; + reg DEBUG_rsv_5_slv_rready /* synthesis noprune */ ; + reg DEBUG_rsv_6_slv_wvalid /* synthesis noprune */ ; + reg DEBUG_rsv_6_slv_wready /* synthesis noprune */ ; + reg DEBUG_rsv_6_slv_rvalid /* synthesis noprune */ ; + reg DEBUG_rsv_6_slv_rready /* synthesis noprune */ ; + reg DEBUG_rsv_7_slv_wvalid /* synthesis noprune */ ; + reg DEBUG_rsv_7_slv_wready /* synthesis noprune */ ; + reg DEBUG_rsv_7_slv_rvalid /* synthesis noprune */ ; + reg DEBUG_rsv_7_slv_rready /* synthesis noprune */ ; + + + always @(posedge clk_1x) begin + + DEBUG_apf_mst_awaddr <= bpf_apf_mst_if.awaddr ; + DEBUG_apf_mst_awprot <= bpf_apf_mst_if.awprot ; + DEBUG_apf_mst_awvalid <= bpf_apf_mst_if.awvalid ; + DEBUG_apf_mst_awready <= bpf_apf_mst_if.awready ; + DEBUG_apf_mst_wstrb <= bpf_apf_mst_if.wstrb ; + DEBUG_apf_mst_wvalid <= bpf_apf_mst_if.wvalid ; + DEBUG_apf_mst_wready <= bpf_apf_mst_if.wready ; + DEBUG_apf_mst_bresp <= bpf_apf_mst_if.bresp ; + DEBUG_apf_mst_bvalid <= bpf_apf_mst_if.bvalid ; + DEBUG_apf_mst_bready <= bpf_apf_mst_if.bready ; + DEBUG_apf_mst_araddr <= bpf_apf_mst_if.araddr ; + DEBUG_apf_mst_arprot <= bpf_apf_mst_if.arprot ; + DEBUG_apf_mst_arvalid <= bpf_apf_mst_if.arvalid ; + DEBUG_apf_mst_arready <= bpf_apf_mst_if.arready ; + DEBUG_apf_mst_rresp <= bpf_apf_mst_if.rresp ; + DEBUG_apf_mst_rvalid <= bpf_apf_mst_if.rvalid ; + DEBUG_apf_mst_rready <= bpf_apf_mst_if.rready ; + + DEBUG_fme_slv_awaddr <= bpf_fme_slv_if.awaddr ; + DEBUG_fme_slv_awprot <= bpf_fme_slv_if.awprot ; + DEBUG_fme_slv_awvalid <= bpf_fme_slv_if.awvalid ; + DEBUG_fme_slv_awready <= bpf_fme_slv_if.awready ; + DEBUG_fme_slv_wstrb <= bpf_fme_slv_if.wstrb ; + DEBUG_fme_slv_wvalid <= bpf_fme_slv_if.wvalid ; + DEBUG_fme_slv_wready <= bpf_fme_slv_if.wready ; + DEBUG_fme_slv_bresp <= bpf_fme_slv_if.bresp ; + DEBUG_fme_slv_bvalid <= bpf_fme_slv_if.bvalid ; + DEBUG_fme_slv_bready <= bpf_fme_slv_if.bready ; + DEBUG_fme_slv_araddr <= bpf_fme_slv_if.araddr ; + DEBUG_fme_slv_arprot <= bpf_fme_slv_if.arprot ; + DEBUG_fme_slv_arvalid <= bpf_fme_slv_if.arvalid ; + DEBUG_fme_slv_arready <= bpf_fme_slv_if.arready ; + DEBUG_fme_slv_rresp <= bpf_fme_slv_if.rresp ; + DEBUG_fme_slv_rvalid <= bpf_fme_slv_if.rvalid ; + DEBUG_fme_slv_rready <= bpf_fme_slv_if.rready ; + + DEBUG_pcie_slv_awaddr <= bpf_pcie_slv_if.awaddr ; + DEBUG_pcie_slv_awprot <= bpf_pcie_slv_if.awprot ; + DEBUG_pcie_slv_awvalid <= bpf_pcie_slv_if.awvalid; + DEBUG_pcie_slv_awready <= bpf_pcie_slv_if.awready; + DEBUG_pcie_slv_wstrb <= bpf_pcie_slv_if.wstrb ; + DEBUG_pcie_slv_wvalid <= bpf_pcie_slv_if.wvalid ; + DEBUG_pcie_slv_wready <= bpf_pcie_slv_if.wready ; + DEBUG_pcie_slv_bresp <= bpf_pcie_slv_if.bresp ; + DEBUG_pcie_slv_bvalid <= bpf_pcie_slv_if.bvalid ; + DEBUG_pcie_slv_bready <= bpf_pcie_slv_if.bready ; + DEBUG_pcie_slv_araddr <= bpf_pcie_slv_if.araddr ; + DEBUG_pcie_slv_arprot <= bpf_pcie_slv_if.arprot ; + DEBUG_pcie_slv_arvalid <= bpf_pcie_slv_if.arvalid; + DEBUG_pcie_slv_arready <= bpf_pcie_slv_if.arready; + DEBUG_pcie_slv_rresp <= bpf_pcie_slv_if.rresp ; + DEBUG_pcie_slv_rvalid <= bpf_pcie_slv_if.rvalid ; + DEBUG_pcie_slv_rready <= bpf_pcie_slv_if.rready ; + + DEBUG_pmci_slv_awaddr <= bpf_pmci_slv_if.awaddr ; + DEBUG_pmci_slv_awprot <= bpf_pmci_slv_if.awprot ; + DEBUG_pmci_slv_awvalid <= bpf_pmci_slv_if.awvalid; + DEBUG_pmci_slv_awready <= bpf_pmci_slv_if.awready; + DEBUG_pmci_slv_wstrb <= bpf_pmci_slv_if.wstrb ; + DEBUG_pmci_slv_wvalid <= bpf_pmci_slv_if.wvalid ; + DEBUG_pmci_slv_wready <= bpf_pmci_slv_if.wready ; + DEBUG_pmci_slv_bresp <= bpf_pmci_slv_if.bresp ; + DEBUG_pmci_slv_bvalid <= bpf_pmci_slv_if.bvalid ; + DEBUG_pmci_slv_bready <= bpf_pmci_slv_if.bready ; + DEBUG_pmci_slv_araddr <= bpf_pmci_slv_if.araddr ; + DEBUG_pmci_slv_arprot <= bpf_pmci_slv_if.arprot ; + DEBUG_pmci_slv_arvalid <= bpf_pmci_slv_if.arvalid; + DEBUG_pmci_slv_arready <= bpf_pmci_slv_if.arready; + DEBUG_pmci_slv_rresp <= bpf_pmci_slv_if.rresp ; + DEBUG_pmci_slv_rvalid <= bpf_pmci_slv_if.rvalid ; + DEBUG_pmci_slv_rready <= bpf_pmci_slv_if.rready ; + + DEBUG_emif_slv_awaddr <= bpf_emif_slv_if.awaddr ; + DEBUG_emif_slv_awprot <= bpf_emif_slv_if.awprot ; + DEBUG_emif_slv_awvalid <= bpf_emif_slv_if.awvalid; + DEBUG_emif_slv_awready <= bpf_emif_slv_if.awready; + DEBUG_emif_slv_wstrb <= bpf_emif_slv_if.wstrb ; + DEBUG_emif_slv_wvalid <= bpf_emif_slv_if.wvalid ; + DEBUG_emif_slv_wready <= bpf_emif_slv_if.wready ; + DEBUG_emif_slv_bresp <= bpf_emif_slv_if.bresp ; + DEBUG_emif_slv_bvalid <= bpf_emif_slv_if.bvalid ; + DEBUG_emif_slv_bready <= bpf_emif_slv_if.bready ; + DEBUG_emif_slv_araddr <= bpf_emif_slv_if.araddr ; + DEBUG_emif_slv_arprot <= bpf_emif_slv_if.arprot ; + DEBUG_emif_slv_arvalid <= bpf_emif_slv_if.arvalid; + DEBUG_emif_slv_arready <= bpf_emif_slv_if.arready; + DEBUG_emif_slv_rresp <= bpf_emif_slv_if.rresp ; + DEBUG_emif_slv_rvalid <= bpf_emif_slv_if.rvalid ; + DEBUG_emif_slv_rready <= bpf_emif_slv_if.rready ; + + DEBUG_hssi_slv_awaddr <= bpf_hssi_slv_if.awaddr ; + DEBUG_hssi_slv_awprot <= bpf_hssi_slv_if.awprot ; + DEBUG_hssi_slv_awvalid <= bpf_hssi_slv_if.awvalid; + DEBUG_hssi_slv_awready <= bpf_hssi_slv_if.awready; + DEBUG_hssi_slv_wstrb <= bpf_hssi_slv_if.wstrb ; + DEBUG_hssi_slv_wvalid <= bpf_hssi_slv_if.wvalid ; + DEBUG_hssi_slv_wready <= bpf_hssi_slv_if.wready ; + DEBUG_hssi_slv_bresp <= bpf_hssi_slv_if.bresp ; + DEBUG_hssi_slv_bvalid <= bpf_hssi_slv_if.bvalid ; + DEBUG_hssi_slv_bready <= bpf_hssi_slv_if.bready ; + DEBUG_hssi_slv_araddr <= bpf_hssi_slv_if.araddr ; + DEBUG_hssi_slv_arprot <= bpf_hssi_slv_if.arprot ; + DEBUG_hssi_slv_arvalid <= bpf_hssi_slv_if.arvalid; + DEBUG_hssi_slv_arready <= bpf_hssi_slv_if.arready; + DEBUG_hssi_slv_rresp <= bpf_hssi_slv_if.rresp ; + DEBUG_hssi_slv_rvalid <= bpf_hssi_slv_if.rvalid ; + DEBUG_hssi_slv_rready <= bpf_hssi_slv_if.rready ; + + DEBUG_rsv_5_slv_wvalid <= bpf_rsv_5_slv_if.wvalid ; + DEBUG_rsv_5_slv_wready <= bpf_rsv_5_slv_if.wready ; + DEBUG_rsv_5_slv_rvalid <= bpf_rsv_5_slv_if.rvalid ; + DEBUG_rsv_5_slv_rready <= bpf_rsv_5_slv_if.rready ; + DEBUG_rsv_6_slv_wvalid <= bpf_rsv_6_slv_if.wvalid ; + DEBUG_rsv_6_slv_wready <= bpf_rsv_6_slv_if.wready ; + DEBUG_rsv_6_slv_rvalid <= bpf_rsv_6_slv_if.rvalid ; + DEBUG_rsv_6_slv_rready <= bpf_rsv_6_slv_if.rready ; + DEBUG_rsv_7_slv_wvalid <= bpf_rsv_7_slv_if.wvalid ; + DEBUG_rsv_7_slv_wready <= bpf_rsv_7_slv_if.wready ; + DEBUG_rsv_7_slv_rvalid <= bpf_rsv_7_slv_if.rvalid ; + DEBUG_rsv_7_slv_rready <= bpf_rsv_7_slv_if.rready ; + end + `endif + +/* +always_comb +begin + bpf_rsv_5_slv_if.awready = 1; + bpf_rsv_5_slv_if.wready = 1; + bpf_rsv_5_slv_if.bresp = 0; + bpf_rsv_5_slv_if.arready = 1; + bpf_rsv_5_slv_if.rdata = 0; + bpf_rsv_5_slv_if.rresp = 0; + + bpf_rsv_6_slv_if.awready = 1; + bpf_rsv_6_slv_if.wready = 1; + bpf_rsv_6_slv_if.bresp = 0; + bpf_rsv_6_slv_if.arready = 1; + bpf_rsv_6_slv_if.rdata = 0; + bpf_rsv_6_slv_if.rresp = 0; + + bpf_rsv_7_slv_if.awready = 1; + bpf_rsv_7_slv_if.wready = 1; + bpf_rsv_7_slv_if.bresp = 0; + bpf_rsv_7_slv_if.arready = 1; + bpf_rsv_7_slv_if.rdata = 0; + bpf_rsv_7_slv_if.rresp = 0; +end + +always_ff @ ( posedge clk_1x ) +begin // DUMMY address response + bpf_rsv_5_slv_if.bvalid <= bpf_rsv_5_slv_if.awvalid; + bpf_rsv_5_slv_if.rvalid <= bpf_rsv_5_slv_if.arvalid; + bpf_rsv_6_slv_if.bvalid <= bpf_rsv_6_slv_if.awvalid; + bpf_rsv_6_slv_if.rvalid <= bpf_rsv_6_slv_if.arvalid; + bpf_rsv_7_slv_if.bvalid <= bpf_rsv_7_slv_if.awvalid; + bpf_rsv_7_slv_if.rvalid <= bpf_rsv_7_slv_if.arvalid; +end +*/ + +//******************************* +// Memory Subsystem +//******************************* +ofs_fim_axi_mmio_if emif_csr_if(); +ofs_fim_irq_axis_if emif_fme_irq_if(); + +axi_lite2mmio axi_lite2mmio ( + .clk (clk_1x), + .rst_n (rst_n_g_1x), + .lite_if(bpf_emif_slv_if), + .mmio_if(emif_csr_if) +); + +emif_top #( + .NUM_LOCAL_MEM_BANKS(NUM_MEM_CH) +) +emif_top_inst ( + .emif_rst_n (rst_n_g_1x), + .afu_reset (~rst_n_g_1x), + .pr_freeze (1'b0), + + // CSR interface + .csr_if (emif_csr_if), //ofs_fim_axi_mmio_if.slave + + // Interrupt interface + .fme_irq_if (emif_fme_irq_if), //ofs_fim_irq_axis_if.master + + // Avalon-MM interface for each EMIF. + .ddr4_avmm (ddr4_avmm), //ofs_fim_emif_avmm_if.emif ddr4_avmm [NUM_LOCAL_MEM_BANKS-1:0] + + // EMIF 4 Interfaces DDR4 x72 RDIMM (x8) + .ddr4_mem (ddr4_mem) //ofs_fim_emif_mem_if.emif ddr4_mem [NUM_LOCAL_MEM_BANKS-1:0] +); + + +endmodule + +module bpf_dummy_slv ( + input clk, + ofs_fim_axi_lite_if.slave dummy_slv_if +); + + always_comb + begin + dummy_slv_if.awready = 1; + dummy_slv_if.wready = 1; + dummy_slv_if.bresp = 0; + dummy_slv_if.arready = 1; + dummy_slv_if.rdata = 0; + dummy_slv_if.rresp = 0; + end + + always_ff @ ( posedge clk ) + begin // DUMMY address response + dummy_slv_if.bvalid <= dummy_slv_if.awvalid; + dummy_slv_if.rvalid <= dummy_slv_if.arvalid; + end + +endmodule diff --git a/src/top/ofs_d5005.ini b/src/top/ofs_d5005.ini new file mode 100644 index 0000000..b19c3ab --- /dev/null +++ b/src/top/ofs_d5005.ini @@ -0,0 +1,75 @@ +;; Copyright (C) 2022-2023 Intel Corporation +;; SPDX-License-Identifier: MIT + +;; Platform Interface Manager configuration +;; +;; Intel® FPGA Programmable Acceleration Card D5005 +;; OFS FIM +;; +;; Local memory with Avalon native interface +;; + +[define] +PLATFORM_FPGA_FAMILY_S10=1 +PLATFORM_FPGA_PAC=1 +PLATFORM_FPGA_PAC_D5005=1 +PLATFORM_FPGA_PAC_DC=1 +;; Indicates that ASE emulation of the afu_main interface is offered +ASE_AFU_MAIN_IF_OFFERED=1 +native_class=none + +[clocks] +pclk_freq=250 +native_class=none + +[host_chan] +num_ports=2 +native_class=native_axis_pcie_tlp +gasket=pcie_ss + +;; Minimum number of outstanding flits that must be in flight to +;; saturate bandwidth. Maximum bandwidth is typically a function +;; of the number flits in flight, indepent of burst sizes. +max_bw_active_flits_rd=384 +max_bw_active_flits_wr=128 + +;; Number of independent interrupt vectors, per host channel port. +num_intr_vecs=4 + +;; Recommended number of times an AFU should register host channel +;; signals before use in order to make successful timing closure likely. +suggested_timing_reg_stages=0 + +[local_mem] +native_class=native_avalon +gasket=fim_emif_avmm +;; Ideally, num_banks would be ofs_fim_emif_cfg_pkg::NUM_LOCAL_MEM_BANKS. +;; Unfortunately, some PIM scripts need to know the actual number of banks, +;; making it impossible to use SystemVerilog package values. +num_banks=top_cfg_pkg::NUM_MEM_CH +addr_width=ofs_fim_emif_cfg_pkg::AVMM_ADDR_WIDTH +data_width=ofs_fim_emif_cfg_pkg::AVMM_DATA_BASE_WIDTH +ecc_width=ofs_fim_emif_cfg_pkg::AVMM_ECC_WIDTH +burst_cnt_width=ofs_fim_emif_cfg_pkg::AVMM_BURSTCOUNT_WIDTH +suggested_timing_reg_stages=2 + +;;[hssi] +;;native_class=native_axi_mac +;;num_channels=ofs_fim_eth_if_pkg::NUM_ETH_CHANNELS +;;has_clkdiv2=1 + +;; Sideband interface specific to this platform. It is used for passing +;; state through plat_ifc.other.ports[] that the PIM does not manage. +[other] +;; Use the PIM's "generic" extension class. The PIM provides the top-level +;; generic wrapper around ports and the implementation of the type is set below. +template_class=generic_templates +native_class=ports +;; All PIM wrappers are vectors. Depending on the data being passed through +;; the interface, FIMs may either use more ports or put vectors inside the +;; port's type. +num_ports=1 +;; Data type of the sideband interface +type=ofs_plat_fim_other_if +;; Import the "other" SystemVerilog definitions into the PIM (relative path) +import=../../ofs-common/src/fpga_family/stratix10/port_gasket/afu_main_pim/extend_pim/ diff --git a/src/top/readme.txt b/src/top/readme.txt new file mode 100644 index 0000000..25568d5 --- /dev/null +++ b/src/top/readme.txt @@ -0,0 +1,33 @@ +Folder Structure: + +├── d5005 +│   ├── afu +│   │   ├── AFU_INTF_CSR.xls // list of CSR details +│   │   ├── afu_intf.sv // AFU interface module between PCIe and PF-VF mux module +│   │   ├── afu_intf_csr.sv // AFU interface to CSR register +│   │   ├── afu_top.sv // AFU top wrapper +│   │   ├── he_mem +│   │   │   └── he_mem_top.sv // HE MEM top level wrapper +│   │   ├── mmio_handler.sv // handles mmio timeout and unexpected read response +│   │   ├── pf_vf_mux_top +│   │   │   └── mux +│   │   │   └── top_cfg_pkg.sv // this is a package define the parameters used in top level module +│   │   ├── port_traffic_control.sv // Controls AFU TX traffic going upstream +│   │   ├── port_tx_fifo.sv // FIFO with store and forward capability to buffer AFU TX packets +│   │   ├── protocol_checker.sv // Considers DM PCIe packet sizes/widths +│   │   ├── prtcl_chkr_pkg.sv // Package contains the localparams used in the protocol checker +│   │   └── tx_filter.sv // Handles MMIO timeout response and block AXI TX traffic on an error +│   ├── includes +│   │   ├── fpga_defines.vh // FPGA defines parameters for D5005 +│   │   ├── ofs_fim_cfg_pkg.sv // This package defines the global parameters of CoreFIM +│   │   ├── ofs_pcie_ss_plat_cfg.vh // to associate a version tag with the values in ofs_pcie_ss_plat_cfg_pkg +│   │   └── ofs_pcie_ss_plat_cfg_pkg.sv // platform-specific PCIe configuration package +│   ├── iofs_top.sv // IOFS top wrapper file which has ethernet, pcie, pmci, fme, afu, bpf interconnect, emif, system rst controller and clk_pll modules +│   ├── ofs_d5005.ini // Platform interface manager configuration +│   ├── pmci +│   │   └── pmci_top.sv // platform management controller with SPI master bridge and SPI CSR +│   ├── rst_ctrl.sv // system reset controller +│   └── spi +│   ├── SPI_CSR.xls // SPI Configuration and Status Register details +│   ├── spi_bridge_csr.sv // SPI CSR register module +│   └── spi_bridge_top.sv // SPI top with SPI master bridge and SPI CSR instatantiated diff --git a/src/top/rst_ctrl.sv b/src/top/rst_ctrl.sv new file mode 100755 index 0000000..1f70f1c --- /dev/null +++ b/src/top/rst_ctrl.sv @@ -0,0 +1,454 @@ +// Copyright 2020 Intel Corporation +// SPDX-License-Identifier: MIT + +// Description +//----------------------------------------------------------------------------- +// +// System reset controller +// +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Module ports +//----------------------------------------------------------------------------- +import ofs_fim_if_pkg::*; +import ofs_fim_cfg_pkg::*; + +module rst_ctrl #( + parameter SYNC_RESET_MIN_WIDTH = 256, + parameter PF0_NUM_VF = FIM_NUM_VF, + parameter PF1_NUM_VF = 0 +)( +input clk_1x, // Global clock +input clk_div2, // Global clock divide by 2 +input clk_100M, // Clock 100 MHz +input pll_locked, // PLL locked flag +input pcie_reset_n, // PCIe pin_perst (active low) +input pcie_reset_status, // PCIe SRC reset status + +output ninit_done, // FPGA initialization done (active low) +output npor, // PCIe PowerOn reset (active low) +output reg rst_n, // Asynchronous system reset +output reg pwr_good_clk_n, // power good reset synchronous to clk_1x +output reg rst_n_1x, // System reset synchronous to clk_1x +output reg rst_n_div2, // System reset synchronous to clk_div2 +output reg rst_n_100M, // System reset synchronous to clk_100M + +// Function Level Reset sideband +input t_sideband_from_pcie p2c_sideband, +output t_sideband_to_pcie c2p_sideband, + +// Function Level Reset request +output logic [PF0_NUM_VF:0] pf0_flrst_n, +output logic [PF1_NUM_VF:0] pf1_flrst_n +); +wire rst_n_d; +wire rst_n_1x_d; +wire rst_n_div2_d; +wire rst_n_100M_d; +logic pll_locked_w; + +// pwr_good_clk_n did not simulate well. Only one clock went by before pll_locked went hi. So we added the below. +`ifdef SIM_MODE + initial begin + pll_locked_w = 1'b0; + #127ns; + pll_locked_w = 1'b1; + end +`else + assign pll_locked_w = pll_locked; +`endif + +assign npor = pcie_reset_n && ~ninit_done; +assign rst_n = npor && pll_locked_w && ~pcie_reset_status; + +//----------------------------------------------------------------------------- +// Modules instances +//----------------------------------------------------------------------------- + +// Configuration reset release IP + +`ifdef SIM_MODE +assign ninit_done = 1'b0; +`else +cfg_mon cfg_mon ( + .ninit_done (ninit_done) +); +`endif + +// Reset syncronizers + +altera_std_synchronizer_nocut rst_clk1x_sync ( + .clk (clk_1x ), +// .reset_n (rst_n ), +// .din (1'b1 ), + .reset_n (1'b1 ), + .din (rst_n ), + .dout (rst_n_1x_d ) +); +always @(posedge clk_1x) rst_n_1x <= rst_n_1x_d; + +altera_std_synchronizer_nocut rst_clkdiv2_sync ( + .clk (clk_div2 ), +// .reset_n (rst_n ), +// .din (1'b1 ), + .reset_n (1'b1 ), + .din (rst_n ), + .dout (rst_n_div2_d) +); +always @(posedge clk_div2) rst_n_div2 <= rst_n_div2_d; + +altera_std_synchronizer_nocut rst_clk100M_sync ( + .clk (clk_100M ), +// .reset_n (rst_n ), +// .din (1'b1 ), + .reset_n (1'b1 ), + .din (rst_n ), + .dout (rst_n_100M_d) +); +always @(posedge clk_100M) rst_n_100M <= rst_n_100M_d; + +// FLR loopback + +typedef enum { + RESET_HOLD_BIT, + RESET_SET_BIT, + RESET_DEACT_BIT, + RESET_CLEAR_BIT, + RESET_STATE_MAX +} reset_control_idx; + +typedef enum logic [RESET_STATE_MAX-1:0] { + RESET_HOLD = (1 << RESET_HOLD_BIT), + RESET_SET = (1 << RESET_SET_BIT), + RESET_DEACT = (1 << RESET_DEACT_BIT), + RESET_CLEAR = (1 << RESET_CLEAR_BIT) +} t_fsm_reset; + +t_fsm_reset vf_fsm_reset, vf_fsm_reset_next, + pf0_fsm_reset, pf0_fsm_reset_next, + pf1_fsm_reset, pf1_fsm_reset_next; + +logic vf_softreset, vf_softreset_next, + pf0_softreset, pf0_softreset_next, + pf1_softreset, pf1_softreset_next; + +logic [$clog2(SYNC_RESET_MIN_WIDTH):0] + vf_reset_pulse_width, vf_reset_pulse_width_next, + pf0_reset_pulse_width, pf0_reset_pulse_width_next, + pf1_reset_pulse_width, pf1_reset_pulse_width_next; + +logic vf_reset_done_state, + pf0_reset_done_state, + pf1_reset_done_state; + +logic flr_active_vf, + flr_active_pf0, + flr_active_pf1; + +logic flr_rcvd_vf_flag; +logic [FIM_VF_WIDTH-1:0] flr_rcvd_vf_num; +logic [FIM_PF_WIDTH-1:0] flr_rcvd_pf_num; + +integer i; + +always_comb +begin + flr_active_vf = flr_rcvd_vf_flag; + flr_active_pf0 = p2c_sideband.flr_active_pf[0]; + flr_active_pf1 = p2c_sideband.flr_active_pf[1]; + + c2p_sideband.flr_completed_vf_num + = flr_rcvd_vf_num; + c2p_sideband.flr_completed_pf_num + = flr_rcvd_pf_num; + c2p_sideband.flr_completed_vf + = vf_reset_done_state && flr_rcvd_vf_flag; + + c2p_sideband.flr_completed_pf + = '0; + c2p_sideband.flr_completed_pf[0] + = pf0_reset_done_state && p2c_sideband.flr_active_pf[0]; + c2p_sideband.flr_completed_pf[1] + = pf1_reset_done_state && p2c_sideband.flr_active_pf[1]; +end + +always_ff @ ( posedge clk_1x ) +begin + vf_reset_done_state = vf_fsm_reset[RESET_DEACT_BIT]; + pf0_reset_done_state = pf0_fsm_reset[RESET_DEACT_BIT]; + pf1_reset_done_state = pf1_fsm_reset[RESET_DEACT_BIT]; +end + +always_ff @ ( posedge clk_1x ) +begin + if ( !rst_n_1x ) + begin + flr_rcvd_vf_flag <= 1'b0; + flr_rcvd_vf_num <= '0; + flr_rcvd_pf_num <= '0; + end + else + if ( p2c_sideband.flr_rcvd_vf ) + begin + flr_rcvd_vf_flag <= 1'b1; + flr_rcvd_vf_num <= p2c_sideband.flr_rcvd_vf_num; + flr_rcvd_pf_num <= p2c_sideband.flr_rcvd_pf_num; + end + else + if ( c2p_sideband.flr_completed_vf ) + begin + flr_rcvd_vf_flag <= 1'b0; + flr_rcvd_vf_num <= '0; + flr_rcvd_pf_num <= '0; + end +end + +// !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +// !! ASSUMPTION !! +// !! ONLY (1) FLR_RCVD_VF -> FLR_COMPLETED_VF AT A TIME !! +// !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + +always_ff @ ( posedge clk_1x ) +begin + if ( !rst_n_1x ) + begin + pf0_flrst_n <= '0; + pf1_flrst_n <= '0; + end + else + begin + pf0_flrst_n <= '{default:'1}; + pf1_flrst_n <= '{default:'1}; + + pf0_flrst_n[0] <= p2c_sideband.flr_active_pf[0] + && pf0_softreset ? 1'b0 : + 1'b1; + + pf1_flrst_n[0] <= p2c_sideband.flr_active_pf[1] + && pf1_softreset ? 1'b0 : + 1'b1; + + if ( vf_softreset ) + begin + case ( flr_rcvd_pf_num ) + + 0: + begin + for ( i = 0 ; i < PF0_NUM_VF ; i++ ) + pf0_flrst_n[i+1] <= ( flr_rcvd_vf_num == i ) ? 1'b0 : + 1'b1; + end + + 1: + begin + for ( i = 0 ; i < PF1_NUM_VF ; i++ ) + pf1_flrst_n[i+1] <= ( flr_rcvd_vf_num == i ) ? 1'b0 : + 1'b1; + end + + endcase + end + end +end + +always_ff @ ( posedge clk_1x ) +begin + if ( !rst_n_1x ) + begin + vf_fsm_reset <= RESET_HOLD; + vf_reset_pulse_width <= '0; + vf_softreset <= 1'b1; + end + else + begin + vf_fsm_reset <= vf_fsm_reset_next; + vf_reset_pulse_width <= vf_reset_pulse_width_next; + vf_softreset <= vf_softreset_next; + end +end + +always_comb +begin + vf_fsm_reset_next = vf_fsm_reset; + vf_reset_pulse_width_next = vf_reset_pulse_width; + vf_softreset_next = vf_softreset; + + unique case ( 1'b1 ) + + vf_fsm_reset[RESET_HOLD_BIT] : + begin + if ( vf_reset_pulse_width[$clog2(SYNC_RESET_MIN_WIDTH)] ) + begin + vf_fsm_reset_next = RESET_DEACT; + end + else + begin + vf_reset_pulse_width_next = vf_reset_pulse_width + 1'b1; + end + end + + vf_fsm_reset[RESET_DEACT_BIT] : + begin + vf_softreset_next = 1'b0; + + if ( !flr_active_vf ) + vf_fsm_reset_next = RESET_CLEAR; + end + + vf_fsm_reset[RESET_CLEAR_BIT] : + begin + if ( flr_active_vf ) + vf_fsm_reset_next = RESET_SET; + end + + vf_fsm_reset[RESET_SET_BIT] : + begin + vf_softreset_next = 1'b1; + vf_reset_pulse_width_next = '0; + + // Stall logic to not terminate multi-CL write? + vf_fsm_reset_next = RESET_HOLD; + end + + endcase +end + +always_ff @ ( posedge clk_1x ) +begin + if ( !rst_n_1x ) + begin + pf0_fsm_reset <= RESET_HOLD; + pf0_reset_pulse_width <= '0; + pf0_softreset <= 1'b1; + end + else + begin + pf0_fsm_reset <= pf0_fsm_reset_next; + pf0_reset_pulse_width <= pf0_reset_pulse_width_next; + pf0_softreset <= pf0_softreset_next; + end +end + +always_comb +begin + pf0_fsm_reset_next = pf0_fsm_reset; + pf0_reset_pulse_width_next = pf0_reset_pulse_width; + pf0_softreset_next = pf0_softreset; + + unique case ( 1'b1 ) + + pf0_fsm_reset[RESET_HOLD_BIT] : + begin + if ( pf0_reset_pulse_width[$clog2(SYNC_RESET_MIN_WIDTH)] ) + begin + pf0_fsm_reset_next = RESET_DEACT; + end + else + begin + pf0_reset_pulse_width_next = pf0_reset_pulse_width + 1'b1; + end + end + + pf0_fsm_reset[RESET_DEACT_BIT] : + begin + pf0_softreset_next = 1'b0; + + if ( !flr_active_pf0 ) + pf0_fsm_reset_next = RESET_CLEAR; + end + + pf0_fsm_reset[RESET_CLEAR_BIT] : + begin + if ( flr_active_pf0 ) + pf0_fsm_reset_next = RESET_SET; + end + + pf0_fsm_reset[RESET_SET_BIT] : + begin + pf0_softreset_next = 1'b1; + pf0_reset_pulse_width_next = '0; + + // Stall logic to not terminate multi-CL write? + pf0_fsm_reset_next = RESET_HOLD; + end + + endcase +end + +always_ff @ ( posedge clk_1x ) +begin + if ( !rst_n_1x ) + begin + pf1_fsm_reset <= RESET_HOLD; + pf1_reset_pulse_width <= '0; + pf1_softreset <= 1'b1; + end + else + begin + pf1_fsm_reset <= pf1_fsm_reset_next; + pf1_reset_pulse_width <= pf1_reset_pulse_width_next; + pf1_softreset <= pf1_softreset_next; + end +end + +always_comb +begin + pf1_fsm_reset_next = pf1_fsm_reset; + pf1_reset_pulse_width_next = pf1_reset_pulse_width; + pf1_softreset_next = pf1_softreset; + + unique case ( 1'b1 ) + + pf1_fsm_reset[RESET_HOLD_BIT] : + begin + if ( pf1_reset_pulse_width[$clog2(SYNC_RESET_MIN_WIDTH)] ) + begin + pf1_fsm_reset_next = RESET_DEACT; + end + else + begin + pf1_reset_pulse_width_next = pf1_reset_pulse_width + 1'b1; + end + end + + pf1_fsm_reset[RESET_DEACT_BIT] : + begin + pf1_softreset_next = 1'b0; + + if ( !flr_active_pf1 ) + pf1_fsm_reset_next = RESET_CLEAR; + end + + pf1_fsm_reset[RESET_CLEAR_BIT] : + begin + if ( flr_active_pf1 ) + pf1_fsm_reset_next = RESET_SET; + end + + pf1_fsm_reset[RESET_SET_BIT] : + begin + pf1_softreset_next = 1'b1; + pf1_reset_pulse_width_next = '0; + + // Stall logic to not terminate multi-CL write? + pf1_fsm_reset_next = RESET_HOLD; + end + + endcase +end + +// FIM power good reset synchronous to clk_1x +fim_resync #( + .SYNC_CHAIN_LENGTH(3), + .WIDTH(1), + .INIT_VALUE(0), + .NO_CUT(1) +) pwr_good_clk_n_resync ( + .clk (clk_1x), + .reset (~pll_locked_w | ninit_done), + .d (1'b1), + .q (pwr_good_clk_n) +); + +endmodule diff --git a/syn/README b/syn/README new file mode 100644 index 0000000..f5b171d --- /dev/null +++ b/syn/README @@ -0,0 +1,27 @@ +Folder Structure: + +├── README.md // This is current file +├── scripts +│   └── build_var_setup.sh // This script is to setup env variables for OFS-D5005 build +├── setup // Build setup files for OFS-D5005 +│   ├── README.md // Refer the README in this section for details +│   ├── ... // various setup files +├── syn_top // D5005 Quartus build area with necessary files for build +│   ├── d5005.ipregen.rpt // IP regeneration report states the output of IP upgrade +│   ├── d5005.qpf // Quartus Project File (qpf) mentions about Quartus version and project revision +│   ├── d5005.qsf // Quartus Settings File (qsf) lists current project settings and entity level assignments +│   ├── d5005.stp // Signal Tap file included in the d5005.qsf. This file can be modified as required +│   ├── fme_id.mif // the fme id hex value is stored in a mif file format +│   ├── iofs_pr_afu.qsf // PR AFU qsf file +│   ├── iofs_pr_afu_sources.tcl // AFU source file list +│   ├── ofs_partial_reconfig // D5005 PR scripts and setp up files +│   │   ├── ... +│   ├── pr_debug.stp   // Signal Tap file for PR debug + + +NOTE - To set the number of DDR channelson d5005, the following files need to be updated: + - $(OFS_ROOTDIR)/src/fims/d5005/afu/pf_vf_mux_top/mux/top_cfg_pkg.sv + - parameter NUM_MEM_CH = 4; + - update NUM_MEM_CH with 2/4 based on number of DDR channels. + + diff --git a/syn/scripts/build_var_setup.sh b/syn/scripts/build_var_setup.sh new file mode 100755 index 0000000..938b017 --- /dev/null +++ b/syn/scripts/build_var_setup.sh @@ -0,0 +1,322 @@ +#!/bin/bash +# Copyright (C) 2021-2023 Intel Corporation +# SPDX-License-Identifier: MIT + +# This script is to setup env variables for OFS-D5005 build +# +#cd ${OFS_ROOTDIR}/src/pd_qsys/d5005/fabric +#sh gen_fabrics.sh +#cd ${OFS_ROOTDIR} + +# enforce sourcing this script +# Note that this section needs to be the first thing this script does +if [ "${BASH_SOURCE[0]}" -ef "$0" ]; then + echo "This script sets up env variables used by the build scripts" + echo "Script must be sourced" + echo "Usage: source ${BASH_SOURCE[0]}" + exit 1 +fi + +# Sourcing this script again should display the environment settings +if [ ! -z ${BUILD_VAR_SETUP_COMPLETE} ]; then + # print env variables only if the variable setup is completed (didn't error out on the first call) + if [ ${BUILD_VAR_SETUP_COMPLETE} == "1" ]; then + ################################################ + ######### Variable output section + ######### don't need to update this section + ######### unless you want to add/remove variables + ######### to output + echo"" + echo "**********************************" + echo "********* ENV SETUP **************" + echo "" + echo "FIM Project:" + echo " OFS_PROJECT = ${OFS_PROJECT}" + echo " OFS_FIM = ${OFS_FIM}" + echo " OFS_BOARD = ${OFS_BOARD}" + echo " Q_PROJECT = ${Q_PROJECT}" + echo " Q_REVISION = ${Q_REVISION}" + echo " Fitter SEED = ${SEED}" + echo "FME id" + echo " BITSTREAM_ID = ${BITSTREAM_ID}" + echo " BITSTREAM_MD = ${BITSTREAM_MD}" + echo "Flow:" + echo " ENA_CREATE_WORK_DIR = ${ENA_CREATE_WORK_DIR}" + echo " ENA_OPAE_SDK_SETUP_FOR_FIM = ${ENA_OPAE_SDK_SETUP_FOR_FIM}" + echo " ENA_PRE_COMPILE_SCRIPT = ${ENA_PRE_COMPILE_SCRIPT}" + echo " ENA_SETUP_IP_LIB_SCRIPT = ${ENA_SETUP_IP_LIB_SCRIPT}" + echo " ENA_FIM_COMPILE = ${ENA_FIM_COMPILE}" + echo " ENA_PR_SETUP = ${ENA_PR_SETUP}" + echo " ENA_FLASH = ${ENA_FLASH}" + echo " ENA_PR_BUILD_TEMPLATE_GEN = ${ENA_PR_BUILD_TEMPLATE_GEN}" + if [ ! -z ${PR_COMPILE} ]; then + if [ ${PR_COMPILE} == "1" ]; then + echo "PR project:" + echo " ENA_OPAE_SDK_SETUP_FOR_PR = ${ENA_OPAE_SDK_SETUP_FOR_PR}" + echo " ENA_PR_COMPILE = ${ENA_PR_COMPILE}" + echo " ENA_GBS_GENERATION = ${ENA_GBS_GENERATION}" + fi + fi + echo "OPAE_SDK:" + echo " OPAE_SDK_REPO = ${OPAE_SDK_REPO}" + echo " OPAE_SDK_REPO_BRANCH = ${OPAE_SDK_REPO_BRANCH}" + echo "" + + echo "File pointers:" + echo " WORK_SYN_TOP_PATH = ${WORK_SYN_TOP_PATH}" + echo " CREATE_WORK_DIR_SH_FILE = ${CREATE_WORK_DIR_SH_FILE}" + echo " FME_ID_MIF_FILE = ${FME_ID_MIF_FILE}" + + echo " WORK_FME_ID_MIF_FILE = ${WORK_FME_ID_MIF_FILE}" + echo " REPORT_TIMING_TCL_FILE = ${REPORT_TIMING_TCL_FILE}" + echo " WORK_BUILD_FLASH_SH_FILE = ${WORK_BUILD_FLASH_SH_FILE}" + + echo " WORK_PRE_COMPILE_SCRIPT_SH_FILE = ${WORK_PRE_COMPILE_SCRIPT_SH_FILE}" + + echo " SETUP_OPAE_SDK_SH_FILE = ${SETUP_OPAE_SDK_SH_FILE}" + + + + # exit as this will be the 2nd pass to just display the variables + exit 0 + fi + +fi + + +# check for required env variables +error=0 +if [ -z ${OFS_ROOTDIR} ]; then + echo "Error: OFS_ROOTDIR not set" + error=1 +fi + +if [ -z ${WORK_DIR} ]; then + echo "Error: WORK_DIR not set" + error=1 +fi + +if [ "${error}" != "0" ]; then + exit 1 +fi +unset error + +###################################################### +###### Project variable section +###### edit variables to suit your project + +## for FME ID ROM MIF generation +# HSSID - 2: Ethernet + PCIe, 1: PCIe only +# VER_DEBUG - 1: debug version 0: normal version + +# bitstream md +RESERVED_BITSTREAM_MD_VAL="000000000" +YEAR=$(date +"%y") +MONTH=$(date +"%m") +DAY=$(date +"%d") + +# bitstream id +VER_DEBUG="0" +VER_MAJOR="4" +VER_MINOR="0" +VER_PATCH="1" +RESERVED_BITSTREAM_ID_VAL="000" +HSSI_ID="2" + +# bitstream info +RESERVED_FIM_VARIANT_REVISION_VAL="00000000" +FIM_VARIANT_REVISION="00000001" + +if [ -z ${OFS_BUILD_NUMBER} ]; then + # use short git commit id for build number + # can also use a number for OFS_BUILD_NUMBER < 8 digits long + # if it's a number, auto zero extend is done below (in derived section) + OFS_BUILD_NUMBER="$(git -C "$OFS_ROOTDIR" rev-parse --short=8 HEAD | cut -c1-8)" +fi + +if [ -z ${COPY_WORK} ]; then + # set COPY_WORK default to '0' + # 0: symlink files, 1: copy files to work directory + COPY_WORK="0" +fi + +## ofs_project, fim, board are used to traverse directory +## e.g. ${WORK_DIR}/syn/${OFS_PROJECT}/${OFS_FIM}/${OFS_BOARD}/syn_top +# use "." or "" for empty +# for D5005: +export OFS_PROJECT="d5005" +export OFS_FIM="." +export OFS_BOARD="." +# for agilex ac on devkit: +#export OFS_PROJECT="ofs_ac" +#export OFS_FIM="base" +#export OFS_BOARD="agilex_f_dk" + +# for Quartus scripts +# D5005 +export Q_PROJECT="d5005" +export Q_REVISION="d5005" +# AC +#export Q_PROJECT="ofs_top" +#export Q_REVISION="ofs_top" + +# repo location/branch variables used by SETUP_OPAE_SDK_SH_FILE +# These variables will override the defaults in that script +#export OPAE_SDK_REPO="https://github.com/OFS/opae-sdk" +#export OPAE_SDK_REPO_BRANCH="master" + + +#### PR BUILD variables ##### +# only set env variables only if it's not set +# allows user to pass in revisions/parittion name variables +# D5005 +if [ -z ${Q_PR_REVISION} ]; then + export Q_PR_REVISION="iofs_pr_afu" +fi +if [ -z ${Q_PR_PARTITION_NAME} ]; then + export Q_PR_PARTITION_NAME="persona1" +fi + + +###################################### +### FIM Build flow + +# 1: enable +# 0: disable +# commenting or removing variable is the same as disable + +# create work directory (this always need to be enabled, here only for custom build scripts) +export ENA_CREATE_WORK_DIR="1" +# setup OPAE SDK (for tools such as PACSign) +export ENA_OPAE_SDK_SETUP_FOR_FIM="1" +# optional pre-compile script +export ENA_PRE_COMPILE_SCRIPT="0" +#FUTURE_IMPROVEMENT: setup IP_LIB script may be temporary (only for ofs_ac project) +export ENA_SETUP_IP_LIB_SCRIPT="1" +# Quartus compilation of FIM +export ENA_FIM_COMPILE="1" +# enable PR post compilation tasks +export ENA_PR_SETUP="1" +# create configuration flash image +export ENA_FLASH="1" +# enable creation of out-of-tree PR build environment +export ENA_PR_BUILD_TEMPLATE_GEN="1" + + + +###################################### +### PR Build Flow + +# 1: enable +# 0: disable +# commenting or removing variable is the same as disable +# setup OPAE SDK (for tools such as 'packager' for GBS creation and PACSign) +export ENA_OPAE_SDK_SETUP_FOR_PR="1" +export ENA_PR_COMPILE="1" +export ENA_GBS_GENERATION="1" + + +################################################### +##### Script path +##### don't need to edit this unless using custom version of scripts +##### naming convention: +##### - directory paths variables should end with "_PATH" +##### - files variables should end with "__FILE" e.g. "_SH_FILE" +##### - files pointers to files in the work directory should begin with "WORK_" + + +export SYN_TOP_PATH=${OFS_ROOTDIR}/syn/syn_top +# WORK_SYN_TOP_PATH is used to copy qsf and other files to +export WORK_SYN_TOP_PATH=${WORK_DIR}/syn/syn_top + +# local path pointers +SYN_COMMON_SCRIPTS_PATH=${OFS_ROOTDIR}/ofs-common/scripts/common/syn +############################################### +##### Script/file pointer + +export CREATE_WORK_DIR_SH_FILE=${SYN_COMMON_SCRIPTS_PATH}/create_work_dir.sh +export FME_ID_MIF_FILE=${OFS_ROOTDIR}/ofs-common/src/common/fme_id_rom/fme_id.mif +export PMCI_NIOS_HEX_FILE=${OFS_ROOTDIR}/${OFS_PROJECT}/ipss/pmci/pmci_ss_nios_fw.hex +# FUTURE_IMPROVEMENT: D5005 points to fme_id_mif in the syn_top path (check to see if this can be removed) +export WORK_FME_ID_MIF_FILE=${WORK_SYN_TOP_PATH}/fme_id.mif +export REPORT_TIMING_TCL_FILE=${SYN_COMMON_SCRIPTS_PATH}/report_timing.tcl +export WORK_BUILD_FLASH_SH_FILE=${WORK_DIR}/syn/syn_top/build_flash/build_flash.sh +export WORK_PRE_COMPILE_SCRIPT_SH_FILE=${WORK_DIR}/ofs-common/scripts/common/syn/pre_compile_script.sh + + +# for opae-sdk repo builds (note that this matches the defaults in setup_opae-sdk.sh) +# commenting most this section out as the defaults have the same settings +# uncomment and modify if the file/directory lcoations change +export SETUP_OPAE_SDK_SH_FILE="${SYN_COMMON_SCRIPTS_PATH}/setup_opae_sdk.sh" + +#### PR file pointers **** +export WORK_PR_JSON_FILE="${WORK_SYN_TOP_PATH}/${Q_PR_REVISION}.json" +export WORK_PR_RBF_FILE="${WORK_SYN_TOP_PATH}/output_files/${Q_PR_REVISION}.${Q_PR_PARTITION_NAME}.rbf" +export WORK_PR_GBS_FILE="${WORK_SYN_TOP_PATH}/output_files/${Q_PR_REVISION}.${Q_PR_PARTITION_NAME}.gbs" +export WORK_PR_PACSIGN_GBS_FILE="${WORK_SYN_TOP_PATH}/output_files/${Q_PR_REVISION}.${Q_PR_PARTITION_NAME}_unsigned.gbs" + +#### Platform Interface Manager configuration +export PIM_PLATFORM_NAME=ofs_d5005 +export PIM_INI_FILE=${OFS_ROOTDIR}/src/top/${PIM_PLATFORM_NAME}.ini +export PIM_DEFAULT_AFU=${OFS_ROOTDIR}/src/port_gasket/afu_main_pim/std_exerciser/filelist.txt + + +#FUTURE_IMPROVEMENT: add capabilities to specify project only work directory so create_work_dir.sh +# will only sync over the pertnant files to . +# currently create_work_dir.sh grabs the whole ofs-dev repo including other projects +# will need to modify create_work_dir.sh to consume the project only source, IPs, and syn (probably verification also) + + +#################################################### +######## Derived variable section +######## * Don't need to edit this section * +######## unless you want a different +######## variable format + +# SEED may be set by the user. if so, use that SEED as that will be changed in qsf of the associated WORK_DIR +# else, get the default SEED value in the qsf file +if [ -z ${SEED} ]; then + export SEED=$(sed -r '/set_global_assignment.*SEED/ ! d; s/.*[[:space:]]+([0-9]+)[[:space:]]*$/\1/; q' ${SYN_TOP_PATH}/${Q_PROJECT}.qsf) + + if [ "${SEED}" == "" ]; then + echo "Error: cannot get SEED from ${SYN_TOP_PATH}/${Q_PROJECT}.qsf" + exit 1 + fi +fi + +# only get the lowest character as the register only has allocation for 1 char +SEED_LSD=${SEED: -1} + +# The build number field is expected to be 8 characters, so it should be left +# padded with zeros in case it is too short. +BUILD_NUMBER=$(printf "%8s" "${OFS_BUILD_NUMBER}" | tr ' ' 0) + +# these variables used by update_fme_ifc_id.py script +export BITSTREAM_MD=${RESERVED_BITSTREAM_MD_VAL}${YEAR}${MONTH}${DAY}${SEED_LSD} +export BITSTREAM_ID=${VER_DEBUG}${VER_MAJOR}${VER_MINOR}${VER_PATCH}${RESERVED_BITSTREAM_ID_VAL}${HSSI_ID}${BUILD_NUMBER} +export BITSTREAM_INFO=${RESERVED_FIM_VARIANT_REVISION_VAL}${FIM_VARIANT_REVISION} + + + +# test len of bitstream ID and MD to ensure it's under 16. need to match with register size in the FIM +# print index to help identify format error +if [ "${#BITSTREAM_ID}" != "16" ]; then + echo "Error: BITSTREAM_ID must be 16 characters long, but is ${#BITSTREAM_ID}" + echo " Index = 0123456789012345" + echo " BITSTREAM_ID = $BITSTREAM_ID" + exit 1 +fi + +if [ "${#BITSTREAM_MD}" != "16" ]; then + echo "Error: BITSTREAM_MD must be 16 characters long, but is ${#BITSTREAM_MD}" + echo " Index = 0123456789012345" + echo " BITSTREAM_MD = $BITSTREAM_MD" + exit 1 +fi + + + +# This variable is set when there are no errors +# indicates that the build variables are setup correctly and build can be started +export BUILD_VAR_SETUP_COMPLETE="1" + diff --git a/syn/setup/README b/syn/setup/README new file mode 100644 index 0000000..65bcf5e --- /dev/null +++ b/syn/setup/README @@ -0,0 +1,8 @@ +Tcl scrips here import RTL and other IP into a FIM build or into an AFU partial +reconfiguration (PR) build. The majority of the scripts are used only during +a FIM base build. Scripts with the name *afu_if* import interfaces and packages +describing data structures passed to AFUs and are used during PR synthesis +as well. + +Only sources that describe an AFU interface and are required for PR builds +should be listed in *afu_if*.tcl files. diff --git a/syn/setup/afu_design_files.tcl b/syn/setup/afu_design_files.tcl new file mode 100644 index 0000000..8d147e0 --- /dev/null +++ b/syn/setup/afu_design_files.tcl @@ -0,0 +1,44 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +#-------------------- +# AFU modules +#-------------------- +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/src/includes/ofs_pcie_ss_plat_cfg_pkg.sv + +#-------------------- +# AFU Top +#-------------------- +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/src/afu_top/afu_top.sv + + +#-------------------- +# Common sources +#-------------------- +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/ofs-common/src/fpga_family/stratix10/afu_design_files.tcl +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/ofs-common/src/common/afu_design_files.tcl + + +#-------------------- +# Port Gasket modules +#-------------------- +# SDC +set_global_assignment -name SDC_FILE $::env(BUILD_ROOT_REL)/syn/setup/user_clock.sdc +# Synthetic timing constraints on user clock to achieve user-defined frequencies. +# *** This must follow the user clock IP. *** +set_global_assignment -name SDC_FILE $::env(BUILD_ROOT_REL)/syn/setup/setup_user_clock_for_pr.sdc + +set_global_assignment -name SDC_FILE $::env(BUILD_ROOT_REL)/ofs-common/src/common/he_hssi/par/he_hssi.sdc + +#-------------------- +# MSIX modules +#-------------------- +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/src/interrupt/pcie_mux_top.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/src/interrupt/fme_msix_table.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/src/interrupt/msix_filter.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/src/interrupt/msix_fme_bridge.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/src/interrupt/msix_pba_update.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/src/interrupt/msix_user_irq.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/src/interrupt/msix_wrapper.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/src/interrupt/msix_top.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/src/interrupt/msix_csr.sv diff --git a/syn/setup/afu_if_design_files.tcl b/syn/setup/afu_if_design_files.tcl new file mode 100644 index 0000000..d005d05 --- /dev/null +++ b/syn/setup/afu_if_design_files.tcl @@ -0,0 +1,25 @@ +# Copyright 2021 Intel Corporation +# SPDX-License-Identifier: MIT + + +## +## Load the subset of interfaces and modules required for AFUs inside the port +## gasket. This is the minimal set of sources loaded when generating the +## out-of-tree PR build environment. +## + +# Include files +set_global_assignment -name SEARCH_PATH $::env(BUILD_ROOT_REL)/src/includes/ + +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/src/includes/ofs_fim_cfg_pkg.sv + +# Common interface files +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/ofs-common/src/fpga_family/stratix10/afu_if_design_files.tcl +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/ofs-common/src/common/ofs_common_if_design_files.tcl + +# Signal tap, available in the PR region +set_global_assignment -name SDC_FILE $::env(BUILD_ROOT_REL)/syn/setup/signaltap_clock_crossing.sdc + +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/syn/setup/eth_afu_if_design_files.tcl +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/syn/setup/emif_afu_if_design_files.tcl +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/syn/setup/pcie_afu_if_design_files.tcl diff --git a/syn/setup/apf_design_files.tcl b/syn/setup/apf_design_files.tcl new file mode 100644 index 0000000..22759f7 --- /dev/null +++ b/syn/setup/apf_design_files.tcl @@ -0,0 +1,31 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# design files +#-------------------- + +#set_global_assignment -name SYSTEMVERILOG_FILE fabric/rtl/s10/apf.sv + +#-------------------- +# IPs +#-------------------- +set_global_assignment -name QSYS_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/apf.qsys + +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/apf/apf_clock_bridge.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/apf/apf_reset_bridge.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/apf/apf_bpf_mst.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/apf/apf_bpf_slv.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/apf/apf_st2mm_mst.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/apf/apf_st2mm_slv.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/apf/apf_pgsk_slv.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/apf/apf_achk_slv.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/apf/apf_rsv_b_slv.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/apf/apf_rsv_c_slv.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/apf/apf_rsv_d_slv.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/apf/apf_rsv_e_slv.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/apf/apf_rsv_f_slv.ip +#-------------------- +# SDC +#-------------------- + + diff --git a/syn/setup/bpf_design_files.tcl b/syn/setup/bpf_design_files.tcl new file mode 100644 index 0000000..f776c75 --- /dev/null +++ b/syn/setup/bpf_design_files.tcl @@ -0,0 +1,27 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# design files +#-------------------- + +#set_global_assignment -name SYSTEMVERILOG_FILE fabric/rtl/s10/apf.sv + + +#-------------------- +# IPs +#-------------------- +set_global_assignment -name QSYS_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/bpf.qsys + +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/bpf/bpf_clock_bridge.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/bpf/bpf_reset_bridge.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/bpf/bpf_apf_mst.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/bpf/bpf_apf_slv.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/bpf/bpf_fme_mst.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/bpf/bpf_fme_slv.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/bpf/bpf_pmci_slv.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/bpf/bpf_pcie_slv.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/bpf/bpf_emif_slv.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/bpf/bpf_hssi_slv.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/bpf/bpf_rsv_5_slv.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/bpf/bpf_rsv_6_slv.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/fabric/ip/bpf/bpf_rsv_7_slv.ip diff --git a/syn/setup/dcfifo.sdc b/syn/setup/dcfifo.sdc new file mode 100644 index 0000000..f2c67fb --- /dev/null +++ b/syn/setup/dcfifo.sdc @@ -0,0 +1,77 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# constraints for DCFIFO sdc +# +# top-level sdc +# convention for module sdc apply_sdc_ +# +proc apply_sdc_dcfifo {hier_path} { +# gray_rdptr +apply_sdc_dcfifo_rdptr $hier_path +# gray_wrptr +apply_sdc_dcfifo_wrptr $hier_path +} +# +# common constraint setting proc +# +proc apply_sdc_dcfifo_for_ptrs {from_node_list to_node_list} { +# control skew for bits +set_max_skew -from $from_node_list -to $to_node_list -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.8 +# path delay (exception for net delay) +if { ![string equal "quartus_syn" $::TimeQuestInfo(nameofexecutable)] } { +set_net_delay -from $from_node_list -to $to_node_list -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 +} +#relax setup and hold calculation +set_max_delay -from $from_node_list -to $to_node_list 100 +set_min_delay -from $from_node_list -to $to_node_list -100 +} +# +# mstable propgation delay +# +proc apply_sdc_dcfifo_mstable_delay {from_node_list to_node_list} { +# mstable delay +if { ![string equal "quartus_syn" $::TimeQuestInfo(nameofexecutable)] } { +set_net_delay -from $from_node_list -to $to_node_list -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 +} +} +# +# rdptr constraints +# +proc apply_sdc_dcfifo_rdptr {hier_path} { +# get from and to list +set from_node_list [get_keepers $hier_path|dcfifo_component|auto_generated|*rdptr_g*] +set to_node_list [get_keepers $hier_path|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*] +apply_sdc_dcfifo_for_ptrs $from_node_list $to_node_list +# mstable +set from_node_mstable_list [get_keepers $hier_path|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*] +set to_node_mstable_list [get_keepers $hier_path|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*] +apply_sdc_dcfifo_mstable_delay $from_node_mstable_list $to_node_mstable_list +} +# +# wrptr constraints +# +proc apply_sdc_dcfifo_wrptr {hier_path} { +# control skew for bits +set from_node_list [get_keepers $hier_path|dcfifo_component|auto_generated|delayed_wrptr_g*] +set to_node_list [get_keepers $hier_path|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*] +apply_sdc_dcfifo_for_ptrs $from_node_list $to_node_list +# mstable +set from_node_mstable_list [get_keepers $hier_path|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*] +set to_node_mstable_list [get_keepers $hier_path|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*] +apply_sdc_dcfifo_mstable_delay $from_node_mstable_list $to_node_mstable_list +} + +proc apply_sdc_pre_dcfifo {entity_name} { + +set inst_list [get_entity_instances $entity_name] + +foreach each_inst $inst_list { + + apply_sdc_dcfifo ${each_inst} + + } +} + +## Apply the constraints +apply_sdc_pre_dcfifo dcfifo diff --git a/syn/setup/design_files_d5005.tcl b/syn/setup/design_files_d5005.tcl new file mode 100644 index 0000000..9ec4cf0 --- /dev/null +++ b/syn/setup/design_files_d5005.tcl @@ -0,0 +1,58 @@ +# Copyright (C) 2022-2023 Intel Corporation +# SPDX-License-Identifier: MIT + +############################################################################################ +# OFS IP database +############################################################################################ + +# Load this first. The script manages a database of IP from which parameters will +# be extracted before synthesis. The parameters are written to header files in +# ofs_ip_cfg_db/. +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE "$::env(BUILD_ROOT_REL)/ofs-common/scripts/common/syn/ip_get_cfg/ofs_ip_cfg_db.tcl" + +# Add the constructed IP database to the search path. It will be populated +# by a hook at the end of ipgenerate +set_global_assignment -name SEARCH_PATH "ofs_ip_cfg_db" + + +## design files and script + +### design files_list +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/syn/setup/afu_if_design_files.tcl +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/syn/setup/eth_afu_if_design_files.tcl +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/syn/setup/emif_afu_if_design_files.tcl +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/syn/setup/pcie_afu_if_design_files.tcl +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/syn/setup/pmci_design_files.tcl +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/ofs-common/src/common/ofs_common_design_files.tcl +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/ofs-common/src/fpga_family/stratix10/common_design_files.tcl +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/syn/setup/pcie_design_files.tcl +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/syn/setup/pcie_location.tcl +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/syn/setup/eth_design_files.tcl +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/syn/setup/eth_location.tcl +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/syn/setup/spi_design_files.tcl +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/syn/setup/spi_location.tcl +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/syn/setup/afu_design_files.tcl +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/syn/setup/apf_design_files.tcl +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/syn/setup/bpf_design_files.tcl +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/syn/setup/emif_design_files.tcl +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/syn/setup/emif_x8_location.tcl +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/ofs-common/src/fpga_family/stratix10/afu_main.tcl + +### Partial Reconfiguration and floorplan +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/syn/setup/sr_logic_lock_region.tcl + +### design files +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/src/top/rst_ctrl.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/src/top/iofs_top.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/src/afu_top/mux/top_cfg_pkg.sv +set_global_assignment -name SDC_FILE $::env(BUILD_ROOT_REL)/syn/setup/top.sdc + +# Generate timing reports during quartus_sta +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT $::env(BUILD_ROOT_REL)/ofs-common/scripts/common/syn/report_timing.tcl + +# Generate PR interface ID +set_global_assignment -name MISC_FILE $::env(BUILD_ROOT_REL)/ofs-common/scripts/common/syn/update_fme_ifc_id.py + +# Post-process the project between modules. For d5005 there is no platform-specific script. +# Invoke the platform-independent script directly. +set_global_assignment -name POST_MODULE_SCRIPT_FILE "quartus_sh:$::env(BUILD_ROOT_REL)/ofs-common/scripts/common/syn/ofs_post_module_script_fim.tcl" diff --git a/syn/setup/emif_afu_if_design_files.tcl b/syn/setup/emif_afu_if_design_files.tcl new file mode 100644 index 0000000..bdc6e20 --- /dev/null +++ b/syn/setup/emif_afu_if_design_files.tcl @@ -0,0 +1,10 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# +# EMIF interfaces passed to AFUs. These files are used by both FIM and PR builds. +# + +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/mem/includes/ofs_fim_emif_cfg_pkg.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/mem/includes/ofs_fim_emif_if.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ofs-common/src/common/includes/emif_avmm_if.sv diff --git a/syn/setup/emif_all_x8.tcl b/syn/setup/emif_all_x8.tcl new file mode 100644 index 0000000..e949cc1 --- /dev/null +++ b/syn/setup/emif_all_x8.tcl @@ -0,0 +1,622 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# Description +#----------------------------------------------------------------------------- +# +# DDR4 pin and location assignments +# +#----------------------------------------------------------------------------- + +#======================================================= +# DDR4 CH0 (Lower 3) - A/C +set_location_assignment PIN_AP10 -to ddr4_mem[2].ck +set_location_assignment PIN_AP11 -to ddr4_mem[2].ck_n +set_location_assignment PIN_AT4 -to ddr4_mem[2].a[0] +set_location_assignment PIN_AT5 -to ddr4_mem[2].a[1] +set_location_assignment PIN_AR2 -to ddr4_mem[2].a[2] +set_location_assignment PIN_AR1 -to ddr4_mem[2].a[3] +set_location_assignment PIN_AR3 -to ddr4_mem[2].a[4] +set_location_assignment PIN_AR4 -to ddr4_mem[2].a[5] +set_location_assignment PIN_AP1 -to ddr4_mem[2].a[6] +set_location_assignment PIN_AN1 -to ddr4_mem[2].a[7] +set_location_assignment PIN_AP4 -to ddr4_mem[2].a[8] +set_location_assignment PIN_AP3 -to ddr4_mem[2].a[9] +set_location_assignment PIN_AT2 -to ddr4_mem[2].a[10] +set_location_assignment PIN_AT1 -to ddr4_mem[2].a[11] +set_location_assignment PIN_AN2 -to ddr4_mem[2].a[12] +set_location_assignment PIN_AN5 -to ddr4_mem[2].a[13] +set_location_assignment PIN_AM5 -to ddr4_mem[2].a[14] +set_location_assignment PIN_AM2 -to ddr4_mem[2].a[15] +set_location_assignment PIN_AM3 -to ddr4_mem[2].a[16] +set_location_assignment PIN_AM4 -to ddr4_mem[2].a[17] +set_location_assignment PIN_AR7 -to ddr4_mem[2].act_n +set_location_assignment PIN_AL1 -to ddr4_mem[2].ba[1] +set_location_assignment PIN_AL4 -to ddr4_mem[2].ba[0] +set_location_assignment PIN_AR9 -to ddr4_mem[2].bg[1] +set_location_assignment PIN_AL2 -to ddr4_mem[2].bg[0] +set_location_assignment PIN_AT6 -to ddr4_mem[2].cke +set_location_assignment PIN_AR8 -to ddr4_mem[2].cs_n +set_location_assignment PIN_AP8 -to ddr4_mem[2].odt +set_location_assignment PIN_AP9 -to ddr4_mem[2].reset_n +set_location_assignment PIN_AP5 -to ddr4_mem[2].par +set_location_assignment PIN_AP6 -to ddr4_mem[2].alert_n +set_location_assignment PIN_AN3 -to ddr4_mem[2].oct_rzqin +set_location_assignment PIN_AL5 -to ddr4_mem[2].ref_clk + +# DDR4 CH0 - DQS0 +set_location_assignment PIN_AH5 -to ddr4_mem[2].dqs[0] +set_location_assignment PIN_AG5 -to ddr4_mem[2].dqs_n[0] +set_location_assignment PIN_AG4 -to ddr4_mem[2].dbi_n[0] +set_location_assignment PIN_AF1 -to ddr4_mem[2].dq[0] +set_location_assignment PIN_AH6 -to ddr4_mem[2].dq[1] +set_location_assignment PIN_AH3 -to ddr4_mem[2].dq[2] +set_location_assignment PIN_AG2 -to ddr4_mem[2].dq[3] +set_location_assignment PIN_AF2 -to ddr4_mem[2].dq[4] +set_location_assignment PIN_AH7 -to ddr4_mem[2].dq[5] +set_location_assignment PIN_AH2 -to ddr4_mem[2].dq[6] +set_location_assignment PIN_AG3 -to ddr4_mem[2].dq[7] + +# DDR4 CH0 - DQS1 +set_location_assignment PIN_AK6 -to ddr4_mem[2].dqs[1] +set_location_assignment PIN_AK7 -to ddr4_mem[2].dqs_n[1] +set_location_assignment PIN_AJ6 -to ddr4_mem[2].dbi_n[1] +set_location_assignment PIN_AK2 -to ddr4_mem[2].dq[8] +set_location_assignment PIN_AJ3 -to ddr4_mem[2].dq[9] +set_location_assignment PIN_AK4 -to ddr4_mem[2].dq[10] +set_location_assignment PIN_AJ4 -to ddr4_mem[2].dq[11] +set_location_assignment PIN_AK1 -to ddr4_mem[2].dq[12] +set_location_assignment PIN_AH1 -to ddr4_mem[2].dq[13] +set_location_assignment PIN_AK3 -to ddr4_mem[2].dq[14] +set_location_assignment PIN_AJ1 -to ddr4_mem[2].dq[15] + +# DDR4 CH0 - DQS2 +set_location_assignment PIN_AL11 -to ddr4_mem[2].dqs[2] +set_location_assignment PIN_AL10 -to ddr4_mem[2].dqs_n[2] +set_location_assignment PIN_AK12 -to ddr4_mem[2].dbi_n[2] +set_location_assignment PIN_AL12 -to ddr4_mem[2].dq[16] +set_location_assignment PIN_AK11 -to ddr4_mem[2].dq[17] +set_location_assignment PIN_AL9 -to ddr4_mem[2].dq[18] +set_location_assignment PIN_AK8 -to ddr4_mem[2].dq[19] +set_location_assignment PIN_AL14 -to ddr4_mem[2].dq[20] +set_location_assignment PIN_AK14 -to ddr4_mem[2].dq[21] +set_location_assignment PIN_AL7 -to ddr4_mem[2].dq[22] +set_location_assignment PIN_AK9 -to ddr4_mem[2].dq[23] + +# DDR4 CH0 - DQS3 +set_location_assignment PIN_AH10 -to ddr4_mem[2].dqs[3] +set_location_assignment PIN_AJ11 -to ddr4_mem[2].dqs_n[3] +set_location_assignment PIN_AH11 -to ddr4_mem[2].dbi_n[3] +set_location_assignment PIN_AH13 -to ddr4_mem[2].dq[24] +set_location_assignment PIN_AG7 -to ddr4_mem[2].dq[25] +set_location_assignment PIN_AJ10 -to ddr4_mem[2].dq[26] +set_location_assignment PIN_AJ8 -to ddr4_mem[2].dq[27] +set_location_assignment PIN_AJ13 -to ddr4_mem[2].dq[28] +set_location_assignment PIN_AG8 -to ddr4_mem[2].dq[29] +set_location_assignment PIN_AJ9 -to ddr4_mem[2].dq[30] +set_location_assignment PIN_AH8 -to ddr4_mem[2].dq[31] + +# DDR4 CH0 - DQS4 +set_location_assignment PIN_AV6 -to ddr4_mem[2].dqs[4] +set_location_assignment PIN_AV5 -to ddr4_mem[2].dqs_n[4] +set_location_assignment PIN_AW1 -to ddr4_mem[2].dbi_n[4] +set_location_assignment PIN_AU4 -to ddr4_mem[2].dq[32] +set_location_assignment PIN_AU5 -to ddr4_mem[2].dq[33] +set_location_assignment PIN_AU3 -to ddr4_mem[2].dq[34] +set_location_assignment PIN_AV2 -to ddr4_mem[2].dq[35] +set_location_assignment PIN_AV7 -to ddr4_mem[2].dq[36] +set_location_assignment PIN_AV8 -to ddr4_mem[2].dq[37] +set_location_assignment PIN_AU2 -to ddr4_mem[2].dq[38] +set_location_assignment PIN_AV3 -to ddr4_mem[2].dq[39] + +# DDR4 CH0 - DQS5 +set_location_assignment PIN_AV10 -to ddr4_mem[2].dqs[5] +set_location_assignment PIN_AU10 -to ddr4_mem[2].dqs_n[5] +set_location_assignment PIN_AU13 -to ddr4_mem[2].dbi_n[5] +set_location_assignment PIN_AY7 -to ddr4_mem[2].dq[40] +set_location_assignment PIN_AW10 -to ddr4_mem[2].dq[41] +set_location_assignment PIN_AV11 -to ddr4_mem[2].dq[42] +set_location_assignment PIN_AW8 -to ddr4_mem[2].dq[43] +set_location_assignment PIN_AY6 -to ddr4_mem[2].dq[44] +set_location_assignment PIN_AW11 -to ddr4_mem[2].dq[45] +set_location_assignment PIN_AV12 -to ddr4_mem[2].dq[46] +set_location_assignment PIN_AW9 -to ddr4_mem[2].dq[47] + +# DDR4 CH0 - DQS6 +set_location_assignment PIN_AT11 -to ddr4_mem[2].dqs[6] +set_location_assignment PIN_AR11 -to ddr4_mem[2].dqs_n[6] +set_location_assignment PIN_AR13 -to ddr4_mem[2].dbi_n[6] +set_location_assignment PIN_AU8 -to ddr4_mem[2].dq[48] +set_location_assignment PIN_AT12 -to ddr4_mem[2].dq[49] +set_location_assignment PIN_AT9 -to ddr4_mem[2].dq[50] +set_location_assignment PIN_AT7 -to ddr4_mem[2].dq[51] +set_location_assignment PIN_AU7 -to ddr4_mem[2].dq[52] +set_location_assignment PIN_AT10 -to ddr4_mem[2].dq[53] +set_location_assignment PIN_AU9 -to ddr4_mem[2].dq[54] +set_location_assignment PIN_AR12 -to ddr4_mem[2].dq[55] + +# DDR4 CH0 - DQS7 +set_location_assignment PIN_BA4 -to ddr4_mem[2].dqs[7] +set_location_assignment PIN_BB4 -to ddr4_mem[2].dqs_n[7] +set_location_assignment PIN_AW5 -to ddr4_mem[2].dbi_n[7] +set_location_assignment PIN_BA2 -to ddr4_mem[2].dq[56] +set_location_assignment PIN_AY4 -to ddr4_mem[2].dq[57] +set_location_assignment PIN_AW3 -to ddr4_mem[2].dq[58] +set_location_assignment PIN_BA5 -to ddr4_mem[2].dq[59] +set_location_assignment PIN_AY2 -to ddr4_mem[2].dq[60] +set_location_assignment PIN_AW4 -to ddr4_mem[2].dq[61] +set_location_assignment PIN_AY3 -to ddr4_mem[2].dq[62] +set_location_assignment PIN_BB5 -to ddr4_mem[2].dq[63] + +# DDR4 CH0 - DQS8 +set_location_assignment PIN_AN10 -to ddr4_mem[2].dqs[8] +set_location_assignment PIN_AN11 -to ddr4_mem[2].dqs_n[8] +set_location_assignment PIN_AM12 -to ddr4_mem[2].dbi_n[8] +set_location_assignment PIN_AM7 -to ddr4_mem[2].dq[64] +set_location_assignment PIN_AM8 -to ddr4_mem[2].dq[65] +set_location_assignment PIN_AN13 -to ddr4_mem[2].dq[66] +set_location_assignment PIN_AN12 -to ddr4_mem[2].dq[67] +set_location_assignment PIN_AN6 -to ddr4_mem[2].dq[68] +set_location_assignment PIN_AN7 -to ddr4_mem[2].dq[69] +set_location_assignment PIN_AM9 -to ddr4_mem[2].dq[70] +set_location_assignment PIN_AM10 -to ddr4_mem[2].dq[71] + +#========================================================= +# DDR4 CH1 (Upper 3) - A/C +set_location_assignment PIN_L6 -to ddr4_mem[3].ck +set_location_assignment PIN_L7 -to ddr4_mem[3].ck_n +set_location_assignment PIN_H1 -to ddr4_mem[3].a[0] +set_location_assignment PIN_J1 -to ddr4_mem[3].a[1] +set_location_assignment PIN_L2 -to ddr4_mem[3].a[2] +set_location_assignment PIN_K2 -to ddr4_mem[3].a[3] +set_location_assignment PIN_F2 -to ddr4_mem[3].a[4] +set_location_assignment PIN_F1 -to ddr4_mem[3].a[5] +set_location_assignment PIN_L1 -to ddr4_mem[3].a[6] +set_location_assignment PIN_K1 -to ddr4_mem[3].a[7] +set_location_assignment PIN_G2 -to ddr4_mem[3].a[8] +set_location_assignment PIN_H2 -to ddr4_mem[3].a[9] +set_location_assignment PIN_K3 -to ddr4_mem[3].a[10] +set_location_assignment PIN_J3 -to ddr4_mem[3].a[11] +set_location_assignment PIN_J4 -to ddr4_mem[3].a[12] +set_location_assignment PIN_K6 -to ddr4_mem[3].a[13] +set_location_assignment PIN_J6 -to ddr4_mem[3].a[14] +set_location_assignment PIN_H3 -to ddr4_mem[3].a[15] +set_location_assignment PIN_G3 -to ddr4_mem[3].a[16] +set_location_assignment PIN_H5 -to ddr4_mem[3].a[17] +set_location_assignment PIN_L5 -to ddr4_mem[3].act_n +set_location_assignment PIN_G4 -to ddr4_mem[3].ba[1] +set_location_assignment PIN_H6 -to ddr4_mem[3].ba[0] +set_location_assignment PIN_M10 -to ddr4_mem[3].bg[1] +set_location_assignment PIN_G5 -to ddr4_mem[3].bg[0] +set_location_assignment PIN_M4 -to ddr4_mem[3].cke +set_location_assignment PIN_M5 -to ddr4_mem[3].cs_n +set_location_assignment PIN_M8 -to ddr4_mem[3].odt +set_location_assignment PIN_M9 -to ddr4_mem[3].reset_n +set_location_assignment PIN_K4 -to ddr4_mem[3].par +set_location_assignment PIN_L4 -to ddr4_mem[3].alert_n +set_location_assignment PIN_J5 -to ddr4_mem[3].oct_rzqin +set_location_assignment PIN_K8 -to ddr4_mem[3].ref_clk + +# DDR4 CH1 - DQS0 +set_location_assignment PIN_G8 -to ddr4_mem[3].dqs[0] +set_location_assignment PIN_G9 -to ddr4_mem[3].dqs_n[0] +set_location_assignment PIN_J13 -to ddr4_mem[3].dbi_n[0] +set_location_assignment PIN_H10 -to ddr4_mem[3].dq[0] +set_location_assignment PIN_H11 -to ddr4_mem[3].dq[1] +set_location_assignment PIN_G10 -to ddr4_mem[3].dq[2] +set_location_assignment PIN_F9 -to ddr4_mem[3].dq[3] +set_location_assignment PIN_J10 -to ddr4_mem[3].dq[4] +set_location_assignment PIN_J11 -to ddr4_mem[3].dq[5] +set_location_assignment PIN_H12 -to ddr4_mem[3].dq[6] +set_location_assignment PIN_F10 -to ddr4_mem[3].dq[7] + +# DDR4 CH1 - DQS1 +set_location_assignment PIN_C7 -to ddr4_mem[3].dqs[1] +set_location_assignment PIN_B7 -to ddr4_mem[3].dqs_n[1] +set_location_assignment PIN_E9 -to ddr4_mem[3].dbi_n[1] +set_location_assignment PIN_B5 -to ddr4_mem[3].dq[8] +set_location_assignment PIN_A5 -to ddr4_mem[3].dq[9] +set_location_assignment PIN_A6 -to ddr4_mem[3].dq[10] +set_location_assignment PIN_E7 -to ddr4_mem[3].dq[11] +set_location_assignment PIN_E6 -to ddr4_mem[3].dq[12] +set_location_assignment PIN_D6 -to ddr4_mem[3].dq[13] +set_location_assignment PIN_C6 -to ddr4_mem[3].dq[14] +set_location_assignment PIN_A7 -to ddr4_mem[3].dq[15] + +# DDR4 CH1 - DQS2 +set_location_assignment PIN_F4 -to ddr4_mem[3].dqs[2] +set_location_assignment PIN_E4 -to ddr4_mem[3].dqs_n[2] +set_location_assignment PIN_E3 -to ddr4_mem[3].dbi_n[2] +set_location_assignment PIN_J8 -to ddr4_mem[3].dq[16] +set_location_assignment PIN_G7 -to ddr4_mem[3].dq[17] +set_location_assignment PIN_J9 -to ddr4_mem[3].dq[18] +set_location_assignment PIN_F6 -to ddr4_mem[3].dq[19] +set_location_assignment PIN_F5 -to ddr4_mem[3].dq[20] +set_location_assignment PIN_H7 -to ddr4_mem[3].dq[21] +set_location_assignment PIN_H8 -to ddr4_mem[3].dq[22] +set_location_assignment PIN_F7 -to ddr4_mem[3].dq[23] + +# DDR4 CH1 - DQS3 +set_location_assignment PIN_C5 -to ddr4_mem[3].dqs[3] +set_location_assignment PIN_D5 -to ddr4_mem[3].dqs_n[3] +set_location_assignment PIN_A4 -to ddr4_mem[3].dbi_n[3] +set_location_assignment PIN_C2 -to ddr4_mem[3].dq[24] +set_location_assignment PIN_D3 -to ddr4_mem[3].dq[25] +set_location_assignment PIN_B2 -to ddr4_mem[3].dq[26] +set_location_assignment PIN_B3 -to ddr4_mem[3].dq[27] +set_location_assignment PIN_E1 -to ddr4_mem[3].dq[28] +set_location_assignment PIN_D1 -to ddr4_mem[3].dq[29] +set_location_assignment PIN_C3 -to ddr4_mem[3].dq[30] +set_location_assignment PIN_D4 -to ddr4_mem[3].dq[31] + +# DDR4 CH1 - DQS4 +set_location_assignment PIN_P1 -to ddr4_mem[3].dqs[4] +set_location_assignment PIN_N1 -to ddr4_mem[3].dqs_n[4] +set_location_assignment PIN_N2 -to ddr4_mem[3].dbi_n[4] +set_location_assignment PIN_R4 -to ddr4_mem[3].dq[32] +set_location_assignment PIN_R1 -to ddr4_mem[3].dq[33] +set_location_assignment PIN_T2 -to ddr4_mem[3].dq[34] +set_location_assignment PIN_R3 -to ddr4_mem[3].dq[35] +set_location_assignment PIN_N3 -to ddr4_mem[3].dq[36] +set_location_assignment PIN_P3 -to ddr4_mem[3].dq[37] +set_location_assignment PIN_T1 -to ddr4_mem[3].dq[38] +set_location_assignment PIN_R2 -to ddr4_mem[3].dq[39] + +# DDR4 CH1 - DQS5 +set_location_assignment PIN_P9 -to ddr4_mem[3].dqs[5] +set_location_assignment PIN_P8 -to ddr4_mem[3].dqs_n[5] +set_location_assignment PIN_R6 -to ddr4_mem[3].dbi_n[5] +set_location_assignment PIN_N5 -to ddr4_mem[3].dq[40] +set_location_assignment PIN_P4 -to ddr4_mem[3].dq[41] +set_location_assignment PIN_N8 -to ddr4_mem[3].dq[42] +set_location_assignment PIN_P10 -to ddr4_mem[3].dq[43] +set_location_assignment PIN_N6 -to ddr4_mem[3].dq[44] +set_location_assignment PIN_P5 -to ddr4_mem[3].dq[45] +set_location_assignment PIN_N7 -to ddr4_mem[3].dq[46] +set_location_assignment PIN_N10 -to ddr4_mem[3].dq[47] + +# DDR4 CH1 - DQS6 +set_location_assignment PIN_T6 -to ddr4_mem[3].dqs[6] +set_location_assignment PIN_T7 -to ddr4_mem[3].dqs_n[6] +set_location_assignment PIN_R7 -to ddr4_mem[3].dbi_n[6] +set_location_assignment PIN_U4 -to ddr4_mem[3].dq[48] +set_location_assignment PIN_T4 -to ddr4_mem[3].dq[49] +set_location_assignment PIN_U5 -to ddr4_mem[3].dq[50] +set_location_assignment PIN_T9 -to ddr4_mem[3].dq[51] +set_location_assignment PIN_U2 -to ddr4_mem[3].dq[52] +set_location_assignment PIN_R9 -to ddr4_mem[3].dq[53] +set_location_assignment PIN_T5 -to ddr4_mem[3].dq[54] +set_location_assignment PIN_U3 -to ddr4_mem[3].dq[55] + +# DDR4 CH1 - DQS7 +set_location_assignment PIN_P13 -to ddr4_mem[3].dqs[7] +set_location_assignment PIN_N13 -to ddr4_mem[3].dqs_n[7] +set_location_assignment PIN_R11 -to ddr4_mem[3].dbi_n[7] +set_location_assignment PIN_R13 -to ddr4_mem[3].dq[56] +set_location_assignment PIN_N11 -to ddr4_mem[3].dq[57] +set_location_assignment PIN_R14 -to ddr4_mem[3].dq[58] +set_location_assignment PIN_T11 -to ddr4_mem[3].dq[59] +set_location_assignment PIN_T12 -to ddr4_mem[3].dq[60] +set_location_assignment PIN_N12 -to ddr4_mem[3].dq[61] +set_location_assignment PIN_T10 -to ddr4_mem[3].dq[62] +set_location_assignment PIN_R12 -to ddr4_mem[3].dq[63] + +# DDR4 CH1 - DQS8 +set_location_assignment PIN_M12 -to ddr4_mem[3].dqs[8] +set_location_assignment PIN_L12 -to ddr4_mem[3].dqs_n[8] +set_location_assignment PIN_K11 -to ddr4_mem[3].dbi_n[8] +set_location_assignment PIN_K14 -to ddr4_mem[3].dq[64] +set_location_assignment PIN_K13 -to ddr4_mem[3].dq[65] +set_location_assignment PIN_L9 -to ddr4_mem[3].dq[66] +set_location_assignment PIN_L11 -to ddr4_mem[3].dq[67] +set_location_assignment PIN_M13 -to ddr4_mem[3].dq[68] +set_location_assignment PIN_M14 -to ddr4_mem[3].dq[69] +set_location_assignment PIN_L10 -to ddr4_mem[3].dq[70] +set_location_assignment PIN_K9 -to ddr4_mem[3].dq[71] + +#========================================================= +# DDR4 CH2 (Lower 2) - A/C +set_location_assignment PIN_AU22 -to ddr4_mem[0].ck +set_location_assignment PIN_AV22 -to ddr4_mem[0].ck_n +set_location_assignment PIN_AM25 -to ddr4_mem[0].a[0] +set_location_assignment PIN_AN25 -to ddr4_mem[0].a[1] +set_location_assignment PIN_AP24 -to ddr4_mem[0].a[2] +set_location_assignment PIN_AP25 -to ddr4_mem[0].a[3] +set_location_assignment PIN_AL24 -to ddr4_mem[0].a[4] +set_location_assignment PIN_AM24 -to ddr4_mem[0].a[5] +set_location_assignment PIN_AL26 -to ddr4_mem[0].a[6] +set_location_assignment PIN_AL25 -to ddr4_mem[0].a[7] +set_location_assignment PIN_AP23 -to ddr4_mem[0].a[8] +set_location_assignment PIN_AN23 -to ddr4_mem[0].a[9] +set_location_assignment PIN_AR23 -to ddr4_mem[0].a[10] +set_location_assignment PIN_AR24 -to ddr4_mem[0].a[11] +set_location_assignment PIN_AY21 -to ddr4_mem[0].a[12] +set_location_assignment PIN_BB19 -to ddr4_mem[0].a[13] +set_location_assignment PIN_BA19 -to ddr4_mem[0].a[14] +set_location_assignment PIN_AW21 -to ddr4_mem[0].a[15] +set_location_assignment PIN_AV21 -to ddr4_mem[0].a[16] +set_location_assignment PIN_BB20 -to ddr4_mem[0].a[17] +set_location_assignment PIN_AR22 -to ddr4_mem[0].act_n +set_location_assignment PIN_AW20 -to ddr4_mem[0].ba[1] +set_location_assignment PIN_BA20 -to ddr4_mem[0].ba[0] +set_location_assignment PIN_BA22 -to ddr4_mem[0].bg[1] +set_location_assignment PIN_AV20 -to ddr4_mem[0].bg[0] +set_location_assignment PIN_AV23 -to ddr4_mem[0].cke +set_location_assignment PIN_AT22 -to ddr4_mem[0].cs_n +set_location_assignment PIN_BB23 -to ddr4_mem[0].odt +set_location_assignment PIN_AY22 -to ddr4_mem[0].reset_n +set_location_assignment PIN_AW23 -to ddr4_mem[0].par +set_location_assignment PIN_AY23 -to ddr4_mem[0].alert_n +set_location_assignment PIN_BA21 -to ddr4_mem[0].oct_rzqin +set_location_assignment PIN_AY19 -to ddr4_mem[0].ref_clk + +# DDR4 CH2 - DQS0 +set_location_assignment PIN_AH18 -to ddr4_mem[0].dqs[0] +set_location_assignment PIN_AJ18 -to ddr4_mem[0].dqs_n[0] +set_location_assignment PIN_AJ19 -to ddr4_mem[0].dbi_n[0] +set_location_assignment PIN_AL17 -to ddr4_mem[0].dq[0] +set_location_assignment PIN_AL19 -to ddr4_mem[0].dq[1] +set_location_assignment PIN_AM17 -to ddr4_mem[0].dq[2] +set_location_assignment PIN_AK17 -to ddr4_mem[0].dq[3] +set_location_assignment PIN_AK19 -to ddr4_mem[0].dq[4] +set_location_assignment PIN_AM20 -to ddr4_mem[0].dq[5] +set_location_assignment PIN_AN17 -to ddr4_mem[0].dq[6] +set_location_assignment PIN_AM19 -to ddr4_mem[0].dq[7] + +# DDR4 CH2 - DQS1 +set_location_assignment PIN_AK22 -to ddr4_mem[0].dqs[1] +set_location_assignment PIN_AK21 -to ddr4_mem[0].dqs_n[1] +set_location_assignment PIN_AJ24 -to ddr4_mem[0].dbi_n[1] +set_location_assignment PIN_AL22 -to ddr4_mem[0].dq[8] +set_location_assignment PIN_AJ23 -to ddr4_mem[0].dq[9] +set_location_assignment PIN_AJ26 -to ddr4_mem[0].dq[10] +set_location_assignment PIN_AK23 -to ddr4_mem[0].dq[11] +set_location_assignment PIN_AL20 -to ddr4_mem[0].dq[12] +set_location_assignment PIN_AH24 -to ddr4_mem[0].dq[13] +set_location_assignment PIN_AJ25 -to ddr4_mem[0].dq[14] +set_location_assignment PIN_AL21 -to ddr4_mem[0].dq[15] + +# DDR4 CH2 - DQS2 +set_location_assignment PIN_AM18 -to ddr4_mem[0].dqs[2] +set_location_assignment PIN_AN18 -to ddr4_mem[0].dqs_n[2] +set_location_assignment PIN_AR18 -to ddr4_mem[0].dbi_n[2] +set_location_assignment PIN_AT17 -to ddr4_mem[0].dq[16] +set_location_assignment PIN_AR16 -to ddr4_mem[0].dq[17] +set_location_assignment PIN_AT16 -to ddr4_mem[0].dq[18] +set_location_assignment PIN_AP18 -to ddr4_mem[0].dq[19] +set_location_assignment PIN_AU17 -to ddr4_mem[0].dq[20] +set_location_assignment PIN_AP19 -to ddr4_mem[0].dq[21] +set_location_assignment PIN_AT19 -to ddr4_mem[0].dq[22] +set_location_assignment PIN_AR19 -to ddr4_mem[0].dq[23] + +# DDR4 CH2 - DQS3 +set_location_assignment PIN_BB18 -to ddr4_mem[0].dqs[3] +set_location_assignment PIN_BB17 -to ddr4_mem[0].dqs_n[3] +set_location_assignment PIN_AV16 -to ddr4_mem[0].dbi_n[3] +set_location_assignment PIN_AY17 -to ddr4_mem[0].dq[24] +set_location_assignment PIN_AY16 -to ddr4_mem[0].dq[25] +set_location_assignment PIN_AU18 -to ddr4_mem[0].dq[26] +set_location_assignment PIN_AY18 -to ddr4_mem[0].dq[27] +set_location_assignment PIN_AV18 -to ddr4_mem[0].dq[28] +set_location_assignment PIN_AW16 -to ddr4_mem[0].dq[29] +set_location_assignment PIN_AW18 -to ddr4_mem[0].dq[30] +set_location_assignment PIN_BA17 -to ddr4_mem[0].dq[31] + +# DDR4 CH2 - DQS4 +set_location_assignment PIN_BB25 -to ddr4_mem[0].dqs[4] +set_location_assignment PIN_BA25 -to ddr4_mem[0].dqs_n[4] +set_location_assignment PIN_BA27 -to ddr4_mem[0].dbi_n[4] +set_location_assignment PIN_BB24 -to ddr4_mem[0].dq[32] +set_location_assignment PIN_BA26 -to ddr4_mem[0].dq[33] +set_location_assignment PIN_AV27 -to ddr4_mem[0].dq[34] +set_location_assignment PIN_AY27 -to ddr4_mem[0].dq[35] +set_location_assignment PIN_BA24 -to ddr4_mem[0].dq[36] +set_location_assignment PIN_AY26 -to ddr4_mem[0].dq[37] +set_location_assignment PIN_AV26 -to ddr4_mem[0].dq[38] +set_location_assignment PIN_AW26 -to ddr4_mem[0].dq[39] + +# DDR4 CH2 - DQS5 +set_location_assignment PIN_AT27 -to ddr4_mem[0].dqs[5] +set_location_assignment PIN_AU27 -to ddr4_mem[0].dqs_n[5] +set_location_assignment PIN_AV25 -to ddr4_mem[0].dbi_n[5] +set_location_assignment PIN_AW24 -to ddr4_mem[0].dq[40] +set_location_assignment PIN_AT26 -to ddr4_mem[0].dq[41] +set_location_assignment PIN_AT24 -to ddr4_mem[0].dq[42] +set_location_assignment PIN_AU24 -to ddr4_mem[0].dq[43] +set_location_assignment PIN_AY24 -to ddr4_mem[0].dq[44] +set_location_assignment PIN_AU25 -to ddr4_mem[0].dq[45] +set_location_assignment PIN_AT25 -to ddr4_mem[0].dq[46] +set_location_assignment PIN_AR27 -to ddr4_mem[0].dq[47] + +# DDR4 CH2 - DQS6 +set_location_assignment PIN_AP29 -to ddr4_mem[0].dqs[6] +set_location_assignment PIN_AR30 -to ddr4_mem[0].dqs_n[6] +set_location_assignment PIN_AL30 -to ddr4_mem[0].dbi_n[6] +set_location_assignment PIN_AT29 -to ddr4_mem[0].dq[48] +set_location_assignment PIN_AR29 -to ddr4_mem[0].dq[49] +set_location_assignment PIN_AP30 -to ddr4_mem[0].dq[50] +set_location_assignment PIN_AN30 -to ddr4_mem[0].dq[51] +set_location_assignment PIN_AP28 -to ddr4_mem[0].dq[52] +set_location_assignment PIN_AR28 -to ddr4_mem[0].dq[53] +set_location_assignment PIN_AT30 -to ddr4_mem[0].dq[54] +set_location_assignment PIN_AT31 -to ddr4_mem[0].dq[55] + +# DDR4 CH2 - DQS7 +set_location_assignment PIN_AK28 -to ddr4_mem[0].dqs[7] +set_location_assignment PIN_AK27 -to ddr4_mem[0].dqs_n[7] +set_location_assignment PIN_AK29 -to ddr4_mem[0].dbi_n[7] +set_location_assignment PIN_AM28 -to ddr4_mem[0].dq[56] +set_location_assignment PIN_AL29 -to ddr4_mem[0].dq[57] +set_location_assignment PIN_AN28 -to ddr4_mem[0].dq[58] +set_location_assignment PIN_AP26 -to ddr4_mem[0].dq[59] +set_location_assignment PIN_AL27 -to ddr4_mem[0].dq[60] +set_location_assignment PIN_AM29 -to ddr4_mem[0].dq[61] +set_location_assignment PIN_AN27 -to ddr4_mem[0].dq[62] +set_location_assignment PIN_AM27 -to ddr4_mem[0].dq[63] + +# DDR4 CH2 - DQS8 +set_location_assignment PIN_AU19 -to ddr4_mem[0].dqs[8] +set_location_assignment PIN_AU20 -to ddr4_mem[0].dqs_n[8] +set_location_assignment PIN_AT21 -to ddr4_mem[0].dbi_n[8] +set_location_assignment PIN_AN22 -to ddr4_mem[0].dq[64] +set_location_assignment PIN_AN20 -to ddr4_mem[0].dq[65] +set_location_assignment PIN_AM22 -to ddr4_mem[0].dq[66] +set_location_assignment PIN_AR21 -to ddr4_mem[0].dq[67] +set_location_assignment PIN_AM23 -to ddr4_mem[0].dq[68] +set_location_assignment PIN_AP20 -to ddr4_mem[0].dq[69] +set_location_assignment PIN_AN21 -to ddr4_mem[0].dq[70] +set_location_assignment PIN_AP21 -to ddr4_mem[0].dq[71] + + +#========================================================= +# DDR4 CH3 (Upper 2) - A/C +set_location_assignment PIN_K31 -to ddr4_mem[1].ck +set_location_assignment PIN_L30 -to ddr4_mem[1].ck_n +set_location_assignment PIN_M28 -to ddr4_mem[1].a[0] +set_location_assignment PIN_N28 -to ddr4_mem[1].a[1] +set_location_assignment PIN_R26 -to ddr4_mem[1].a[2] +set_location_assignment PIN_P26 -to ddr4_mem[1].a[3] +set_location_assignment PIN_P28 -to ddr4_mem[1].a[4] +set_location_assignment PIN_R27 -to ddr4_mem[1].a[5] +set_location_assignment PIN_K26 -to ddr4_mem[1].a[6] +set_location_assignment PIN_K27 -to ddr4_mem[1].a[7] +set_location_assignment PIN_N26 -to ddr4_mem[1].a[8] +set_location_assignment PIN_N27 -to ddr4_mem[1].a[9] +set_location_assignment PIN_L27 -to ddr4_mem[1].a[10] +set_location_assignment PIN_M27 -to ddr4_mem[1].a[11] +set_location_assignment PIN_J29 -to ddr4_mem[1].a[12] +set_location_assignment PIN_J28 -to ddr4_mem[1].a[13] +set_location_assignment PIN_K28 -to ddr4_mem[1].a[14] +set_location_assignment PIN_H31 -to ddr4_mem[1].a[15] +set_location_assignment PIN_H30 -to ddr4_mem[1].a[16] +set_location_assignment PIN_H28 -to ddr4_mem[1].a[17] +set_location_assignment PIN_L29 -to ddr4_mem[1].act_n +set_location_assignment PIN_G27 -to ddr4_mem[1].ba[1] +set_location_assignment PIN_H27 -to ddr4_mem[1].ba[0] +set_location_assignment PIN_N30 -to ddr4_mem[1].bg[1] +set_location_assignment PIN_F27 -to ddr4_mem[1].bg[0] +set_location_assignment PIN_M30 -to ddr4_mem[1].cke +set_location_assignment PIN_M29 -to ddr4_mem[1].cs_n +set_location_assignment PIN_K30 -to ddr4_mem[1].odt +set_location_assignment PIN_P31 -to ddr4_mem[1].reset_n +set_location_assignment PIN_P29 -to ddr4_mem[1].par +set_location_assignment PIN_P30 -to ddr4_mem[1].alert_n +set_location_assignment PIN_J30 -to ddr4_mem[1].oct_rzqin +set_location_assignment PIN_D27 -to ddr4_mem[1].ref_clk + +# DDR4 CH3 - DQS0 +set_location_assignment PIN_T23 -to ddr4_mem[1].dqs[0] +set_location_assignment PIN_R24 -to ddr4_mem[1].dqs_n[0] +set_location_assignment PIN_K23 -to ddr4_mem[1].dbi_n[0] +set_location_assignment PIN_N23 -to ddr4_mem[1].dq[0] +set_location_assignment PIN_P23 -to ddr4_mem[1].dq[1] +set_location_assignment PIN_M22 -to ddr4_mem[1].dq[2] +set_location_assignment PIN_M23 -to ddr4_mem[1].dq[3] +set_location_assignment PIN_P24 -to ddr4_mem[1].dq[4] +set_location_assignment PIN_N22 -to ddr4_mem[1].dq[5] +set_location_assignment PIN_L22 -to ddr4_mem[1].dq[6] +set_location_assignment PIN_M24 -to ddr4_mem[1].dq[7] + +# DDR4 CH3 - DQS1 +set_location_assignment PIN_N25 -to ddr4_mem[1].dqs[1] +set_location_assignment PIN_P25 -to ddr4_mem[1].dqs_n[1] +set_location_assignment PIN_L25 -to ddr4_mem[1].dbi_n[1] +set_location_assignment PIN_G25 -to ddr4_mem[1].dq[8] +set_location_assignment PIN_H26 -to ddr4_mem[1].dq[9] +set_location_assignment PIN_J24 -to ddr4_mem[1].dq[10] +set_location_assignment PIN_J25 -to ddr4_mem[1].dq[11] +set_location_assignment PIN_G24 -to ddr4_mem[1].dq[12] +set_location_assignment PIN_H25 -to ddr4_mem[1].dq[13] +set_location_assignment PIN_L24 -to ddr4_mem[1].dq[14] +set_location_assignment PIN_K24 -to ddr4_mem[1].dq[15] + +# DDR4 CH3 - DQS2 +set_location_assignment PIN_B24 -to ddr4_mem[1].dqs[2] +set_location_assignment PIN_B25 -to ddr4_mem[1].dqs_n[2] +set_location_assignment PIN_C27 -to ddr4_mem[1].dbi_n[2] +set_location_assignment PIN_E26 -to ddr4_mem[1].dq[16] +set_location_assignment PIN_D26 -to ddr4_mem[1].dq[17] +set_location_assignment PIN_D25 -to ddr4_mem[1].dq[18] +set_location_assignment PIN_C25 -to ddr4_mem[1].dq[19] +set_location_assignment PIN_F26 -to ddr4_mem[1].dq[20] +set_location_assignment PIN_F25 -to ddr4_mem[1].dq[21] +set_location_assignment PIN_A24 -to ddr4_mem[1].dq[22] +set_location_assignment PIN_A25 -to ddr4_mem[1].dq[23] + +# DDR4 CH3 - DQS3 +set_location_assignment PIN_C23 -to ddr4_mem[1].dqs[3] +set_location_assignment PIN_C22 -to ddr4_mem[1].dqs_n[3] +set_location_assignment PIN_D24 -to ddr4_mem[1].dbi_n[3] +set_location_assignment PIN_B23 -to ddr4_mem[1].dq[24] +set_location_assignment PIN_G23 -to ddr4_mem[1].dq[25] +set_location_assignment PIN_E23 -to ddr4_mem[1].dq[26] +set_location_assignment PIN_B22 -to ddr4_mem[1].dq[27] +set_location_assignment PIN_D23 -to ddr4_mem[1].dq[28] +set_location_assignment PIN_F24 -to ddr4_mem[1].dq[29] +set_location_assignment PIN_A21 -to ddr4_mem[1].dq[30] +set_location_assignment PIN_A22 -to ddr4_mem[1].dq[31] + +# DDR4 CH3 - DQS4 +set_location_assignment PIN_D8 -to ddr4_mem[1].dqs[4] +set_location_assignment PIN_C8 -to ddr4_mem[1].dqs_n[4] +set_location_assignment PIN_C10 -to ddr4_mem[1].dbi_n[4] +set_location_assignment PIN_D11 -to ddr4_mem[1].dq[32] +set_location_assignment PIN_D9 -to ddr4_mem[1].dq[33] +set_location_assignment PIN_F12 -to ddr4_mem[1].dq[34] +set_location_assignment PIN_G12 -to ddr4_mem[1].dq[35] +set_location_assignment PIN_E12 -to ddr4_mem[1].dq[36] +set_location_assignment PIN_D10 -to ddr4_mem[1].dq[37] +set_location_assignment PIN_E11 -to ddr4_mem[1].dq[38] +set_location_assignment PIN_F11 -to ddr4_mem[1].dq[39] + +# DDR4 CH3 - DQS5 +set_location_assignment PIN_N17 -to ddr4_mem[1].dqs[5] +set_location_assignment PIN_M17 -to ddr4_mem[1].dqs_n[5] +set_location_assignment PIN_M18 -to ddr4_mem[1].dbi_n[5] +set_location_assignment PIN_H16 -to ddr4_mem[1].dq[40] +set_location_assignment PIN_L17 -to ddr4_mem[1].dq[41] +set_location_assignment PIN_F17 -to ddr4_mem[1].dq[42] +set_location_assignment PIN_F16 -to ddr4_mem[1].dq[43] +set_location_assignment PIN_H17 -to ddr4_mem[1].dq[44] +set_location_assignment PIN_K17 -to ddr4_mem[1].dq[45] +set_location_assignment PIN_E16 -to ddr4_mem[1].dq[46] +set_location_assignment PIN_G17 -to ddr4_mem[1].dq[47] + +# DDR4 CH3 - DQS6 +set_location_assignment PIN_R17 -to ddr4_mem[1].dqs[6] +set_location_assignment PIN_P18 -to ddr4_mem[1].dqs_n[6] +set_location_assignment PIN_M15 -to ddr4_mem[1].dbi_n[6] +set_location_assignment PIN_K16 -to ddr4_mem[1].dq[48] +set_location_assignment PIN_L15 -to ddr4_mem[1].dq[49] +set_location_assignment PIN_P16 -to ddr4_mem[1].dq[50] +set_location_assignment PIN_N16 -to ddr4_mem[1].dq[51] +set_location_assignment PIN_J16 -to ddr4_mem[1].dq[52] +set_location_assignment PIN_L16 -to ddr4_mem[1].dq[53] +set_location_assignment PIN_P15 -to ddr4_mem[1].dq[54] +set_location_assignment PIN_R16 -to ddr4_mem[1].dq[55] + +# DDR4 CH3 - DQS7 +set_location_assignment PIN_E14 -to ddr4_mem[1].dqs[7] +set_location_assignment PIN_F14 -to ddr4_mem[1].dqs_n[7] +set_location_assignment PIN_D15 -to ddr4_mem[1].dbi_n[7] +set_location_assignment PIN_H15 -to ddr4_mem[1].dq[56] +set_location_assignment PIN_F15 -to ddr4_mem[1].dq[57] +set_location_assignment PIN_G13 -to ddr4_mem[1].dq[58] +set_location_assignment PIN_G14 -to ddr4_mem[1].dq[59] +set_location_assignment PIN_J15 -to ddr4_mem[1].dq[60] +set_location_assignment PIN_G15 -to ddr4_mem[1].dq[61] +set_location_assignment PIN_E13 -to ddr4_mem[1].dq[62] +set_location_assignment PIN_D13 -to ddr4_mem[1].dq[63] + +# DDR4 CH3 - DQS8 +set_location_assignment PIN_J23 -to ddr4_mem[1].dqs[8] +set_location_assignment PIN_H23 -to ddr4_mem[1].dqs_n[8] +set_location_assignment PIN_E21 -to ddr4_mem[1].dbi_n[8] +set_location_assignment PIN_C21 -to ddr4_mem[1].dq[64] +set_location_assignment PIN_D21 -to ddr4_mem[1].dq[65] +set_location_assignment PIN_J21 -to ddr4_mem[1].dq[66] +set_location_assignment PIN_H21 -to ddr4_mem[1].dq[67] +set_location_assignment PIN_F22 -to ddr4_mem[1].dq[68] +set_location_assignment PIN_E22 -to ddr4_mem[1].dq[69] +set_location_assignment PIN_H22 -to ddr4_mem[1].dq[70] +set_location_assignment PIN_G22 -to ddr4_mem[1].dq[71] diff --git a/syn/setup/emif_design_files.tcl b/syn/setup/emif_design_files.tcl new file mode 100644 index 0000000..c23a82b --- /dev/null +++ b/syn/setup/emif_design_files.tcl @@ -0,0 +1,24 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# EMIF +#-------------------- + +# Library and package +set_global_assignment -name SEARCH_PATH $::env(BUILD_ROOT_REL)/ipss/mem/includes + +# EMIF design files +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/mem/custom_altera_avalon_mm_bridge.v +set_global_assignment -name VERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/mem/ddr_avmm_bridge.v +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/mem/mem_intf.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/mem/emif_csr.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/mem/avmm_chkr/avmm_chkr.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/mem/emif_top.sv + +# EMIF IP +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/ipss/mem/ip/emif_ddr4_no_ecc.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/ipss/mem/ip/avmm_cdc.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/ipss/mem/ip/avmm_pipeline_bridge.ip + +# SDC +set_global_assignment -name SDC_FILE ../setup/emif_top.sdc diff --git a/syn/setup/emif_fitter_assignments.tcl b/syn/setup/emif_fitter_assignments.tcl new file mode 100644 index 0000000..cf7e59b --- /dev/null +++ b/syn/setup/emif_fitter_assignments.tcl @@ -0,0 +1,26 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# EMIF pins assignments +#-------------------------- +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE ./emif_all_x8.tcl + +#-------------------------- +# EMIF location assignments +#-------------------------- +#set_global_assignment -name SOURCE_TCL_SCRIPT_FILE ./mem_bank_0_location.tcl +#set_global_assignment -name SOURCE_TCL_SCRIPT_FILE ./mem_bank_1_location.tcl + +#-------------------------- +# EMIF fitter assignments +#-------------------------- +for {set ddr_bank 0} {$ddr_bank < 4} {incr ddr_bank} { + # Disable global signal promotion on reset_sync_pri_sdc_anchor, + # due to long routing to global driver in the core causing recovery failure + set_instance_assignment -name GLOBAL_SIGNAL OFF -to mem|mem_bank[$ddr_bank].emif_ddr4_inst|emif_s10_0|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor + + # Overwrite MAX_FANOUT assignment in EMIF IP core to avoid resource congestion + # in DDR region due to synthesis duplication + set_instance_assignment -name MAX_FANOUT 256 -to mem|mem_bank[$ddr_bank].emif_ddr4_inst|emif_s10_0|arch|arch_inst|hmc_avl_if_inst|amm.ready_0_hyper_regs.amm_ready_0_r1 + set_instance_assignment -name MAX_FANOUT 256 -to mem|mem_bank[$ddr_bank].emif_ddr4_inst|emif_s10_0|arch|arch_inst|hmc_avl_if_inst|amm.ready_1_hyper_regs.amm_ready_1_r1 +} diff --git a/syn/setup/emif_top.sdc b/syn/setup/emif_top.sdc new file mode 100644 index 0000000..f7c7818 --- /dev/null +++ b/syn/setup/emif_top.sdc @@ -0,0 +1,29 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# Description +#----------------------------------------------------------------------------- +# +# EMIF SDC +# +#----------------------------------------------------------------------------- + +proc add_reset_sync_sdc { pin_name } { + set_max_delay -to [get_pins $pin_name] 100.000 + set_min_delay -to [get_pins $pin_name] -100.000 + #set_max_skew -to [get_pins $pin_name] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 +} + +proc add_sync_sdc { name } { + set_max_delay -to [get_keepers $name] 100.000 + set_min_delay -to [get_keepers $name] -100.000 +} + +#--------------------------------------------- +# CDC constraints for synchronizers +#--------------------------------------------- +add_sync_sdc {emif_top_inst|mem_bank[*].ddr4_*_sync|resync_chains[*].synchronizer_nocut|din_s1} +add_sync_sdc {emif_top_inst|emif_csr|emif_csr_stat_sync|resync_chains[*].synchronizer_nocut|din_s1} + + + diff --git a/syn/setup/emif_x8_location.tcl b/syn/setup/emif_x8_location.tcl new file mode 100644 index 0000000..96af63f --- /dev/null +++ b/syn/setup/emif_x8_location.tcl @@ -0,0 +1,625 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# Description +#----------------------------------------------------------------------------- +# +# DDR4 pin and location assignments +# +#----------------------------------------------------------------------------- + +#======================================================= +# DDR4 CH0 (Lower 3) - A/C +#======================================================= +set_location_assignment PIN_AP10 -to ddr4_mem[2].ck +set_location_assignment PIN_AP11 -to ddr4_mem[2].ck_n +set_location_assignment PIN_AT4 -to ddr4_mem[2].a[0] +set_location_assignment PIN_AT5 -to ddr4_mem[2].a[1] +set_location_assignment PIN_AR2 -to ddr4_mem[2].a[2] +set_location_assignment PIN_AR1 -to ddr4_mem[2].a[3] +set_location_assignment PIN_AR3 -to ddr4_mem[2].a[4] +set_location_assignment PIN_AR4 -to ddr4_mem[2].a[5] +set_location_assignment PIN_AP1 -to ddr4_mem[2].a[6] +set_location_assignment PIN_AN1 -to ddr4_mem[2].a[7] +set_location_assignment PIN_AP4 -to ddr4_mem[2].a[8] +set_location_assignment PIN_AP3 -to ddr4_mem[2].a[9] +set_location_assignment PIN_AT2 -to ddr4_mem[2].a[10] +set_location_assignment PIN_AT1 -to ddr4_mem[2].a[11] +set_location_assignment PIN_AN2 -to ddr4_mem[2].a[12] +set_location_assignment PIN_AN5 -to ddr4_mem[2].a[13] +set_location_assignment PIN_AM5 -to ddr4_mem[2].a[14] +set_location_assignment PIN_AM2 -to ddr4_mem[2].a[15] +set_location_assignment PIN_AM3 -to ddr4_mem[2].a[16] +set_location_assignment PIN_AM4 -to ddr4_mem[2].a[17] +set_location_assignment PIN_AR7 -to ddr4_mem[2].act_n +set_location_assignment PIN_AL1 -to ddr4_mem[2].ba[1] +set_location_assignment PIN_AL4 -to ddr4_mem[2].ba[0] +set_location_assignment PIN_AR9 -to ddr4_mem[2].bg[1] +set_location_assignment PIN_AL2 -to ddr4_mem[2].bg[0] +set_location_assignment PIN_AT6 -to ddr4_mem[2].cke +set_location_assignment PIN_AR8 -to ddr4_mem[2].cs_n +set_location_assignment PIN_AP8 -to ddr4_mem[2].odt +set_location_assignment PIN_AP9 -to ddr4_mem[2].reset_n +set_location_assignment PIN_AP5 -to ddr4_mem[2].par +set_location_assignment PIN_AP6 -to ddr4_mem[2].alert_n +set_location_assignment PIN_AN3 -to ddr4_mem[2].oct_rzqin +set_location_assignment PIN_AL5 -to ddr4_mem[2].ref_clk + +# DDR4 CH0 - DQS0 +set_location_assignment PIN_AH5 -to ddr4_mem[2].dqs[0] +set_location_assignment PIN_AG5 -to ddr4_mem[2].dqs_n[0] +set_location_assignment PIN_AG4 -to ddr4_mem[2].dbi_n[0] +set_location_assignment PIN_AF1 -to ddr4_mem[2].dq[0] +set_location_assignment PIN_AH6 -to ddr4_mem[2].dq[1] +set_location_assignment PIN_AH3 -to ddr4_mem[2].dq[2] +set_location_assignment PIN_AG2 -to ddr4_mem[2].dq[3] +set_location_assignment PIN_AF2 -to ddr4_mem[2].dq[4] +set_location_assignment PIN_AH7 -to ddr4_mem[2].dq[5] +set_location_assignment PIN_AH2 -to ddr4_mem[2].dq[6] +set_location_assignment PIN_AG3 -to ddr4_mem[2].dq[7] + +# DDR4 CH0 - DQS1 +set_location_assignment PIN_AK6 -to ddr4_mem[2].dqs[1] +set_location_assignment PIN_AK7 -to ddr4_mem[2].dqs_n[1] +set_location_assignment PIN_AJ6 -to ddr4_mem[2].dbi_n[1] +set_location_assignment PIN_AK2 -to ddr4_mem[2].dq[8] +set_location_assignment PIN_AJ3 -to ddr4_mem[2].dq[9] +set_location_assignment PIN_AK4 -to ddr4_mem[2].dq[10] +set_location_assignment PIN_AJ4 -to ddr4_mem[2].dq[11] +set_location_assignment PIN_AK1 -to ddr4_mem[2].dq[12] +set_location_assignment PIN_AH1 -to ddr4_mem[2].dq[13] +set_location_assignment PIN_AK3 -to ddr4_mem[2].dq[14] +set_location_assignment PIN_AJ1 -to ddr4_mem[2].dq[15] + +# DDR4 CH0 - DQS2 +set_location_assignment PIN_AL11 -to ddr4_mem[2].dqs[2] +set_location_assignment PIN_AL10 -to ddr4_mem[2].dqs_n[2] +set_location_assignment PIN_AK12 -to ddr4_mem[2].dbi_n[2] +set_location_assignment PIN_AL12 -to ddr4_mem[2].dq[16] +set_location_assignment PIN_AK11 -to ddr4_mem[2].dq[17] +set_location_assignment PIN_AL9 -to ddr4_mem[2].dq[18] +set_location_assignment PIN_AK8 -to ddr4_mem[2].dq[19] +set_location_assignment PIN_AL14 -to ddr4_mem[2].dq[20] +set_location_assignment PIN_AK14 -to ddr4_mem[2].dq[21] +set_location_assignment PIN_AL7 -to ddr4_mem[2].dq[22] +set_location_assignment PIN_AK9 -to ddr4_mem[2].dq[23] + +# DDR4 CH0 - DQS3 +set_location_assignment PIN_AH10 -to ddr4_mem[2].dqs[3] +set_location_assignment PIN_AJ11 -to ddr4_mem[2].dqs_n[3] +set_location_assignment PIN_AH11 -to ddr4_mem[2].dbi_n[3] +set_location_assignment PIN_AH13 -to ddr4_mem[2].dq[24] +set_location_assignment PIN_AG7 -to ddr4_mem[2].dq[25] +set_location_assignment PIN_AJ10 -to ddr4_mem[2].dq[26] +set_location_assignment PIN_AJ8 -to ddr4_mem[2].dq[27] +set_location_assignment PIN_AJ13 -to ddr4_mem[2].dq[28] +set_location_assignment PIN_AG8 -to ddr4_mem[2].dq[29] +set_location_assignment PIN_AJ9 -to ddr4_mem[2].dq[30] +set_location_assignment PIN_AH8 -to ddr4_mem[2].dq[31] + +# DDR4 CH0 - DQS4 +set_location_assignment PIN_AV6 -to ddr4_mem[2].dqs[4] +set_location_assignment PIN_AV5 -to ddr4_mem[2].dqs_n[4] +set_location_assignment PIN_AW1 -to ddr4_mem[2].dbi_n[4] +set_location_assignment PIN_AU4 -to ddr4_mem[2].dq[32] +set_location_assignment PIN_AU5 -to ddr4_mem[2].dq[33] +set_location_assignment PIN_AU3 -to ddr4_mem[2].dq[34] +set_location_assignment PIN_AV2 -to ddr4_mem[2].dq[35] +set_location_assignment PIN_AV7 -to ddr4_mem[2].dq[36] +set_location_assignment PIN_AV8 -to ddr4_mem[2].dq[37] +set_location_assignment PIN_AU2 -to ddr4_mem[2].dq[38] +set_location_assignment PIN_AV3 -to ddr4_mem[2].dq[39] + +# DDR4 CH0 - DQS5 +set_location_assignment PIN_AV10 -to ddr4_mem[2].dqs[5] +set_location_assignment PIN_AU10 -to ddr4_mem[2].dqs_n[5] +set_location_assignment PIN_AU13 -to ddr4_mem[2].dbi_n[5] +set_location_assignment PIN_AY7 -to ddr4_mem[2].dq[40] +set_location_assignment PIN_AW10 -to ddr4_mem[2].dq[41] +set_location_assignment PIN_AV11 -to ddr4_mem[2].dq[42] +set_location_assignment PIN_AW8 -to ddr4_mem[2].dq[43] +set_location_assignment PIN_AY6 -to ddr4_mem[2].dq[44] +set_location_assignment PIN_AW11 -to ddr4_mem[2].dq[45] +set_location_assignment PIN_AV12 -to ddr4_mem[2].dq[46] +set_location_assignment PIN_AW9 -to ddr4_mem[2].dq[47] + +# DDR4 CH0 - DQS6 +set_location_assignment PIN_AT11 -to ddr4_mem[2].dqs[6] +set_location_assignment PIN_AR11 -to ddr4_mem[2].dqs_n[6] +set_location_assignment PIN_AR13 -to ddr4_mem[2].dbi_n[6] +set_location_assignment PIN_AU8 -to ddr4_mem[2].dq[48] +set_location_assignment PIN_AT12 -to ddr4_mem[2].dq[49] +set_location_assignment PIN_AT9 -to ddr4_mem[2].dq[50] +set_location_assignment PIN_AT7 -to ddr4_mem[2].dq[51] +set_location_assignment PIN_AU7 -to ddr4_mem[2].dq[52] +set_location_assignment PIN_AT10 -to ddr4_mem[2].dq[53] +set_location_assignment PIN_AU9 -to ddr4_mem[2].dq[54] +set_location_assignment PIN_AR12 -to ddr4_mem[2].dq[55] + +# DDR4 CH0 - DQS7 +set_location_assignment PIN_BA4 -to ddr4_mem[2].dqs[7] +set_location_assignment PIN_BB4 -to ddr4_mem[2].dqs_n[7] +set_location_assignment PIN_AW5 -to ddr4_mem[2].dbi_n[7] +set_location_assignment PIN_BA2 -to ddr4_mem[2].dq[56] +set_location_assignment PIN_AY4 -to ddr4_mem[2].dq[57] +set_location_assignment PIN_AW3 -to ddr4_mem[2].dq[58] +set_location_assignment PIN_BA5 -to ddr4_mem[2].dq[59] +set_location_assignment PIN_AY2 -to ddr4_mem[2].dq[60] +set_location_assignment PIN_AW4 -to ddr4_mem[2].dq[61] +set_location_assignment PIN_AY3 -to ddr4_mem[2].dq[62] +set_location_assignment PIN_BB5 -to ddr4_mem[2].dq[63] + +# DDR4 CH0 - DQS8 +set_location_assignment PIN_AN10 -to ddr4_mem[2].dqs[8] +set_location_assignment PIN_AN11 -to ddr4_mem[2].dqs_n[8] +set_location_assignment PIN_AM12 -to ddr4_mem[2].dbi_n[8] +set_location_assignment PIN_AM7 -to ddr4_mem[2].dq[64] +set_location_assignment PIN_AM8 -to ddr4_mem[2].dq[65] +set_location_assignment PIN_AN13 -to ddr4_mem[2].dq[66] +set_location_assignment PIN_AN12 -to ddr4_mem[2].dq[67] +set_location_assignment PIN_AN6 -to ddr4_mem[2].dq[68] +set_location_assignment PIN_AN7 -to ddr4_mem[2].dq[69] +set_location_assignment PIN_AM9 -to ddr4_mem[2].dq[70] +set_location_assignment PIN_AM10 -to ddr4_mem[2].dq[71] + +#========================================================= +# DDR4 CH1 (Upper 3) - A/C +#========================================================= +set_location_assignment PIN_L6 -to ddr4_mem[3].ck +set_location_assignment PIN_L7 -to ddr4_mem[3].ck_n +set_location_assignment PIN_H1 -to ddr4_mem[3].a[0] +set_location_assignment PIN_J1 -to ddr4_mem[3].a[1] +set_location_assignment PIN_L2 -to ddr4_mem[3].a[2] +set_location_assignment PIN_K2 -to ddr4_mem[3].a[3] +set_location_assignment PIN_F2 -to ddr4_mem[3].a[4] +set_location_assignment PIN_F1 -to ddr4_mem[3].a[5] +set_location_assignment PIN_L1 -to ddr4_mem[3].a[6] +set_location_assignment PIN_K1 -to ddr4_mem[3].a[7] +set_location_assignment PIN_G2 -to ddr4_mem[3].a[8] +set_location_assignment PIN_H2 -to ddr4_mem[3].a[9] +set_location_assignment PIN_K3 -to ddr4_mem[3].a[10] +set_location_assignment PIN_J3 -to ddr4_mem[3].a[11] +set_location_assignment PIN_J4 -to ddr4_mem[3].a[12] +set_location_assignment PIN_K6 -to ddr4_mem[3].a[13] +set_location_assignment PIN_J6 -to ddr4_mem[3].a[14] +set_location_assignment PIN_H3 -to ddr4_mem[3].a[15] +set_location_assignment PIN_G3 -to ddr4_mem[3].a[16] +set_location_assignment PIN_H5 -to ddr4_mem[3].a[17] +set_location_assignment PIN_L5 -to ddr4_mem[3].act_n +set_location_assignment PIN_G4 -to ddr4_mem[3].ba[1] +set_location_assignment PIN_H6 -to ddr4_mem[3].ba[0] +set_location_assignment PIN_M10 -to ddr4_mem[3].bg[1] +set_location_assignment PIN_G5 -to ddr4_mem[3].bg[0] +set_location_assignment PIN_M4 -to ddr4_mem[3].cke +set_location_assignment PIN_M5 -to ddr4_mem[3].cs_n +set_location_assignment PIN_M8 -to ddr4_mem[3].odt +set_location_assignment PIN_M9 -to ddr4_mem[3].reset_n +set_location_assignment PIN_K4 -to ddr4_mem[3].par +set_location_assignment PIN_L4 -to ddr4_mem[3].alert_n +set_location_assignment PIN_J5 -to ddr4_mem[3].oct_rzqin +set_location_assignment PIN_K8 -to ddr4_mem[3].ref_clk + +# DDR4 CH1 - DQS0 +set_location_assignment PIN_G8 -to ddr4_mem[3].dqs[0] +set_location_assignment PIN_G9 -to ddr4_mem[3].dqs_n[0] +set_location_assignment PIN_J13 -to ddr4_mem[3].dbi_n[0] +set_location_assignment PIN_H10 -to ddr4_mem[3].dq[0] +set_location_assignment PIN_H11 -to ddr4_mem[3].dq[1] +set_location_assignment PIN_G10 -to ddr4_mem[3].dq[2] +set_location_assignment PIN_F9 -to ddr4_mem[3].dq[3] +set_location_assignment PIN_J10 -to ddr4_mem[3].dq[4] +set_location_assignment PIN_J11 -to ddr4_mem[3].dq[5] +set_location_assignment PIN_H12 -to ddr4_mem[3].dq[6] +set_location_assignment PIN_F10 -to ddr4_mem[3].dq[7] + +# DDR4 CH1 - DQS1 +set_location_assignment PIN_C7 -to ddr4_mem[3].dqs[1] +set_location_assignment PIN_B7 -to ddr4_mem[3].dqs_n[1] +set_location_assignment PIN_E9 -to ddr4_mem[3].dbi_n[1] +set_location_assignment PIN_B5 -to ddr4_mem[3].dq[8] +set_location_assignment PIN_A5 -to ddr4_mem[3].dq[9] +set_location_assignment PIN_A6 -to ddr4_mem[3].dq[10] +set_location_assignment PIN_E7 -to ddr4_mem[3].dq[11] +set_location_assignment PIN_E6 -to ddr4_mem[3].dq[12] +set_location_assignment PIN_D6 -to ddr4_mem[3].dq[13] +set_location_assignment PIN_C6 -to ddr4_mem[3].dq[14] +set_location_assignment PIN_A7 -to ddr4_mem[3].dq[15] + +# DDR4 CH1 - DQS2 +set_location_assignment PIN_F4 -to ddr4_mem[3].dqs[2] +set_location_assignment PIN_E4 -to ddr4_mem[3].dqs_n[2] +set_location_assignment PIN_E3 -to ddr4_mem[3].dbi_n[2] +set_location_assignment PIN_J8 -to ddr4_mem[3].dq[16] +set_location_assignment PIN_G7 -to ddr4_mem[3].dq[17] +set_location_assignment PIN_J9 -to ddr4_mem[3].dq[18] +set_location_assignment PIN_F6 -to ddr4_mem[3].dq[19] +set_location_assignment PIN_F5 -to ddr4_mem[3].dq[20] +set_location_assignment PIN_H7 -to ddr4_mem[3].dq[21] +set_location_assignment PIN_H8 -to ddr4_mem[3].dq[22] +set_location_assignment PIN_F7 -to ddr4_mem[3].dq[23] + +# DDR4 CH1 - DQS3 +set_location_assignment PIN_C5 -to ddr4_mem[3].dqs[3] +set_location_assignment PIN_D5 -to ddr4_mem[3].dqs_n[3] +set_location_assignment PIN_A4 -to ddr4_mem[3].dbi_n[3] +set_location_assignment PIN_C2 -to ddr4_mem[3].dq[24] +set_location_assignment PIN_D3 -to ddr4_mem[3].dq[25] +set_location_assignment PIN_B2 -to ddr4_mem[3].dq[26] +set_location_assignment PIN_B3 -to ddr4_mem[3].dq[27] +set_location_assignment PIN_E1 -to ddr4_mem[3].dq[28] +set_location_assignment PIN_D1 -to ddr4_mem[3].dq[29] +set_location_assignment PIN_C3 -to ddr4_mem[3].dq[30] +set_location_assignment PIN_D4 -to ddr4_mem[3].dq[31] + +# DDR4 CH1 - DQS4 +set_location_assignment PIN_P1 -to ddr4_mem[3].dqs[4] +set_location_assignment PIN_N1 -to ddr4_mem[3].dqs_n[4] +set_location_assignment PIN_N2 -to ddr4_mem[3].dbi_n[4] +set_location_assignment PIN_R4 -to ddr4_mem[3].dq[32] +set_location_assignment PIN_R1 -to ddr4_mem[3].dq[33] +set_location_assignment PIN_T2 -to ddr4_mem[3].dq[34] +set_location_assignment PIN_R3 -to ddr4_mem[3].dq[35] +set_location_assignment PIN_N3 -to ddr4_mem[3].dq[36] +set_location_assignment PIN_P3 -to ddr4_mem[3].dq[37] +set_location_assignment PIN_T1 -to ddr4_mem[3].dq[38] +set_location_assignment PIN_R2 -to ddr4_mem[3].dq[39] + +# DDR4 CH1 - DQS5 +set_location_assignment PIN_P9 -to ddr4_mem[3].dqs[5] +set_location_assignment PIN_P8 -to ddr4_mem[3].dqs_n[5] +set_location_assignment PIN_R6 -to ddr4_mem[3].dbi_n[5] +set_location_assignment PIN_N5 -to ddr4_mem[3].dq[40] +set_location_assignment PIN_P4 -to ddr4_mem[3].dq[41] +set_location_assignment PIN_N8 -to ddr4_mem[3].dq[42] +set_location_assignment PIN_P10 -to ddr4_mem[3].dq[43] +set_location_assignment PIN_N6 -to ddr4_mem[3].dq[44] +set_location_assignment PIN_P5 -to ddr4_mem[3].dq[45] +set_location_assignment PIN_N7 -to ddr4_mem[3].dq[46] +set_location_assignment PIN_N10 -to ddr4_mem[3].dq[47] + +# DDR4 CH1 - DQS6 +set_location_assignment PIN_T6 -to ddr4_mem[3].dqs[6] +set_location_assignment PIN_T7 -to ddr4_mem[3].dqs_n[6] +set_location_assignment PIN_R7 -to ddr4_mem[3].dbi_n[6] +set_location_assignment PIN_U4 -to ddr4_mem[3].dq[48] +set_location_assignment PIN_T4 -to ddr4_mem[3].dq[49] +set_location_assignment PIN_U5 -to ddr4_mem[3].dq[50] +set_location_assignment PIN_T9 -to ddr4_mem[3].dq[51] +set_location_assignment PIN_U2 -to ddr4_mem[3].dq[52] +set_location_assignment PIN_R9 -to ddr4_mem[3].dq[53] +set_location_assignment PIN_T5 -to ddr4_mem[3].dq[54] +set_location_assignment PIN_U3 -to ddr4_mem[3].dq[55] + +# DDR4 CH1 - DQS7 +set_location_assignment PIN_P13 -to ddr4_mem[3].dqs[7] +set_location_assignment PIN_N13 -to ddr4_mem[3].dqs_n[7] +set_location_assignment PIN_R11 -to ddr4_mem[3].dbi_n[7] +set_location_assignment PIN_R13 -to ddr4_mem[3].dq[56] +set_location_assignment PIN_N11 -to ddr4_mem[3].dq[57] +set_location_assignment PIN_R14 -to ddr4_mem[3].dq[58] +set_location_assignment PIN_T11 -to ddr4_mem[3].dq[59] +set_location_assignment PIN_T12 -to ddr4_mem[3].dq[60] +set_location_assignment PIN_N12 -to ddr4_mem[3].dq[61] +set_location_assignment PIN_T10 -to ddr4_mem[3].dq[62] +set_location_assignment PIN_R12 -to ddr4_mem[3].dq[63] + +# DDR4 CH1 - DQS8 +set_location_assignment PIN_M12 -to ddr4_mem[3].dqs[8] +set_location_assignment PIN_L12 -to ddr4_mem[3].dqs_n[8] +set_location_assignment PIN_K11 -to ddr4_mem[3].dbi_n[8] +set_location_assignment PIN_K14 -to ddr4_mem[3].dq[64] +set_location_assignment PIN_K13 -to ddr4_mem[3].dq[65] +set_location_assignment PIN_L9 -to ddr4_mem[3].dq[66] +set_location_assignment PIN_L11 -to ddr4_mem[3].dq[67] +set_location_assignment PIN_M13 -to ddr4_mem[3].dq[68] +set_location_assignment PIN_M14 -to ddr4_mem[3].dq[69] +set_location_assignment PIN_L10 -to ddr4_mem[3].dq[70] +set_location_assignment PIN_K9 -to ddr4_mem[3].dq[71] + +#========================================================= +# DDR4 CH2 (Lower 2) - A/C +#========================================================= +set_location_assignment PIN_AU22 -to ddr4_mem[0].ck +set_location_assignment PIN_AV22 -to ddr4_mem[0].ck_n +set_location_assignment PIN_AM25 -to ddr4_mem[0].a[0] +set_location_assignment PIN_AN25 -to ddr4_mem[0].a[1] +set_location_assignment PIN_AP24 -to ddr4_mem[0].a[2] +set_location_assignment PIN_AP25 -to ddr4_mem[0].a[3] +set_location_assignment PIN_AL24 -to ddr4_mem[0].a[4] +set_location_assignment PIN_AM24 -to ddr4_mem[0].a[5] +set_location_assignment PIN_AL26 -to ddr4_mem[0].a[6] +set_location_assignment PIN_AL25 -to ddr4_mem[0].a[7] +set_location_assignment PIN_AP23 -to ddr4_mem[0].a[8] +set_location_assignment PIN_AN23 -to ddr4_mem[0].a[9] +set_location_assignment PIN_AR23 -to ddr4_mem[0].a[10] +set_location_assignment PIN_AR24 -to ddr4_mem[0].a[11] +set_location_assignment PIN_AY21 -to ddr4_mem[0].a[12] +set_location_assignment PIN_BB19 -to ddr4_mem[0].a[13] +set_location_assignment PIN_BA19 -to ddr4_mem[0].a[14] +set_location_assignment PIN_AW21 -to ddr4_mem[0].a[15] +set_location_assignment PIN_AV21 -to ddr4_mem[0].a[16] +set_location_assignment PIN_BB20 -to ddr4_mem[0].a[17] +set_location_assignment PIN_AR22 -to ddr4_mem[0].act_n +set_location_assignment PIN_AW20 -to ddr4_mem[0].ba[1] +set_location_assignment PIN_BA20 -to ddr4_mem[0].ba[0] +set_location_assignment PIN_BA22 -to ddr4_mem[0].bg[1] +set_location_assignment PIN_AV20 -to ddr4_mem[0].bg[0] +set_location_assignment PIN_AV23 -to ddr4_mem[0].cke +set_location_assignment PIN_AT22 -to ddr4_mem[0].cs_n +set_location_assignment PIN_BB23 -to ddr4_mem[0].odt +set_location_assignment PIN_AY22 -to ddr4_mem[0].reset_n +set_location_assignment PIN_AW23 -to ddr4_mem[0].par +set_location_assignment PIN_AY23 -to ddr4_mem[0].alert_n +set_location_assignment PIN_BA21 -to ddr4_mem[0].oct_rzqin +set_location_assignment PIN_AY19 -to ddr4_mem[0].ref_clk + +# DDR4 CH2 - DQS0 +set_location_assignment PIN_AH18 -to ddr4_mem[0].dqs[0] +set_location_assignment PIN_AJ18 -to ddr4_mem[0].dqs_n[0] +set_location_assignment PIN_AJ19 -to ddr4_mem[0].dbi_n[0] +set_location_assignment PIN_AL17 -to ddr4_mem[0].dq[0] +set_location_assignment PIN_AL19 -to ddr4_mem[0].dq[1] +set_location_assignment PIN_AM17 -to ddr4_mem[0].dq[2] +set_location_assignment PIN_AK17 -to ddr4_mem[0].dq[3] +set_location_assignment PIN_AK19 -to ddr4_mem[0].dq[4] +set_location_assignment PIN_AM20 -to ddr4_mem[0].dq[5] +set_location_assignment PIN_AN17 -to ddr4_mem[0].dq[6] +set_location_assignment PIN_AM19 -to ddr4_mem[0].dq[7] + +# DDR4 CH2 - DQS1 +set_location_assignment PIN_AK22 -to ddr4_mem[0].dqs[1] +set_location_assignment PIN_AK21 -to ddr4_mem[0].dqs_n[1] +set_location_assignment PIN_AJ24 -to ddr4_mem[0].dbi_n[1] +set_location_assignment PIN_AL22 -to ddr4_mem[0].dq[8] +set_location_assignment PIN_AJ23 -to ddr4_mem[0].dq[9] +set_location_assignment PIN_AJ26 -to ddr4_mem[0].dq[10] +set_location_assignment PIN_AK23 -to ddr4_mem[0].dq[11] +set_location_assignment PIN_AL20 -to ddr4_mem[0].dq[12] +set_location_assignment PIN_AH24 -to ddr4_mem[0].dq[13] +set_location_assignment PIN_AJ25 -to ddr4_mem[0].dq[14] +set_location_assignment PIN_AL21 -to ddr4_mem[0].dq[15] + +# DDR4 CH2 - DQS2 +set_location_assignment PIN_AM18 -to ddr4_mem[0].dqs[2] +set_location_assignment PIN_AN18 -to ddr4_mem[0].dqs_n[2] +set_location_assignment PIN_AR18 -to ddr4_mem[0].dbi_n[2] +set_location_assignment PIN_AT17 -to ddr4_mem[0].dq[16] +set_location_assignment PIN_AR16 -to ddr4_mem[0].dq[17] +set_location_assignment PIN_AT16 -to ddr4_mem[0].dq[18] +set_location_assignment PIN_AP18 -to ddr4_mem[0].dq[19] +set_location_assignment PIN_AU17 -to ddr4_mem[0].dq[20] +set_location_assignment PIN_AP19 -to ddr4_mem[0].dq[21] +set_location_assignment PIN_AT19 -to ddr4_mem[0].dq[22] +set_location_assignment PIN_AR19 -to ddr4_mem[0].dq[23] + +# DDR4 CH2 - DQS3 +set_location_assignment PIN_BB18 -to ddr4_mem[0].dqs[3] +set_location_assignment PIN_BB17 -to ddr4_mem[0].dqs_n[3] +set_location_assignment PIN_AV16 -to ddr4_mem[0].dbi_n[3] +set_location_assignment PIN_AY17 -to ddr4_mem[0].dq[24] +set_location_assignment PIN_AY16 -to ddr4_mem[0].dq[25] +set_location_assignment PIN_AU18 -to ddr4_mem[0].dq[26] +set_location_assignment PIN_AY18 -to ddr4_mem[0].dq[27] +set_location_assignment PIN_AV18 -to ddr4_mem[0].dq[28] +set_location_assignment PIN_AW16 -to ddr4_mem[0].dq[29] +set_location_assignment PIN_AW18 -to ddr4_mem[0].dq[30] +set_location_assignment PIN_BA17 -to ddr4_mem[0].dq[31] + +# DDR4 CH2 - DQS4 +set_location_assignment PIN_BB25 -to ddr4_mem[0].dqs[4] +set_location_assignment PIN_BA25 -to ddr4_mem[0].dqs_n[4] +set_location_assignment PIN_BA27 -to ddr4_mem[0].dbi_n[4] +set_location_assignment PIN_BB24 -to ddr4_mem[0].dq[32] +set_location_assignment PIN_BA26 -to ddr4_mem[0].dq[33] +set_location_assignment PIN_AV27 -to ddr4_mem[0].dq[34] +set_location_assignment PIN_AY27 -to ddr4_mem[0].dq[35] +set_location_assignment PIN_BA24 -to ddr4_mem[0].dq[36] +set_location_assignment PIN_AY26 -to ddr4_mem[0].dq[37] +set_location_assignment PIN_AV26 -to ddr4_mem[0].dq[38] +set_location_assignment PIN_AW26 -to ddr4_mem[0].dq[39] + +# DDR4 CH2 - DQS5 +set_location_assignment PIN_AT27 -to ddr4_mem[0].dqs[5] +set_location_assignment PIN_AU27 -to ddr4_mem[0].dqs_n[5] +set_location_assignment PIN_AV25 -to ddr4_mem[0].dbi_n[5] +set_location_assignment PIN_AW24 -to ddr4_mem[0].dq[40] +set_location_assignment PIN_AT26 -to ddr4_mem[0].dq[41] +set_location_assignment PIN_AT24 -to ddr4_mem[0].dq[42] +set_location_assignment PIN_AU24 -to ddr4_mem[0].dq[43] +set_location_assignment PIN_AY24 -to ddr4_mem[0].dq[44] +set_location_assignment PIN_AU25 -to ddr4_mem[0].dq[45] +set_location_assignment PIN_AT25 -to ddr4_mem[0].dq[46] +set_location_assignment PIN_AR27 -to ddr4_mem[0].dq[47] + +# DDR4 CH2 - DQS6 +set_location_assignment PIN_AP29 -to ddr4_mem[0].dqs[6] +set_location_assignment PIN_AR30 -to ddr4_mem[0].dqs_n[6] +set_location_assignment PIN_AL30 -to ddr4_mem[0].dbi_n[6] +set_location_assignment PIN_AT29 -to ddr4_mem[0].dq[48] +set_location_assignment PIN_AR29 -to ddr4_mem[0].dq[49] +set_location_assignment PIN_AP30 -to ddr4_mem[0].dq[50] +set_location_assignment PIN_AN30 -to ddr4_mem[0].dq[51] +set_location_assignment PIN_AP28 -to ddr4_mem[0].dq[52] +set_location_assignment PIN_AR28 -to ddr4_mem[0].dq[53] +set_location_assignment PIN_AT30 -to ddr4_mem[0].dq[54] +set_location_assignment PIN_AT31 -to ddr4_mem[0].dq[55] + +# DDR4 CH2 - DQS7 +set_location_assignment PIN_AK28 -to ddr4_mem[0].dqs[7] +set_location_assignment PIN_AK27 -to ddr4_mem[0].dqs_n[7] +set_location_assignment PIN_AK29 -to ddr4_mem[0].dbi_n[7] +set_location_assignment PIN_AM28 -to ddr4_mem[0].dq[56] +set_location_assignment PIN_AL29 -to ddr4_mem[0].dq[57] +set_location_assignment PIN_AN28 -to ddr4_mem[0].dq[58] +set_location_assignment PIN_AP26 -to ddr4_mem[0].dq[59] +set_location_assignment PIN_AL27 -to ddr4_mem[0].dq[60] +set_location_assignment PIN_AM29 -to ddr4_mem[0].dq[61] +set_location_assignment PIN_AN27 -to ddr4_mem[0].dq[62] +set_location_assignment PIN_AM27 -to ddr4_mem[0].dq[63] + +# DDR4 CH2 - DQS8 +set_location_assignment PIN_AU19 -to ddr4_mem[0].dqs[8] +set_location_assignment PIN_AU20 -to ddr4_mem[0].dqs_n[8] +set_location_assignment PIN_AT21 -to ddr4_mem[0].dbi_n[8] +set_location_assignment PIN_AN22 -to ddr4_mem[0].dq[64] +set_location_assignment PIN_AN20 -to ddr4_mem[0].dq[65] +set_location_assignment PIN_AM22 -to ddr4_mem[0].dq[66] +set_location_assignment PIN_AR21 -to ddr4_mem[0].dq[67] +set_location_assignment PIN_AM23 -to ddr4_mem[0].dq[68] +set_location_assignment PIN_AP20 -to ddr4_mem[0].dq[69] +set_location_assignment PIN_AN21 -to ddr4_mem[0].dq[70] +set_location_assignment PIN_AP21 -to ddr4_mem[0].dq[71] + +#========================================================= +# DDR4 CH3 (Upper 2) - A/C +#========================================================= +set_location_assignment PIN_K31 -to ddr4_mem[1].ck +set_location_assignment PIN_L30 -to ddr4_mem[1].ck_n +set_location_assignment PIN_M28 -to ddr4_mem[1].a[0] +set_location_assignment PIN_N28 -to ddr4_mem[1].a[1] +set_location_assignment PIN_R26 -to ddr4_mem[1].a[2] +set_location_assignment PIN_P26 -to ddr4_mem[1].a[3] +set_location_assignment PIN_P28 -to ddr4_mem[1].a[4] +set_location_assignment PIN_R27 -to ddr4_mem[1].a[5] +set_location_assignment PIN_K26 -to ddr4_mem[1].a[6] +set_location_assignment PIN_K27 -to ddr4_mem[1].a[7] +set_location_assignment PIN_N26 -to ddr4_mem[1].a[8] +set_location_assignment PIN_N27 -to ddr4_mem[1].a[9] +set_location_assignment PIN_L27 -to ddr4_mem[1].a[10] +set_location_assignment PIN_M27 -to ddr4_mem[1].a[11] +set_location_assignment PIN_J29 -to ddr4_mem[1].a[12] +set_location_assignment PIN_J28 -to ddr4_mem[1].a[13] +set_location_assignment PIN_K28 -to ddr4_mem[1].a[14] +set_location_assignment PIN_H31 -to ddr4_mem[1].a[15] +set_location_assignment PIN_H30 -to ddr4_mem[1].a[16] +set_location_assignment PIN_H28 -to ddr4_mem[1].a[17] +set_location_assignment PIN_L29 -to ddr4_mem[1].act_n +set_location_assignment PIN_G27 -to ddr4_mem[1].ba[1] +set_location_assignment PIN_H27 -to ddr4_mem[1].ba[0] +set_location_assignment PIN_N30 -to ddr4_mem[1].bg[1] +set_location_assignment PIN_F27 -to ddr4_mem[1].bg[0] +set_location_assignment PIN_M30 -to ddr4_mem[1].cke +set_location_assignment PIN_M29 -to ddr4_mem[1].cs_n +set_location_assignment PIN_K30 -to ddr4_mem[1].odt +set_location_assignment PIN_P31 -to ddr4_mem[1].reset_n +set_location_assignment PIN_P29 -to ddr4_mem[1].par +set_location_assignment PIN_P30 -to ddr4_mem[1].alert_n +set_location_assignment PIN_J30 -to ddr4_mem[1].oct_rzqin +set_location_assignment PIN_D27 -to ddr4_mem[1].ref_clk + +# DDR4 CH3 - DQS0 +set_location_assignment PIN_T23 -to ddr4_mem[1].dqs[0] +set_location_assignment PIN_R24 -to ddr4_mem[1].dqs_n[0] +set_location_assignment PIN_K23 -to ddr4_mem[1].dbi_n[0] +set_location_assignment PIN_N23 -to ddr4_mem[1].dq[0] +set_location_assignment PIN_P23 -to ddr4_mem[1].dq[1] +set_location_assignment PIN_M22 -to ddr4_mem[1].dq[2] +set_location_assignment PIN_M23 -to ddr4_mem[1].dq[3] +set_location_assignment PIN_P24 -to ddr4_mem[1].dq[4] +set_location_assignment PIN_N22 -to ddr4_mem[1].dq[5] +set_location_assignment PIN_L22 -to ddr4_mem[1].dq[6] +set_location_assignment PIN_M24 -to ddr4_mem[1].dq[7] + +# DDR4 CH3 - DQS1 +set_location_assignment PIN_N25 -to ddr4_mem[1].dqs[1] +set_location_assignment PIN_P25 -to ddr4_mem[1].dqs_n[1] +set_location_assignment PIN_L25 -to ddr4_mem[1].dbi_n[1] +set_location_assignment PIN_G25 -to ddr4_mem[1].dq[8] +set_location_assignment PIN_H26 -to ddr4_mem[1].dq[9] +set_location_assignment PIN_J24 -to ddr4_mem[1].dq[10] +set_location_assignment PIN_J25 -to ddr4_mem[1].dq[11] +set_location_assignment PIN_G24 -to ddr4_mem[1].dq[12] +set_location_assignment PIN_H25 -to ddr4_mem[1].dq[13] +set_location_assignment PIN_L24 -to ddr4_mem[1].dq[14] +set_location_assignment PIN_K24 -to ddr4_mem[1].dq[15] + +# DDR4 CH3 - DQS2 +set_location_assignment PIN_B24 -to ddr4_mem[1].dqs[2] +set_location_assignment PIN_B25 -to ddr4_mem[1].dqs_n[2] +set_location_assignment PIN_C27 -to ddr4_mem[1].dbi_n[2] +set_location_assignment PIN_E26 -to ddr4_mem[1].dq[16] +set_location_assignment PIN_D26 -to ddr4_mem[1].dq[17] +set_location_assignment PIN_D25 -to ddr4_mem[1].dq[18] +set_location_assignment PIN_C25 -to ddr4_mem[1].dq[19] +set_location_assignment PIN_F26 -to ddr4_mem[1].dq[20] +set_location_assignment PIN_F25 -to ddr4_mem[1].dq[21] +set_location_assignment PIN_A24 -to ddr4_mem[1].dq[22] +set_location_assignment PIN_A25 -to ddr4_mem[1].dq[23] + +# DDR4 CH3 - DQS3 +set_location_assignment PIN_C23 -to ddr4_mem[1].dqs[3] +set_location_assignment PIN_C22 -to ddr4_mem[1].dqs_n[3] +set_location_assignment PIN_D24 -to ddr4_mem[1].dbi_n[3] +set_location_assignment PIN_B23 -to ddr4_mem[1].dq[24] +set_location_assignment PIN_G23 -to ddr4_mem[1].dq[25] +set_location_assignment PIN_E23 -to ddr4_mem[1].dq[26] +set_location_assignment PIN_B22 -to ddr4_mem[1].dq[27] +set_location_assignment PIN_D23 -to ddr4_mem[1].dq[28] +set_location_assignment PIN_F24 -to ddr4_mem[1].dq[29] +set_location_assignment PIN_A21 -to ddr4_mem[1].dq[30] +set_location_assignment PIN_A22 -to ddr4_mem[1].dq[31] + +# DDR4 CH3 - DQS4 +set_location_assignment PIN_D8 -to ddr4_mem[1].dqs[4] +set_location_assignment PIN_C8 -to ddr4_mem[1].dqs_n[4] +set_location_assignment PIN_C10 -to ddr4_mem[1].dbi_n[4] +set_location_assignment PIN_D11 -to ddr4_mem[1].dq[32] +set_location_assignment PIN_D9 -to ddr4_mem[1].dq[33] +set_location_assignment PIN_F12 -to ddr4_mem[1].dq[34] +set_location_assignment PIN_G12 -to ddr4_mem[1].dq[35] +set_location_assignment PIN_E12 -to ddr4_mem[1].dq[36] +set_location_assignment PIN_D10 -to ddr4_mem[1].dq[37] +set_location_assignment PIN_E11 -to ddr4_mem[1].dq[38] +set_location_assignment PIN_F11 -to ddr4_mem[1].dq[39] + +# DDR4 CH3 - DQS5 +set_location_assignment PIN_N17 -to ddr4_mem[1].dqs[5] +set_location_assignment PIN_M17 -to ddr4_mem[1].dqs_n[5] +set_location_assignment PIN_M18 -to ddr4_mem[1].dbi_n[5] +set_location_assignment PIN_H16 -to ddr4_mem[1].dq[40] +set_location_assignment PIN_L17 -to ddr4_mem[1].dq[41] +set_location_assignment PIN_F17 -to ddr4_mem[1].dq[42] +set_location_assignment PIN_F16 -to ddr4_mem[1].dq[43] +set_location_assignment PIN_H17 -to ddr4_mem[1].dq[44] +set_location_assignment PIN_K17 -to ddr4_mem[1].dq[45] +set_location_assignment PIN_E16 -to ddr4_mem[1].dq[46] +set_location_assignment PIN_G17 -to ddr4_mem[1].dq[47] + +# DDR4 CH3 - DQS6 +set_location_assignment PIN_R17 -to ddr4_mem[1].dqs[6] +set_location_assignment PIN_P18 -to ddr4_mem[1].dqs_n[6] +set_location_assignment PIN_M15 -to ddr4_mem[1].dbi_n[6] +set_location_assignment PIN_K16 -to ddr4_mem[1].dq[48] +set_location_assignment PIN_L15 -to ddr4_mem[1].dq[49] +set_location_assignment PIN_P16 -to ddr4_mem[1].dq[50] +set_location_assignment PIN_N16 -to ddr4_mem[1].dq[51] +set_location_assignment PIN_J16 -to ddr4_mem[1].dq[52] +set_location_assignment PIN_L16 -to ddr4_mem[1].dq[53] +set_location_assignment PIN_P15 -to ddr4_mem[1].dq[54] +set_location_assignment PIN_R16 -to ddr4_mem[1].dq[55] + +# DDR4 CH3 - DQS7 +set_location_assignment PIN_E14 -to ddr4_mem[1].dqs[7] +set_location_assignment PIN_F14 -to ddr4_mem[1].dqs_n[7] +set_location_assignment PIN_D15 -to ddr4_mem[1].dbi_n[7] +set_location_assignment PIN_H15 -to ddr4_mem[1].dq[56] +set_location_assignment PIN_F15 -to ddr4_mem[1].dq[57] +set_location_assignment PIN_G13 -to ddr4_mem[1].dq[58] +set_location_assignment PIN_G14 -to ddr4_mem[1].dq[59] +set_location_assignment PIN_J15 -to ddr4_mem[1].dq[60] +set_location_assignment PIN_G15 -to ddr4_mem[1].dq[61] +set_location_assignment PIN_E13 -to ddr4_mem[1].dq[62] +set_location_assignment PIN_D13 -to ddr4_mem[1].dq[63] + +# DDR4 CH3 - DQS8 +set_location_assignment PIN_J23 -to ddr4_mem[1].dqs[8] +set_location_assignment PIN_H23 -to ddr4_mem[1].dqs_n[8] +set_location_assignment PIN_E21 -to ddr4_mem[1].dbi_n[8] +set_location_assignment PIN_C21 -to ddr4_mem[1].dq[64] +set_location_assignment PIN_D21 -to ddr4_mem[1].dq[65] +set_location_assignment PIN_J21 -to ddr4_mem[1].dq[66] +set_location_assignment PIN_H21 -to ddr4_mem[1].dq[67] +set_location_assignment PIN_F22 -to ddr4_mem[1].dq[68] +set_location_assignment PIN_E22 -to ddr4_mem[1].dq[69] +set_location_assignment PIN_H22 -to ddr4_mem[1].dq[70] +set_location_assignment PIN_G22 -to ddr4_mem[1].dq[71] diff --git a/syn/setup/eth_afu_if_design_files.tcl b/syn/setup/eth_afu_if_design_files.tcl new file mode 100644 index 0000000..6cde44d --- /dev/null +++ b/syn/setup/eth_afu_if_design_files.tcl @@ -0,0 +1,11 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# +# Ethernet interfaces passed to AFUs. These files are used by both FIM and PR builds. +# +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/includes/ofs_fim_eth_plat_if_pkg.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/inc/ofs_fim_eth_if_pkg.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/inc/ofs_fim_eth_if.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/inc/ofs_fim_eth_avst_if_pkg.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/inc/ofs_fim_eth_avst_if.sv diff --git a/syn/setup/eth_design_files.tcl b/syn/setup/eth_design_files.tcl new file mode 100644 index 0000000..bcb8b82 --- /dev/null +++ b/syn/setup/eth_design_files.tcl @@ -0,0 +1,44 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# +# Ethernet +#-------------------- + +set_global_assignment -name SEARCH_PATH $::env(BUILD_ROOT_REL)/ + +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/lib/ofs_fim_eth_plat_clocks_noprune.sv +#set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/d5005/eth/s10/includes/ofs_fim_eth_plat_if_pkg.sv + +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/lib/bridge/ofs_fim_eth_afu_avst_to_fim_axis_bridge.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/lib/bridge/ofs_fim_eth_sb_afu_avst_to_fim_axis_bridge.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/lib/bridge/ofs_fim_eth_axis_connect.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/lib/pipeline/pr_eth_axis_if_reg.sv + +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/hssi_csr_pkg.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/hssi_stats_sync.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/av_axi_st_bridge.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/altera_eth_10g_mac_base_r_wrap.v +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/resync.v +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/mm_ctrl_xcvr.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/hssi_csr.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/eth_top.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/eth_ac_wrapper.sv + +set_global_assignment -name QSYS_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/ip/address_decoder/address_decode.qsys +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_clk_csr.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_master_0.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_merlin_master_translator_0.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_mm_to_mac.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_mm_to_phy.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_rx_xcvr_clk.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_tx_xcvr_clk.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/ip/address_decoder/ip/address_decode/address_decode_tx_xcvr_half_clk.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/ip/mac/altera_eth_10g_mac.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/ip/phy/altera_eth_10gbaser_phy.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/ip/pll_atxpll/altera_xcvr_atx_pll_ip.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/ip/pll_mpll/pll.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/ipss/hssi/s10/ip/xcvr_reset_controller/reset_control.ip + +# SDC +set_global_assignment -name SDC_FILE $::env(BUILD_ROOT_REL)/syn/setup/eth_top.sdc diff --git a/syn/setup/eth_location.tcl b/syn/setup/eth_location.tcl new file mode 100644 index 0000000..ea5dc68 --- /dev/null +++ b/syn/setup/eth_location.tcl @@ -0,0 +1,71 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# Description +#----------------------------------------------------------------------------- +# +# HSSI pin and location assignments +# +#----------------------------------------------------------------------------- +##################################################### +# QSFP / Ethernet +##################################################### +# Pin and location assignments +set_location_assignment PIN_Y28 -to qsfp_3v0_port_en +set_location_assignment PIN_W28 -to qsfp_3v0_port_int_n + +set_location_assignment PIN_H34 -to qsfp1_644_53125_clk +set_location_assignment PIN_F38 -to qsfp1_tx_serial[0] +set_location_assignment PIN_C32 -to qsfp1_rx_serial[0] +set_location_assignment PIN_C40 -to qsfp1_tx_serial[1] +set_location_assignment PIN_B30 -to qsfp1_rx_serial[1] +set_location_assignment PIN_B38 -to qsfp1_tx_serial[2] +set_location_assignment PIN_A28 -to qsfp1_rx_serial[2] +set_location_assignment PIN_A36 -to qsfp1_tx_serial[3] +set_location_assignment PIN_D30 -to qsfp1_rx_serial[3] + +# set_location_assignment PIN_AD34 -to qsfp0_644_53125_clk +# set_location_assignment PIN_AG40 -to qsfp0_tx_serial[0] +# set_location_assignment PIN_AG36 -to qsfp0_rx_serial[0] +# set_location_assignment PIN_AF42 -to qsfp0_tx_serial[1] +# set_location_assignment PIN_AD38 -to qsfp0_rx_serial[1] +# set_location_assignment PIN_AD42 -to qsfp0_tx_serial[2] +# set_location_assignment PIN_AB38 -to qsfp0_rx_serial[2] +# set_location_assignment PIN_AC40 -to qsfp0_tx_serial[3] +# set_location_assignment PIN_AC36 -to qsfp0_rx_serial[3] + +#set_location_assignment PIN_AG29 -to ETH_RefClk +#set_instance_assignment -name IO_STANDARD LVDS -to ETH_RefClk +#set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to ETH_RefClk + +##################################################### +# Fitter assignments +set_instance_assignment -name GXB_0PPM_CORECLK ON -to qsfp1_rx_serial -entity ofs_fim +set_instance_assignment -name GXB_0PPM_CORECLK ON -to qsfp1_tx_serial -entity ofs_fim +set_instance_assignment -name GXB_0PPM_CORECLK ON -to qsfp1_rx_serial[*] -entity ofs_fim +set_instance_assignment -name GXB_0PPM_CORECLK ON -to qsfp1_tx_serial[*] -entity ofs_fim +set_instance_assignment -name GXB_0PPM_CORECLK ON -to qsfp0_rx_serial -entity ofs_fim +set_instance_assignment -name GXB_0PPM_CORECLK ON -to qsfp0_tx_serial -entity ofs_fim +set_instance_assignment -name GXB_0PPM_CORECLK ON -to qsfp0_rx_serial[*] -entity ofs_fim +set_instance_assignment -name GXB_0PPM_CORECLK ON -to qsfp0_tx_serial[*] -entity ofs_fim +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to qsfp1_rx_serial -entity ofs_fim +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to qsfp1_tx_serial -entity ofs_fim +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to qsfp1_rx_serial[*] -entity ofs_fim +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to qsfp1_tx_serial[*] -entity ofs_fim +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to qsfp1_rx_serial[*] -entity ofs_fim +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to qsfp1_tx_serial[*] -entity ofs_fim +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to qsfp0_rx_serial -entity ofs_fim +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to qsfp0_tx_serial -entity ofs_fim +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to qsfp0_rx_serial[*] -entity ofs_fim +set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to qsfp0_tx_serial[*] -entity ofs_fim +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to qsfp0_rx_serial[*] -entity ofs_fim +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to qsfp0_tx_serial[*] -entity ofs_fim +set_instance_assignment -name IO_STANDARD LVDS -to qsfp1_644_53125_clk -entity ofs_fim +set_instance_assignment -name IO_STANDARD LVDS -to "qsfp1_644_53125_clk(n)" -entity ofs_fim +set_instance_assignment -name IO_STANDARD LVDS -to qsfp0_644_53125_clk -entity ofs_fim +set_instance_assignment -name IO_STANDARD LVDS -to "qsfp0_644_53125_clk(n)" -entity ofs_fim +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to qsfp_3v0_port_en -entity ofs_fim +set_instance_assignment -name USE_AS_3V_GPIO ON -to qsfp_3v0_port_en +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to qsfp_3v0_port_int_n -entity ofs_fim +set_instance_assignment -name USE_AS_3V_GPIO ON -to qsfp_3v0_port_int_n + diff --git a/syn/setup/eth_top.sdc b/syn/setup/eth_top.sdc new file mode 100755 index 0000000..f52d2cf --- /dev/null +++ b/syn/setup/eth_top.sdc @@ -0,0 +1,67 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +#----------------------------------------------------------------------------- +# Description +#----------------------------------------------------------------------------- +# +# Eth Top SDC +# +#----------------------------------------------------------------------------- + +#-------------------- +# Common procedures +#-------------------- +proc add_reset_sync_sdc { pin_name } { + set_max_delay -to [get_pins $pin_name] 100.000 + set_min_delay -to [get_pins $pin_name] -100.000 + #set_max_skew -to [get_pins $pin_name] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 +} + +proc add_sync_sdc { name } { + set_max_delay -to [get_keepers $name] 100.000 + set_min_delay -to [get_keepers $name] -100.000 +} + +#--------------------------------------------- +# CDC constraints for reset synchronizers +#--------------------------------------------- + +#--------------------------------------------- +# CDC constraints for synchronizers +#--------------------------------------------- +add_sync_sdc {eth_ac_wrapper|eth_top|*|altera_reset_synchronizer_int_chain[*]} +add_sync_sdc {eth_ac_wrapper|eth_top|*|altera_reset_synchronizer_int_chain_out} +add_sync_sdc {eth_ac_wrapper|eth_top|*|resync_chains[*].synchronizer_nocut|din_s1} + +add_sync_sdc {*|he_hssi_top_inst|*|resync_chains[*].synchronizer_nocut|din_s1} + +set_false_path -from {rst_ctrl|rst_clk1x_sync|dreg[*]} -to {*|he_hssi_top_inst|GenRstSync[0].tx_reset_synchronizer|resync_chains[0].synchronizer|dreg[*]} +set_false_path -from {rst_ctrl|rst_clk1x_sync|dreg[*]} -to {*|he_hssi_top_inst|GenRstSync[0].tx_reset_synchronizer|resync_chains[0].synchronizer|din_s1} -setup + + +# 100G +set CLK100 [get_clocks sys_pll|iopll_0_clk_100M] +set CLK250 [get_clocks sys_pll|iopll_0_clk_250M] +set TX_CORE_CLK [get_clocks eth_ac_wrapper|eth_top|CHANNEL[0].eth_channel|ll_100g_ethernet_inst|alt_e100s10_0|xcvr|tx_clkout2|ch1] +set RX_CORE_CLK [get_clocks eth_ac_wrapper|eth_top|CHANNEL[0].eth_channel|ll_100g_ethernet_inst|alt_e100s10_0|xcvr|rx_clkout2|ch1] + +# RSFEC clocks +set RX_RS_CORE_CLK [get_clocks eth_ac_wrapper|eth_top|CHANNEL[0].eth_channel|ll_100g_ethernet_inst|alt_e100s10_0|WITH_FEC.fecpll|RXIOPLL_INST.fecrxpll|alt_e100s10ex_iopll_rx_outclk0] +set RX_RS_CORE_NCK [get_clocks eth_ac_wrapper|eth_top|CHANNEL[0].eth_channel|ll_100g_ethernet_inst|alt_e100s10_0|WITH_FEC.fecpll|RXIOPLL_INST.fecrxpll|alt_e100s10ex_iopll_rx_n_cnt_clk] +set TX_RS_CORE_CLK [get_clocks eth_ac_wrapper|eth_top|CHANNEL[0].eth_channel|ll_100g_ethernet_inst|alt_e100s10_0|WITH_FEC.fecpll|TXPLL_IN.TXFPLL_INST.tx_pll_gen.fectxpll|clkdiv_output_div1] + +set_clock_groups -asynchronous -group -group $TX_CORE_CLK -group $CLK100 +set_clock_groups -asynchronous -group -group $TX_CORE_CLK -group $CLK250 +set_clock_groups -asynchronous -group -group $RX_CORE_CLK -group $CLK100 + +set_clock_groups -asynchronous -group $TX_CORE_CLK -group $RX_CORE_CLK -group -group $CLK100 -group $RX_RS_CORE_CLK -group $TX_RS_CORE_CLK -group $RX_RS_CORE_NCK + +for {set chNum 0} {$chNum < 4} {incr chNum} { + set RX_CLK [get_clocks eth_ac_wrapper|eth_top|CHANNEL[0].eth_channel|ll_100g_ethernet_inst|alt_e100s10_0|xcvr|rx_pcs_x2_clk|ch$chNum] + set TX_CLK [get_clocks eth_ac_wrapper|eth_top|CHANNEL[0].eth_channel|ll_100g_ethernet_inst|alt_e100s10_0|xcvr|tx_pcs_x2_clk|ch$chNum] + + set_clock_groups -asynchronous -group $TX_CLK -group $CLK100 -group + set_clock_groups -asynchronous -group $RX_CLK -group $CLK100 -group + +} diff --git a/syn/setup/he_lb.sdc b/syn/setup/he_lb.sdc new file mode 100644 index 0000000..a6e9bd0 --- /dev/null +++ b/syn/setup/he_lb.sdc @@ -0,0 +1,19 @@ +# Copyright (C) 2021 Intel Corporation +# SPDX-License-Identifier: MIT + +#************************************************************** +# Set Maximum Delay +# Set Minimum Delay +#************************************************************** +set_multicycle_path -from [get_cells {afu_top|*|he_lb_csr|*}] -to [get_cells {afu_top|*|he_lb_req|csr_*}] -setup -end 2 +set_multicycle_path -from [get_cells {afu_top|*|he_lb_csr|*}] -to [get_cells {afu_top|*|he_lb_req|csr_*}] -hold -end 1 + +set_multicycle_path -from [get_cells {afu_top|*|he_lb_req|csr_*}] -to [get_cells {afu_top|*|mode_*|*}] -setup -end 2 +set_multicycle_path -from [get_cells {afu_top|*|he_lb_req|csr_*}] -to [get_cells {afu_top|*|mode_*|*}] -hold -end 1 + +set_max_delay -through {*he_lb_req*re2csr_num_reads*} -to {*he_lb_csr*} 2.0 +set_max_delay -through {*he_lb_req*re2csr_num_writes*} -to {*he_lb_csr*} 2.0 +set_max_delay -through {*he_lb_req*re2csr_num_rdpend*} -to {*he_lb_csr*} 2.0 +set_max_delay -through {*he_lb_req*re2csr_num_wrpend*} -to {*he_lb_csr*} 2.0 +set_max_delay -through {*he_lb_req*re2csr_error*} -to {*he_lb_csr*} 2.0 + diff --git a/syn/setup/mem_design_files.tcl b/syn/setup/mem_design_files.tcl new file mode 100644 index 0000000..538eb2f --- /dev/null +++ b/syn/setup/mem_design_files.tcl @@ -0,0 +1,38 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +#-------------------- +# Packages +#-------------------- +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/d5005/mem/rtl/mc_ha_pkg.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/mem/includes/ofs_fim_emif_if.sv + +#-------------------- +# EMIF IP +#-------------------- +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/ipss/d5005/mem/qip/emif_8GB_2400/emif_8GB_2400.ip + +#-------------------- +# Other IP +#-------------------- +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/ipss/d5005/mem/qip/reqfifo/reqfifo.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/ipss/d5005/mem/qip/rspfifo/rspfifo.ip + + +#-------------------- +# Memory Controller RTL +#-------------------- +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/mem/mc_top.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/mem/mc_channel.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/mem/mc_csr.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/mem/mc_emif_poison.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/mem/mc_mmr_ctrl.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/mem/mc_rmw_shim.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/mem/mem_intf.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/mem/qip/emif_8GB_2400/mem_wrapper.sv + +#---------- +# SDC +#---------- +#set_global_assignment -name SDC_FILE ../../syn/mem/sdc/s10/mc_top.sdc + diff --git a/syn/setup/mem_location.tcl b/syn/setup/mem_location.tcl new file mode 100644 index 0000000..83850c6 --- /dev/null +++ b/syn/setup/mem_location.tcl @@ -0,0 +1,550 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# Description +#----------------------------------------------------------------------------- +# +# DDR pin and location assignments +# +#----------------------------------------------------------------------------- +#========================================================= +# DDR4 CH0 (Lower 2) - A/C +#========================================================= +set_location_assignment PIN_AU22 -to ddr4_mem[0].ck +set_location_assignment PIN_AV22 -to ddr4_mem[0].ck_n +set_location_assignment PIN_AR22 -to ddr4_mem[0].act_n +set_location_assignment PIN_AV23 -to ddr4_mem[0].cke +set_location_assignment PIN_AT22 -to ddr4_mem[0].cs_n +set_location_assignment PIN_BB23 -to ddr4_mem[0].odt +set_location_assignment PIN_AY22 -to ddr4_mem[0].reset_n +set_location_assignment PIN_AW23 -to ddr4_mem[0].par +set_location_assignment PIN_AY23 -to ddr4_mem[0].alert_n +set_location_assignment PIN_BA21 -to ddr4_mem[0].oct_rzqin +set_location_assignment PIN_AY19 -to ddr4_mem[0].ref_clk +set_location_assignment PIN_AM25 -to ddr4_mem[0].a[0] +set_location_assignment PIN_AN25 -to ddr4_mem[0].a[1] +set_location_assignment PIN_AP24 -to ddr4_mem[0].a[2] +set_location_assignment PIN_AP25 -to ddr4_mem[0].a[3] +set_location_assignment PIN_AL24 -to ddr4_mem[0].a[4] +set_location_assignment PIN_AM24 -to ddr4_mem[0].a[5] +set_location_assignment PIN_AL26 -to ddr4_mem[0].a[6] +set_location_assignment PIN_AL25 -to ddr4_mem[0].a[7] +set_location_assignment PIN_AP23 -to ddr4_mem[0].a[8] +set_location_assignment PIN_AN23 -to ddr4_mem[0].a[9] +set_location_assignment PIN_AR23 -to ddr4_mem[0].a[10] +set_location_assignment PIN_AR24 -to ddr4_mem[0].a[11] +set_location_assignment PIN_AY21 -to ddr4_mem[0].a[12] +set_location_assignment PIN_BB19 -to ddr4_mem[0].a[13] +set_location_assignment PIN_BA19 -to ddr4_mem[0].a[14] +set_location_assignment PIN_AW21 -to ddr4_mem[0].a[15] +set_location_assignment PIN_AV21 -to ddr4_mem[0].a[16] +set_location_assignment PIN_BB20 -to ddr4_mem[0].a[17] +set_location_assignment PIN_AW20 -to ddr4_mem[0].ba[1] +set_location_assignment PIN_BA20 -to ddr4_mem[0].ba[0] +set_location_assignment PIN_BA22 -to ddr4_mem[0].bg[1] +set_location_assignment PIN_AV20 -to ddr4_mem[0].bg[0] +set_location_assignment PIN_AH18 -to ddr4_mem[0].dqs[0] +set_location_assignment PIN_AJ18 -to ddr4_mem[0].dqs_n[0] +set_location_assignment PIN_AJ19 -to ddr4_mem[0].dqs[9] +set_location_assignment PIN_AK22 -to ddr4_mem[0].dqs[1] +set_location_assignment PIN_AK21 -to ddr4_mem[0].dqs_n[1] +set_location_assignment PIN_AJ24 -to ddr4_mem[0].dqs[10] +set_location_assignment PIN_AM18 -to ddr4_mem[0].dqs[2] +set_location_assignment PIN_AN18 -to ddr4_mem[0].dqs_n[2] +set_location_assignment PIN_AR18 -to ddr4_mem[0].dqs[11] +set_location_assignment PIN_BB18 -to ddr4_mem[0].dqs[3] +set_location_assignment PIN_BB17 -to ddr4_mem[0].dqs_n[3] +set_location_assignment PIN_AV16 -to ddr4_mem[0].dqs[12] +set_location_assignment PIN_BB25 -to ddr4_mem[0].dqs[4] +set_location_assignment PIN_BA25 -to ddr4_mem[0].dqs_n[4] +set_location_assignment PIN_BA27 -to ddr4_mem[0].dqs[13] +set_location_assignment PIN_AT27 -to ddr4_mem[0].dqs[5] +set_location_assignment PIN_AU27 -to ddr4_mem[0].dqs_n[5] +set_location_assignment PIN_AV25 -to ddr4_mem[0].dqs[14] +set_location_assignment PIN_AP29 -to ddr4_mem[0].dqs[6] +set_location_assignment PIN_AR30 -to ddr4_mem[0].dqs_n[6] +set_location_assignment PIN_AL30 -to ddr4_mem[0].dqs[15] +set_location_assignment PIN_AK28 -to ddr4_mem[0].dqs[7] +set_location_assignment PIN_AK27 -to ddr4_mem[0].dqs_n[7] +set_location_assignment PIN_AK29 -to ddr4_mem[0].dqs[16] +set_location_assignment PIN_AU19 -to ddr4_mem[0].dqs[8] +set_location_assignment PIN_AU20 -to ddr4_mem[0].dqs_n[8] +set_location_assignment PIN_AT21 -to ddr4_mem[0].dqs[17] +set_location_assignment PIN_AL17 -to ddr4_mem[0].dq[0] +set_location_assignment PIN_AL19 -to ddr4_mem[0].dq[1] +set_location_assignment PIN_AM17 -to ddr4_mem[0].dq[2] +set_location_assignment PIN_AK17 -to ddr4_mem[0].dq[3] +set_location_assignment PIN_AK19 -to ddr4_mem[0].dq[4] +set_location_assignment PIN_AM20 -to ddr4_mem[0].dq[5] +set_location_assignment PIN_AN17 -to ddr4_mem[0].dq[6] +set_location_assignment PIN_AM19 -to ddr4_mem[0].dq[7] +set_location_assignment PIN_AL22 -to ddr4_mem[0].dq[8] +set_location_assignment PIN_AJ23 -to ddr4_mem[0].dq[9] +set_location_assignment PIN_AJ26 -to ddr4_mem[0].dq[10] +set_location_assignment PIN_AK23 -to ddr4_mem[0].dq[11] +set_location_assignment PIN_AL20 -to ddr4_mem[0].dq[12] +set_location_assignment PIN_AH24 -to ddr4_mem[0].dq[13] +set_location_assignment PIN_AJ25 -to ddr4_mem[0].dq[14] +set_location_assignment PIN_AL21 -to ddr4_mem[0].dq[15] +set_location_assignment PIN_AT17 -to ddr4_mem[0].dq[16] +set_location_assignment PIN_AR16 -to ddr4_mem[0].dq[17] +set_location_assignment PIN_AT16 -to ddr4_mem[0].dq[18] +set_location_assignment PIN_AP18 -to ddr4_mem[0].dq[19] +set_location_assignment PIN_AU17 -to ddr4_mem[0].dq[20] +set_location_assignment PIN_AP19 -to ddr4_mem[0].dq[21] +set_location_assignment PIN_AT19 -to ddr4_mem[0].dq[22] +set_location_assignment PIN_AR19 -to ddr4_mem[0].dq[23] +set_location_assignment PIN_AY17 -to ddr4_mem[0].dq[24] +set_location_assignment PIN_AY16 -to ddr4_mem[0].dq[25] +set_location_assignment PIN_AU18 -to ddr4_mem[0].dq[26] +set_location_assignment PIN_AY18 -to ddr4_mem[0].dq[27] +set_location_assignment PIN_AV18 -to ddr4_mem[0].dq[28] +set_location_assignment PIN_AW16 -to ddr4_mem[0].dq[29] +set_location_assignment PIN_AW18 -to ddr4_mem[0].dq[30] +set_location_assignment PIN_BA17 -to ddr4_mem[0].dq[31] +set_location_assignment PIN_BB24 -to ddr4_mem[0].dq[32] +set_location_assignment PIN_BA26 -to ddr4_mem[0].dq[33] +set_location_assignment PIN_AV27 -to ddr4_mem[0].dq[34] +set_location_assignment PIN_AY27 -to ddr4_mem[0].dq[35] +set_location_assignment PIN_BA24 -to ddr4_mem[0].dq[36] +set_location_assignment PIN_AY26 -to ddr4_mem[0].dq[37] +set_location_assignment PIN_AV26 -to ddr4_mem[0].dq[38] +set_location_assignment PIN_AW26 -to ddr4_mem[0].dq[39] +set_location_assignment PIN_AW24 -to ddr4_mem[0].dq[40] +set_location_assignment PIN_AT26 -to ddr4_mem[0].dq[41] +set_location_assignment PIN_AT24 -to ddr4_mem[0].dq[42] +set_location_assignment PIN_AU24 -to ddr4_mem[0].dq[43] +set_location_assignment PIN_AY24 -to ddr4_mem[0].dq[44] +set_location_assignment PIN_AU25 -to ddr4_mem[0].dq[45] +set_location_assignment PIN_AT25 -to ddr4_mem[0].dq[46] +set_location_assignment PIN_AR27 -to ddr4_mem[0].dq[47] +set_location_assignment PIN_AT29 -to ddr4_mem[0].dq[48] +set_location_assignment PIN_AR29 -to ddr4_mem[0].dq[49] +set_location_assignment PIN_AP30 -to ddr4_mem[0].dq[50] +set_location_assignment PIN_AN30 -to ddr4_mem[0].dq[51] +set_location_assignment PIN_AP28 -to ddr4_mem[0].dq[52] +set_location_assignment PIN_AR28 -to ddr4_mem[0].dq[53] +set_location_assignment PIN_AT30 -to ddr4_mem[0].dq[54] +set_location_assignment PIN_AT31 -to ddr4_mem[0].dq[55] +set_location_assignment PIN_AM28 -to ddr4_mem[0].dq[56] +set_location_assignment PIN_AL29 -to ddr4_mem[0].dq[57] +set_location_assignment PIN_AN28 -to ddr4_mem[0].dq[58] +set_location_assignment PIN_AP26 -to ddr4_mem[0].dq[59] +set_location_assignment PIN_AL27 -to ddr4_mem[0].dq[60] +set_location_assignment PIN_AM29 -to ddr4_mem[0].dq[61] +set_location_assignment PIN_AN27 -to ddr4_mem[0].dq[62] +set_location_assignment PIN_AM27 -to ddr4_mem[0].dq[63] +set_location_assignment PIN_AN22 -to ddr4_mem[0].dq[64] +set_location_assignment PIN_AN20 -to ddr4_mem[0].dq[65] +set_location_assignment PIN_AM22 -to ddr4_mem[0].dq[66] +set_location_assignment PIN_AR21 -to ddr4_mem[0].dq[67] +set_location_assignment PIN_AM23 -to ddr4_mem[0].dq[68] +set_location_assignment PIN_AP20 -to ddr4_mem[0].dq[69] +set_location_assignment PIN_AN21 -to ddr4_mem[0].dq[70] +set_location_assignment PIN_AP21 -to ddr4_mem[0].dq[71] +#========================================================= +# DDR4 CH1 (Upper 2) - A/C +#========================================================= +set_location_assignment PIN_K31 -to ddr4_mem[1].ck +set_location_assignment PIN_L30 -to ddr4_mem[1].ck_n +set_location_assignment PIN_L29 -to ddr4_mem[1].act_n +set_location_assignment PIN_M30 -to ddr4_mem[1].cke +set_location_assignment PIN_M29 -to ddr4_mem[1].cs_n +set_location_assignment PIN_K30 -to ddr4_mem[1].odt +set_location_assignment PIN_P31 -to ddr4_mem[1].reset_n +set_location_assignment PIN_P29 -to ddr4_mem[1].par +set_location_assignment PIN_P30 -to ddr4_mem[1].alert_n +set_location_assignment PIN_J30 -to ddr4_mem[1].oct_rzqin +set_location_assignment PIN_D27 -to ddr4_mem[1].ref_clk +set_location_assignment PIN_M28 -to ddr4_mem[1].a[0] +set_location_assignment PIN_N28 -to ddr4_mem[1].a[1] +set_location_assignment PIN_R26 -to ddr4_mem[1].a[2] +set_location_assignment PIN_P26 -to ddr4_mem[1].a[3] +set_location_assignment PIN_P28 -to ddr4_mem[1].a[4] +set_location_assignment PIN_R27 -to ddr4_mem[1].a[5] +set_location_assignment PIN_K26 -to ddr4_mem[1].a[6] +set_location_assignment PIN_K27 -to ddr4_mem[1].a[7] +set_location_assignment PIN_N26 -to ddr4_mem[1].a[8] +set_location_assignment PIN_N27 -to ddr4_mem[1].a[9] +set_location_assignment PIN_L27 -to ddr4_mem[1].a[10] +set_location_assignment PIN_M27 -to ddr4_mem[1].a[11] +set_location_assignment PIN_J29 -to ddr4_mem[1].a[12] +set_location_assignment PIN_J28 -to ddr4_mem[1].a[13] +set_location_assignment PIN_K28 -to ddr4_mem[1].a[14] +set_location_assignment PIN_H31 -to ddr4_mem[1].a[15] +set_location_assignment PIN_H30 -to ddr4_mem[1].a[16] +set_location_assignment PIN_H28 -to ddr4_mem[1].a[17] +set_location_assignment PIN_G27 -to ddr4_mem[1].ba[1] +set_location_assignment PIN_H27 -to ddr4_mem[1].ba[0] +set_location_assignment PIN_N30 -to ddr4_mem[1].bg[1] +set_location_assignment PIN_F27 -to ddr4_mem[1].bg[0] +set_location_assignment PIN_T23 -to ddr4_mem[1].dqs[0] +set_location_assignment PIN_R24 -to ddr4_mem[1].dqs_n[0] +set_location_assignment PIN_K23 -to ddr4_mem[1].dqs[9] +set_location_assignment PIN_N25 -to ddr4_mem[1].dqs[1] +set_location_assignment PIN_P25 -to ddr4_mem[1].dqs_n[1] +set_location_assignment PIN_L25 -to ddr4_mem[1].dqs[10] +set_location_assignment PIN_B24 -to ddr4_mem[1].dqs[2] +set_location_assignment PIN_B25 -to ddr4_mem[1].dqs_n[2] +set_location_assignment PIN_C27 -to ddr4_mem[1].dqs[11] +set_location_assignment PIN_C23 -to ddr4_mem[1].dqs[3] +set_location_assignment PIN_C22 -to ddr4_mem[1].dqs_n[3] +set_location_assignment PIN_D24 -to ddr4_mem[1].dqs[12] +set_location_assignment PIN_D8 -to ddr4_mem[1].dqs[4] +set_location_assignment PIN_C8 -to ddr4_mem[1].dqs_n[4] +set_location_assignment PIN_C10 -to ddr4_mem[1].dqs[13] +set_location_assignment PIN_N17 -to ddr4_mem[1].dqs[5] +set_location_assignment PIN_M17 -to ddr4_mem[1].dqs_n[5] +set_location_assignment PIN_M18 -to ddr4_mem[1].dqs[14] +set_location_assignment PIN_R17 -to ddr4_mem[1].dqs[6] +set_location_assignment PIN_P18 -to ddr4_mem[1].dqs_n[6] +set_location_assignment PIN_M15 -to ddr4_mem[1].dqs[15] +set_location_assignment PIN_E14 -to ddr4_mem[1].dqs[7] +set_location_assignment PIN_F14 -to ddr4_mem[1].dqs_n[7] +set_location_assignment PIN_D15 -to ddr4_mem[1].dqs[16] +set_location_assignment PIN_J23 -to ddr4_mem[1].dqs[8] +set_location_assignment PIN_H23 -to ddr4_mem[1].dqs_n[8] +set_location_assignment PIN_E21 -to ddr4_mem[1].dqs[17] +set_location_assignment PIN_N23 -to ddr4_mem[1].dq[0] +set_location_assignment PIN_P23 -to ddr4_mem[1].dq[1] +set_location_assignment PIN_M22 -to ddr4_mem[1].dq[2] +set_location_assignment PIN_M23 -to ddr4_mem[1].dq[3] +set_location_assignment PIN_P24 -to ddr4_mem[1].dq[4] +set_location_assignment PIN_N22 -to ddr4_mem[1].dq[5] +set_location_assignment PIN_L22 -to ddr4_mem[1].dq[6] +set_location_assignment PIN_M24 -to ddr4_mem[1].dq[7] +set_location_assignment PIN_G25 -to ddr4_mem[1].dq[8] +set_location_assignment PIN_H26 -to ddr4_mem[1].dq[9] +set_location_assignment PIN_J24 -to ddr4_mem[1].dq[10] +set_location_assignment PIN_J25 -to ddr4_mem[1].dq[11] +set_location_assignment PIN_G24 -to ddr4_mem[1].dq[12] +set_location_assignment PIN_H25 -to ddr4_mem[1].dq[13] +set_location_assignment PIN_L24 -to ddr4_mem[1].dq[14] +set_location_assignment PIN_K24 -to ddr4_mem[1].dq[15] +set_location_assignment PIN_E26 -to ddr4_mem[1].dq[16] +set_location_assignment PIN_D26 -to ddr4_mem[1].dq[17] +set_location_assignment PIN_D25 -to ddr4_mem[1].dq[18] +set_location_assignment PIN_C25 -to ddr4_mem[1].dq[19] +set_location_assignment PIN_F26 -to ddr4_mem[1].dq[20] +set_location_assignment PIN_F25 -to ddr4_mem[1].dq[21] +set_location_assignment PIN_A24 -to ddr4_mem[1].dq[22] +set_location_assignment PIN_A25 -to ddr4_mem[1].dq[23] +set_location_assignment PIN_B23 -to ddr4_mem[1].dq[24] +set_location_assignment PIN_G23 -to ddr4_mem[1].dq[25] +set_location_assignment PIN_E23 -to ddr4_mem[1].dq[26] +set_location_assignment PIN_B22 -to ddr4_mem[1].dq[27] +set_location_assignment PIN_D23 -to ddr4_mem[1].dq[28] +set_location_assignment PIN_F24 -to ddr4_mem[1].dq[29] +set_location_assignment PIN_A21 -to ddr4_mem[1].dq[30] +set_location_assignment PIN_A22 -to ddr4_mem[1].dq[31] +set_location_assignment PIN_D11 -to ddr4_mem[1].dq[32] +set_location_assignment PIN_D9 -to ddr4_mem[1].dq[33] +set_location_assignment PIN_F12 -to ddr4_mem[1].dq[34] +set_location_assignment PIN_G12 -to ddr4_mem[1].dq[35] +set_location_assignment PIN_E12 -to ddr4_mem[1].dq[36] +set_location_assignment PIN_D10 -to ddr4_mem[1].dq[37] +set_location_assignment PIN_E11 -to ddr4_mem[1].dq[38] +set_location_assignment PIN_F11 -to ddr4_mem[1].dq[39] +set_location_assignment PIN_H16 -to ddr4_mem[1].dq[40] +set_location_assignment PIN_L17 -to ddr4_mem[1].dq[41] +set_location_assignment PIN_F17 -to ddr4_mem[1].dq[42] +set_location_assignment PIN_F16 -to ddr4_mem[1].dq[43] +set_location_assignment PIN_H17 -to ddr4_mem[1].dq[44] +set_location_assignment PIN_K17 -to ddr4_mem[1].dq[45] +set_location_assignment PIN_E16 -to ddr4_mem[1].dq[46] +set_location_assignment PIN_G17 -to ddr4_mem[1].dq[47] +set_location_assignment PIN_K16 -to ddr4_mem[1].dq[48] +set_location_assignment PIN_L15 -to ddr4_mem[1].dq[49] +set_location_assignment PIN_P16 -to ddr4_mem[1].dq[50] +set_location_assignment PIN_N16 -to ddr4_mem[1].dq[51] +set_location_assignment PIN_J16 -to ddr4_mem[1].dq[52] +set_location_assignment PIN_L16 -to ddr4_mem[1].dq[53] +set_location_assignment PIN_P15 -to ddr4_mem[1].dq[54] +set_location_assignment PIN_R16 -to ddr4_mem[1].dq[55] +set_location_assignment PIN_H15 -to ddr4_mem[1].dq[56] +set_location_assignment PIN_F15 -to ddr4_mem[1].dq[57] +set_location_assignment PIN_G13 -to ddr4_mem[1].dq[58] +set_location_assignment PIN_G14 -to ddr4_mem[1].dq[59] +set_location_assignment PIN_J15 -to ddr4_mem[1].dq[60] +set_location_assignment PIN_G15 -to ddr4_mem[1].dq[61] +set_location_assignment PIN_E13 -to ddr4_mem[1].dq[62] +set_location_assignment PIN_D13 -to ddr4_mem[1].dq[63] +set_location_assignment PIN_C21 -to ddr4_mem[1].dq[64] +set_location_assignment PIN_D21 -to ddr4_mem[1].dq[65] +set_location_assignment PIN_J21 -to ddr4_mem[1].dq[66] +set_location_assignment PIN_H21 -to ddr4_mem[1].dq[67] +set_location_assignment PIN_F22 -to ddr4_mem[1].dq[68] +set_location_assignment PIN_E22 -to ddr4_mem[1].dq[69] +set_location_assignment PIN_H22 -to ddr4_mem[1].dq[70] +set_location_assignment PIN_G22 -to ddr4_mem[1].dq[71] +#========================================================= +# DDR4 CH1 (Lower 2) - A/C +#========================================================= +#set_location_assignment PIN_AP10 -to mem_ck [2] +#set_location_assignment PIN_AP11 -to mem_ck_n [2] +#set_location_assignment PIN_AR7 -to mem_act_n [2] +#set_location_assignment PIN_AT6 -to mem_cke [2] +#set_location_assignment PIN_AR8 -to mem_cs_n [2] +#set_location_assignment PIN_AP8 -to mem_odt [2] +#set_location_assignment PIN_AP9 -to mem_reset_n [2] +#set_location_assignment PIN_AP5 -to mem_par [2] +#set_location_assignment PIN_AP6 -to mem_alert_n [2] +#set_location_assignment PIN_AN3 -to mem_oct_rzqin[2] +#set_location_assignment PIN_AL5 -to mem_ref_clk [2] +#set_location_assignment PIN_AT4 -to mem_a [2][0] +#set_location_assignment PIN_AT5 -to mem_a [2][1] +#set_location_assignment PIN_AR2 -to mem_a [2][2] +#set_location_assignment PIN_AR1 -to mem_a [2][3] +#set_location_assignment PIN_AR3 -to mem_a [2][4] +#set_location_assignment PIN_AR4 -to mem_a [2][5] +#set_location_assignment PIN_AP1 -to mem_a [2][6] +#set_location_assignment PIN_AN1 -to mem_a [2][7] +#set_location_assignment PIN_AP4 -to mem_a [2][8] +#set_location_assignment PIN_AP3 -to mem_a [2][9] +#set_location_assignment PIN_AT2 -to mem_a [2][10] +#set_location_assignment PIN_AT1 -to mem_a [2][11] +#set_location_assignment PIN_AN2 -to mem_a [2][12] +#set_location_assignment PIN_AN5 -to mem_a [2][13] +#set_location_assignment PIN_AM5 -to mem_a [2][14] +#set_location_assignment PIN_AM2 -to mem_a [2][15] +#set_location_assignment PIN_AM3 -to mem_a [2][16] +#set_location_assignment PIN_AM4 -to mem_a [2][17] +#set_location_assignment PIN_AL1 -to mem_ba [2][1] +#set_location_assignment PIN_AL4 -to mem_ba [2][0] +#set_location_assignment PIN_AR9 -to mem_bg [2][1] +#set_location_assignment PIN_AL2 -to mem_bg [2][0] +#set_location_assignment PIN_AH5 -to mem_dqs [2][0] +#set_location_assignment PIN_AG5 -to mem_dqs_n [2][0] +#set_location_assignment PIN_AG4 -to mem_dbi_n [2][0] +#set_location_assignment PIN_AK6 -to mem_dqs [2][1] +#set_location_assignment PIN_AK7 -to mem_dqs_n [2][1] +#set_location_assignment PIN_AJ6 -to mem_dbi_n [2][1] +#set_location_assignment PIN_AL11 -to mem_dqs [2][2] +#set_location_assignment PIN_AL10 -to mem_dqs_n [2][2] +#set_location_assignment PIN_AK12 -to mem_dbi_n [2][2] +#set_location_assignment PIN_AH10 -to mem_dqs [2][3] +#set_location_assignment PIN_AJ11 -to mem_dqs_n [2][3] +#set_location_assignment PIN_AH11 -to mem_dbi_n [2][3] +#set_location_assignment PIN_AV6 -to mem_dqs [2][4] +#set_location_assignment PIN_AV5 -to mem_dqs_n [2][4] +#set_location_assignment PIN_AW1 -to mem_dbi_n [2][4] +#set_location_assignment PIN_AV10 -to mem_dqs [2][5] +#set_location_assignment PIN_AU10 -to mem_dqs_n [2][5] +#set_location_assignment PIN_AU13 -to mem_dbi_n [2][5] +#set_location_assignment PIN_AT11 -to mem_dqs [2][6] +#set_location_assignment PIN_AR11 -to mem_dqs_n [2][6] +#set_location_assignment PIN_AR13 -to mem_dbi_n [2][6] +#set_location_assignment PIN_BA4 -to mem_dqs [2][7] +#set_location_assignment PIN_BB4 -to mem_dqs_n [2][7] +#set_location_assignment PIN_AW5 -to mem_dbi_n [2][7] +#set_location_assignment PIN_AN10 -to mem_dqs [2][8] +#set_location_assignment PIN_AN11 -to mem_dqs_n [2][8] +#set_location_assignment PIN_AM12 -to mem_dbi_n [2][8] +#set_location_assignment PIN_AF1 -to mem_dq [2][0] +#set_location_assignment PIN_AH6 -to mem_dq [2][1] +#set_location_assignment PIN_AH3 -to mem_dq [2][2] +#set_location_assignment PIN_AG2 -to mem_dq [2][3] +#set_location_assignment PIN_AF2 -to mem_dq [2][4] +#set_location_assignment PIN_AH7 -to mem_dq [2][5] +#set_location_assignment PIN_AH2 -to mem_dq [2][6] +#set_location_assignment PIN_AG3 -to mem_dq [2][7] +#set_location_assignment PIN_AK2 -to mem_dq [2][8] +#set_location_assignment PIN_AJ3 -to mem_dq [2][9] +#set_location_assignment PIN_AK4 -to mem_dq [2][10] +#set_location_assignment PIN_AJ4 -to mem_dq [2][11] +#set_location_assignment PIN_AK1 -to mem_dq [2][12] +#set_location_assignment PIN_AH1 -to mem_dq [2][13] +#set_location_assignment PIN_AK3 -to mem_dq [2][14] +#set_location_assignment PIN_AJ1 -to mem_dq [2][15] +#set_location_assignment PIN_AL12 -to mem_dq [2][16] +#set_location_assignment PIN_AK11 -to mem_dq [2][17] +#set_location_assignment PIN_AL9 -to mem_dq [2][18] +#set_location_assignment PIN_AK8 -to mem_dq [2][19] +#set_location_assignment PIN_AL14 -to mem_dq [2][20] +#set_location_assignment PIN_AK14 -to mem_dq [2][21] +#set_location_assignment PIN_AL7 -to mem_dq [2][22] +#set_location_assignment PIN_AK9 -to mem_dq [2][23] +#set_location_assignment PIN_AH13 -to mem_dq [2][24] +#set_location_assignment PIN_AG7 -to mem_dq [2][25] +#set_location_assignment PIN_AJ10 -to mem_dq [2][26] +#set_location_assignment PIN_AJ8 -to mem_dq [2][27] +#set_location_assignment PIN_AJ13 -to mem_dq [2][28] +#set_location_assignment PIN_AG8 -to mem_dq [2][29] +#set_location_assignment PIN_AJ9 -to mem_dq [2][30] +#set_location_assignment PIN_AH8 -to mem_dq [2][31] +#set_location_assignment PIN_AU4 -to mem_dq [2][32] +#set_location_assignment PIN_AU5 -to mem_dq [2][33] +#set_location_assignment PIN_AU3 -to mem_dq [2][34] +#set_location_assignment PIN_AV2 -to mem_dq [2][35] +#set_location_assignment PIN_AV7 -to mem_dq [2][36] +#set_location_assignment PIN_AV8 -to mem_dq [2][37] +#set_location_assignment PIN_AU2 -to mem_dq [2][38] +#set_location_assignment PIN_AV3 -to mem_dq [2][39] +#set_location_assignment PIN_AY7 -to mem_dq [2][40] +#set_location_assignment PIN_AW10 -to mem_dq [2][41] +#set_location_assignment PIN_AV11 -to mem_dq [2][42] +#set_location_assignment PIN_AW8 -to mem_dq [2][43] +#set_location_assignment PIN_AY6 -to mem_dq [2][44] +#set_location_assignment PIN_AW11 -to mem_dq [2][45] +#set_location_assignment PIN_AV12 -to mem_dq [2][46] +#set_location_assignment PIN_AW9 -to mem_dq [2][47] +#set_location_assignment PIN_AU8 -to mem_dq [2][48] +#set_location_assignment PIN_AT12 -to mem_dq [2][49] +#set_location_assignment PIN_AT9 -to mem_dq [2][50] +#set_location_assignment PIN_AT7 -to mem_dq [2][51] +#set_location_assignment PIN_AU7 -to mem_dq [2][52] +#set_location_assignment PIN_AT10 -to mem_dq [2][53] +#set_location_assignment PIN_AU9 -to mem_dq [2][54] +#set_location_assignment PIN_AR12 -to mem_dq [2][55] +#set_location_assignment PIN_BA2 -to mem_dq [2][56] +#set_location_assignment PIN_AY4 -to mem_dq [2][57] +#set_location_assignment PIN_AW3 -to mem_dq [2][58] +#set_location_assignment PIN_BA5 -to mem_dq [2][59] +#set_location_assignment PIN_AY2 -to mem_dq [2][60] +#set_location_assignment PIN_AW4 -to mem_dq [2][61] +#set_location_assignment PIN_AY3 -to mem_dq [2][62] +#set_location_assignment PIN_BB5 -to mem_dq [2][63] +#set_location_assignment PIN_AM7 -to mem_dq [2][64] +#set_location_assignment PIN_AM8 -to mem_dq [2][65] +#set_location_assignment PIN_AN13 -to mem_dq [2][66] +#set_location_assignment PIN_AN12 -to mem_dq [2][67] +#set_location_assignment PIN_AN6 -to mem_dq [2][68] +#set_location_assignment PIN_AN7 -to mem_dq [2][69] +#set_location_assignment PIN_AM9 -to mem_dq [2][70] +#set_location_assignment PIN_AM10 -to mem_dq [2][71] +#========================================================= +# DDR4 CH3 (Upper 3) - A/C +#========================================================= +#set_location_assignment PIN_L6 -to mem_ck [3] +#set_location_assignment PIN_L7 -to mem_ck_n [3] +#set_location_assignment PIN_L5 -to mem_act_n [3] +#set_location_assignment PIN_M4 -to mem_cke [3] +#set_location_assignment PIN_M5 -to mem_cs_n [3] +#set_location_assignment PIN_M8 -to mem_odt [3] +#set_location_assignment PIN_M9 -to mem_reset_n [3] +#set_location_assignment PIN_K4 -to mem_par [3] +#set_location_assignment PIN_L4 -to mem_alert_n [3] +#set_location_assignment PIN_J5 -to mem_oct_rzqin[3] +#set_location_assignment PIN_K8 -to mem_ref_clk [3] +#set_location_assignment PIN_H1 -to mem_a [3][0] +#set_location_assignment PIN_J1 -to mem_a [3][1] +#set_location_assignment PIN_L2 -to mem_a [3][2] +#set_location_assignment PIN_K2 -to mem_a [3][3] +#set_location_assignment PIN_F2 -to mem_a [3][4] +#set_location_assignment PIN_F1 -to mem_a [3][5] +#set_location_assignment PIN_L1 -to mem_a [3][6] +#set_location_assignment PIN_K1 -to mem_a [3][7] +#set_location_assignment PIN_G2 -to mem_a [3][8] +#set_location_assignment PIN_H2 -to mem_a [3][9] +#set_location_assignment PIN_K3 -to mem_a [3][10] +#set_location_assignment PIN_J3 -to mem_a [3][11] +#set_location_assignment PIN_J4 -to mem_a [3][12] +#set_location_assignment PIN_K6 -to mem_a [3][13] +#set_location_assignment PIN_J6 -to mem_a [3][14] +#set_location_assignment PIN_H3 -to mem_a [3][15] +#set_location_assignment PIN_G3 -to mem_a [3][16] +#set_location_assignment PIN_H5 -to mem_a [3][17] +#set_location_assignment PIN_G4 -to mem_ba [3][1] +#set_location_assignment PIN_H6 -to mem_ba [3][0] +#set_location_assignment PIN_M10 -to mem_bg [3][1] +#set_location_assignment PIN_G5 -to mem_bg [3][0] +#set_location_assignment PIN_G8 -to mem_dqs [3][0] +#set_location_assignment PIN_G9 -to mem_dqs_n [3][0] +#set_location_assignment PIN_J13 -to mem_dbi_n [3][0] +#set_location_assignment PIN_C7 -to mem_dqs [3][1] +#set_location_assignment PIN_B7 -to mem_dqs_n [3][1] +#set_location_assignment PIN_E9 -to mem_dbi_n [3][1] +#set_location_assignment PIN_F4 -to mem_dqs [3][2] +#set_location_assignment PIN_E4 -to mem_dqs_n [3][2] +#set_location_assignment PIN_E3 -to mem_dbi_n [3][2] +#set_location_assignment PIN_C5 -to mem_dqs [3][3] +#set_location_assignment PIN_D5 -to mem_dqs_n [3][3] +#set_location_assignment PIN_A4 -to mem_dbi_n [3][3] +#set_location_assignment PIN_P1 -to mem_dqs [3][4] +#set_location_assignment PIN_N1 -to mem_dqs_n [3][4] +#set_location_assignment PIN_N2 -to mem_dbi_n [3][4] +#set_location_assignment PIN_P9 -to mem_dqs [3][5] +#set_location_assignment PIN_P8 -to mem_dqs_n [3][5] +#set_location_assignment PIN_R6 -to mem_dbi_n [3][5] +#set_location_assignment PIN_T6 -to mem_dqs [3][6] +#set_location_assignment PIN_T7 -to mem_dqs_n [3][6] +#set_location_assignment PIN_R7 -to mem_dbi_n [3][6] +#set_location_assignment PIN_P13 -to mem_dqs [3][7] +#set_location_assignment PIN_N13 -to mem_dqs_n [3][7] +#set_location_assignment PIN_R11 -to mem_dbi_n [3][7] +#set_location_assignment PIN_M12 -to mem_dqs [3][8] +#set_location_assignment PIN_L12 -to mem_dqs_n [3][8] +#set_location_assignment PIN_K11 -to mem_dbi_n [3][8] +#set_location_assignment PIN_H10 -to mem_dq [3][0] +#set_location_assignment PIN_H11 -to mem_dq [3][1] +#set_location_assignment PIN_G10 -to mem_dq [3][2] +#set_location_assignment PIN_F9 -to mem_dq [3][3] +#set_location_assignment PIN_J10 -to mem_dq [3][4] +#set_location_assignment PIN_J11 -to mem_dq [3][5] +#set_location_assignment PIN_H12 -to mem_dq [3][6] +#set_location_assignment PIN_F10 -to mem_dq [3][7] +#set_location_assignment PIN_B5 -to mem_dq [3][8] +#set_location_assignment PIN_A5 -to mem_dq [3][9] +#set_location_assignment PIN_A6 -to mem_dq [3][10] +#set_location_assignment PIN_E7 -to mem_dq [3][11] +#set_location_assignment PIN_E6 -to mem_dq [3][12] +#set_location_assignment PIN_D6 -to mem_dq [3][13] +#set_location_assignment PIN_C6 -to mem_dq [3][14] +#set_location_assignment PIN_A7 -to mem_dq [3][15] +#set_location_assignment PIN_J8 -to mem_dq [3][16] +#set_location_assignment PIN_G7 -to mem_dq [3][17] +#set_location_assignment PIN_J9 -to mem_dq [3][18] +#set_location_assignment PIN_F6 -to mem_dq [3][19] +#set_location_assignment PIN_F5 -to mem_dq [3][20] +#set_location_assignment PIN_H7 -to mem_dq [3][21] +#set_location_assignment PIN_H8 -to mem_dq [3][22] +#set_location_assignment PIN_F7 -to mem_dq [3][23] +#set_location_assignment PIN_C2 -to mem_dq [3][24] +#set_location_assignment PIN_D3 -to mem_dq [3][25] +#set_location_assignment PIN_B2 -to mem_dq [3][26] +#set_location_assignment PIN_B3 -to mem_dq [3][27] +#set_location_assignment PIN_E1 -to mem_dq [3][28] +#set_location_assignment PIN_D1 -to mem_dq [3][29] +#set_location_assignment PIN_C3 -to mem_dq [3][30] +#set_location_assignment PIN_D4 -to mem_dq [3][31] +#set_location_assignment PIN_R4 -to mem_dq [3][32] +#set_location_assignment PIN_R1 -to mem_dq [3][33] +#set_location_assignment PIN_T2 -to mem_dq [3][34] +#set_location_assignment PIN_R3 -to mem_dq [3][35] +#set_location_assignment PIN_N3 -to mem_dq [3][36] +#set_location_assignment PIN_P3 -to mem_dq [3][37] +#set_location_assignment PIN_T1 -to mem_dq [3][38] +#set_location_assignment PIN_R2 -to mem_dq [3][39] +#set_location_assignment PIN_N5 -to mem_dq [3][40] +#set_location_assignment PIN_P4 -to mem_dq [3][41] +#set_location_assignment PIN_N8 -to mem_dq [3][42] +#set_location_assignment PIN_P10 -to mem_dq [3][43] +#set_location_assignment PIN_N6 -to mem_dq [3][44] +#set_location_assignment PIN_P5 -to mem_dq [3][45] +#set_location_assignment PIN_N7 -to mem_dq [3][46] +#set_location_assignment PIN_N10 -to mem_dq [3][47] +#set_location_assignment PIN_U4 -to mem_dq [3][48] +#set_location_assignment PIN_T4 -to mem_dq [3][49] +#set_location_assignment PIN_U5 -to mem_dq [3][50] +#set_location_assignment PIN_T9 -to mem_dq [3][51] +#set_location_assignment PIN_U2 -to mem_dq [3][52] +#set_location_assignment PIN_R9 -to mem_dq [3][53] +#set_location_assignment PIN_T5 -to mem_dq [3][54] +#set_location_assignment PIN_U3 -to mem_dq [3][55] +#set_location_assignment PIN_R13 -to mem_dq [3][56] +#set_location_assignment PIN_N11 -to mem_dq [3][57] +#set_location_assignment PIN_R14 -to mem_dq [3][58] +#set_location_assignment PIN_T11 -to mem_dq [3][59] +#set_location_assignment PIN_T12 -to mem_dq [3][60] +#set_location_assignment PIN_N12 -to mem_dq [3][61] +#set_location_assignment PIN_T10 -to mem_dq [3][62] +#set_location_assignment PIN_R12 -to mem_dq [3][63] +#set_location_assignment PIN_K14 -to mem_dq [3][64] +#set_location_assignment PIN_K13 -to mem_dq [3][65] +#set_location_assignment PIN_L9 -to mem_dq [3][66] +#set_location_assignment PIN_L11 -to mem_dq [3][67] +#set_location_assignment PIN_M13 -to mem_dq [3][68] +#set_location_assignment PIN_M14 -to mem_dq [3][69] +#set_location_assignment PIN_L10 -to mem_dq [3][70] +#set_location_assignment PIN_K9 -to mem_dq [3][71] + diff --git a/syn/setup/pcie_afu_if_design_files.tcl b/syn/setup/pcie_afu_if_design_files.tcl new file mode 100644 index 0000000..3dcb662 --- /dev/null +++ b/syn/setup/pcie_afu_if_design_files.tcl @@ -0,0 +1,17 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# +# PCIe interfaces passed to AFUs. These files are used by both FIM and PR builds. +# + +#-------------------- +# Packages +#-------------------- +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/ofs_fim_pcie_hdr_def.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/ofs_fim_pcie_pkg.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/ofs_fim_axis_if.sv + +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/src/includes/ofs_pcie_ss_plat_cfg_pkg.sv + +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/ofs-common/src/common/includes/pcie_afu_if_design_files.tcl diff --git a/syn/setup/pcie_design_files.tcl b/syn/setup/pcie_design_files.tcl new file mode 100644 index 0000000..e7510a2 --- /dev/null +++ b/syn/setup/pcie_design_files.tcl @@ -0,0 +1,57 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +set_global_assignment -name SEARCH_PATH $::env(BUILD_ROOT_REL)/ + +#-------------------- +# PCIE IP +#-------------------- +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/qip/pcie_ep_g3x16.ip + +#-------------------- +# PCIE bridge +#-------------------- +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/pcie_bridge.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/pcie_bridge_cdc.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/pcie_rx_bridge_cdc.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/pcie_tx_bridge_cdc.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/pcie_checker.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/pipeline/axis_reg_pcie_txs.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/pcie_rx_bridge_htile.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/pcie_rx_bridge.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/pcie_tx_bridge.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/pcie_tx_bridge_htile.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/pcie_rx_bridge_ptile.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/pcie_tx_bridge_ptile.sv + +#---------- +# PCIE CSR +#---------- +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/pcie_csr.sv + +#---------- +# PCIE top +#---------- +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/pcie_flr_resync.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/pcie_msix_resync.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/pcie_top.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/pcie_wrapper.sv + +#---------- +# PCIE Adapter +#---------- +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/axi_s_adapter.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/pcie_ch0_align_tx.sv + +#---------- +# PCIE Tx Arbiter +#---------- +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pcie/rtl/pcie_tx_arbiter.sv + + +#---------- +# SDC +#---------- +set_global_assignment -name SDC_FILE $::env(BUILD_ROOT_REL)/syn/setup/pcie_top.sdc +set_global_assignment -name SDC_FILE $::env(BUILD_ROOT_REL)/syn/setup/dcfifo.sdc + diff --git a/syn/setup/pcie_location.tcl b/syn/setup/pcie_location.tcl new file mode 100644 index 0000000..4480cd6 --- /dev/null +++ b/syn/setup/pcie_location.tcl @@ -0,0 +1,53 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# Description +#----------------------------------------------------------------------------- +# +# PCIe pin and location assignments +# +#----------------------------------------------------------------------------- + +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PCIE_Rst_n +set_location_assignment PIN_AC26 -to PCIE_Rst_n + +set_instance_assignment -name IO_STANDARD HCSL -to PCIE_RefClk +set_location_assignment PIN_AM34 -to PCIE_RefClk +set_location_assignment PIN_AM33 -to "PCIE_RefClk(n)" + +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to PCIE_Tx[*] +set_location_assignment PIN_BB34 -to PCIE_Tx[0] +set_location_assignment PIN_BA36 -to PCIE_Tx[1] +set_location_assignment PIN_BB38 -to PCIE_Tx[2] +set_location_assignment PIN_AY38 -to PCIE_Tx[3] +set_location_assignment PIN_BA40 -to PCIE_Tx[4] +set_location_assignment PIN_AV38 -to PCIE_Tx[5] +set_location_assignment PIN_AW40 -to PCIE_Tx[6] +set_location_assignment PIN_AV42 -to PCIE_Tx[7] +set_location_assignment PIN_AU40 -to PCIE_Tx[8] +set_location_assignment PIN_AT42 -to PCIE_Tx[9] +set_location_assignment PIN_AR40 -to PCIE_Tx[10] +set_location_assignment PIN_AP42 -to PCIE_Tx[11] +set_location_assignment PIN_AN40 -to PCIE_Tx[12] +set_location_assignment PIN_AM42 -to PCIE_Tx[13] +set_location_assignment PIN_AL40 -to PCIE_Tx[14] +set_location_assignment PIN_AK42 -to PCIE_Tx[15] + +set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to PCIE_Rx[*] +set_location_assignment PIN_AV30 -to PCIE_Rx[0] +set_location_assignment PIN_AY30 -to PCIE_Rx[1] +set_location_assignment PIN_BB30 -to PCIE_Rx[2] +set_location_assignment PIN_AW32 -to PCIE_Rx[3] +set_location_assignment PIN_BA32 -to PCIE_Rx[4] +set_location_assignment PIN_AY34 -to PCIE_Rx[5] +set_location_assignment PIN_AU36 -to PCIE_Rx[6] +set_location_assignment PIN_AW36 -to PCIE_Rx[7] +set_location_assignment PIN_AR36 -to PCIE_Rx[8] +set_location_assignment PIN_AN36 -to PCIE_Rx[9] +set_location_assignment PIN_AT38 -to PCIE_Rx[10] +set_location_assignment PIN_AP38 -to PCIE_Rx[11] +set_location_assignment PIN_AL36 -to PCIE_Rx[12] +set_location_assignment PIN_AM38 -to PCIE_Rx[13] +set_location_assignment PIN_AK38 -to PCIE_Rx[14] +set_location_assignment PIN_AJ36 -to PCIE_Rx[15] + diff --git a/syn/setup/pcie_top.sdc b/syn/setup/pcie_top.sdc new file mode 100755 index 0000000..0e79d96 --- /dev/null +++ b/syn/setup/pcie_top.sdc @@ -0,0 +1,18 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# Description +#----------------------------------------------------------------------------- +# +# Platform top level SDC +# +#----------------------------------------------------------------------------- + +#************************************************************** +# IP/Quartus Workaround +#************************************************************** +# Disable min_pulse_width check for known failure in PCIe Gen3x16 IP (case:590754) +#disable_min_pulse_width [get_clocks {pcie_wrapper|pcie_top|dut|dut|altera_pcie_s10_hip_ast_pipen1b_inst|altera_pcie_s10_hip_ast_pllnphy_inst|g_phy_g3x16.phy_g3x16|phy_g3x16|tx_pcs_x2_clk|ch0}] +disable_min_pulse_width [get_clocks {pcie_wrapper|pcie_top|dut|pcie_s10_hip_ast_0|altera_pcie_s10_hip_ast_pipen1b_inst|altera_pcie_s10_hip_ast_pllnphy_inst|g_phy_g3x16.phy_g3x16|phy_g3x16|tx_pcs_x2_clk|ch0}] + + diff --git a/syn/setup/pmci_design_files.tcl b/syn/setup/pmci_design_files.tcl new file mode 100644 index 0000000..61b7a04 --- /dev/null +++ b/syn/setup/pmci_design_files.tcl @@ -0,0 +1,5 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +##top +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/pmci/pmci_top.sv diff --git a/syn/setup/setup_user_clock_for_pr.sdc b/syn/setup/setup_user_clock_for_pr.sdc new file mode 100644 index 0000000..453f0ba --- /dev/null +++ b/syn/setup/setup_user_clock_for_pr.sdc @@ -0,0 +1,42 @@ +# Copyright (C) 2023 Intel Corporation +# SPDX-License-Identifier: MIT + +## +## Define user clock information as a side effect of timing analysis. This +## may be used later, especially in PR builds, to constrain the user clock +## to an AFU-specific frequency. +## + +# Only create the script once... +if {[file exists "ofs_partial_reconfig/user_clock_defs.tcl"] == 0} { + # A common script for walking the clocks and finding the user clock + source $::env(BUILD_ROOT_REL)/ofs-common/scripts/common/syn/import_user_clk_sdc.tcl + + # + # Platform/architecture specific configuration: + # - The pattern to search for user clock + # - The maximum frequency + # - Tcl file to generate that will configured user clock constraints + # + setup_user_clk_sdc "*user_clk_iopll|iopll_0_outclk*" 600 ofs_partial_reconfig/user_clock_defs.tcl +} + +# Load the clock constraint functions, generated by the previous command +source ofs_partial_reconfig/user_clock_defs.tcl + +# Constrain the user clock to the maximum legal frequency during the FIM build. +# Nothing is actually attached to it, but we add the constraint so the clock +# tree reaching the AFU will meeting aggressive timing. +# +# The absurdly large frequencies here will be reduced to platform-specific +# maximum values by constrain_user_clks. +# +# Do not apply the constraint during the STA phase of the FIM build. Instead, +# leave the user clock constrained at its native frequency. This is the frequency +# at which it will be initialized when the FIM is loaded. +if { ![string equal "quartus_sta" $::TimeQuestInfo(nameofexecutable)] } { + if { ![info exists ::userClocks::no_added_constraints] } { + post_message "Applying high frequency constraint to FIM user clock during $::TimeQuestInfo(nameofexecutable)." + constrain_user_clks {5000 5000} + } +} diff --git a/syn/setup/spi_design_files.tcl b/syn/setup/spi_design_files.tcl new file mode 100644 index 0000000..6a8f59e --- /dev/null +++ b/syn/setup/spi_design_files.tcl @@ -0,0 +1,23 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# SPI +#-------------------- +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/spi/spi_bridge_top.sv +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/ipss/spi/spi_bridge_csr.sv + +#-------------------- +# SPI IP +#-------------------- +set_global_assignment -name QSYS_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/spi_bridge/spi_bridge.qsys + +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/spi_bridge/ip/spi_bridge/spi_bridge_reset_in.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/spi_bridge/ip/spi_bridge/spi_bridge_spi_0.ip +set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/src/pd_qsys/spi_bridge/ip/spi_bridge/spi_bridge_clock_in.ip + +#-------------------- +# SDC +#-------------------- + +set_global_assignment -name SDC_FILE $::env(BUILD_ROOT_REL)/syn/setup/spi_top.sdc + diff --git a/syn/setup/spi_location.tcl b/syn/setup/spi_location.tcl new file mode 100644 index 0000000..8b76477 --- /dev/null +++ b/syn/setup/spi_location.tcl @@ -0,0 +1,17 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# Description +#----------------------------------------------------------------------------- +# +# SPI Bridge pin and location assignments +# +#----------------------------------------------------------------------------- +set_location_assignment PIN_Y11 -to SPI_sclk +set_location_assignment PIN_W11 -to SPI_cs_l +set_location_assignment PIN_AA12 -to SPI_mosi +set_location_assignment PIN_AA11 -to SPI_miso +set_instance_assignment -name IO_STANDARD "1.8 V" -to SPI_sclk +set_instance_assignment -name IO_STANDARD "1.8 V" -to SPI_cs_l +set_instance_assignment -name IO_STANDARD "1.8 V" -to SPI_mosi +set_instance_assignment -name IO_STANDARD "1.8 V" -to SPI_miso diff --git a/syn/setup/spi_top.sdc b/syn/setup/spi_top.sdc new file mode 100644 index 0000000..d4426b7 --- /dev/null +++ b/syn/setup/spi_top.sdc @@ -0,0 +1,40 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# no special sdc constraints needed. +# FUTURE_IMPROVEMENT markdte (there are warnings in the auto-generated constraints (ip)) + +# Create generated clock at sclk port derived from SCLK_reg pin + +create_generated_clock \ + -source [get_pins {pmci_top|spi_bridge_top|spi_bridge|spi_0|spi_0|SCLK_reg|clk}] \ + -divide_by 10 -multiply_by 1 -duty_cycle 50 -phase 0 -offset 0 \ + -name spi_sclk_internal [get_pins {pmci_top|spi_bridge_top|spi_bridge|spi_0|spi_0|SCLK_reg|q}] + +create_generated_clock \ + -source [get_pins {pmci_top|spi_bridge_top|spi_bridge|spi_0|spi_0|SCLK_reg|q}] \ + -name spi_sclk [get_ports {SPI_sclk}] + +# setup multicycle constraints + +set_multicycle_path 5 -setup -start -from sys_pll|iopll_0_clk1x -to spi_sclk +set_multicycle_path 5 -setup -end -from spi_sclk -to sys_pll|iopll_0_clk1x + +set_multicycle_path 9 -hold -start -from sys_pll|iopll_0_clk1x -to spi_sclk +set_multicycle_path 9 -hold -end -from spi_sclk -to sys_pll|iopll_0_clk1x + +set_output_delay -clock spi_sclk -clock_fall -min 0 [get_ports {SPI_mosi}] +set_output_delay -clock spi_sclk -clock_fall -max 7 [get_ports {SPI_mosi}] + +set_output_delay -clock spi_sclk -clock_fall -min 0 [get_ports {SPI_mosi}] +set_output_delay -clock spi_sclk -clock_fall -max 15 [get_ports {SPI_mosi}] + +set_input_delay -clock spi_sclk -min 0 [get_ports {SPI_miso}] +set_input_delay -clock spi_sclk -max 15 [get_ports {SPI_miso}] + +# False path for chip select.IP chip select is active at least 1 full clock cycle before clock is active. +set_false_path -to [get_ports {SPI_cs_l}] + +# False path CDC +set_false_path -from [get_clocks {spi_sclk}] -to [get_clocks {sys_pll|iopll_0_clk_125M}] +set_false_path -from [get_clocks {sys_pll|iopll_0_clk_125M}] -to [get_clocks {spi_sclk}] diff --git a/syn/setup/sr_logic_lock_region.tcl b/syn/setup/sr_logic_lock_region.tcl new file mode 100644 index 0000000..a184de1 --- /dev/null +++ b/syn/setup/sr_logic_lock_region.tcl @@ -0,0 +1,14 @@ +# Copyright (C) 2022 Intel Corporation +# SPDX-License-Identifier: MIT + +############################################################################################ +# PARTIAL RECONFIGURATION # +############################################################################################ + +set_global_assignment -name REVISION_TYPE PR_BASE +set_instance_assignment -name PARTITION persona1 -to afu_top|port_gasket|pr_slot|afu_main -entity iofs_top +set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON -to afu_top|port_gasket|pr_slot|afu_main -entity iofs_top +set_instance_assignment -name PLACE_REGION "X240 Y0 X280 Y430;X75 Y40 X76 Y109;X77 Y40 X204 Y320;X67 Y110 X76 Y320;X205 Y110 X239 Y320;X75 Y321 X203 Y393" -to afu_top|port_gasket|pr_slot|afu_main +set_instance_assignment -name ROUTE_REGION "0 0 282 432" -to afu_top|port_gasket|pr_slot|afu_main +set_instance_assignment -name RESERVE_PLACE_REGION ON -to afu_top|port_gasket|pr_slot|afu_main +set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to afu_top|port_gasket|pr_slot|afu_main diff --git a/syn/setup/top.sdc b/syn/setup/top.sdc new file mode 100755 index 0000000..e7f0024 --- /dev/null +++ b/syn/setup/top.sdc @@ -0,0 +1,107 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# Description +#----------------------------------------------------------------------------- +# +# Platform top level SDC +# +#----------------------------------------------------------------------------- +proc add_reset_sync_sdc { pin_name } { + set_max_delay -to [get_pins $pin_name] 100.000 + set_min_delay -to [get_pins $pin_name] -100.000 + #set_max_skew -to [get_pins $pin_name] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 +} + +proc add_sync_sdc { name } { + set_max_delay -to [get_keepers $name] 100.000 + set_min_delay -to [get_keepers $name] -100.000 +} + +#************************************************************** +# Create Clock +#************************************************************** +derive_clock_uncertainty + +create_clock -name qsfp1_644_53125_clk -period 1.552 -waveform {0.000 0.776} [get_ports {qsfp1_644_53125_clk}] +create_clock -name qsfp0_644_53125_clk -period 1.552 -waveform {0.000 0.776} [get_ports {qsfp0_644_53125_clk}] +create_clock -name {altera_reserved_tck} -period 100.000 -waveform {0.000 50.000} [get_ports {altera_reserved_tck}] + +#************************************************************** +# Set Clock Groups +#************************************************************** +set_clock_groups -asynchronous -group {altera_reserved_tck} + +#--------------------------------------------- +# CDC constraints for reset synchronizers +#--------------------------------------------- +add_reset_sync_sdc {*|rst_clk100_resync|resync_chains[0].synchronizer_nocut|*|clrn} +add_reset_sync_sdc {*|rst_clk1x_resync|resync_chains[0].synchronizer_nocut|*|clrn} +add_reset_sync_sdc {*|rst_clk2x_resync|resync_chains[0].synchronizer_nocut|*|clrn} +add_reset_sync_sdc {*|pwr_good_n_resync|resync_chains[0].synchronizer_nocut|*|clrn} +add_reset_sync_sdc {pcie_wrapper|pcie_top|pcie_bridge|pcie_bridge_cdc|rx_cdc|rx_avst_dcfifo|rst_rclk_resync|resync_chains[0].synchronizer_nocut|*|clrn} +add_reset_sync_sdc {pcie_wrapper|pcie_top|pcie_bridge|pcie_bridge_cdc|rx_cdc|rx_avst_dcfifo|dcfifo|dcfifo_component|auto_generated|wraclr|*|clrn} +add_reset_sync_sdc {pcie_wrapper|pcie_top|pcie_bridge|pcie_bridge_cdc|tx_cdc|tx_axis_dcfifo|rst_rclk_resync|resync_chains[0].synchronizer_nocut|*|clrn} +add_reset_sync_sdc {pcie_wrapper|pcie_top|pcie_bridge|pcie_bridge_cdc|tx_cdc|tx_axis_dcfifo|dcfifo|dcfifo_component|auto_generated|rdaclr|*|clrn} +add_sync_sdc {afu_top|port_gasket|remote_stp_top_inst|remote_debug_jtag_only|*|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]} +#----------------------------------------------------------------------------------------------------------------------------------------------- +# CDCs... +#----------------------------------------------------------------------------------------------------------------------------------------------- + +if {$::quartus(nameofexecutable) != "quartus_sta"} { # constraints for synthesis + set_max_delay -to *_cal_*_sync_* 10ns + set_max_delay -to *resync_chains*synchronizer*|din* 10ns + set_max_delay -to *dcfifo_*dffpipe_*aclr|dffe*a[*] 10ns + set_max_delay -from *softreset* -to *pr_slot|rst_p0_tx_sync|d* 10ns + set_max_delay -from rst_n_e_1x -to *pr_slot|rst_p0_tx_sync|d* 10ns + set_max_delay -from rst_n_b_1x -to *pcie_bridge_cdc*dcfifo*|*aclr|dff* 10ns + set_max_delay -from *qph_user_clk_freq|prescaler[*] -to *qph_user_clk_freq|smpclk_meta 10ns + set_max_delay -from *pr_freeze[*] -to *pr_freeze_sync|* 10ns + set_max_delay -from *pcie_flr*launch[*] -to *pcie_flr*capture[*] 10ns + set_max_delay -from *pcie_top*dcfifo*|*delayed_wrptr_g* -to *pcie_top*dcfifo*|*rs_dgwp* 10ns + set_max_delay -from *pcie_top*dcfifo*|*rdptr_g* -to *pcie_top*dcfifo*|*ws_dgrp* 10ns + set_max_delay -from *altera_iopll_i*pll~pll_e_reg__nff -to *rst_ctrl|* 10ns + set_max_delay -from *pcie_top*pcie_s10_hip*reset_*_reg* -to *rst_ctrl|* 10ns + + set_min_delay -to *_cal_*_sync_* -100ns + set_min_delay -to *resync_chains*synchronizer*|din* -100ns + set_min_delay -to *dcfifo_*dffpipe_*aclr|dffe*a[*] -100ns + set_min_delay -from *softreset* -to *pr_slot|rst_p0_tx_sync|d* -100ns + set_min_delay -from rst_n_e_1x -to *pr_slot|rst_p0_tx_sync|d* -100ns + set_min_delay -from rst_n_b_1x -to *pcie_bridge_cdc*dcfifo*|*aclr|dff* -100ns + set_min_delay -from *qph_user_clk_freq|prescaler[*] -to *qph_user_clk_freq|smpclk_meta -100ns + set_min_delay -from *pr_freeze[*] -to *pr_freeze_sync|* -100ns + set_min_delay -from *pcie_flr*launch[*] -to *pcie_flr*capture[*] -100ns + set_min_delay -from *pcie_top*dcfifo*|*delayed_wrptr_g* -to *pcie_top*dcfifo*|*rs_dgwp* -100ns + set_min_delay -from *pcie_top*dcfifo*|*rdptr_g* -to *pcie_top*dcfifo*|*ws_dgrp* -100ns + set_min_delay -from *altera_iopll_i*pll~pll_e_reg__nff -to *rst_ctrl|* -100ns + set_min_delay -from *pcie_top*pcie_s10_hip*reset_*_reg* -to *rst_ctrl|* -100ns +} else { # contraints for timing report + set_max_delay -to *_cal_*_sync_* 100ns + set_max_delay -to *resync_chains*synchronizer*|din* 100ns + set_max_delay -to *dcfifo_*dffpipe_*aclr|dffe*a[*] 100ns + set_max_delay -from *softreset* -to *pr_slot|rst_p0_tx_sync|d* 100ns + set_max_delay -from rst_n_e_1x -to *pr_slot|rst_p0_tx_sync|d* 100ns + set_max_delay -from rst_n_b_1x -to *pcie_bridge_cdc*dcfifo*|*aclr|dff* 100ns + set_max_delay -from *qph_user_clk_freq|prescaler[*] -to *qph_user_clk_freq|smpclk_meta 100ns + set_max_delay -from *pr_freeze[*] -to *pr_freeze_sync|* 100ns + set_max_delay -from *pcie_flr*launch[*] -to *pcie_flr*capture[*] 100ns + set_max_delay -from *pcie_top*dcfifo*|*delayed_wrptr_g* -to *pcie_top*dcfifo*|*rs_dgwp* 100ns + set_max_delay -from *pcie_top*dcfifo*|*rdptr_g* -to *pcie_top*dcfifo*|*ws_dgrp* 100ns + set_max_delay -from *altera_iopll_i*pll~pll_e_reg__nff -to *rst_ctrl|* 100ns + set_max_delay -from *pcie_top*pcie_s10_hip*reset_*_reg* -to *rst_ctrl|* 100ns + + set_false_path -to *_cal_*_sync_* -hold + set_false_path -to *resync_chains*synchronizer*|din* -hold + set_false_path -to *dcfifo_*dffpipe_*aclr|dffe*a[*] -hold + set_false_path -from *softreset* -to *pr_slot|rst_p0_tx_sync|d* -hold + set_false_path -from rst_n_e_1x -to *pr_slot|rst_p0_tx_sync|d* -hold + set_false_path -from rst_n_b_1x -to *pcie_bridge_cdc*dcfifo*|*aclr|dff* -hold + set_false_path -from *qph_user_clk_freq|prescaler[*] -to *qph_user_clk_freq|smpclk_meta -hold + set_false_path -from *pr_freeze[*] -to *pr_freeze_sync|* -hold + set_false_path -from *pcie_flr*launch[*] -to *pcie_flr*capture[*] -hold + set_false_path -from *pcie_top*dcfifo*|*delayed_wrptr_g* -to *pcie_top*dcfifo*|*rs_dgwp* -hold + set_false_path -from *pcie_top*dcfifo*|*rdptr_g* -to *pcie_top*dcfifo*|*ws_dgrp* -hold + set_false_path -from *altera_iopll_i*pll~pll_e_reg__nff -to *rst_ctrl|* -hold + set_false_path -from *pcie_top*pcie_s10_hip*reset_*_reg* -to *rst_ctrl|* -hold +} diff --git a/syn/setup/user_clock.sdc b/syn/setup/user_clock.sdc new file mode 100755 index 0000000..bfbccbc --- /dev/null +++ b/syn/setup/user_clock.sdc @@ -0,0 +1,53 @@ +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +# Description +#----------------------------------------------------------------------------- +# +# User clock SDC +# +#----------------------------------------------------------------------------- + +proc add_reset_sync_sdc { pin_name } { + set_max_delay -to [get_pins $pin_name] 100.000 + set_min_delay -to [get_pins $pin_name] -100.000 + #set_max_skew -to [get_pins $pin_name] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 +} + +proc add_sync_sdc { name } { + set_max_delay -to [get_keepers $name] 100.000 + set_min_delay -to [get_keepers $name] -100.000 +} + +#--------------------------------------------- +# CDC constraints for synchronizers +#--------------------------------------------- +add_sync_sdc {*|qph_user_clk|qph_user_clk_locked_resync|resync_chains[*].synchronizer_nocut|din_s1} + +# For input to a 2-FFs synchronizer chain within qph_user_clk module +set_false_path -from [get_registers {*|qph_user_clk|qph_user_clk_freq|prescaler[*]}] -to [get_registers {*|qph_user_clk|qph_user_clk_freq|smpclk_meta}] +set_false_path -from [get_registers {*|qph_user_clk|qph_user_clk_freq|prescaler_div2[*]}] -to [get_registers {*|qph_user_clk|qph_user_clk_freq|smpclk_meta_div2}] + +#--------------------------------------------- +# Multicycle path for handshake CDC between CSR clock and QPH clock domain +#--------------------------------------------- +# CSR to QPH crossing +set_multicycle_path -from {*|resync|csr_to_qph_sync|launch[*]} -to {*|resync|csr_to_qph_sync|capture[*]} -setup -end 2 +set_multicycle_path -from {*|resync|csr_to_qph_sync|launch[*]} -to {*|resync|csr_to_qph_sync|capture[*]} -hold -end 1 +set_multicycle_path -to {*|resync|csr_to_qph_sync|*_strb*sr*synchronizer_nocut*din_s1} 2 +set_false_path -hold -to {*|resync|csr_to_qph_sync|*_strb*sr*synchronizer_nocut*din_s1} + +# QPH to CSR crossing +set_multicycle_path -from {*|resync|qph_to_csr_sync|launch[*]} -to {*|resync|qph_to_csr_sync|capture[*]} -setup -end 2 +set_multicycle_path -from {*|resync|qph_to_csr_sync|launch[*]} -to {*|resync|qph_to_csr_sync|capture[*]} -hold -end 1 +set_multicycle_path -to {*|resync|qph_to_csr_sync|*_strb*sr*synchronizer_nocut*din_s1} 2 +set_false_path -hold -to {*|resync|qph_to_csr_sync|*_strb*sr*synchronizer_nocut*din_s1} + +#---------------------------------------------- +# Contraints for the clock mux that selects between user outclk[0] and outclk[1] +# to the input of frequency counter +#---------------------------------------------- +create_generated_clock -name qph_user_clk_clkpsc_clk0 -source [get_pins {*|qph_user_clk|qph_user_clk_iopll|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll|outclk[0]}] [get_pins {user_clock|qph_user_clk|qph_user_clk_freq|qph_user_clk_clkpsc|combout}] +create_generated_clock -add -name qph_user_clk_clkpsc_clk1 -source [get_pins {*|qph_user_clk|qph_user_clk_iopll|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll|outclk[1]}] [get_pins {user_clock|qph_user_clk|qph_user_clk_freq|qph_user_clk_clkpsc|combout}] + + diff --git a/syn/syn_top/build_flash/README b/syn/syn_top/build_flash/README new file mode 100644 index 0000000..4fa2696 --- /dev/null +++ b/syn/syn_top/build_flash/README @@ -0,0 +1,61 @@ + +Build Flash (for D5005 PAC card) + +The build flash files are located in the syn////scripts/build_flash folder + +The build_flash.sh is the top level script + +The purpose of the flash build is to construct images to update the 2Gb CFI flash file +(either whole flash update, or with just the user images) from the base build sof file. + +Main Inputs: +⦁ FIM image sof file + +Main Outputs: +⦁ .pof – image for the 2GB CFI flash for use with Quartus programmer and BMC bridge image. +⦁ _page1.bin – raw binary file for the OFS FIM user image (pre-PACSign) +⦁ _page1_unsigned.bin – OFS FIM user image to be used with fpgasupdate to perform in-system update of the user image in flash (post-PACSign) + +The build_flash.sh script performs the following tasks: +1. Sets up bit ordering of the binary components (root hey hashes, PFLII option bits, BMC FW) and + converts them to hex for consumption by the Quartus program file generator (specified in the d5005.pfg file) + uses reverse.py tool to swap bit order of every byte boundary +2. Calls Quartus program file generator to generate the .pof image from the include d5005.pfg file +3. Converts the .pof to a binary representation .bin + Note that the .bin contains infomation of the whole flash image (bin equivalent of the pof) + conversion to binary from pof has 2 steps: + - quartus_cpf is used to convert the pof to ihex format + - objcopy is used to convert ihex to bin +4. Extracts the user image from the .bin to _page1.bin + Note that _page1.bin has the page 1 image extracted. + This file does not contain any other informaion other than the user image bitstream +5. PACSigns the user image ofs_fim_page1.bin to ofs_fim_page1_unsigned.bin + Adds Block 0/1 data to the fpga bitstream for use with fpgasupdate tool + +The following files are used in setting up the flash image by the Quartus program file generator specified by d5005.pfg. +The main purpose is to generate the complete, unsigned pof image of the 2Gb CFI flash: +⦁ blank_bmc_key_programmed: blank key for BMC update +⦁ blank_bmc_root_hash: blank BMC update root key hash +⦁ blank_sr_key_programmed : blank key for FIM image update +⦁ blank_sr_root_hash: blank root key hash for FIM image update +⦁ darby_rot_xip_factory.bin: D5005 BMC FW image +⦁ darby_rot_xip_factory_header.bin: D5005 BMC FW factory hader +⦁ dc_option_bits: PFLII option bits with image size set to the space allotted in flash spec. + (note that the d5005.pfg file will automatically generate option bits that matches the size of the image at address 0x0. + This is not used as the option bits generated are only for that particular image size and may not match subsequent updates to the user image. + The dc_option_bits above has the correct sizes to account for any images and are used by the PFLII core) + Please reference the Stratix 10 configuration user guide for more information on editing the option bits + (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-config.pdf) + note that the option bits stored in dc_option_bits have the bit order reversed in every byte boundary +⦁ factory_image.sof – this is the factory image (resides at page 0 of the fpga images on the flash) + if the factory_image.sof is not present in the directory, the current project sof file will be copied as factory_image.sof + (page 0 and page 1 will be the same image) + If the user image is stable enough to be a fall back image, + copy the user image as 'factory_image.sof' and include it in the repository's build_flash directory +⦁ max10_device_table.bin.hex: contains the device tree for the BMC +The d5005.pfg specifies the files and flash address location of the above images. +The d5005.pfg is a Quartus PFG generated file and was modified for relative paths. + +Note that the .pof can be used to unsign PAC D5005 cards via 10-pin JTAG port. The BMC RoT bypass image (max10_flash_programming.sof) is not included with OFS. + + diff --git a/syn/syn_top/build_flash/blank_bmc_key_programmed b/syn/syn_top/build_flash/blank_bmc_key_programmed new file mode 100644 index 0000000..7bde864 --- /dev/null +++ b/syn/syn_top/build_flash/blank_bmc_key_programmed @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/syn/syn_top/build_flash/blank_bmc_root_hash b/syn/syn_top/build_flash/blank_bmc_root_hash new file mode 100644 index 0000000..d4af00a --- /dev/null +++ b/syn/syn_top/build_flash/blank_bmc_root_hash @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/syn/syn_top/build_flash/blank_sr_key_programmed b/syn/syn_top/build_flash/blank_sr_key_programmed new file mode 100644 index 0000000..7bde864 --- /dev/null +++ b/syn/syn_top/build_flash/blank_sr_key_programmed @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/syn/syn_top/build_flash/blank_sr_root_hash b/syn/syn_top/build_flash/blank_sr_root_hash new file mode 100644 index 0000000..d4af00a --- /dev/null +++ b/syn/syn_top/build_flash/blank_sr_root_hash @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/syn/syn_top/build_flash/build_flash.sh b/syn/syn_top/build_flash/build_flash.sh new file mode 100755 index 0000000..0e75e0a --- /dev/null +++ b/syn/syn_top/build_flash/build_flash.sh @@ -0,0 +1,100 @@ +#!/bin/bash +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +if [ -z ${Q_PROJECT} ]; then + Q_PROJECT="d5005" +fi +SOF_FILE=${Q_PROJECT}.sof + + +FACTORY_SOF="factory_image.sof" +PFG_FILE=d5005.pfg +pacsign_infile=${Q_PROJECT}_page1.bin +pacsign_outfile=${pacsign_infile%.*}_unsigned.bin + + + + +# this script can be run from build_fim.sh script or +# directly in the build_flash directory +if [ -z "${OFS_ROOTDIR}" ] ; then + LOCAL_SCRIPT_DIR="." +else + LOCAL_SCRIPT_DIR="$(dirname ${WORK_BUILD_FLASH_SH_FILE})/" +fi + +Q_OUTPUT_FILES_PATH="${LOCAL_SCRIPT_DIR}/../../syn_top/output_files" + +# check for factory_image.sof, if not available, +# copy over the ofs_fim.sof as the factory +if [ -e ${LOCAL_SCRIPT_DIR}/$FACTORY_SOF ]; then + echo "Using $FACTORY_SOF as the factory image" +else + if [ -e ${Q_OUTPUT_FILES_PATH}/${SOF_FILE} ]; then + echo "No ${FACTORY_SOF} found, but $SOF_FILE exists" + echo "Copying over $SOF_FILE as the $FACTORY_SOF" + cp --remove-destination ${Q_OUTPUT_FILES_PATH}/${SOF_FILE} ${LOCAL_SCRIPT_DIR}/${FACTORY_SOF} + echo "" + else + echo "Cannot find ${Q_OUTPUT_FILES_PATH}/${SOF_FILE}" + echo "Cannot find ${LOCAL_SCRIPT_DIR}/${FACTORY_SOF}" + echo "Check that you are running the script that is in the work directory" + echo " - this script uses relative paths to the compile output_files directory" + exit 1 + fi +fi + + +## blank bmc key - 4 bytes of FF +python3 reverse.py blank_bmc_key_programmed blank_bmc_key_programmed.reversed +objcopy -I binary -O ihex ${LOCAL_SCRIPT_DIR}/blank_bmc_key_programmed.reversed ${LOCAL_SCRIPT_DIR}/blank_bmc_key_programmed.reversed.hex + +## blank bmc root key hash - 32 bytes of FF +python3 ${LOCAL_SCRIPT_DIR}/reverse.py ${LOCAL_SCRIPT_DIR}/blank_bmc_root_hash ${LOCAL_SCRIPT_DIR}/blank_bmc_root_hash.reversed +objcopy -I binary -O ihex ${LOCAL_SCRIPT_DIR}/blank_bmc_root_hash.reversed ${LOCAL_SCRIPT_DIR}/blank_bmc_root_hash.reversed.hex + +## blank sr (FIM) key - 4 bytes of FF +python3 ${LOCAL_SCRIPT_DIR}/reverse.py ${LOCAL_SCRIPT_DIR}/blank_sr_key_programmed ${LOCAL_SCRIPT_DIR}/blank_sr_key_programmed.reversed +objcopy -I binary -O ihex blank_sr_key_programmed.reversed blank_sr_key_programmed.reversed.hex + +## blank sr (FIM) root key hash - 32 bytes of FF +python3 ${LOCAL_SCRIPT_DIR}/reverse.py ${LOCAL_SCRIPT_DIR}/blank_sr_root_hash ${LOCAL_SCRIPT_DIR}/blank_sr_root_hash.reversed +objcopy -I binary -O ihex ${LOCAL_SCRIPT_DIR}/blank_sr_root_hash.reversed ${LOCAL_SCRIPT_DIR}/blank_sr_root_hash.reversed.hex + + +### option bits +objcopy -I binary -O ihex ${LOCAL_SCRIPT_DIR}/pac_d5005_option_bits ${LOCAL_SCRIPT_DIR}/pac_d5005_option_bits.hex + +### pac_d5005_rot_xip_factory>bin.reversed +python3 ${LOCAL_SCRIPT_DIR}/reverse.py ${LOCAL_SCRIPT_DIR}/pac_d5005_rot_xip_factory.bin ${LOCAL_SCRIPT_DIR}/pac_d5005_rot_xip_factory.bin.reversed +objcopy -I binary -O ihex pac_d5005_rot_xip_factory.bin.reversed pac_d5005_rot_xip_factory.bin.reversed.hex + +### pac_d5005_rot_xip_factory_header.bin.reversed +python3 ${LOCAL_SCRIPT_DIR}/reverse.py ${LOCAL_SCRIPT_DIR}/pac_d5005_rot_xip_factory_header.bin ${LOCAL_SCRIPT_DIR}/pac_d5005_rot_xip_factory_header.bin.reversed +objcopy -I binary -O ihex ${LOCAL_SCRIPT_DIR}/pac_d5005_rot_xip_factory_header.bin.reversed ${LOCAL_SCRIPT_DIR}/pac_d5005_rot_xip_factory_header.bin.reversed.hex + + +# -- generate very special pof with no root entry hash information +quartus_pfg -c ${LOCAL_SCRIPT_DIR}/${PFG_FILE} + + +# -- generate ihex from pof +quartus_cpf -c ${Q_OUTPUT_FILES_PATH}/${Q_PROJECT}.pof ${Q_OUTPUT_FILES_PATH}/${Q_PROJECT}.hexout + +# -- convert to ihex to bin +objcopy -I ihex -O binary ${Q_OUTPUT_FILES_PATH}/${Q_PROJECT}.hexout ${Q_OUTPUT_FILES_PATH}/${Q_PROJECT}.bin + +python3 ${LOCAL_SCRIPT_DIR}/extract_bitstream.py ${Q_OUTPUT_FILES_PATH}/${Q_PROJECT}.map ${Q_OUTPUT_FILES_PATH}/${Q_PROJECT}.bin ${Q_OUTPUT_FILES_PATH}/$pacsign_infile + + +# -- generate manufacturing image for 3rd party programmer to write to flash before board assembly +# uncomment following line if mfg image is desired +python ${LOCAL_SCRIPT_DIR}/reverse.py ${Q_OUTPUT_FILES_PATH}/${Q_PROJECT}.bin ${Q_OUTPUT_FILES_PATH}/mfg_${Q_PROJECT}_reversed.bin + +# -- create unsigned FIM user image for fpgasupdate tool +if which PACSign &> /dev/null ; then + PACSign SR -y -v -t UPDATE -H openssl_manager -i ${Q_OUTPUT_FILES_PATH}/$pacsign_infile -o ${Q_OUTPUT_FILES_PATH}/$pacsign_outfile +else + echo "PACSign not found! Please manually sign ${Q_OUTPUT_FILES_PATH}/$pacsign_infile." 1>&2 +fi diff --git a/syn/syn_top/build_flash/d5005.pfg b/syn/syn_top/build_flash/d5005.pfg new file mode 100644 index 0000000..5de8cfe --- /dev/null +++ b/syn/syn_top/build_flash/d5005.pfg @@ -0,0 +1,78 @@ + + + + + + + + + Flash_Device_1 + + + + + ./factory_image.sof + + + ../../syn_top/output_files/d5005.sof + + + + ./blank_bmc_key_programmed.reversed.hex + ./blank_bmc_root_hash.reversed.hex + ./blank_sr_key_programmed.reversed.hex + ./blank_sr_root_hash.reversed.hex + ./pac_d5005_rot_xip_factory.bin.reversed.hex + ./pac_d5005_rot_xip_factory_header.bin.reversed.hex + ./max10_device_table.bin.hex + ./pac_d5005_option_bits.hex + + + + + + + + + + + + + + + + + + + Raw_File_6 + + + Raw_File_5 + + + Raw_File_4 + + + Raw_File_3 + + + Raw_File_2 + + + Raw_File_1 + + + Bitstream_2 + + + Bitstream_1 + + + Raw_File_8 + + + Raw_File_7 + + + + diff --git a/syn/syn_top/build_flash/extract_bitstream.py b/syn/syn_top/build_flash/extract_bitstream.py new file mode 100755 index 0000000..e9a07fa --- /dev/null +++ b/syn/syn_top/build_flash/extract_bitstream.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +import argparse +import logging +import re +import sys + +logging.basicConfig(level=0) +LOGGER= logging.getLogger(__name__) + +def main(args): + pof_map = args.map_file.read().decode('utf-8') + + m = re.search(r"Page_1\s+(0x[0-9a-fA-F]{8})\s+(0x[0-9a-fA-F]{8})", pof_map) + if not m: + LOGGER.error("Page_1 not found in map file") + sys.exit(1) + + start = int(m.group(1), 0) + bs_len = int(m.group(2), 0) - start + 1 + + args.in_file.seek(start) + bs = args.in_file.read(bs_len) + args.out_file.write(bs) + +if __name__ == '__main__': + + parser = argparse.ArgumentParser() + + parser.add_argument('map_file', type=argparse.FileType('rb'), + help='map_file of pof') + parser.add_argument('in_file', type=argparse.FileType('rb'), + help='binary input file') + parser.add_argument('out_file', type=argparse.FileType('wb'), + help='output file') + + args = parser.parse_args() + main(args) diff --git a/syn/syn_top/build_flash/max10_device_table.bin.hex b/syn/syn_top/build_flash/max10_device_table.bin.hex new file mode 100644 index 0000000..96fccd6 --- /dev/null +++ b/syn/syn_top/build_flash/max10_device_table.bin.hex @@ -0,0 +1,513 @@ +:100000000BB07FB7000004000000001C0000180CBB +:10001000000000140000008800000008000000003C +:10002000000000CA0000E81F0000000000000000FF +:100030000000000000000000000000800000000040 +:10004000000000C0000000300000000096762EA6E0 +:100050003634B6861E8C0C00000000C00000002064 +:10006000000000D000000080000000C00000002060 +:10007000000000580000008000000080CE9ECE2EC0 +:10008000A6B6B4B6867686E6A64E0000000000C08E +:10009000000000D80000000096762EA636B4B68682 +:1000A0001E8C0C34CE9ECE2EA6B6B4B6867686E6D0 +:1000B000A64E0000000000C000000020000000D09C +:1000C00000000080000000C0000000200000005878 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b/syn/syn_top/build_flash/pac_d5005_rot_xip_factory.bin new file mode 100644 index 0000000..3921efd Binary files /dev/null and b/syn/syn_top/build_flash/pac_d5005_rot_xip_factory.bin differ diff --git a/syn/syn_top/build_flash/pac_d5005_rot_xip_factory_header.bin b/syn/syn_top/build_flash/pac_d5005_rot_xip_factory_header.bin new file mode 100644 index 0000000..eb3cb0e Binary files /dev/null and b/syn/syn_top/build_flash/pac_d5005_rot_xip_factory_header.bin differ diff --git a/syn/syn_top/build_flash/reverse.py b/syn/syn_top/build_flash/reverse.py new file mode 100755 index 0000000..0ed175b --- /dev/null +++ b/syn/syn_top/build_flash/reverse.py @@ -0,0 +1,64 @@ +#!/usr/bin/env python3 +# Copyright 2020 Intel Corporation +# SPDX-License-Identifier: MIT + +from __future__ import absolute_import +import argparse +from array import array +import logging + +logging.basicConfig(level=0) # display all logger messages +LOGGER = logging.getLogger(__name__) + + +def reverse_bits(x, n): + result = 0 + for i in range(n): + if (x >> i) & 1: + result |= 1 << (n - 1 - i) + return result + + +def reverse_bits_in_file(ifile, ofile): + + LOGGER.info("Reading input file: %s" % ifile) + LOGGER.info("Writing output file: %s" % ofile) + bit_rev = array('B') + for i in range(0, 256): + bit_rev.append(reverse_bits(i, 8)) + + while True: + ichunk = ifile.read(4096) + if not ichunk: + break + + if isinstance(ichunk, str): + ochunk = '' + for b in ichunk: + ochunk += chr(bit_rev[ord(b)]) + ofile.write(ochunk) + elif isinstance(ichunk, bytes): + ochunk = [] + for b in ichunk: + ochunk.append(bit_rev[b]) + ofile.write(bytes(ochunk)) + LOGGER.info("Finished") + + +def main(): + parser = argparse.ArgumentParser() + parser.add_argument('ifile', type=argparse.FileType('rb'), + help='input file to be reversed') + parser.add_argument('ofile', type=argparse.FileType('wb'), + help='output file') + + args = parser.parse_args() + + reverse_bits_in_file(args.ifile, args.ofile) + + +if __name__ == '__main__': + + LOGGER.info("---Reverse Bits---") + main() + diff --git a/syn/syn_top/d5005.qpf b/syn/syn_top/d5005.qpf new file mode 100644 index 0000000..75b9922 --- /dev/null +++ b/syn/syn_top/d5005.qpf @@ -0,0 +1,18 @@ +# Copyright 2021 Intel Corporation +# SPDX-License-Identifier: MIT + +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 21.1.0 Build 169 03/24/2021 SC Pro Edition +# Date created = 15:33:07 May 06, 2021 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "21.1" +DATE = "15:33:07 May 06, 2021" + +# Revisions + +PROJECT_REVISION = "d5005" +PROJECT_REVISION = "iofs_pr_afu" diff --git a/syn/syn_top/d5005.qsf b/syn/syn_top/d5005.qsf new file mode 100644 index 0000000..3e43651 --- /dev/null +++ b/syn/syn_top/d5005.qsf @@ -0,0 +1,126 @@ +# Copyright (C) 2020-2022 Intel Corporation +# SPDX-License-Identifier: MIT + +set_global_assignment -name PRESERVE_FOR_DEBUG_ENABLE ON +############################################################################################ +# FPGA Device # +############################################################################################ + +set_global_assignment -name FAMILY "Stratix 10" +set_global_assignment -name DEVICE 1SX280HN2F43E2VG +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "1.2 V" +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION OFF +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON + +############################################################################################ +# Synthesis Options # +############################################################################################ + +set_global_assignment -name TOP_LEVEL_ENTITY iofs_top +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name OPTIMIZATION_MODE "SUPERIOR PERFORMANCE" +set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name ALLOW_REGISTER_RETIMING ON +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON +set_global_assignment -name MUX_RESTRUCTURE ON +set_global_assignment -name LAST_QUARTUS_VERSION "22.1.0 Pro Edition" +set_global_assignment -name FLOW_DISABLE_ASSEMBLER OFF +set_global_assignment -name FLOW_ENABLE_INTERACTIVE_TIMING_ANALYZER OFF + +############################################################################################ +# PWR MGMT +############################################################################################ +set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER" +set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 +set_global_assignment -name USE_PWRMGT_SDA SDM_IO12 +set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHZ" +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE OTHER +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 60 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "DIRECT FORMAT" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 1 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 3 +set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS +set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE OFF + +############################################################################################ +# Configuration Interface +############################################################################################ + +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "AVST X8" +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE AUTO +set_global_assignment -name GENERATE_PR_RBF_FILE ON +set_global_assignment -name ENABLE_ED_CRC_CHECK ON +set_global_assignment -name MINIMUM_SEU_INTERVAL 0 +set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ +set_global_assignment -name USE_CONF_DONE SDM_IO16 +set_global_assignment -name GENERATE_RBF_FILE ON + +#Required for Clk Tree Synthesis to pass on Quartus 21.1 +set_instance_assignment -name GLOBAL_SIGNAL ON -from pcie_wrapper|pcie_top|dut|pcie_s10_hip_ast_0|altera_pcie_s10_hip_ast_pipen1b_inst|altera_pcie_s10_hip_ast_pllnphy_inst|g_phy_g3x16.phy_g3x16|phy_g3x16|altera_xcvr_hip_channel_s10_ch0|altera_xcvr_pcie_hip_channel_s10_ch0|g_xcvr_native_insts[0].ct2_xcvr_native_inst|inst_ct2_xcvr_channel_multi|gen_rev.ct2_xcvr_channel_inst|out_pld_pcs_tx_clk_out1_dcm -to pcie_wrapper|pcie_top|dut|pcie_s10_hip_ast_0|pio_clkCtrl|altera_pio_clkctrl|clkdiv_inst -entity iofs_top +set_instance_assignment -name GLOBAL_SIGNAL OFF -to emif_top_inst|mem_bank[0].emif_ddr4_inst|emif_s10_0|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor -entity iofs_top +set_instance_assignment -name GLOBAL_SIGNAL OFF -to emif_top_inst|mem_bank[1].emif_ddr4_inst|emif_s10_0|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor -entity iofs_top +set_instance_assignment -name GLOBAL_SIGNAL OFF -to emif_top_inst|mem_bank[2].emif_ddr4_inst|emif_s10_0|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor -entity iofs_top +set_instance_assignment -name GLOBAL_SIGNAL OFF -to emif_top_inst|mem_bank[3].emif_ddr4_inst|emif_s10_0|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor -entity iofs_top + +############################################################################################ +# GLOBAL PINS # +############################################################################################ + +##### Electrical standard assigments +set_instance_assignment -name IO_STANDARD "LVDS" -to SYS_RefClk -entity iofs_top +set_instance_assignment -name IO_STANDARD "LVDS" -to SYS_RefClk(n) -entity iofs_top + +##### Location assignments +set_location_assignment PIN_AD8 -to SYS_RefClk +set_location_assignment PIN_AD9 -to SYS_RefClk(n) +set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to SYS_RefClk -entity iofs_top +set_global_assignment -name SEARCH_PATH ../../src +set_global_assignment -name SEARCH_PATH ../../src/includes +set_global_assignment -name IP_SEARCH_PATHS "$::env(BUILD_ROOT_REL)/src/pd_qsys/**/*;" + + +##### Verilog parameters +#set_global_assignment -name VERILOG_MACRO INCLUDE_SPI_BRIDGE +set_global_assignment -name VERILOG_MACRO INCLUDE_HSSI +set_global_assignment -name VERILOG_MACRO INCLUDE_HE_HSSI +#set_global_assignment -name VERILOG_MACRO DEBUG_MUX +#set_global_assignment -name VERILOG_MACRO DEBUG_APF +#set_global_assignment -name VERILOG_MACRO DEBUG_BPF + +############################################################################################ +# SIGNALTAP # +############################################################################################ +set_instance_assignment -name PARTITION_COLOUR 4294246223 -to iofs_top -entity iofs_top +set_instance_assignment -name PARTITION_COLOUR 4294952834 -to auto_fab_0 -entity iofs_top + +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE d5005.stp + +############################################################################################ +# SETUP # +############################################################################################ + +# Ensure that variables such as BUILD_ROOT_REL are set (must be relative) +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE ../setup/config_env.tcl + +set_global_assignment -name SEED 10 +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE ../setup/design_files_d5005.tcl diff --git a/syn/syn_top/d5005.stp b/syn/syn_top/d5005.stp new file mode 100644 index 0000000..f699719 --- /dev/null +++ b/syn/syn_top/d5005.stp @@ -0,0 +1,13583 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 11111 + 11111 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/syn/syn_top/fme_id.mif b/syn/syn_top/fme_id.mif new file mode 100644 index 0000000..ae60525 --- /dev/null +++ b/syn/syn_top/fme_id.mif @@ -0,0 +1,18 @@ +-- Quartus Prime generated Memory Initialization File (.mif) + +WIDTH=64; +DEPTH=8; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + 0 : 0123456789ABCDEF; + 1 : AAAAAAAAAAAAAAAA; + 2 : 2222222222222222; + 3 : EEEEEEEEEEEEEEEE; + 4 : 0000000000000001; + 5 : 0000000000000000; + 6 : 0000000000000000; + 7 : 0000000000000000; +END; diff --git a/syn/syn_top/iofs_pr_afu.json b/syn/syn_top/iofs_pr_afu.json new file mode 100644 index 0000000..13f48dd --- /dev/null +++ b/syn/syn_top/iofs_pr_afu.json @@ -0,0 +1,15 @@ +{ + "version": 1, + "afu-image": { + "power": 0, + "accelerator-clusters": + [ + { + "name": "iofs_pr_afu", + "total-contexts": 1, + "accelerator-type-uuid": "222baa4c-0ab8-4574-bf74-aa35b945a223" + } + ] + } +} + diff --git a/syn/syn_top/iofs_pr_afu.qsf b/syn/syn_top/iofs_pr_afu.qsf new file mode 100644 index 0000000..dd3a295 --- /dev/null +++ b/syn/syn_top/iofs_pr_afu.qsf @@ -0,0 +1,124 @@ +# Copyright (C) 2021-2023 Intel Corporation +# SPDX-License-Identifier: MIT + +############################################################################################ +# FPGA Device # +############################################################################################ + + +set_global_assignment -name FAMILY "Stratix 10" +set_global_assignment -name DEVICE 1SX280HN2F43E2VG +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "1.2 V" + +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION OFF +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON + +############################################################################################ +# Synthesis Options # +############################################################################################ + +set_global_assignment -name TOP_LEVEL_ENTITY iofs_top +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name OPTIMIZATION_MODE "SUPERIOR PERFORMANCE" +set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name ALLOW_REGISTER_RETIMING ON +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON +set_global_assignment -name MUX_RESTRUCTURE ON + +set_global_assignment -name LAST_QUARTUS_VERSION "22.3.0 Pro Edition" + +set_global_assignment -name FLOW_DISABLE_ASSEMBLER OFF +set_global_assignment -name FLOW_ENABLE_INTERACTIVE_TIMING_ANALYZER OFF +set_global_assignment -name SEED 0 + +############################################################################################ +# PWR MGMT +############################################################################################ + +set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER" +set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 +set_global_assignment -name USE_PWRMGT_SDA SDM_IO12 +set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHZ" +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE OTHER +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 60 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "DIRECT FORMAT" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 1 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 3 +set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS +set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE OFF + +############################################################################################ +# Configuration Interface +############################################################################################ + +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "AVST X8" +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE AUTO +set_global_assignment -name GENERATE_PR_RBF_FILE ON +set_global_assignment -name ENABLE_ED_CRC_CHECK ON +set_global_assignment -name MINIMUM_SEU_INTERVAL 0 +set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ + +set_global_assignment -name GENERATE_RBF_FILE ON + +############################################################################################ +# PARTIAL RECONFIGURATION # +############################################################################################ + +set_instance_assignment -name PARTITION persona1 -to afu_top|port_gasket|pr_slot|afu_main -entity iofs_top +set_instance_assignment -name QDB_FILE_PARTITION d5005.qdb -to | -entity iofs_top +set_instance_assignment -name ENTITY_REBINDING afu_main -to afu_top|port_gasket|pr_slot|afu_main -entity iofs_top +set_global_assignment -name REVISION_TYPE PR_IMPL + +# Load macros defined in the Quartus project during the FIM build. +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE fim_project_macros.tcl + +# IP required in a PR build from the base build (created by the OFS +# emit_project_ip.tcl script at the end of the FIM build) +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE fim_base_ip.tcl + +# Generate a GBS file at the end of the build +set_global_assignment -name POST_FLOW_SCRIPT_FILE quartus_sh:ofs_partial_reconfig/gen_gbs.tcl + +############################################################################################ +# Timing Constraints # +############################################################################################ + +# Timing constraints extracted from the FIM build +set_global_assignment -name SDC_FILE d5005.out.sdc +set_global_assignment -name SDC_FILE ../setup/user_clock.sdc + +# Compute user clock frequency and generate timing reports during quartus_sta +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT ofs_partial_reconfig/ofs_sta_report_script_pr.tcl + +############################################################################################ +# AFU design files # +############################################################################################ + +# Ensure that variables such as BUILD_ROOT_REL are set (must be relative) +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE ../setup/config_env.tcl + +## +## *** Sources are specified in iofs_pr_afu_sources.tcl, not in this .qsf file, so *** +## *** that scripting can be used. In addition, the PR out-of-tree build construction *** +## *** script depends on being able to replace the sources only in the .tcl file. *** +## + +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE iofs_pr_afu_sources.tcl diff --git a/syn/syn_top/iofs_pr_afu_sources.tcl b/syn/syn_top/iofs_pr_afu_sources.tcl new file mode 100644 index 0000000..8262cfa --- /dev/null +++ b/syn/syn_top/iofs_pr_afu_sources.tcl @@ -0,0 +1,56 @@ +# Copyright (C) 2021-2023 Intel Corporation +# SPDX-License-Identifier: MIT + +## +## Top-level AFU sources specification. +## +## Import AFU interfaces from the FIM as well as the AFU sources. +## + +# FIM-provided configuration scripts +set FIM_SCRIPT_DIR "../setup" + +##### OFS IP database + +# Add the constructed IP database to the search path. It was generated during +# the base FIM build. +set_global_assignment -name SEARCH_PATH "ofs_ip_cfg_db" + +# Create an empty ofs_ip_cfg_db namespace. The namespace is used by OFS IP +# during the FIM build but is not required for PR. Defining the namespace +# prevents errors in Tcl files that are shared by FIM and PR builds. +namespace eval ::ofs_ip_cfg_db {} + + +##### Paths were sources are found +set_global_assignment -name SEARCH_PATH $::env(BUILD_ROOT_REL)/src/includes + +##### Interfaces and definitions +set_global_assignment -name SYSTEMVERILOG_FILE $::env(BUILD_ROOT_REL)/src/afu_top/mux/top_cfg_pkg.sv +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE ${FIM_SCRIPT_DIR}/afu_if_design_files.tcl + +##### AFU <- Keep this tag. The pattern is used by scripts to update AFU sources. + +# OPAE_PLATFORM_GEN is set when a script is generating the PR build environment +# used with OPAE SDK tools. The Verilog macro is consumed in the PIM variant +# of afu_main, causing afu_main to act as a simple template that defines the module +# but doesn't include an actual AFU. +if { [info exist env(OPAE_PLATFORM_GEN) ] } { + # In OPAE_PLATFORM_GEN mode, no additional sources are loaded. The goal is + # to configure the minimal environment required to define AFU interfaces and + # instantiate the top-level PR module. + set_global_assignment -name VERILOG_MACRO OPAE_PLATFORM_GEN +} else { + # In non-OPAE_PLATFORM_GEN mode, a sample PR AFU is configured using the + # FIM-provided exercisers. These sources are required for those exercisers, + # but are unlikely to be required by other AFUs. + set_global_assignment -name SEARCH_PATH $::env(BUILD_ROOT_REL)/src + set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/ofs-common/src/common/ofs_common_design_files.tcl + set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/ofs-common/src/fpga_family/stratix10/common_design_files.tcl + set_global_assignment -name SOURCE_TCL_SCRIPT_FILE ${FIM_SCRIPT_DIR}/pcie_design_files.tcl + set_global_assignment -name SOURCE_TCL_SCRIPT_FILE ${FIM_SCRIPT_DIR}/eth_design_files.tcl + set_global_assignment -name SOURCE_TCL_SCRIPT_FILE ${FIM_SCRIPT_DIR}/afu_design_files.tcl +} + +# Import a specific AFU +set_global_assignment -name SOURCE_TCL_SCRIPT_FILE $::env(BUILD_ROOT_REL)/ofs-common/src/fpga_family/stratix10/afu_main.tcl diff --git a/syn/syn_top/pr_debug.stp b/syn/syn_top/pr_debug.stp new file mode 100644 index 0000000..374c94b --- /dev/null +++ b/syn/syn_top/pr_debug.stp @@ -0,0 +1,1678 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1111 + 1111 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 11 + 11 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1111 + 1111 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 11 + 11 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 11 + 11 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verification/README b/verification/README new file mode 100644 index 0000000..25b7f1b --- /dev/null +++ b/verification/README @@ -0,0 +1,86 @@ +How to setup UVM TB and run sumulation for UVM Testcase? + +Initial Setup: + 1) Get a Bash shell (e.g. xterm) + 2) Go to ./applications.fpga.ofs.reference-fims +For Internal Customers: + 3) source env_not_shipped/d5005/env.sh +For External Customers: + 3) Set all tool paths vcs, python etc. Please make sure Tool versions used are as follows: + VCS : vcsmx/T-2022.06-SP1-1 + VERDI: T-2022.06-SP1-1 + Python : python/3.7.7 + SNPS VIP Portfolio Version : vip_Q-2020.03A + PCIe VIP : Q-2020.03 + AXI VIP : Q-2020.03 + Ethernet VIP : Q-2020.03 + 4) Set the required environment and directory Structure variables (as shown below) + export OFS_ROOTDIR= + export QUARTUS_HOME= + export QUARTUS_INSTALL_DIR=$QUARTUS_HOME + export IMPORT_IP_ROOTDIR=$QUARTUS_HOME/../ip + export VERDIR=$OFS_ROOTDIR/verification + export VIPDIR=$VERDIR + export VIPDIR=$VERDIR + export DESIGNWARE_HOME= + export EMAIL_LIST=$OFS_ROOTDIR/ + +How to Run UVM Testcases for VCS?: +1) cd $VERDIR/scripts +2) For Compiling IPs and Subsystems, execute: "gmake -f Makefile_VCS.mk cmplib" +3) For building RTL & TB, execute: "gmake -f Makefile_VCS.mk build " +4) For run, execute: "gmake -f Makefile_VCS.mk run TESTNAME=mmio_test >" +5) Results are created in a sim directory ($VERDIR/sim) +6) How to build and run single testcase with coverage enabled? + gmake -f Makefile_VCS.mk build_all COV=1 && gmake -f Makefile_VCS.mk run TESTNAME=mmio_test COV=1 + +**Note: Step 2 Compiles IPs and subsystems from scratch instead of using precompiled versions. + This step can be skipped if there is no change in Quartus generated files from the previous build. + +**Note: To clean previous build and sim files, Run "gmake -f Makefile_VCS.mk clean" command. + +How to Run UVM Testcases for MSIM?: +1) cd $VERDIR/scripts +2) For Compiling IPs and Subsystems, execute: "gmake -f Makefile_MSIM.mk cmplib" +3) For building RTL & TB, execute: "gmake -f Makefile_MSIM.mk build " +4) For run, execute: "gmake -f Makefile_MSIM.mk run TESTNAME=mmio_test >" +5) Results are created in a sim directory ($VERDIR/sim_msim) + +**Note: Step 2 Compiles IPs and subsystems from scratch instead of using precompiled versions. + This step can be skipped if there is no change in Quartus generated files from the previous build. + +**Note: To clean previous build and sim files, Run "gmake -f Makefile_MSIM.mk clean" command. + + +How to Run UVM Regressions?: + +** usage : python uvm_regress.py --help + + -l, --local Run regression locally, or run it on Farm. (Default:False) + -n[N], --n_procs [N] Maximum number of processes/UVM tests to run in parallel when run locally. This has no effect on Farm run. (Default #CPUs-1: 11) + -s [{vcs,msim}], --sim [{vcs,msim}] Simulator used for regression test. (Default: vcs) + -c , --cov Code coverage used for regression, if any. (Default:fun_cov) + -e --email_list Sends the regression results on email provided in list (Default : It will send it to regression Owner) + +1) cd $VERDIR/scripts + +###run locally, with 8 processes, for adp platform, using top_pkg set of tests, using VCS with code coverage.  +python uvm_regress.py -l -n 8 -s vcs -c -e + +###run locally, with 8 processes, for adp platform, using top_pkg set of tests, using VCS with no code coverage.  +python uvm_regress.py -l -n 8 -s vcs -e + +###Same as above, but run on Intel Farm (no --local):   +python uvm_regress.py --sim vcs -c -e + +###Running script using defaults: run on Farm, adp platform, using top_pkg set of tests, using VCS with no code coverage and sends result to owner +python uvm_regress.py + +2) Results are created in a sim directory ($VERDIR/sim) with individual testcase log dir + + +**Note: Each testcase runs with random seeds in regression. +**Note: To run regression using MSIM :python uvm_regress.py -l -n 8 -s msim -e + + + diff --git a/verification/coverage/Tag_remap_exclusions.el b/verification/coverage/Tag_remap_exclusions.el new file mode 100644 index 0000000..2d2faed --- /dev/null +++ b/verification/coverage/Tag_remap_exclusions.el @@ -0,0 +1,279 @@ +//================================================== +// This file contains the Excluded objects +// Generated By User: ppawar2x +// Format Version: 2 +// Date: Mon Apr 4 00:08:13 2022 +// ExclMode: default +//================================================== +CHECKSUM: "3630569307" +INSTANCE:tb_top.DUT.afu_top.tag_remap.map.tag_pool.out_fifo.sfifo.scfifo_inst.dev +CHECKSUM: "2100166288" +INSTANCE:tb_top.DUT.afu_top.tag_remap.map.tag_pool.out_fifo.sfifo.scfifo_inst +CHECKSUM: "3552924867 1999692272" +INSTANCE: tb_top.DUT.afu_top.tag_remap.map.tag_pool +Condition 6 "2289557457" "(((!rst_n)) || ((!test_ram_rdy))) 1 -1" (3 "10") +CHECKSUM: "1525786188 2015403655" +INSTANCE: tb_top.DUT.afu_top.tag_remap.map.tag_pool.out_fifo +Toggle 0to1 sclr "logic sclr" +Toggle 1to0 sclr "logic sclr" +CHECKSUM: "1434925502 1296707280" +INSTANCE: tb_top.DUT.afu_top.tag_remap.map.tx_arb.gen_1way_arbiter.inst_fair_arbiter_1way +Toggle 0to1 hold_priority "logic hold_priority" +Toggle 1to0 hold_priority "logic hold_priority" +CHECKSUM: "4202741256 701653482" +INSTANCE: tb_top.DUT.afu_top.tag_remap.map.ho2mx_rx_in +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "4202741256 701653482" +INSTANCE: tb_top.DUT.afu_top.tag_remap.map.rx_axis_pipe.r.axis_pl[0] +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "4202741256 701653482" +INSTANCE: tb_top.DUT.afu_top.tag_remap.map.rx_axis_pipe.r.axis_pl[1] +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "4202741256 701653482" +INSTANCE: tb_top.DUT.afu_top.tag_remap.map.mx2ho_tx_out[0] +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "4202741256 701653482" +INSTANCE: tb_top.DUT.afu_top.tag_remap.mx2ho_tx_port_vec[0] +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "4202741256 701653482" +INSTANCE: tb_top.DUT.afu_top.tag_remap.mx2ho_tx_remap_vec[0] +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "1259019545 3297052881" +INSTANCE: tb_top.DUT.afu_top.tag_remap.map.rx_axis_pipe.r.axis_pl_stage[0].axis_reg_inst +Toggle m_tdest "net m_tdest[7:0]" +Toggle m_tid "net m_tid[7:0]" +Toggle genblk1.s_tdest_reg "reg genblk1.s_tdest_reg[7:0]" +Toggle genblk1.s_tid_reg "reg genblk1.s_tid_reg[7:0]" +Toggle genblk1.m_tdest_pre "reg genblk1.m_tdest_pre[7:0]" +Toggle s_tid "net s_tid[7:0]" +Toggle s_tdest "net s_tdest[7:0]" +Toggle genblk1.m_tid_reg "reg genblk1.m_tid_reg[7:0]" +Toggle genblk1.m_tid_pre "reg genblk1.m_tid_pre[7:0]" +Toggle genblk1.m_tdest_reg "reg genblk1.m_tdest_reg[7:0]" +Toggle 0to1 m_tuser [9] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [9] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [1] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [1] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [2] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [2] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [3] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [3] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [4] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [4] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [5] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [5] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [6] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [6] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [7] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [7] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [8] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [8] "net m_tuser[9:0]" +Toggle 0to1 s_tuser [9] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [9] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [1] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [1] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [2] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [2] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [3] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [3] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [4] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [4] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [5] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [5] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [6] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [6] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [7] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [7] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [8] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [8] "net s_tuser[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +CHECKSUM: "3190985420 2753199155" +INSTANCE: tb_top.DUT.afu_top.tag_remap.map.tag_reg +Toggle 0to1 perr "logic perr" +Toggle 1to0 perr "logic perr" +Toggle 0to1 perr_or "logic perr_or" +Toggle 1to0 perr_or "logic perr_or" +Toggle 0to1 perr_in [0] "logic perr_in[0:0]" +Toggle 1to0 perr_in [0] "logic perr_in[0:0]" +CHECKSUM: "3190985420 3798477159" +INSTANCE: tb_top.DUT.afu_top.tag_remap.map.tag_pool.tracker +Toggle 0to1 perr "logic perr" +Toggle 1to0 perr "logic perr" +Toggle 0to1 perr_or "logic perr_or" +Toggle 1to0 perr_or "logic perr_or" +Toggle 0to1 perr_in [0] "logic perr_in[0:0]" +Toggle 1to0 perr_in [0] "logic perr_in[0:0]" +CHECKSUM: "124270709 2518479107" +INSTANCE: tb_top.DUT.afu_top.tag_remap.map.tag_pool.out_fifo.sfifo +Toggle 0to1 sclr "logic sclr" +Toggle 1to0 sclr "logic sclr" +CHECKSUM: "1259019545 702362531" +INSTANCE: tb_top.DUT.afu_top.tag_remap.map.rx_axis_pipe.r.axis_pl_stage[0].axis_reg_inst +Condition 1 "4206754987" "(((~genblk1.s_tready_pre)) && genblk1.s_tready_reg) 1 -1" (1 "01") +CHECKSUM: "3777034231 604730263" +INSTANCE: tb_top.DUT.afu_top.tag_remap.map.tx_arb +Toggle 0to1 hold_priority [0] "logic hold_priority[0:0]" +Toggle 1to0 hold_priority [0] "logic hold_priority[0:0]" +CHECKSUM: "3589944323 1280539332" +INSTANCE: tb_top.DUT.afu_top.tag_remap.map.tag_reg.genblk2.inst_gram_sdp +Toggle 0to1 driveX "reg driveX" +Toggle 1to0 driveX "reg driveX" +ANNOTATION: " these signals are used when only GRAM_MODE!=0, here GRAM_MODE is 'h0. " +Toggle ram_dout "reg ram_dout[6:0]" +ANNOTATION: " these signals are used when only GRAM_MODE!=0, here GRAM_MODE is 'h0. " +Toggle raddr_q "reg raddr_q[6:0]" diff --git a/verification/coverage/a_port_exclusions.el b/verification/coverage/a_port_exclusions.el new file mode 100644 index 0000000..e815acd --- /dev/null +++ b/verification/coverage/a_port_exclusions.el @@ -0,0 +1,365 @@ +//================================================== +// This file contains the Excluded objects +// Generated By User: srudrarx +// Format Version: 2 +// Date: Wed May 25 02:58:18 2022 +// ExclMode: default +//================================================== +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.fn2mx_tx_a_port[2] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.fn2mx_tx_a_port[3] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.afu_tx_a_port[1] +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_a_port[0] +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_a_port[1] +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_a_port[2] +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_a_port[3] +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_a_port[0] +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_a_port[1] +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_a_port[2] +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_a_port[3] +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.afu_tx_a_port[0] +Toggle 0to1 tkeep [31] "logic tkeep[63:0]" +Toggle 1to0 tkeep [31] "logic tkeep[63:0]" +Toggle 0to1 tkeep [0] "logic tkeep[63:0]" +Toggle 1to0 tkeep [0] "logic tkeep[63:0]" +Toggle 0to1 tkeep [1] "logic tkeep[63:0]" +Toggle 1to0 tkeep [1] "logic tkeep[63:0]" +Toggle 0to1 tkeep [2] "logic tkeep[63:0]" +Toggle 1to0 tkeep [2] "logic tkeep[63:0]" +Toggle 0to1 tkeep [3] "logic tkeep[63:0]" +Toggle 1to0 tkeep [3] "logic tkeep[63:0]" +Toggle 0to1 tkeep [4] "logic tkeep[63:0]" +Toggle 1to0 tkeep [4] "logic tkeep[63:0]" +Toggle 0to1 tkeep [5] "logic tkeep[63:0]" +Toggle 1to0 tkeep [5] "logic tkeep[63:0]" +Toggle 0to1 tkeep [6] "logic tkeep[63:0]" +Toggle 1to0 tkeep [6] "logic tkeep[63:0]" +Toggle 0to1 tkeep [7] "logic tkeep[63:0]" +Toggle 1to0 tkeep [7] "logic tkeep[63:0]" +Toggle 0to1 tkeep [8] "logic tkeep[63:0]" +Toggle 1to0 tkeep [8] "logic tkeep[63:0]" +Toggle 0to1 tkeep [9] "logic tkeep[63:0]" +Toggle 1to0 tkeep [9] "logic tkeep[63:0]" +Toggle 0to1 tkeep [10] "logic tkeep[63:0]" +Toggle 1to0 tkeep [10] "logic tkeep[63:0]" +Toggle 0to1 tkeep [11] "logic tkeep[63:0]" +Toggle 1to0 tkeep [11] "logic tkeep[63:0]" +Toggle 0to1 tkeep [12] "logic tkeep[63:0]" +Toggle 1to0 tkeep [12] "logic tkeep[63:0]" +Toggle 0to1 tkeep [13] "logic tkeep[63:0]" +Toggle 1to0 tkeep [13] "logic tkeep[63:0]" +Toggle 0to1 tkeep [14] "logic tkeep[63:0]" +Toggle 1to0 tkeep [14] "logic tkeep[63:0]" +Toggle 0to1 tkeep [15] "logic tkeep[63:0]" +Toggle 1to0 tkeep [15] "logic tkeep[63:0]" +Toggle 0to1 tkeep [16] "logic tkeep[63:0]" +Toggle 1to0 tkeep [16] "logic tkeep[63:0]" +Toggle 0to1 tkeep [17] "logic tkeep[63:0]" +Toggle 1to0 tkeep [17] "logic tkeep[63:0]" +Toggle 0to1 tkeep [18] "logic tkeep[63:0]" +Toggle 1to0 tkeep [18] "logic tkeep[63:0]" +Toggle 0to1 tkeep [19] "logic tkeep[63:0]" +Toggle 1to0 tkeep [19] "logic tkeep[63:0]" +Toggle 0to1 tkeep [20] "logic tkeep[63:0]" +Toggle 1to0 tkeep [20] "logic tkeep[63:0]" +Toggle 0to1 tkeep [21] "logic tkeep[63:0]" +Toggle 1to0 tkeep [21] "logic tkeep[63:0]" +Toggle 0to1 tkeep [22] "logic tkeep[63:0]" +Toggle 1to0 tkeep [22] "logic tkeep[63:0]" +Toggle 0to1 tkeep [23] "logic tkeep[63:0]" +Toggle 1to0 tkeep [23] "logic tkeep[63:0]" +Toggle 0to1 tkeep [24] "logic tkeep[63:0]" +Toggle 1to0 tkeep [24] "logic tkeep[63:0]" +Toggle 0to1 tkeep [25] "logic tkeep[63:0]" +Toggle 1to0 tkeep [25] "logic tkeep[63:0]" +Toggle 0to1 tkeep [26] "logic tkeep[63:0]" +Toggle 1to0 tkeep [26] "logic tkeep[63:0]" +Toggle 0to1 tkeep [27] "logic tkeep[63:0]" +Toggle 1to0 tkeep [27] "logic tkeep[63:0]" +Toggle 0to1 tkeep [28] "logic tkeep[63:0]" +Toggle 1to0 tkeep [28] "logic tkeep[63:0]" +Toggle 0to1 tkeep [29] "logic tkeep[63:0]" +Toggle 1to0 tkeep [29] "logic tkeep[63:0]" +Toggle 0to1 tkeep [30] "logic tkeep[63:0]" +Toggle 1to0 tkeep [30] "logic tkeep[63:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_a_port[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_a_port[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_a_port[3] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_a_port[2] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_a_port[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_a_port[2] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_a_port[3] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.afu_rx_a_port[0] +Assert assert_tdata_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.afu_rx_a_port[1] +Assert assert_tdata_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_a_port[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.afu_tx_a_port[0] +Assert assert_tdata_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.afu_tx_a_port[1] +Assert assert_tdata_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" diff --git a/verification/coverage/afu_protocol.el b/verification/coverage/afu_protocol.el new file mode 100644 index 0000000..1c5b09e --- /dev/null +++ b/verification/coverage/afu_protocol.el @@ -0,0 +1,3961 @@ +//================================================== +// This file contains the Excluded objects +// Generated By User: srudrarx +// Format Version: 2 +// Date: Thu Jun 9 22:21:13 2022 +// ExclMode: default +//================================================== +CHECKSUM: "3204455366" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst.pri_enc.p4 +CHECKSUM: "1911647781" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router +CHECKSUM: "528445187" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst.pri_enc.p3 +CHECKSUM: "2447340884" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_demux_002 +CHECKSUM: "2447340884" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_demux_003 +CHECKSUM: "604022260" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst.pri_enc.p2 +CHECKSUM: "1918984139" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst.pri_enc.p1 +CHECKSUM: "3156651152" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_achk_slv_altera_axi4lite_slave_agent +CHECKSUM: "2475624245" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_001 +CHECKSUM: "1410300878" +INSTANCE:tb_top.DUT.afu_top.apf.apf_achk_slv.apf_achk_slv +CHECKSUM: "1410300878" +INSTANCE:tb_top.DUT.afu_top.apf.apf_bpf_mst.apf_bpf_mst +CHECKSUM: "1410300878" +INSTANCE:tb_top.DUT.afu_top.apf.apf_bpf_slv.apf_bpf_slv +CHECKSUM: "1410300878" +INSTANCE:tb_top.DUT.afu_top.apf.apf_st2mm_mst.apf_st2mm_mst +CHECKSUM: "1410300878" +INSTANCE:tb_top.DUT.afu_top.apf.apf_st2mm_slv.apf_st2mm_slv +CHECKSUM: "1542397522" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_002.the_default_decode +CHECKSUM: "2037871818" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_003.the_default_decode +CHECKSUM: "3965101838" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_mux +CHECKSUM: "3965101838" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_mux_001 +CHECKSUM: "3965101838" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_mux_004 +CHECKSUM: "3965101838" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_mux_005 +CHECKSUM: "3965101838" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_mux_006 +CHECKSUM: "3965101838" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_mux_007 +CHECKSUM: "3965101838" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_mux_008 +CHECKSUM: "3965101838" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_mux_009 +CHECKSUM: "3965101838" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_mux_010 +CHECKSUM: "3965101838" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_mux_011 +CHECKSUM: "3965101838" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_mux_012 +CHECKSUM: "3965101838" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_mux_013 +CHECKSUM: "3965101838" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_mux_014 +CHECKSUM: "3965101838" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_mux_015 +CHECKSUM: "3965101838" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_mux_016 +CHECKSUM: "3965101838" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_mux_017 +CHECKSUM: "243855812" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_005 +CHECKSUM: "243855812" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_009 +CHECKSUM: "243855812" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_011 +CHECKSUM: "243855812" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_013 +CHECKSUM: "243855812" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_015 +CHECKSUM: "243855812" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_017 +CHECKSUM: "243855812" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_019 +CHECKSUM: "243855812" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_021 +CHECKSUM: "1804361750" +INSTANCE:tb_top.DUT.afu_top.apf.apf_bpf_slv +CHECKSUM: "4245844112" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_004 +CHECKSUM: "4245844112" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_008 +CHECKSUM: "4245844112" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_010 +CHECKSUM: "4245844112" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_012 +CHECKSUM: "4245844112" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_014 +CHECKSUM: "4245844112" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_016 +CHECKSUM: "4245844112" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_018 +CHECKSUM: "4245844112" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_020 +CHECKSUM: "3265406813" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst.pri_enc.p0.p1 +CHECKSUM: "3265406813" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst.pri_enc.p1.p1 +CHECKSUM: "3265406813" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst.pri_enc.p2.p1 +CHECKSUM: "3265406813" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst.pri_enc.p3.p1 +CHECKSUM: "3265406813" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst.pri_enc.p4.p1 +CHECKSUM: "3265406813" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst.pri_enc.p5.p1 +CHECKSUM: "2709875921" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_bpf_slv_altera_axi4lite_slave_agent.read_burst_uncompressor +CHECKSUM: "2709875921" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_st2mm_slv_altera_axi4lite_slave_agent.read_burst_uncompressor +CHECKSUM: "2709875921" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_achk_slv_altera_axi4lite_slave_agent.read_burst_uncompressor +CHECKSUM: "3420762164" +INSTANCE:tb_top.DUT.afu_top.apf.apf_achk_slv +CHECKSUM: "3318579355" +INSTANCE:tb_top.DUT.afu_top.apf.apf_clock_bridge +CHECKSUM: "1112658341" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_007.the_default_decode +CHECKSUM: "4249558537" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_bpf_slv_altera_axi4lite_slave_agent +CHECKSUM: "2588071009" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_mux +CHECKSUM: "2588071009" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_mux_001 +CHECKSUM: "2004148774" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_demux_002 +CHECKSUM: "2004148774" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_demux_003 +CHECKSUM: "2004148774" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_demux +CHECKSUM: "2004148774" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_demux_001 +CHECKSUM: "2004148774" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_demux_004 +CHECKSUM: "2004148774" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_demux_005 +CHECKSUM: "2004148774" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_demux_006 +CHECKSUM: "2004148774" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_demux_007 +CHECKSUM: "2004148774" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_demux_008 +CHECKSUM: "2004148774" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_demux_009 +CHECKSUM: "2004148774" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_demux_010 +CHECKSUM: "2004148774" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_demux_011 +CHECKSUM: "2004148774" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_demux_012 +CHECKSUM: "2004148774" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_demux_013 +CHECKSUM: "2004148774" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_demux_014 +CHECKSUM: "2004148774" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_demux_015 +CHECKSUM: "2004148774" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_demux_016 +CHECKSUM: "2004148774" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_demux_017 +CHECKSUM: "4273098319" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_007 +CHECKSUM: "309578334" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_mux_002 +CHECKSUM: "309578334" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_mux_003 +CHECKSUM: "676339810" +INSTANCE:tb_top.DUT.afu_top.apf.apf_reset_bridge +CHECKSUM: "1287734984" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0 +CHECKSUM: "878525151" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst.pri_enc.p5 +CHECKSUM: "3982549083" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_st2mm_slv_altera_axi4lite_slave_agent +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.rst_hs_resync.resync_chains[0].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.rst_hs_resync.resync_chains[1].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.rst_hs_resync.resync_chains[2].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.rst_hs_resync.resync_chains[3].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.rst_hs_resync.resync_chains[4].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.rst_hs_resync.resync_chains[5].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.rst_hs_resync.resync_chains[6].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.rst_hs_resync.resync_chains[7].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.rst_hs_resync.resync_chains[8].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.rst_hs_resync.resync_chains[9].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.rst_hs_resync.resync_chains[10].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.rst_hs_resync.resync_chains[11].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.rst_hs_resync.resync_chains[12].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.rst_hs_resync.resync_chains[13].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.rst_hs_resync.resync_chains[14].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.rst_hs_resync.resync_chains[15].genblk1.synchronizer +CHECKSUM: "422023275" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_002 +CHECKSUM: "2916460945" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_st2mm_mst_altera_axi4lite_master_agent +CHECKSUM: "2916460945" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_bpf_mst_altera_axi4lite_master_agent +CHECKSUM: "1820093876" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst.pri_enc.p0.p0 +CHECKSUM: "1820093876" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst.pri_enc.p1.p0 +CHECKSUM: "1820093876" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst.pri_enc.p2.p0 +CHECKSUM: "1820093876" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst.pri_enc.p3.p0 +CHECKSUM: "1820093876" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst.pri_enc.p4.p0 +CHECKSUM: "1820093876" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst.pri_enc.p5.p0 +CHECKSUM: "3806301588" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst.pri_enc.s0 +CHECKSUM: "2188741727" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_005.the_default_decode +CHECKSUM: "2188741727" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_009.the_default_decode +CHECKSUM: "2188741727" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_011.the_default_decode +CHECKSUM: "2188741727" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_013.the_default_decode +CHECKSUM: "2188741727" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_015.the_default_decode +CHECKSUM: "2188741727" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_017.the_default_decode +CHECKSUM: "2188741727" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_019.the_default_decode +CHECKSUM: "2188741727" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_021.the_default_decode +CHECKSUM: "2725671737" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.rst_hs_resync +CHECKSUM: "1818569026" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_bpf_slv_altera_axi4lite_slave_agent.write_rsp_fifo.my_altera_avalon_sc_fifo_wr +CHECKSUM: "1818569026" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_bpf_slv_altera_axi4lite_slave_agent.read_rsp_fifo.my_altera_avalon_sc_fifo_wr +CHECKSUM: "1818569026" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_st2mm_slv_altera_axi4lite_slave_agent.write_rsp_fifo.my_altera_avalon_sc_fifo_wr +CHECKSUM: "1818569026" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_st2mm_slv_altera_axi4lite_slave_agent.read_rsp_fifo.my_altera_avalon_sc_fifo_wr +CHECKSUM: "1818569026" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_achk_slv_altera_axi4lite_slave_agent.write_rsp_fifo.my_altera_avalon_sc_fifo_wr +CHECKSUM: "1818569026" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_achk_slv_altera_axi4lite_slave_agent.read_rsp_fifo.my_altera_avalon_sc_fifo_wr +CHECKSUM: "3937263212" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_mux_002.arb +CHECKSUM: "3937263212" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_mux_003.arb +CHECKSUM: "3937263212" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_mux.arb +CHECKSUM: "3937263212" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_mux_001.arb +CHECKSUM: "1364503136" +INSTANCE:tb_top.DUT.afu_top.apf.apf_bpf_mst +CHECKSUM: "4005113863" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_mux_002 +CHECKSUM: "4005113863" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_mux_003 +CHECKSUM: "114691403" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_bpf_slv_altera_axi4lite_slave_agent.check_and_align_address_to_size +CHECKSUM: "114691403" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_st2mm_slv_altera_axi4lite_slave_agent.check_and_align_address_to_size +CHECKSUM: "114691403" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_achk_slv_altera_axi4lite_slave_agent.check_and_align_address_to_size +CHECKSUM: "128344353" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_001.the_default_decode +CHECKSUM: "4198356598" +INSTANCE:tb_top.DUT.afu_top.apf.apf_st2mm_mst +CHECKSUM: "147046857" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router.the_default_decode +CHECKSUM: "3982988022" +INSTANCE:tb_top.DUT.afu_top.apf.apf_st2mm_slv +CHECKSUM: "3339211258" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_mux_002.arb.adder +CHECKSUM: "3339211258" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_mux_003.arb.adder +CHECKSUM: "3339211258" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_mux.arb.adder +CHECKSUM: "3339211258" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.rsp_mux_001.arb.adder +CHECKSUM: "1214479269" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst.pri_enc.p0 +CHECKSUM: "612941108" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_006 +CHECKSUM: "2588178902" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_bpf_slv_altera_axi4lite_slave_agent.write_rsp_fifo +CHECKSUM: "2588178902" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_bpf_slv_altera_axi4lite_slave_agent.read_rsp_fifo +CHECKSUM: "2588178902" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_st2mm_slv_altera_axi4lite_slave_agent.write_rsp_fifo +CHECKSUM: "2588178902" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_st2mm_slv_altera_axi4lite_slave_agent.read_rsp_fifo +CHECKSUM: "2588178902" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_achk_slv_altera_axi4lite_slave_agent.write_rsp_fifo +CHECKSUM: "2588178902" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_achk_slv_altera_axi4lite_slave_agent.read_rsp_fifo +CHECKSUM: "1458656250" +INSTANCE:tb_top.DUT.fme_top.pfa_master +CHECKSUM: "1374988421" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_demux +CHECKSUM: "1374988421" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.cmd_demux_001 +CHECKSUM: "3179375656" +INSTANCE:tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst.pri_enc +CHECKSUM: "1374955797" +INSTANCE:tb_top.DUT.fme_top.pgn +CHECKSUM: "2204854892" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_004.the_default_decode +CHECKSUM: "2204854892" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_008.the_default_decode +CHECKSUM: "2204854892" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_010.the_default_decode +CHECKSUM: "2204854892" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_012.the_default_decode +CHECKSUM: "2204854892" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_014.the_default_decode +CHECKSUM: "2204854892" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_016.the_default_decode +CHECKSUM: "2204854892" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_018.the_default_decode +CHECKSUM: "2204854892" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_020.the_default_decode +CHECKSUM: "703567974" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_006.the_default_decode +CHECKSUM: "3947213816" +INSTANCE:tb_top.DUT.afu_top.apf.mm_interconnect_0.router_003 +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.tx_filter_if +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tkeep [31] "logic tkeep[63:0]" +Toggle 1to0 tkeep [31] "logic tkeep[63:0]" +Toggle 0to1 tkeep [0] "logic tkeep[63:0]" +Toggle 1to0 tkeep [0] "logic tkeep[63:0]" +Toggle 0to1 tkeep [1] "logic tkeep[63:0]" +Toggle 1to0 tkeep [1] "logic tkeep[63:0]" +Toggle 0to1 tkeep [2] "logic tkeep[63:0]" +Toggle 1to0 tkeep [2] "logic tkeep[63:0]" +Toggle 0to1 tkeep [3] "logic tkeep[63:0]" +Toggle 1to0 tkeep [3] "logic tkeep[63:0]" +Toggle 0to1 tkeep [4] "logic tkeep[63:0]" +Toggle 1to0 tkeep [4] "logic tkeep[63:0]" +Toggle 0to1 tkeep [5] "logic tkeep[63:0]" +Toggle 1to0 tkeep [5] "logic tkeep[63:0]" +Toggle 0to1 tkeep [6] "logic tkeep[63:0]" +Toggle 1to0 tkeep [6] "logic tkeep[63:0]" +Toggle 0to1 tkeep [7] "logic tkeep[63:0]" +Toggle 1to0 tkeep [7] "logic tkeep[63:0]" +Toggle 0to1 tkeep [8] "logic tkeep[63:0]" +Toggle 1to0 tkeep [8] "logic tkeep[63:0]" +Toggle 0to1 tkeep [9] "logic tkeep[63:0]" +Toggle 1to0 tkeep [9] "logic tkeep[63:0]" +Toggle 0to1 tkeep [10] "logic tkeep[63:0]" +Toggle 1to0 tkeep [10] "logic tkeep[63:0]" +Toggle 0to1 tkeep [11] "logic tkeep[63:0]" +Toggle 1to0 tkeep [11] "logic tkeep[63:0]" +Toggle 0to1 tkeep [12] "logic tkeep[63:0]" +Toggle 1to0 tkeep [12] "logic tkeep[63:0]" +Toggle 0to1 tkeep [13] "logic tkeep[63:0]" +Toggle 1to0 tkeep [13] "logic tkeep[63:0]" +Toggle 0to1 tkeep [14] "logic tkeep[63:0]" +Toggle 1to0 tkeep [14] "logic tkeep[63:0]" +Toggle 0to1 tkeep [15] "logic tkeep[63:0]" +Toggle 1to0 tkeep [15] "logic tkeep[63:0]" +Toggle 0to1 tkeep [16] "logic tkeep[63:0]" +Toggle 1to0 tkeep [16] "logic tkeep[63:0]" +Toggle 0to1 tkeep [17] "logic tkeep[63:0]" +Toggle 1to0 tkeep [17] "logic tkeep[63:0]" +Toggle 0to1 tkeep [18] "logic tkeep[63:0]" +Toggle 1to0 tkeep [18] "logic tkeep[63:0]" +Toggle 0to1 tkeep [19] "logic tkeep[63:0]" +Toggle 1to0 tkeep [19] "logic tkeep[63:0]" +Toggle 0to1 tkeep [20] "logic tkeep[63:0]" +Toggle 1to0 tkeep [20] "logic tkeep[63:0]" +Toggle 0to1 tkeep [21] "logic tkeep[63:0]" +Toggle 1to0 tkeep [21] "logic tkeep[63:0]" +Toggle 0to1 tkeep [22] "logic tkeep[63:0]" +Toggle 1to0 tkeep [22] "logic tkeep[63:0]" +Toggle 0to1 tkeep [23] "logic tkeep[63:0]" +Toggle 1to0 tkeep [23] "logic tkeep[63:0]" +Toggle 0to1 tkeep [24] "logic tkeep[63:0]" +Toggle 1to0 tkeep [24] "logic tkeep[63:0]" +Toggle 0to1 tkeep [25] "logic tkeep[63:0]" +Toggle 1to0 tkeep [25] "logic tkeep[63:0]" +Toggle 0to1 tkeep [26] "logic tkeep[63:0]" +Toggle 1to0 tkeep [26] "logic tkeep[63:0]" +Toggle 0to1 tkeep [27] "logic tkeep[63:0]" +Toggle 1to0 tkeep [27] "logic tkeep[63:0]" +Toggle 0to1 tkeep [28] "logic tkeep[63:0]" +Toggle 1to0 tkeep [28] "logic tkeep[63:0]" +Toggle 0to1 tkeep [29] "logic tkeep[63:0]" +Toggle 1to0 tkeep [29] "logic tkeep[63:0]" +Toggle 0to1 tkeep [30] "logic tkeep[63:0]" +Toggle 1to0 tkeep [30] "logic tkeep[63:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.tx_filter_mmio_if +Toggle 1to0 tdata [32] "logic tdata[511:0]" +Toggle 0to1 tdata [32] "logic tdata[511:0]" +Toggle 1to0 tdata [33] "logic tdata[511:0]" +Toggle 0to1 tdata [33] "logic tdata[511:0]" +Toggle 1to0 tdata [62] "logic tdata[511:0]" +Toggle 0to1 tdata [62] "logic tdata[511:0]" +Toggle 1to0 tdata [61] "logic tdata[511:0]" +Toggle 0to1 tdata [61] "logic tdata[511:0]" +Toggle 1to0 tdata [59] "logic tdata[511:0]" +Toggle 0to1 tdata [59] "logic tdata[511:0]" +Toggle 1to0 tdata [57] "logic tdata[511:0]" +Toggle 0to1 tdata [57] "logic tdata[511:0]" +Toggle 1to0 tdata [56] "logic tdata[511:0]" +Toggle 0to1 tdata [56] "logic tdata[511:0]" +Toggle 1to0 tdata [60] "logic tdata[511:0]" +Toggle 0to1 tdata [60] "logic tdata[511:0]" +Toggle 1to0 tdata [58] "logic tdata[511:0]" +Toggle 0to1 tdata [58] "logic tdata[511:0]" +Toggle 1to0 tdata [55] "logic tdata[511:0]" +Toggle 0to1 tdata [55] "logic tdata[511:0]" +Toggle 1to0 tdata [53] "logic tdata[511:0]" +Toggle 0to1 tdata [53] "logic tdata[511:0]" +Toggle 1to0 tdata [51] "logic tdata[511:0]" +Toggle 0to1 tdata [51] "logic tdata[511:0]" +Toggle 1to0 tdata [50] "logic tdata[511:0]" +Toggle 0to1 tdata [50] "logic tdata[511:0]" +Toggle 1to0 tdata [47] "logic tdata[511:0]" +Toggle 0to1 tdata [47] "logic tdata[511:0]" +Toggle 1to0 tdata [46] "logic tdata[511:0]" +Toggle 0to1 tdata [46] "logic tdata[511:0]" +Toggle 1to0 tdata [45] "logic tdata[511:0]" +Toggle 0to1 tdata [45] "logic tdata[511:0]" +Toggle 1to0 tdata [44] "logic tdata[511:0]" +Toggle 0to1 tdata [44] "logic tdata[511:0]" +Toggle 1to0 tdata [42] "logic tdata[511:0]" +Toggle 0to1 tdata [42] "logic tdata[511:0]" +Toggle 1to0 tdata [40] "logic tdata[511:0]" +Toggle 0to1 tdata [40] "logic tdata[511:0]" +Toggle 1to0 tdata [43] "logic tdata[511:0]" +Toggle 0to1 tdata [43] "logic tdata[511:0]" +Toggle 1to0 tdata [41] "logic tdata[511:0]" +Toggle 0to1 tdata [41] "logic tdata[511:0]" +Toggle 1to0 tdata [48] "logic tdata[511:0]" +Toggle 0to1 tdata [48] "logic tdata[511:0]" +Toggle 1to0 tdata [49] "logic tdata[511:0]" +Toggle 0to1 tdata [49] "logic tdata[511:0]" +Toggle 1to0 tdata [52] "logic tdata[511:0]" +Toggle 0to1 tdata [52] "logic tdata[511:0]" +Toggle 1to0 tdata [54] "logic tdata[511:0]" +Toggle 0to1 tdata [54] "logic tdata[511:0]" +Toggle 1to0 tdata [39] "logic tdata[511:0]" +Toggle 0to1 tdata [39] "logic tdata[511:0]" +Toggle 1to0 tdata [36] "logic tdata[511:0]" +Toggle 0to1 tdata [36] "logic tdata[511:0]" +Toggle 1to0 tdata [38] "logic tdata[511:0]" +Toggle 0to1 tdata [38] "logic tdata[511:0]" +Toggle 1to0 tdata [37] "logic tdata[511:0]" +Toggle 0to1 tdata [37] "logic tdata[511:0]" +Toggle 1to0 tdata [63] "logic tdata[511:0]" +Toggle 0to1 tdata [63] "logic tdata[511:0]" +Toggle 1to0 tdata [71] "logic tdata[511:0]" +Toggle 0to1 tdata [71] "logic tdata[511:0]" +Toggle 1to0 tdata [78] "logic tdata[511:0]" +Toggle 0to1 tdata [78] "logic tdata[511:0]" +Toggle 1to0 tdata [77] "logic tdata[511:0]" +Toggle 0to1 tdata [77] "logic tdata[511:0]" +Toggle 1to0 tdata [79] "logic tdata[511:0]" +Toggle 0to1 tdata [79] "logic tdata[511:0]" +ANNOTATION: " TKEEP assigned fixed value depend on access type " +Toggle tkeep "logic tkeep[63:0]" +Toggle tuser_vendor "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 clk "net clk" +Toggle 1to0 clk "net clk" +Toggle 0to1 tdata [255] "logic tdata[511:0]" +Toggle 1to0 tdata [255] "logic tdata[511:0]" +Toggle 0to1 tdata [81] "logic tdata[511:0]" +Toggle 1to0 tdata [81] "logic tdata[511:0]" +Toggle 0to1 tdata [82] "logic tdata[511:0]" +Toggle 1to0 tdata [82] "logic tdata[511:0]" +Toggle 0to1 tdata [83] "logic tdata[511:0]" +Toggle 1to0 tdata [83] "logic tdata[511:0]" +Toggle 0to1 tdata [84] "logic tdata[511:0]" +Toggle 1to0 tdata [84] "logic tdata[511:0]" +Toggle 0to1 tdata [85] "logic tdata[511:0]" +Toggle 1to0 tdata [85] "logic tdata[511:0]" +Toggle 0to1 tdata [86] "logic tdata[511:0]" +Toggle 1to0 tdata [86] "logic tdata[511:0]" +Toggle 0to1 tdata [87] "logic tdata[511:0]" +Toggle 1to0 tdata [87] "logic tdata[511:0]" +Toggle 0to1 tdata [88] "logic tdata[511:0]" +Toggle 1to0 tdata [88] "logic tdata[511:0]" +Toggle 0to1 tdata [89] "logic tdata[511:0]" +Toggle 1to0 tdata [89] "logic tdata[511:0]" +Toggle 0to1 tdata [90] "logic tdata[511:0]" +Toggle 1to0 tdata [90] "logic tdata[511:0]" +Toggle 0to1 tdata [91] "logic tdata[511:0]" +Toggle 1to0 tdata [91] "logic tdata[511:0]" +Toggle 0to1 tdata [92] "logic tdata[511:0]" +Toggle 1to0 tdata [92] "logic tdata[511:0]" +Toggle 0to1 tdata [93] "logic tdata[511:0]" +Toggle 1to0 tdata [93] "logic tdata[511:0]" +Toggle 0to1 tdata [94] "logic tdata[511:0]" +Toggle 1to0 tdata [94] "logic tdata[511:0]" +Toggle 0to1 tdata [95] "logic tdata[511:0]" +Toggle 1to0 tdata [95] "logic tdata[511:0]" +Toggle 0to1 tdata [96] "logic tdata[511:0]" +Toggle 1to0 tdata [96] "logic tdata[511:0]" +Toggle 0to1 tdata [97] "logic tdata[511:0]" +Toggle 1to0 tdata [97] "logic tdata[511:0]" +Toggle 0to1 tdata [98] "logic tdata[511:0]" +Toggle 1to0 tdata [98] "logic tdata[511:0]" +Toggle 0to1 tdata [99] "logic tdata[511:0]" +Toggle 1to0 tdata [99] "logic tdata[511:0]" +Toggle 0to1 tdata [100] "logic tdata[511:0]" +Toggle 1to0 tdata [100] "logic tdata[511:0]" +Toggle 0to1 tdata [101] "logic tdata[511:0]" +Toggle 1to0 tdata [101] "logic tdata[511:0]" +Toggle 0to1 tdata [102] "logic tdata[511:0]" +Toggle 1to0 tdata [102] "logic tdata[511:0]" +Toggle 0to1 tdata [103] "logic tdata[511:0]" +Toggle 1to0 tdata [103] "logic tdata[511:0]" +Toggle 0to1 tdata [104] "logic tdata[511:0]" +Toggle 1to0 tdata [104] "logic tdata[511:0]" +Toggle 0to1 tdata [105] "logic tdata[511:0]" +Toggle 1to0 tdata [105] "logic tdata[511:0]" +Toggle 0to1 tdata [106] "logic tdata[511:0]" +Toggle 1to0 tdata [106] "logic tdata[511:0]" +Toggle 0to1 tdata [107] "logic tdata[511:0]" +Toggle 1to0 tdata [107] "logic tdata[511:0]" +Toggle 0to1 tdata [108] "logic tdata[511:0]" +Toggle 1to0 tdata [108] "logic tdata[511:0]" +Toggle 0to1 tdata [109] "logic tdata[511:0]" +Toggle 1to0 tdata [109] "logic tdata[511:0]" +Toggle 0to1 tdata [110] "logic tdata[511:0]" +Toggle 1to0 tdata [110] "logic tdata[511:0]" +Toggle 0to1 tdata [111] "logic tdata[511:0]" +Toggle 1to0 tdata [111] "logic tdata[511:0]" +Toggle 0to1 tdata [112] "logic tdata[511:0]" +Toggle 1to0 tdata [112] "logic tdata[511:0]" +Toggle 0to1 tdata [113] "logic tdata[511:0]" +Toggle 1to0 tdata [113] "logic tdata[511:0]" +Toggle 0to1 tdata [114] "logic tdata[511:0]" +Toggle 1to0 tdata [114] "logic tdata[511:0]" +Toggle 0to1 tdata [115] "logic tdata[511:0]" +Toggle 1to0 tdata [115] "logic tdata[511:0]" +Toggle 0to1 tdata [116] "logic tdata[511:0]" +Toggle 1to0 tdata [116] "logic tdata[511:0]" +Toggle 0to1 tdata [117] "logic tdata[511:0]" +Toggle 1to0 tdata [117] "logic tdata[511:0]" +Toggle 0to1 tdata [118] "logic tdata[511:0]" +Toggle 1to0 tdata [118] "logic tdata[511:0]" +Toggle 0to1 tdata [119] "logic tdata[511:0]" +Toggle 1to0 tdata [119] "logic tdata[511:0]" +Toggle 0to1 tdata [120] "logic tdata[511:0]" +Toggle 1to0 tdata [120] "logic tdata[511:0]" +Toggle 0to1 tdata [121] "logic tdata[511:0]" +Toggle 1to0 tdata [121] "logic tdata[511:0]" +Toggle 0to1 tdata [122] "logic tdata[511:0]" +Toggle 1to0 tdata [122] "logic tdata[511:0]" +Toggle 0to1 tdata [123] "logic tdata[511:0]" +Toggle 1to0 tdata [123] "logic tdata[511:0]" +Toggle 0to1 tdata [124] "logic tdata[511:0]" +Toggle 1to0 tdata [124] "logic tdata[511:0]" +Toggle 0to1 tdata [125] "logic tdata[511:0]" +Toggle 1to0 tdata [125] "logic tdata[511:0]" +Toggle 0to1 tdata [126] "logic tdata[511:0]" +Toggle 1to0 tdata [126] "logic tdata[511:0]" +Toggle 0to1 tdata [127] "logic tdata[511:0]" +Toggle 1to0 tdata [127] "logic tdata[511:0]" +Toggle 0to1 tdata [128] "logic tdata[511:0]" +Toggle 1to0 tdata [128] "logic tdata[511:0]" +Toggle 0to1 tdata [129] "logic tdata[511:0]" +Toggle 1to0 tdata [129] "logic tdata[511:0]" +Toggle 0to1 tdata [130] "logic tdata[511:0]" +Toggle 1to0 tdata [130] "logic tdata[511:0]" +Toggle 0to1 tdata [131] "logic tdata[511:0]" +Toggle 1to0 tdata [131] "logic tdata[511:0]" +Toggle 0to1 tdata [132] "logic tdata[511:0]" +Toggle 1to0 tdata [132] "logic tdata[511:0]" +Toggle 0to1 tdata [133] "logic tdata[511:0]" +Toggle 1to0 tdata [133] "logic tdata[511:0]" +Toggle 0to1 tdata [134] "logic tdata[511:0]" +Toggle 1to0 tdata [134] "logic tdata[511:0]" +Toggle 0to1 tdata [135] "logic tdata[511:0]" +Toggle 1to0 tdata [135] "logic tdata[511:0]" +Toggle 0to1 tdata [136] "logic tdata[511:0]" +Toggle 1to0 tdata [136] "logic tdata[511:0]" +Toggle 0to1 tdata [137] "logic tdata[511:0]" +Toggle 1to0 tdata [137] "logic tdata[511:0]" +Toggle 0to1 tdata [138] "logic tdata[511:0]" +Toggle 1to0 tdata [138] "logic tdata[511:0]" +Toggle 0to1 tdata [139] "logic tdata[511:0]" +Toggle 1to0 tdata [139] "logic tdata[511:0]" +Toggle 0to1 tdata [140] "logic tdata[511:0]" +Toggle 1to0 tdata [140] "logic tdata[511:0]" +Toggle 0to1 tdata [141] "logic tdata[511:0]" +Toggle 1to0 tdata [141] "logic tdata[511:0]" +Toggle 0to1 tdata [142] "logic tdata[511:0]" +Toggle 1to0 tdata [142] "logic tdata[511:0]" +Toggle 0to1 tdata [143] "logic tdata[511:0]" +Toggle 1to0 tdata [143] "logic tdata[511:0]" +Toggle 0to1 tdata [144] "logic tdata[511:0]" +Toggle 1to0 tdata [144] "logic tdata[511:0]" +Toggle 0to1 tdata [145] "logic tdata[511:0]" +Toggle 1to0 tdata [145] "logic tdata[511:0]" +Toggle 0to1 tdata [146] "logic tdata[511:0]" +Toggle 1to0 tdata [146] "logic tdata[511:0]" +Toggle 0to1 tdata [147] "logic tdata[511:0]" +Toggle 1to0 tdata [147] "logic tdata[511:0]" +Toggle 0to1 tdata [148] "logic tdata[511:0]" +Toggle 1to0 tdata [148] "logic tdata[511:0]" +Toggle 0to1 tdata [149] "logic tdata[511:0]" +Toggle 1to0 tdata [149] "logic tdata[511:0]" +Toggle 0to1 tdata [150] "logic tdata[511:0]" +Toggle 1to0 tdata [150] "logic tdata[511:0]" +Toggle 0to1 tdata [151] "logic tdata[511:0]" +Toggle 1to0 tdata [151] "logic tdata[511:0]" +Toggle 0to1 tdata [152] "logic tdata[511:0]" +Toggle 1to0 tdata [152] "logic tdata[511:0]" +Toggle 0to1 tdata [153] "logic tdata[511:0]" +Toggle 1to0 tdata [153] "logic tdata[511:0]" +Toggle 0to1 tdata [154] "logic tdata[511:0]" +Toggle 1to0 tdata [154] "logic tdata[511:0]" +Toggle 0to1 tdata [155] "logic tdata[511:0]" +Toggle 1to0 tdata [155] "logic tdata[511:0]" +Toggle 0to1 tdata [156] "logic tdata[511:0]" +Toggle 1to0 tdata [156] "logic tdata[511:0]" +Toggle 0to1 tdata [157] "logic tdata[511:0]" +Toggle 1to0 tdata [157] "logic tdata[511:0]" +Toggle 0to1 tdata [158] "logic tdata[511:0]" +Toggle 1to0 tdata [158] "logic tdata[511:0]" +Toggle 0to1 tdata [159] "logic tdata[511:0]" +Toggle 1to0 tdata [159] "logic tdata[511:0]" +Toggle 0to1 tdata [160] "logic tdata[511:0]" +Toggle 1to0 tdata [160] "logic tdata[511:0]" +Toggle 0to1 tdata [161] "logic tdata[511:0]" +Toggle 1to0 tdata [161] "logic tdata[511:0]" +Toggle 0to1 tdata [162] "logic tdata[511:0]" +Toggle 1to0 tdata [162] "logic tdata[511:0]" +Toggle 0to1 tdata [163] "logic tdata[511:0]" +Toggle 1to0 tdata [163] "logic tdata[511:0]" +Toggle 0to1 tdata [164] "logic tdata[511:0]" +Toggle 1to0 tdata [164] "logic tdata[511:0]" +Toggle 0to1 tdata [165] "logic tdata[511:0]" +Toggle 1to0 tdata [165] "logic tdata[511:0]" +Toggle 0to1 tdata [166] "logic tdata[511:0]" +Toggle 1to0 tdata [166] "logic tdata[511:0]" +Toggle 0to1 tdata [167] "logic tdata[511:0]" +Toggle 1to0 tdata [167] "logic tdata[511:0]" +Toggle 0to1 tdata [168] "logic tdata[511:0]" +Toggle 1to0 tdata [168] "logic tdata[511:0]" +Toggle 0to1 tdata [169] "logic tdata[511:0]" +Toggle 1to0 tdata [169] "logic tdata[511:0]" +Toggle 0to1 tdata [170] "logic tdata[511:0]" +Toggle 1to0 tdata [170] "logic tdata[511:0]" +Toggle 0to1 tdata [171] "logic tdata[511:0]" +Toggle 1to0 tdata [171] "logic tdata[511:0]" +Toggle 0to1 tdata [172] "logic tdata[511:0]" +Toggle 1to0 tdata [172] "logic tdata[511:0]" +Toggle 0to1 tdata [173] "logic tdata[511:0]" +Toggle 1to0 tdata [173] "logic tdata[511:0]" +Toggle 0to1 tdata [174] "logic tdata[511:0]" +Toggle 1to0 tdata [174] "logic tdata[511:0]" +Toggle 0to1 tdata [175] "logic tdata[511:0]" +Toggle 1to0 tdata [175] "logic tdata[511:0]" +Toggle 0to1 tdata [176] "logic tdata[511:0]" +Toggle 1to0 tdata [176] "logic tdata[511:0]" +Toggle 0to1 tdata [177] "logic tdata[511:0]" +Toggle 1to0 tdata [177] "logic tdata[511:0]" +Toggle 0to1 tdata [178] "logic tdata[511:0]" +Toggle 1to0 tdata [178] "logic tdata[511:0]" +Toggle 0to1 tdata [179] "logic tdata[511:0]" +Toggle 1to0 tdata [179] "logic tdata[511:0]" +Toggle 0to1 tdata [180] "logic tdata[511:0]" +Toggle 1to0 tdata [180] "logic tdata[511:0]" +Toggle 0to1 tdata [181] "logic tdata[511:0]" +Toggle 1to0 tdata [181] "logic tdata[511:0]" +Toggle 0to1 tdata [182] "logic tdata[511:0]" +Toggle 1to0 tdata [182] "logic tdata[511:0]" +Toggle 0to1 tdata [183] "logic tdata[511:0]" +Toggle 1to0 tdata [183] "logic tdata[511:0]" +Toggle 0to1 tdata [184] "logic tdata[511:0]" +Toggle 1to0 tdata [184] "logic tdata[511:0]" +Toggle 0to1 tdata [185] "logic tdata[511:0]" +Toggle 1to0 tdata [185] "logic tdata[511:0]" +Toggle 0to1 tdata [186] "logic tdata[511:0]" +Toggle 1to0 tdata [186] "logic tdata[511:0]" +Toggle 0to1 tdata [187] "logic tdata[511:0]" +Toggle 1to0 tdata [187] "logic tdata[511:0]" +Toggle 0to1 tdata [188] "logic tdata[511:0]" +Toggle 1to0 tdata [188] "logic tdata[511:0]" +Toggle 0to1 tdata [189] "logic tdata[511:0]" +Toggle 1to0 tdata [189] "logic tdata[511:0]" +Toggle 0to1 tdata [190] "logic tdata[511:0]" +Toggle 1to0 tdata [190] "logic tdata[511:0]" +Toggle 0to1 tdata [191] "logic tdata[511:0]" +Toggle 1to0 tdata [191] "logic tdata[511:0]" +Toggle 0to1 tdata [192] "logic tdata[511:0]" +Toggle 1to0 tdata [192] "logic tdata[511:0]" +Toggle 0to1 tdata [193] "logic tdata[511:0]" +Toggle 1to0 tdata [193] "logic tdata[511:0]" +Toggle 0to1 tdata [194] "logic tdata[511:0]" +Toggle 1to0 tdata [194] "logic tdata[511:0]" +Toggle 0to1 tdata [195] "logic tdata[511:0]" +Toggle 1to0 tdata [195] "logic tdata[511:0]" +Toggle 0to1 tdata [196] "logic tdata[511:0]" +Toggle 1to0 tdata [196] "logic tdata[511:0]" +Toggle 0to1 tdata [197] "logic tdata[511:0]" +Toggle 1to0 tdata [197] "logic tdata[511:0]" +Toggle 0to1 tdata [198] "logic tdata[511:0]" +Toggle 1to0 tdata [198] "logic tdata[511:0]" +Toggle 0to1 tdata [199] "logic tdata[511:0]" +Toggle 1to0 tdata [199] "logic tdata[511:0]" +Toggle 0to1 tdata [200] "logic tdata[511:0]" +Toggle 1to0 tdata [200] "logic tdata[511:0]" +Toggle 0to1 tdata [201] "logic tdata[511:0]" +Toggle 1to0 tdata [201] "logic tdata[511:0]" +Toggle 0to1 tdata [202] "logic tdata[511:0]" +Toggle 1to0 tdata [202] "logic tdata[511:0]" +Toggle 0to1 tdata [203] "logic tdata[511:0]" +Toggle 1to0 tdata [203] "logic tdata[511:0]" +Toggle 0to1 tdata [204] "logic tdata[511:0]" +Toggle 1to0 tdata [204] "logic tdata[511:0]" +Toggle 0to1 tdata [205] "logic tdata[511:0]" +Toggle 1to0 tdata [205] "logic tdata[511:0]" +Toggle 0to1 tdata [206] "logic tdata[511:0]" +Toggle 1to0 tdata [206] "logic tdata[511:0]" +Toggle 0to1 tdata [207] "logic tdata[511:0]" +Toggle 1to0 tdata [207] "logic tdata[511:0]" +Toggle 0to1 tdata [208] "logic tdata[511:0]" +Toggle 1to0 tdata [208] "logic tdata[511:0]" +Toggle 0to1 tdata [209] "logic tdata[511:0]" +Toggle 1to0 tdata [209] "logic tdata[511:0]" +Toggle 0to1 tdata [210] "logic tdata[511:0]" +Toggle 1to0 tdata [210] "logic tdata[511:0]" +Toggle 0to1 tdata [211] "logic tdata[511:0]" +Toggle 1to0 tdata [211] "logic tdata[511:0]" +Toggle 0to1 tdata [212] "logic tdata[511:0]" +Toggle 1to0 tdata [212] "logic tdata[511:0]" +Toggle 0to1 tdata [213] "logic tdata[511:0]" +Toggle 1to0 tdata [213] "logic tdata[511:0]" +Toggle 0to1 tdata [214] "logic tdata[511:0]" +Toggle 1to0 tdata [214] "logic tdata[511:0]" +Toggle 0to1 tdata [215] "logic tdata[511:0]" +Toggle 1to0 tdata [215] "logic tdata[511:0]" +Toggle 0to1 tdata [216] "logic tdata[511:0]" +Toggle 1to0 tdata [216] "logic tdata[511:0]" +Toggle 0to1 tdata [217] "logic tdata[511:0]" +Toggle 1to0 tdata [217] "logic tdata[511:0]" +Toggle 0to1 tdata [218] "logic tdata[511:0]" +Toggle 1to0 tdata [218] "logic tdata[511:0]" +Toggle 0to1 tdata [219] "logic tdata[511:0]" +Toggle 1to0 tdata [219] "logic tdata[511:0]" +Toggle 0to1 tdata [220] "logic tdata[511:0]" +Toggle 1to0 tdata [220] "logic tdata[511:0]" +Toggle 0to1 tdata [221] "logic tdata[511:0]" +Toggle 1to0 tdata [221] "logic tdata[511:0]" +Toggle 0to1 tdata [222] "logic tdata[511:0]" +Toggle 1to0 tdata [222] "logic tdata[511:0]" +Toggle 0to1 tdata [223] "logic tdata[511:0]" +Toggle 1to0 tdata [223] "logic tdata[511:0]" +Toggle 0to1 tdata [224] "logic tdata[511:0]" +Toggle 1to0 tdata [224] "logic tdata[511:0]" +Toggle 0to1 tdata [225] "logic tdata[511:0]" +Toggle 1to0 tdata [225] "logic tdata[511:0]" +Toggle 0to1 tdata [226] "logic tdata[511:0]" +Toggle 1to0 tdata [226] "logic tdata[511:0]" +Toggle 0to1 tdata [227] "logic tdata[511:0]" +Toggle 1to0 tdata [227] "logic tdata[511:0]" +Toggle 0to1 tdata [228] "logic tdata[511:0]" +Toggle 1to0 tdata [228] "logic tdata[511:0]" +Toggle 0to1 tdata [229] "logic tdata[511:0]" +Toggle 1to0 tdata [229] "logic tdata[511:0]" +Toggle 0to1 tdata [230] "logic tdata[511:0]" +Toggle 1to0 tdata [230] "logic tdata[511:0]" +Toggle 0to1 tdata [231] "logic tdata[511:0]" +Toggle 1to0 tdata [231] "logic tdata[511:0]" +Toggle 0to1 tdata [232] "logic tdata[511:0]" +Toggle 1to0 tdata [232] "logic tdata[511:0]" +Toggle 0to1 tdata [233] "logic tdata[511:0]" +Toggle 1to0 tdata [233] "logic tdata[511:0]" +Toggle 0to1 tdata [234] "logic tdata[511:0]" +Toggle 1to0 tdata [234] "logic tdata[511:0]" +Toggle 0to1 tdata [235] "logic tdata[511:0]" +Toggle 1to0 tdata [235] "logic tdata[511:0]" +Toggle 0to1 tdata [236] "logic tdata[511:0]" +Toggle 1to0 tdata [236] "logic tdata[511:0]" +Toggle 0to1 tdata [237] "logic tdata[511:0]" +Toggle 1to0 tdata [237] "logic tdata[511:0]" +Toggle 0to1 tdata [238] "logic tdata[511:0]" +Toggle 1to0 tdata [238] "logic tdata[511:0]" +Toggle 0to1 tdata [239] "logic tdata[511:0]" +Toggle 1to0 tdata [239] "logic tdata[511:0]" +Toggle 0to1 tdata [240] "logic tdata[511:0]" +Toggle 1to0 tdata [240] "logic tdata[511:0]" +Toggle 0to1 tdata [241] "logic tdata[511:0]" +Toggle 1to0 tdata [241] "logic tdata[511:0]" +Toggle 0to1 tdata [242] "logic tdata[511:0]" +Toggle 1to0 tdata [242] "logic tdata[511:0]" +Toggle 0to1 tdata [243] "logic tdata[511:0]" +Toggle 1to0 tdata [243] "logic tdata[511:0]" +Toggle 0to1 tdata [244] "logic tdata[511:0]" +Toggle 1to0 tdata [244] "logic tdata[511:0]" +Toggle 0to1 tdata [245] "logic tdata[511:0]" +Toggle 1to0 tdata [245] "logic tdata[511:0]" +Toggle 0to1 tdata [246] "logic tdata[511:0]" +Toggle 1to0 tdata [246] "logic tdata[511:0]" +Toggle 0to1 tdata [247] "logic tdata[511:0]" +Toggle 1to0 tdata [247] "logic tdata[511:0]" +Toggle 0to1 tdata [248] "logic tdata[511:0]" +Toggle 1to0 tdata [248] "logic tdata[511:0]" +Toggle 0to1 tdata [249] "logic tdata[511:0]" +Toggle 1to0 tdata [249] "logic tdata[511:0]" +Toggle 0to1 tdata [250] "logic tdata[511:0]" +Toggle 1to0 tdata [250] "logic tdata[511:0]" +Toggle 0to1 tdata [251] "logic tdata[511:0]" +Toggle 1to0 tdata [251] "logic tdata[511:0]" +Toggle 0to1 tdata [252] "logic tdata[511:0]" +Toggle 1to0 tdata [252] "logic tdata[511:0]" +Toggle 0to1 tdata [253] "logic tdata[511:0]" +Toggle 1to0 tdata [253] "logic tdata[511:0]" +Toggle 0to1 tdata [254] "logic tdata[511:0]" +Toggle 1to0 tdata [254] "logic tdata[511:0]" +Toggle 0to1 rst_n "net rst_n" +Toggle 1to0 rst_n "net rst_n" +Toggle 0to1 tdata [31] "logic tdata[511:0]" +Toggle 1to0 tdata [31] "logic tdata[511:0]" +Toggle 0to1 tdata [2] "logic tdata[511:0]" +Toggle 1to0 tdata [2] "logic tdata[511:0]" +Toggle 0to1 tdata [3] "logic tdata[511:0]" +Toggle 1to0 tdata [3] "logic tdata[511:0]" +Toggle 0to1 tdata [4] "logic tdata[511:0]" +Toggle 1to0 tdata [4] "logic tdata[511:0]" +Toggle 0to1 tdata [5] "logic tdata[511:0]" +Toggle 1to0 tdata [5] "logic tdata[511:0]" +Toggle 0to1 tdata [6] "logic tdata[511:0]" +Toggle 1to0 tdata [6] "logic tdata[511:0]" +Toggle 0to1 tdata [7] "logic tdata[511:0]" +Toggle 1to0 tdata [7] "logic tdata[511:0]" +Toggle 0to1 tdata [8] "logic tdata[511:0]" +Toggle 1to0 tdata [8] "logic tdata[511:0]" +Toggle 0to1 tdata [9] "logic tdata[511:0]" +Toggle 1to0 tdata [9] "logic tdata[511:0]" +Toggle 0to1 tdata [10] "logic tdata[511:0]" +Toggle 1to0 tdata [10] "logic tdata[511:0]" +Toggle 0to1 tdata [11] "logic tdata[511:0]" +Toggle 1to0 tdata [11] "logic tdata[511:0]" +Toggle 0to1 tdata [12] "logic tdata[511:0]" +Toggle 1to0 tdata [12] "logic tdata[511:0]" +Toggle 0to1 tdata [13] "logic tdata[511:0]" +Toggle 1to0 tdata [13] "logic tdata[511:0]" +Toggle 0to1 tdata [14] "logic tdata[511:0]" +Toggle 1to0 tdata [14] "logic tdata[511:0]" +Toggle 0to1 tdata [15] "logic tdata[511:0]" +Toggle 1to0 tdata [15] "logic tdata[511:0]" +Toggle 0to1 tdata [20] "logic tdata[511:0]" +Toggle 1to0 tdata [20] "logic tdata[511:0]" +Toggle 0to1 tdata [21] "logic tdata[511:0]" +Toggle 1to0 tdata [21] "logic tdata[511:0]" +Toggle 0to1 tdata [22] "logic tdata[511:0]" +Toggle 1to0 tdata [22] "logic tdata[511:0]" +Toggle 0to1 tdata [23] "logic tdata[511:0]" +Toggle 1to0 tdata [23] "logic tdata[511:0]" +Toggle 0to1 tdata [24] "logic tdata[511:0]" +Toggle 1to0 tdata [24] "logic tdata[511:0]" +Toggle 0to1 tdata [26] "logic tdata[511:0]" +Toggle 1to0 tdata [26] "logic tdata[511:0]" +Toggle 0to1 tdata [28] "logic tdata[511:0]" +Toggle 1to0 tdata [28] "logic tdata[511:0]" +Toggle 0to1 tdata [29] "logic tdata[511:0]" +Toggle 1to0 tdata [29] "logic tdata[511:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.tx_port_control_if +Toggle tkeep "logic tkeep[63:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 clk "net clk" +Toggle 1to0 clk "net clk" +Toggle 0to1 rst_n "net rst_n" +Toggle 1to0 rst_n "net rst_n" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.port_traffic_control_inst.tx_fifo_st +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.port_traffic_control_inst.tx_st +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +CHECKSUM: "2414341016 2380279834" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst +Condition 12 "3277062238" "(rst_n && h2a_axis_rx.tvalid && h2a_axis_rx.tready) 1 -1" (1 "011") +Condition 10 "982667336" "(rst_n && afu_axis_tx.tvalid && afu_axis_tx.tready) 1 -1" (1 "011") +Condition 11 "3264047442" "(rst_n && a2h_axis_tx.tvalid && a2h_axis_tx.tready) 1 -1" (1 "011") +Condition 13 "325912493" "(rst_n && afu_axis_rx.tvalid && afu_axis_rx.tready) 1 -1" (1 "011") +CHECKSUM: "2346030483 211527496" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst +Condition 40 "83544224" "((tx_length_T1 == 24'h000004) && (tx_cpld_bytecount_T1 == 12'b0)) 1 -1" (1 "01") +Condition 41 "3938893723" "((tx_length_T1 == 24'h000008) && (tx_cpld_bytecount_T1 <= 12'h004)) 1 -1" (3 "11") +Condition 43 "324430506" "((tx_length_T1 == 24'h000008) && (tx_cpld_bytecount_T1 > 12'h008)) 1 -1" (3 "11") +Condition 43 "324430506" "((tx_length_T1 == 24'h000008) && (tx_cpld_bytecount_T1 > 12'h008)) 1 -1" (1 "01") +Condition 24 "802366991" "((tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_CAS32)) ? 1'b1 : 1'b0) 1 -1" (2 "1") +Condition 25 "3770603476" "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_CAS32)) 1 -1" (3 "11") +Condition 26 "523612213" "((tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_CAS64)) ? 1'b1 : 1'b0) 1 -1" (2 "1") +Condition 27 "3983207327" "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_CAS64)) 1 -1" (3 "11") +Condition 10 "659788244" "((tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_CFG_WRITE)) ? 1'b1 : 1'b0) 1 -1" (2 "1") +Condition 11 "71005812" "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_CFG_WRITE)) 1 -1" (3 "11") +Condition 12 "3722529362" "((tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_CPL)) ? 1'b1 : 1'b0) 1 -1" (2 "1") +Condition 13 "1260227863" "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_CPL)) 1 -1" (3 "11") +Condition 16 "224650897" "((tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_FETCH_ADD32)) ? 1'b1 : 1'b0) 1 -1" (2 "1") +Condition 17 "114730578" "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_FETCH_ADD32)) 1 -1" (3 "11") +Condition 18 "1322449423" "((tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_FETCH_ADD64)) ? 1'b1 : 1'b0) 1 -1" (2 "1") +Condition 19 "2200721474" "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_FETCH_ADD64)) 1 -1" (3 "11") +Condition 21 "3036937861" "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_SWAP32)) 1 -1" (3 "11") +Condition 20 "1650994927" "((tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_SWAP32)) ? 1'b1 : 1'b0) 1 -1" (2 "1") +Condition 23 "3039076197" "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_SWAP64)) 1 -1" (3 "11") +Condition 22 "3253076993" "((tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_SWAP64)) ? 1'b1 : 1'b0) 1 -1" (2 "1") +Condition 45 "423416356" "(i_afu_softreset && rx_valid_sop_T1 && rx_mrd_T1) 1 -1" +Condition 46 "3302273339" "(i_afu_softreset && rx_valid_sop_T1 && rx_mwr_T1) 1 -1" +Condition 1 "1016843462" "(i_rx_valid && i_rx_sop && i_rx_ready) 1 -1" (3 "110") +Condition 1 "1016843462" "(i_rx_valid && i_rx_sop && i_rx_ready) 1 -1" (1 "011") +CHECKSUM: "3208458026 2534818043" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.genblk1.tx_filter_inst +Condition 6 "3890213174" "(i_mmio_timeout_err ? i_mmio_timeout_info : timeout_info) 1 -1" +Condition 4 "3407088952" "(mmio_rsp_tready && tx_mmio_st.tvalid) 1 -1" (1 "01") +CHECKSUM: "1713082210 4279624649" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.mc_csr_slave +Condition 21 "2276905993" "(((csr_arburst_err | csr_arlen_err)) || (((~csr_arburst_err)) && csr_araddr_err)) 1 -1" (2 "01") +Condition 21 "2276905993" "(((csr_arburst_err | csr_arlen_err)) || (((~csr_arburst_err)) && csr_araddr_err)) 1 -1" (3 "10") +Condition 8 "2835308056" "(((|csr_if.awaddr[1:0])) || (csr_if.awsize[0] && csr_if.awaddr[2])) 1 -1" (2 "01") +Condition 8 "2835308056" "(((|csr_if.awaddr[1:0])) || (csr_if.awsize[0] && csr_if.awaddr[2])) 1 -1" (3 "10") +Condition 14 "3203782688" "(((|csr_if.arburst)) || ((~((csr_if.arsize == 3'b010) || (csr_if.arsize == 3'b011))))) 1 -1" (2 "01") +Condition 14 "3203782688" "(((|csr_if.arburst)) || ((~((csr_if.arsize == 3'b010) || (csr_if.arsize == 3'b011))))) 1 -1" (3 "10") +Condition 15 "2222075962" "(((|csr_if.araddr[1:0])) || (csr_if.arsize[0] && csr_if.araddr[2])) 1 -1" (2 "01") +Condition 15 "2222075962" "(((|csr_if.araddr[1:0])) || (csr_if.arsize[0] && csr_if.araddr[2])) 1 -1" (3 "10") +Condition 17 "4067926759" "(((csr_awburst_err | csr_awlen_err)) || (((~csr_awburst_err)) && csr_awaddr_err)) 1 -1" (2 "01") +Condition 17 "4067926759" "(((csr_awburst_err | csr_awlen_err)) || (((~csr_awburst_err)) && csr_awaddr_err)) 1 -1" (3 "10") +Condition 7 "1147368833" "(((|csr_if.awburst)) || ((~((csr_if.awsize == 3'b010) || (csr_if.awsize == 3'b011))))) 1 -1" (2 "01") +Condition 7 "1147368833" "(((|csr_if.awburst)) || ((~((csr_if.awsize == 3'b010) || (csr_if.awsize == 3'b011))))) 1 -1" (3 "10") +Condition 11 "362226083" "(((|csr_if.wstrb[3:0])) || ((~&csr_if.wstrb[7:4]))) 1 -1" (2 "01") +Condition 11 "362226083" "(((|csr_if.wstrb[3:0])) || ((~&csr_if.wstrb[7:4]))) 1 -1" (3 "10") +Condition 10 "1583158705" "(((|csr_if.wstrb[7:4])) || ((~&csr_if.wstrb[3:0]))) 1 -1" (2 "01") +Condition 10 "1583158705" "(((|csr_if.wstrb[7:4])) || ((~&csr_if.wstrb[3:0]))) 1 -1" (3 "10") +Condition 4 "3546147543" "(csr_slv_wready ? WR_RESP_STATE : WR_CSR_STATE) 1 -1" +Condition 2 "3836483245" "(csr_if.wvalid && csr_if.wready) 1 -1" (1 "01") +Condition 2 "3836483245" "(csr_if.wvalid && csr_if.wready) 1 -1" (2 "10") +Condition 13 "2963235801" "(csr_if.rvalid && csr_if.rready) 1 -1" (1 "01") +Condition 3 "330535913" "(csr_aw_legal && ((~csr_wstrb_err)) && csr_wlast) 1 -1" +Condition 12 "3748757535" "(csr_if.arvalid && csr_if.arready) 1 -1" (2 "10") +Condition 1 "117926484" "(csr_if.awvalid && csr_if.awready) 1 -1" (2 "10") +Condition 6 "2521810998" "(csr_if.bvalid && csr_if.bready) 1 -1" (1 "01") +Condition 5 "964632512" "(csr_aw_legal && ((~csr_wstrb_err)) && csr_wlast) 1 -1" (1 "011") +Condition 5 "964632512" "(csr_aw_legal && ((~csr_wstrb_err)) && csr_wlast) 1 -1" (3 "110") +Condition 5 "964632512" "(csr_aw_legal && ((~csr_wstrb_err)) && csr_wlast) 1 -1" (2 "101") +Condition 9 "1463641219" "(csr_if.awsize[0] && csr_if.awaddr[2]) 1 -1" (3 "11") +Condition 9 "1463641219" "(csr_if.awsize[0] && csr_if.awaddr[2]) 1 -1" (1 "01") +Condition 16 "736754236" "(csr_if.arsize[0] && csr_if.araddr[2]) 1 -1" (3 "11") +Condition 16 "736754236" "(csr_if.arsize[0] && csr_if.araddr[2]) 1 -1" (1 "01") +Condition 18 "3511878966" "(((~csr_awburst_err)) && csr_awaddr_err) 1 -1" (1 "01") +Condition 18 "3511878966" "(((~csr_awburst_err)) && csr_awaddr_err) 1 -1" (3 "11") +Condition 22 "1552010784" "(((~csr_arburst_err)) && csr_araddr_err) 1 -1" (3 "11") +Condition 22 "1552010784" "(((~csr_arburst_err)) && csr_araddr_err) 1 -1" (1 "01") +Condition 11 "362226083" "(((|csr_if.wstrb[3:0])) || ((~&csr_if.wstrb[7:4]))) 1 -1" (1 "00") +Condition 21 "2276905993" "(((csr_arburst_err | csr_arlen_err)) || (((~csr_arburst_err)) && csr_araddr_err)) 1 -1" (1 "00") +Condition 10 "1583158705" "(((|csr_if.wstrb[7:4])) || ((~&csr_if.wstrb[3:0]))) 1 -1" (1 "00") +Condition 20 "4064289544" "(csr_if.awaddr[2] ? UPPER32 : LOWER32) 1 -1" (2 "1") +CHECKSUM: "1713082210 3287333166" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.mc_csr_slave +Branch 3 "3657547784" "1'b1" (3) "1'b1 wr_state[WR_DATA_BIT] ,-,0,-,-,-" +Branch 11 "2957300531" "(~csr_read_legal)" (0) "(~csr_read_legal) 1" +CHECKSUM: "1713082210 4237878642" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.mc_csr_slave +Toggle 0to1 csr_araddr_err "logic csr_araddr_err" +Toggle 1to0 csr_araddr_err "logic csr_araddr_err" +Toggle 0to1 csr_wstrb_err "logic csr_wstrb_err" +Toggle 1to0 csr_wstrb_err "logic csr_wstrb_err" +Toggle 0to1 csr_rerr_comb "logic csr_rerr_comb" +Toggle 1to0 csr_rerr_comb "logic csr_rerr_comb" +Toggle 0to1 csr_awlen_err "logic csr_awlen_err" +Toggle 1to0 csr_awlen_err "logic csr_awlen_err" +Toggle csr_awid "logic csr_awid[5:0]" +Toggle 0to1 csr_awerr_comb "logic csr_awerr_comb" +Toggle 1to0 csr_awerr_comb "logic csr_awerr_comb" +Toggle 0to1 csr_awburst_err "logic csr_awburst_err" +Toggle 1to0 csr_awburst_err "logic csr_awburst_err" +Toggle 0to1 csr_awaddr_err "logic csr_awaddr_err" +Toggle 1to0 csr_awaddr_err "logic csr_awaddr_err" +Toggle 0to1 csr_arlen_err "logic csr_arlen_err" +Toggle 1to0 csr_arlen_err "logic csr_arlen_err" +Toggle csr_arid "logic csr_arid[5:0]" +Toggle 0to1 csr_arburst_err "logic csr_arburst_err" +Toggle 1to0 csr_arburst_err "logic csr_arburst_err" +Toggle 0to1 csr_aw_legal "logic csr_aw_legal" +Toggle 1to0 csr_aw_legal "logic csr_aw_legal" +Toggle 0to1 csr_read_legal "logic csr_read_legal" +Toggle 1to0 csr_read_legal "logic csr_read_legal" +Toggle csr_bresp "logic csr_bresp[1:0]" +Toggle csr_rresp "logic csr_rresp[1:0]" +Toggle 0to1 csr_raddr [19] "logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [19] "logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [0] "logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [0] "logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [1] "logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [1] "logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [6] "logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [6] "logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [7] "logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [7] "logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [8] "logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [8] "logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [9] "logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [9] "logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [10] "logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [10] "logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [11] "logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [11] "logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [12] "logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [12] "logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [13] "logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [13] "logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [14] "logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [14] "logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [15] "logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [15] "logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [16] "logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [16] "logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [17] "logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [17] "logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [18] "logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [18] "logic csr_raddr[19:0]" +Toggle 0to1 csr_waddr [19] "logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [19] "logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [0] "logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [0] "logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [1] "logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [1] "logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [6] "logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [6] "logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [7] "logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [7] "logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [8] "logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [8] "logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [9] "logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [9] "logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [10] "logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [10] "logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [11] "logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [11] "logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [12] "logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [12] "logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [13] "logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [13] "logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [14] "logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [14] "logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [15] "logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [15] "logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [16] "logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [16] "logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [17] "logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [17] "logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [18] "logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [18] "logic csr_waddr[19:0]" +Toggle 0to1 csr_wlast "logic csr_wlast" +Toggle 1to0 csr_wlast "logic csr_wlast" +Toggle 0to1 csr_wstrb [7] "logic csr_wstrb[7:0]" +Toggle 1to0 csr_wstrb [7] "logic csr_wstrb[7:0]" +Toggle 0to1 csr_wstrb [0] "logic csr_wstrb[7:0]" +Toggle 1to0 csr_wstrb [0] "logic csr_wstrb[7:0]" +Toggle 0to1 csr_wstrb [1] "logic csr_wstrb[7:0]" +Toggle 1to0 csr_wstrb [1] "logic csr_wstrb[7:0]" +Toggle 0to1 csr_wstrb [2] "logic csr_wstrb[7:0]" +Toggle 1to0 csr_wstrb [2] "logic csr_wstrb[7:0]" +Toggle 0to1 csr_wstrb [3] "logic csr_wstrb[7:0]" +Toggle 1to0 csr_wstrb [3] "logic csr_wstrb[7:0]" +Toggle 0to1 csr_wstrb [4] "logic csr_wstrb[7:0]" +Toggle 1to0 csr_wstrb [4] "logic csr_wstrb[7:0]" +Toggle 0to1 csr_wstrb [5] "logic csr_wstrb[7:0]" +Toggle 1to0 csr_wstrb [5] "logic csr_wstrb[7:0]" +Toggle 0to1 csr_wstrb [6] "logic csr_wstrb[7:0]" +Toggle 1to0 csr_wstrb [6] "logic csr_wstrb[7:0]" +Toggle 0to1 csr_slv_wready "logic csr_slv_wready" +Toggle 1to0 csr_slv_wready "logic csr_slv_wready" +Toggle 1to0 rst_n "logic rst_n" +CHECKSUM: "2621707631 1903240413" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.genblk1.mmio_handler_inst +Toggle 1to0 curr_idx_mmio_timeout_info_r0.addr [20] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.addr [20] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [62] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [62] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [61] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [61] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [60] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [60] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [59] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [59] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [58] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [58] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [57] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [57] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [56] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [56] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [55] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [55] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [54] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [54] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [53] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [53] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [52] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [52] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [51] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [51] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [50] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [50] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [49] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [49] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [48] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [48] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [47] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [47] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [46] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [46] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [45] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [45] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [44] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [44] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [43] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [43] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [42] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [42] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [41] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [41] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [40] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [40] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [39] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [39] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [38] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [38] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [37] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [37] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [36] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [36] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [35] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [35] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [34] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [34] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [33] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [33] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [32] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [32] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_unexp_rsp [63] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 0to1 pending_rd_req_tags_unexp_rsp [63] "logic pending_rd_req_tags_unexp_rsp[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [62] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [62] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [61] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [61] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [60] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [60] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [59] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [59] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [58] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [58] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [57] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [57] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [56] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [56] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [55] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [55] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [54] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [54] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [53] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [53] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [52] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [52] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [51] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [51] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [50] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [50] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [49] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [49] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [48] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [48] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [47] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [47] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [46] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [46] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [45] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [45] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [44] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [44] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [43] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [43] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [42] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [42] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [41] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [41] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [40] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [40] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [39] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [39] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [38] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [38] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [37] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [37] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [36] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [36] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [35] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [35] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [34] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [34] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [33] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [33] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [32] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [32] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 pending_rd_req_tags_timeout [63] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 0to1 pending_rd_req_tags_timeout [63] "logic pending_rd_req_tags_timeout[63:0]" +Toggle 1to0 o_mmio_timeout_info.tag [6] "logic o_mmio_timeout_info.tag[7:0]" +Toggle 0to1 o_mmio_timeout_info.tag [6] "logic o_mmio_timeout_info.tag[7:0]" +Toggle 1to0 o_mmio_timeout_info.tag [5] "logic o_mmio_timeout_info.tag[7:0]" +Toggle 0to1 o_mmio_timeout_info.tag [5] "logic o_mmio_timeout_info.tag[7:0]" +Toggle 1to0 o_mmio_timeout_info.tag [7] "logic o_mmio_timeout_info.tag[7:0]" +Toggle 0to1 o_mmio_timeout_info.tag [7] "logic o_mmio_timeout_info.tag[7:0]" +Toggle 1to0 o_mmio_timeout_info.requester_id [14] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 o_mmio_timeout_info.requester_id [14] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 o_mmio_timeout_info.requester_id [13] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 o_mmio_timeout_info.requester_id [13] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 o_mmio_timeout_info.requester_id [12] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 o_mmio_timeout_info.requester_id [12] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 o_mmio_timeout_info.requester_id [11] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 o_mmio_timeout_info.requester_id [11] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 o_mmio_timeout_info.requester_id [10] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 o_mmio_timeout_info.requester_id [10] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 o_mmio_timeout_info.requester_id [9] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 o_mmio_timeout_info.requester_id [9] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 o_mmio_timeout_info.requester_id [8] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 o_mmio_timeout_info.requester_id [8] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 o_mmio_timeout_info.requester_id [7] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 o_mmio_timeout_info.requester_id [7] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 o_mmio_timeout_info.requester_id [6] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 o_mmio_timeout_info.requester_id [6] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 o_mmio_timeout_info.requester_id [5] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 o_mmio_timeout_info.requester_id [5] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 o_mmio_timeout_info.requester_id [4] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 o_mmio_timeout_info.requester_id [4] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 o_mmio_timeout_info.requester_id [3] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 o_mmio_timeout_info.requester_id [3] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 o_mmio_timeout_info.requester_id [2] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 o_mmio_timeout_info.requester_id [2] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 o_mmio_timeout_info.requester_id [1] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 o_mmio_timeout_info.requester_id [1] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 o_mmio_timeout_info.requester_id [15] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 o_mmio_timeout_info.requester_id [15] "logic o_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 o_mmio_timeout_info.addr [28] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 0to1 o_mmio_timeout_info.addr [28] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 1to0 o_mmio_timeout_info.addr [31] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 0to1 o_mmio_timeout_info.addr [31] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 1to0 o_mmio_timeout_info.addr [29] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 0to1 o_mmio_timeout_info.addr [29] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 1to0 o_mmio_timeout_info.addr [27] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 0to1 o_mmio_timeout_info.addr [27] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 1to0 o_mmio_timeout_info.addr [26] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 0to1 o_mmio_timeout_info.addr [26] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 1to0 o_mmio_timeout_info.addr [25] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 0to1 o_mmio_timeout_info.addr [25] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 1to0 o_mmio_timeout_info.addr [23] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 0to1 o_mmio_timeout_info.addr [23] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 1to0 o_mmio_timeout_info.addr [24] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 0to1 o_mmio_timeout_info.addr [24] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 1to0 o_mmio_timeout_info.addr [22] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 0to1 o_mmio_timeout_info.addr [22] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 1to0 o_mmio_timeout_info.addr [21] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 0to1 o_mmio_timeout_info.addr [21] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 1to0 o_mmio_timeout_info.addr [20] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 0to1 o_mmio_timeout_info.addr [20] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 1to0 o_mmio_timeout_info.addr [18] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 0to1 o_mmio_timeout_info.addr [18] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 1to0 o_mmio_timeout_info.addr [13] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 0to1 o_mmio_timeout_info.addr [13] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 1to0 o_mmio_timeout_info.addr [14] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 0to1 o_mmio_timeout_info.addr [14] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 1to0 o_mmio_timeout_info.addr [12] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 0to1 o_mmio_timeout_info.addr [12] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 1to0 o_mmio_timeout_info.addr [9] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 0to1 o_mmio_timeout_info.addr [9] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 1to0 o_mmio_timeout_info.addr [8] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 0to1 o_mmio_timeout_info.addr [8] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 1to0 o_mmio_timeout_info.addr [7] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 0to1 o_mmio_timeout_info.addr [7] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 1to0 o_mmio_timeout_info.addr [6] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 0to1 o_mmio_timeout_info.addr [6] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 1to0 o_mmio_timeout_info.addr [0] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 0to1 o_mmio_timeout_info.addr [0] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 1to0 o_mmio_timeout_info.addr [30] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 0to1 o_mmio_timeout_info.addr [30] "logic o_mmio_timeout_info.addr[31:0]" +Toggle 1to0 mmio_timeout_info.tag [6] "logic mmio_timeout_info.tag[7:0]" +Toggle 0to1 mmio_timeout_info.tag [6] "logic mmio_timeout_info.tag[7:0]" +Toggle 1to0 mmio_timeout_info.tag [5] "logic mmio_timeout_info.tag[7:0]" +Toggle 0to1 mmio_timeout_info.tag [5] "logic mmio_timeout_info.tag[7:0]" +Toggle 1to0 mmio_timeout_info.tag [7] "logic mmio_timeout_info.tag[7:0]" +Toggle 0to1 mmio_timeout_info.tag [7] "logic mmio_timeout_info.tag[7:0]" +Toggle 1to0 mmio_timeout_info.requester_id [14] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 mmio_timeout_info.requester_id [14] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 mmio_timeout_info.requester_id [13] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 mmio_timeout_info.requester_id [13] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 mmio_timeout_info.requester_id [12] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 mmio_timeout_info.requester_id [12] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 mmio_timeout_info.requester_id [11] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 mmio_timeout_info.requester_id [11] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 mmio_timeout_info.requester_id [10] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 mmio_timeout_info.requester_id [10] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 mmio_timeout_info.requester_id [9] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 mmio_timeout_info.requester_id [9] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 mmio_timeout_info.requester_id [8] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 mmio_timeout_info.requester_id [8] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 mmio_timeout_info.requester_id [7] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 mmio_timeout_info.requester_id [7] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 mmio_timeout_info.requester_id [6] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 mmio_timeout_info.requester_id [6] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 mmio_timeout_info.requester_id [5] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 mmio_timeout_info.requester_id [5] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 mmio_timeout_info.requester_id [4] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 mmio_timeout_info.requester_id [4] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 mmio_timeout_info.requester_id [3] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 mmio_timeout_info.requester_id [3] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 mmio_timeout_info.requester_id [2] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 mmio_timeout_info.requester_id [2] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 mmio_timeout_info.requester_id [1] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 mmio_timeout_info.requester_id [1] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 mmio_timeout_info.requester_id [15] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 mmio_timeout_info.requester_id [15] "logic mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 mmio_timeout_info.addr [31] "logic mmio_timeout_info.addr[31:0]" +Toggle 0to1 mmio_timeout_info.addr [31] "logic mmio_timeout_info.addr[31:0]" +Toggle 1to0 mmio_timeout_info.addr [27] "logic mmio_timeout_info.addr[31:0]" +Toggle 0to1 mmio_timeout_info.addr [27] "logic mmio_timeout_info.addr[31:0]" +Toggle 1to0 mmio_timeout_info.addr [29] "logic mmio_timeout_info.addr[31:0]" +Toggle 0to1 mmio_timeout_info.addr [29] "logic mmio_timeout_info.addr[31:0]" +Toggle 1to0 mmio_timeout_info.addr [28] "logic mmio_timeout_info.addr[31:0]" +Toggle 0to1 mmio_timeout_info.addr [28] "logic mmio_timeout_info.addr[31:0]" +Toggle 1to0 mmio_timeout_info.addr [26] "logic mmio_timeout_info.addr[31:0]" +Toggle 0to1 mmio_timeout_info.addr [26] "logic mmio_timeout_info.addr[31:0]" +Toggle 1to0 mmio_timeout_info.addr [25] "logic mmio_timeout_info.addr[31:0]" +Toggle 0to1 mmio_timeout_info.addr [25] "logic mmio_timeout_info.addr[31:0]" +Toggle 1to0 mmio_timeout_info.addr [24] "logic mmio_timeout_info.addr[31:0]" +Toggle 0to1 mmio_timeout_info.addr [24] "logic mmio_timeout_info.addr[31:0]" +Toggle 1to0 mmio_timeout_info.addr [23] "logic mmio_timeout_info.addr[31:0]" +Toggle 0to1 mmio_timeout_info.addr [23] "logic mmio_timeout_info.addr[31:0]" +Toggle 1to0 mmio_timeout_info.addr [22] "logic mmio_timeout_info.addr[31:0]" +Toggle 0to1 mmio_timeout_info.addr [22] "logic mmio_timeout_info.addr[31:0]" +Toggle 1to0 mmio_timeout_info.addr [21] "logic mmio_timeout_info.addr[31:0]" +Toggle 0to1 mmio_timeout_info.addr [21] "logic mmio_timeout_info.addr[31:0]" +Toggle 1to0 mmio_timeout_info.addr [20] "logic mmio_timeout_info.addr[31:0]" +Toggle 0to1 mmio_timeout_info.addr [20] "logic mmio_timeout_info.addr[31:0]" +Toggle 1to0 mmio_timeout_info.addr [18] "logic mmio_timeout_info.addr[31:0]" +Toggle 0to1 mmio_timeout_info.addr [18] "logic mmio_timeout_info.addr[31:0]" +Toggle 1to0 mmio_timeout_info.addr [14] "logic mmio_timeout_info.addr[31:0]" +Toggle 0to1 mmio_timeout_info.addr [14] "logic mmio_timeout_info.addr[31:0]" +Toggle 1to0 mmio_timeout_info.addr [13] "logic mmio_timeout_info.addr[31:0]" +Toggle 0to1 mmio_timeout_info.addr [13] "logic mmio_timeout_info.addr[31:0]" +Toggle 1to0 mmio_timeout_info.addr [12] "logic mmio_timeout_info.addr[31:0]" +Toggle 0to1 mmio_timeout_info.addr [12] "logic mmio_timeout_info.addr[31:0]" +Toggle 1to0 mmio_timeout_info.addr [9] "logic mmio_timeout_info.addr[31:0]" +Toggle 0to1 mmio_timeout_info.addr [9] "logic mmio_timeout_info.addr[31:0]" +Toggle 1to0 mmio_timeout_info.addr [8] "logic mmio_timeout_info.addr[31:0]" +Toggle 0to1 mmio_timeout_info.addr [8] "logic mmio_timeout_info.addr[31:0]" +Toggle 1to0 mmio_timeout_info.addr [7] "logic mmio_timeout_info.addr[31:0]" +Toggle 0to1 mmio_timeout_info.addr [7] "logic mmio_timeout_info.addr[31:0]" +Toggle 1to0 mmio_timeout_info.addr [6] "logic mmio_timeout_info.addr[31:0]" +Toggle 0to1 mmio_timeout_info.addr [6] "logic mmio_timeout_info.addr[31:0]" +Toggle 1to0 mmio_timeout_info.addr [0] "logic mmio_timeout_info.addr[31:0]" +Toggle 0to1 mmio_timeout_info.addr [0] "logic mmio_timeout_info.addr[31:0]" +Toggle 1to0 mmio_timeout_info.addr [30] "logic mmio_timeout_info.addr[31:0]" +Toggle 0to1 mmio_timeout_info.addr [30] "logic mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_tx_filter_rsp_tag [6] "logic i_tx_filter_rsp_tag[7:0]" +Toggle 0to1 i_tx_filter_rsp_tag [6] "logic i_tx_filter_rsp_tag[7:0]" +Toggle 1to0 i_tx_filter_rsp_tag [5] "logic i_tx_filter_rsp_tag[7:0]" +Toggle 0to1 i_tx_filter_rsp_tag [5] "logic i_tx_filter_rsp_tag[7:0]" +Toggle 1to0 i_tx_filter_rsp_tag [7] "logic i_tx_filter_rsp_tag[7:0]" +Toggle 0to1 i_tx_filter_rsp_tag [7] "logic i_tx_filter_rsp_tag[7:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.tag [6] "logic curr_idx_mmio_timeout_info_r3.tag[7:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.tag [6] "logic curr_idx_mmio_timeout_info_r3.tag[7:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.tag [5] "logic curr_idx_mmio_timeout_info_r3.tag[7:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.tag [5] "logic curr_idx_mmio_timeout_info_r3.tag[7:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.tag [7] "logic curr_idx_mmio_timeout_info_r3.tag[7:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.tag [7] "logic curr_idx_mmio_timeout_info_r3.tag[7:0]" +Toggle curr_idx_mmio_timeout_info_r3.requester_id "logic curr_idx_mmio_timeout_info_r3.requester_id[15:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.addr [28] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.addr [28] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.addr [31] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.addr [31] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.addr [29] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.addr [29] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.addr [27] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.addr [27] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.addr [26] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.addr [26] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.addr [25] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.addr [25] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.addr [24] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.addr [24] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.addr [23] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.addr [23] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.addr [22] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.addr [22] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.addr [20] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.addr [20] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.addr [21] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.addr [21] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.addr [13] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.addr [13] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.addr [30] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.addr [30] "logic curr_idx_mmio_timeout_info_r3.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.tag [6] "logic curr_idx_mmio_timeout_info_r2.tag[7:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.tag [6] "logic curr_idx_mmio_timeout_info_r2.tag[7:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.tag [5] "logic curr_idx_mmio_timeout_info_r2.tag[7:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.tag [5] "logic curr_idx_mmio_timeout_info_r2.tag[7:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.tag [7] "logic curr_idx_mmio_timeout_info_r2.tag[7:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.tag [7] "logic curr_idx_mmio_timeout_info_r2.tag[7:0]" +Toggle curr_idx_mmio_timeout_info_r2.requester_id "logic curr_idx_mmio_timeout_info_r2.requester_id[15:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.addr [30] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.addr [30] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.addr [29] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.addr [29] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.addr [25] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.addr [25] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.addr [28] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.addr [28] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.addr [27] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.addr [27] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.addr [26] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.addr [26] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.addr [24] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.addr [24] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.addr [23] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.addr [23] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.addr [22] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.addr [22] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.addr [20] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.addr [20] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.addr [21] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.addr [21] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.addr [13] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.addr [13] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.addr [31] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.addr [31] "logic curr_idx_mmio_timeout_info_r2.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.tag [6] "logic curr_idx_mmio_timeout_info_r1.tag[7:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.tag [6] "logic curr_idx_mmio_timeout_info_r1.tag[7:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.tag [5] "logic curr_idx_mmio_timeout_info_r1.tag[7:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.tag [5] "logic curr_idx_mmio_timeout_info_r1.tag[7:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.tag [7] "logic curr_idx_mmio_timeout_info_r1.tag[7:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.tag [7] "logic curr_idx_mmio_timeout_info_r1.tag[7:0]" +Toggle curr_idx_mmio_timeout_info_r1.requester_id "logic curr_idx_mmio_timeout_info_r1.requester_id[15:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.addr [30] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.addr [30] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.addr [29] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.addr [29] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.addr [28] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.addr [28] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.addr [27] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.addr [27] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.addr [26] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.addr [26] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.addr [25] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.addr [25] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.addr [24] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.addr [24] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.addr [22] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.addr [22] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.addr [21] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.addr [21] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.addr [23] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.addr [23] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.addr [20] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.addr [20] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.addr [13] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.addr [13] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.addr [31] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.addr [31] "logic curr_idx_mmio_timeout_info_r1.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.addr [13] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.addr [13] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.addr [30] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.addr [30] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.addr [27] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.addr [27] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.addr [25] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.addr [25] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.addr [26] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.addr [26] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.addr [28] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.addr [28] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.addr [29] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.addr [29] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.addr [24] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.addr [24] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.addr [23] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.addr [23] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.addr [21] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.addr [21] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.addr [22] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.addr [22] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.addr [31] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.addr [31] "logic curr_idx_mmio_timeout_info_r0.addr[31:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [13] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [13] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [46] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [46] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [47] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [47] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [44] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [44] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [43] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [43] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [42] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [42] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [40] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [40] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [41] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [41] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [39] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [39] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [38] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [38] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [37] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [37] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [35] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [35] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [33] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [33] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [36] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [36] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [34] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [34] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [32] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [32] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [29] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [29] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [27] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [27] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [25] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [25] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [28] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [28] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [26] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [26] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [31] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [31] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [30] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [30] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [24] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [24] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [23] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [23] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [20] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [20] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [21] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [21] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [22] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [22] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [45] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [45] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.tag [6] "logic curr_idx_mmio_timeout_info_r0.tag[7:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.tag [6] "logic curr_idx_mmio_timeout_info_r0.tag[7:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.tag [5] "logic curr_idx_mmio_timeout_info_r0.tag[7:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.tag [5] "logic curr_idx_mmio_timeout_info_r0.tag[7:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.tag [7] "logic curr_idx_mmio_timeout_info_r0.tag[7:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.tag [7] "logic curr_idx_mmio_timeout_info_r0.tag[7:0]" +Toggle curr_idx_mmio_timeout_info_r0.requester_id "logic curr_idx_mmio_timeout_info_r0.requester_id[15:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [64] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [64] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [63] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [63] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [57] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [57] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [56] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [56] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [55] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [55] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [54] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [54] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [53] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [53] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [52] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [52] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [51] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [51] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [50] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [50] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 1to0 curr_idx_mmio_timeout_info [65] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle 0to1 curr_idx_mmio_timeout_info [65] "logic curr_idx_mmio_timeout_info[65:0]" +Toggle curr_idx_mmio_timeout_tag "logic curr_idx_mmio_timeout_tag[7:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.dw0_len [9] "logic curr_idx_mmio_timeout_info_r0.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.dw0_len [9] "logic curr_idx_mmio_timeout_info_r0.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.dw0_len [2] "logic curr_idx_mmio_timeout_info_r0.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.dw0_len [2] "logic curr_idx_mmio_timeout_info_r0.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.dw0_len [3] "logic curr_idx_mmio_timeout_info_r0.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.dw0_len [3] "logic curr_idx_mmio_timeout_info_r0.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.dw0_len [4] "logic curr_idx_mmio_timeout_info_r0.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.dw0_len [4] "logic curr_idx_mmio_timeout_info_r0.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.dw0_len [5] "logic curr_idx_mmio_timeout_info_r0.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.dw0_len [5] "logic curr_idx_mmio_timeout_info_r0.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.dw0_len [6] "logic curr_idx_mmio_timeout_info_r0.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.dw0_len [6] "logic curr_idx_mmio_timeout_info_r0.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.dw0_len [7] "logic curr_idx_mmio_timeout_info_r0.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.dw0_len [7] "logic curr_idx_mmio_timeout_info_r0.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r0.dw0_len [8] "logic curr_idx_mmio_timeout_info_r0.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r0.dw0_len [8] "logic curr_idx_mmio_timeout_info_r0.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.dw0_len [9] "logic curr_idx_mmio_timeout_info_r1.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.dw0_len [9] "logic curr_idx_mmio_timeout_info_r1.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.dw0_len [2] "logic curr_idx_mmio_timeout_info_r1.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.dw0_len [2] "logic curr_idx_mmio_timeout_info_r1.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.dw0_len [3] "logic curr_idx_mmio_timeout_info_r1.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.dw0_len [3] "logic curr_idx_mmio_timeout_info_r1.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.dw0_len [4] "logic curr_idx_mmio_timeout_info_r1.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.dw0_len [4] "logic curr_idx_mmio_timeout_info_r1.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.dw0_len [5] "logic curr_idx_mmio_timeout_info_r1.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.dw0_len [5] "logic curr_idx_mmio_timeout_info_r1.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.dw0_len [6] "logic curr_idx_mmio_timeout_info_r1.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.dw0_len [6] "logic curr_idx_mmio_timeout_info_r1.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.dw0_len [7] "logic curr_idx_mmio_timeout_info_r1.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.dw0_len [7] "logic curr_idx_mmio_timeout_info_r1.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r1.dw0_len [8] "logic curr_idx_mmio_timeout_info_r1.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r1.dw0_len [8] "logic curr_idx_mmio_timeout_info_r1.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.dw0_len [9] "logic curr_idx_mmio_timeout_info_r2.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.dw0_len [9] "logic curr_idx_mmio_timeout_info_r2.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.dw0_len [2] "logic curr_idx_mmio_timeout_info_r2.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.dw0_len [2] "logic curr_idx_mmio_timeout_info_r2.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.dw0_len [3] "logic curr_idx_mmio_timeout_info_r2.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.dw0_len [3] "logic curr_idx_mmio_timeout_info_r2.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.dw0_len [4] "logic curr_idx_mmio_timeout_info_r2.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.dw0_len [4] "logic curr_idx_mmio_timeout_info_r2.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.dw0_len [5] "logic curr_idx_mmio_timeout_info_r2.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.dw0_len [5] "logic curr_idx_mmio_timeout_info_r2.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.dw0_len [6] "logic curr_idx_mmio_timeout_info_r2.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.dw0_len [6] "logic curr_idx_mmio_timeout_info_r2.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.dw0_len [7] "logic curr_idx_mmio_timeout_info_r2.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.dw0_len [7] "logic curr_idx_mmio_timeout_info_r2.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r2.dw0_len [8] "logic curr_idx_mmio_timeout_info_r2.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r2.dw0_len [8] "logic curr_idx_mmio_timeout_info_r2.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.dw0_len [9] "logic curr_idx_mmio_timeout_info_r3.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.dw0_len [9] "logic curr_idx_mmio_timeout_info_r3.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.dw0_len [2] "logic curr_idx_mmio_timeout_info_r3.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.dw0_len [2] "logic curr_idx_mmio_timeout_info_r3.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.dw0_len [3] "logic curr_idx_mmio_timeout_info_r3.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.dw0_len [3] "logic curr_idx_mmio_timeout_info_r3.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.dw0_len [4] "logic curr_idx_mmio_timeout_info_r3.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.dw0_len [4] "logic curr_idx_mmio_timeout_info_r3.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.dw0_len [5] "logic curr_idx_mmio_timeout_info_r3.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.dw0_len [5] "logic curr_idx_mmio_timeout_info_r3.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.dw0_len [6] "logic curr_idx_mmio_timeout_info_r3.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.dw0_len [6] "logic curr_idx_mmio_timeout_info_r3.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.dw0_len [7] "logic curr_idx_mmio_timeout_info_r3.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.dw0_len [7] "logic curr_idx_mmio_timeout_info_r3.dw0_len[9:0]" +Toggle 0to1 curr_idx_mmio_timeout_info_r3.dw0_len [8] "logic curr_idx_mmio_timeout_info_r3.dw0_len[9:0]" +Toggle 1to0 curr_idx_mmio_timeout_info_r3.dw0_len [8] "logic curr_idx_mmio_timeout_info_r3.dw0_len[9:0]" +Toggle 0to1 curr_idx_time [31] "logic curr_idx_time[31:0]" +Toggle 1to0 curr_idx_time [31] "logic curr_idx_time[31:0]" +Toggle 0to1 curr_idx_time [19] "logic curr_idx_time[31:0]" +Toggle 1to0 curr_idx_time [19] "logic curr_idx_time[31:0]" +Toggle 0to1 curr_idx_time [20] "logic curr_idx_time[31:0]" +Toggle 1to0 curr_idx_time [20] "logic curr_idx_time[31:0]" +Toggle 0to1 curr_idx_time [21] "logic curr_idx_time[31:0]" +Toggle 1to0 curr_idx_time [21] "logic curr_idx_time[31:0]" +Toggle 0to1 curr_idx_time [22] "logic curr_idx_time[31:0]" +Toggle 1to0 curr_idx_time [22] "logic curr_idx_time[31:0]" +Toggle 0to1 curr_idx_time [23] "logic curr_idx_time[31:0]" +Toggle 1to0 curr_idx_time [23] "logic curr_idx_time[31:0]" +Toggle 0to1 curr_idx_time [24] "logic curr_idx_time[31:0]" +Toggle 1to0 curr_idx_time [24] "logic curr_idx_time[31:0]" +Toggle 0to1 curr_idx_time [25] "logic curr_idx_time[31:0]" +Toggle 1to0 curr_idx_time [25] "logic curr_idx_time[31:0]" +Toggle 0to1 curr_idx_time [26] "logic curr_idx_time[31:0]" +Toggle 1to0 curr_idx_time [26] "logic curr_idx_time[31:0]" +Toggle 0to1 curr_idx_time [27] "logic curr_idx_time[31:0]" +Toggle 1to0 curr_idx_time [27] "logic curr_idx_time[31:0]" +Toggle 0to1 curr_idx_time [28] "logic curr_idx_time[31:0]" +Toggle 1to0 curr_idx_time [28] "logic curr_idx_time[31:0]" +Toggle 0to1 curr_idx_time [29] "logic curr_idx_time[31:0]" +Toggle 1to0 curr_idx_time [29] "logic curr_idx_time[31:0]" +Toggle 0to1 curr_idx_time [30] "logic curr_idx_time[31:0]" +Toggle 1to0 curr_idx_time [30] "logic curr_idx_time[31:0]" +Toggle 0to1 curr_idx_time_r1 [31] "logic curr_idx_time_r1[31:0]" +Toggle 1to0 curr_idx_time_r1 [31] "logic curr_idx_time_r1[31:0]" +Toggle 0to1 curr_idx_time_r1 [19] "logic curr_idx_time_r1[31:0]" +Toggle 1to0 curr_idx_time_r1 [19] "logic curr_idx_time_r1[31:0]" +Toggle 0to1 curr_idx_time_r1 [20] "logic curr_idx_time_r1[31:0]" +Toggle 1to0 curr_idx_time_r1 [20] "logic curr_idx_time_r1[31:0]" +Toggle 0to1 curr_idx_time_r1 [21] "logic curr_idx_time_r1[31:0]" +Toggle 1to0 curr_idx_time_r1 [21] "logic curr_idx_time_r1[31:0]" +Toggle 0to1 curr_idx_time_r1 [22] "logic curr_idx_time_r1[31:0]" +Toggle 1to0 curr_idx_time_r1 [22] "logic curr_idx_time_r1[31:0]" +Toggle 0to1 curr_idx_time_r1 [23] "logic curr_idx_time_r1[31:0]" +Toggle 1to0 curr_idx_time_r1 [23] "logic curr_idx_time_r1[31:0]" +Toggle 0to1 curr_idx_time_r1 [24] "logic curr_idx_time_r1[31:0]" +Toggle 1to0 curr_idx_time_r1 [24] "logic curr_idx_time_r1[31:0]" +Toggle 0to1 curr_idx_time_r1 [25] "logic curr_idx_time_r1[31:0]" +Toggle 1to0 curr_idx_time_r1 [25] "logic curr_idx_time_r1[31:0]" +Toggle 0to1 curr_idx_time_r1 [26] "logic curr_idx_time_r1[31:0]" +Toggle 1to0 curr_idx_time_r1 [26] "logic curr_idx_time_r1[31:0]" +Toggle 0to1 curr_idx_time_r1 [27] "logic curr_idx_time_r1[31:0]" +Toggle 1to0 curr_idx_time_r1 [27] "logic curr_idx_time_r1[31:0]" +Toggle 0to1 curr_idx_time_r1 [28] "logic curr_idx_time_r1[31:0]" +Toggle 1to0 curr_idx_time_r1 [28] "logic curr_idx_time_r1[31:0]" +Toggle 0to1 curr_idx_time_r1 [29] "logic curr_idx_time_r1[31:0]" +Toggle 1to0 curr_idx_time_r1 [29] "logic curr_idx_time_r1[31:0]" +Toggle 0to1 curr_idx_time_r1 [30] "logic curr_idx_time_r1[31:0]" +Toggle 1to0 curr_idx_time_r1 [30] "logic curr_idx_time_r1[31:0]" +Toggle 0to1 mmio_timeout_info.dw0_len [9] "logic mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 mmio_timeout_info.dw0_len [9] "logic mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 mmio_timeout_info.dw0_len [2] "logic mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 mmio_timeout_info.dw0_len [2] "logic mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 mmio_timeout_info.dw0_len [3] "logic mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 mmio_timeout_info.dw0_len [3] "logic mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 mmio_timeout_info.dw0_len [4] "logic mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 mmio_timeout_info.dw0_len [4] "logic mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 mmio_timeout_info.dw0_len [5] "logic mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 mmio_timeout_info.dw0_len [5] "logic mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 mmio_timeout_info.dw0_len [6] "logic mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 mmio_timeout_info.dw0_len [6] "logic mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 mmio_timeout_info.dw0_len [7] "logic mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 mmio_timeout_info.dw0_len [7] "logic mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 mmio_timeout_info.dw0_len [8] "logic mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 mmio_timeout_info.dw0_len [8] "logic mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 o_mmio_timeout_info.dw0_len [9] "logic o_mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 o_mmio_timeout_info.dw0_len [9] "logic o_mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 o_mmio_timeout_info.dw0_len [2] "logic o_mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 o_mmio_timeout_info.dw0_len [2] "logic o_mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 o_mmio_timeout_info.dw0_len [3] "logic o_mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 o_mmio_timeout_info.dw0_len [3] "logic o_mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 o_mmio_timeout_info.dw0_len [4] "logic o_mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 o_mmio_timeout_info.dw0_len [4] "logic o_mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 o_mmio_timeout_info.dw0_len [5] "logic o_mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 o_mmio_timeout_info.dw0_len [5] "logic o_mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 o_mmio_timeout_info.dw0_len [6] "logic o_mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 o_mmio_timeout_info.dw0_len [6] "logic o_mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 o_mmio_timeout_info.dw0_len [7] "logic o_mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 o_mmio_timeout_info.dw0_len [7] "logic o_mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 o_mmio_timeout_info.dw0_len [8] "logic o_mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 o_mmio_timeout_info.dw0_len [8] "logic o_mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 timestamp_cntr [31] "logic timestamp_cntr[31:0]" +Toggle 1to0 timestamp_cntr [31] "logic timestamp_cntr[31:0]" +Toggle 0to1 timestamp_cntr [19] "logic timestamp_cntr[31:0]" +Toggle 1to0 timestamp_cntr [19] "logic timestamp_cntr[31:0]" +Toggle 0to1 timestamp_cntr [20] "logic timestamp_cntr[31:0]" +Toggle 1to0 timestamp_cntr [20] "logic timestamp_cntr[31:0]" +Toggle 0to1 timestamp_cntr [21] "logic timestamp_cntr[31:0]" +Toggle 1to0 timestamp_cntr [21] "logic timestamp_cntr[31:0]" +Toggle 0to1 timestamp_cntr [22] "logic timestamp_cntr[31:0]" +Toggle 1to0 timestamp_cntr [22] "logic timestamp_cntr[31:0]" +Toggle 0to1 timestamp_cntr [23] "logic timestamp_cntr[31:0]" +Toggle 1to0 timestamp_cntr [23] "logic timestamp_cntr[31:0]" +Toggle 0to1 timestamp_cntr [24] "logic timestamp_cntr[31:0]" +Toggle 1to0 timestamp_cntr [24] "logic timestamp_cntr[31:0]" +Toggle 0to1 timestamp_cntr [25] "logic timestamp_cntr[31:0]" +Toggle 1to0 timestamp_cntr [25] "logic timestamp_cntr[31:0]" +Toggle 0to1 timestamp_cntr [26] "logic timestamp_cntr[31:0]" +Toggle 1to0 timestamp_cntr [26] "logic timestamp_cntr[31:0]" +Toggle 0to1 timestamp_cntr [27] "logic timestamp_cntr[31:0]" +Toggle 1to0 timestamp_cntr [27] "logic timestamp_cntr[31:0]" +Toggle 0to1 timestamp_cntr [28] "logic timestamp_cntr[31:0]" +Toggle 1to0 timestamp_cntr [28] "logic timestamp_cntr[31:0]" +Toggle 0to1 timestamp_cntr [29] "logic timestamp_cntr[31:0]" +Toggle 1to0 timestamp_cntr [29] "logic timestamp_cntr[31:0]" +Toggle 0to1 timestamp_cntr [30] "logic timestamp_cntr[31:0]" +Toggle 1to0 timestamp_cntr [30] "logic timestamp_cntr[31:0]" +Toggle 0to1 timestamp_cntr_r1 [31] "logic timestamp_cntr_r1[31:0]" +Toggle 1to0 timestamp_cntr_r1 [31] "logic timestamp_cntr_r1[31:0]" +Toggle 0to1 timestamp_cntr_r1 [19] "logic timestamp_cntr_r1[31:0]" +Toggle 1to0 timestamp_cntr_r1 [19] "logic timestamp_cntr_r1[31:0]" +Toggle 0to1 timestamp_cntr_r1 [20] "logic timestamp_cntr_r1[31:0]" +Toggle 1to0 timestamp_cntr_r1 [20] "logic timestamp_cntr_r1[31:0]" +Toggle 0to1 timestamp_cntr_r1 [21] "logic timestamp_cntr_r1[31:0]" +Toggle 1to0 timestamp_cntr_r1 [21] "logic timestamp_cntr_r1[31:0]" +Toggle 0to1 timestamp_cntr_r1 [22] "logic timestamp_cntr_r1[31:0]" +Toggle 1to0 timestamp_cntr_r1 [22] "logic timestamp_cntr_r1[31:0]" +Toggle 0to1 timestamp_cntr_r1 [23] "logic timestamp_cntr_r1[31:0]" +Toggle 1to0 timestamp_cntr_r1 [23] "logic timestamp_cntr_r1[31:0]" +Toggle 0to1 timestamp_cntr_r1 [24] "logic timestamp_cntr_r1[31:0]" +Toggle 1to0 timestamp_cntr_r1 [24] "logic timestamp_cntr_r1[31:0]" +Toggle 0to1 timestamp_cntr_r1 [25] "logic timestamp_cntr_r1[31:0]" +Toggle 1to0 timestamp_cntr_r1 [25] "logic timestamp_cntr_r1[31:0]" +Toggle 0to1 timestamp_cntr_r1 [26] "logic timestamp_cntr_r1[31:0]" +Toggle 1to0 timestamp_cntr_r1 [26] "logic timestamp_cntr_r1[31:0]" +Toggle 0to1 timestamp_cntr_r1 [27] "logic timestamp_cntr_r1[31:0]" +Toggle 1to0 timestamp_cntr_r1 [27] "logic timestamp_cntr_r1[31:0]" +Toggle 0to1 timestamp_cntr_r1 [28] "logic timestamp_cntr_r1[31:0]" +Toggle 1to0 timestamp_cntr_r1 [28] "logic timestamp_cntr_r1[31:0]" +Toggle 0to1 timestamp_cntr_r1 [29] "logic timestamp_cntr_r1[31:0]" +Toggle 1to0 timestamp_cntr_r1 [29] "logic timestamp_cntr_r1[31:0]" +Toggle 0to1 timestamp_cntr_r1 [30] "logic timestamp_cntr_r1[31:0]" +Toggle 1to0 timestamp_cntr_r1 [30] "logic timestamp_cntr_r1[31:0]" +CHECKSUM: "3208458026 1943593004" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.genblk1.tx_filter_inst +Toggle 1to0 tx_mmio_st.tdata [254] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [254] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [253] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [253] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [252] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [252] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [251] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [251] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [250] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [250] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [249] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [249] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [248] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [248] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [247] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [247] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [246] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [246] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [245] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [245] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [244] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [244] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [243] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [243] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [242] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [242] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [241] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [241] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [240] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [240] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [239] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [239] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [238] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [238] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [237] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [237] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [236] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [236] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [235] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [235] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [234] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [234] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [233] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [233] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [232] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [232] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [231] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [231] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [230] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [230] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [229] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [229] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [228] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [228] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [227] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [227] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [226] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [226] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [225] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [225] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [224] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [224] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [223] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [223] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [222] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [222] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [221] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [221] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [220] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [220] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [219] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [219] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [218] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [218] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [217] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [217] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [216] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [216] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [215] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [215] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [214] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [214] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [213] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [213] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [212] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [212] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [211] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [211] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [210] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [210] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [209] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [209] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [208] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [208] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [207] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [207] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [206] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [206] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [205] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [205] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [204] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [204] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [203] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [203] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [202] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [202] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [201] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [201] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [200] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [200] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [199] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [199] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [198] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [198] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [197] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [197] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [196] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [196] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [195] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [195] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [194] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [194] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [193] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [193] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [192] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [192] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [191] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [191] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [190] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [190] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [189] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [189] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [188] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [188] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [187] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [187] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [186] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [186] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [185] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [185] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [184] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [184] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [183] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [183] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [182] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [182] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [181] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [181] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [180] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [180] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [179] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [179] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [178] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [178] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [177] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [177] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [176] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [176] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [175] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [175] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [174] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [174] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [173] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [173] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [172] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [172] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [171] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [171] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [170] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [170] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [169] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [169] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [168] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [168] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [167] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [167] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [166] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [166] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [165] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [165] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [164] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [164] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [163] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [163] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [162] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [162] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [161] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [161] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [160] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [160] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [159] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [159] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [158] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [158] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [157] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [157] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [156] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [156] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [155] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [155] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [154] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [154] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [153] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [153] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [152] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [152] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [151] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [151] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [150] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [150] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [149] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [149] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [148] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [148] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [147] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [147] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [146] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [146] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [145] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [145] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [144] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [144] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [143] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [143] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [142] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [142] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [141] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [141] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [140] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [140] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [139] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [139] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [138] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [138] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [137] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [137] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [136] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [136] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [135] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [135] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [134] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [134] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [133] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [133] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [132] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [132] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [131] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [131] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [130] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [130] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [129] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [129] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [128] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [128] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [127] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [127] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [126] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [126] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [125] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [125] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [124] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [124] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [123] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [123] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [122] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [122] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [121] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [121] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [120] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [120] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [119] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [119] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [118] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [118] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [117] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [117] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [116] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [116] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [115] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [115] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [114] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [114] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [113] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [113] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [112] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [112] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [111] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [111] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [110] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [110] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [109] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [109] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [108] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [108] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [107] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [107] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [106] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [106] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [105] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [105] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [104] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [104] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [103] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [103] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [102] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [102] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [101] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [101] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [100] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [100] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [99] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [99] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [98] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [98] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [97] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [97] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [96] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [96] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [95] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [95] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [94] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [94] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [93] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [93] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [92] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [92] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [91] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [91] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [90] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [90] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [89] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [89] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [88] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [88] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [87] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [87] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [86] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [86] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [85] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [85] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [84] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [84] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [83] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [83] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [82] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [82] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [81] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [81] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [15] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [15] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [14] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [14] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [12] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [12] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [13] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [13] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [11] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [11] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [10] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [10] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [9] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [9] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [8] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [8] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [7] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [7] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [6] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [6] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [5] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [5] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [4] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [4] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [2] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [2] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [3] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [3] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [20] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [20] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [22] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [22] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [21] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [21] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [23] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [23] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [24] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [24] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [26] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [26] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [29] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [29] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [28] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [28] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [31] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [31] "logic tx_mmio_st.tdata[511:0]" +Toggle 1to0 tx_mmio_st.tdata [255] "logic tx_mmio_st.tdata[511:0]" +Toggle 0to1 tx_mmio_st.tdata [255] "logic tx_mmio_st.tdata[511:0]" +Toggle cpl_hdr.TC "logic cpl_hdr.TC[2:0]" +Toggle cpl_hdr.fmt_type "logic cpl_hdr.fmt_type[7:0]" +Toggle cpl_hdr.cpl_status "logic cpl_hdr.cpl_status[2:0]" +Toggle cpl_hdr.comp_id "logic cpl_hdr.comp_id[15:0]" +Toggle 0to1 cpl_hdr.bcm "logic cpl_hdr.bcm" +Toggle 1to0 cpl_hdr.bcm "logic cpl_hdr.bcm" +Toggle cpl_hdr.attr.rsvd2 "logic cpl_hdr.attr.rsvd2[1:0]" +Toggle 0to1 cpl_hdr.attr.rsvd1 "logic cpl_hdr.attr.rsvd1" +Toggle 1to0 cpl_hdr.attr.rsvd1 "logic cpl_hdr.attr.rsvd1" +Toggle 0to1 cpl_hdr.attr.TH "logic cpl_hdr.attr.TH" +Toggle 1to0 cpl_hdr.attr.TH "logic cpl_hdr.attr.TH" +Toggle 0to1 cpl_hdr.attr.TD "logic cpl_hdr.attr.TD" +Toggle 1to0 cpl_hdr.attr.TD "logic cpl_hdr.attr.TD" +Toggle 0to1 cpl_hdr.attr.LN "logic cpl_hdr.attr.LN" +Toggle 1to0 cpl_hdr.attr.LN "logic cpl_hdr.attr.LN" +Toggle 0to1 cpl_hdr.attr.EP "logic cpl_hdr.attr.EP" +Toggle 1to0 cpl_hdr.attr.EP "logic cpl_hdr.attr.EP" +Toggle cpl_hdr.attr.AT "logic cpl_hdr.attr.AT[1:0]" +Toggle cpl_hdr.metadata_h "logic cpl_hdr.metadata_h[31:0]" +Toggle cpl_hdr.pref "logic cpl_hdr.pref[23:0]" +Toggle cpl_hdr.pf_num "logic cpl_hdr.pf_num[2:0]" +Toggle 0to1 cpl_hdr.mm_mode "logic cpl_hdr.mm_mode" +Toggle 1to0 cpl_hdr.mm_mode "logic cpl_hdr.mm_mode" +Toggle cpl_hdr.metadata_l "logic cpl_hdr.metadata_l[31:0]" +Toggle cpl_hdr.slot_num "logic cpl_hdr.slot_num[4:0]" +Toggle 0to1 cpl_hdr.pref_present "logic cpl_hdr.pref_present" +Toggle 1to0 cpl_hdr.pref_present "logic cpl_hdr.pref_present" +Toggle cpl_hdr.pref_type "logic cpl_hdr.pref_type[4:0]" +Toggle cpl_hdr.rsvd3 "logic cpl_hdr.rsvd3[1:0]" +Toggle cpl_hdr.req_id "logic cpl_hdr.req_id[15:0]" +Toggle cpl_hdr.rsvd1 "logic cpl_hdr.rsvd1[6:0]" +Toggle cpl_hdr.rsvd2 "logic cpl_hdr.rsvd2[3:0]" +Toggle 0to1 cpl_hdr.rsvd5 "logic cpl_hdr.rsvd5" +Toggle 1to0 cpl_hdr.rsvd5 "logic cpl_hdr.rsvd5" +Toggle cpl_hdr.rsvd4 "logic cpl_hdr.rsvd4[31:0]" +Toggle 0to1 cpl_hdr.vf_active "logic cpl_hdr.vf_active" +Toggle 1to0 cpl_hdr.vf_active "logic cpl_hdr.vf_active" +Toggle cpl_hdr.vf_num "logic cpl_hdr.vf_num[10:0]" +Toggle 0to1 i_mmio_timeout_info.addr [17] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [17] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [19] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [19] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [21] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [21] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [25] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [25] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [26] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [26] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [29] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [29] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [28] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [28] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [27] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [27] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [31] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [31] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [30] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [30] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [24] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [24] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [23] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [23] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [22] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [22] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [20] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [20] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [18] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [18] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [6] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [6] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [7] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [7] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [8] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [8] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [10] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [10] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [14] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [14] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [9] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [9] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [11] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [11] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [12] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [12] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [13] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [13] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [5] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [5] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [0] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [0] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.addr [2] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 1to0 i_mmio_timeout_info.addr [2] "logic i_mmio_timeout_info.addr[31:0]" +Toggle 0to1 i_mmio_timeout_info.dw0_len [9] "logic i_mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 i_mmio_timeout_info.dw0_len [9] "logic i_mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 i_mmio_timeout_info.dw0_len [2] "logic i_mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 i_mmio_timeout_info.dw0_len [2] "logic i_mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 i_mmio_timeout_info.dw0_len [3] "logic i_mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 i_mmio_timeout_info.dw0_len [3] "logic i_mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 i_mmio_timeout_info.dw0_len [4] "logic i_mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 i_mmio_timeout_info.dw0_len [4] "logic i_mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 i_mmio_timeout_info.dw0_len [5] "logic i_mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 i_mmio_timeout_info.dw0_len [5] "logic i_mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 i_mmio_timeout_info.dw0_len [6] "logic i_mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 i_mmio_timeout_info.dw0_len [6] "logic i_mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 i_mmio_timeout_info.dw0_len [7] "logic i_mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 i_mmio_timeout_info.dw0_len [7] "logic i_mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 i_mmio_timeout_info.dw0_len [8] "logic i_mmio_timeout_info.dw0_len[9:0]" +Toggle 1to0 i_mmio_timeout_info.dw0_len [8] "logic i_mmio_timeout_info.dw0_len[9:0]" +Toggle 0to1 i_mmio_timeout_info.requester_id [15] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 i_mmio_timeout_info.requester_id [15] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 i_mmio_timeout_info.requester_id [1] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 i_mmio_timeout_info.requester_id [1] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 i_mmio_timeout_info.requester_id [2] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 i_mmio_timeout_info.requester_id [2] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 i_mmio_timeout_info.requester_id [3] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 i_mmio_timeout_info.requester_id [3] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 i_mmio_timeout_info.requester_id [4] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 i_mmio_timeout_info.requester_id [4] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 i_mmio_timeout_info.requester_id [5] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 i_mmio_timeout_info.requester_id [5] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 i_mmio_timeout_info.requester_id [6] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 i_mmio_timeout_info.requester_id [6] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 i_mmio_timeout_info.requester_id [7] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 i_mmio_timeout_info.requester_id [7] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 i_mmio_timeout_info.requester_id [8] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 i_mmio_timeout_info.requester_id [8] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 i_mmio_timeout_info.requester_id [9] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 i_mmio_timeout_info.requester_id [9] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 i_mmio_timeout_info.requester_id [10] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 i_mmio_timeout_info.requester_id [10] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 i_mmio_timeout_info.requester_id [11] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 i_mmio_timeout_info.requester_id [11] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 i_mmio_timeout_info.requester_id [12] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 i_mmio_timeout_info.requester_id [12] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 i_mmio_timeout_info.requester_id [13] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 i_mmio_timeout_info.requester_id [13] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 i_mmio_timeout_info.requester_id [14] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 1to0 i_mmio_timeout_info.requester_id [14] "logic i_mmio_timeout_info.requester_id[15:0]" +Toggle 0to1 tx_st_t1.tready "logic tx_st_t1.tready" +Toggle 1to0 tx_st_t1.tready "logic tx_st_t1.tready" +Toggle 0to1 tx_st_t1.tuser [9] "logic tx_st_t1.tuser[9:0]" +Toggle 1to0 tx_st_t1.tuser [9] "logic tx_st_t1.tuser[9:0]" +Toggle 0to1 tx_st_t1.tuser [1] "logic tx_st_t1.tuser[9:0]" +Toggle 1to0 tx_st_t1.tuser [1] "logic tx_st_t1.tuser[9:0]" +Toggle 0to1 tx_st_t1.tuser [2] "logic tx_st_t1.tuser[9:0]" +Toggle 1to0 tx_st_t1.tuser [2] "logic tx_st_t1.tuser[9:0]" +Toggle 0to1 tx_st_t1.tuser [3] "logic tx_st_t1.tuser[9:0]" +Toggle 1to0 tx_st_t1.tuser [3] "logic tx_st_t1.tuser[9:0]" +Toggle 0to1 tx_st_t1.tuser [4] "logic tx_st_t1.tuser[9:0]" +Toggle 1to0 tx_st_t1.tuser [4] "logic tx_st_t1.tuser[9:0]" +Toggle 0to1 tx_st_t1.tuser [5] "logic tx_st_t1.tuser[9:0]" +Toggle 1to0 tx_st_t1.tuser [5] "logic tx_st_t1.tuser[9:0]" +Toggle 0to1 tx_st_t1.tuser [6] "logic tx_st_t1.tuser[9:0]" +Toggle 1to0 tx_st_t1.tuser [6] "logic tx_st_t1.tuser[9:0]" +Toggle 0to1 tx_st_t1.tuser [7] "logic tx_st_t1.tuser[9:0]" +Toggle 1to0 tx_st_t1.tuser [7] "logic tx_st_t1.tuser[9:0]" +Toggle 0to1 tx_st_t1.tuser [8] "logic tx_st_t1.tuser[9:0]" +Toggle 1to0 tx_st_t1.tuser [8] "logic tx_st_t1.tuser[9:0]" +Toggle 0to1 tx_st_t2.tready "logic tx_st_t2.tready" +Toggle 1to0 tx_st_t2.tready "logic tx_st_t2.tready" +Toggle 0to1 tx_st_t2.tuser [9] "logic tx_st_t2.tuser[9:0]" +Toggle 1to0 tx_st_t2.tuser [9] "logic tx_st_t2.tuser[9:0]" +Toggle 0to1 tx_st_t2.tuser [1] "logic tx_st_t2.tuser[9:0]" +Toggle 1to0 tx_st_t2.tuser [1] "logic tx_st_t2.tuser[9:0]" +Toggle 0to1 tx_st_t2.tuser [2] "logic tx_st_t2.tuser[9:0]" +Toggle 1to0 tx_st_t2.tuser [2] "logic tx_st_t2.tuser[9:0]" +Toggle 0to1 tx_st_t2.tuser [3] "logic tx_st_t2.tuser[9:0]" +Toggle 1to0 tx_st_t2.tuser [3] "logic tx_st_t2.tuser[9:0]" +Toggle 0to1 tx_st_t2.tuser [4] "logic tx_st_t2.tuser[9:0]" +Toggle 1to0 tx_st_t2.tuser [4] "logic tx_st_t2.tuser[9:0]" +Toggle 0to1 tx_st_t2.tuser [5] "logic tx_st_t2.tuser[9:0]" +Toggle 1to0 tx_st_t2.tuser [5] "logic tx_st_t2.tuser[9:0]" +Toggle 0to1 tx_st_t2.tuser [6] "logic tx_st_t2.tuser[9:0]" +Toggle 1to0 tx_st_t2.tuser [6] "logic tx_st_t2.tuser[9:0]" +Toggle 0to1 tx_st_t2.tuser [7] "logic tx_st_t2.tuser[9:0]" +Toggle 1to0 tx_st_t2.tuser [7] "logic tx_st_t2.tuser[9:0]" +Toggle 0to1 tx_st_t2.tuser [8] "logic tx_st_t2.tuser[9:0]" +Toggle 1to0 tx_st_t2.tuser [8] "logic tx_st_t2.tuser[9:0]" +Toggle 0to1 tx_st_t3.tready "logic tx_st_t3.tready" +Toggle 1to0 tx_st_t3.tready "logic tx_st_t3.tready" +Toggle 0to1 tx_st_t3.tuser [9] "logic tx_st_t3.tuser[9:0]" +Toggle 1to0 tx_st_t3.tuser [9] "logic tx_st_t3.tuser[9:0]" +Toggle 0to1 tx_st_t3.tuser [1] "logic tx_st_t3.tuser[9:0]" +Toggle 1to0 tx_st_t3.tuser [1] "logic tx_st_t3.tuser[9:0]" +Toggle 0to1 tx_st_t3.tuser [2] "logic tx_st_t3.tuser[9:0]" +Toggle 1to0 tx_st_t3.tuser [2] "logic tx_st_t3.tuser[9:0]" +Toggle 0to1 tx_st_t3.tuser [3] "logic tx_st_t3.tuser[9:0]" +Toggle 1to0 tx_st_t3.tuser [3] "logic tx_st_t3.tuser[9:0]" +Toggle 0to1 tx_st_t3.tuser [4] "logic tx_st_t3.tuser[9:0]" +Toggle 1to0 tx_st_t3.tuser [4] "logic tx_st_t3.tuser[9:0]" +Toggle 0to1 tx_st_t3.tuser [5] "logic tx_st_t3.tuser[9:0]" +Toggle 1to0 tx_st_t3.tuser [5] "logic tx_st_t3.tuser[9:0]" +Toggle 0to1 tx_st_t3.tuser [6] "logic tx_st_t3.tuser[9:0]" +Toggle 1to0 tx_st_t3.tuser [6] "logic tx_st_t3.tuser[9:0]" +Toggle 0to1 tx_st_t3.tuser [7] "logic tx_st_t3.tuser[9:0]" +Toggle 1to0 tx_st_t3.tuser [7] "logic tx_st_t3.tuser[9:0]" +Toggle 0to1 tx_st_t3.tuser [8] "logic tx_st_t3.tuser[9:0]" +Toggle 1to0 tx_st_t3.tuser [8] "logic tx_st_t3.tuser[9:0]" +Toggle 0to1 tx_st_t4.tready "logic tx_st_t4.tready" +Toggle 1to0 tx_st_t4.tready "logic tx_st_t4.tready" +Toggle 0to1 tx_st_t4.tuser [9] "logic tx_st_t4.tuser[9:0]" +Toggle 1to0 tx_st_t4.tuser [9] "logic tx_st_t4.tuser[9:0]" +Toggle 0to1 tx_st_t4.tuser [1] "logic tx_st_t4.tuser[9:0]" +Toggle 1to0 tx_st_t4.tuser [1] "logic tx_st_t4.tuser[9:0]" +Toggle 0to1 tx_st_t4.tuser [2] "logic tx_st_t4.tuser[9:0]" +Toggle 1to0 tx_st_t4.tuser [2] "logic tx_st_t4.tuser[9:0]" +Toggle 0to1 tx_st_t4.tuser [3] "logic tx_st_t4.tuser[9:0]" +Toggle 1to0 tx_st_t4.tuser [3] "logic tx_st_t4.tuser[9:0]" +Toggle 0to1 tx_st_t4.tuser [4] "logic tx_st_t4.tuser[9:0]" +Toggle 1to0 tx_st_t4.tuser [4] "logic tx_st_t4.tuser[9:0]" +Toggle 0to1 tx_st_t4.tuser [5] "logic tx_st_t4.tuser[9:0]" +Toggle 1to0 tx_st_t4.tuser [5] "logic tx_st_t4.tuser[9:0]" +Toggle 0to1 tx_st_t4.tuser [6] "logic tx_st_t4.tuser[9:0]" +Toggle 1to0 tx_st_t4.tuser [6] "logic tx_st_t4.tuser[9:0]" +Toggle 0to1 tx_st_t4.tuser [7] "logic tx_st_t4.tuser[9:0]" +Toggle 1to0 tx_st_t4.tuser [7] "logic tx_st_t4.tuser[9:0]" +Toggle 0to1 tx_st_t4.tuser [8] "logic tx_st_t4.tuser[9:0]" +Toggle 1to0 tx_st_t4.tuser [8] "logic tx_st_t4.tuser[9:0]" +Toggle 0to1 tx_st_t4.tkeep [31] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [31] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [0] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [0] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [1] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [1] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [2] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [2] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [3] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [3] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [4] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [4] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [5] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [5] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [6] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [6] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [7] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [7] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [8] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [8] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [9] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [9] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [10] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [10] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [11] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [11] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [12] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [12] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [13] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [13] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [14] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [14] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [15] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [15] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [16] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [16] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [17] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [17] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [18] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [18] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [19] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [19] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [20] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [20] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [21] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [21] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [22] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [22] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [23] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [23] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [24] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [24] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [25] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [25] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [26] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [26] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [27] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [27] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [28] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [28] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [29] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [29] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t4.tkeep [30] "logic tx_st_t4.tkeep[63:0]" +Toggle 1to0 tx_st_t4.tkeep [30] "logic tx_st_t4.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [31] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [31] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [0] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [0] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [1] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [1] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [2] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [2] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [3] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [3] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [4] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [4] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [5] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [5] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [6] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [6] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [7] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [7] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [8] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [8] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [9] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [9] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [10] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [10] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [11] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [11] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [12] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [12] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [13] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [13] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [14] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [14] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [15] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [15] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [16] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [16] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [17] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [17] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [18] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [18] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [19] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [19] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [20] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [20] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [21] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [21] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [22] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [22] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [23] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [23] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [24] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [24] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [25] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [25] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [26] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [26] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [27] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [27] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [28] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [28] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [29] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [29] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t1.tkeep [30] "logic tx_st_t1.tkeep[63:0]" +Toggle 1to0 tx_st_t1.tkeep [30] "logic tx_st_t1.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [31] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [31] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [0] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [0] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [1] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [1] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [2] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [2] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [3] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [3] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [4] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [4] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [5] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [5] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [6] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [6] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [7] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [7] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [8] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [8] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [9] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [9] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [10] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [10] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [11] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [11] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [12] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [12] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [13] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [13] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [14] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [14] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [15] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [15] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [16] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [16] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [17] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [17] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [18] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [18] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [19] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [19] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [20] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [20] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [21] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [21] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [22] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [22] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [23] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [23] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [24] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [24] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [25] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [25] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [26] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [26] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [27] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [27] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [28] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [28] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [29] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [29] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t2.tkeep [30] "logic tx_st_t2.tkeep[63:0]" +Toggle 1to0 tx_st_t2.tkeep [30] "logic tx_st_t2.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [31] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [31] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [0] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [0] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [1] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [1] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [2] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [2] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [3] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [3] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [4] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [4] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [5] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [5] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [6] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [6] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [7] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [7] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [8] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [8] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [9] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [9] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [10] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [10] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [11] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [11] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [12] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [12] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [13] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [13] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [14] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [14] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [15] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [15] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [16] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [16] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [17] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [17] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [18] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [18] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [19] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [19] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [20] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [20] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [21] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [21] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [22] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [22] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [23] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [23] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [24] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [24] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [25] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [25] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [26] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [26] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [27] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [27] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [28] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [28] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [29] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [29] "logic tx_st_t3.tkeep[63:0]" +Toggle 0to1 tx_st_t3.tkeep [30] "logic tx_st_t3.tkeep[63:0]" +Toggle 1to0 tx_st_t3.tkeep [30] "logic tx_st_t3.tkeep[63:0]" +CHECKSUM: "2621707631 1364962013" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.genblk1.mmio_handler_inst +Fsm state "1364962013" +Transition FIND_NEXT_PENDING_RD->NOMINAL "2->0" +Fsm state "1364962013" +Transition WAIT_FOR_MMIO_RD_RSP->NOMINAL "1->0" +CHECKSUM: "1713082210 1847888105" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.mc_csr_slave +Fsm rd_state "3926564203" +Transition RD_CSR_BIT->RD_IDLE_BIT "2->1" +Fsm rd_state "3926564203" +Transition RD_WAIT_BIT->RD_IDLE_BIT "4->1" +Fsm wr_state "3695951294" +Transition WR_DATA_BIT->WR_IDLE_BIT "2->1" +Fsm wr_state "3695951294" +Transition WR_CSR_BIT->WR_IDLE_BIT "4->1" +CHECKSUM: "3208458026 2700146979" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.genblk1.tx_filter_inst +Fsm state "2700146979" +Transition SEND_MMIO_TIMEOUT_RSP->IDLE "1->0" +CHECKSUM: "4222645203 2367304296" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.axi_lite2mmio +Toggle 1to0 rst_n "net rst_n" +CHECKSUM: "1062064731 2935107029" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.port_traffic_control_inst.port_tx_fifo +Condition 1 "724213785" "(softreset_asserted ? i_afu_softreset : 1'b0) 1 -1" (2 "1") +CHECKSUM: "2346030483 1878446231" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst +Branch 5 "3707924482" "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_CFG_WRITE))" (0) "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_CFG_WRITE)) 1" +Branch 12 "2472182135" "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_CAS32))" (0) "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_CAS32)) 1" +Branch 11 "4263743617" "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_SWAP64))" (0) "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_SWAP64)) 1" +Branch 10 "3338836289" "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_SWAP32))" (0) "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_SWAP32)) 1" +Branch 9 "175153993" "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_FETCH_ADD64))" (0) "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_FETCH_ADD64)) 1" +Branch 8 "860990089" "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_FETCH_ADD32))" (0) "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_FETCH_ADD32)) 1" +Branch 6 "739647916" "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_CPL))" (0) "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_CPL)) 1" +Branch 13 "2860222647" "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_CAS64))" (0) "(tx_valid_sop_T1 && (tx_fmttype_T1 == pcie_ss_hdr_pkg::PCIE_FMTTYPE_CAS64)) 1" +Branch 19 "3223004554" "i_afu_softreset_dlyd" (1) "i_afu_softreset_dlyd 0,1,1,-,-,-,-,-" +Branch 22 "1934606245" "i_afu_softreset_dlyd" (1) "i_afu_softreset_dlyd 0,1" +Branch 21 "1646363674" "i_afu_softreset_dlyd" (1) "i_afu_softreset_dlyd 0,1" +CHECKSUM: "2402049597 748327626" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.csr_if +ANNOTATION: " Values are fixed/tied in design " +Toggle awburst "logic awburst[1:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle arqos "logic arqos[3:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle arcache "logic arcache[3:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle arburst "logic arburst[1:0]" +Toggle 0to1 wlast "logic wlast" +Toggle 1to0 wlast "logic wlast" +ANNOTATION: " Values are fixed/tied in design " +Toggle awqos "logic awqos[3:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle awcache "logic awcache[3:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle arid "logic arid[9:0]" +Toggle 0to1 aruser [0] "logic aruser[0:0]" +Toggle 1to0 aruser [0] "logic aruser[0:0]" +Toggle 0to1 arlock "logic arlock" +Toggle 1to0 arlock "logic arlock" +ANNOTATION: " Values are fixed/tied in design " +Toggle arlen "logic arlen[7:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle awid "logic awid[9:0]" +Toggle 0to1 awlock "logic awlock" +Toggle 1to0 awlock "logic awlock" +ANNOTATION: " Values are fixed/tied in design " +Toggle awlen "logic awlen[7:0]" +Toggle 0to1 awuser [0] "logic awuser[0:0]" +Toggle 1to0 awuser [0] "logic awuser[0:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle bid "logic bid[9:0]" +Toggle 0to1 buser [0] "logic buser[0:0]" +Toggle 1to0 buser [0] "logic buser[0:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle rid "logic rid[9:0]" +Toggle 0to1 ruser [0] "logic ruser[0:0]" +Toggle 1to0 ruser [0] "logic ruser[0:0]" +Toggle 0to1 wuser [0] "logic wuser[0:0]" +Toggle 1to0 wuser [0] "logic wuser[0:0]" +Toggle 0to1 araddr [1] "logic araddr[20:0]" +Toggle 1to0 araddr [1] "logic araddr[20:0]" +Toggle 0to1 araddr [6] "logic araddr[20:0]" +Toggle 1to0 araddr [6] "logic araddr[20:0]" +Toggle 0to1 araddr [7] "logic araddr[20:0]" +Toggle 1to0 araddr [7] "logic araddr[20:0]" +Toggle 0to1 araddr [8] "logic araddr[20:0]" +Toggle 1to0 araddr [8] "logic araddr[20:0]" +Toggle 0to1 araddr [9] "logic araddr[20:0]" +Toggle 1to0 araddr [9] "logic araddr[20:0]" +Toggle 0to1 araddr [10] "logic araddr[20:0]" +Toggle 1to0 araddr [10] "logic araddr[20:0]" +Toggle 0to1 araddr [11] "logic araddr[20:0]" +Toggle 1to0 araddr [11] "logic araddr[20:0]" +Toggle 0to1 araddr [12] "logic araddr[20:0]" +Toggle 1to0 araddr [12] "logic araddr[20:0]" +Toggle 0to1 araddr [13] "logic araddr[20:0]" +Toggle 1to0 araddr [13] "logic araddr[20:0]" +Toggle 0to1 araddr [14] "logic araddr[20:0]" +Toggle 1to0 araddr [14] "logic araddr[20:0]" +Toggle 0to1 araddr [15] "logic araddr[20:0]" +Toggle 1to0 araddr [15] "logic araddr[20:0]" +Toggle 0to1 araddr [16] "logic araddr[20:0]" +Toggle 1to0 araddr [16] "logic araddr[20:0]" +Toggle 0to1 araddr [17] "logic araddr[20:0]" +Toggle 1to0 araddr [17] "logic araddr[20:0]" +Toggle 0to1 araddr [18] "logic araddr[20:0]" +Toggle 1to0 araddr [18] "logic araddr[20:0]" +Toggle 0to1 araddr [19] "logic araddr[20:0]" +Toggle 1to0 araddr [19] "logic araddr[20:0]" +Toggle 0to1 araddr [20] "logic araddr[20:0]" +Toggle 1to0 araddr [20] "logic araddr[20:0]" +Toggle 0to1 araddr [0] "logic araddr[20:0]" +Toggle 1to0 araddr [0] "logic araddr[20:0]" +Toggle 0to1 awaddr [20] "logic awaddr[20:0]" +Toggle 1to0 awaddr [20] "logic awaddr[20:0]" +Toggle 0to1 awaddr [0] "logic awaddr[20:0]" +Toggle 1to0 awaddr [0] "logic awaddr[20:0]" +Toggle 0to1 awaddr [1] "logic awaddr[20:0]" +Toggle 1to0 awaddr [1] "logic awaddr[20:0]" +Toggle 0to1 awaddr [6] "logic awaddr[20:0]" +Toggle 1to0 awaddr [6] "logic awaddr[20:0]" +Toggle 0to1 awaddr [7] "logic awaddr[20:0]" +Toggle 1to0 awaddr [7] "logic awaddr[20:0]" +Toggle 0to1 awaddr [8] "logic awaddr[20:0]" +Toggle 1to0 awaddr [8] "logic awaddr[20:0]" +Toggle 0to1 awaddr [9] "logic awaddr[20:0]" +Toggle 1to0 awaddr [9] "logic awaddr[20:0]" +Toggle 0to1 awaddr [10] "logic awaddr[20:0]" +Toggle 1to0 awaddr [10] "logic awaddr[20:0]" +Toggle 0to1 awaddr [11] "logic awaddr[20:0]" +Toggle 1to0 awaddr [11] "logic awaddr[20:0]" +Toggle 0to1 awaddr [12] "logic awaddr[20:0]" +Toggle 1to0 awaddr [12] "logic awaddr[20:0]" +Toggle 0to1 awaddr [13] "logic awaddr[20:0]" +Toggle 1to0 awaddr [13] "logic awaddr[20:0]" +Toggle 0to1 awaddr [14] "logic awaddr[20:0]" +Toggle 1to0 awaddr [14] "logic awaddr[20:0]" +Toggle 0to1 awaddr [15] "logic awaddr[20:0]" +Toggle 1to0 awaddr [15] "logic awaddr[20:0]" +Toggle 0to1 awaddr [16] "logic awaddr[20:0]" +Toggle 1to0 awaddr [16] "logic awaddr[20:0]" +Toggle 0to1 awaddr [17] "logic awaddr[20:0]" +Toggle 1to0 awaddr [17] "logic awaddr[20:0]" +Toggle 0to1 awaddr [18] "logic awaddr[20:0]" +Toggle 1to0 awaddr [18] "logic awaddr[20:0]" +Toggle 0to1 awaddr [19] "logic awaddr[20:0]" +Toggle 1to0 awaddr [19] "logic awaddr[20:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle bresp "logic bresp[1:0]" +Toggle rresp "logic rresp[1:0]" +Toggle 0to1 awsize [2] "logic awsize[2:0]" +Toggle 1to0 awsize [2] "logic awsize[2:0]" +Toggle 0to1 awsize [1] "logic awsize[2:0]" +Toggle 1to0 awsize [1] "logic awsize[2:0]" +Toggle 0to1 arsize [2] "logic arsize[2:0]" +Toggle 1to0 arsize [2] "logic arsize[2:0]" +Toggle 0to1 arsize [1] "logic arsize[2:0]" +Toggle 1to0 arsize [1] "logic arsize[2:0]" +CHECKSUM: "1259019545 3297052881" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.port_traffic_control_inst.axi_tx_stage +Toggle s_tid "net s_tid[7:0]" +Toggle 1to0 s_tuser [8] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [8] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [7] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [7] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [6] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [6] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [5] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [5] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [4] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [4] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [3] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [3] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [2] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [2] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [1] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [1] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [9] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [9] "net s_tuser[9:0]" +Toggle s_tdest "net s_tdest[7:0]" +Toggle 1to0 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tdest_reg [6] "reg genblk1.s_tdest_reg[7:0]" +Toggle 0to1 genblk1.s_tdest_reg [6] "reg genblk1.s_tdest_reg[7:0]" +Toggle 1to0 genblk1.s_tdest_reg [5] "reg genblk1.s_tdest_reg[7:0]" +Toggle 0to1 genblk1.s_tdest_reg [5] "reg genblk1.s_tdest_reg[7:0]" +Toggle 1to0 genblk1.s_tdest_reg [4] "reg genblk1.s_tdest_reg[7:0]" +Toggle 0to1 genblk1.s_tdest_reg [4] "reg genblk1.s_tdest_reg[7:0]" +Toggle 1to0 genblk1.s_tdest_reg [3] "reg genblk1.s_tdest_reg[7:0]" +Toggle 0to1 genblk1.s_tdest_reg [3] "reg genblk1.s_tdest_reg[7:0]" +Toggle 1to0 genblk1.s_tdest_reg [2] "reg genblk1.s_tdest_reg[7:0]" +Toggle 0to1 genblk1.s_tdest_reg [2] "reg genblk1.s_tdest_reg[7:0]" +Toggle 1to0 genblk1.s_tdest_reg [1] "reg genblk1.s_tdest_reg[7:0]" +Toggle 0to1 genblk1.s_tdest_reg [1] "reg genblk1.s_tdest_reg[7:0]" +Toggle 1to0 genblk1.s_tdest_reg [0] "reg genblk1.s_tdest_reg[7:0]" +Toggle 0to1 genblk1.s_tdest_reg [0] "reg genblk1.s_tdest_reg[7:0]" +Toggle 1to0 genblk1.s_tdest_reg [7] "reg genblk1.s_tdest_reg[7:0]" +Toggle 0to1 genblk1.s_tdest_reg [7] "reg genblk1.s_tdest_reg[7:0]" +Toggle genblk1.s_tid_reg "reg genblk1.s_tid_reg[7:0]" +Toggle 1to0 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle m_tdest "net m_tdest[7:0]" +Toggle m_tid "net m_tid[7:0]" +Toggle 1to0 m_tuser [8] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [8] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [7] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [7] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [6] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [6] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [5] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [5] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [4] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [4] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [3] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [3] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [2] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [2] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [1] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [1] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [9] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [9] "net m_tuser[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle genblk1.m_tdest_reg "reg genblk1.m_tdest_reg[7:0]" +Toggle genblk1.m_tid_pre "reg genblk1.m_tid_pre[7:0]" +Toggle genblk1.m_tid_reg "reg genblk1.m_tid_reg[7:0]" +Toggle genblk1.m_tdest_pre "reg genblk1.m_tdest_pre[7:0]" +CHECKSUM: "2414341016 1012398714" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst +Toggle 0to1 error_vector.mmio_rd_while_rst "logic error_vector.mmio_rd_while_rst" +Toggle 1to0 error_vector.mmio_rd_while_rst "logic error_vector.mmio_rd_while_rst" +Toggle 0to1 error_vector.unaligned_addr "logic error_vector.unaligned_addr" +Toggle 1to0 error_vector.unaligned_addr "logic error_vector.unaligned_addr" +Toggle 0to1 error_vector.tx_valid_violation "logic error_vector.tx_valid_violation" +Toggle 1to0 error_vector.tx_valid_violation "logic error_vector.tx_valid_violation" +Toggle 0to1 error_vector.tx_req_counter_oflow "logic error_vector.tx_req_counter_oflow" +Toggle 1to0 error_vector.tx_req_counter_oflow "logic error_vector.tx_req_counter_oflow" +Toggle 0to1 error_vector.tag_occupied "logic error_vector.tag_occupied" +Toggle 1to0 error_vector.tag_occupied "logic error_vector.tag_occupied" +Toggle 0to1 error_vector.mmio_wr_while_rst "logic error_vector.mmio_wr_while_rst" +Toggle 1to0 error_vector.mmio_wr_while_rst "logic error_vector.mmio_wr_while_rst" +Toggle 0to1 mmio_rd_while_rst_err "logic mmio_rd_while_rst_err" +Toggle 1to0 mmio_rd_while_rst_err "logic mmio_rd_while_rst_err" +Toggle 0to1 tag_occupied_err "logic tag_occupied_err" +Toggle 1to0 tag_occupied_err "logic tag_occupied_err" +Toggle 0to1 mmio_wr_while_rst_err "logic mmio_wr_while_rst_err" +Toggle 1to0 mmio_wr_while_rst_err "logic mmio_wr_while_rst_err" +CHECKSUM: "1062064731 608200567" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.port_traffic_control_inst.port_tx_fifo +Toggle 1to0 afu_softreset_r2 "logic afu_softreset_r2" +Toggle 0to1 afu_softreset_r2 "logic afu_softreset_r2" +Toggle 1to0 i_afu_softreset "logic i_afu_softreset" +Toggle 0to1 i_afu_softreset "logic i_afu_softreset" +Toggle 1to0 softreset_asserted "logic softreset_asserted" +Toggle 0to1 softreset_asserted "logic softreset_asserted" +Toggle 1to0 afu_softreset_r1 "logic afu_softreset_r1" +Toggle 0to1 afu_softreset_r1 "logic afu_softreset_r1" +CHECKSUM: "2346030483 61578261" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.genblk1.protocol_checker_inst +Toggle 1to0 rx_mwr_T1 "logic rx_mwr_T1" +Toggle 0to1 rx_mwr_T1 "logic rx_mwr_T1" +Toggle 1to0 rx_mrd_T1 "logic rx_mrd_T1" +Toggle 0to1 rx_mrd_T1 "logic rx_mrd_T1" +Toggle 1to0 i_rx_mwr "logic i_rx_mwr" +Toggle 0to1 i_rx_mwr "logic i_rx_mwr" +Toggle 1to0 i_rx_mrd "logic i_rx_mrd" +Toggle 0to1 i_rx_mrd "logic i_rx_mrd" +Toggle 1to0 fmttype_err_bus [11] "logic fmttype_err_bus[15:0]" +Toggle 0to1 fmttype_err_bus [11] "logic fmttype_err_bus[15:0]" +Toggle 1to0 fmttype_err_bus [10] "logic fmttype_err_bus[15:0]" +Toggle 0to1 fmttype_err_bus [10] "logic fmttype_err_bus[15:0]" +Toggle 1to0 fmttype_err_bus [9] "logic fmttype_err_bus[15:0]" +Toggle 0to1 fmttype_err_bus [9] "logic fmttype_err_bus[15:0]" +Toggle 1to0 fmttype_err_bus [8] "logic fmttype_err_bus[15:0]" +Toggle 0to1 fmttype_err_bus [8] "logic fmttype_err_bus[15:0]" +Toggle 1to0 fmttype_err_bus [7] "logic fmttype_err_bus[15:0]" +Toggle 0to1 fmttype_err_bus [7] "logic fmttype_err_bus[15:0]" +Toggle 1to0 fmttype_err_bus [5] "logic fmttype_err_bus[15:0]" +Toggle 0to1 fmttype_err_bus [5] "logic fmttype_err_bus[15:0]" +Toggle 1to0 fmttype_err_bus [4] "logic fmttype_err_bus[15:0]" +Toggle 0to1 fmttype_err_bus [4] "logic fmttype_err_bus[15:0]" +Toggle 1to0 fmttype_err_bus [12] "logic fmttype_err_bus[15:0]" +Toggle 0to1 fmttype_err_bus [12] "logic fmttype_err_bus[15:0]" +Toggle 1to0 o_mmio_rd_while_rst_err "logic o_mmio_rd_while_rst_err" +Toggle 0to1 o_mmio_rd_while_rst_err "logic o_mmio_rd_while_rst_err" +Toggle 1to0 o_mmio_wr_while_rst_err "logic o_mmio_wr_while_rst_err" +Toggle 0to1 o_mmio_wr_while_rst_err "logic o_mmio_wr_while_rst_err" +Toggle 1to0 o_max_read_req_size_err "logic o_max_read_req_size_err" +Toggle 0to1 o_max_read_req_size_err "logic o_max_read_req_size_err" +Toggle 0to1 acc_len [4] "logic acc_len[23:0]" +Toggle 1to0 acc_len [4] "logic acc_len[23:0]" +Toggle 0to1 acc_len [8] "logic acc_len[23:0]" +Toggle 1to0 acc_len [8] "logic acc_len[23:0]" +Toggle 0to1 acc_len [9] "logic acc_len[23:0]" +Toggle 1to0 acc_len [9] "logic acc_len[23:0]" +Toggle 0to1 acc_len [10] "logic acc_len[23:0]" +Toggle 1to0 acc_len [10] "logic acc_len[23:0]" +Toggle 0to1 acc_len [11] "logic acc_len[23:0]" +Toggle 1to0 acc_len [11] "logic acc_len[23:0]" +Toggle 0to1 acc_len [12] "logic acc_len[23:0]" +Toggle 1to0 acc_len [12] "logic acc_len[23:0]" +Toggle 0to1 acc_len [13] "logic acc_len[23:0]" +Toggle 1to0 acc_len [13] "logic acc_len[23:0]" +Toggle 0to1 acc_len [14] "logic acc_len[23:0]" +Toggle 1to0 acc_len [14] "logic acc_len[23:0]" +Toggle 0to1 acc_len [15] "logic acc_len[23:0]" +Toggle 1to0 acc_len [15] "logic acc_len[23:0]" +Toggle 0to1 acc_len [16] "logic acc_len[23:0]" +Toggle 1to0 acc_len [16] "logic acc_len[23:0]" +Toggle 0to1 acc_len [17] "logic acc_len[23:0]" +Toggle 1to0 acc_len [17] "logic acc_len[23:0]" +Toggle 0to1 acc_len [18] "logic acc_len[23:0]" +Toggle 1to0 acc_len [18] "logic acc_len[23:0]" +Toggle 0to1 acc_len [19] "logic acc_len[23:0]" +Toggle 1to0 acc_len [19] "logic acc_len[23:0]" +Toggle 0to1 acc_len [20] "logic acc_len[23:0]" +Toggle 1to0 acc_len [20] "logic acc_len[23:0]" +Toggle 0to1 acc_len [21] "logic acc_len[23:0]" +Toggle 1to0 acc_len [21] "logic acc_len[23:0]" +Toggle 0to1 acc_len [22] "logic acc_len[23:0]" +Toggle 1to0 acc_len [22] "logic acc_len[23:0]" +Toggle 0to1 acc_len [23] "logic acc_len[23:0]" +Toggle 1to0 acc_len [23] "logic acc_len[23:0]" +Toggle 0to1 acc_len [0] "logic acc_len[23:0]" +Toggle 1to0 acc_len [0] "logic acc_len[23:0]" +Toggle 0to1 acc_len [1] "logic acc_len[23:0]" +Toggle 1to0 acc_len [1] "logic acc_len[23:0]" +Toggle 0to1 acc_len [2] "logic acc_len[23:0]" +Toggle 1to0 acc_len [2] "logic acc_len[23:0]" +Toggle 0to1 acc_len [3] "logic acc_len[23:0]" +Toggle 1to0 acc_len [3] "logic acc_len[23:0]" +Toggle 0to1 i_tx_length [1] "logic i_tx_length[23:0]" +Toggle 1to0 i_tx_length [1] "logic i_tx_length[23:0]" +Toggle 0to1 i_tx_length [12] "logic i_tx_length[23:0]" +Toggle 1to0 i_tx_length [12] "logic i_tx_length[23:0]" +Toggle 0to1 i_tx_length [13] "logic i_tx_length[23:0]" +Toggle 1to0 i_tx_length [13] "logic i_tx_length[23:0]" +Toggle 0to1 i_tx_length [14] "logic i_tx_length[23:0]" +Toggle 1to0 i_tx_length [14] "logic i_tx_length[23:0]" +Toggle 0to1 i_tx_length [15] "logic i_tx_length[23:0]" +Toggle 1to0 i_tx_length [15] "logic i_tx_length[23:0]" +Toggle 0to1 i_tx_length [16] "logic i_tx_length[23:0]" +Toggle 1to0 i_tx_length [16] "logic i_tx_length[23:0]" +Toggle 0to1 i_tx_length [17] "logic i_tx_length[23:0]" +Toggle 1to0 i_tx_length [17] "logic i_tx_length[23:0]" +Toggle 0to1 i_tx_length [18] "logic i_tx_length[23:0]" +Toggle 1to0 i_tx_length [18] "logic i_tx_length[23:0]" +Toggle 0to1 i_tx_length [19] "logic i_tx_length[23:0]" +Toggle 1to0 i_tx_length [19] "logic i_tx_length[23:0]" +Toggle 0to1 i_tx_length [20] "logic i_tx_length[23:0]" +Toggle 1to0 i_tx_length [20] "logic i_tx_length[23:0]" +Toggle 0to1 i_tx_length [21] "logic i_tx_length[23:0]" +Toggle 1to0 i_tx_length [21] "logic i_tx_length[23:0]" +Toggle 0to1 i_tx_length [22] "logic i_tx_length[23:0]" +Toggle 1to0 i_tx_length [22] "logic i_tx_length[23:0]" +Toggle 0to1 i_tx_length [23] "logic i_tx_length[23:0]" +Toggle 1to0 i_tx_length [23] "logic i_tx_length[23:0]" +Toggle 0to1 i_tx_length [0] "logic i_tx_length[23:0]" +Toggle 1to0 i_tx_length [0] "logic i_tx_length[23:0]" +Toggle 0to1 tx_length_T1 [1] "logic tx_length_T1[23:0]" +Toggle 1to0 tx_length_T1 [1] "logic tx_length_T1[23:0]" +Toggle 0to1 tx_length_T1 [12] "logic tx_length_T1[23:0]" +Toggle 1to0 tx_length_T1 [12] "logic tx_length_T1[23:0]" +Toggle 0to1 tx_length_T1 [13] "logic tx_length_T1[23:0]" +Toggle 1to0 tx_length_T1 [13] "logic tx_length_T1[23:0]" +Toggle 0to1 tx_length_T1 [14] "logic tx_length_T1[23:0]" +Toggle 1to0 tx_length_T1 [14] "logic tx_length_T1[23:0]" +Toggle 0to1 tx_length_T1 [15] "logic tx_length_T1[23:0]" +Toggle 1to0 tx_length_T1 [15] "logic tx_length_T1[23:0]" +Toggle 0to1 tx_length_T1 [16] "logic tx_length_T1[23:0]" +Toggle 1to0 tx_length_T1 [16] "logic tx_length_T1[23:0]" +Toggle 0to1 tx_length_T1 [17] "logic tx_length_T1[23:0]" +Toggle 1to0 tx_length_T1 [17] "logic tx_length_T1[23:0]" +Toggle 0to1 tx_length_T1 [18] "logic tx_length_T1[23:0]" +Toggle 1to0 tx_length_T1 [18] "logic tx_length_T1[23:0]" +Toggle 0to1 tx_length_T1 [19] "logic tx_length_T1[23:0]" +Toggle 1to0 tx_length_T1 [19] "logic tx_length_T1[23:0]" +Toggle 0to1 tx_length_T1 [20] "logic tx_length_T1[23:0]" +Toggle 1to0 tx_length_T1 [20] "logic tx_length_T1[23:0]" +Toggle 0to1 tx_length_T1 [21] "logic tx_length_T1[23:0]" +Toggle 1to0 tx_length_T1 [21] "logic tx_length_T1[23:0]" +Toggle 0to1 tx_length_T1 [22] "logic tx_length_T1[23:0]" +Toggle 1to0 tx_length_T1 [22] "logic tx_length_T1[23:0]" +Toggle 0to1 tx_length_T1 [23] "logic tx_length_T1[23:0]" +Toggle 1to0 tx_length_T1 [23] "logic tx_length_T1[23:0]" +Toggle 0to1 tx_length_T1 [0] "logic tx_length_T1[23:0]" +Toggle 1to0 tx_length_T1 [0] "logic tx_length_T1[23:0]" +Toggle 0to1 tx_length_T2 [1] "logic tx_length_T2[23:0]" +Toggle 1to0 tx_length_T2 [1] "logic tx_length_T2[23:0]" +Toggle 0to1 tx_length_T2 [12] "logic tx_length_T2[23:0]" +Toggle 1to0 tx_length_T2 [12] "logic tx_length_T2[23:0]" +Toggle 0to1 tx_length_T2 [13] "logic tx_length_T2[23:0]" +Toggle 1to0 tx_length_T2 [13] "logic tx_length_T2[23:0]" +Toggle 0to1 tx_length_T2 [14] "logic tx_length_T2[23:0]" +Toggle 1to0 tx_length_T2 [14] "logic tx_length_T2[23:0]" +Toggle 0to1 tx_length_T2 [15] "logic tx_length_T2[23:0]" +Toggle 1to0 tx_length_T2 [15] "logic tx_length_T2[23:0]" +Toggle 0to1 tx_length_T2 [16] "logic tx_length_T2[23:0]" +Toggle 1to0 tx_length_T2 [16] "logic tx_length_T2[23:0]" +Toggle 0to1 tx_length_T2 [17] "logic tx_length_T2[23:0]" +Toggle 1to0 tx_length_T2 [17] "logic tx_length_T2[23:0]" +Toggle 0to1 tx_length_T2 [18] "logic tx_length_T2[23:0]" +Toggle 1to0 tx_length_T2 [18] "logic tx_length_T2[23:0]" +Toggle 0to1 tx_length_T2 [19] "logic tx_length_T2[23:0]" +Toggle 1to0 tx_length_T2 [19] "logic tx_length_T2[23:0]" +Toggle 0to1 tx_length_T2 [20] "logic tx_length_T2[23:0]" +Toggle 1to0 tx_length_T2 [20] "logic tx_length_T2[23:0]" +Toggle 0to1 tx_length_T2 [21] "logic tx_length_T2[23:0]" +Toggle 1to0 tx_length_T2 [21] "logic tx_length_T2[23:0]" +Toggle 0to1 tx_length_T2 [22] "logic tx_length_T2[23:0]" +Toggle 1to0 tx_length_T2 [22] "logic tx_length_T2[23:0]" +Toggle 0to1 tx_length_T2 [23] "logic tx_length_T2[23:0]" +Toggle 1to0 tx_length_T2 [23] "logic tx_length_T2[23:0]" +Toggle 0to1 tx_length_T2 [0] "logic tx_length_T2[23:0]" +Toggle 1to0 tx_length_T2 [0] "logic tx_length_T2[23:0]" +Toggle 0to1 tx_length_T3 [23] "logic tx_length_T3[23:0]" +Toggle 1to0 tx_length_T3 [23] "logic tx_length_T3[23:0]" +Toggle 0to1 tx_length_T3 [0] "logic tx_length_T3[23:0]" +Toggle 1to0 tx_length_T3 [0] "logic tx_length_T3[23:0]" +Toggle 0to1 tx_length_T3 [1] "logic tx_length_T3[23:0]" +Toggle 1to0 tx_length_T3 [1] "logic tx_length_T3[23:0]" +Toggle 0to1 tx_length_T3 [12] "logic tx_length_T3[23:0]" +Toggle 1to0 tx_length_T3 [12] "logic tx_length_T3[23:0]" +Toggle 0to1 tx_length_T3 [13] "logic tx_length_T3[23:0]" +Toggle 1to0 tx_length_T3 [13] "logic tx_length_T3[23:0]" +Toggle 0to1 tx_length_T3 [14] "logic tx_length_T3[23:0]" +Toggle 1to0 tx_length_T3 [14] "logic tx_length_T3[23:0]" +Toggle 0to1 tx_length_T3 [15] "logic tx_length_T3[23:0]" +Toggle 1to0 tx_length_T3 [15] "logic tx_length_T3[23:0]" +Toggle 0to1 tx_length_T3 [16] "logic tx_length_T3[23:0]" +Toggle 1to0 tx_length_T3 [16] "logic tx_length_T3[23:0]" +Toggle 0to1 tx_length_T3 [17] "logic tx_length_T3[23:0]" +Toggle 1to0 tx_length_T3 [17] "logic tx_length_T3[23:0]" +Toggle 0to1 tx_length_T3 [18] "logic tx_length_T3[23:0]" +Toggle 1to0 tx_length_T3 [18] "logic tx_length_T3[23:0]" +Toggle 0to1 tx_length_T3 [19] "logic tx_length_T3[23:0]" +Toggle 1to0 tx_length_T3 [19] "logic tx_length_T3[23:0]" +Toggle 0to1 tx_length_T3 [20] "logic tx_length_T3[23:0]" +Toggle 1to0 tx_length_T3 [20] "logic tx_length_T3[23:0]" +Toggle 0to1 tx_length_T3 [21] "logic tx_length_T3[23:0]" +Toggle 1to0 tx_length_T3 [21] "logic tx_length_T3[23:0]" +Toggle 0to1 tx_length_T3 [22] "logic tx_length_T3[23:0]" +Toggle 1to0 tx_length_T3 [22] "logic tx_length_T3[23:0]" +Toggle 0to1 i_tx_keep [31] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [31] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [0] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [0] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [1] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [1] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [2] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [2] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [3] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [3] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [4] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [4] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [5] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [5] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [6] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [6] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [7] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [7] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [8] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [8] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [9] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [9] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [10] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [10] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [11] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [11] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [12] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [12] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [13] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [13] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [14] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [14] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [15] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [15] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [16] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [16] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [17] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [17] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [18] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [18] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [19] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [19] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [20] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [20] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [21] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [21] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [22] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [22] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [23] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [23] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [24] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [24] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [25] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [25] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [26] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [26] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [27] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [27] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [28] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [28] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [29] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [29] "logic i_tx_keep[63:0]" +Toggle 0to1 i_tx_keep [30] "logic i_tx_keep[63:0]" +Toggle 1to0 i_tx_keep [30] "logic i_tx_keep[63:0]" +CHECKSUM: "2725671737 490696940" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr.rst_hs_resync +Toggle 1to0 resync_chains[0].sync_d_in "net resync_chains[0].sync_d_in" +Toggle 0to1 resync_chains[0].sync_d_in "net resync_chains[0].sync_d_in" +Toggle 1to0 resync_chains[0].sync_q_out "net resync_chains[0].sync_q_out" +Toggle 0to1 resync_chains[0].sync_q_out "net resync_chains[0].sync_q_out" +Toggle 1to0 resync_chains[5].d_in "net resync_chains[5].d_in" +Toggle 0to1 resync_chains[5].d_in "net resync_chains[5].d_in" +Toggle 1to0 resync_chains[5].sync_d_in "net resync_chains[5].sync_d_in" +Toggle 0to1 resync_chains[5].sync_d_in "net resync_chains[5].sync_d_in" +Toggle 1to0 resync_chains[5].sync_q_out "net resync_chains[5].sync_q_out" +Toggle 0to1 resync_chains[5].sync_q_out "net resync_chains[5].sync_q_out" +Toggle 1to0 resync_chains[6].d_in "net resync_chains[6].d_in" +Toggle 0to1 resync_chains[6].d_in "net resync_chains[6].d_in" +Toggle 1to0 resync_chains[6].sync_d_in "net resync_chains[6].sync_d_in" +Toggle 0to1 resync_chains[6].sync_d_in "net resync_chains[6].sync_d_in" +Toggle 1to0 resync_chains[6].sync_q_out "net resync_chains[6].sync_q_out" +Toggle 0to1 resync_chains[6].sync_q_out "net resync_chains[6].sync_q_out" +Toggle 1to0 resync_chains[9].d_in "net resync_chains[9].d_in" +Toggle 0to1 resync_chains[9].d_in "net resync_chains[9].d_in" +Toggle 1to0 resync_chains[9].sync_d_in "net resync_chains[9].sync_d_in" +Toggle 0to1 resync_chains[9].sync_d_in "net resync_chains[9].sync_d_in" +Toggle 1to0 resync_chains[9].sync_q_out "net resync_chains[9].sync_q_out" +Toggle 0to1 resync_chains[9].sync_q_out "net resync_chains[9].sync_q_out" +Toggle 1to0 resync_chains[10].d_in "net resync_chains[10].d_in" +Toggle 0to1 resync_chains[10].d_in "net resync_chains[10].d_in" +Toggle 1to0 resync_chains[10].sync_d_in "net resync_chains[10].sync_d_in" +Toggle 0to1 resync_chains[10].sync_d_in "net resync_chains[10].sync_d_in" +Toggle 1to0 resync_chains[10].sync_q_out "net resync_chains[10].sync_q_out" +Toggle 0to1 resync_chains[10].sync_q_out "net resync_chains[10].sync_q_out" +Toggle 1to0 resync_chains[12].d_in "net resync_chains[12].d_in" +Toggle 0to1 resync_chains[12].d_in "net resync_chains[12].d_in" +Toggle 1to0 resync_chains[12].sync_d_in "net resync_chains[12].sync_d_in" +Toggle 0to1 resync_chains[12].sync_d_in "net resync_chains[12].sync_d_in" +Toggle 1to0 resync_chains[12].sync_q_out "net resync_chains[12].sync_q_out" +Toggle 0to1 resync_chains[12].sync_q_out "net resync_chains[12].sync_q_out" +Toggle 1to0 resync_chains[15].d_in "net resync_chains[15].d_in" +Toggle 0to1 resync_chains[15].d_in "net resync_chains[15].d_in" +Toggle 1to0 resync_chains[15].sync_d_in "net resync_chains[15].sync_d_in" +Toggle 0to1 resync_chains[15].sync_d_in "net resync_chains[15].sync_d_in" +Toggle 1to0 resync_chains[15].sync_q_out "net resync_chains[15].sync_q_out" +Toggle 0to1 resync_chains[15].sync_q_out "net resync_chains[15].sync_q_out" +Toggle 1to0 resync_chains[0].d_in "net resync_chains[0].d_in" +Toggle 0to1 resync_chains[0].d_in "net resync_chains[0].d_in" +CHECKSUM: "1259019545 702362531" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.port_traffic_control_inst.axi_tx_stage +Condition 1 "4206754987" "(((~genblk1.s_tready_pre)) && genblk1.s_tready_reg) 1 -1" (1 "01") +CHECKSUM: "2334324724 2275284531" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr +Toggle 0to1 error_vector_csr.mmio_rd_while_rst "logic error_vector_csr.mmio_rd_while_rst" +Toggle 1to0 error_vector_csr.mmio_rd_while_rst "logic error_vector_csr.mmio_rd_while_rst" +Toggle 0to1 i_error_vector.unaligned_addr "logic i_error_vector.unaligned_addr" +Toggle 1to0 i_error_vector.unaligned_addr "logic i_error_vector.unaligned_addr" +Toggle 0to1 i_error_vector.tx_valid_violation "logic i_error_vector.tx_valid_violation" +Toggle 1to0 i_error_vector.tx_valid_violation "logic i_error_vector.tx_valid_violation" +Toggle 0to1 i_error_vector.tx_req_counter_oflow "logic i_error_vector.tx_req_counter_oflow" +Toggle 1to0 i_error_vector.tx_req_counter_oflow "logic i_error_vector.tx_req_counter_oflow" +Toggle 0to1 i_error_vector.tag_occupied "logic i_error_vector.tag_occupied" +Toggle 1to0 i_error_vector.tag_occupied "logic i_error_vector.tag_occupied" +Toggle 0to1 i_error_vector.mmio_wr_while_rst "logic i_error_vector.mmio_wr_while_rst" +Toggle 1to0 i_error_vector.mmio_wr_while_rst "logic i_error_vector.mmio_wr_while_rst" +Toggle 0to1 i_error_vector.mmio_rd_while_rst "logic i_error_vector.mmio_rd_while_rst" +Toggle 1to0 i_error_vector.mmio_rd_while_rst "logic i_error_vector.mmio_rd_while_rst" +Toggle 0to1 error_vector_r6.unaligned_addr "logic error_vector_r6.unaligned_addr" +Toggle 1to0 error_vector_r6.unaligned_addr "logic error_vector_r6.unaligned_addr" +Toggle 0to1 error_vector_r6.tx_valid_violation "logic error_vector_r6.tx_valid_violation" +Toggle 1to0 error_vector_r6.tx_valid_violation "logic error_vector_r6.tx_valid_violation" +Toggle 0to1 error_vector_r6.tx_req_counter_oflow "logic error_vector_r6.tx_req_counter_oflow" +Toggle 1to0 error_vector_r6.tx_req_counter_oflow "logic error_vector_r6.tx_req_counter_oflow" +Toggle 0to1 error_vector_r6.tag_occupied "logic error_vector_r6.tag_occupied" +Toggle 1to0 error_vector_r6.tag_occupied "logic error_vector_r6.tag_occupied" +Toggle 0to1 error_vector_r6.mmio_wr_while_rst "logic error_vector_r6.mmio_wr_while_rst" +Toggle 1to0 error_vector_r6.mmio_wr_while_rst "logic error_vector_r6.mmio_wr_while_rst" +Toggle 0to1 error_vector_r6.mmio_rd_while_rst "logic error_vector_r6.mmio_rd_while_rst" +Toggle 1to0 error_vector_r6.mmio_rd_while_rst "logic error_vector_r6.mmio_rd_while_rst" +Toggle 0to1 error_vector_r5.unaligned_addr "logic error_vector_r5.unaligned_addr" +Toggle 1to0 error_vector_r5.unaligned_addr "logic error_vector_r5.unaligned_addr" +Toggle 0to1 error_vector_r5.tx_valid_violation "logic error_vector_r5.tx_valid_violation" +Toggle 1to0 error_vector_r5.tx_valid_violation "logic error_vector_r5.tx_valid_violation" +Toggle 0to1 error_vector_r5.tx_req_counter_oflow "logic error_vector_r5.tx_req_counter_oflow" +Toggle 1to0 error_vector_r5.tx_req_counter_oflow "logic error_vector_r5.tx_req_counter_oflow" +Toggle 0to1 error_vector_r5.tag_occupied "logic error_vector_r5.tag_occupied" +Toggle 1to0 error_vector_r5.tag_occupied "logic error_vector_r5.tag_occupied" +Toggle 0to1 error_vector_r5.mmio_wr_while_rst "logic error_vector_r5.mmio_wr_while_rst" +Toggle 1to0 error_vector_r5.mmio_wr_while_rst "logic error_vector_r5.mmio_wr_while_rst" +Toggle 0to1 error_vector_r5.mmio_rd_while_rst "logic error_vector_r5.mmio_rd_while_rst" +Toggle 1to0 error_vector_r5.mmio_rd_while_rst "logic error_vector_r5.mmio_rd_while_rst" +Toggle 0to1 error_vector_r4.unaligned_addr "logic error_vector_r4.unaligned_addr" +Toggle 1to0 error_vector_r4.unaligned_addr "logic error_vector_r4.unaligned_addr" +Toggle 0to1 error_vector_r4.tx_valid_violation "logic error_vector_r4.tx_valid_violation" +Toggle 1to0 error_vector_r4.tx_valid_violation "logic error_vector_r4.tx_valid_violation" +Toggle 0to1 error_vector_r4.tx_req_counter_oflow "logic error_vector_r4.tx_req_counter_oflow" +Toggle 1to0 error_vector_r4.tx_req_counter_oflow "logic error_vector_r4.tx_req_counter_oflow" +Toggle 0to1 error_vector_r4.tag_occupied "logic error_vector_r4.tag_occupied" +Toggle 1to0 error_vector_r4.tag_occupied "logic error_vector_r4.tag_occupied" +Toggle 0to1 error_vector_r4.mmio_wr_while_rst "logic error_vector_r4.mmio_wr_while_rst" +Toggle 1to0 error_vector_r4.mmio_wr_while_rst "logic error_vector_r4.mmio_wr_while_rst" +Toggle 0to1 error_vector_r4.mmio_rd_while_rst "logic error_vector_r4.mmio_rd_while_rst" +Toggle 1to0 error_vector_r4.mmio_rd_while_rst "logic error_vector_r4.mmio_rd_while_rst" +Toggle 0to1 error_vector_r3.unaligned_addr "logic error_vector_r3.unaligned_addr" +Toggle 1to0 error_vector_r3.unaligned_addr "logic error_vector_r3.unaligned_addr" +Toggle 0to1 error_vector_r3.tx_valid_violation "logic error_vector_r3.tx_valid_violation" +Toggle 1to0 error_vector_r3.tx_valid_violation "logic error_vector_r3.tx_valid_violation" +Toggle 0to1 error_vector_r3.tx_req_counter_oflow "logic error_vector_r3.tx_req_counter_oflow" +Toggle 1to0 error_vector_r3.tx_req_counter_oflow "logic error_vector_r3.tx_req_counter_oflow" +Toggle 0to1 error_vector_r3.tag_occupied "logic error_vector_r3.tag_occupied" +Toggle 1to0 error_vector_r3.tag_occupied "logic error_vector_r3.tag_occupied" +Toggle 0to1 error_vector_r3.mmio_wr_while_rst "logic error_vector_r3.mmio_wr_while_rst" +Toggle 1to0 error_vector_r3.mmio_wr_while_rst "logic error_vector_r3.mmio_wr_while_rst" +Toggle 0to1 error_vector_r3.mmio_rd_while_rst "logic error_vector_r3.mmio_rd_while_rst" +Toggle 1to0 error_vector_r3.mmio_rd_while_rst "logic error_vector_r3.mmio_rd_while_rst" +Toggle 0to1 error_vector_r2.unaligned_addr "logic error_vector_r2.unaligned_addr" +Toggle 1to0 error_vector_r2.unaligned_addr "logic error_vector_r2.unaligned_addr" +Toggle 0to1 error_vector_r2.tx_valid_violation "logic error_vector_r2.tx_valid_violation" +Toggle 1to0 error_vector_r2.tx_valid_violation "logic error_vector_r2.tx_valid_violation" +Toggle 0to1 error_vector_r2.tx_req_counter_oflow "logic error_vector_r2.tx_req_counter_oflow" +Toggle 1to0 error_vector_r2.tx_req_counter_oflow "logic error_vector_r2.tx_req_counter_oflow" +Toggle 0to1 error_vector_r2.tag_occupied "logic error_vector_r2.tag_occupied" +Toggle 1to0 error_vector_r2.tag_occupied "logic error_vector_r2.tag_occupied" +Toggle 0to1 error_vector_r2.mmio_wr_while_rst "logic error_vector_r2.mmio_wr_while_rst" +Toggle 1to0 error_vector_r2.mmio_wr_while_rst "logic error_vector_r2.mmio_wr_while_rst" +Toggle 0to1 error_vector_r2.mmio_rd_while_rst "logic error_vector_r2.mmio_rd_while_rst" +Toggle 1to0 error_vector_r2.mmio_rd_while_rst "logic error_vector_r2.mmio_rd_while_rst" +Toggle 0to1 error_vector_or.unaligned_addr "logic error_vector_or.unaligned_addr" +Toggle 1to0 error_vector_or.unaligned_addr "logic error_vector_or.unaligned_addr" +Toggle 0to1 error_vector_or.tx_valid_violation "logic error_vector_or.tx_valid_violation" +Toggle 1to0 error_vector_or.tx_valid_violation "logic error_vector_or.tx_valid_violation" +Toggle 0to1 error_vector_or.tx_req_counter_oflow "logic error_vector_or.tx_req_counter_oflow" +Toggle 1to0 error_vector_or.tx_req_counter_oflow "logic error_vector_or.tx_req_counter_oflow" +Toggle 0to1 error_vector_or.tag_occupied "logic error_vector_or.tag_occupied" +Toggle 1to0 error_vector_or.tag_occupied "logic error_vector_or.tag_occupied" +Toggle 0to1 error_vector_or.mmio_wr_while_rst "logic error_vector_or.mmio_wr_while_rst" +Toggle 1to0 error_vector_or.mmio_wr_while_rst "logic error_vector_or.mmio_wr_while_rst" +Toggle 0to1 error_vector_or.mmio_rd_while_rst "logic error_vector_or.mmio_rd_while_rst" +Toggle 1to0 error_vector_or.mmio_rd_while_rst "logic error_vector_or.mmio_rd_while_rst" +Toggle 0to1 error_vector_csr.unaligned_addr "logic error_vector_csr.unaligned_addr" +Toggle 1to0 error_vector_csr.unaligned_addr "logic error_vector_csr.unaligned_addr" +Toggle 0to1 error_vector_csr.tx_valid_violation "logic error_vector_csr.tx_valid_violation" +Toggle 1to0 error_vector_csr.tx_valid_violation "logic error_vector_csr.tx_valid_violation" +Toggle 0to1 error_vector_csr.tx_req_counter_oflow "logic error_vector_csr.tx_req_counter_oflow" +Toggle 1to0 error_vector_csr.tx_req_counter_oflow "logic error_vector_csr.tx_req_counter_oflow" +Toggle 0to1 error_vector_csr.tag_occupied "logic error_vector_csr.tag_occupied" +Toggle 1to0 error_vector_csr.tag_occupied "logic error_vector_csr.tag_occupied" +Toggle 0to1 error_vector_csr.mmio_wr_while_rst "logic error_vector_csr.mmio_wr_while_rst" +Toggle 1to0 error_vector_csr.mmio_wr_while_rst "logic error_vector_csr.mmio_wr_while_rst" +Toggle 0to1 blockingtraffic "logic blockingtraffic" +Toggle 1to0 blockingtraffic "logic blockingtraffic" +Toggle afu_intf_dfh_wire "net afu_intf_dfh_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [63] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [63] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [0] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [0] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [5] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [5] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [6] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [6] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [9] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [9] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [10] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [10] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [12] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [12] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [15] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [15] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [16] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [16] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [17] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [17] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [18] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [18] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [19] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [19] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [20] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [20] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [21] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [21] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [22] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [22] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [23] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [23] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [24] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [24] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [25] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [25] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [26] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [26] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [27] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [27] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [28] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [28] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [29] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [29] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [30] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [30] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [31] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [31] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [32] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [32] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [33] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [33] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [34] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [34] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [35] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [35] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [36] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [36] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [37] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [37] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [38] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [38] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [39] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [39] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [40] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [40] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [41] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [41] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [42] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [42] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [43] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [43] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [44] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [44] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [45] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [45] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [46] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [46] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [47] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [47] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [48] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [48] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [49] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [49] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [50] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [50] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [51] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [51] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [52] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [52] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [53] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [53] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [54] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [54] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [55] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [55] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [56] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [56] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [57] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [57] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [58] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [58] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [59] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [59] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [60] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [60] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [61] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [61] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_error_wire [62] "net afu_intf_error_wire[63:0]" +Toggle 1to0 afu_intf_error_wire [62] "net afu_intf_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [63] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [63] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [0] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [0] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [5] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [5] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [6] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [6] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [9] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [9] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [10] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [10] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [12] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [12] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [15] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [15] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [16] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [16] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [17] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [17] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [18] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [18] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [19] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [19] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [20] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [20] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [21] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [21] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [22] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [22] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [23] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [23] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [24] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [24] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [25] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [25] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [26] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [26] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [27] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [27] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [28] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [28] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [29] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [29] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [30] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [30] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [31] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [31] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [32] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [32] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [33] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [33] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [34] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [34] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [35] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [35] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [36] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [36] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [37] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [37] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [38] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [38] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [39] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [39] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [40] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [40] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [41] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [41] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [42] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [42] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [43] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [43] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [44] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [44] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [45] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [45] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [46] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [46] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [47] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [47] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [48] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [48] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [49] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [49] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [50] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [50] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [51] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [51] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [52] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [52] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [53] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [53] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [54] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [54] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [55] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [55] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [56] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [56] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [57] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [57] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [58] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [58] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [59] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [59] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [60] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [60] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [61] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [61] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 afu_intf_first_error_wire [62] "net afu_intf_first_error_wire[63:0]" +Toggle 1to0 afu_intf_first_error_wire [62] "net afu_intf_first_error_wire[63:0]" +Toggle 0to1 blocking_traffic_default "net blocking_traffic_default" +Toggle 1to0 blocking_traffic_default "net blocking_traffic_default" +Toggle 0to1 blocking_traffic_reg "net blocking_traffic_reg" +Toggle 1to0 blocking_traffic_reg "net blocking_traffic_reg" +Toggle 0to1 eol_default "net eol_default" +Toggle 1to0 eol_default "net eol_default" +Toggle 1to0 pwr_good_csr_clk_n "net pwr_good_csr_clk_n" +Toggle 0to1 o_clear_errors "logic o_clear_errors" +Toggle 1to0 o_clear_errors "logic o_clear_errors" +Toggle next_dfh_byte_offset_reg "net next_dfh_byte_offset_reg[23:0]" +Toggle next_dfh_byte_offset_default "net next_dfh_byte_offset_default[23:0]" +Toggle 0to1 mmio_timeout_ferr_default "net mmio_timeout_ferr_default" +Toggle 1to0 mmio_timeout_ferr_default "net mmio_timeout_ferr_default" +Toggle 0to1 mmio_timeout_err_default "net mmio_timeout_err_default" +Toggle 1to0 mmio_timeout_err_default "net mmio_timeout_err_default" +Toggle 0to1 mmio_insufficient_data_ferr_default "net mmio_insufficient_data_ferr_default" +Toggle 1to0 mmio_insufficient_data_ferr_default "net mmio_insufficient_data_ferr_default" +Toggle 0to1 mmio_insufficient_data_err_default "net mmio_insufficient_data_err_default" +Toggle 1to0 mmio_insufficient_data_err_default "net mmio_insufficient_data_err_default" +Toggle 0to1 mmio_data_payload_overrun_ferr_default "net mmio_data_payload_overrun_ferr_default" +Toggle 1to0 mmio_data_payload_overrun_ferr_default "net mmio_data_payload_overrun_ferr_default" +Toggle 0to1 mmio_data_payload_overrun_err_default "net mmio_data_payload_overrun_err_default" +Toggle 1to0 mmio_data_payload_overrun_err_default "net mmio_data_payload_overrun_err_default" +Toggle 0to1 max_tag_ferr_default "net max_tag_ferr_default" +Toggle 1to0 max_tag_ferr_default "net max_tag_ferr_default" +Toggle 0to1 max_tag_err_default "net max_tag_err_default" +Toggle 1to0 max_tag_err_default "net max_tag_err_default" +Toggle 0to1 max_read_req_size_ferr_reg "reg max_read_req_size_ferr_reg" +Toggle 1to0 max_read_req_size_ferr_reg "reg max_read_req_size_ferr_reg" +Toggle 0to1 max_read_req_size_ferr_default "net max_read_req_size_ferr_default" +Toggle 1to0 max_read_req_size_ferr_default "net max_read_req_size_ferr_default" +Toggle 0to1 max_read_req_size_err_reg "reg max_read_req_size_err_reg" +Toggle 1to0 max_read_req_size_err_reg "reg max_read_req_size_err_reg" +Toggle 0to1 max_read_req_size_err_default "net max_read_req_size_err_default" +Toggle 1to0 max_read_req_size_err_default "net max_read_req_size_err_default" +Toggle 0to1 max_read_req_size "logic max_read_req_size" +Toggle 1to0 max_read_req_size "logic max_read_req_size" +Toggle 0to1 max_payload_ferr_default "net max_payload_ferr_default" +Toggle 1to0 max_payload_ferr_default "net max_payload_ferr_default" +Toggle 0to1 max_payload_err_default "net max_payload_err_default" +Toggle 1to0 max_payload_err_default "net max_payload_err_default" +Toggle 0to1 malformed_tlp_ferr_default "net malformed_tlp_ferr_default" +Toggle 1to0 malformed_tlp_ferr_default "net malformed_tlp_ferr_default" +Toggle 0to1 malformed_tlp_err_default "net malformed_tlp_err_default" +Toggle 1to0 malformed_tlp_err_default "net malformed_tlp_err_default" +Toggle 0to1 i_error_vector.max_read_req_size "logic i_error_vector.max_read_req_size" +Toggle 1to0 i_error_vector.max_read_req_size "logic i_error_vector.max_read_req_size" +Toggle feature_type_reg "net feature_type_reg[3:0]" +Toggle feature_type_default "net feature_type_default[3:0]" +Toggle feature_rev_default "net feature_rev_default[3:0]" +Toggle feature_rev_reg "net feature_rev_reg[3:0]" +Toggle feature_id_reg "net feature_id_reg[11:0]" +Toggle feature_id_default "net feature_id_default[11:0]" +Toggle 0to1 error_vector_r6.max_read_req_size "logic error_vector_r6.max_read_req_size" +Toggle 1to0 error_vector_r6.max_read_req_size "logic error_vector_r6.max_read_req_size" +Toggle 0to1 error_vector_r5.max_read_req_size "logic error_vector_r5.max_read_req_size" +Toggle 1to0 error_vector_r5.max_read_req_size "logic error_vector_r5.max_read_req_size" +Toggle 0to1 error_vector_r4.max_read_req_size "logic error_vector_r4.max_read_req_size" +Toggle 1to0 error_vector_r4.max_read_req_size "logic error_vector_r4.max_read_req_size" +Toggle 0to1 error_vector_r3.max_read_req_size "logic error_vector_r3.max_read_req_size" +Toggle 1to0 error_vector_r3.max_read_req_size "logic error_vector_r3.max_read_req_size" +Toggle 0to1 error_vector_r2.max_read_req_size "logic error_vector_r2.max_read_req_size" +Toggle 1to0 error_vector_r2.max_read_req_size "logic error_vector_r2.max_read_req_size" +Toggle 0to1 error_vector_or.max_read_req_size "logic error_vector_or.max_read_req_size" +Toggle 1to0 error_vector_or.max_read_req_size "logic error_vector_or.max_read_req_size" +Toggle 0to1 error_vector_csr.max_read_req_size "logic error_vector_csr.max_read_req_size" +Toggle 1to0 error_vector_csr.max_read_req_size "logic error_vector_csr.max_read_req_size" +Toggle 0to1 eol_reg "net eol_reg" +Toggle 1to0 eol_reg "net eol_reg" +Toggle 1to0 rst_n_csr "net rst_n_csr" +Toggle 0to1 vf_flr_access_ferr_default "net vf_flr_access_ferr_default" +Toggle 1to0 vf_flr_access_ferr_default "net vf_flr_access_ferr_default" +Toggle 0to1 vf_flr_access_ferr_reg "net vf_flr_access_ferr_reg" +Toggle 1to0 vf_flr_access_ferr_reg "net vf_flr_access_ferr_reg" +Toggle vf_num_default "net vf_num_default[10:0]" +Toggle vf_num_ferr_default "net vf_num_ferr_default[10:0]" +Toggle vf_num_reg "reg vf_num_reg[10:0]" +Toggle vf_num_ferr_reg "reg vf_num_ferr_reg[10:0]" +Toggle vf_num "logic vf_num[10:0]" +Toggle 0to1 vf_flr_access_reg "net vf_flr_access_reg" +Toggle 1to0 vf_flr_access_reg "net vf_flr_access_reg" +Toggle 0to1 vf_flr_access_default "net vf_flr_access_default" +Toggle 1to0 vf_flr_access_default "net vf_flr_access_default" +Toggle 0to1 unexp_mmio_rsp_ferr_default "net unexp_mmio_rsp_ferr_default" +Toggle 1to0 unexp_mmio_rsp_ferr_default "net unexp_mmio_rsp_ferr_default" +Toggle 0to1 unexp_mmio_rsp_err_default "net unexp_mmio_rsp_err_default" +Toggle 1to0 unexp_mmio_rsp_err_default "net unexp_mmio_rsp_err_default" +Toggle 0to1 tx_mwr_insufficient_data_ferr_default "net tx_mwr_insufficient_data_ferr_default" +Toggle 1to0 tx_mwr_insufficient_data_ferr_default "net tx_mwr_insufficient_data_ferr_default" +Toggle 0to1 tx_mwr_insufficient_data_err_default "net tx_mwr_insufficient_data_err_default" +Toggle 1to0 tx_mwr_insufficient_data_err_default "net tx_mwr_insufficient_data_err_default" +Toggle 0to1 tx_mwr_data_payload_overrun_ferr_default "net tx_mwr_data_payload_overrun_ferr_default" +Toggle 1to0 tx_mwr_data_payload_overrun_ferr_default "net tx_mwr_data_payload_overrun_ferr_default" +Toggle 0to1 tx_mwr_data_payload_overrun_err_default "net tx_mwr_data_payload_overrun_err_default" +Toggle 1to0 tx_mwr_data_payload_overrun_err_default "net tx_mwr_data_payload_overrun_err_default" +Toggle 0to1 targeting_clk1_domain_register_r2 "reg targeting_clk1_domain_register_r2" +Toggle 1to0 targeting_clk1_domain_register_r2 "reg targeting_clk1_domain_register_r2" +Toggle 0to1 targeting_clk0_domain_register_r2 "reg targeting_clk0_domain_register_r2" +Toggle 1to0 targeting_clk0_domain_register_r2 "reg targeting_clk0_domain_register_r2" +Toggle scratchpad_default "net scratchpad_default[63:0]" +CHECKSUM: "2005438484 3741922867" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a +ANNOTATION: "vcs_gen_start:i=0:vcs_gen_end" +Block 61 "620713089" "$fwrite(log_fd, \"From_PORT%0d: %s\n\", 0, pcie_ss_pkg::func_pcie_ss_flit_to_string(N_sop[0], fn2mx_tx_port[0].tlast, pcie_ss_hdr_pkg::func_hdr_is_pu_mode(fn2mx_tx_port[0].tuser_vendor), fn2mx_tx_port[0].tdata, fn2mx_tx_port[0].tkeep));" +ANNOTATION: "vcs_gen_start:i=3:vcs_gen_end" +Block 82 "3452622318" "$fwrite(log_fd, \" To_PORT%0d: %s\n\", 3, pcie_ss_pkg::func_pcie_ss_flit_to_string(N_out_sop[3], mx2fn_rx_port[3].tlast, pcie_ss_hdr_pkg::func_hdr_is_pu_mode(mx2fn_rx_port[3].tuser_vendor), mx2fn_rx_port[3].tdata, mx2fn_rx_port[3].tkeep));" +ANNOTATION: "vcs_gen_start:i=2:vcs_gen_end" +Block 76 "2973380689" "$fwrite(log_fd, \" To_PORT%0d: %s\n\", 2, pcie_ss_pkg::func_pcie_ss_flit_to_string(N_out_sop[2], mx2fn_rx_port[2].tlast, pcie_ss_hdr_pkg::func_hdr_is_pu_mode(mx2fn_rx_port[2].tuser_vendor), mx2fn_rx_port[2].tdata, mx2fn_rx_port[2].tkeep));" +ANNOTATION: "vcs_gen_start:i=1:vcs_gen_end" +Block 70 "1548701152" "$fwrite(log_fd, \" To_PORT%0d: %s\n\", 1, pcie_ss_pkg::func_pcie_ss_flit_to_string(N_out_sop[1], mx2fn_rx_port[1].tlast, pcie_ss_hdr_pkg::func_hdr_is_pu_mode(mx2fn_rx_port[1].tuser_vendor), mx2fn_rx_port[1].tdata, mx2fn_rx_port[1].tkeep));" +ANNOTATION: "vcs_gen_start:i=0:vcs_gen_end" +Block 64 "549431391" "$fwrite(log_fd, \" To_PORT%0d: %s\n\", 0, pcie_ss_pkg::func_pcie_ss_flit_to_string(N_out_sop[0], mx2fn_rx_port[0].tlast, pcie_ss_hdr_pkg::func_hdr_is_pu_mode(mx2fn_rx_port[0].tuser_vendor), mx2fn_rx_port[0].tdata, mx2fn_rx_port[0].tkeep));" +ANNOTATION: "vcs_gen_start:i=3:vcs_gen_end" +Block 79 "3944199491" "$fwrite(log_fd, \"From_PORT%0d: %s\n\", 3, pcie_ss_pkg::func_pcie_ss_flit_to_string(N_sop[3], fn2mx_tx_port[3].tlast, pcie_ss_hdr_pkg::func_hdr_is_pu_mode(fn2mx_tx_port[3].tuser_vendor), fn2mx_tx_port[3].tdata, fn2mx_tx_port[3].tkeep));" +ANNOTATION: "vcs_gen_start:i=2:vcs_gen_end" +Block 73 "2379338548" "$fwrite(log_fd, \"From_PORT%0d: %s\n\", 2, pcie_ss_pkg::func_pcie_ss_flit_to_string(N_sop[2], fn2mx_tx_port[2].tlast, pcie_ss_hdr_pkg::func_hdr_is_pu_mode(fn2mx_tx_port[2].tuser_vendor), fn2mx_tx_port[2].tdata, fn2mx_tx_port[2].tkeep));" +ANNOTATION: "vcs_gen_start:i=1:vcs_gen_end" +Block 67 "1111044854" "$fwrite(log_fd, \"From_PORT%0d: %s\n\", 1, pcie_ss_pkg::func_pcie_ss_flit_to_string(N_sop[1], fn2mx_tx_port[1].tlast, pcie_ss_hdr_pkg::func_hdr_is_pu_mode(fn2mx_tx_port[1].tuser_vendor), fn2mx_tx_port[1].tdata, fn2mx_tx_port[1].tkeep));" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.port_traffic_control_inst.tx_fifo_st +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.port_traffic_control_inst.tx_st +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.tx_filter_if +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.tx_filter_mmio_if +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.tx_port_control_if +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "1988388719 2251038728" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr +Toggle 0to1 csr_raddr [0:0]"logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [0:0]"logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [1:1]"logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [1:1]"logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [2:2]"logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [2:2]"logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [6:6]"logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [6:6]"logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [7:7]"logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [7:7]"logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [8:8]"logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [8:8]"logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [9:9]"logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [9:9]"logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [10:10]"logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [10:10]"logic csr_raddr[19:0]" +Toggle 0to1 csr_raddr [11:11]"logic csr_raddr[19:0]" +Toggle 1to0 csr_raddr [11:11]"logic csr_raddr[19:0]" +Toggle 0to1 csr_waddr [0:0]"logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [0:0]"logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [1:1]"logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [1:1]"logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [2:2]"logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [2:2]"logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [6:6]"logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [6:6]"logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [7:7]"logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [7:7]"logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [8:8]"logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [8:8]"logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [9:9]"logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [9:9]"logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [10:10]"logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [10:10]"logic csr_waddr[19:0]" +Toggle 0to1 csr_waddr [11:11]"logic csr_waddr[19:0]" +Toggle 1to0 csr_waddr [11:11]"logic csr_waddr[19:0]" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.port_traffic_control_inst.tx_fifo_st +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.port_traffic_control_inst.tx_st +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.tx_filter_if +ANNOTATION: " Clks and resets are tied to 0 " +Assert assert_tkeep_undef_when_tvalid_high "assertion" +ANNOTATION: " Clks and resets are tied to 0 " +Assert assert_tvalid_undef_when_not_in_reset "assertion" +ANNOTATION: " Clks and resets are tied to 0 " +Assert assert_tvalid_tready_handshake "assertion" +ANNOTATION: " Clks and resets are tied to 0 " +Assert assert_tuser_undef_when_tvalid_high "assertion" +ANNOTATION: " Clks and resets are tied to 0 " +Assert assert_tready_undef_when_not_in_reset "assertion" +ANNOTATION: " Clks and resets are tied to 0 " +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.tx_filter_mmio_if +ANNOTATION: " Clks and resets are tied to 0 " +Assert assert_tkeep_undef_when_tvalid_high "assertion" +ANNOTATION: " Clks and resets are tied to 0 " +Assert assert_tvalid_undef_when_not_in_reset "assertion" +ANNOTATION: " Clks and resets are tied to 0 " +Assert assert_tvalid_tready_handshake "assertion" +ANNOTATION: " Clks and resets are tied to 0 " +Assert assert_tuser_undef_when_tvalid_high "assertion" +ANNOTATION: " Clks and resets are tied to 0 " +Assert assert_tready_undef_when_not_in_reset "assertion" +ANNOTATION: " Clks and resets are tied to 0 " +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.tx_port_control_if +ANNOTATION: " Clks and resets are tied to 0 " +Assert assert_tkeep_undef_when_tvalid_high "assertion" +ANNOTATION: " Clks and resets are tied to 0 " +Assert assert_tvalid_undef_when_not_in_reset "assertion" +ANNOTATION: " Clks and resets are tied to 0 " +Assert assert_tvalid_tready_handshake "assertion" +ANNOTATION: " Clks and resets are tied to 0 " +Assert assert_tuser_undef_when_tvalid_high "assertion" +ANNOTATION: " Clks and resets are tied to 0 " +Assert assert_tready_undef_when_not_in_reset "assertion" +ANNOTATION: " Clks and resets are tied to 0 " +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "1988388719 1464101043" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr +Toggle vf_num_csr "logic vf_num_csr[10:0]" +Toggle 0to1 range_valid "logic range_valid" +Toggle 0to1 csr_raddr [19:19]"logic csr_raddr[19:0]" +Toggle 0to1 csr_waddr [19:19]"logic csr_waddr[19:0]" +Toggle 0to1 csr_raddr_reg [19:19]"logic csr_raddr_reg[19:0]" +Toggle 0to1 first_error_capture [0:0]"logic first_error_capture[63:0]" +Toggle 0to1 port_error_update [63:63]"logic port_error_update[63:0]" +CHECKSUM: "1988388719 1902299370" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr +Condition 1 "1150059955" "((csr_raddr[(CSR_ADDR_WIDTH - 1):3] < CSR_NUM_REG) ? 1'b1 : 1'b0) 1 -1" (1 "0") +Condition 2 "3923712595" "(csr_read_reg && range_valid) 1 -1" (2 "10") +CHECKSUM: "1988388719 2251038728" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.protocol_checker_csr +Branch 2 "1696262920" "(csr_raddr[(CSR_ADDR_WIDTH - 1):3] < CSR_NUM_REG)" (1) "(csr_raddr[(CSR_ADDR_WIDTH - 1):3] < CSR_NUM_REG) 0" +Branch 3 "2841476710" "(csr_read_reg && range_valid)" (0) "(csr_read_reg && range_valid) 1,1,1" diff --git a/verification/coverage/axis_axil_bridge.el b/verification/coverage/axis_axil_bridge.el new file mode 100644 index 0000000..822e2f8 --- /dev/null +++ b/verification/coverage/axis_axil_bridge.el @@ -0,0 +1,119 @@ +//================================================== +// This file contains the Excluded objects +// Generated By User: ppawar2x +// Format Version: 2 +// Date: Fri Apr 8 05:50:17 2022 +// ExclMode: default +//================================================== +CHECKSUM: "2140578723 1035001113" +INSTANCE: tb_top.DUT.afu_top.axis_axil_bridge.axis_tx_msix_bridge +Toggle intr_hdr.rsvd2 "logic intr_hdr.rsvd2[31:0]" +Toggle intr_hdr.rsvd3 "logic intr_hdr.rsvd3[6:0]" +Toggle intr_hdr.rsvd4 "logic intr_hdr.rsvd4[3:0]" +Toggle intr_hdr.rsvd5 "logic intr_hdr.rsvd5[1:0]" +Toggle intr_hdr.rsvd6 "logic intr_hdr.rsvd6[31:0]" +Toggle intr_hdr.rsvd7 "logic intr_hdr.rsvd7[15:0]" +Toggle intr_hdr.rsvd8 "logic intr_hdr.rsvd8[31:0]" +Toggle intr_hdr.rsvd9 "logic intr_hdr.rsvd9[23:0]" +Toggle intr_hdr.rsvd1 "logic intr_hdr.rsvd1[31:0]" +CHECKSUM: "1768182563 3337303171" +INSTANCE: tb_top.DUT.afu_top.axis_axil_bridge.axis_tx_mmio_bridge +Toggle cpl_hdr.rsvd2 "logic cpl_hdr.rsvd2[3:0]" +Toggle cpl_hdr.rsvd3 "logic cpl_hdr.rsvd3[1:0]" +Toggle cpl_hdr.rsvd4 "logic cpl_hdr.rsvd4[31:0]" +Toggle 1to0 cpl_hdr.rsvd5 "logic cpl_hdr.rsvd5" +Toggle 0to1 cpl_hdr.rsvd5 "logic cpl_hdr.rsvd5" +Toggle cpl_hdr.rsvd1 "logic cpl_hdr.rsvd1[6:0]" +Toggle 1to0 cpl_hdr.attr.EP "logic cpl_hdr.attr.EP" +Toggle 0to1 cpl_hdr.attr.EP "logic cpl_hdr.attr.EP" +Toggle 1to0 cpl_hdr.attr.LN "logic cpl_hdr.attr.LN" +Toggle 0to1 cpl_hdr.attr.LN "logic cpl_hdr.attr.LN" +Toggle 1to0 cpl_hdr.attr.TD "logic cpl_hdr.attr.TD" +Toggle 0to1 cpl_hdr.attr.TD "logic cpl_hdr.attr.TD" +Toggle 1to0 cpl_hdr.attr.TH "logic cpl_hdr.attr.TH" +Toggle 0to1 cpl_hdr.attr.TH "logic cpl_hdr.attr.TH" +Toggle 1to0 cpl_hdr.attr.rsvd1 "logic cpl_hdr.attr.rsvd1" +Toggle 0to1 cpl_hdr.attr.rsvd1 "logic cpl_hdr.attr.rsvd1" +ANNOTATION: " Attribute and reserved fields " +Toggle cpl_hdr.attr.rsvd2 "logic cpl_hdr.attr.rsvd2[1:0]" +ANNOTATION: " Attribute and reserved fields " +Toggle cpl_hdr.attr.AT "logic cpl_hdr.attr.AT[1:0]" +Toggle cpl_hdr.pf_num "logic cpl_hdr.pf_num[2:0]" +Toggle cpl_hdr.pref_type "logic cpl_hdr.pref_type[4:0]" +Toggle 0to1 cpl_hdr.pref_present "logic cpl_hdr.pref_present" +Toggle 1to0 cpl_hdr.pref_present "logic cpl_hdr.pref_present" +Toggle cpl_hdr.pref "logic cpl_hdr.pref[23:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.axis_axil_bridge.axis_tx_st[0] +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.axis_axil_bridge.axis_tx_st[1] +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.axis_axil_bridge.axis_tx_st[0] +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.axis_axil_bridge.axis_tx_st[1] +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.axis_axil_bridge.axis_tx_st[0] +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.axis_axil_bridge.axis_tx_st[1] +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" diff --git a/verification/coverage/b_port_exclusions.el b/verification/coverage/b_port_exclusions.el new file mode 100644 index 0000000..34f7b62 --- /dev/null +++ b/verification/coverage/b_port_exclusions.el @@ -0,0 +1,7058 @@ +//================================================== +// This file contains the Excluded objects +// Generated By User: srudrarx +// Format Version: 2 +// Date: Wed May 25 21:55:11 2022 +// ExclMode: default +//================================================== +CHECKSUM: "3308023931" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.switch +CHECKSUM: "2005438484" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b +CHECKSUM: "1761785565" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.host_axi[0] +CHECKSUM: "1761785565" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.mux_axi[0] +CHECKSUM: "1761785565" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.mux_axi[1] +CHECKSUM: "1761785565" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.mux_axi[2] +CHECKSUM: "1761785565" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.mux_axi[3] +CHECKSUM: "1110801996" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.switch.M_mux[0] +CHECKSUM: "1110801996" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[0] +CHECKSUM: "1110801996" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[1] +CHECKSUM: "1110801996" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[2] +CHECKSUM: "1110801996" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[3] +CHECKSUM: "3190985420" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.switch.M_mux[0].out_q.fifo_ram +CHECKSUM: "3190985420" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[0].out_q.fifo_ram +CHECKSUM: "3190985420" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[1].out_q.fifo_ram +CHECKSUM: "3190985420" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[2].out_q.fifo_ram +CHECKSUM: "3190985420" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[3].out_q.fifo_ram +CHECKSUM: "3589944323" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.switch.M_mux[0].out_q.fifo_ram.genblk2.inst_gram_sdp +CHECKSUM: "3589944323" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[0].out_q.fifo_ram.genblk2.inst_gram_sdp +CHECKSUM: "3589944323" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[1].out_q.fifo_ram.genblk2.inst_gram_sdp +CHECKSUM: "3589944323" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[2].out_q.fifo_ram.genblk2.inst_gram_sdp +CHECKSUM: "3589944323" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[3].out_q.fifo_ram.genblk2.inst_gram_sdp +CHECKSUM: "4144234428" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.switch.M_mux[0].out_q +CHECKSUM: "4144234428" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[0].out_q +CHECKSUM: "4144234428" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[1].out_q +CHECKSUM: "4144234428" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[2].out_q +CHECKSUM: "4144234428" +INSTANCE:tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[3].out_q +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.arb2mx_rx_b +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.mx2fn_rx_b_port[0] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.mx2fn_rx_b_port[1] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.mx2fn_rx_b_port[2] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.mx2fn_rx_b_port[3] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.fn2mx_tx_b_port[0] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.fn2mx_tx_b_port[1] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.fn2mx_tx_b_port[2] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.fn2mx_tx_b_port[3] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.mx2ho_tx_ab[1] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.afu_rx_b_port[0] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.afu_rx_b_port[1] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.afu_tx_b_port[0] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.afu_tx_b_port[1] +CHECKSUM: "1761785565 1411067667" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a.mux_axi[2] +Toggle 0to1 in_port_data [588] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [588] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [515] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [515] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [516] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [516] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [517] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [517] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [518] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [518] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [519] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [519] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [520] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [520] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [521] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [521] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [522] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [522] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [523] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [523] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [524] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [524] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [525] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [525] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [526] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [526] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [527] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [527] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [528] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [528] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [529] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [529] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [530] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [530] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [531] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [531] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [532] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [532] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [533] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [533] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [534] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [534] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [535] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [535] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [536] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [536] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [537] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [537] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [538] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [538] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [539] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [539] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [540] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [540] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [541] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [541] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [542] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [542] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [543] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [543] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [544] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [544] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [545] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [545] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [546] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [546] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [547] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [547] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [548] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [548] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [549] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [549] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [550] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [550] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [551] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [551] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [552] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [552] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [553] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [553] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [554] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [554] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [555] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [555] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [556] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [556] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [557] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [557] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [558] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [558] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [559] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [559] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [560] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [560] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [561] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [561] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [562] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [562] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [563] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [563] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [564] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [564] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [565] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [565] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [566] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [566] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [567] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [567] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [568] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [568] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [569] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [569] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [570] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [570] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [571] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [571] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [572] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [572] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [573] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [573] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [574] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [574] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [575] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [575] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [576] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [576] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [577] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [577] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [578] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [578] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [579] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [579] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [580] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [580] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [581] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [581] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [582] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [582] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [583] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [583] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [584] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [584] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [585] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [585] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [586] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [586] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [587] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [587] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [511] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [511] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [384] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [384] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [385] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [385] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [386] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [386] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [387] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [387] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [388] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [388] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [389] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [389] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [390] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [390] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [391] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [391] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [392] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [392] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [393] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [393] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [394] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [394] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [395] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [395] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [396] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [396] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [397] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [397] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [398] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [398] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [399] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [399] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [400] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [400] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [401] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [401] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [402] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [402] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [403] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [403] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [404] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [404] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [405] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [405] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [406] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [406] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [407] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [407] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [408] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [408] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [409] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [409] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [410] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [410] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [411] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [411] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [412] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [412] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [413] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [413] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [414] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [414] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [415] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [415] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [416] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [416] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [417] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [417] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [418] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [418] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [419] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [419] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [420] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [420] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [421] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [421] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [422] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [422] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [423] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [423] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [424] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [424] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [425] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [425] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [426] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [426] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [427] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [427] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [428] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [428] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [429] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [429] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [430] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [430] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [431] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [431] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [432] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [432] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [433] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [433] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [434] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [434] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [435] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [435] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [436] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [436] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [437] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [437] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [438] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [438] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [439] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [439] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [440] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [440] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [441] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [441] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [442] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [442] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [443] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [443] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [444] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [444] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [445] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [445] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [446] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [446] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [447] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [447] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [448] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [448] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [449] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [449] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [450] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [450] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [451] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [451] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [452] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [452] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [453] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [453] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [454] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [454] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [455] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [455] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [456] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [456] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [457] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [457] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [458] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [458] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [459] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [459] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [460] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [460] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [461] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [461] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [462] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [462] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [463] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [463] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [464] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [464] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [465] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [465] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [466] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [466] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [467] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [467] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [468] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [468] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [469] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [469] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [470] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [470] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [471] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [471] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [472] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [472] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [473] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [473] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [474] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [474] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [475] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [475] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [476] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [476] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [477] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [477] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [478] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [478] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [479] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [479] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [480] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [480] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [481] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [481] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [482] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [482] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [483] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [483] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [484] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [484] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [485] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [485] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [486] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [486] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [487] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [487] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [488] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [488] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [489] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [489] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [490] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [490] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [491] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [491] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [492] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [492] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [493] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [493] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [494] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [494] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [495] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [495] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [496] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [496] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [497] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [497] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [498] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [498] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [499] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [499] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [500] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [500] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [501] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [501] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [502] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [502] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [503] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [503] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [504] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [504] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [505] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [505] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [506] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [506] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [507] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [507] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [508] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [508] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [509] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [509] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [510] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [510] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [255] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [255] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [175] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [175] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [176] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [176] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [177] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [177] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [178] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [178] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [179] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [179] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [180] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [180] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [181] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [181] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [182] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [182] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [183] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [183] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [184] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [184] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [185] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [185] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [186] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [186] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [187] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [187] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [188] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [188] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [189] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [189] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [190] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [190] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [191] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [191] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [192] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [192] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [193] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [193] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [194] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [194] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [195] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [195] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [196] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [196] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [197] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [197] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [198] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [198] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [199] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [199] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [200] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [200] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [201] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [201] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [202] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [202] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [203] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [203] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [204] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [204] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [205] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [205] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [206] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [206] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [207] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [207] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [208] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [208] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [209] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [209] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [210] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [210] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [211] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [211] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [212] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [212] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [213] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [213] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [214] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [214] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [215] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [215] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [216] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [216] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [217] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [217] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [218] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [218] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [219] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [219] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [220] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [220] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [221] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [221] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [222] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [222] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [223] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [223] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [224] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [224] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [225] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [225] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [226] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [226] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [227] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [227] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [228] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [228] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [229] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [229] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [230] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [230] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [231] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [231] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [232] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [232] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [233] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [233] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [234] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [234] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [235] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [235] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [236] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [236] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [237] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [237] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [238] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [238] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [239] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [239] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [240] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [240] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [241] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [241] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [242] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [242] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [243] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [243] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [244] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [244] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [245] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [245] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [246] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [246] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [247] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [247] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [248] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [248] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [249] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [249] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [250] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [250] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [251] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [251] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [252] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [252] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [253] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [253] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [254] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [254] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [174] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [173] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [173] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [164] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [164] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [165] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [165] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [166] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [166] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [167] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [167] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [168] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [168] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [169] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [169] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [170] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [170] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [171] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [171] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [172] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [172] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [81] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [81] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [82] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [82] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [83] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [83] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [84] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [84] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [85] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [85] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [86] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [86] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [87] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [87] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [88] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [88] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [89] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [89] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [90] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [90] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [91] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [91] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [92] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [92] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [93] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [93] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [94] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [94] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [95] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [95] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [96] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [96] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [97] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [97] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [98] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [98] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [99] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [99] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [100] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [100] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [101] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [101] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [102] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [102] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [103] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [103] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [104] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [104] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [105] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [105] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [106] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [106] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [107] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [107] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [108] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [108] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [109] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [109] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [110] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [110] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [111] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [111] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [112] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [112] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [113] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [113] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [114] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [114] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [115] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [115] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [116] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [116] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [117] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [117] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [118] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [118] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [119] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [119] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [120] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [120] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [121] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [121] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [122] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [122] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [123] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [123] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [124] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [124] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [125] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [125] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [126] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [126] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [127] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [127] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [128] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [128] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [129] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [129] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [130] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [130] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [131] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [131] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [132] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [132] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [133] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [133] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [134] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [134] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [135] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [135] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [136] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [136] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [137] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [137] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [138] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [138] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [139] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [139] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [140] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [140] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [141] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [141] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [142] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [142] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [143] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [143] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [144] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [144] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [145] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [145] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [146] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [146] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [147] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [147] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [148] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [148] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [149] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [149] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [150] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [150] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [151] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [151] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [152] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [152] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [153] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [153] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [154] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [154] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [155] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [155] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [156] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [156] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [157] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [157] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [158] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [158] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [159] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [159] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [160] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [160] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [161] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [161] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [162] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [162] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [163] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [80] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [51] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [52] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [53] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [53] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [54] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [54] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [55] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [55] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [56] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [56] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [57] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [57] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [58] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [58] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [59] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [59] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [60] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [60] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [61] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [61] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [62] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [62] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [63] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [63] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [64] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [64] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [65] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [65] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [66] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [66] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [71] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [71] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [77] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [77] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [78] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [78] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [79] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [79] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [50] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [50] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [31] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [31] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [32] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [32] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [33] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [33] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [36] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [36] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [37] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [37] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [38] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [38] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [39] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [39] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [40] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [40] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [41] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [41] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [42] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [42] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [43] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [43] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [44] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [44] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [45] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [45] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [46] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [46] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [47] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [47] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [48] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [48] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [49] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [49] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [30] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [29] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [29] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [28] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [28] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [27] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [25] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [2] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [2] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [3] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [3] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [4] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [4] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [5] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [5] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [6] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [6] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [7] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [7] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [8] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [8] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [9] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [9] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [10] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [10] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [11] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [11] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [12] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [12] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [13] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [13] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [14] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [14] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [15] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [15] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [16] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [16] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [17] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [17] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [18] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [18] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [19] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [19] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [20] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [20] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [21] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [21] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [22] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [22] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [23] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [23] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [24] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [24] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [26] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [26] "net in_port_data[588:0]" +CHECKSUM: "1761785565 1411067667" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a.mux_axi[3] +Toggle 0to1 in_port_data [588] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [588] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [384] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [384] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [385] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [385] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [386] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [386] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [387] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [387] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [388] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [388] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [389] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [389] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [390] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [390] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [391] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [391] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [392] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [392] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [393] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [393] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [394] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [394] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [395] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [395] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [396] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [396] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [397] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [397] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [398] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [398] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [399] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [399] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [400] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [400] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [401] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [401] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [402] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [402] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [403] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [403] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [404] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [404] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [405] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [405] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [406] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [406] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [407] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [407] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [408] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [408] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [409] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [409] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [410] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [410] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [411] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [411] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [412] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [412] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [413] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [413] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [414] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [414] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [415] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [415] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [416] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [416] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [417] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [417] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [418] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [418] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [419] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [419] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [420] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [420] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [421] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [421] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [422] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [422] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [423] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [423] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [424] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [424] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [425] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [425] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [426] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [426] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [427] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [427] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [428] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [428] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [429] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [429] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [430] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [430] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [431] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [431] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [432] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [432] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [433] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [433] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [434] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [434] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [435] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [435] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [436] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [436] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [437] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [437] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [438] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [438] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [439] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [439] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [440] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [440] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [441] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [441] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [442] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [442] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [443] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [443] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [444] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [444] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [445] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [445] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [446] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [446] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [447] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [447] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [448] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [448] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [449] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [449] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [450] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [450] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [451] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [451] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [452] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [452] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [453] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [453] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [454] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [454] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [455] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [455] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [456] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [456] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [457] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [457] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [458] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [458] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [459] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [459] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [460] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [460] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [461] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [461] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [462] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [462] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [463] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [463] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [464] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [464] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [465] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [465] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [466] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [466] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [467] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [467] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [468] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [468] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [469] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [469] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [470] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [470] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [471] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [471] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [472] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [472] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [473] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [473] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [474] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [474] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [475] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [475] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [476] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [476] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [477] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [477] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [478] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [478] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [479] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [479] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [480] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [480] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [481] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [481] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [482] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [482] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [483] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [483] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [484] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [484] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [485] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [485] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [486] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [486] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [487] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [487] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [488] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [488] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [489] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [489] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [490] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [490] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [491] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [491] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [492] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [492] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [493] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [493] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [494] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [494] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [495] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [495] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [496] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [496] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [497] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [497] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [498] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [498] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [499] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [499] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [500] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [500] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [501] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [501] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [502] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [502] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [503] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [503] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [504] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [504] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [505] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [505] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [506] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [506] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [507] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [507] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [508] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [508] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [509] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [509] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [510] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [510] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [511] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [511] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [515] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [515] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [516] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [516] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [517] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [517] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [518] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [518] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [519] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [519] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [520] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [520] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [521] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [521] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [522] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [522] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [523] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [523] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [524] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [524] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [525] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [525] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [526] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [526] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [527] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [527] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [528] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [528] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [529] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [529] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [530] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [530] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [531] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [531] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [532] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [532] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [533] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [533] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [534] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [534] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [535] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [535] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [536] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [536] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [537] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [537] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [538] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [538] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [539] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [539] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [540] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [540] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [541] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [541] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [542] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [542] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [543] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [543] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [544] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [544] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [545] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [545] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [546] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [546] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [547] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [547] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [548] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [548] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [549] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [549] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [550] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [550] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [551] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [551] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [552] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [552] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [553] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [553] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [554] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [554] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [555] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [555] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [556] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [556] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [557] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [557] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [558] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [558] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [559] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [559] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [560] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [560] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [561] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [561] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [562] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [562] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [563] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [563] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [564] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [564] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [565] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [565] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [566] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [566] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [567] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [567] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [568] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [568] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [569] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [569] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [570] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [570] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [571] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [571] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [572] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [572] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [573] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [573] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [574] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [574] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [575] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [575] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [576] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [576] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [577] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [577] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [578] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [578] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [579] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [579] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [580] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [580] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [581] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [581] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [582] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [582] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [583] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [583] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [584] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [584] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [585] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [585] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [586] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [586] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [587] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [587] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [255] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [255] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [81] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [81] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [82] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [82] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [83] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [83] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [84] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [84] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [85] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [85] "net in_port_data[588:0]" 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"net in_port_data[588:0]" +Toggle 0to1 in_port_data [95] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [95] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [96] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [96] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [97] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [97] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [98] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [98] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [99] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [99] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [100] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [100] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [101] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [101] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [102] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [102] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [103] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [103] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [104] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [104] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [105] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [105] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [106] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [106] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [107] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [107] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [108] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [108] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [109] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [109] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [110] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [110] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [111] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [111] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [112] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [112] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [113] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [113] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [114] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [114] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [115] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [115] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [116] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [116] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [117] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [117] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [118] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [118] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [119] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [119] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [120] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [120] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [121] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [121] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [122] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [122] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [123] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [123] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [124] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [124] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [125] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [125] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [126] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [126] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [127] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [127] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [128] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [128] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [129] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [129] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [130] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [130] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [131] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [131] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [132] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [132] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [133] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [133] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [134] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [134] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [135] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [135] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [136] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [136] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [137] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [137] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [138] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [138] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [139] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [139] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [140] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [140] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [141] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [141] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [142] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [142] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [143] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [143] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [144] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [144] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [145] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [145] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [146] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [146] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [147] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [147] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [148] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [148] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [149] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [149] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [150] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [150] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [151] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [151] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [152] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [152] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [153] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [153] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [154] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [154] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [155] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [155] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [156] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [156] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [157] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [157] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [158] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [158] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [159] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [159] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [160] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [160] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [161] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [161] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [162] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [162] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [163] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [163] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [165] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [165] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [166] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [166] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [167] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [167] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [168] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [168] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [169] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [169] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [170] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [170] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [171] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [171] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [172] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [172] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [173] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [173] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [175] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [175] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [176] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [176] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [177] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [177] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [178] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [178] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [179] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [179] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [180] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [180] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [181] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [181] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [182] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [182] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [183] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [183] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [184] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [184] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [185] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [185] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [186] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [186] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [187] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [187] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [188] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [188] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [189] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [189] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [190] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [190] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [191] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [191] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [192] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [192] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [193] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [193] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [194] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [194] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [195] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [195] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [196] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [196] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [197] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [197] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [198] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [198] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [199] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [199] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [200] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [200] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [201] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [201] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [202] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [202] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [203] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [203] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [204] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [204] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [205] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [205] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [206] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [206] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [207] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [207] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [208] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [208] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [209] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [209] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [210] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [210] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [211] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [211] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [212] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [212] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [213] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [213] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [214] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [214] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [215] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [215] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [216] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [216] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [217] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [217] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [218] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [218] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [219] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [219] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [220] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [220] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [221] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [221] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [222] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [222] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [223] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [223] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [224] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [224] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [225] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [225] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [226] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [226] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [227] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [227] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [228] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [228] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [229] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [229] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [230] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [230] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [231] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [231] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [232] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [232] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [233] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [233] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [234] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [234] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [235] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [235] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [236] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [236] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [237] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [237] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [238] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [238] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [239] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [239] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [240] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [240] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [241] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [241] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [242] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [242] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [243] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [243] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [244] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [244] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [245] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [245] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [246] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [246] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [247] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [247] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [248] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [248] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [249] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [249] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [250] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [250] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [251] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [251] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [252] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [252] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [253] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [253] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [254] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [254] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [174] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [164] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [80] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [79] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [79] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [77] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [77] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [78] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [78] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [71] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [71] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [70] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [65] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [65] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [36] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [36] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [37] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [37] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [38] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [38] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [39] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [39] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [40] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [40] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [41] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [41] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [42] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [42] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [43] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [43] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [44] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [44] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [45] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [45] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [46] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [46] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [47] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [47] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [48] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [48] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [49] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [49] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [50] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [50] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [52] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [52] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [54] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [54] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [55] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [55] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [56] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [56] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [57] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [57] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [58] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [58] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [59] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [59] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [60] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [60] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [61] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [61] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [62] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [62] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [63] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [63] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [64] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [64] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [53] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [51] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [33] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [33] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [31] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [31] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [32] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [32] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [28] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [28] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [29] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [29] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [30] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [27] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [26] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [26] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [25] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [24] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [24] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [2] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [2] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [3] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [3] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [4] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [4] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [5] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [5] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [6] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [6] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [7] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [7] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [8] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [8] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [9] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [9] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [10] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [10] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [11] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [11] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [12] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [12] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [13] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [13] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [14] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [14] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [15] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [15] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [16] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [16] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [17] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [17] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [18] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [18] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [19] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [19] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [20] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [20] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [21] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [21] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [22] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [22] "net in_port_data[588:0]" +Toggle 0to1 in_port_data [23] "net in_port_data[588:0]" +Toggle 1to0 in_port_data [23] "net in_port_data[588:0]" +CHECKSUM: "3589944323 3620682728" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a.switch.N_mux[2].out_q.fifo_ram.genblk2.inst_gram_sdp +Toggle ram_dout "reg ram_dout[588:0]" +Toggle 0to1 driveX "reg driveX" +Toggle 1to0 driveX "reg driveX" +Toggle 0to1 raddr_q [0] "reg raddr_q[0:0]" +Toggle 1to0 raddr_q [0] "reg raddr_q[0:0]" +CHECKSUM: "3589944323 3620682728" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a.switch.M_mux[0].out_q.fifo_ram.genblk2.inst_gram_sdp +Toggle 0to1 raddr_q [0] "reg raddr_q[0:0]" +Toggle 1to0 raddr_q [0] "reg raddr_q[0:0]" +Toggle ram_dout "reg ram_dout[588:0]" +CHECKSUM: "3589944323 3620682728" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a.switch.N_mux[0].out_q.fifo_ram.genblk2.inst_gram_sdp +Toggle 0to1 raddr_q [0] "reg raddr_q[0:0]" +Toggle 1to0 raddr_q [0] "reg raddr_q[0:0]" +Toggle ram_dout "reg ram_dout[588:0]" +CHECKSUM: "3589944323 3620682728" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a.switch.N_mux[1].out_q.fifo_ram.genblk2.inst_gram_sdp +Toggle 0to1 raddr_q [0] "reg raddr_q[0:0]" +Toggle 1to0 raddr_q [0] "reg raddr_q[0:0]" +Toggle ram_dout "reg ram_dout[588:0]" +CHECKSUM: "3589944323 3620682728" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a.switch.N_mux[3].out_q.fifo_ram.genblk2.inst_gram_sdp +Toggle 0to1 dout [375] "reg dout[588:0]" +Toggle 1to0 dout [375] "reg dout[588:0]" +Toggle 0to1 dout [96] "reg dout[588:0]" +Toggle 1to0 dout [96] "reg dout[588:0]" +Toggle 0to1 dout [97] "reg dout[588:0]" +Toggle 1to0 dout [97] "reg dout[588:0]" +Toggle 0to1 dout [103] "reg dout[588:0]" +Toggle 1to0 dout [103] "reg dout[588:0]" +Toggle 0to1 dout [104] "reg dout[588:0]" +Toggle 1to0 dout [104] "reg dout[588:0]" +Toggle 0to1 dout [105] "reg dout[588:0]" +Toggle 1to0 dout [105] "reg dout[588:0]" +Toggle 0to1 dout [106] "reg dout[588:0]" +Toggle 1to0 dout [106] "reg dout[588:0]" +Toggle 0to1 dout [107] "reg dout[588:0]" +Toggle 1to0 dout [107] "reg dout[588:0]" +Toggle 0to1 dout [109] "reg dout[588:0]" +Toggle 1to0 dout [109] "reg dout[588:0]" +Toggle 0to1 dout [110] "reg dout[588:0]" +Toggle 1to0 dout [110] "reg dout[588:0]" +Toggle 0to1 dout [111] "reg dout[588:0]" +Toggle 1to0 dout [111] "reg dout[588:0]" +Toggle 0to1 dout [112] "reg dout[588:0]" +Toggle 1to0 dout [112] "reg dout[588:0]" +Toggle 0to1 dout [113] "reg dout[588:0]" +Toggle 1to0 dout [113] "reg dout[588:0]" +Toggle 0to1 dout [114] "reg dout[588:0]" +Toggle 1to0 dout [114] "reg dout[588:0]" +Toggle 0to1 dout [115] "reg dout[588:0]" +Toggle 1to0 dout [115] "reg dout[588:0]" +Toggle 0to1 dout [116] "reg dout[588:0]" +Toggle 1to0 dout [116] "reg dout[588:0]" +Toggle 0to1 dout [117] "reg dout[588:0]" +Toggle 1to0 dout [117] "reg dout[588:0]" +Toggle 0to1 dout [118] "reg dout[588:0]" +Toggle 1to0 dout [118] "reg dout[588:0]" +Toggle 0to1 dout [119] "reg dout[588:0]" +Toggle 1to0 dout [119] "reg dout[588:0]" +Toggle 0to1 dout [120] "reg dout[588:0]" +Toggle 1to0 dout [120] "reg dout[588:0]" +Toggle 0to1 dout [121] "reg dout[588:0]" +Toggle 1to0 dout [121] "reg dout[588:0]" +Toggle 0to1 dout [122] "reg dout[588:0]" +Toggle 1to0 dout [122] "reg dout[588:0]" +Toggle 0to1 dout [123] "reg dout[588:0]" +Toggle 1to0 dout [123] "reg dout[588:0]" +Toggle 0to1 dout [124] "reg dout[588:0]" +Toggle 1to0 dout [124] "reg dout[588:0]" +Toggle 0to1 dout [125] "reg dout[588:0]" +Toggle 1to0 dout [125] "reg dout[588:0]" +Toggle 0to1 dout [126] "reg dout[588:0]" +Toggle 1to0 dout [126] "reg dout[588:0]" +Toggle 0to1 dout [127] "reg dout[588:0]" +Toggle 1to0 dout [127] "reg dout[588:0]" +Toggle 0to1 dout [128] "reg dout[588:0]" +Toggle 1to0 dout [128] "reg dout[588:0]" +Toggle 0to1 dout [129] "reg dout[588:0]" +Toggle 1to0 dout [129] "reg dout[588:0]" +Toggle 0to1 dout [130] "reg dout[588:0]" +Toggle 1to0 dout [130] "reg dout[588:0]" +Toggle 0to1 dout [131] "reg dout[588:0]" +Toggle 1to0 dout [131] "reg dout[588:0]" +Toggle 0to1 dout [132] "reg dout[588:0]" +Toggle 1to0 dout [132] "reg dout[588:0]" +Toggle 0to1 dout [133] "reg dout[588:0]" +Toggle 1to0 dout [133] "reg dout[588:0]" +Toggle 0to1 dout [134] "reg dout[588:0]" +Toggle 1to0 dout [134] "reg dout[588:0]" +Toggle 0to1 dout [135] "reg dout[588:0]" +Toggle 1to0 dout [135] "reg dout[588:0]" +Toggle 0to1 dout [136] "reg dout[588:0]" +Toggle 1to0 dout [136] "reg dout[588:0]" +Toggle 0to1 dout [137] "reg dout[588:0]" +Toggle 1to0 dout [137] "reg dout[588:0]" +Toggle 0to1 dout [138] "reg dout[588:0]" +Toggle 1to0 dout [138] "reg dout[588:0]" +Toggle 0to1 dout [139] "reg dout[588:0]" +Toggle 1to0 dout [139] "reg dout[588:0]" +Toggle 0to1 dout [140] "reg dout[588:0]" +Toggle 1to0 dout [140] "reg dout[588:0]" +Toggle 0to1 dout [141] "reg dout[588:0]" +Toggle 1to0 dout [141] "reg dout[588:0]" +Toggle 0to1 dout [142] "reg dout[588:0]" +Toggle 1to0 dout [142] "reg dout[588:0]" +Toggle 0to1 dout [143] "reg dout[588:0]" +Toggle 1to0 dout [143] "reg dout[588:0]" +Toggle 0to1 dout [144] "reg dout[588:0]" +Toggle 1to0 dout [144] "reg dout[588:0]" +Toggle 0to1 dout [145] "reg dout[588:0]" +Toggle 1to0 dout [145] "reg dout[588:0]" +Toggle 0to1 dout [146] "reg dout[588:0]" +Toggle 1to0 dout [146] "reg dout[588:0]" +Toggle 0to1 dout [147] "reg dout[588:0]" +Toggle 1to0 dout [147] "reg dout[588:0]" +Toggle 0to1 dout [148] "reg dout[588:0]" +Toggle 1to0 dout [148] "reg dout[588:0]" +Toggle 0to1 dout [149] "reg dout[588:0]" +Toggle 1to0 dout [149] "reg dout[588:0]" +Toggle 0to1 dout [150] "reg dout[588:0]" +Toggle 1to0 dout [150] "reg dout[588:0]" +Toggle 0to1 dout [151] "reg dout[588:0]" +Toggle 1to0 dout [151] "reg dout[588:0]" +Toggle 0to1 dout [152] "reg dout[588:0]" +Toggle 1to0 dout [152] "reg dout[588:0]" +Toggle 0to1 dout [153] "reg dout[588:0]" +Toggle 1to0 dout [153] "reg dout[588:0]" +Toggle 0to1 dout [154] "reg dout[588:0]" +Toggle 1to0 dout [154] "reg dout[588:0]" +Toggle 0to1 dout [155] "reg dout[588:0]" +Toggle 1to0 dout [155] "reg dout[588:0]" +Toggle 0to1 dout [156] "reg dout[588:0]" +Toggle 1to0 dout [156] "reg dout[588:0]" +Toggle 0to1 dout [157] "reg dout[588:0]" +Toggle 1to0 dout [157] "reg dout[588:0]" +Toggle 0to1 dout [158] "reg dout[588:0]" +Toggle 1to0 dout [158] "reg dout[588:0]" +Toggle 0to1 dout [159] "reg dout[588:0]" +Toggle 1to0 dout [159] "reg dout[588:0]" +Toggle 0to1 dout [160] "reg dout[588:0]" +Toggle 1to0 dout [160] "reg dout[588:0]" +Toggle 0to1 dout [161] "reg dout[588:0]" +Toggle 1to0 dout [161] "reg dout[588:0]" +Toggle 0to1 dout [162] "reg dout[588:0]" +Toggle 1to0 dout [162] "reg dout[588:0]" +Toggle 0to1 dout [163] "reg dout[588:0]" +Toggle 1to0 dout [163] "reg dout[588:0]" +Toggle 0to1 dout [164] "reg dout[588:0]" +Toggle 1to0 dout [164] "reg dout[588:0]" +Toggle 0to1 dout [165] "reg dout[588:0]" +Toggle 1to0 dout [165] "reg dout[588:0]" +Toggle 0to1 dout [166] "reg dout[588:0]" +Toggle 1to0 dout [166] "reg dout[588:0]" +Toggle 0to1 dout [167] "reg dout[588:0]" +Toggle 1to0 dout [167] "reg dout[588:0]" +Toggle 0to1 dout [168] "reg dout[588:0]" +Toggle 1to0 dout [168] "reg dout[588:0]" +Toggle 0to1 dout [169] "reg dout[588:0]" +Toggle 1to0 dout [169] "reg dout[588:0]" +Toggle 0to1 dout [170] "reg dout[588:0]" +Toggle 1to0 dout [170] "reg dout[588:0]" +Toggle 0to1 dout [171] "reg dout[588:0]" +Toggle 1to0 dout [171] "reg dout[588:0]" +Toggle 0to1 dout [172] "reg dout[588:0]" +Toggle 1to0 dout [172] "reg dout[588:0]" +Toggle 0to1 dout [173] "reg dout[588:0]" +Toggle 1to0 dout [173] "reg dout[588:0]" +Toggle 0to1 dout [174] "reg dout[588:0]" +Toggle 1to0 dout [174] "reg dout[588:0]" +Toggle 0to1 dout [175] "reg dout[588:0]" +Toggle 1to0 dout [175] "reg dout[588:0]" +Toggle 0to1 dout [176] "reg dout[588:0]" +Toggle 1to0 dout [176] "reg dout[588:0]" +Toggle 0to1 dout [177] "reg dout[588:0]" +Toggle 1to0 dout [177] "reg dout[588:0]" +Toggle 0to1 dout [178] "reg dout[588:0]" +Toggle 1to0 dout [178] "reg dout[588:0]" +Toggle 0to1 dout [179] "reg dout[588:0]" +Toggle 1to0 dout [179] "reg dout[588:0]" +Toggle 0to1 dout [180] "reg dout[588:0]" +Toggle 1to0 dout [180] "reg dout[588:0]" +Toggle 0to1 dout [181] "reg dout[588:0]" +Toggle 1to0 dout [181] "reg dout[588:0]" +Toggle 0to1 dout [182] "reg dout[588:0]" +Toggle 1to0 dout [182] "reg dout[588:0]" +Toggle 0to1 dout [183] "reg dout[588:0]" +Toggle 1to0 dout [183] "reg dout[588:0]" +Toggle 0to1 dout [184] "reg dout[588:0]" +Toggle 1to0 dout [184] "reg dout[588:0]" +Toggle 0to1 dout [185] "reg dout[588:0]" +Toggle 1to0 dout [185] "reg dout[588:0]" +Toggle 0to1 dout [186] "reg dout[588:0]" +Toggle 1to0 dout [186] "reg dout[588:0]" +Toggle 0to1 dout [187] "reg dout[588:0]" +Toggle 1to0 dout [187] "reg dout[588:0]" +Toggle 0to1 dout [188] "reg dout[588:0]" +Toggle 1to0 dout [188] "reg dout[588:0]" +Toggle 0to1 dout [189] "reg dout[588:0]" +Toggle 1to0 dout [189] "reg dout[588:0]" +Toggle 0to1 dout [190] "reg dout[588:0]" +Toggle 1to0 dout [190] "reg dout[588:0]" +Toggle 0to1 dout [191] "reg dout[588:0]" +Toggle 1to0 dout [191] "reg dout[588:0]" +Toggle 0to1 dout [192] "reg dout[588:0]" +Toggle 1to0 dout [192] "reg dout[588:0]" +Toggle 0to1 dout [193] "reg dout[588:0]" +Toggle 1to0 dout [193] "reg dout[588:0]" +Toggle 0to1 dout [194] "reg dout[588:0]" +Toggle 1to0 dout [194] "reg dout[588:0]" +Toggle 0to1 dout [195] "reg dout[588:0]" +Toggle 1to0 dout [195] "reg dout[588:0]" +Toggle 0to1 dout [196] "reg dout[588:0]" +Toggle 1to0 dout [196] "reg dout[588:0]" +Toggle 0to1 dout [197] "reg dout[588:0]" +Toggle 1to0 dout [197] "reg dout[588:0]" +Toggle 0to1 dout [198] "reg dout[588:0]" +Toggle 1to0 dout [198] "reg dout[588:0]" +Toggle 0to1 dout [199] "reg dout[588:0]" +Toggle 1to0 dout [199] "reg dout[588:0]" +Toggle 0to1 dout [200] "reg dout[588:0]" +Toggle 1to0 dout [200] "reg dout[588:0]" +Toggle 0to1 dout [201] "reg dout[588:0]" +Toggle 1to0 dout [201] "reg dout[588:0]" +Toggle 0to1 dout [202] "reg dout[588:0]" +Toggle 1to0 dout [202] "reg dout[588:0]" +Toggle 0to1 dout [203] "reg dout[588:0]" +Toggle 1to0 dout [203] "reg dout[588:0]" +Toggle 0to1 dout [204] "reg dout[588:0]" +Toggle 1to0 dout [204] "reg dout[588:0]" +Toggle 0to1 dout [205] "reg dout[588:0]" +Toggle 1to0 dout [205] "reg dout[588:0]" +Toggle 0to1 dout [206] "reg dout[588:0]" +Toggle 1to0 dout [206] "reg dout[588:0]" +Toggle 0to1 dout [207] "reg dout[588:0]" +Toggle 1to0 dout [207] "reg dout[588:0]" +Toggle 0to1 dout [208] "reg dout[588:0]" +Toggle 1to0 dout [208] "reg dout[588:0]" +Toggle 0to1 dout [209] "reg dout[588:0]" +Toggle 1to0 dout [209] "reg dout[588:0]" +Toggle 0to1 dout [210] "reg dout[588:0]" +Toggle 1to0 dout [210] "reg dout[588:0]" +Toggle 0to1 dout [211] "reg dout[588:0]" +Toggle 1to0 dout [211] "reg dout[588:0]" +Toggle 0to1 dout [212] "reg dout[588:0]" +Toggle 1to0 dout [212] "reg dout[588:0]" +Toggle 0to1 dout [213] "reg dout[588:0]" +Toggle 1to0 dout [213] "reg dout[588:0]" +Toggle 0to1 dout [214] "reg dout[588:0]" +Toggle 1to0 dout [214] "reg dout[588:0]" +Toggle 0to1 dout [215] "reg dout[588:0]" +Toggle 1to0 dout [215] "reg dout[588:0]" +Toggle 0to1 dout [216] "reg dout[588:0]" +Toggle 1to0 dout [216] "reg dout[588:0]" +Toggle 0to1 dout [217] "reg dout[588:0]" +Toggle 1to0 dout [217] "reg dout[588:0]" +Toggle 0to1 dout [218] "reg dout[588:0]" +Toggle 1to0 dout [218] "reg dout[588:0]" +Toggle 0to1 dout [219] "reg dout[588:0]" +Toggle 1to0 dout [219] "reg dout[588:0]" +Toggle 0to1 dout [220] "reg dout[588:0]" +Toggle 1to0 dout [220] "reg dout[588:0]" +Toggle 0to1 dout [221] "reg dout[588:0]" +Toggle 1to0 dout [221] "reg dout[588:0]" +Toggle 0to1 dout [222] "reg dout[588:0]" +Toggle 1to0 dout [222] "reg dout[588:0]" +Toggle 0to1 dout [223] "reg dout[588:0]" +Toggle 1to0 dout [223] "reg dout[588:0]" +Toggle 0to1 dout [224] "reg dout[588:0]" +Toggle 1to0 dout [224] "reg dout[588:0]" +Toggle 0to1 dout [225] "reg dout[588:0]" +Toggle 1to0 dout [225] "reg dout[588:0]" +Toggle 0to1 dout [226] "reg dout[588:0]" +Toggle 1to0 dout [226] "reg dout[588:0]" +Toggle 0to1 dout [227] "reg dout[588:0]" +Toggle 1to0 dout [227] "reg dout[588:0]" +Toggle 0to1 dout [228] "reg dout[588:0]" +Toggle 1to0 dout [228] "reg dout[588:0]" +Toggle 0to1 dout [229] "reg dout[588:0]" +Toggle 1to0 dout [229] "reg dout[588:0]" +Toggle 0to1 dout [230] "reg dout[588:0]" +Toggle 1to0 dout [230] "reg dout[588:0]" +Toggle 0to1 dout [231] "reg dout[588:0]" +Toggle 1to0 dout [231] "reg dout[588:0]" +Toggle 0to1 dout [232] "reg dout[588:0]" +Toggle 1to0 dout [232] "reg dout[588:0]" +Toggle 0to1 dout [233] "reg dout[588:0]" +Toggle 1to0 dout [233] "reg dout[588:0]" +Toggle 0to1 dout [234] "reg dout[588:0]" +Toggle 1to0 dout [234] "reg dout[588:0]" +Toggle 0to1 dout [235] "reg dout[588:0]" +Toggle 1to0 dout [235] "reg dout[588:0]" +Toggle 0to1 dout [236] "reg dout[588:0]" +Toggle 1to0 dout [236] "reg dout[588:0]" +Toggle 0to1 dout [237] "reg dout[588:0]" +Toggle 1to0 dout [237] "reg dout[588:0]" +Toggle 0to1 dout [238] "reg dout[588:0]" +Toggle 1to0 dout [238] "reg dout[588:0]" +Toggle 0to1 dout [239] "reg dout[588:0]" +Toggle 1to0 dout [239] "reg dout[588:0]" +Toggle 0to1 dout [240] "reg dout[588:0]" +Toggle 1to0 dout [240] "reg dout[588:0]" +Toggle 0to1 dout [241] "reg dout[588:0]" +Toggle 1to0 dout [241] "reg dout[588:0]" +Toggle 0to1 dout [242] "reg dout[588:0]" +Toggle 1to0 dout [242] "reg dout[588:0]" +Toggle 0to1 dout [243] "reg dout[588:0]" +Toggle 1to0 dout [243] "reg dout[588:0]" +Toggle 0to1 dout [244] "reg dout[588:0]" +Toggle 1to0 dout [244] "reg dout[588:0]" +Toggle 0to1 dout [245] "reg dout[588:0]" +Toggle 1to0 dout [245] "reg dout[588:0]" +Toggle 0to1 dout [246] "reg dout[588:0]" +Toggle 1to0 dout [246] "reg dout[588:0]" +Toggle 0to1 dout [247] "reg dout[588:0]" +Toggle 1to0 dout [247] "reg dout[588:0]" +Toggle 0to1 dout [248] "reg dout[588:0]" +Toggle 1to0 dout [248] "reg dout[588:0]" +Toggle 0to1 dout [249] "reg dout[588:0]" +Toggle 1to0 dout [249] "reg dout[588:0]" +Toggle 0to1 dout [250] "reg dout[588:0]" +Toggle 1to0 dout [250] "reg dout[588:0]" +Toggle 0to1 dout [251] "reg dout[588:0]" +Toggle 1to0 dout [251] "reg dout[588:0]" +Toggle 0to1 dout [252] "reg dout[588:0]" +Toggle 1to0 dout [252] "reg dout[588:0]" +Toggle 0to1 dout [253] "reg dout[588:0]" +Toggle 1to0 dout [253] "reg dout[588:0]" +Toggle 0to1 dout [254] "reg dout[588:0]" +Toggle 1to0 dout [254] "reg dout[588:0]" +Toggle 0to1 dout [255] "reg dout[588:0]" +Toggle 1to0 dout [255] "reg dout[588:0]" +Toggle 0to1 dout [372] "reg dout[588:0]" +Toggle 1to0 dout [372] "reg dout[588:0]" +Toggle 0to1 dout [373] "reg dout[588:0]" +Toggle 1to0 dout [373] "reg dout[588:0]" +Toggle 0to1 dout [374] "reg dout[588:0]" +Toggle 1to0 dout [374] "reg dout[588:0]" +Toggle 0to1 dout [95] "reg dout[588:0]" +Toggle 1to0 dout [95] "reg dout[588:0]" +Toggle 0to1 dout [77] "reg dout[588:0]" +Toggle 1to0 dout [77] "reg dout[588:0]" +Toggle 0to1 dout [78] "reg dout[588:0]" +Toggle 1to0 dout [78] "reg dout[588:0]" +Toggle 0to1 dout [79] "reg dout[588:0]" +Toggle 1to0 dout [79] "reg dout[588:0]" +Toggle 0to1 dout [80] "reg dout[588:0]" +Toggle 1to0 dout [80] "reg dout[588:0]" +Toggle 0to1 dout [81] "reg dout[588:0]" +Toggle 1to0 dout [81] "reg dout[588:0]" +Toggle 0to1 dout [82] "reg dout[588:0]" +Toggle 1to0 dout [82] "reg dout[588:0]" +Toggle 0to1 dout [83] "reg dout[588:0]" +Toggle 1to0 dout [83] "reg dout[588:0]" +Toggle 0to1 dout [84] "reg dout[588:0]" +Toggle 1to0 dout [84] "reg dout[588:0]" +Toggle 0to1 dout [85] "reg dout[588:0]" +Toggle 1to0 dout [85] "reg dout[588:0]" +Toggle 0to1 dout [86] "reg dout[588:0]" +Toggle 1to0 dout [86] "reg dout[588:0]" +Toggle 0to1 dout [87] "reg dout[588:0]" +Toggle 1to0 dout [87] "reg dout[588:0]" +Toggle 0to1 dout [88] "reg dout[588:0]" +Toggle 1to0 dout [88] "reg dout[588:0]" +Toggle 0to1 dout [89] "reg dout[588:0]" +Toggle 1to0 dout [89] "reg dout[588:0]" +Toggle 0to1 dout [90] "reg dout[588:0]" +Toggle 1to0 dout [90] "reg dout[588:0]" +Toggle 0to1 dout [91] "reg dout[588:0]" +Toggle 1to0 dout [91] "reg dout[588:0]" +Toggle 0to1 dout [92] "reg dout[588:0]" +Toggle 1to0 dout [92] "reg dout[588:0]" +Toggle 0to1 dout [93] "reg dout[588:0]" +Toggle 1to0 dout [93] "reg dout[588:0]" +Toggle 0to1 dout [94] "reg dout[588:0]" +Toggle 1to0 dout [94] "reg dout[588:0]" +Toggle 0to1 dout [76] "reg dout[588:0]" +Toggle 1to0 dout [76] "reg dout[588:0]" +Toggle 0to1 dout [72] "reg dout[588:0]" +Toggle 1to0 dout [72] "reg dout[588:0]" +Toggle 0to1 dout [73] "reg dout[588:0]" +Toggle 1to0 dout [73] "reg dout[588:0]" +Toggle 0to1 dout [74] "reg dout[588:0]" +Toggle 1to0 dout [74] "reg dout[588:0]" +Toggle 0to1 dout [75] "reg dout[588:0]" +Toggle 1to0 dout [75] "reg dout[588:0]" +Toggle 0to1 dout [71] "reg dout[588:0]" +Toggle 1to0 dout [71] "reg dout[588:0]" +Toggle 0to1 dout [65] "reg dout[588:0]" +Toggle 1to0 dout [65] "reg dout[588:0]" +Toggle 0to1 dout [2] "reg dout[588:0]" +Toggle 1to0 dout [2] "reg dout[588:0]" +Toggle 0to1 dout [3] "reg dout[588:0]" +Toggle 1to0 dout [3] "reg dout[588:0]" +Toggle 0to1 dout [4] "reg dout[588:0]" +Toggle 1to0 dout [4] "reg dout[588:0]" +Toggle 0to1 dout [5] "reg dout[588:0]" +Toggle 1to0 dout [5] "reg dout[588:0]" +Toggle 0to1 dout [6] "reg dout[588:0]" +Toggle 1to0 dout [6] "reg dout[588:0]" +Toggle 0to1 dout [7] "reg dout[588:0]" +Toggle 1to0 dout [7] "reg dout[588:0]" +Toggle 0to1 dout [8] "reg dout[588:0]" +Toggle 1to0 dout [8] "reg dout[588:0]" +Toggle 0to1 dout [9] "reg dout[588:0]" +Toggle 1to0 dout [9] "reg dout[588:0]" +Toggle 0to1 dout [10] "reg dout[588:0]" +Toggle 1to0 dout [10] "reg dout[588:0]" +Toggle 0to1 dout [11] "reg dout[588:0]" +Toggle 1to0 dout [11] "reg dout[588:0]" +Toggle 0to1 dout [12] "reg dout[588:0]" +Toggle 1to0 dout [12] "reg dout[588:0]" +Toggle 0to1 dout [13] "reg dout[588:0]" +Toggle 1to0 dout [13] "reg dout[588:0]" +Toggle 0to1 dout [14] "reg dout[588:0]" +Toggle 1to0 dout [14] "reg dout[588:0]" +Toggle 0to1 dout [15] "reg dout[588:0]" +Toggle 1to0 dout [15] "reg dout[588:0]" +Toggle 0to1 dout [16] "reg dout[588:0]" +Toggle 1to0 dout [16] "reg dout[588:0]" +Toggle 0to1 dout [17] "reg dout[588:0]" +Toggle 1to0 dout [17] "reg dout[588:0]" +Toggle 0to1 dout [18] "reg dout[588:0]" +Toggle 1to0 dout [18] "reg dout[588:0]" +Toggle 0to1 dout [19] "reg dout[588:0]" +Toggle 1to0 dout [19] "reg dout[588:0]" +Toggle 0to1 dout [20] "reg dout[588:0]" +Toggle 1to0 dout [20] "reg dout[588:0]" +Toggle 0to1 dout [21] "reg dout[588:0]" +Toggle 1to0 dout [21] "reg dout[588:0]" +Toggle 0to1 dout [22] "reg dout[588:0]" +Toggle 1to0 dout [22] "reg dout[588:0]" +Toggle 0to1 dout [23] "reg dout[588:0]" +Toggle 1to0 dout [23] "reg dout[588:0]" +Toggle 0to1 dout [24] "reg dout[588:0]" +Toggle 1to0 dout [24] "reg dout[588:0]" +Toggle 0to1 dout [25] "reg dout[588:0]" +Toggle 1to0 dout [25] "reg dout[588:0]" +Toggle 0to1 dout [26] "reg dout[588:0]" +Toggle 1to0 dout [26] "reg dout[588:0]" +Toggle 0to1 dout [27] "reg dout[588:0]" +Toggle 1to0 dout [27] "reg dout[588:0]" +Toggle 0to1 dout [28] "reg dout[588:0]" +Toggle 1to0 dout [28] "reg dout[588:0]" +Toggle 0to1 dout [29] "reg dout[588:0]" +Toggle 1to0 dout [29] "reg dout[588:0]" +Toggle 0to1 dout [31] "reg dout[588:0]" +Toggle 1to0 dout [31] "reg dout[588:0]" +Toggle 0to1 dout [32] "reg dout[588:0]" +Toggle 1to0 dout [32] "reg dout[588:0]" +Toggle 0to1 dout [33] "reg dout[588:0]" +Toggle 1to0 dout [33] "reg dout[588:0]" +Toggle 0to1 dout [34] "reg dout[588:0]" +Toggle 1to0 dout [34] "reg dout[588:0]" +Toggle 0to1 dout [35] "reg dout[588:0]" +Toggle 1to0 dout [35] "reg dout[588:0]" +Toggle 0to1 dout [48] "reg dout[588:0]" +Toggle 1to0 dout [48] "reg dout[588:0]" +Toggle 0to1 dout [49] "reg dout[588:0]" +Toggle 1to0 dout [49] "reg dout[588:0]" +Toggle 0to1 dout [50] "reg dout[588:0]" +Toggle 1to0 dout [50] "reg dout[588:0]" +Toggle 0to1 dout [51] "reg dout[588:0]" +Toggle 1to0 dout [51] "reg dout[588:0]" +Toggle 0to1 dout [52] "reg dout[588:0]" +Toggle 1to0 dout [52] "reg dout[588:0]" +Toggle 0to1 dout [53] "reg dout[588:0]" +Toggle 1to0 dout [53] "reg dout[588:0]" +Toggle 0to1 dout [54] "reg dout[588:0]" +Toggle 1to0 dout [54] "reg dout[588:0]" +Toggle 0to1 dout [55] "reg dout[588:0]" +Toggle 1to0 dout [55] "reg dout[588:0]" +Toggle 0to1 dout [56] "reg dout[588:0]" +Toggle 1to0 dout [56] "reg dout[588:0]" +Toggle 0to1 dout [57] "reg dout[588:0]" +Toggle 1to0 dout [57] "reg dout[588:0]" +Toggle 0to1 dout [58] "reg dout[588:0]" +Toggle 1to0 dout [58] "reg dout[588:0]" +Toggle 0to1 dout [59] "reg dout[588:0]" +Toggle 1to0 dout [59] "reg dout[588:0]" +Toggle 0to1 dout [60] "reg dout[588:0]" +Toggle 1to0 dout [60] "reg dout[588:0]" +Toggle 0to1 dout [61] "reg dout[588:0]" +Toggle 1to0 dout [61] "reg dout[588:0]" +Toggle 0to1 dout [62] "reg dout[588:0]" +Toggle 1to0 dout [62] "reg dout[588:0]" +Toggle 0to1 dout [63] "reg dout[588:0]" +Toggle 1to0 dout [63] "reg dout[588:0]" +Toggle 0to1 dout [64] "reg dout[588:0]" +Toggle 1to0 dout [64] "reg dout[588:0]" +Toggle 0to1 driveX "reg driveX" +Toggle 1to0 driveX "reg driveX" +Toggle ram_dout "reg ram_dout[588:0]" +Toggle 0to1 raddr_q [0] "reg raddr_q[0:0]" +Toggle 1to0 raddr_q [0] "reg raddr_q[0:0]" +CHECKSUM: "1110801996 542254858" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[0] +Toggle 0to1 out_q_perr "logic out_q_perr" +Toggle 1to0 out_q_perr "logic out_q_perr" +CHECKSUM: "1110801996 542254858" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a.switch.N_mux[0] +Toggle 0to1 out_q_full "logic out_q_full" +Toggle 1to0 out_q_full "logic out_q_full" +Toggle 0to1 select [0] "logic select[0:0]" +Toggle 1to0 select [0] "logic select[0:0]" +Toggle 0to1 select_q [0] "logic select_q[0:0]" +Toggle 1to0 select_q [0] "logic select_q[0:0]" +Toggle 0to1 out_q_perr "logic out_q_perr" +Toggle 1to0 out_q_perr "logic out_q_perr" +Toggle 0to1 out_q_err "logic out_q_err" +Toggle 1to0 out_q_err "logic out_q_err" +CHECKSUM: "1110801996 542254858" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a.switch.N_mux[1] +Toggle 0to1 select_q [0] "logic select_q[0:0]" +Toggle 1to0 select_q [0] "logic select_q[0:0]" +Toggle 0to1 out_q_err "logic out_q_err" +Toggle 1to0 out_q_err "logic out_q_err" +Toggle 0to1 out_q_perr "logic out_q_perr" +Toggle 1to0 out_q_perr "logic out_q_perr" +Toggle 0to1 select [0] "logic select[0:0]" +Toggle 1to0 select [0] "logic select[0:0]" +CHECKSUM: "1110801996 542254858" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a.switch.N_mux[2] +Toggle 0to1 out_q_err "logic out_q_err" +Toggle 1to0 out_q_err "logic out_q_err" +Toggle 0to1 select_q [0] "logic select_q[0:0]" +Toggle 1to0 select_q [0] "logic select_q[0:0]" +Toggle 0to1 select_en "logic select_en" +Toggle 1to0 select_en "logic select_en" +Toggle 0to1 select [0] "logic select[0:0]" +Toggle 1to0 select [0] "logic select[0:0]" +Toggle 0to1 out_q_perr "logic out_q_perr" +Toggle 1to0 out_q_perr "logic out_q_perr" +Toggle 0to1 out_q_full "logic out_q_full" +Toggle 1to0 out_q_full "logic out_q_full" +CHECKSUM: "1110801996 542254858" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a.switch.N_mux[3] +Toggle 0to1 out_q_err "logic out_q_err" +Toggle 1to0 out_q_err "logic out_q_err" +Toggle 0to1 select_q [0] "logic select_q[0:0]" +Toggle 1to0 select_q [0] "logic select_q[0:0]" +Toggle 0to1 select_en "logic select_en" +Toggle 1to0 select_en "logic select_en" +Toggle 0to1 select [0] "logic select[0:0]" +Toggle 1to0 select [0] "logic select[0:0]" +Toggle 0to1 out_q_perr "logic out_q_perr" +Toggle 1to0 out_q_perr "logic out_q_perr" +Toggle 0to1 out_q_full "logic out_q_full" +Toggle 1to0 out_q_full "logic out_q_full" +CHECKSUM: "1110801996 542254858" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[1] +Toggle 0to1 out_q_perr "logic out_q_perr" +Toggle 1to0 out_q_perr "logic out_q_perr" +CHECKSUM: "1110801996 542254858" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[2] +Toggle 0to1 out_q_perr "logic out_q_perr" +Toggle 1to0 out_q_perr "logic out_q_perr" +CHECKSUM: "1110801996 542254858" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[3] +Toggle 0to1 out_q_perr "logic out_q_perr" +Toggle 1to0 out_q_perr "logic out_q_perr" +CHECKSUM: "1110801996 227967188" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_b.switch.M_mux[0] +Toggle 0to1 out_q_perr "logic out_q_perr" +Toggle 1to0 out_q_perr "logic out_q_perr" +CHECKSUM: "3308023931 265358504" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_b.switch +Toggle 0to1 M_out_q_perr [0] "logic M_out_q_perr[0:0]" +Toggle 1to0 M_out_q_perr [0] "logic M_out_q_perr[0:0]" +Toggle 0to1 out_q_perr "logic out_q_perr" +Toggle 1to0 out_q_perr "logic out_q_perr" +Toggle N_out_q_perr "logic N_out_q_perr[3:0]" +CHECKSUM: "2005438484 1461518658" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a +Toggle 0to1 out_q_perr "logic out_q_perr" +Toggle 1to0 out_q_perr "logic out_q_perr" +Toggle 0to1 out_fifo_err "logic out_fifo_err" +Toggle 1to0 out_fifo_err "logic out_fifo_err" +Toggle 0to1 out_fifo_perr "logic out_fifo_perr" +Toggle 1to0 out_fifo_perr "logic out_fifo_perr" +Toggle 0to1 out_q_err "logic out_q_err" +Toggle 1to0 out_q_err "logic out_q_err" +CHECKSUM: "2005438484 1461518658" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_b +Toggle 0to1 out_q_perr "logic out_q_perr" +Toggle 1to0 out_q_perr "logic out_q_perr" +CHECKSUM: "4144234428 2546017566" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a.switch.N_mux[2].out_q +Toggle 0to1 fifo_err "reg fifo_err" +Toggle 1to0 fifo_err "reg fifo_err" +Toggle 0to1 fifo_in_q [384] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [384] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [385] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [385] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [386] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [386] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [387] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [387] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [388] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [388] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [389] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [389] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [390] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [390] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [391] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [391] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [392] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [392] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [393] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [393] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [394] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [394] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [395] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [395] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [396] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [396] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [397] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [397] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [398] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [398] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [399] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [399] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [400] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [400] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [401] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [401] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [402] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [402] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [403] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [403] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [404] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [404] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [405] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [405] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [406] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [406] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [407] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [407] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [408] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [408] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [409] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [409] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [410] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [410] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [411] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [411] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [412] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [412] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [413] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [413] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [414] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [414] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [415] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [415] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [416] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [416] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [417] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [417] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [418] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [418] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [419] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [419] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [420] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [420] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [421] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [421] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [422] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [422] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [423] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [423] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [424] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [424] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [425] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [425] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [426] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [426] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [427] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [427] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [428] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [428] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [429] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [429] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [430] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [430] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [431] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [431] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [432] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [432] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [433] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [433] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [434] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [434] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [435] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [435] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [436] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [436] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [437] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [437] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [438] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [438] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [439] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [439] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [440] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [440] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [441] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [441] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [442] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [442] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [443] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [443] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [444] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [444] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [445] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [445] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [446] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [446] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [447] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [447] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [448] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [448] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [449] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [449] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [450] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [450] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [451] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [451] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [452] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [452] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [453] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [453] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [454] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [454] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [455] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [455] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [456] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [456] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [457] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [457] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [458] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [458] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [459] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [459] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [460] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [460] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [461] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [461] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [462] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [462] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [463] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [463] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [464] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [464] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [465] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [465] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [466] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [466] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [467] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [467] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [468] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [468] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [469] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [469] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [470] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [470] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [471] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [471] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [472] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [472] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [473] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [473] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [474] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [474] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [475] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [475] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [476] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [476] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [477] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [477] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [478] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [478] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [479] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [479] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [480] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [480] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [481] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [481] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [482] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [482] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [483] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [483] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [484] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [484] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [485] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [485] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [486] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [486] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [487] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [487] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [488] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [488] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [489] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [489] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [490] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [490] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [491] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [491] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [492] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [492] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [493] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [493] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [494] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [494] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [495] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [495] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [496] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [496] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [497] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [497] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [498] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [498] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [499] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [499] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [500] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [500] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [501] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [501] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [502] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [502] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [503] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [503] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [504] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [504] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [505] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [505] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [506] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [506] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [507] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [507] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [508] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [508] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [509] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [509] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [510] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [510] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [511] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [511] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [512] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [512] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [513] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [513] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [514] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [514] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [515] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [515] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [516] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [516] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [517] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [517] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [518] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [518] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [519] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [519] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [520] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [520] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [521] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [521] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [522] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [522] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [523] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [523] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [524] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [524] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [525] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [525] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [526] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [526] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [527] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [527] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [528] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [528] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [529] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [529] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [530] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [530] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [531] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [531] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [532] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [532] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [533] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [533] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [534] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [534] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [535] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [535] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [536] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [536] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [537] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [537] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [538] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [538] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [539] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [539] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [540] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [540] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [541] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [541] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [542] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [542] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [543] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [543] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [544] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [544] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [545] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [545] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [546] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [546] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [547] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [547] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [548] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [548] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [549] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [549] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [550] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [550] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [551] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [551] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [552] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [552] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [553] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [553] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [554] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [554] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [555] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [555] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [556] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [556] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [557] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [557] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [558] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [558] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [559] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [559] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [560] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [560] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [565] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [565] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [566] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [566] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [567] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [567] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [568] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [568] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [569] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [569] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [570] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [570] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [571] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [571] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [572] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [572] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [573] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [573] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [574] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [574] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [575] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [575] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [576] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [576] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [577] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [577] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [578] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [578] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [579] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [579] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [580] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [580] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [581] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [581] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [582] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [582] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [583] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [583] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [584] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [584] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [585] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [585] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [586] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [586] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [587] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [587] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [588] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [588] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [255] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [255] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [128] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [128] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [129] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [129] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [130] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [130] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [131] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [131] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [132] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [132] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [133] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [133] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [134] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [134] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [135] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [135] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [136] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [136] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [137] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [137] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [138] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [138] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [139] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [139] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [140] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [140] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [141] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [141] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [142] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [142] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [143] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [143] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [144] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [144] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [145] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [145] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [146] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [146] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [147] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [147] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [148] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [148] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [149] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [149] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [150] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [150] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [151] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [151] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [152] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [152] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [153] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [153] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [154] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [154] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [155] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [155] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [156] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [156] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [157] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [157] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [158] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [158] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [159] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [159] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [160] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [160] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [161] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [161] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [162] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [162] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [163] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [163] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [164] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [164] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [165] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [165] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [166] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [166] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [167] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [167] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [168] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [168] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [169] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [169] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [170] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [170] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [171] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [171] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [172] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [172] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [173] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [173] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [174] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [174] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [175] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [175] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [176] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [176] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [177] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [177] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [178] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [178] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [179] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [179] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [180] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [180] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [181] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [181] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [182] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [182] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [183] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [183] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [184] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [184] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [185] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [185] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [186] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [186] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [187] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [187] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [188] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [188] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [189] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [189] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [190] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [190] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [191] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [191] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [192] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [192] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [193] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [193] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [194] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [194] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [195] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [195] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [196] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [196] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [197] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [197] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [198] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [198] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [199] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [199] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [200] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [200] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [201] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [201] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [202] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [202] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [203] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [203] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [204] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [204] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [205] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [205] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [206] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [206] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [207] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [207] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [208] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [208] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [209] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [209] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [210] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [210] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [211] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [211] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [212] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [212] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [213] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [213] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [214] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [214] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [215] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [215] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [216] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [216] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [217] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [217] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [218] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [218] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [219] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [219] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [220] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [220] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [221] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [221] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [222] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [222] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [223] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [223] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [224] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [224] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [225] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [225] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [226] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [226] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [227] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [227] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [228] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [228] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [229] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [229] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [230] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [230] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [231] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [231] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [232] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [232] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [233] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [233] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [234] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [234] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [235] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [235] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [236] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [236] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [237] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [237] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [238] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [238] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [239] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [239] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [240] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [240] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [241] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [241] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [242] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [242] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [243] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [243] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [244] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [244] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [245] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [245] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [246] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [246] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [247] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [247] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [248] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [248] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [249] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [249] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [250] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [250] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [251] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [251] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [252] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [252] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [253] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [253] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [254] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [254] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [127] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [127] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [112] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [112] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [113] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [113] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [114] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [114] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [115] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [115] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [116] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [116] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [117] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [117] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [118] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [118] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [119] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [119] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [120] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [120] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [121] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [121] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [122] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [122] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [123] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [123] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [124] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [124] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [125] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [125] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [126] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [126] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_perr "net fifo_perr" +Toggle 1to0 fifo_perr "net fifo_perr" +Toggle ram_out_q "reg ram_out_q[588:0]" +Toggle 0to1 perr_en_q "reg perr_en_q" +Toggle 1to0 perr_en_q "reg perr_en_q" +Toggle 0to1 perr_en "reg perr_en" +Toggle 1to0 perr_en "reg perr_en" +Toggle 0to1 perr "net perr" +Toggle 1to0 perr "net perr" +Toggle 0to1 full "reg full" +Toggle 1to0 full "reg full" +Toggle 0to1 ram_out [588] "net ram_out[588:0]" +Toggle 1to0 ram_out [588] "net ram_out[588:0]" +Toggle 0to1 ram_out [112] "net ram_out[588:0]" +Toggle 1to0 ram_out [112] "net ram_out[588:0]" +Toggle 0to1 ram_out [113] "net ram_out[588:0]" +Toggle 1to0 ram_out [113] "net ram_out[588:0]" +Toggle 0to1 ram_out [114] "net ram_out[588:0]" +Toggle 1to0 ram_out [114] "net ram_out[588:0]" +Toggle 0to1 ram_out [115] "net ram_out[588:0]" +Toggle 1to0 ram_out [115] "net ram_out[588:0]" +Toggle 0to1 ram_out [116] "net ram_out[588:0]" +Toggle 1to0 ram_out [116] "net ram_out[588:0]" +Toggle 0to1 ram_out [117] "net ram_out[588:0]" +Toggle 1to0 ram_out [117] "net ram_out[588:0]" +Toggle 0to1 ram_out [118] "net ram_out[588:0]" +Toggle 1to0 ram_out [118] "net ram_out[588:0]" +Toggle 0to1 ram_out [119] "net ram_out[588:0]" +Toggle 1to0 ram_out [119] "net ram_out[588:0]" +Toggle 0to1 ram_out [120] "net ram_out[588:0]" +Toggle 1to0 ram_out [120] "net ram_out[588:0]" +Toggle 0to1 ram_out [121] "net ram_out[588:0]" +Toggle 1to0 ram_out [121] "net ram_out[588:0]" +Toggle 0to1 ram_out [122] "net ram_out[588:0]" +Toggle 1to0 ram_out [122] "net ram_out[588:0]" +Toggle 0to1 ram_out [123] "net ram_out[588:0]" +Toggle 1to0 ram_out [123] "net ram_out[588:0]" +Toggle 0to1 ram_out [124] "net ram_out[588:0]" +Toggle 1to0 ram_out [124] "net ram_out[588:0]" +Toggle 0to1 ram_out [125] "net ram_out[588:0]" +Toggle 1to0 ram_out [125] "net ram_out[588:0]" +Toggle 0to1 ram_out [126] "net ram_out[588:0]" +Toggle 1to0 ram_out [126] "net ram_out[588:0]" +Toggle 0to1 ram_out [127] "net ram_out[588:0]" +Toggle 1to0 ram_out [127] "net ram_out[588:0]" +Toggle 0to1 ram_out [128] "net ram_out[588:0]" +Toggle 1to0 ram_out [128] "net ram_out[588:0]" +Toggle 0to1 ram_out [129] "net ram_out[588:0]" +Toggle 1to0 ram_out [129] "net ram_out[588:0]" +Toggle 0to1 ram_out [130] "net ram_out[588:0]" +Toggle 1to0 ram_out [130] "net ram_out[588:0]" +Toggle 0to1 ram_out [131] "net ram_out[588:0]" +Toggle 1to0 ram_out [131] "net ram_out[588:0]" +Toggle 0to1 ram_out [132] "net ram_out[588:0]" +Toggle 1to0 ram_out [132] "net ram_out[588:0]" +Toggle 0to1 ram_out [133] "net ram_out[588:0]" +Toggle 1to0 ram_out [133] "net ram_out[588:0]" +Toggle 0to1 ram_out [134] "net ram_out[588:0]" +Toggle 1to0 ram_out [134] "net ram_out[588:0]" +Toggle 0to1 ram_out [135] "net ram_out[588:0]" +Toggle 1to0 ram_out [135] "net ram_out[588:0]" +Toggle 0to1 ram_out [136] "net ram_out[588:0]" +Toggle 1to0 ram_out [136] "net ram_out[588:0]" +Toggle 0to1 ram_out [137] "net ram_out[588:0]" +Toggle 1to0 ram_out [137] "net ram_out[588:0]" +Toggle 0to1 ram_out [138] "net ram_out[588:0]" +Toggle 1to0 ram_out [138] "net ram_out[588:0]" +Toggle 0to1 ram_out [139] "net ram_out[588:0]" +Toggle 1to0 ram_out [139] "net ram_out[588:0]" +Toggle 0to1 ram_out [140] "net ram_out[588:0]" +Toggle 1to0 ram_out [140] "net ram_out[588:0]" +Toggle 0to1 ram_out [141] "net ram_out[588:0]" +Toggle 1to0 ram_out [141] "net ram_out[588:0]" +Toggle 0to1 ram_out [142] "net ram_out[588:0]" +Toggle 1to0 ram_out [142] "net ram_out[588:0]" +Toggle 0to1 ram_out [143] "net ram_out[588:0]" +Toggle 1to0 ram_out [143] "net ram_out[588:0]" +Toggle 0to1 ram_out [144] "net ram_out[588:0]" +Toggle 1to0 ram_out [144] "net ram_out[588:0]" +Toggle 0to1 ram_out [145] "net ram_out[588:0]" +Toggle 1to0 ram_out [145] "net ram_out[588:0]" +Toggle 0to1 ram_out [146] "net ram_out[588:0]" +Toggle 1to0 ram_out [146] "net ram_out[588:0]" +Toggle 0to1 ram_out [147] "net ram_out[588:0]" +Toggle 1to0 ram_out [147] "net ram_out[588:0]" +Toggle 0to1 ram_out [148] "net ram_out[588:0]" +Toggle 1to0 ram_out [148] "net ram_out[588:0]" +Toggle 0to1 ram_out [149] "net ram_out[588:0]" +Toggle 1to0 ram_out [149] "net ram_out[588:0]" +Toggle 0to1 ram_out [150] "net ram_out[588:0]" +Toggle 1to0 ram_out [150] "net ram_out[588:0]" +Toggle 0to1 ram_out [151] "net ram_out[588:0]" +Toggle 1to0 ram_out [151] "net ram_out[588:0]" +Toggle 0to1 ram_out [152] "net ram_out[588:0]" +Toggle 1to0 ram_out [152] "net ram_out[588:0]" +Toggle 0to1 ram_out [153] "net ram_out[588:0]" +Toggle 1to0 ram_out [153] "net ram_out[588:0]" +Toggle 0to1 ram_out [154] "net ram_out[588:0]" +Toggle 1to0 ram_out [154] "net ram_out[588:0]" +Toggle 0to1 ram_out [155] "net ram_out[588:0]" +Toggle 1to0 ram_out [155] "net ram_out[588:0]" +Toggle 0to1 ram_out [156] "net ram_out[588:0]" +Toggle 1to0 ram_out [156] "net ram_out[588:0]" +Toggle 0to1 ram_out [157] "net ram_out[588:0]" +Toggle 1to0 ram_out [157] "net ram_out[588:0]" +Toggle 0to1 ram_out [158] "net ram_out[588:0]" +Toggle 1to0 ram_out [158] "net ram_out[588:0]" +Toggle 0to1 ram_out [159] "net ram_out[588:0]" +Toggle 1to0 ram_out [159] "net ram_out[588:0]" +Toggle 0to1 ram_out [160] "net ram_out[588:0]" +Toggle 1to0 ram_out [160] "net ram_out[588:0]" +Toggle 0to1 ram_out [161] "net ram_out[588:0]" +Toggle 1to0 ram_out [161] "net ram_out[588:0]" +Toggle 0to1 ram_out [162] "net ram_out[588:0]" +Toggle 1to0 ram_out [162] "net ram_out[588:0]" +Toggle 0to1 ram_out [163] "net ram_out[588:0]" +Toggle 1to0 ram_out [163] "net ram_out[588:0]" +Toggle 0to1 ram_out [164] "net ram_out[588:0]" +Toggle 1to0 ram_out [164] "net ram_out[588:0]" +Toggle 0to1 ram_out [165] "net ram_out[588:0]" +Toggle 1to0 ram_out [165] "net ram_out[588:0]" +Toggle 0to1 ram_out [166] "net ram_out[588:0]" +Toggle 1to0 ram_out [166] "net ram_out[588:0]" +Toggle 0to1 ram_out [167] "net ram_out[588:0]" +Toggle 1to0 ram_out [167] "net ram_out[588:0]" +Toggle 0to1 ram_out [168] "net ram_out[588:0]" +Toggle 1to0 ram_out [168] "net ram_out[588:0]" +Toggle 0to1 ram_out [169] "net ram_out[588:0]" +Toggle 1to0 ram_out [169] "net ram_out[588:0]" +Toggle 0to1 ram_out [170] "net ram_out[588:0]" +Toggle 1to0 ram_out [170] "net ram_out[588:0]" +Toggle 0to1 ram_out [171] "net ram_out[588:0]" +Toggle 1to0 ram_out [171] "net ram_out[588:0]" +Toggle 0to1 ram_out [172] "net ram_out[588:0]" +Toggle 1to0 ram_out [172] "net ram_out[588:0]" +Toggle 0to1 ram_out [173] "net ram_out[588:0]" +Toggle 1to0 ram_out [173] "net ram_out[588:0]" +Toggle 0to1 ram_out [174] "net ram_out[588:0]" +Toggle 1to0 ram_out [174] "net ram_out[588:0]" +Toggle 0to1 ram_out [175] "net ram_out[588:0]" +Toggle 1to0 ram_out [175] "net ram_out[588:0]" +Toggle 0to1 ram_out [176] "net ram_out[588:0]" +Toggle 1to0 ram_out [176] "net ram_out[588:0]" +Toggle 0to1 ram_out [177] "net ram_out[588:0]" +Toggle 1to0 ram_out [177] "net ram_out[588:0]" +Toggle 0to1 ram_out [178] "net ram_out[588:0]" +Toggle 1to0 ram_out [178] "net ram_out[588:0]" +Toggle 0to1 ram_out [179] "net ram_out[588:0]" +Toggle 1to0 ram_out [179] "net ram_out[588:0]" +Toggle 0to1 ram_out [180] "net ram_out[588:0]" +Toggle 1to0 ram_out [180] "net ram_out[588:0]" +Toggle 0to1 ram_out [181] "net ram_out[588:0]" +Toggle 1to0 ram_out [181] "net ram_out[588:0]" +Toggle 0to1 ram_out [182] "net ram_out[588:0]" +Toggle 1to0 ram_out [182] "net ram_out[588:0]" +Toggle 0to1 ram_out [183] "net ram_out[588:0]" +Toggle 1to0 ram_out [183] "net ram_out[588:0]" +Toggle 0to1 ram_out [184] "net ram_out[588:0]" +Toggle 1to0 ram_out [184] "net ram_out[588:0]" +Toggle 0to1 ram_out [185] "net ram_out[588:0]" +Toggle 1to0 ram_out [185] "net ram_out[588:0]" +Toggle 0to1 ram_out [186] "net ram_out[588:0]" +Toggle 1to0 ram_out [186] "net ram_out[588:0]" +Toggle 0to1 ram_out [187] "net ram_out[588:0]" +Toggle 1to0 ram_out [187] "net ram_out[588:0]" +Toggle 0to1 ram_out [188] "net ram_out[588:0]" +Toggle 1to0 ram_out [188] "net ram_out[588:0]" +Toggle 0to1 ram_out [189] "net ram_out[588:0]" +Toggle 1to0 ram_out [189] "net ram_out[588:0]" +Toggle 0to1 ram_out [190] "net ram_out[588:0]" +Toggle 1to0 ram_out [190] "net ram_out[588:0]" +Toggle 0to1 ram_out [191] "net ram_out[588:0]" +Toggle 1to0 ram_out [191] "net ram_out[588:0]" +Toggle 0to1 ram_out [192] "net ram_out[588:0]" +Toggle 1to0 ram_out [192] "net ram_out[588:0]" +Toggle 0to1 ram_out [193] "net ram_out[588:0]" +Toggle 1to0 ram_out [193] "net ram_out[588:0]" +Toggle 0to1 ram_out [194] "net ram_out[588:0]" +Toggle 1to0 ram_out [194] "net ram_out[588:0]" +Toggle 0to1 ram_out [195] "net ram_out[588:0]" +Toggle 1to0 ram_out [195] "net ram_out[588:0]" +Toggle 0to1 ram_out [196] "net ram_out[588:0]" +Toggle 1to0 ram_out [196] "net ram_out[588:0]" +Toggle 0to1 ram_out [197] "net ram_out[588:0]" +Toggle 1to0 ram_out [197] "net ram_out[588:0]" +Toggle 0to1 ram_out [198] "net ram_out[588:0]" +Toggle 1to0 ram_out [198] "net ram_out[588:0]" +Toggle 0to1 ram_out [199] "net ram_out[588:0]" +Toggle 1to0 ram_out [199] "net ram_out[588:0]" +Toggle 0to1 ram_out [200] "net ram_out[588:0]" +Toggle 1to0 ram_out [200] "net ram_out[588:0]" +Toggle 0to1 ram_out [201] "net ram_out[588:0]" +Toggle 1to0 ram_out [201] "net ram_out[588:0]" +Toggle 0to1 ram_out [202] "net ram_out[588:0]" +Toggle 1to0 ram_out [202] "net ram_out[588:0]" +Toggle 0to1 ram_out [203] "net ram_out[588:0]" +Toggle 1to0 ram_out [203] "net ram_out[588:0]" +Toggle 0to1 ram_out [204] "net ram_out[588:0]" +Toggle 1to0 ram_out [204] "net ram_out[588:0]" +Toggle 0to1 ram_out [205] "net ram_out[588:0]" +Toggle 1to0 ram_out [205] "net ram_out[588:0]" +Toggle 0to1 ram_out [206] "net ram_out[588:0]" +Toggle 1to0 ram_out [206] "net ram_out[588:0]" +Toggle 0to1 ram_out [207] "net ram_out[588:0]" +Toggle 1to0 ram_out [207] "net ram_out[588:0]" +Toggle 0to1 ram_out [208] "net ram_out[588:0]" +Toggle 1to0 ram_out [208] "net ram_out[588:0]" +Toggle 0to1 ram_out [209] "net ram_out[588:0]" +Toggle 1to0 ram_out [209] "net ram_out[588:0]" +Toggle 0to1 ram_out [210] "net ram_out[588:0]" +Toggle 1to0 ram_out [210] "net ram_out[588:0]" +Toggle 0to1 ram_out [211] "net ram_out[588:0]" +Toggle 1to0 ram_out [211] "net ram_out[588:0]" +Toggle 0to1 ram_out [212] "net ram_out[588:0]" +Toggle 1to0 ram_out [212] "net ram_out[588:0]" +Toggle 0to1 ram_out [213] "net ram_out[588:0]" +Toggle 1to0 ram_out [213] "net ram_out[588:0]" +Toggle 0to1 ram_out [214] "net ram_out[588:0]" +Toggle 1to0 ram_out [214] "net ram_out[588:0]" +Toggle 0to1 ram_out [215] "net ram_out[588:0]" +Toggle 1to0 ram_out [215] "net ram_out[588:0]" +Toggle 0to1 ram_out [216] "net ram_out[588:0]" +Toggle 1to0 ram_out [216] "net ram_out[588:0]" +Toggle 0to1 ram_out [217] "net ram_out[588:0]" +Toggle 1to0 ram_out [217] "net ram_out[588:0]" +Toggle 0to1 ram_out [218] "net ram_out[588:0]" +Toggle 1to0 ram_out [218] "net ram_out[588:0]" +Toggle 0to1 ram_out [219] "net ram_out[588:0]" +Toggle 1to0 ram_out [219] "net ram_out[588:0]" +Toggle 0to1 ram_out [220] "net ram_out[588:0]" +Toggle 1to0 ram_out [220] "net ram_out[588:0]" +Toggle 0to1 ram_out [221] "net ram_out[588:0]" +Toggle 1to0 ram_out [221] "net ram_out[588:0]" +Toggle 0to1 ram_out [222] "net ram_out[588:0]" +Toggle 1to0 ram_out [222] "net ram_out[588:0]" +Toggle 0to1 ram_out [223] "net ram_out[588:0]" +Toggle 1to0 ram_out [223] "net ram_out[588:0]" +Toggle 0to1 ram_out [224] "net ram_out[588:0]" +Toggle 1to0 ram_out [224] "net ram_out[588:0]" +Toggle 0to1 ram_out [225] "net ram_out[588:0]" +Toggle 1to0 ram_out [225] "net ram_out[588:0]" +Toggle 0to1 ram_out [226] "net ram_out[588:0]" +Toggle 1to0 ram_out [226] "net ram_out[588:0]" +Toggle 0to1 ram_out [227] "net ram_out[588:0]" +Toggle 1to0 ram_out [227] "net ram_out[588:0]" +Toggle 0to1 ram_out [228] "net ram_out[588:0]" +Toggle 1to0 ram_out [228] "net ram_out[588:0]" +Toggle 0to1 ram_out [229] "net ram_out[588:0]" +Toggle 1to0 ram_out [229] "net ram_out[588:0]" +Toggle 0to1 ram_out [230] "net ram_out[588:0]" +Toggle 1to0 ram_out [230] "net ram_out[588:0]" +Toggle 0to1 ram_out [231] "net ram_out[588:0]" +Toggle 1to0 ram_out [231] "net ram_out[588:0]" +Toggle 0to1 ram_out [232] "net ram_out[588:0]" +Toggle 1to0 ram_out [232] "net ram_out[588:0]" +Toggle 0to1 ram_out [233] "net ram_out[588:0]" +Toggle 1to0 ram_out [233] "net ram_out[588:0]" +Toggle 0to1 ram_out [234] "net ram_out[588:0]" +Toggle 1to0 ram_out [234] "net ram_out[588:0]" +Toggle 0to1 ram_out [235] "net ram_out[588:0]" +Toggle 1to0 ram_out [235] "net ram_out[588:0]" +Toggle 0to1 ram_out [236] "net ram_out[588:0]" +Toggle 1to0 ram_out [236] "net ram_out[588:0]" +Toggle 0to1 ram_out [237] "net ram_out[588:0]" +Toggle 1to0 ram_out [237] "net ram_out[588:0]" +Toggle 0to1 ram_out [238] "net ram_out[588:0]" +Toggle 1to0 ram_out [238] "net ram_out[588:0]" +Toggle 0to1 ram_out [239] "net ram_out[588:0]" +Toggle 1to0 ram_out [239] "net ram_out[588:0]" +Toggle 0to1 ram_out [240] "net ram_out[588:0]" +Toggle 1to0 ram_out [240] "net ram_out[588:0]" +Toggle 0to1 ram_out [241] "net ram_out[588:0]" +Toggle 1to0 ram_out [241] "net ram_out[588:0]" +Toggle 0to1 ram_out [242] "net ram_out[588:0]" +Toggle 1to0 ram_out [242] "net ram_out[588:0]" +Toggle 0to1 ram_out [243] "net ram_out[588:0]" +Toggle 1to0 ram_out [243] "net ram_out[588:0]" +Toggle 0to1 ram_out [244] "net ram_out[588:0]" +Toggle 1to0 ram_out [244] "net ram_out[588:0]" +Toggle 0to1 ram_out [245] "net ram_out[588:0]" +Toggle 1to0 ram_out [245] "net ram_out[588:0]" +Toggle 0to1 ram_out [246] "net ram_out[588:0]" +Toggle 1to0 ram_out [246] "net ram_out[588:0]" +Toggle 0to1 ram_out [247] "net ram_out[588:0]" +Toggle 1to0 ram_out [247] "net ram_out[588:0]" +Toggle 0to1 ram_out [248] "net ram_out[588:0]" +Toggle 1to0 ram_out [248] "net ram_out[588:0]" +Toggle 0to1 ram_out [249] "net ram_out[588:0]" +Toggle 1to0 ram_out [249] "net ram_out[588:0]" +Toggle 0to1 ram_out [250] "net ram_out[588:0]" +Toggle 1to0 ram_out [250] "net ram_out[588:0]" +Toggle 0to1 ram_out [251] "net ram_out[588:0]" +Toggle 1to0 ram_out [251] "net ram_out[588:0]" +Toggle 0to1 ram_out [252] "net ram_out[588:0]" +Toggle 1to0 ram_out [252] "net ram_out[588:0]" +Toggle 0to1 ram_out [253] "net ram_out[588:0]" +Toggle 1to0 ram_out [253] "net ram_out[588:0]" +Toggle 0to1 ram_out [254] "net ram_out[588:0]" +Toggle 1to0 ram_out [254] "net ram_out[588:0]" +Toggle 0to1 ram_out [255] "net ram_out[588:0]" +Toggle 1to0 ram_out [255] "net ram_out[588:0]" +Toggle 0to1 ram_out [384] "net ram_out[588:0]" +Toggle 1to0 ram_out [384] "net ram_out[588:0]" +Toggle 0to1 ram_out [385] "net ram_out[588:0]" +Toggle 1to0 ram_out [385] "net ram_out[588:0]" +Toggle 0to1 ram_out [386] "net ram_out[588:0]" +Toggle 1to0 ram_out [386] "net ram_out[588:0]" +Toggle 0to1 ram_out [387] "net ram_out[588:0]" +Toggle 1to0 ram_out [387] "net ram_out[588:0]" +Toggle 0to1 ram_out [388] "net ram_out[588:0]" +Toggle 1to0 ram_out [388] "net ram_out[588:0]" +Toggle 0to1 ram_out [389] "net ram_out[588:0]" +Toggle 1to0 ram_out [389] "net ram_out[588:0]" +Toggle 0to1 ram_out [390] "net ram_out[588:0]" +Toggle 1to0 ram_out [390] "net ram_out[588:0]" +Toggle 0to1 ram_out [391] "net ram_out[588:0]" +Toggle 1to0 ram_out [391] "net ram_out[588:0]" +Toggle 0to1 ram_out [392] "net ram_out[588:0]" +Toggle 1to0 ram_out [392] "net ram_out[588:0]" +Toggle 0to1 ram_out [393] "net ram_out[588:0]" +Toggle 1to0 ram_out [393] "net ram_out[588:0]" +Toggle 0to1 ram_out [394] "net ram_out[588:0]" +Toggle 1to0 ram_out [394] "net ram_out[588:0]" +Toggle 0to1 ram_out [395] "net ram_out[588:0]" +Toggle 1to0 ram_out [395] "net ram_out[588:0]" +Toggle 0to1 ram_out [396] "net ram_out[588:0]" +Toggle 1to0 ram_out [396] "net ram_out[588:0]" +Toggle 0to1 ram_out [397] "net ram_out[588:0]" +Toggle 1to0 ram_out [397] "net ram_out[588:0]" +Toggle 0to1 ram_out [398] "net ram_out[588:0]" +Toggle 1to0 ram_out [398] "net ram_out[588:0]" +Toggle 0to1 ram_out [399] "net ram_out[588:0]" +Toggle 1to0 ram_out [399] "net ram_out[588:0]" +Toggle 0to1 ram_out [400] "net ram_out[588:0]" +Toggle 1to0 ram_out [400] "net ram_out[588:0]" +Toggle 0to1 ram_out [401] "net ram_out[588:0]" +Toggle 1to0 ram_out [401] "net ram_out[588:0]" +Toggle 0to1 ram_out [402] "net ram_out[588:0]" +Toggle 1to0 ram_out [402] "net ram_out[588:0]" +Toggle 0to1 ram_out [403] "net ram_out[588:0]" +Toggle 1to0 ram_out [403] "net ram_out[588:0]" +Toggle 0to1 ram_out [404] "net ram_out[588:0]" +Toggle 1to0 ram_out [404] "net ram_out[588:0]" +Toggle 0to1 ram_out [405] "net ram_out[588:0]" +Toggle 1to0 ram_out [405] "net ram_out[588:0]" +Toggle 0to1 ram_out [406] "net ram_out[588:0]" +Toggle 1to0 ram_out [406] "net ram_out[588:0]" +Toggle 0to1 ram_out [407] "net ram_out[588:0]" +Toggle 1to0 ram_out [407] "net ram_out[588:0]" +Toggle 0to1 ram_out [408] "net ram_out[588:0]" +Toggle 1to0 ram_out [408] "net ram_out[588:0]" +Toggle 0to1 ram_out [409] "net ram_out[588:0]" +Toggle 1to0 ram_out [409] "net ram_out[588:0]" +Toggle 0to1 ram_out [410] "net ram_out[588:0]" +Toggle 1to0 ram_out [410] "net ram_out[588:0]" +Toggle 0to1 ram_out [411] "net ram_out[588:0]" +Toggle 1to0 ram_out [411] "net ram_out[588:0]" +Toggle 0to1 ram_out [412] "net ram_out[588:0]" +Toggle 1to0 ram_out [412] "net ram_out[588:0]" +Toggle 0to1 ram_out [413] "net ram_out[588:0]" +Toggle 1to0 ram_out [413] "net ram_out[588:0]" +Toggle 0to1 ram_out [414] "net ram_out[588:0]" +Toggle 1to0 ram_out [414] "net ram_out[588:0]" +Toggle 0to1 ram_out [415] "net ram_out[588:0]" +Toggle 1to0 ram_out [415] "net ram_out[588:0]" +Toggle 0to1 ram_out [416] "net ram_out[588:0]" +Toggle 1to0 ram_out [416] "net ram_out[588:0]" +Toggle 0to1 ram_out [417] "net ram_out[588:0]" +Toggle 1to0 ram_out [417] "net ram_out[588:0]" +Toggle 0to1 ram_out [418] "net ram_out[588:0]" +Toggle 1to0 ram_out [418] "net ram_out[588:0]" +Toggle 0to1 ram_out [419] "net ram_out[588:0]" +Toggle 1to0 ram_out [419] "net ram_out[588:0]" +Toggle 0to1 ram_out [420] "net ram_out[588:0]" +Toggle 1to0 ram_out [420] "net ram_out[588:0]" +Toggle 0to1 ram_out [421] "net ram_out[588:0]" +Toggle 1to0 ram_out [421] "net ram_out[588:0]" +Toggle 0to1 ram_out [422] "net ram_out[588:0]" +Toggle 1to0 ram_out [422] "net ram_out[588:0]" +Toggle 0to1 ram_out [423] "net ram_out[588:0]" +Toggle 1to0 ram_out [423] "net ram_out[588:0]" +Toggle 0to1 ram_out [424] "net ram_out[588:0]" +Toggle 1to0 ram_out [424] "net ram_out[588:0]" +Toggle 0to1 ram_out [425] "net ram_out[588:0]" +Toggle 1to0 ram_out [425] "net ram_out[588:0]" +Toggle 0to1 ram_out [426] "net ram_out[588:0]" +Toggle 1to0 ram_out [426] "net ram_out[588:0]" +Toggle 0to1 ram_out [427] "net ram_out[588:0]" +Toggle 1to0 ram_out [427] "net ram_out[588:0]" +Toggle 0to1 ram_out [428] "net ram_out[588:0]" +Toggle 1to0 ram_out [428] "net ram_out[588:0]" +Toggle 0to1 ram_out [429] "net ram_out[588:0]" +Toggle 1to0 ram_out [429] "net ram_out[588:0]" +Toggle 0to1 ram_out [430] "net ram_out[588:0]" +Toggle 1to0 ram_out [430] "net ram_out[588:0]" +Toggle 0to1 ram_out [431] "net ram_out[588:0]" +Toggle 1to0 ram_out [431] "net ram_out[588:0]" +Toggle 0to1 ram_out [432] "net ram_out[588:0]" +Toggle 1to0 ram_out [432] "net ram_out[588:0]" +Toggle 0to1 ram_out [433] "net ram_out[588:0]" +Toggle 1to0 ram_out [433] "net ram_out[588:0]" +Toggle 0to1 ram_out [434] "net ram_out[588:0]" +Toggle 1to0 ram_out [434] "net ram_out[588:0]" +Toggle 0to1 ram_out [435] "net ram_out[588:0]" +Toggle 1to0 ram_out [435] "net ram_out[588:0]" +Toggle 0to1 ram_out [436] "net ram_out[588:0]" +Toggle 1to0 ram_out [436] "net ram_out[588:0]" +Toggle 0to1 ram_out [437] "net ram_out[588:0]" +Toggle 1to0 ram_out [437] "net ram_out[588:0]" +Toggle 0to1 ram_out [438] "net ram_out[588:0]" +Toggle 1to0 ram_out [438] "net ram_out[588:0]" +Toggle 0to1 ram_out [439] "net ram_out[588:0]" +Toggle 1to0 ram_out [439] "net ram_out[588:0]" +Toggle 0to1 ram_out [440] "net ram_out[588:0]" +Toggle 1to0 ram_out [440] "net ram_out[588:0]" +Toggle 0to1 ram_out [441] "net ram_out[588:0]" +Toggle 1to0 ram_out [441] "net ram_out[588:0]" +Toggle 0to1 ram_out [442] "net ram_out[588:0]" +Toggle 1to0 ram_out [442] "net ram_out[588:0]" +Toggle 0to1 ram_out [443] "net ram_out[588:0]" +Toggle 1to0 ram_out [443] "net ram_out[588:0]" +Toggle 0to1 ram_out [444] "net ram_out[588:0]" +Toggle 1to0 ram_out [444] "net ram_out[588:0]" +Toggle 0to1 ram_out [445] "net ram_out[588:0]" +Toggle 1to0 ram_out [445] "net ram_out[588:0]" +Toggle 0to1 ram_out [446] "net ram_out[588:0]" +Toggle 1to0 ram_out [446] "net ram_out[588:0]" +Toggle 0to1 ram_out [447] "net ram_out[588:0]" +Toggle 1to0 ram_out [447] "net ram_out[588:0]" +Toggle 0to1 ram_out [448] "net ram_out[588:0]" +Toggle 1to0 ram_out [448] "net ram_out[588:0]" +Toggle 0to1 ram_out [449] "net ram_out[588:0]" +Toggle 1to0 ram_out [449] "net ram_out[588:0]" +Toggle 0to1 ram_out [450] "net ram_out[588:0]" +Toggle 1to0 ram_out [450] "net ram_out[588:0]" +Toggle 0to1 ram_out [451] "net ram_out[588:0]" +Toggle 1to0 ram_out [451] "net ram_out[588:0]" +Toggle 0to1 ram_out [452] "net ram_out[588:0]" +Toggle 1to0 ram_out [452] "net ram_out[588:0]" +Toggle 0to1 ram_out [453] "net ram_out[588:0]" +Toggle 1to0 ram_out [453] "net ram_out[588:0]" +Toggle 0to1 ram_out [454] "net ram_out[588:0]" +Toggle 1to0 ram_out [454] "net ram_out[588:0]" +Toggle 0to1 ram_out [455] "net ram_out[588:0]" +Toggle 1to0 ram_out [455] "net ram_out[588:0]" +Toggle 0to1 ram_out [456] "net ram_out[588:0]" +Toggle 1to0 ram_out [456] "net ram_out[588:0]" +Toggle 0to1 ram_out [457] "net ram_out[588:0]" +Toggle 1to0 ram_out [457] "net ram_out[588:0]" +Toggle 0to1 ram_out [458] "net ram_out[588:0]" +Toggle 1to0 ram_out [458] "net ram_out[588:0]" +Toggle 0to1 ram_out [459] "net ram_out[588:0]" +Toggle 1to0 ram_out [459] "net ram_out[588:0]" +Toggle 0to1 ram_out [460] "net ram_out[588:0]" +Toggle 1to0 ram_out [460] "net ram_out[588:0]" +Toggle 0to1 ram_out [461] "net ram_out[588:0]" +Toggle 1to0 ram_out [461] "net ram_out[588:0]" +Toggle 0to1 ram_out [462] "net ram_out[588:0]" +Toggle 1to0 ram_out [462] "net ram_out[588:0]" +Toggle 0to1 ram_out [463] "net ram_out[588:0]" +Toggle 1to0 ram_out [463] "net ram_out[588:0]" +Toggle 0to1 ram_out [464] "net ram_out[588:0]" +Toggle 1to0 ram_out [464] "net ram_out[588:0]" +Toggle 0to1 ram_out [465] "net ram_out[588:0]" +Toggle 1to0 ram_out [465] "net ram_out[588:0]" +Toggle 0to1 ram_out [466] "net ram_out[588:0]" +Toggle 1to0 ram_out [466] "net ram_out[588:0]" +Toggle 0to1 ram_out [467] "net ram_out[588:0]" +Toggle 1to0 ram_out [467] "net ram_out[588:0]" +Toggle 0to1 ram_out [468] "net ram_out[588:0]" +Toggle 1to0 ram_out [468] "net ram_out[588:0]" +Toggle 0to1 ram_out [469] "net ram_out[588:0]" +Toggle 1to0 ram_out [469] "net ram_out[588:0]" +Toggle 0to1 ram_out [470] "net ram_out[588:0]" +Toggle 1to0 ram_out [470] "net ram_out[588:0]" +Toggle 0to1 ram_out [471] "net ram_out[588:0]" +Toggle 1to0 ram_out [471] "net ram_out[588:0]" +Toggle 0to1 ram_out [472] "net ram_out[588:0]" +Toggle 1to0 ram_out [472] "net ram_out[588:0]" +Toggle 0to1 ram_out [473] "net ram_out[588:0]" +Toggle 1to0 ram_out [473] "net ram_out[588:0]" +Toggle 0to1 ram_out [474] "net ram_out[588:0]" +Toggle 1to0 ram_out [474] "net ram_out[588:0]" +Toggle 0to1 ram_out [475] "net ram_out[588:0]" +Toggle 1to0 ram_out [475] "net ram_out[588:0]" +Toggle 0to1 ram_out [476] "net ram_out[588:0]" +Toggle 1to0 ram_out [476] "net ram_out[588:0]" +Toggle 0to1 ram_out [477] "net ram_out[588:0]" +Toggle 1to0 ram_out [477] "net ram_out[588:0]" +Toggle 0to1 ram_out [478] "net ram_out[588:0]" +Toggle 1to0 ram_out [478] "net ram_out[588:0]" +Toggle 0to1 ram_out [479] "net ram_out[588:0]" +Toggle 1to0 ram_out [479] "net ram_out[588:0]" +Toggle 0to1 ram_out [480] "net ram_out[588:0]" +Toggle 1to0 ram_out [480] "net ram_out[588:0]" +Toggle 0to1 ram_out [481] "net ram_out[588:0]" +Toggle 1to0 ram_out [481] "net ram_out[588:0]" +Toggle 0to1 ram_out [482] "net ram_out[588:0]" +Toggle 1to0 ram_out [482] "net ram_out[588:0]" +Toggle 0to1 ram_out [483] "net ram_out[588:0]" +Toggle 1to0 ram_out [483] "net ram_out[588:0]" +Toggle 0to1 ram_out [484] "net ram_out[588:0]" +Toggle 1to0 ram_out [484] "net ram_out[588:0]" +Toggle 0to1 ram_out [485] "net ram_out[588:0]" +Toggle 1to0 ram_out [485] "net ram_out[588:0]" +Toggle 0to1 ram_out [486] "net ram_out[588:0]" +Toggle 1to0 ram_out [486] "net ram_out[588:0]" +Toggle 0to1 ram_out [487] "net ram_out[588:0]" +Toggle 1to0 ram_out [487] "net ram_out[588:0]" +Toggle 0to1 ram_out [488] "net ram_out[588:0]" +Toggle 1to0 ram_out [488] "net ram_out[588:0]" +Toggle 0to1 ram_out [489] "net ram_out[588:0]" +Toggle 1to0 ram_out [489] "net ram_out[588:0]" +Toggle 0to1 ram_out [490] "net ram_out[588:0]" +Toggle 1to0 ram_out [490] "net ram_out[588:0]" +Toggle 0to1 ram_out [491] "net ram_out[588:0]" +Toggle 1to0 ram_out [491] "net ram_out[588:0]" +Toggle 0to1 ram_out [492] "net ram_out[588:0]" +Toggle 1to0 ram_out [492] "net ram_out[588:0]" +Toggle 0to1 ram_out [493] "net ram_out[588:0]" +Toggle 1to0 ram_out [493] "net ram_out[588:0]" +Toggle 0to1 ram_out [494] "net ram_out[588:0]" +Toggle 1to0 ram_out [494] "net ram_out[588:0]" +Toggle 0to1 ram_out [495] "net ram_out[588:0]" +Toggle 1to0 ram_out [495] "net ram_out[588:0]" +Toggle 0to1 ram_out [496] "net ram_out[588:0]" +Toggle 1to0 ram_out [496] "net ram_out[588:0]" +Toggle 0to1 ram_out [497] "net ram_out[588:0]" +Toggle 1to0 ram_out [497] "net ram_out[588:0]" +Toggle 0to1 ram_out [498] "net ram_out[588:0]" +Toggle 1to0 ram_out [498] "net ram_out[588:0]" +Toggle 0to1 ram_out [499] "net ram_out[588:0]" +Toggle 1to0 ram_out [499] "net ram_out[588:0]" +Toggle 0to1 ram_out [500] "net ram_out[588:0]" +Toggle 1to0 ram_out [500] "net ram_out[588:0]" +Toggle 0to1 ram_out [501] "net ram_out[588:0]" +Toggle 1to0 ram_out [501] "net ram_out[588:0]" +Toggle 0to1 ram_out [502] "net ram_out[588:0]" +Toggle 1to0 ram_out [502] "net ram_out[588:0]" +Toggle 0to1 ram_out [503] "net ram_out[588:0]" +Toggle 1to0 ram_out [503] "net ram_out[588:0]" +Toggle 0to1 ram_out [504] "net ram_out[588:0]" +Toggle 1to0 ram_out [504] "net ram_out[588:0]" +Toggle 0to1 ram_out [505] "net ram_out[588:0]" +Toggle 1to0 ram_out [505] "net ram_out[588:0]" +Toggle 0to1 ram_out [506] "net ram_out[588:0]" +Toggle 1to0 ram_out [506] "net ram_out[588:0]" +Toggle 0to1 ram_out [507] "net ram_out[588:0]" +Toggle 1to0 ram_out [507] "net ram_out[588:0]" +Toggle 0to1 ram_out [508] "net ram_out[588:0]" +Toggle 1to0 ram_out [508] "net ram_out[588:0]" +Toggle 0to1 ram_out [509] "net ram_out[588:0]" +Toggle 1to0 ram_out [509] "net ram_out[588:0]" +Toggle 0to1 ram_out [510] "net ram_out[588:0]" +Toggle 1to0 ram_out [510] "net ram_out[588:0]" +Toggle 0to1 ram_out [511] "net ram_out[588:0]" +Toggle 1to0 ram_out [511] "net ram_out[588:0]" +Toggle 0to1 ram_out [512] "net ram_out[588:0]" +Toggle 1to0 ram_out [512] "net ram_out[588:0]" +Toggle 0to1 ram_out [513] "net ram_out[588:0]" +Toggle 1to0 ram_out [513] "net ram_out[588:0]" +Toggle 0to1 ram_out [514] "net ram_out[588:0]" +Toggle 1to0 ram_out [514] "net ram_out[588:0]" +Toggle 0to1 ram_out [515] "net ram_out[588:0]" +Toggle 1to0 ram_out [515] "net ram_out[588:0]" +Toggle 0to1 ram_out [516] "net ram_out[588:0]" +Toggle 1to0 ram_out [516] "net ram_out[588:0]" +Toggle 0to1 ram_out [517] "net ram_out[588:0]" +Toggle 1to0 ram_out [517] "net ram_out[588:0]" +Toggle 0to1 ram_out [518] "net ram_out[588:0]" +Toggle 1to0 ram_out [518] "net ram_out[588:0]" +Toggle 0to1 ram_out [519] "net ram_out[588:0]" +Toggle 1to0 ram_out [519] "net ram_out[588:0]" +Toggle 0to1 ram_out [520] "net ram_out[588:0]" +Toggle 1to0 ram_out [520] "net ram_out[588:0]" +Toggle 0to1 ram_out [521] "net ram_out[588:0]" +Toggle 1to0 ram_out [521] "net ram_out[588:0]" +Toggle 0to1 ram_out [522] "net ram_out[588:0]" +Toggle 1to0 ram_out [522] "net ram_out[588:0]" +Toggle 0to1 ram_out [523] "net ram_out[588:0]" +Toggle 1to0 ram_out [523] "net ram_out[588:0]" +Toggle 0to1 ram_out [524] "net ram_out[588:0]" +Toggle 1to0 ram_out [524] "net ram_out[588:0]" +Toggle 0to1 ram_out [525] "net ram_out[588:0]" +Toggle 1to0 ram_out [525] "net ram_out[588:0]" +Toggle 0to1 ram_out [526] "net ram_out[588:0]" +Toggle 1to0 ram_out [526] "net ram_out[588:0]" +Toggle 0to1 ram_out [527] "net ram_out[588:0]" +Toggle 1to0 ram_out [527] "net ram_out[588:0]" +Toggle 0to1 ram_out [528] "net ram_out[588:0]" +Toggle 1to0 ram_out [528] "net ram_out[588:0]" +Toggle 0to1 ram_out [529] "net ram_out[588:0]" +Toggle 1to0 ram_out [529] "net ram_out[588:0]" +Toggle 0to1 ram_out [530] "net ram_out[588:0]" +Toggle 1to0 ram_out [530] "net ram_out[588:0]" +Toggle 0to1 ram_out [531] "net ram_out[588:0]" +Toggle 1to0 ram_out [531] "net ram_out[588:0]" +Toggle 0to1 ram_out [532] "net ram_out[588:0]" +Toggle 1to0 ram_out [532] "net ram_out[588:0]" +Toggle 0to1 ram_out [533] "net ram_out[588:0]" +Toggle 1to0 ram_out [533] "net ram_out[588:0]" +Toggle 0to1 ram_out [534] "net ram_out[588:0]" +Toggle 1to0 ram_out [534] "net ram_out[588:0]" +Toggle 0to1 ram_out [535] "net ram_out[588:0]" +Toggle 1to0 ram_out [535] "net ram_out[588:0]" +Toggle 0to1 ram_out [536] "net ram_out[588:0]" +Toggle 1to0 ram_out [536] "net ram_out[588:0]" +Toggle 0to1 ram_out [537] "net ram_out[588:0]" +Toggle 1to0 ram_out [537] "net ram_out[588:0]" +Toggle 0to1 ram_out [538] "net ram_out[588:0]" +Toggle 1to0 ram_out [538] "net ram_out[588:0]" +Toggle 0to1 ram_out [539] "net ram_out[588:0]" +Toggle 1to0 ram_out [539] "net ram_out[588:0]" +Toggle 0to1 ram_out [540] "net ram_out[588:0]" +Toggle 1to0 ram_out [540] "net ram_out[588:0]" +Toggle 0to1 ram_out [541] "net ram_out[588:0]" +Toggle 1to0 ram_out [541] "net ram_out[588:0]" +Toggle 0to1 ram_out [542] "net ram_out[588:0]" +Toggle 1to0 ram_out [542] "net ram_out[588:0]" +Toggle 0to1 ram_out [543] "net ram_out[588:0]" +Toggle 1to0 ram_out [543] "net ram_out[588:0]" +Toggle 0to1 ram_out [544] "net ram_out[588:0]" +Toggle 1to0 ram_out [544] "net ram_out[588:0]" +Toggle 0to1 ram_out [545] "net ram_out[588:0]" +Toggle 1to0 ram_out [545] "net ram_out[588:0]" +Toggle 0to1 ram_out [546] "net ram_out[588:0]" +Toggle 1to0 ram_out [546] "net ram_out[588:0]" +Toggle 0to1 ram_out [547] "net ram_out[588:0]" +Toggle 1to0 ram_out [547] "net ram_out[588:0]" +Toggle 0to1 ram_out [548] "net ram_out[588:0]" +Toggle 1to0 ram_out [548] "net ram_out[588:0]" +Toggle 0to1 ram_out [549] "net ram_out[588:0]" +Toggle 1to0 ram_out [549] "net ram_out[588:0]" +Toggle 0to1 ram_out [550] "net ram_out[588:0]" +Toggle 1to0 ram_out [550] "net ram_out[588:0]" +Toggle 0to1 ram_out [551] "net ram_out[588:0]" +Toggle 1to0 ram_out [551] "net ram_out[588:0]" +Toggle 0to1 ram_out [552] "net ram_out[588:0]" +Toggle 1to0 ram_out [552] "net ram_out[588:0]" +Toggle 0to1 ram_out [553] "net ram_out[588:0]" +Toggle 1to0 ram_out [553] "net ram_out[588:0]" +Toggle 0to1 ram_out [554] "net ram_out[588:0]" +Toggle 1to0 ram_out [554] "net ram_out[588:0]" +Toggle 0to1 ram_out [555] "net ram_out[588:0]" +Toggle 1to0 ram_out [555] "net ram_out[588:0]" +Toggle 0to1 ram_out [556] "net ram_out[588:0]" +Toggle 1to0 ram_out [556] "net ram_out[588:0]" +Toggle 0to1 ram_out [557] "net ram_out[588:0]" +Toggle 1to0 ram_out [557] "net ram_out[588:0]" +Toggle 0to1 ram_out [558] "net ram_out[588:0]" +Toggle 1to0 ram_out [558] "net ram_out[588:0]" +Toggle 0to1 ram_out [559] "net ram_out[588:0]" +Toggle 1to0 ram_out [559] "net ram_out[588:0]" +Toggle 0to1 ram_out [560] "net ram_out[588:0]" +Toggle 1to0 ram_out [560] "net ram_out[588:0]" +Toggle 0to1 ram_out [565] "net ram_out[588:0]" +Toggle 1to0 ram_out [565] "net ram_out[588:0]" +Toggle 0to1 ram_out [566] "net ram_out[588:0]" +Toggle 1to0 ram_out [566] "net ram_out[588:0]" +Toggle 0to1 ram_out [567] "net ram_out[588:0]" +Toggle 1to0 ram_out [567] "net ram_out[588:0]" +Toggle 0to1 ram_out [568] "net ram_out[588:0]" +Toggle 1to0 ram_out [568] "net ram_out[588:0]" +Toggle 0to1 ram_out [569] "net ram_out[588:0]" +Toggle 1to0 ram_out [569] "net ram_out[588:0]" +Toggle 0to1 ram_out [570] "net ram_out[588:0]" +Toggle 1to0 ram_out [570] "net ram_out[588:0]" +Toggle 0to1 ram_out [571] "net ram_out[588:0]" +Toggle 1to0 ram_out [571] "net ram_out[588:0]" +Toggle 0to1 ram_out [572] "net ram_out[588:0]" +Toggle 1to0 ram_out [572] "net ram_out[588:0]" +Toggle 0to1 ram_out [573] "net ram_out[588:0]" +Toggle 1to0 ram_out [573] "net ram_out[588:0]" +Toggle 0to1 ram_out [574] "net ram_out[588:0]" +Toggle 1to0 ram_out [574] "net ram_out[588:0]" +Toggle 0to1 ram_out [575] "net ram_out[588:0]" +Toggle 1to0 ram_out [575] "net ram_out[588:0]" +Toggle 0to1 ram_out [576] "net ram_out[588:0]" +Toggle 1to0 ram_out [576] "net ram_out[588:0]" +Toggle 0to1 ram_out [577] "net ram_out[588:0]" +Toggle 1to0 ram_out [577] "net ram_out[588:0]" +Toggle 0to1 ram_out [578] "net ram_out[588:0]" +Toggle 1to0 ram_out [578] "net ram_out[588:0]" +Toggle 0to1 ram_out [579] "net ram_out[588:0]" +Toggle 1to0 ram_out [579] "net ram_out[588:0]" +Toggle 0to1 ram_out [580] "net ram_out[588:0]" +Toggle 1to0 ram_out [580] "net ram_out[588:0]" +Toggle 0to1 ram_out [581] "net ram_out[588:0]" +Toggle 1to0 ram_out [581] "net ram_out[588:0]" +Toggle 0to1 ram_out [582] "net ram_out[588:0]" +Toggle 1to0 ram_out [582] "net ram_out[588:0]" +Toggle 0to1 ram_out [583] "net ram_out[588:0]" +Toggle 1to0 ram_out [583] "net ram_out[588:0]" +Toggle 0to1 ram_out [584] "net ram_out[588:0]" +Toggle 1to0 ram_out [584] "net ram_out[588:0]" +Toggle 0to1 ram_out [585] "net ram_out[588:0]" +Toggle 1to0 ram_out [585] "net ram_out[588:0]" +Toggle 0to1 ram_out [586] "net ram_out[588:0]" +Toggle 1to0 ram_out [586] "net ram_out[588:0]" +Toggle 0to1 ram_out [587] "net ram_out[588:0]" +Toggle 1to0 ram_out [587] "net ram_out[588:0]" +CHECKSUM: "4144234428 2546017566" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a.switch.M_mux[0].out_q +Toggle 0to1 fifo_err "reg fifo_err" +Toggle 1to0 fifo_err "reg fifo_err" +Toggle ram_out_q "reg ram_out_q[588:0]" +Toggle 0to1 perr_en_q "reg perr_en_q" +Toggle 1to0 perr_en_q "reg perr_en_q" +Toggle 0to1 perr_en "reg perr_en" +Toggle 1to0 perr_en "reg perr_en" +Toggle 0to1 perr "net perr" +Toggle 1to0 perr "net perr" +Toggle 0to1 fifo_perr "net fifo_perr" +Toggle 1to0 fifo_perr "net fifo_perr" +CHECKSUM: "4144234428 2546017566" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a.switch.N_mux[0].out_q +Toggle 0to1 fifo_err "reg fifo_err" +Toggle 1to0 fifo_err "reg fifo_err" +Toggle 0to1 fifo_in_q [533] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [533] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [516] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [516] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [517] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [517] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [518] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [518] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [531] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [531] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [530] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [530] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [528] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [528] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [527] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [527] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [526] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [526] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [522] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [522] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [523] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [523] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [524] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [524] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [519] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [519] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [520] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [520] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [521] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [521] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [525] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [525] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [529] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [529] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [532] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [532] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [536] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [536] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [535] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [535] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [534] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [534] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_perr "net fifo_perr" +Toggle 1to0 fifo_perr "net fifo_perr" +Toggle 0to1 fifo_in_q [515] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [515] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [512] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [512] "reg fifo_in_q[588:0]" +Toggle 0to1 full "reg full" +Toggle 1to0 full "reg full" +Toggle ram_out_q "reg ram_out_q[588:0]" +Toggle 0to1 perr_en_q "reg perr_en_q" +Toggle 1to0 perr_en_q "reg perr_en_q" +Toggle 0to1 perr_en "reg perr_en" +Toggle 1to0 perr_en "reg perr_en" +Toggle 0to1 perr "net perr" +Toggle 1to0 perr "net perr" +Toggle 0to1 ram_out [512] "net ram_out[588:0]" +Toggle 1to0 ram_out [512] "net ram_out[588:0]" +Toggle 0to1 ram_out [515] "net ram_out[588:0]" +Toggle 1to0 ram_out [515] "net ram_out[588:0]" +Toggle 0to1 ram_out [536] "net ram_out[588:0]" +Toggle 1to0 ram_out [536] "net ram_out[588:0]" +Toggle 0to1 ram_out [516] "net ram_out[588:0]" +Toggle 1to0 ram_out [516] "net ram_out[588:0]" +Toggle 0to1 ram_out [517] "net ram_out[588:0]" +Toggle 1to0 ram_out [517] "net ram_out[588:0]" +Toggle 0to1 ram_out [518] "net ram_out[588:0]" +Toggle 1to0 ram_out [518] "net ram_out[588:0]" +Toggle 0to1 ram_out [519] "net ram_out[588:0]" +Toggle 1to0 ram_out [519] "net ram_out[588:0]" +Toggle 0to1 ram_out [522] "net ram_out[588:0]" +Toggle 1to0 ram_out [522] "net ram_out[588:0]" +Toggle 0to1 ram_out [525] "net ram_out[588:0]" +Toggle 1to0 ram_out [525] "net ram_out[588:0]" +Toggle 0to1 ram_out [527] "net ram_out[588:0]" +Toggle 1to0 ram_out [527] "net ram_out[588:0]" +Toggle 0to1 ram_out [526] "net ram_out[588:0]" +Toggle 1to0 ram_out [526] "net ram_out[588:0]" +Toggle 0to1 ram_out [524] "net ram_out[588:0]" +Toggle 1to0 ram_out [524] "net ram_out[588:0]" +Toggle 0to1 ram_out [523] "net ram_out[588:0]" +Toggle 1to0 ram_out [523] "net ram_out[588:0]" +Toggle 0to1 ram_out [521] "net ram_out[588:0]" +Toggle 1to0 ram_out [521] "net ram_out[588:0]" +Toggle 0to1 ram_out [520] "net ram_out[588:0]" +Toggle 1to0 ram_out [520] "net ram_out[588:0]" +Toggle 0to1 ram_out [529] "net ram_out[588:0]" +Toggle 1to0 ram_out [529] "net ram_out[588:0]" +Toggle 0to1 ram_out [528] "net ram_out[588:0]" +Toggle 1to0 ram_out [528] "net ram_out[588:0]" +Toggle 0to1 ram_out [530] "net ram_out[588:0]" +Toggle 1to0 ram_out [530] "net ram_out[588:0]" +Toggle 0to1 ram_out [532] "net ram_out[588:0]" +Toggle 1to0 ram_out [532] "net ram_out[588:0]" +Toggle 0to1 ram_out [531] "net ram_out[588:0]" +Toggle 1to0 ram_out [531] "net ram_out[588:0]" +Toggle 0to1 ram_out [534] "net ram_out[588:0]" +Toggle 1to0 ram_out [534] "net ram_out[588:0]" +Toggle 0to1 ram_out [533] "net ram_out[588:0]" +Toggle 1to0 ram_out [533] "net ram_out[588:0]" +Toggle 0to1 ram_out [535] "net ram_out[588:0]" +Toggle 1to0 ram_out [535] "net ram_out[588:0]" +CHECKSUM: "4144234428 2546017566" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a.switch.N_mux[1].out_q +Toggle 0to1 fifo_err "reg fifo_err" +Toggle 1to0 fifo_err "reg fifo_err" +Toggle 0to1 fifo_in_q [556] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [556] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [512] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [512] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [516] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [516] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [517] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [517] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [518] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [518] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [519] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [519] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [520] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [520] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [521] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [521] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [522] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [522] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [523] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [523] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [524] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [524] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [525] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [525] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [526] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [526] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [527] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [527] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [528] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [528] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [529] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [529] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [530] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [530] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [531] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [531] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [532] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [532] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [533] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [533] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [534] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [534] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [535] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [535] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [536] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [536] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [537] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [537] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [538] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [538] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [539] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [539] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [540] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [540] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [541] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [541] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [542] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [542] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [543] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [543] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [544] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [544] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [545] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [545] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [546] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [546] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [547] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [547] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [548] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [548] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [549] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [549] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [550] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [550] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [551] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [551] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [552] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [552] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [553] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [553] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [554] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [554] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [555] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [555] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_perr "net fifo_perr" +Toggle 1to0 fifo_perr "net fifo_perr" +Toggle 0to1 perr "net perr" +Toggle 1to0 perr "net perr" +Toggle ram_out_q "reg ram_out_q[588:0]" +Toggle 0to1 perr_en_q "reg perr_en_q" +Toggle 1to0 perr_en_q "reg perr_en_q" +Toggle 0to1 perr_en "reg perr_en" +Toggle 1to0 perr_en "reg perr_en" +Toggle 0to1 ram_out [556] "net ram_out[588:0]" +Toggle 1to0 ram_out [556] "net ram_out[588:0]" +Toggle 0to1 ram_out [512] "net ram_out[588:0]" +Toggle 1to0 ram_out [512] "net ram_out[588:0]" +Toggle 0to1 ram_out [516] "net ram_out[588:0]" +Toggle 1to0 ram_out [516] "net ram_out[588:0]" +Toggle 0to1 ram_out [517] "net ram_out[588:0]" +Toggle 1to0 ram_out [517] "net ram_out[588:0]" +Toggle 0to1 ram_out [518] "net ram_out[588:0]" +Toggle 1to0 ram_out [518] "net ram_out[588:0]" +Toggle 0to1 ram_out [519] "net ram_out[588:0]" +Toggle 1to0 ram_out [519] "net ram_out[588:0]" +Toggle 0to1 ram_out [520] "net ram_out[588:0]" +Toggle 1to0 ram_out [520] "net ram_out[588:0]" +Toggle 0to1 ram_out [521] "net ram_out[588:0]" +Toggle 1to0 ram_out [521] "net ram_out[588:0]" +Toggle 0to1 ram_out [522] "net ram_out[588:0]" +Toggle 1to0 ram_out [522] "net ram_out[588:0]" +Toggle 0to1 ram_out [523] "net ram_out[588:0]" +Toggle 1to0 ram_out [523] "net ram_out[588:0]" +Toggle 0to1 ram_out [524] "net ram_out[588:0]" +Toggle 1to0 ram_out [524] "net ram_out[588:0]" +Toggle 0to1 ram_out [525] "net ram_out[588:0]" +Toggle 1to0 ram_out [525] "net ram_out[588:0]" +Toggle 0to1 ram_out [526] "net ram_out[588:0]" +Toggle 1to0 ram_out [526] "net ram_out[588:0]" +Toggle 0to1 ram_out [527] "net ram_out[588:0]" +Toggle 1to0 ram_out [527] "net ram_out[588:0]" +Toggle 0to1 ram_out [528] "net ram_out[588:0]" +Toggle 1to0 ram_out [528] "net ram_out[588:0]" +Toggle 0to1 ram_out [529] "net ram_out[588:0]" +Toggle 1to0 ram_out [529] "net ram_out[588:0]" +Toggle 0to1 ram_out [530] "net ram_out[588:0]" +Toggle 1to0 ram_out [530] "net ram_out[588:0]" +Toggle 0to1 ram_out [531] "net ram_out[588:0]" +Toggle 1to0 ram_out [531] "net ram_out[588:0]" +Toggle 0to1 ram_out [532] "net ram_out[588:0]" +Toggle 1to0 ram_out [532] "net ram_out[588:0]" +Toggle 0to1 ram_out [533] "net ram_out[588:0]" +Toggle 1to0 ram_out [533] "net ram_out[588:0]" +Toggle 0to1 ram_out [534] "net ram_out[588:0]" +Toggle 1to0 ram_out [534] "net ram_out[588:0]" +Toggle 0to1 ram_out [535] "net ram_out[588:0]" +Toggle 1to0 ram_out [535] "net ram_out[588:0]" +Toggle 0to1 ram_out [536] "net ram_out[588:0]" +Toggle 1to0 ram_out [536] "net ram_out[588:0]" +Toggle 0to1 ram_out [537] "net ram_out[588:0]" +Toggle 1to0 ram_out [537] "net ram_out[588:0]" +Toggle 0to1 ram_out [538] "net ram_out[588:0]" +Toggle 1to0 ram_out [538] "net ram_out[588:0]" +Toggle 0to1 ram_out [539] "net ram_out[588:0]" +Toggle 1to0 ram_out [539] "net ram_out[588:0]" +Toggle 0to1 ram_out [540] "net ram_out[588:0]" +Toggle 1to0 ram_out [540] "net ram_out[588:0]" +Toggle 0to1 ram_out [541] "net ram_out[588:0]" +Toggle 1to0 ram_out [541] "net ram_out[588:0]" +Toggle 0to1 ram_out [542] "net ram_out[588:0]" +Toggle 1to0 ram_out [542] "net ram_out[588:0]" +Toggle 0to1 ram_out [543] "net ram_out[588:0]" +Toggle 1to0 ram_out [543] "net ram_out[588:0]" +Toggle 0to1 ram_out [544] "net ram_out[588:0]" +Toggle 1to0 ram_out [544] "net ram_out[588:0]" +Toggle 0to1 ram_out [545] "net ram_out[588:0]" +Toggle 1to0 ram_out [545] "net ram_out[588:0]" +Toggle 0to1 ram_out [546] "net ram_out[588:0]" +Toggle 1to0 ram_out [546] "net ram_out[588:0]" +Toggle 0to1 ram_out [547] "net ram_out[588:0]" +Toggle 1to0 ram_out [547] "net ram_out[588:0]" +Toggle 0to1 ram_out [548] "net ram_out[588:0]" +Toggle 1to0 ram_out [548] "net ram_out[588:0]" +Toggle 0to1 ram_out [549] "net ram_out[588:0]" +Toggle 1to0 ram_out [549] "net ram_out[588:0]" +Toggle 0to1 ram_out [550] "net ram_out[588:0]" +Toggle 1to0 ram_out [550] "net ram_out[588:0]" +Toggle 0to1 ram_out [551] "net ram_out[588:0]" +Toggle 1to0 ram_out [551] "net ram_out[588:0]" +Toggle 0to1 ram_out [552] "net ram_out[588:0]" +Toggle 1to0 ram_out [552] "net ram_out[588:0]" +Toggle 0to1 ram_out [553] "net ram_out[588:0]" +Toggle 1to0 ram_out [553] "net ram_out[588:0]" +Toggle 0to1 ram_out [554] "net ram_out[588:0]" +Toggle 1to0 ram_out [554] "net ram_out[588:0]" +Toggle 0to1 ram_out [555] "net ram_out[588:0]" +Toggle 1to0 ram_out [555] "net ram_out[588:0]" +CHECKSUM: "4144234428 2546017566" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a.switch.N_mux[3].out_q +Toggle 0to1 fifo_err "reg fifo_err" +Toggle 1to0 fifo_err "reg fifo_err" +Toggle 0to1 fifo_in_q [375] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [375] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [372] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [372] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [373] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [373] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [374] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [374] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [255] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [255] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [96] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [96] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [97] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [97] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [103] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [103] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [104] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [104] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [105] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [105] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [106] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [106] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [107] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [107] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [109] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [109] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [110] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [110] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [111] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [111] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [112] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [112] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [113] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [113] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [114] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [114] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [115] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [115] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [116] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [116] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [117] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [117] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [118] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [118] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [119] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [119] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [120] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [120] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [121] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [121] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [122] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [122] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [123] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [123] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [124] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [124] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [125] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [125] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [126] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [126] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [127] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [127] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [128] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [128] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [129] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [129] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [130] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [130] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [131] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [131] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [132] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [132] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [133] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [133] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [134] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [134] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [135] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [135] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [136] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [136] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [137] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [137] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [138] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [138] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [139] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [139] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [140] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [140] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [141] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [141] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [142] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [142] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [143] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [143] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [144] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [144] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [145] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [145] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [146] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [146] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [147] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [147] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [148] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [148] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [149] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [149] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [150] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [150] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [151] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [151] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [152] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [152] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [153] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [153] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [154] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [154] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [155] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [155] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [156] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [156] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [157] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [157] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [158] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [158] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [159] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [159] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [160] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [160] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [161] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [161] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [162] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [162] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [163] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [163] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [164] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [164] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [165] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [165] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [166] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [166] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [167] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [167] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [168] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [168] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [169] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [169] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [170] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [170] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [171] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [171] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [172] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [172] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [173] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [173] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [174] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [174] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [175] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [175] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [176] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [176] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [177] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [177] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [178] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [178] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [179] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [179] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [180] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [180] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [181] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [181] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [182] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [182] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [183] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [183] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [184] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [184] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [185] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [185] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [186] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [186] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [187] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [187] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [188] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [188] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [189] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [189] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [190] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [190] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [191] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [191] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [192] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [192] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [193] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [193] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [194] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [194] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [195] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [195] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [196] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [196] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [197] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [197] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [198] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [198] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [199] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [199] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [200] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [200] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [201] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [201] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [202] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [202] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [203] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [203] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [204] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [204] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [205] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [205] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [206] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [206] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [207] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [207] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [208] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [208] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [209] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [209] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [210] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [210] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [211] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [211] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [212] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [212] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [213] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [213] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [214] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [214] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [215] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [215] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [216] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [216] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [217] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [217] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [218] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [218] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [219] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [219] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [220] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [220] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [221] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [221] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [222] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [222] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [223] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [223] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [224] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [224] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [225] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [225] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [226] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [226] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [227] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [227] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [228] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [228] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [229] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [229] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [230] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [230] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [231] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [231] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [232] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [232] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [233] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [233] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [234] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [234] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [235] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [235] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [236] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [236] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [237] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [237] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [238] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [238] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [239] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [239] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [240] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [240] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [241] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [241] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [242] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [242] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [243] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [243] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [244] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [244] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [245] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [245] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [246] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [246] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [247] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [247] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [248] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [248] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [249] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [249] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [250] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [250] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [251] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [251] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [252] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [252] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [253] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [253] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [254] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [254] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [77] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [77] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [78] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [78] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [79] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [79] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [80] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [80] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [81] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [81] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [82] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [82] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [83] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [83] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [84] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [84] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [85] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [85] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [86] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [86] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [87] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [87] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [88] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [88] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [89] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [89] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [90] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [90] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [91] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [91] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [92] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [92] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [93] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [93] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [94] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [94] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [95] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [95] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [75] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [75] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [2] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [2] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [3] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [3] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [4] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [4] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [5] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [5] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [6] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [6] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [7] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [7] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [8] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [8] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [9] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [9] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [10] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [10] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [11] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [11] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [12] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [12] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [13] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [13] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [14] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [14] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [15] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [15] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [16] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [16] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [17] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [17] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [18] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [18] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [19] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [19] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [20] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [20] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [21] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [21] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [22] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [22] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [23] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [23] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [24] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [24] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [25] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [25] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [26] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [26] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [27] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [27] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [28] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [28] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [29] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [29] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [31] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [31] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [32] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [32] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [33] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [33] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [34] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [34] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [35] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [35] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [48] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [48] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [49] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [49] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [50] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [50] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [51] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [51] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [52] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [52] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [53] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [53] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [54] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [54] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [55] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [55] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [56] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [56] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [57] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [57] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [58] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [58] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [59] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [59] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [60] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [60] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [61] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [61] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [62] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [62] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [63] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [63] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [64] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [64] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [65] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [65] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [71] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [71] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [72] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [72] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [73] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [73] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_in_q [74] "reg fifo_in_q[588:0]" +Toggle 1to0 fifo_in_q [74] "reg fifo_in_q[588:0]" +Toggle 0to1 fifo_perr "net fifo_perr" +Toggle 1to0 fifo_perr "net fifo_perr" +Toggle ram_out_q "reg ram_out_q[588:0]" +Toggle 0to1 perr_en_q "reg perr_en_q" +Toggle 1to0 perr_en_q "reg perr_en_q" +Toggle 0to1 perr_en "reg perr_en" +Toggle 1to0 perr_en "reg perr_en" +Toggle 0to1 perr "net perr" +Toggle 1to0 perr "net perr" +Toggle 0to1 full "reg full" +Toggle 1to0 full "reg full" +Toggle 0to1 ram_out [375] "net ram_out[588:0]" +Toggle 1to0 ram_out [375] "net ram_out[588:0]" +Toggle 0to1 ram_out [372] "net ram_out[588:0]" +Toggle 1to0 ram_out [372] "net ram_out[588:0]" +Toggle 0to1 ram_out [373] "net ram_out[588:0]" +Toggle 1to0 ram_out [373] "net ram_out[588:0]" +Toggle 0to1 ram_out [374] "net ram_out[588:0]" +Toggle 1to0 ram_out [374] "net ram_out[588:0]" +Toggle 0to1 ram_out [255] "net ram_out[588:0]" +Toggle 1to0 ram_out [255] "net ram_out[588:0]" +Toggle 0to1 ram_out [48] "net ram_out[588:0]" +Toggle 1to0 ram_out [48] "net ram_out[588:0]" +Toggle 0to1 ram_out [49] "net ram_out[588:0]" +Toggle 1to0 ram_out [49] "net ram_out[588:0]" +Toggle 0to1 ram_out [50] "net ram_out[588:0]" +Toggle 1to0 ram_out [50] "net ram_out[588:0]" +Toggle 0to1 ram_out [51] "net ram_out[588:0]" +Toggle 1to0 ram_out [51] "net ram_out[588:0]" +Toggle 0to1 ram_out [52] "net ram_out[588:0]" +Toggle 1to0 ram_out [52] "net ram_out[588:0]" +Toggle 0to1 ram_out [53] "net ram_out[588:0]" +Toggle 1to0 ram_out [53] "net ram_out[588:0]" +Toggle 0to1 ram_out [54] "net ram_out[588:0]" +Toggle 1to0 ram_out [54] "net ram_out[588:0]" +Toggle 0to1 ram_out [55] "net ram_out[588:0]" +Toggle 1to0 ram_out [55] "net ram_out[588:0]" +Toggle 0to1 ram_out [56] "net ram_out[588:0]" +Toggle 1to0 ram_out [56] "net ram_out[588:0]" +Toggle 0to1 ram_out [57] "net ram_out[588:0]" +Toggle 1to0 ram_out [57] "net ram_out[588:0]" +Toggle 0to1 ram_out [58] "net ram_out[588:0]" +Toggle 1to0 ram_out [58] "net ram_out[588:0]" +Toggle 0to1 ram_out [59] "net ram_out[588:0]" +Toggle 1to0 ram_out [59] "net ram_out[588:0]" +Toggle 0to1 ram_out [60] "net ram_out[588:0]" +Toggle 1to0 ram_out [60] "net ram_out[588:0]" +Toggle 0to1 ram_out [61] "net ram_out[588:0]" +Toggle 1to0 ram_out [61] "net ram_out[588:0]" +Toggle 0to1 ram_out [62] "net ram_out[588:0]" +Toggle 1to0 ram_out [62] "net ram_out[588:0]" +Toggle 0to1 ram_out [63] "net ram_out[588:0]" +Toggle 1to0 ram_out [63] "net ram_out[588:0]" +Toggle 0to1 ram_out [64] "net ram_out[588:0]" +Toggle 1to0 ram_out [64] "net ram_out[588:0]" +Toggle 0to1 ram_out [65] "net ram_out[588:0]" +Toggle 1to0 ram_out [65] "net ram_out[588:0]" +Toggle 0to1 ram_out [31] "net ram_out[588:0]" +Toggle 1to0 ram_out [31] "net ram_out[588:0]" +Toggle 0to1 ram_out [32] "net ram_out[588:0]" +Toggle 1to0 ram_out [32] "net ram_out[588:0]" +Toggle 0to1 ram_out [33] "net ram_out[588:0]" +Toggle 1to0 ram_out [33] "net ram_out[588:0]" +Toggle 0to1 ram_out [34] "net ram_out[588:0]" +Toggle 1to0 ram_out [34] "net ram_out[588:0]" +Toggle 0to1 ram_out [35] "net ram_out[588:0]" +Toggle 1to0 ram_out [35] "net ram_out[588:0]" +Toggle 0to1 ram_out [2] "net ram_out[588:0]" +Toggle 1to0 ram_out [2] "net ram_out[588:0]" +Toggle 0to1 ram_out [3] "net ram_out[588:0]" +Toggle 1to0 ram_out [3] "net ram_out[588:0]" +Toggle 0to1 ram_out [4] "net ram_out[588:0]" +Toggle 1to0 ram_out [4] "net ram_out[588:0]" +Toggle 0to1 ram_out [5] "net ram_out[588:0]" +Toggle 1to0 ram_out [5] "net ram_out[588:0]" +Toggle 0to1 ram_out [6] "net ram_out[588:0]" +Toggle 1to0 ram_out [6] "net ram_out[588:0]" +Toggle 0to1 ram_out [7] "net ram_out[588:0]" +Toggle 1to0 ram_out [7] "net ram_out[588:0]" +Toggle 0to1 ram_out [8] "net ram_out[588:0]" +Toggle 1to0 ram_out [8] "net ram_out[588:0]" +Toggle 0to1 ram_out [9] "net ram_out[588:0]" +Toggle 1to0 ram_out [9] "net ram_out[588:0]" +Toggle 0to1 ram_out [10] "net ram_out[588:0]" +Toggle 1to0 ram_out [10] "net ram_out[588:0]" +Toggle 0to1 ram_out [11] "net ram_out[588:0]" +Toggle 1to0 ram_out [11] "net ram_out[588:0]" +Toggle 0to1 ram_out [12] "net ram_out[588:0]" +Toggle 1to0 ram_out [12] "net ram_out[588:0]" +Toggle 0to1 ram_out [13] "net ram_out[588:0]" +Toggle 1to0 ram_out [13] "net ram_out[588:0]" +Toggle 0to1 ram_out [14] "net ram_out[588:0]" +Toggle 1to0 ram_out [14] "net ram_out[588:0]" +Toggle 0to1 ram_out [15] "net ram_out[588:0]" +Toggle 1to0 ram_out [15] "net ram_out[588:0]" +Toggle 0to1 ram_out [16] "net ram_out[588:0]" +Toggle 1to0 ram_out [16] "net ram_out[588:0]" +Toggle 0to1 ram_out [17] "net ram_out[588:0]" +Toggle 1to0 ram_out [17] "net ram_out[588:0]" +Toggle 0to1 ram_out [18] "net ram_out[588:0]" +Toggle 1to0 ram_out [18] "net ram_out[588:0]" +Toggle 0to1 ram_out [19] "net ram_out[588:0]" +Toggle 1to0 ram_out [19] "net ram_out[588:0]" +Toggle 0to1 ram_out [20] "net ram_out[588:0]" +Toggle 1to0 ram_out [20] "net ram_out[588:0]" +Toggle 0to1 ram_out [21] "net ram_out[588:0]" +Toggle 1to0 ram_out [21] "net ram_out[588:0]" +Toggle 0to1 ram_out [22] "net ram_out[588:0]" +Toggle 1to0 ram_out [22] "net ram_out[588:0]" +Toggle 0to1 ram_out [23] "net ram_out[588:0]" +Toggle 1to0 ram_out [23] "net ram_out[588:0]" +Toggle 0to1 ram_out [24] "net ram_out[588:0]" +Toggle 1to0 ram_out [24] "net ram_out[588:0]" +Toggle 0to1 ram_out [25] "net ram_out[588:0]" +Toggle 1to0 ram_out [25] "net ram_out[588:0]" +Toggle 0to1 ram_out [26] "net ram_out[588:0]" +Toggle 1to0 ram_out [26] "net ram_out[588:0]" +Toggle 0to1 ram_out [27] "net ram_out[588:0]" +Toggle 1to0 ram_out [27] "net ram_out[588:0]" +Toggle 0to1 ram_out [28] "net ram_out[588:0]" +Toggle 1to0 ram_out [28] "net ram_out[588:0]" +Toggle 0to1 ram_out [29] "net ram_out[588:0]" +Toggle 1to0 ram_out [29] "net ram_out[588:0]" +Toggle 0to1 ram_out [96] "net ram_out[588:0]" +Toggle 1to0 ram_out [96] "net ram_out[588:0]" +Toggle 0to1 ram_out [97] "net ram_out[588:0]" +Toggle 1to0 ram_out [97] "net ram_out[588:0]" +Toggle 0to1 ram_out [103] "net ram_out[588:0]" +Toggle 1to0 ram_out [103] "net ram_out[588:0]" +Toggle 0to1 ram_out [104] "net ram_out[588:0]" +Toggle 1to0 ram_out [104] "net ram_out[588:0]" +Toggle 0to1 ram_out [105] "net ram_out[588:0]" +Toggle 1to0 ram_out [105] "net ram_out[588:0]" +Toggle 0to1 ram_out [106] "net ram_out[588:0]" +Toggle 1to0 ram_out [106] "net ram_out[588:0]" +Toggle 0to1 ram_out [107] "net ram_out[588:0]" +Toggle 1to0 ram_out [107] "net ram_out[588:0]" +Toggle 0to1 ram_out [109] "net ram_out[588:0]" +Toggle 1to0 ram_out [109] "net ram_out[588:0]" +Toggle 0to1 ram_out [110] "net ram_out[588:0]" +Toggle 1to0 ram_out [110] "net ram_out[588:0]" +Toggle 0to1 ram_out [111] "net ram_out[588:0]" +Toggle 1to0 ram_out [111] "net ram_out[588:0]" +Toggle 0to1 ram_out [112] "net ram_out[588:0]" +Toggle 1to0 ram_out [112] "net ram_out[588:0]" +Toggle 0to1 ram_out [113] "net ram_out[588:0]" +Toggle 1to0 ram_out [113] "net ram_out[588:0]" +Toggle 0to1 ram_out [114] "net ram_out[588:0]" +Toggle 1to0 ram_out [114] "net ram_out[588:0]" +Toggle 0to1 ram_out [115] "net ram_out[588:0]" +Toggle 1to0 ram_out [115] "net ram_out[588:0]" +Toggle 0to1 ram_out [116] "net ram_out[588:0]" +Toggle 1to0 ram_out [116] "net ram_out[588:0]" +Toggle 0to1 ram_out [117] "net ram_out[588:0]" +Toggle 1to0 ram_out [117] "net ram_out[588:0]" +Toggle 0to1 ram_out [118] "net ram_out[588:0]" +Toggle 1to0 ram_out [118] "net ram_out[588:0]" +Toggle 0to1 ram_out [119] "net ram_out[588:0]" +Toggle 1to0 ram_out [119] "net ram_out[588:0]" +Toggle 0to1 ram_out [120] "net ram_out[588:0]" +Toggle 1to0 ram_out [120] "net ram_out[588:0]" +Toggle 0to1 ram_out [121] "net ram_out[588:0]" +Toggle 1to0 ram_out [121] "net ram_out[588:0]" +Toggle 0to1 ram_out [122] "net ram_out[588:0]" +Toggle 1to0 ram_out [122] "net ram_out[588:0]" +Toggle 0to1 ram_out [123] "net ram_out[588:0]" +Toggle 1to0 ram_out [123] "net ram_out[588:0]" +Toggle 0to1 ram_out [124] "net ram_out[588:0]" +Toggle 1to0 ram_out [124] "net ram_out[588:0]" +Toggle 0to1 ram_out [125] "net ram_out[588:0]" +Toggle 1to0 ram_out [125] "net ram_out[588:0]" +Toggle 0to1 ram_out [126] "net ram_out[588:0]" +Toggle 1to0 ram_out [126] "net ram_out[588:0]" +Toggle 0to1 ram_out [127] "net ram_out[588:0]" +Toggle 1to0 ram_out [127] "net ram_out[588:0]" +Toggle 0to1 ram_out [128] "net ram_out[588:0]" +Toggle 1to0 ram_out [128] "net ram_out[588:0]" +Toggle 0to1 ram_out [129] "net ram_out[588:0]" +Toggle 1to0 ram_out [129] "net ram_out[588:0]" +Toggle 0to1 ram_out [130] "net ram_out[588:0]" +Toggle 1to0 ram_out [130] "net ram_out[588:0]" +Toggle 0to1 ram_out [131] "net ram_out[588:0]" +Toggle 1to0 ram_out [131] "net ram_out[588:0]" +Toggle 0to1 ram_out [132] "net ram_out[588:0]" +Toggle 1to0 ram_out [132] "net ram_out[588:0]" +Toggle 0to1 ram_out [133] "net ram_out[588:0]" +Toggle 1to0 ram_out [133] "net ram_out[588:0]" +Toggle 0to1 ram_out [134] "net ram_out[588:0]" +Toggle 1to0 ram_out [134] "net ram_out[588:0]" +Toggle 0to1 ram_out [135] "net ram_out[588:0]" +Toggle 1to0 ram_out [135] "net ram_out[588:0]" +Toggle 0to1 ram_out [136] "net ram_out[588:0]" +Toggle 1to0 ram_out [136] "net ram_out[588:0]" +Toggle 0to1 ram_out [137] "net ram_out[588:0]" +Toggle 1to0 ram_out [137] "net ram_out[588:0]" +Toggle 0to1 ram_out [138] "net ram_out[588:0]" +Toggle 1to0 ram_out [138] "net ram_out[588:0]" +Toggle 0to1 ram_out [139] "net ram_out[588:0]" +Toggle 1to0 ram_out [139] "net ram_out[588:0]" +Toggle 0to1 ram_out [140] "net ram_out[588:0]" +Toggle 1to0 ram_out [140] "net ram_out[588:0]" +Toggle 0to1 ram_out [141] "net ram_out[588:0]" +Toggle 1to0 ram_out [141] "net ram_out[588:0]" +Toggle 0to1 ram_out [142] "net ram_out[588:0]" +Toggle 1to0 ram_out [142] "net ram_out[588:0]" +Toggle 0to1 ram_out [143] "net ram_out[588:0]" +Toggle 1to0 ram_out [143] "net ram_out[588:0]" +Toggle 0to1 ram_out [144] "net ram_out[588:0]" +Toggle 1to0 ram_out [144] "net ram_out[588:0]" +Toggle 0to1 ram_out [145] "net ram_out[588:0]" +Toggle 1to0 ram_out [145] "net ram_out[588:0]" +Toggle 0to1 ram_out [146] "net ram_out[588:0]" +Toggle 1to0 ram_out [146] "net ram_out[588:0]" +Toggle 0to1 ram_out [147] "net ram_out[588:0]" +Toggle 1to0 ram_out [147] "net ram_out[588:0]" +Toggle 0to1 ram_out [148] "net ram_out[588:0]" +Toggle 1to0 ram_out [148] "net ram_out[588:0]" +Toggle 0to1 ram_out [149] "net ram_out[588:0]" +Toggle 1to0 ram_out [149] "net ram_out[588:0]" +Toggle 0to1 ram_out [150] "net ram_out[588:0]" +Toggle 1to0 ram_out [150] "net ram_out[588:0]" +Toggle 0to1 ram_out [151] "net ram_out[588:0]" +Toggle 1to0 ram_out [151] "net ram_out[588:0]" +Toggle 0to1 ram_out [152] "net ram_out[588:0]" +Toggle 1to0 ram_out [152] "net ram_out[588:0]" +Toggle 0to1 ram_out [153] "net ram_out[588:0]" +Toggle 1to0 ram_out [153] "net ram_out[588:0]" +Toggle 0to1 ram_out [154] "net ram_out[588:0]" +Toggle 1to0 ram_out [154] "net ram_out[588:0]" +Toggle 0to1 ram_out [155] "net ram_out[588:0]" +Toggle 1to0 ram_out [155] "net ram_out[588:0]" +Toggle 0to1 ram_out [156] "net ram_out[588:0]" +Toggle 1to0 ram_out [156] "net ram_out[588:0]" +Toggle 0to1 ram_out [157] "net ram_out[588:0]" +Toggle 1to0 ram_out [157] "net ram_out[588:0]" +Toggle 0to1 ram_out [158] "net ram_out[588:0]" +Toggle 1to0 ram_out [158] "net ram_out[588:0]" +Toggle 0to1 ram_out [159] "net ram_out[588:0]" +Toggle 1to0 ram_out [159] "net ram_out[588:0]" +Toggle 0to1 ram_out [160] "net ram_out[588:0]" +Toggle 1to0 ram_out [160] "net ram_out[588:0]" +Toggle 0to1 ram_out [161] "net ram_out[588:0]" +Toggle 1to0 ram_out [161] "net ram_out[588:0]" +Toggle 0to1 ram_out [162] "net ram_out[588:0]" +Toggle 1to0 ram_out [162] "net ram_out[588:0]" +Toggle 0to1 ram_out [163] "net ram_out[588:0]" +Toggle 1to0 ram_out [163] "net ram_out[588:0]" +Toggle 0to1 ram_out [164] "net ram_out[588:0]" +Toggle 1to0 ram_out [164] "net ram_out[588:0]" +Toggle 0to1 ram_out [165] "net ram_out[588:0]" +Toggle 1to0 ram_out [165] "net ram_out[588:0]" +Toggle 0to1 ram_out [166] "net ram_out[588:0]" +Toggle 1to0 ram_out [166] "net ram_out[588:0]" +Toggle 0to1 ram_out [167] "net ram_out[588:0]" +Toggle 1to0 ram_out [167] "net ram_out[588:0]" +Toggle 0to1 ram_out [168] "net ram_out[588:0]" +Toggle 1to0 ram_out [168] "net ram_out[588:0]" +Toggle 0to1 ram_out [169] "net ram_out[588:0]" +Toggle 1to0 ram_out [169] "net ram_out[588:0]" +Toggle 0to1 ram_out [170] "net ram_out[588:0]" +Toggle 1to0 ram_out [170] "net ram_out[588:0]" +Toggle 0to1 ram_out [171] "net ram_out[588:0]" +Toggle 1to0 ram_out [171] "net ram_out[588:0]" +Toggle 0to1 ram_out [172] "net ram_out[588:0]" +Toggle 1to0 ram_out [172] "net ram_out[588:0]" +Toggle 0to1 ram_out [173] "net ram_out[588:0]" +Toggle 1to0 ram_out [173] "net ram_out[588:0]" +Toggle 0to1 ram_out [174] "net ram_out[588:0]" +Toggle 1to0 ram_out [174] "net ram_out[588:0]" +Toggle 0to1 ram_out [175] "net ram_out[588:0]" +Toggle 1to0 ram_out [175] "net ram_out[588:0]" +Toggle 0to1 ram_out [176] "net ram_out[588:0]" +Toggle 1to0 ram_out [176] "net ram_out[588:0]" +Toggle 0to1 ram_out [177] "net ram_out[588:0]" +Toggle 1to0 ram_out [177] "net ram_out[588:0]" +Toggle 0to1 ram_out [178] "net ram_out[588:0]" +Toggle 1to0 ram_out [178] "net ram_out[588:0]" +Toggle 0to1 ram_out [179] "net ram_out[588:0]" +Toggle 1to0 ram_out [179] "net ram_out[588:0]" +Toggle 0to1 ram_out [180] "net ram_out[588:0]" +Toggle 1to0 ram_out [180] "net ram_out[588:0]" +Toggle 0to1 ram_out [181] "net ram_out[588:0]" +Toggle 1to0 ram_out [181] "net ram_out[588:0]" +Toggle 0to1 ram_out [182] "net ram_out[588:0]" +Toggle 1to0 ram_out [182] "net ram_out[588:0]" +Toggle 0to1 ram_out [183] "net ram_out[588:0]" +Toggle 1to0 ram_out [183] "net ram_out[588:0]" +Toggle 0to1 ram_out [184] "net ram_out[588:0]" +Toggle 1to0 ram_out [184] "net ram_out[588:0]" +Toggle 0to1 ram_out [185] "net ram_out[588:0]" +Toggle 1to0 ram_out [185] "net ram_out[588:0]" +Toggle 0to1 ram_out [186] "net ram_out[588:0]" +Toggle 1to0 ram_out [186] "net ram_out[588:0]" +Toggle 0to1 ram_out [187] "net ram_out[588:0]" +Toggle 1to0 ram_out [187] "net ram_out[588:0]" +Toggle 0to1 ram_out [188] "net ram_out[588:0]" +Toggle 1to0 ram_out [188] "net ram_out[588:0]" +Toggle 0to1 ram_out [189] "net ram_out[588:0]" +Toggle 1to0 ram_out [189] "net ram_out[588:0]" +Toggle 0to1 ram_out [190] "net ram_out[588:0]" +Toggle 1to0 ram_out [190] "net ram_out[588:0]" +Toggle 0to1 ram_out [191] "net ram_out[588:0]" +Toggle 1to0 ram_out [191] "net ram_out[588:0]" +Toggle 0to1 ram_out [192] "net ram_out[588:0]" +Toggle 1to0 ram_out [192] "net ram_out[588:0]" +Toggle 0to1 ram_out [193] "net ram_out[588:0]" +Toggle 1to0 ram_out [193] "net ram_out[588:0]" +Toggle 0to1 ram_out [194] "net ram_out[588:0]" +Toggle 1to0 ram_out [194] "net ram_out[588:0]" +Toggle 0to1 ram_out [195] "net ram_out[588:0]" +Toggle 1to0 ram_out [195] "net ram_out[588:0]" +Toggle 0to1 ram_out [196] "net ram_out[588:0]" +Toggle 1to0 ram_out [196] "net ram_out[588:0]" +Toggle 0to1 ram_out [197] "net ram_out[588:0]" +Toggle 1to0 ram_out [197] "net ram_out[588:0]" +Toggle 0to1 ram_out [198] "net ram_out[588:0]" +Toggle 1to0 ram_out [198] "net ram_out[588:0]" +Toggle 0to1 ram_out [199] "net ram_out[588:0]" +Toggle 1to0 ram_out [199] "net ram_out[588:0]" +Toggle 0to1 ram_out [200] "net ram_out[588:0]" +Toggle 1to0 ram_out [200] "net ram_out[588:0]" +Toggle 0to1 ram_out [201] "net ram_out[588:0]" +Toggle 1to0 ram_out [201] "net ram_out[588:0]" +Toggle 0to1 ram_out [202] "net ram_out[588:0]" +Toggle 1to0 ram_out [202] "net ram_out[588:0]" +Toggle 0to1 ram_out [203] "net ram_out[588:0]" +Toggle 1to0 ram_out [203] "net ram_out[588:0]" +Toggle 0to1 ram_out [204] "net ram_out[588:0]" +Toggle 1to0 ram_out [204] "net ram_out[588:0]" +Toggle 0to1 ram_out [205] "net ram_out[588:0]" +Toggle 1to0 ram_out [205] "net ram_out[588:0]" +Toggle 0to1 ram_out [206] "net ram_out[588:0]" +Toggle 1to0 ram_out [206] "net ram_out[588:0]" +Toggle 0to1 ram_out [207] "net ram_out[588:0]" +Toggle 1to0 ram_out [207] "net ram_out[588:0]" +Toggle 0to1 ram_out [208] "net ram_out[588:0]" +Toggle 1to0 ram_out [208] "net ram_out[588:0]" +Toggle 0to1 ram_out [209] "net ram_out[588:0]" +Toggle 1to0 ram_out [209] "net ram_out[588:0]" +Toggle 0to1 ram_out [210] "net ram_out[588:0]" +Toggle 1to0 ram_out [210] "net ram_out[588:0]" +Toggle 0to1 ram_out [211] "net ram_out[588:0]" +Toggle 1to0 ram_out [211] "net ram_out[588:0]" +Toggle 0to1 ram_out [212] "net ram_out[588:0]" +Toggle 1to0 ram_out [212] "net ram_out[588:0]" +Toggle 0to1 ram_out [213] "net ram_out[588:0]" +Toggle 1to0 ram_out [213] "net ram_out[588:0]" +Toggle 0to1 ram_out [214] "net ram_out[588:0]" +Toggle 1to0 ram_out [214] "net ram_out[588:0]" +Toggle 0to1 ram_out [215] "net ram_out[588:0]" +Toggle 1to0 ram_out [215] "net ram_out[588:0]" +Toggle 0to1 ram_out [216] "net ram_out[588:0]" +Toggle 1to0 ram_out [216] "net ram_out[588:0]" +Toggle 0to1 ram_out [217] "net ram_out[588:0]" +Toggle 1to0 ram_out [217] "net ram_out[588:0]" +Toggle 0to1 ram_out [218] "net ram_out[588:0]" +Toggle 1to0 ram_out [218] "net ram_out[588:0]" +Toggle 0to1 ram_out [219] "net ram_out[588:0]" +Toggle 1to0 ram_out [219] "net ram_out[588:0]" +Toggle 0to1 ram_out [220] "net ram_out[588:0]" +Toggle 1to0 ram_out [220] "net ram_out[588:0]" +Toggle 0to1 ram_out [221] "net ram_out[588:0]" +Toggle 1to0 ram_out [221] "net ram_out[588:0]" +Toggle 0to1 ram_out [222] "net ram_out[588:0]" +Toggle 1to0 ram_out [222] "net ram_out[588:0]" +Toggle 0to1 ram_out [223] "net ram_out[588:0]" +Toggle 1to0 ram_out [223] "net ram_out[588:0]" +Toggle 0to1 ram_out [224] "net ram_out[588:0]" +Toggle 1to0 ram_out [224] "net ram_out[588:0]" +Toggle 0to1 ram_out [225] "net ram_out[588:0]" +Toggle 1to0 ram_out [225] "net ram_out[588:0]" +Toggle 0to1 ram_out [226] "net ram_out[588:0]" +Toggle 1to0 ram_out [226] "net ram_out[588:0]" +Toggle 0to1 ram_out [227] "net ram_out[588:0]" +Toggle 1to0 ram_out [227] "net ram_out[588:0]" +Toggle 0to1 ram_out [228] "net ram_out[588:0]" +Toggle 1to0 ram_out [228] "net ram_out[588:0]" +Toggle 0to1 ram_out [229] "net ram_out[588:0]" +Toggle 1to0 ram_out [229] "net ram_out[588:0]" +Toggle 0to1 ram_out [230] "net ram_out[588:0]" +Toggle 1to0 ram_out [230] "net ram_out[588:0]" +Toggle 0to1 ram_out [231] "net ram_out[588:0]" +Toggle 1to0 ram_out [231] "net ram_out[588:0]" +Toggle 0to1 ram_out [232] "net ram_out[588:0]" +Toggle 1to0 ram_out [232] "net ram_out[588:0]" +Toggle 0to1 ram_out [233] "net ram_out[588:0]" +Toggle 1to0 ram_out [233] "net ram_out[588:0]" +Toggle 0to1 ram_out [234] "net ram_out[588:0]" +Toggle 1to0 ram_out [234] "net ram_out[588:0]" +Toggle 0to1 ram_out [235] "net ram_out[588:0]" +Toggle 1to0 ram_out [235] "net ram_out[588:0]" +Toggle 0to1 ram_out [236] "net ram_out[588:0]" +Toggle 1to0 ram_out [236] "net ram_out[588:0]" +Toggle 0to1 ram_out [237] "net ram_out[588:0]" +Toggle 1to0 ram_out [237] "net ram_out[588:0]" +Toggle 0to1 ram_out [238] "net ram_out[588:0]" +Toggle 1to0 ram_out [238] "net ram_out[588:0]" +Toggle 0to1 ram_out [239] "net ram_out[588:0]" +Toggle 1to0 ram_out [239] "net ram_out[588:0]" +Toggle 0to1 ram_out [240] "net ram_out[588:0]" +Toggle 1to0 ram_out [240] "net ram_out[588:0]" +Toggle 0to1 ram_out [241] "net ram_out[588:0]" +Toggle 1to0 ram_out [241] "net ram_out[588:0]" +Toggle 0to1 ram_out [242] "net ram_out[588:0]" +Toggle 1to0 ram_out [242] "net ram_out[588:0]" +Toggle 0to1 ram_out [243] "net ram_out[588:0]" +Toggle 1to0 ram_out [243] "net ram_out[588:0]" +Toggle 0to1 ram_out [244] "net ram_out[588:0]" +Toggle 1to0 ram_out [244] "net ram_out[588:0]" +Toggle 0to1 ram_out [245] "net ram_out[588:0]" +Toggle 1to0 ram_out [245] "net ram_out[588:0]" +Toggle 0to1 ram_out [246] "net ram_out[588:0]" +Toggle 1to0 ram_out [246] "net ram_out[588:0]" +Toggle 0to1 ram_out [247] "net ram_out[588:0]" +Toggle 1to0 ram_out [247] "net ram_out[588:0]" +Toggle 0to1 ram_out [248] "net ram_out[588:0]" +Toggle 1to0 ram_out [248] "net ram_out[588:0]" +Toggle 0to1 ram_out [249] "net ram_out[588:0]" +Toggle 1to0 ram_out [249] "net ram_out[588:0]" +Toggle 0to1 ram_out [250] "net ram_out[588:0]" +Toggle 1to0 ram_out [250] "net ram_out[588:0]" +Toggle 0to1 ram_out [251] "net ram_out[588:0]" +Toggle 1to0 ram_out [251] "net ram_out[588:0]" +Toggle 0to1 ram_out [252] "net ram_out[588:0]" +Toggle 1to0 ram_out [252] "net ram_out[588:0]" +Toggle 0to1 ram_out [253] "net ram_out[588:0]" +Toggle 1to0 ram_out [253] "net ram_out[588:0]" +Toggle 0to1 ram_out [254] "net ram_out[588:0]" +Toggle 1to0 ram_out [254] "net ram_out[588:0]" +Toggle 0to1 ram_out [95] "net ram_out[588:0]" +Toggle 1to0 ram_out [95] "net ram_out[588:0]" +Toggle 0to1 ram_out [78] "net ram_out[588:0]" +Toggle 1to0 ram_out [78] "net ram_out[588:0]" +Toggle 0to1 ram_out [79] "net ram_out[588:0]" +Toggle 1to0 ram_out [79] "net ram_out[588:0]" +Toggle 0to1 ram_out [80] "net ram_out[588:0]" +Toggle 1to0 ram_out [80] "net ram_out[588:0]" +Toggle 0to1 ram_out [81] "net ram_out[588:0]" +Toggle 1to0 ram_out [81] "net ram_out[588:0]" +Toggle 0to1 ram_out [82] "net ram_out[588:0]" +Toggle 1to0 ram_out [82] "net ram_out[588:0]" +Toggle 0to1 ram_out [83] "net ram_out[588:0]" +Toggle 1to0 ram_out [83] "net ram_out[588:0]" +Toggle 0to1 ram_out [84] "net ram_out[588:0]" +Toggle 1to0 ram_out [84] "net ram_out[588:0]" +Toggle 0to1 ram_out [85] "net ram_out[588:0]" +Toggle 1to0 ram_out [85] "net ram_out[588:0]" +Toggle 0to1 ram_out [86] "net ram_out[588:0]" +Toggle 1to0 ram_out [86] "net ram_out[588:0]" +Toggle 0to1 ram_out [87] "net ram_out[588:0]" +Toggle 1to0 ram_out [87] "net ram_out[588:0]" +Toggle 0to1 ram_out [88] "net ram_out[588:0]" +Toggle 1to0 ram_out [88] "net ram_out[588:0]" +Toggle 0to1 ram_out [89] "net ram_out[588:0]" +Toggle 1to0 ram_out [89] "net ram_out[588:0]" +Toggle 0to1 ram_out [90] "net ram_out[588:0]" +Toggle 1to0 ram_out [90] "net ram_out[588:0]" +Toggle 0to1 ram_out [91] "net ram_out[588:0]" +Toggle 1to0 ram_out [91] "net ram_out[588:0]" +Toggle 0to1 ram_out [92] "net ram_out[588:0]" +Toggle 1to0 ram_out [92] "net ram_out[588:0]" +Toggle 0to1 ram_out [93] "net ram_out[588:0]" +Toggle 1to0 ram_out [93] "net ram_out[588:0]" +Toggle 0to1 ram_out [94] "net ram_out[588:0]" +Toggle 1to0 ram_out [94] "net ram_out[588:0]" +Toggle 0to1 ram_out [77] "net ram_out[588:0]" +Toggle 1to0 ram_out [77] "net ram_out[588:0]" +Toggle 0to1 ram_out [72] "net ram_out[588:0]" +Toggle 1to0 ram_out [72] "net ram_out[588:0]" +Toggle 0to1 ram_out [73] "net ram_out[588:0]" +Toggle 1to0 ram_out [73] "net ram_out[588:0]" +Toggle 0to1 ram_out [74] "net ram_out[588:0]" +Toggle 1to0 ram_out [74] "net ram_out[588:0]" +Toggle 0to1 ram_out [75] "net ram_out[588:0]" +Toggle 1to0 ram_out [75] "net ram_out[588:0]" +Toggle 0to1 ram_out [71] "net ram_out[588:0]" +Toggle 1to0 ram_out [71] "net ram_out[588:0]" +CHECKSUM: "4144234428 2546017566" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_b.switch.M_mux[0].out_q +Toggle 0to1 fifo_perr "net fifo_perr" +Toggle 1to0 fifo_perr "net fifo_perr" +Toggle 0to1 perr "net perr" +Toggle 1to0 perr "net perr" +Toggle 0to1 perr_en "reg perr_en" +Toggle 1to0 perr_en "reg perr_en" +Toggle 0to1 perr_en_q "reg perr_en_q" +Toggle 1to0 perr_en_q "reg perr_en_q" +CHECKSUM: "4144234428 2546017566" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[0].out_q +Toggle 0to1 fifo_perr "net fifo_perr" +Toggle 1to0 fifo_perr "net fifo_perr" +Toggle 0to1 perr "net perr" +Toggle 1to0 perr "net perr" +Toggle 0to1 perr_en "reg perr_en" +Toggle 1to0 perr_en "reg perr_en" +Toggle 0to1 perr_en_q "reg perr_en_q" +Toggle 1to0 perr_en_q "reg perr_en_q" +CHECKSUM: "4144234428 2546017566" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[1].out_q +Toggle 0to1 fifo_perr "net fifo_perr" +Toggle 1to0 fifo_perr "net fifo_perr" +Toggle 0to1 perr "net perr" +Toggle 1to0 perr "net perr" +Toggle 0to1 perr_en "reg perr_en" +Toggle 1to0 perr_en "reg perr_en" +Toggle 0to1 perr_en_q "reg perr_en_q" +Toggle 1to0 perr_en_q "reg perr_en_q" +CHECKSUM: "4144234428 2546017566" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[2].out_q +Toggle 0to1 fifo_perr "net fifo_perr" +Toggle 1to0 fifo_perr "net fifo_perr" +Toggle 0to1 perr "net perr" +Toggle 1to0 perr "net perr" +Toggle 0to1 perr_en "reg perr_en" +Toggle 1to0 perr_en "reg perr_en" +Toggle 0to1 perr_en_q "reg perr_en_q" +Toggle 1to0 perr_en_q "reg perr_en_q" +CHECKSUM: "4144234428 2546017566" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[3].out_q +Toggle 0to1 fifo_perr "net fifo_perr" +Toggle 1to0 fifo_perr "net fifo_perr" +Toggle 0to1 perr "net perr" +Toggle 1to0 perr "net perr" +Toggle 0to1 perr_en "reg perr_en" +Toggle 1to0 perr_en "reg perr_en" +Toggle 0to1 perr_en_q "reg perr_en_q" +Toggle 1to0 perr_en_q "reg perr_en_q" +CHECKSUM: "3190985420 1606079823" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a.switch.N_mux[2].out_q.fifo_ram +Toggle 0to1 ram_dout [255] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [255] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [96] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [96] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [97] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [97] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [103] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [103] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [104] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [104] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [105] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [105] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [106] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [106] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [107] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [107] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [109] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [109] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [110] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [110] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [111] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [111] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [112] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [112] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [113] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [113] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [114] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [114] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [115] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [115] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [116] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [116] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [117] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [117] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [118] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [118] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [119] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [119] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [120] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [120] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [121] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [121] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [122] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [122] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [123] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [123] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [124] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [124] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [125] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [125] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [126] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [126] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [127] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [127] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [128] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [128] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [129] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [129] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [130] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [130] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [131] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [131] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [132] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [132] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [133] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [133] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [134] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [134] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [135] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [135] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [136] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [136] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [137] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [137] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [138] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [138] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [139] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [139] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [140] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [140] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [141] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [141] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [142] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [142] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [143] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [143] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [144] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [144] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [145] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [145] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [146] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [146] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [147] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [147] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [148] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [148] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [149] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [149] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [150] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [150] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [151] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [151] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [152] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [152] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [153] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [153] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [154] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [154] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [155] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [155] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [156] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [156] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [157] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [157] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [158] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [158] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [159] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [159] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [160] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [160] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [161] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [161] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [162] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [162] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [163] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [163] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [164] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [164] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [165] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [165] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [166] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [166] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [167] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [167] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [168] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [168] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [169] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [169] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [170] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [170] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [171] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [171] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [172] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [172] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [173] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [173] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [174] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [174] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [175] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [175] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [176] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [176] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [177] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [177] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [178] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [178] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [179] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [179] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [180] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [180] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [181] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [181] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [182] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [182] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [183] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [183] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [184] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [184] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [185] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [185] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [186] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [186] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [187] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [187] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [188] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [188] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [189] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [189] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [190] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [190] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [191] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [191] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [192] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [192] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [193] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [193] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [194] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [194] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [195] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [195] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [196] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [196] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [197] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [197] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [198] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [198] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [199] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [199] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [200] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [200] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [201] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [201] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [202] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [202] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [203] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [203] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [204] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [204] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [205] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [205] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [206] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [206] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [207] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [207] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [208] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [208] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [209] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [209] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [210] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [210] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [211] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [211] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [212] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [212] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [213] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [213] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [214] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [214] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [215] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [215] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [216] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [216] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [217] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [217] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [218] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [218] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [219] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [219] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [220] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [220] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [221] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [221] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [222] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [222] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [223] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [223] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [224] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [224] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [225] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [225] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [226] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [226] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [227] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [227] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [228] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [228] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [229] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [229] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [230] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [230] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [231] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [231] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [232] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [232] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [233] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [233] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [234] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [234] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [235] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [235] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [236] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [236] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [237] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [237] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [238] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [238] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [239] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [239] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [240] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [240] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [241] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [241] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [242] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [242] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [243] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [243] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [244] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [244] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [245] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [245] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [246] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [246] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [247] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [247] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [248] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [248] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [249] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [249] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [250] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [250] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [251] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [251] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [252] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [252] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [253] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [253] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [254] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [254] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [95] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [95] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [71] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [71] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [72] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [72] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [73] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [73] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [74] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [74] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [75] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [75] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [77] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [77] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [78] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [78] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [79] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [79] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [80] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [80] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [81] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [81] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [82] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [82] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [83] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [83] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [84] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [84] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [85] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [85] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [86] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [86] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [87] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [87] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [88] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [88] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [89] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [89] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [90] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [90] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [91] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [91] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [92] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [92] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [93] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [93] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [94] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [94] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [76] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [65] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [65] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [2] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [2] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [3] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [3] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [4] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [4] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [5] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [5] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [6] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [6] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [7] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [7] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [8] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [8] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [9] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [9] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [10] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [10] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [11] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [11] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [12] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [12] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [13] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [13] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [14] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [14] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [15] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [15] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [16] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [16] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [17] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [17] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [18] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [18] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [19] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [19] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [20] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [20] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [21] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [21] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [22] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [22] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [23] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [23] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [24] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [24] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [25] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [25] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [26] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [26] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [27] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [27] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [28] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [28] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [29] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [29] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [31] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [31] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [32] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [32] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [33] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [33] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [34] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [34] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [35] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [35] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [48] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [48] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [49] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [49] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [50] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [50] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [51] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [51] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [52] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [52] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [53] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [53] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [54] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [54] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [55] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [55] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [56] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [56] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [57] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [57] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [58] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [58] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [59] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [59] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [60] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [60] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [61] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [61] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [62] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [62] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [63] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [63] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [64] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [64] "logic ram_dout[588:0]" +Toggle 0to1 perr_or "logic perr_or" +Toggle 1to0 perr_or "logic perr_or" +Toggle 0to1 perr "logic perr" +Toggle 1to0 perr "logic perr" +Toggle perr_in "logic perr_in[18:0]" +Toggle 0to1 dout [255] "logic dout[588:0]" +Toggle 1to0 dout [255] "logic dout[588:0]" +Toggle 0to1 dout [48] "logic dout[588:0]" +Toggle 1to0 dout [48] "logic dout[588:0]" +Toggle 0to1 dout [49] "logic dout[588:0]" +Toggle 1to0 dout [49] "logic dout[588:0]" +Toggle 0to1 dout [50] "logic dout[588:0]" +Toggle 1to0 dout [50] "logic dout[588:0]" +Toggle 0to1 dout [51] "logic dout[588:0]" +Toggle 1to0 dout [51] "logic dout[588:0]" +Toggle 0to1 dout [52] "logic dout[588:0]" +Toggle 1to0 dout [52] "logic dout[588:0]" +Toggle 0to1 dout [53] "logic dout[588:0]" +Toggle 1to0 dout [53] "logic dout[588:0]" +Toggle 0to1 dout [54] "logic dout[588:0]" +Toggle 1to0 dout [54] "logic dout[588:0]" +Toggle 0to1 dout [55] "logic dout[588:0]" +Toggle 1to0 dout [55] "logic dout[588:0]" +Toggle 0to1 dout [56] "logic dout[588:0]" +Toggle 1to0 dout [56] "logic dout[588:0]" +Toggle 0to1 dout [57] "logic dout[588:0]" +Toggle 1to0 dout [57] "logic dout[588:0]" +Toggle 0to1 dout [58] "logic dout[588:0]" +Toggle 1to0 dout [58] "logic dout[588:0]" +Toggle 0to1 dout [59] "logic dout[588:0]" +Toggle 1to0 dout [59] "logic dout[588:0]" +Toggle 0to1 dout [60] "logic dout[588:0]" +Toggle 1to0 dout [60] "logic dout[588:0]" +Toggle 0to1 dout [61] "logic dout[588:0]" +Toggle 1to0 dout [61] "logic dout[588:0]" +Toggle 0to1 dout [62] "logic dout[588:0]" +Toggle 1to0 dout [62] "logic dout[588:0]" +Toggle 0to1 dout [63] "logic dout[588:0]" +Toggle 1to0 dout [63] "logic dout[588:0]" +Toggle 0to1 dout [64] "logic dout[588:0]" +Toggle 1to0 dout [64] "logic dout[588:0]" +Toggle 0to1 dout [65] "logic dout[588:0]" +Toggle 1to0 dout [65] "logic dout[588:0]" +Toggle 0to1 dout [31] "logic dout[588:0]" +Toggle 1to0 dout [31] "logic dout[588:0]" +Toggle 0to1 dout [32] "logic dout[588:0]" +Toggle 1to0 dout [32] "logic dout[588:0]" +Toggle 0to1 dout [33] "logic dout[588:0]" +Toggle 1to0 dout [33] "logic dout[588:0]" +Toggle 0to1 dout [34] "logic dout[588:0]" +Toggle 1to0 dout [34] "logic dout[588:0]" +Toggle 0to1 dout [35] "logic dout[588:0]" +Toggle 1to0 dout [35] "logic dout[588:0]" +Toggle 0to1 dout [2] "logic dout[588:0]" +Toggle 1to0 dout [2] "logic dout[588:0]" +Toggle 0to1 dout [3] "logic dout[588:0]" +Toggle 1to0 dout [3] "logic dout[588:0]" +Toggle 0to1 dout [4] "logic dout[588:0]" +Toggle 1to0 dout [4] "logic dout[588:0]" +Toggle 0to1 dout [5] "logic dout[588:0]" +Toggle 1to0 dout [5] "logic dout[588:0]" +Toggle 0to1 dout [6] "logic dout[588:0]" +Toggle 1to0 dout [6] "logic dout[588:0]" +Toggle 0to1 dout [7] "logic dout[588:0]" +Toggle 1to0 dout [7] "logic dout[588:0]" +Toggle 0to1 dout [8] "logic dout[588:0]" +Toggle 1to0 dout [8] "logic dout[588:0]" +Toggle 0to1 dout [9] "logic dout[588:0]" +Toggle 1to0 dout [9] "logic dout[588:0]" +Toggle 0to1 dout [10] "logic dout[588:0]" +Toggle 1to0 dout [10] "logic dout[588:0]" +Toggle 0to1 dout [11] "logic dout[588:0]" +Toggle 1to0 dout [11] "logic dout[588:0]" +Toggle 0to1 dout [12] "logic dout[588:0]" +Toggle 1to0 dout [12] "logic dout[588:0]" +Toggle 0to1 dout [13] "logic dout[588:0]" +Toggle 1to0 dout [13] "logic dout[588:0]" +Toggle 0to1 dout [14] "logic dout[588:0]" +Toggle 1to0 dout [14] "logic dout[588:0]" +Toggle 0to1 dout [15] "logic dout[588:0]" +Toggle 1to0 dout [15] "logic dout[588:0]" +Toggle 0to1 dout [16] "logic dout[588:0]" +Toggle 1to0 dout [16] "logic dout[588:0]" +Toggle 0to1 dout [17] "logic dout[588:0]" +Toggle 1to0 dout [17] "logic dout[588:0]" +Toggle 0to1 dout [18] "logic dout[588:0]" +Toggle 1to0 dout [18] "logic dout[588:0]" +Toggle 0to1 dout [19] "logic dout[588:0]" +Toggle 1to0 dout [19] "logic dout[588:0]" +Toggle 0to1 dout [20] "logic dout[588:0]" +Toggle 1to0 dout [20] "logic dout[588:0]" +Toggle 0to1 dout [21] "logic dout[588:0]" +Toggle 1to0 dout [21] "logic dout[588:0]" +Toggle 0to1 dout [22] "logic dout[588:0]" +Toggle 1to0 dout [22] "logic dout[588:0]" +Toggle 0to1 dout [23] "logic dout[588:0]" +Toggle 1to0 dout [23] "logic dout[588:0]" +Toggle 0to1 dout [24] "logic dout[588:0]" +Toggle 1to0 dout [24] "logic dout[588:0]" +Toggle 0to1 dout [25] "logic dout[588:0]" +Toggle 1to0 dout [25] "logic dout[588:0]" +Toggle 0to1 dout [26] "logic dout[588:0]" +Toggle 1to0 dout [26] "logic dout[588:0]" +Toggle 0to1 dout [27] "logic dout[588:0]" +Toggle 1to0 dout [27] "logic dout[588:0]" +Toggle 0to1 dout [28] "logic dout[588:0]" +Toggle 1to0 dout [28] "logic dout[588:0]" +Toggle 0to1 dout [29] "logic dout[588:0]" +Toggle 1to0 dout [29] "logic dout[588:0]" +Toggle 0to1 dout [96] "logic dout[588:0]" +Toggle 1to0 dout [96] "logic dout[588:0]" +Toggle 0to1 dout [97] "logic dout[588:0]" +Toggle 1to0 dout [97] "logic dout[588:0]" +Toggle 0to1 dout [103] "logic dout[588:0]" +Toggle 1to0 dout [103] "logic dout[588:0]" +Toggle 0to1 dout [104] "logic dout[588:0]" +Toggle 1to0 dout [104] "logic dout[588:0]" +Toggle 0to1 dout [105] "logic dout[588:0]" +Toggle 1to0 dout [105] "logic dout[588:0]" +Toggle 0to1 dout [106] "logic dout[588:0]" +Toggle 1to0 dout [106] "logic dout[588:0]" +Toggle 0to1 dout [107] "logic dout[588:0]" +Toggle 1to0 dout [107] "logic dout[588:0]" +Toggle 0to1 dout [109] "logic dout[588:0]" +Toggle 1to0 dout [109] "logic dout[588:0]" +Toggle 0to1 dout [110] "logic dout[588:0]" +Toggle 1to0 dout [110] "logic dout[588:0]" +Toggle 0to1 dout [111] "logic dout[588:0]" +Toggle 1to0 dout [111] "logic dout[588:0]" +Toggle 0to1 dout [112] "logic dout[588:0]" +Toggle 1to0 dout [112] "logic dout[588:0]" +Toggle 0to1 dout [113] "logic dout[588:0]" +Toggle 1to0 dout [113] "logic dout[588:0]" +Toggle 0to1 dout [114] "logic dout[588:0]" +Toggle 1to0 dout [114] "logic dout[588:0]" +Toggle 0to1 dout [115] "logic dout[588:0]" +Toggle 1to0 dout [115] "logic dout[588:0]" +Toggle 0to1 dout [116] "logic dout[588:0]" +Toggle 1to0 dout [116] "logic dout[588:0]" +Toggle 0to1 dout [117] "logic dout[588:0]" +Toggle 1to0 dout [117] "logic dout[588:0]" +Toggle 0to1 dout [118] "logic dout[588:0]" +Toggle 1to0 dout [118] "logic dout[588:0]" +Toggle 0to1 dout [119] "logic dout[588:0]" +Toggle 1to0 dout [119] "logic dout[588:0]" +Toggle 0to1 dout [120] "logic dout[588:0]" +Toggle 1to0 dout [120] "logic dout[588:0]" +Toggle 0to1 dout [121] "logic dout[588:0]" +Toggle 1to0 dout [121] "logic dout[588:0]" +Toggle 0to1 dout [122] "logic dout[588:0]" +Toggle 1to0 dout [122] "logic dout[588:0]" +Toggle 0to1 dout [123] "logic dout[588:0]" +Toggle 1to0 dout [123] "logic dout[588:0]" +Toggle 0to1 dout [124] "logic dout[588:0]" +Toggle 1to0 dout [124] "logic dout[588:0]" +Toggle 0to1 dout [125] "logic dout[588:0]" +Toggle 1to0 dout [125] "logic dout[588:0]" +Toggle 0to1 dout [126] "logic dout[588:0]" +Toggle 1to0 dout [126] "logic dout[588:0]" +Toggle 0to1 dout [127] "logic dout[588:0]" +Toggle 1to0 dout [127] "logic dout[588:0]" +Toggle 0to1 dout [128] "logic dout[588:0]" +Toggle 1to0 dout [128] "logic dout[588:0]" +Toggle 0to1 dout [129] "logic dout[588:0]" +Toggle 1to0 dout [129] "logic dout[588:0]" +Toggle 0to1 dout [130] "logic dout[588:0]" +Toggle 1to0 dout [130] "logic dout[588:0]" +Toggle 0to1 dout [131] "logic dout[588:0]" +Toggle 1to0 dout [131] "logic dout[588:0]" +Toggle 0to1 dout [132] "logic dout[588:0]" +Toggle 1to0 dout [132] "logic dout[588:0]" +Toggle 0to1 dout [133] "logic dout[588:0]" +Toggle 1to0 dout [133] "logic dout[588:0]" +Toggle 0to1 dout [134] "logic dout[588:0]" +Toggle 1to0 dout [134] "logic dout[588:0]" +Toggle 0to1 dout [135] "logic dout[588:0]" +Toggle 1to0 dout [135] "logic dout[588:0]" +Toggle 0to1 dout [136] "logic dout[588:0]" +Toggle 1to0 dout [136] "logic dout[588:0]" +Toggle 0to1 dout [137] "logic dout[588:0]" +Toggle 1to0 dout [137] "logic dout[588:0]" +Toggle 0to1 dout [138] "logic dout[588:0]" +Toggle 1to0 dout [138] "logic dout[588:0]" +Toggle 0to1 dout [139] "logic dout[588:0]" +Toggle 1to0 dout [139] "logic dout[588:0]" +Toggle 0to1 dout [140] "logic dout[588:0]" +Toggle 1to0 dout [140] "logic dout[588:0]" +Toggle 0to1 dout [141] "logic dout[588:0]" +Toggle 1to0 dout [141] "logic dout[588:0]" +Toggle 0to1 dout [142] "logic dout[588:0]" +Toggle 1to0 dout [142] "logic dout[588:0]" +Toggle 0to1 dout [143] "logic dout[588:0]" +Toggle 1to0 dout [143] "logic dout[588:0]" +Toggle 0to1 dout [144] "logic dout[588:0]" +Toggle 1to0 dout [144] "logic dout[588:0]" +Toggle 0to1 dout [145] "logic dout[588:0]" +Toggle 1to0 dout [145] "logic dout[588:0]" +Toggle 0to1 dout [146] "logic dout[588:0]" +Toggle 1to0 dout [146] "logic dout[588:0]" +Toggle 0to1 dout [147] "logic dout[588:0]" +Toggle 1to0 dout [147] "logic dout[588:0]" +Toggle 0to1 dout [148] "logic dout[588:0]" +Toggle 1to0 dout [148] "logic dout[588:0]" +Toggle 0to1 dout [149] "logic dout[588:0]" +Toggle 1to0 dout [149] "logic dout[588:0]" +Toggle 0to1 dout [150] "logic dout[588:0]" +Toggle 1to0 dout [150] "logic dout[588:0]" +Toggle 0to1 dout [151] "logic dout[588:0]" +Toggle 1to0 dout [151] "logic dout[588:0]" +Toggle 0to1 dout [152] "logic dout[588:0]" +Toggle 1to0 dout [152] "logic dout[588:0]" +Toggle 0to1 dout [153] "logic dout[588:0]" +Toggle 1to0 dout [153] "logic dout[588:0]" +Toggle 0to1 dout [154] "logic dout[588:0]" +Toggle 1to0 dout [154] "logic dout[588:0]" +Toggle 0to1 dout [155] "logic dout[588:0]" +Toggle 1to0 dout [155] "logic dout[588:0]" +Toggle 0to1 dout [156] "logic dout[588:0]" +Toggle 1to0 dout [156] "logic dout[588:0]" +Toggle 0to1 dout [157] "logic dout[588:0]" +Toggle 1to0 dout [157] "logic dout[588:0]" +Toggle 0to1 dout [158] "logic dout[588:0]" +Toggle 1to0 dout [158] "logic dout[588:0]" +Toggle 0to1 dout [159] "logic dout[588:0]" +Toggle 1to0 dout [159] "logic dout[588:0]" +Toggle 0to1 dout [160] "logic dout[588:0]" +Toggle 1to0 dout [160] "logic dout[588:0]" +Toggle 0to1 dout [161] "logic dout[588:0]" +Toggle 1to0 dout [161] "logic dout[588:0]" +Toggle 0to1 dout [162] "logic dout[588:0]" +Toggle 1to0 dout [162] "logic dout[588:0]" +Toggle 0to1 dout [163] "logic dout[588:0]" +Toggle 1to0 dout [163] "logic dout[588:0]" +Toggle 0to1 dout [164] "logic dout[588:0]" +Toggle 1to0 dout [164] "logic dout[588:0]" +Toggle 0to1 dout [165] "logic dout[588:0]" +Toggle 1to0 dout [165] "logic dout[588:0]" +Toggle 0to1 dout [166] "logic dout[588:0]" +Toggle 1to0 dout [166] "logic dout[588:0]" +Toggle 0to1 dout [167] "logic dout[588:0]" +Toggle 1to0 dout [167] "logic dout[588:0]" +Toggle 0to1 dout [168] "logic dout[588:0]" +Toggle 1to0 dout [168] "logic dout[588:0]" +Toggle 0to1 dout [169] "logic dout[588:0]" +Toggle 1to0 dout [169] "logic dout[588:0]" +Toggle 0to1 dout [170] "logic dout[588:0]" +Toggle 1to0 dout [170] "logic dout[588:0]" +Toggle 0to1 dout [171] "logic dout[588:0]" +Toggle 1to0 dout [171] "logic dout[588:0]" +Toggle 0to1 dout [172] "logic dout[588:0]" +Toggle 1to0 dout [172] "logic dout[588:0]" +Toggle 0to1 dout [173] "logic dout[588:0]" +Toggle 1to0 dout [173] "logic dout[588:0]" +Toggle 0to1 dout [174] "logic dout[588:0]" +Toggle 1to0 dout [174] "logic dout[588:0]" +Toggle 0to1 dout [175] "logic dout[588:0]" +Toggle 1to0 dout [175] "logic dout[588:0]" +Toggle 0to1 dout [176] "logic dout[588:0]" +Toggle 1to0 dout [176] "logic dout[588:0]" +Toggle 0to1 dout [177] "logic dout[588:0]" +Toggle 1to0 dout [177] "logic dout[588:0]" +Toggle 0to1 dout [178] "logic dout[588:0]" +Toggle 1to0 dout [178] "logic dout[588:0]" +Toggle 0to1 dout [179] "logic dout[588:0]" +Toggle 1to0 dout [179] "logic dout[588:0]" +Toggle 0to1 dout [180] "logic dout[588:0]" +Toggle 1to0 dout [180] "logic dout[588:0]" +Toggle 0to1 dout [181] "logic dout[588:0]" +Toggle 1to0 dout [181] "logic dout[588:0]" +Toggle 0to1 dout [182] "logic dout[588:0]" +Toggle 1to0 dout [182] "logic dout[588:0]" +Toggle 0to1 dout [183] "logic dout[588:0]" +Toggle 1to0 dout [183] "logic dout[588:0]" +Toggle 0to1 dout [184] "logic dout[588:0]" +Toggle 1to0 dout [184] "logic dout[588:0]" +Toggle 0to1 dout [185] "logic dout[588:0]" +Toggle 1to0 dout [185] "logic dout[588:0]" +Toggle 0to1 dout [186] "logic dout[588:0]" +Toggle 1to0 dout [186] "logic dout[588:0]" +Toggle 0to1 dout [187] "logic dout[588:0]" +Toggle 1to0 dout [187] "logic dout[588:0]" +Toggle 0to1 dout [188] "logic dout[588:0]" +Toggle 1to0 dout [188] "logic dout[588:0]" +Toggle 0to1 dout [189] "logic dout[588:0]" +Toggle 1to0 dout [189] "logic dout[588:0]" +Toggle 0to1 dout [190] "logic dout[588:0]" +Toggle 1to0 dout [190] "logic dout[588:0]" +Toggle 0to1 dout [191] "logic dout[588:0]" +Toggle 1to0 dout [191] "logic dout[588:0]" +Toggle 0to1 dout [192] "logic dout[588:0]" +Toggle 1to0 dout [192] "logic dout[588:0]" +Toggle 0to1 dout [193] "logic dout[588:0]" +Toggle 1to0 dout [193] "logic dout[588:0]" +Toggle 0to1 dout [194] "logic dout[588:0]" +Toggle 1to0 dout [194] "logic dout[588:0]" +Toggle 0to1 dout [195] "logic dout[588:0]" +Toggle 1to0 dout [195] "logic dout[588:0]" +Toggle 0to1 dout [196] "logic dout[588:0]" +Toggle 1to0 dout [196] "logic dout[588:0]" +Toggle 0to1 dout [197] "logic dout[588:0]" +Toggle 1to0 dout [197] "logic dout[588:0]" +Toggle 0to1 dout [198] "logic dout[588:0]" +Toggle 1to0 dout [198] "logic dout[588:0]" +Toggle 0to1 dout [199] "logic dout[588:0]" +Toggle 1to0 dout [199] "logic dout[588:0]" +Toggle 0to1 dout [200] "logic dout[588:0]" +Toggle 1to0 dout [200] "logic dout[588:0]" +Toggle 0to1 dout [201] "logic dout[588:0]" +Toggle 1to0 dout [201] "logic dout[588:0]" +Toggle 0to1 dout [202] "logic dout[588:0]" +Toggle 1to0 dout [202] "logic dout[588:0]" +Toggle 0to1 dout [203] "logic dout[588:0]" +Toggle 1to0 dout [203] "logic dout[588:0]" +Toggle 0to1 dout [204] "logic dout[588:0]" +Toggle 1to0 dout [204] "logic dout[588:0]" +Toggle 0to1 dout [205] "logic dout[588:0]" +Toggle 1to0 dout [205] "logic dout[588:0]" +Toggle 0to1 dout [206] "logic dout[588:0]" +Toggle 1to0 dout [206] "logic dout[588:0]" +Toggle 0to1 dout [207] "logic dout[588:0]" +Toggle 1to0 dout [207] "logic dout[588:0]" +Toggle 0to1 dout [208] "logic dout[588:0]" +Toggle 1to0 dout [208] "logic dout[588:0]" +Toggle 0to1 dout [209] "logic dout[588:0]" +Toggle 1to0 dout [209] "logic dout[588:0]" +Toggle 0to1 dout [210] "logic dout[588:0]" +Toggle 1to0 dout [210] "logic dout[588:0]" +Toggle 0to1 dout [211] "logic dout[588:0]" +Toggle 1to0 dout [211] "logic dout[588:0]" +Toggle 0to1 dout [212] "logic dout[588:0]" +Toggle 1to0 dout [212] "logic dout[588:0]" +Toggle 0to1 dout [213] "logic dout[588:0]" +Toggle 1to0 dout [213] "logic dout[588:0]" +Toggle 0to1 dout [214] "logic dout[588:0]" +Toggle 1to0 dout [214] "logic dout[588:0]" +Toggle 0to1 dout [215] "logic dout[588:0]" +Toggle 1to0 dout [215] "logic dout[588:0]" +Toggle 0to1 dout [216] "logic dout[588:0]" +Toggle 1to0 dout [216] "logic dout[588:0]" +Toggle 0to1 dout [217] "logic dout[588:0]" +Toggle 1to0 dout [217] "logic dout[588:0]" +Toggle 0to1 dout [218] "logic dout[588:0]" +Toggle 1to0 dout [218] "logic dout[588:0]" +Toggle 0to1 dout [219] "logic dout[588:0]" +Toggle 1to0 dout [219] "logic dout[588:0]" +Toggle 0to1 dout [220] "logic dout[588:0]" +Toggle 1to0 dout [220] "logic dout[588:0]" +Toggle 0to1 dout [221] "logic dout[588:0]" +Toggle 1to0 dout [221] "logic dout[588:0]" +Toggle 0to1 dout [222] "logic dout[588:0]" +Toggle 1to0 dout [222] "logic dout[588:0]" +Toggle 0to1 dout [223] "logic dout[588:0]" +Toggle 1to0 dout [223] "logic dout[588:0]" +Toggle 0to1 dout [224] "logic dout[588:0]" +Toggle 1to0 dout [224] "logic dout[588:0]" +Toggle 0to1 dout [225] "logic dout[588:0]" +Toggle 1to0 dout [225] "logic dout[588:0]" +Toggle 0to1 dout [226] "logic dout[588:0]" +Toggle 1to0 dout [226] "logic dout[588:0]" +Toggle 0to1 dout [227] "logic dout[588:0]" +Toggle 1to0 dout [227] "logic dout[588:0]" +Toggle 0to1 dout [228] "logic dout[588:0]" +Toggle 1to0 dout [228] "logic dout[588:0]" +Toggle 0to1 dout [229] "logic dout[588:0]" +Toggle 1to0 dout [229] "logic dout[588:0]" +Toggle 0to1 dout [230] "logic dout[588:0]" +Toggle 1to0 dout [230] "logic dout[588:0]" +Toggle 0to1 dout [231] "logic dout[588:0]" +Toggle 1to0 dout [231] "logic dout[588:0]" +Toggle 0to1 dout [232] "logic dout[588:0]" +Toggle 1to0 dout [232] "logic dout[588:0]" +Toggle 0to1 dout [233] "logic dout[588:0]" +Toggle 1to0 dout [233] "logic dout[588:0]" +Toggle 0to1 dout [234] "logic dout[588:0]" +Toggle 1to0 dout [234] "logic dout[588:0]" +Toggle 0to1 dout [235] "logic dout[588:0]" +Toggle 1to0 dout [235] "logic dout[588:0]" +Toggle 0to1 dout [236] "logic dout[588:0]" +Toggle 1to0 dout [236] "logic dout[588:0]" +Toggle 0to1 dout [237] "logic dout[588:0]" +Toggle 1to0 dout [237] "logic dout[588:0]" +Toggle 0to1 dout [238] "logic dout[588:0]" +Toggle 1to0 dout [238] "logic dout[588:0]" +Toggle 0to1 dout [239] "logic dout[588:0]" +Toggle 1to0 dout [239] "logic dout[588:0]" +Toggle 0to1 dout [240] "logic dout[588:0]" +Toggle 1to0 dout [240] "logic dout[588:0]" +Toggle 0to1 dout [241] "logic dout[588:0]" +Toggle 1to0 dout [241] "logic dout[588:0]" +Toggle 0to1 dout [242] "logic dout[588:0]" +Toggle 1to0 dout [242] "logic dout[588:0]" +Toggle 0to1 dout [243] "logic dout[588:0]" +Toggle 1to0 dout [243] "logic dout[588:0]" +Toggle 0to1 dout [244] "logic dout[588:0]" +Toggle 1to0 dout [244] "logic dout[588:0]" +Toggle 0to1 dout [245] "logic dout[588:0]" +Toggle 1to0 dout [245] "logic dout[588:0]" +Toggle 0to1 dout [246] "logic dout[588:0]" +Toggle 1to0 dout [246] "logic dout[588:0]" +Toggle 0to1 dout [247] "logic dout[588:0]" +Toggle 1to0 dout [247] "logic dout[588:0]" +Toggle 0to1 dout [248] "logic dout[588:0]" +Toggle 1to0 dout [248] "logic dout[588:0]" +Toggle 0to1 dout [249] "logic dout[588:0]" +Toggle 1to0 dout [249] "logic dout[588:0]" +Toggle 0to1 dout [250] "logic dout[588:0]" +Toggle 1to0 dout [250] "logic dout[588:0]" +Toggle 0to1 dout [251] "logic dout[588:0]" +Toggle 1to0 dout [251] "logic dout[588:0]" +Toggle 0to1 dout [252] "logic dout[588:0]" +Toggle 1to0 dout [252] "logic dout[588:0]" +Toggle 0to1 dout [253] "logic dout[588:0]" +Toggle 1to0 dout [253] "logic dout[588:0]" +Toggle 0to1 dout [254] "logic dout[588:0]" +Toggle 1to0 dout [254] "logic dout[588:0]" +Toggle 1to0 dout [108] "logic dout[588:0]" +Toggle 0to1 dout [95] "logic dout[588:0]" +Toggle 1to0 dout [95] "logic dout[588:0]" +Toggle 0to1 dout [75] "logic dout[588:0]" +Toggle 1to0 dout [75] "logic dout[588:0]" +Toggle 0to1 dout [77] "logic dout[588:0]" +Toggle 1to0 dout [77] "logic dout[588:0]" +Toggle 0to1 dout [78] "logic dout[588:0]" +Toggle 1to0 dout [78] "logic dout[588:0]" +Toggle 0to1 dout [79] "logic dout[588:0]" +Toggle 1to0 dout [79] "logic dout[588:0]" +Toggle 0to1 dout [80] "logic dout[588:0]" +Toggle 1to0 dout [80] "logic dout[588:0]" +Toggle 0to1 dout [81] "logic dout[588:0]" +Toggle 1to0 dout [81] "logic dout[588:0]" +Toggle 0to1 dout [82] "logic dout[588:0]" +Toggle 1to0 dout [82] "logic dout[588:0]" +Toggle 0to1 dout [83] "logic dout[588:0]" +Toggle 1to0 dout [83] "logic dout[588:0]" +Toggle 0to1 dout [84] "logic dout[588:0]" +Toggle 1to0 dout [84] "logic dout[588:0]" +Toggle 0to1 dout [86] "logic dout[588:0]" +Toggle 1to0 dout [86] "logic dout[588:0]" +Toggle 0to1 dout [85] "logic dout[588:0]" +Toggle 1to0 dout [85] "logic dout[588:0]" +Toggle 0to1 dout [87] "logic dout[588:0]" +Toggle 1to0 dout [87] "logic dout[588:0]" +Toggle 0to1 dout [88] "logic dout[588:0]" +Toggle 1to0 dout [88] "logic dout[588:0]" +Toggle 0to1 dout [89] "logic dout[588:0]" +Toggle 1to0 dout [89] "logic dout[588:0]" +Toggle 0to1 dout [90] "logic dout[588:0]" +Toggle 1to0 dout [90] "logic dout[588:0]" +Toggle 0to1 dout [91] "logic dout[588:0]" +Toggle 1to0 dout [91] "logic dout[588:0]" +Toggle 0to1 dout [92] "logic dout[588:0]" +Toggle 1to0 dout [92] "logic dout[588:0]" +Toggle 0to1 dout [93] "logic dout[588:0]" +Toggle 1to0 dout [93] "logic dout[588:0]" +Toggle 0to1 dout [94] "logic dout[588:0]" +Toggle 1to0 dout [94] "logic dout[588:0]" +Toggle 1to0 dout [76] "logic dout[588:0]" +Toggle 0to1 dout [74] "logic dout[588:0]" +Toggle 1to0 dout [74] "logic dout[588:0]" +Toggle 0to1 dout [71] "logic dout[588:0]" +Toggle 1to0 dout [71] "logic dout[588:0]" +Toggle 0to1 dout [72] "logic dout[588:0]" +Toggle 1to0 dout [72] "logic dout[588:0]" +Toggle 0to1 dout [73] "logic dout[588:0]" +Toggle 1to0 dout [73] "logic dout[588:0]" +CHECKSUM: "3190985420 1606079823" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a.switch.M_mux[0].out_q.fifo_ram +Toggle 0to1 perr "logic perr" +Toggle 1to0 perr "logic perr" +Toggle 0to1 perr_or "logic perr_or" +Toggle 1to0 perr_or "logic perr_or" +Toggle perr_in "logic perr_in[18:0]" +CHECKSUM: "3190985420 1606079823" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a.switch.N_mux[0].out_q.fifo_ram +Toggle 0to1 perr "logic perr" +Toggle 1to0 perr "logic perr" +Toggle perr_in "logic perr_in[18:0]" +Toggle 0to1 perr_or "logic perr_or" +Toggle 1to0 perr_or "logic perr_or" +CHECKSUM: "3190985420 1606079823" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a.switch.N_mux[1].out_q.fifo_ram +Toggle 0to1 perr "logic perr" +Toggle 1to0 perr "logic perr" +Toggle 0to1 perr_or "logic perr_or" +Toggle 1to0 perr_or "logic perr_or" +Toggle perr_in "logic perr_in[18:0]" +CHECKSUM: "3190985420 1606079823" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_a.switch.N_mux[3].out_q.fifo_ram +Toggle 0to1 perr_or "logic perr_or" +Toggle 1to0 perr_or "logic perr_or" +Toggle 0to1 perr "logic perr" +Toggle 1to0 perr "logic perr" +Toggle perr_in "logic perr_in[18:0]" +Toggle 0to1 ram_dout [375] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [375] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [96] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [96] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [97] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [97] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [103] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [103] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [104] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [104] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [105] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [105] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [106] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [106] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [107] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [107] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [109] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [109] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [110] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [110] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [111] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [111] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [112] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [112] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [113] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [113] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [114] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [114] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [115] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [115] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [116] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [116] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [117] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [117] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [118] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [118] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [119] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [119] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [120] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [120] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [121] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [121] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [122] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [122] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [123] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [123] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [124] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [124] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [125] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [125] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [126] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [126] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [127] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [127] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [128] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [128] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [129] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [129] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [130] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [130] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [131] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [131] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [132] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [132] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [133] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [133] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [134] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [134] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [135] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [135] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [136] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [136] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [137] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [137] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [138] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [138] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [139] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [139] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [140] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [140] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [141] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [141] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [142] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [142] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [143] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [143] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [144] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [144] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [145] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [145] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [146] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [146] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [147] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [147] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [148] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [148] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [149] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [149] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [150] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [150] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [151] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [151] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [152] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [152] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [153] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [153] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [154] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [154] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [155] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [155] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [156] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [156] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [157] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [157] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [158] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [158] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [159] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [159] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [160] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [160] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [161] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [161] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [162] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [162] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [163] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [163] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [164] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [164] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [165] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [165] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [166] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [166] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [167] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [167] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [168] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [168] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [169] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [169] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [170] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [170] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [171] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [171] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [172] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [172] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [173] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [173] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [174] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [174] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [175] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [175] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [176] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [176] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [177] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [177] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [178] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [178] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [179] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [179] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [180] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [180] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [181] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [181] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [182] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [182] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [183] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [183] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [184] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [184] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [185] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [185] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [186] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [186] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [187] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [187] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [188] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [188] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [189] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [189] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [190] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [190] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [191] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [191] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [192] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [192] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [193] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [193] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [194] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [194] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [195] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [195] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [196] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [196] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [197] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [197] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [198] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [198] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [199] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [199] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [200] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [200] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [201] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [201] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [202] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [202] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [203] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [203] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [204] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [204] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [205] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [205] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [206] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [206] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [207] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [207] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [208] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [208] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [209] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [209] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [210] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [210] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [211] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [211] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [212] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [212] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [213] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [213] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [214] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [214] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [215] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [215] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [216] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [216] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [217] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [217] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [218] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [218] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [219] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [219] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [220] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [220] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [221] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [221] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [222] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [222] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [223] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [223] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [224] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [224] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [225] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [225] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [226] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [226] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [227] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [227] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [228] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [228] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [229] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [229] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [230] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [230] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [231] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [231] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [232] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [232] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [233] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [233] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [234] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [234] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [235] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [235] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [236] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [236] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [237] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [237] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [238] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [238] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [239] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [239] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [240] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [240] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [241] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [241] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [242] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [242] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [243] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [243] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [244] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [244] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [245] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [245] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [246] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [246] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [247] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [247] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [248] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [248] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [249] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [249] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [250] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [250] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [251] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [251] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [252] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [252] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [253] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [253] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [254] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [254] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [255] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [255] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [374] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [374] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [373] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [373] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [372] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [372] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [95] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [95] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [78] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [78] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [79] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [79] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [80] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [80] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [81] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [81] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [82] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [82] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [83] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [83] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [84] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [84] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [85] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [85] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [86] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [86] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [87] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [87] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [88] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [88] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [89] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [89] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [90] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [90] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [91] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [91] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [92] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [92] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [93] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [93] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [94] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [94] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [77] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [77] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [71] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [71] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [72] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [72] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [73] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [73] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [74] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [74] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [75] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [75] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [65] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [65] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [2] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [2] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [3] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [3] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [4] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [4] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [5] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [5] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [6] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [6] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [7] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [7] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [8] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [8] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [9] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [9] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [10] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [10] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [11] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [11] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [12] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [12] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [13] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [13] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [14] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [14] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [15] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [15] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [16] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [16] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [17] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [17] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [18] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [18] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [19] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [19] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [20] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [20] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [21] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [21] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [22] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [22] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [23] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [23] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [24] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [24] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [25] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [25] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [26] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [26] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [27] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [27] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [28] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [28] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [29] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [29] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [31] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [31] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [32] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [32] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [33] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [33] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [34] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [34] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [35] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [35] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [48] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [48] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [49] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [49] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [50] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [50] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [51] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [51] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [52] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [52] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [53] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [53] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [54] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [54] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [55] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [55] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [56] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [56] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [57] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [57] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [58] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [58] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [59] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [59] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [60] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [60] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [61] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [61] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [62] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [62] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [63] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [63] "logic ram_dout[588:0]" +Toggle 0to1 ram_dout [64] "logic ram_dout[588:0]" +Toggle 1to0 ram_dout [64] "logic ram_dout[588:0]" +Toggle 0to1 dout [375] "logic dout[588:0]" +Toggle 1to0 dout [375] "logic dout[588:0]" +Toggle 0to1 dout [96] "logic dout[588:0]" +Toggle 1to0 dout [96] "logic dout[588:0]" +Toggle 0to1 dout [97] "logic dout[588:0]" +Toggle 1to0 dout [97] "logic dout[588:0]" +Toggle 0to1 dout [103] "logic dout[588:0]" +Toggle 1to0 dout [103] "logic dout[588:0]" +Toggle 0to1 dout [104] "logic dout[588:0]" +Toggle 1to0 dout [104] "logic dout[588:0]" +Toggle 0to1 dout [105] "logic dout[588:0]" +Toggle 1to0 dout [105] "logic dout[588:0]" +Toggle 0to1 dout [106] "logic dout[588:0]" +Toggle 1to0 dout [106] "logic dout[588:0]" +Toggle 0to1 dout [107] "logic dout[588:0]" +Toggle 1to0 dout [107] "logic dout[588:0]" +Toggle 0to1 dout [109] "logic dout[588:0]" +Toggle 1to0 dout [109] "logic dout[588:0]" +Toggle 0to1 dout [110] "logic dout[588:0]" +Toggle 1to0 dout [110] "logic dout[588:0]" +Toggle 0to1 dout [111] "logic dout[588:0]" +Toggle 1to0 dout [111] "logic dout[588:0]" +Toggle 0to1 dout [112] "logic dout[588:0]" +Toggle 1to0 dout [112] "logic dout[588:0]" +Toggle 0to1 dout [113] "logic dout[588:0]" +Toggle 1to0 dout [113] "logic dout[588:0]" +Toggle 0to1 dout [114] "logic dout[588:0]" +Toggle 1to0 dout [114] "logic dout[588:0]" +Toggle 0to1 dout [115] "logic dout[588:0]" +Toggle 1to0 dout [115] "logic dout[588:0]" +Toggle 0to1 dout [116] "logic dout[588:0]" +Toggle 1to0 dout [116] "logic dout[588:0]" +Toggle 0to1 dout [117] "logic dout[588:0]" +Toggle 1to0 dout [117] "logic dout[588:0]" +Toggle 0to1 dout [118] "logic dout[588:0]" +Toggle 1to0 dout [118] "logic dout[588:0]" +Toggle 0to1 dout [119] "logic dout[588:0]" +Toggle 1to0 dout [119] "logic dout[588:0]" +Toggle 0to1 dout [120] "logic dout[588:0]" +Toggle 1to0 dout [120] "logic dout[588:0]" +Toggle 0to1 dout [121] "logic dout[588:0]" +Toggle 1to0 dout [121] "logic dout[588:0]" +Toggle 0to1 dout [122] "logic dout[588:0]" +Toggle 1to0 dout [122] "logic dout[588:0]" +Toggle 0to1 dout [123] "logic dout[588:0]" +Toggle 1to0 dout [123] "logic dout[588:0]" +Toggle 0to1 dout [124] "logic dout[588:0]" +Toggle 1to0 dout [124] "logic dout[588:0]" +Toggle 0to1 dout [125] "logic dout[588:0]" +Toggle 1to0 dout [125] "logic dout[588:0]" +Toggle 0to1 dout [126] "logic dout[588:0]" +Toggle 1to0 dout [126] "logic dout[588:0]" +Toggle 0to1 dout [127] "logic dout[588:0]" +Toggle 1to0 dout [127] "logic dout[588:0]" +Toggle 0to1 dout [128] "logic dout[588:0]" +Toggle 1to0 dout [128] "logic dout[588:0]" +Toggle 0to1 dout [129] "logic dout[588:0]" +Toggle 1to0 dout [129] "logic dout[588:0]" +Toggle 0to1 dout [130] "logic dout[588:0]" +Toggle 1to0 dout [130] "logic dout[588:0]" +Toggle 0to1 dout [131] "logic dout[588:0]" +Toggle 1to0 dout [131] "logic dout[588:0]" +Toggle 0to1 dout [132] "logic dout[588:0]" +Toggle 1to0 dout [132] "logic dout[588:0]" +Toggle 0to1 dout [133] "logic dout[588:0]" +Toggle 1to0 dout [133] "logic dout[588:0]" +Toggle 0to1 dout [134] "logic dout[588:0]" +Toggle 1to0 dout [134] "logic dout[588:0]" +Toggle 0to1 dout [135] "logic dout[588:0]" +Toggle 1to0 dout [135] "logic dout[588:0]" +Toggle 0to1 dout [136] "logic dout[588:0]" +Toggle 1to0 dout [136] "logic dout[588:0]" +Toggle 0to1 dout [137] "logic dout[588:0]" +Toggle 1to0 dout [137] "logic dout[588:0]" +Toggle 0to1 dout [138] "logic dout[588:0]" +Toggle 1to0 dout [138] "logic dout[588:0]" +Toggle 0to1 dout [139] "logic dout[588:0]" +Toggle 1to0 dout [139] "logic dout[588:0]" +Toggle 0to1 dout [140] "logic dout[588:0]" +Toggle 1to0 dout [140] "logic dout[588:0]" +Toggle 0to1 dout [141] "logic dout[588:0]" +Toggle 1to0 dout [141] "logic dout[588:0]" +Toggle 0to1 dout [142] "logic dout[588:0]" +Toggle 1to0 dout [142] "logic dout[588:0]" +Toggle 0to1 dout [143] "logic dout[588:0]" +Toggle 1to0 dout [143] "logic dout[588:0]" +Toggle 0to1 dout [144] "logic dout[588:0]" +Toggle 1to0 dout [144] "logic dout[588:0]" +Toggle 0to1 dout [145] "logic dout[588:0]" +Toggle 1to0 dout [145] "logic dout[588:0]" +Toggle 0to1 dout [146] "logic dout[588:0]" +Toggle 1to0 dout [146] "logic dout[588:0]" +Toggle 0to1 dout [147] "logic dout[588:0]" +Toggle 1to0 dout [147] "logic dout[588:0]" +Toggle 0to1 dout [148] "logic dout[588:0]" +Toggle 1to0 dout [148] "logic dout[588:0]" +Toggle 0to1 dout [149] "logic dout[588:0]" +Toggle 1to0 dout [149] "logic dout[588:0]" +Toggle 0to1 dout [150] "logic dout[588:0]" +Toggle 1to0 dout [150] "logic dout[588:0]" +Toggle 0to1 dout [151] "logic dout[588:0]" +Toggle 1to0 dout [151] "logic dout[588:0]" +Toggle 0to1 dout [152] "logic dout[588:0]" +Toggle 1to0 dout [152] "logic dout[588:0]" +Toggle 0to1 dout [153] "logic dout[588:0]" +Toggle 1to0 dout [153] "logic dout[588:0]" +Toggle 0to1 dout [154] "logic dout[588:0]" +Toggle 1to0 dout [154] "logic dout[588:0]" +Toggle 0to1 dout [155] "logic dout[588:0]" +Toggle 1to0 dout [155] "logic dout[588:0]" +Toggle 0to1 dout [156] "logic dout[588:0]" +Toggle 1to0 dout [156] "logic dout[588:0]" +Toggle 0to1 dout [157] "logic dout[588:0]" +Toggle 1to0 dout [157] "logic dout[588:0]" +Toggle 0to1 dout [158] "logic dout[588:0]" +Toggle 1to0 dout [158] "logic dout[588:0]" +Toggle 0to1 dout [159] "logic dout[588:0]" +Toggle 1to0 dout [159] "logic dout[588:0]" +Toggle 0to1 dout [160] "logic dout[588:0]" +Toggle 1to0 dout [160] "logic dout[588:0]" +Toggle 0to1 dout [161] "logic dout[588:0]" +Toggle 1to0 dout [161] "logic dout[588:0]" +Toggle 0to1 dout [162] "logic dout[588:0]" +Toggle 1to0 dout [162] "logic dout[588:0]" +Toggle 0to1 dout [163] "logic dout[588:0]" +Toggle 1to0 dout [163] "logic dout[588:0]" +Toggle 0to1 dout [164] "logic dout[588:0]" +Toggle 1to0 dout [164] "logic dout[588:0]" +Toggle 0to1 dout [165] "logic dout[588:0]" +Toggle 1to0 dout [165] "logic dout[588:0]" +Toggle 0to1 dout [166] "logic dout[588:0]" +Toggle 1to0 dout [166] "logic dout[588:0]" +Toggle 0to1 dout [167] "logic dout[588:0]" +Toggle 1to0 dout [167] "logic dout[588:0]" +Toggle 0to1 dout [168] "logic dout[588:0]" +Toggle 1to0 dout [168] "logic dout[588:0]" +Toggle 0to1 dout [169] "logic dout[588:0]" +Toggle 1to0 dout [169] "logic dout[588:0]" +Toggle 0to1 dout [170] "logic dout[588:0]" +Toggle 1to0 dout [170] "logic dout[588:0]" +Toggle 0to1 dout [171] "logic dout[588:0]" +Toggle 1to0 dout [171] "logic dout[588:0]" +Toggle 0to1 dout [172] "logic dout[588:0]" +Toggle 1to0 dout [172] "logic dout[588:0]" +Toggle 0to1 dout [173] "logic dout[588:0]" +Toggle 1to0 dout [173] "logic dout[588:0]" +Toggle 0to1 dout [174] "logic dout[588:0]" +Toggle 1to0 dout [174] "logic dout[588:0]" +Toggle 0to1 dout [175] "logic dout[588:0]" +Toggle 1to0 dout [175] "logic dout[588:0]" +Toggle 0to1 dout [176] "logic dout[588:0]" +Toggle 1to0 dout [176] "logic dout[588:0]" +Toggle 0to1 dout [177] "logic dout[588:0]" +Toggle 1to0 dout [177] "logic dout[588:0]" +Toggle 0to1 dout [178] "logic dout[588:0]" +Toggle 1to0 dout [178] "logic dout[588:0]" +Toggle 0to1 dout [179] "logic dout[588:0]" +Toggle 1to0 dout [179] "logic dout[588:0]" +Toggle 0to1 dout [180] "logic dout[588:0]" +Toggle 1to0 dout [180] "logic dout[588:0]" +Toggle 0to1 dout [181] "logic dout[588:0]" +Toggle 1to0 dout [181] "logic dout[588:0]" +Toggle 0to1 dout [182] "logic dout[588:0]" +Toggle 1to0 dout [182] "logic dout[588:0]" +Toggle 0to1 dout [183] "logic dout[588:0]" +Toggle 1to0 dout [183] "logic dout[588:0]" +Toggle 0to1 dout [184] "logic dout[588:0]" +Toggle 1to0 dout [184] "logic dout[588:0]" +Toggle 0to1 dout [185] "logic dout[588:0]" +Toggle 1to0 dout [185] "logic dout[588:0]" +Toggle 0to1 dout [186] "logic dout[588:0]" +Toggle 1to0 dout [186] "logic dout[588:0]" +Toggle 0to1 dout [187] "logic dout[588:0]" +Toggle 1to0 dout [187] "logic dout[588:0]" +Toggle 0to1 dout [188] "logic dout[588:0]" +Toggle 1to0 dout [188] "logic dout[588:0]" +Toggle 0to1 dout [189] "logic dout[588:0]" +Toggle 1to0 dout [189] "logic dout[588:0]" +Toggle 0to1 dout [190] "logic dout[588:0]" +Toggle 1to0 dout [190] "logic dout[588:0]" +Toggle 0to1 dout [191] "logic dout[588:0]" +Toggle 1to0 dout [191] "logic dout[588:0]" +Toggle 0to1 dout [192] "logic dout[588:0]" +Toggle 1to0 dout [192] "logic dout[588:0]" +Toggle 0to1 dout [193] "logic dout[588:0]" +Toggle 1to0 dout [193] "logic dout[588:0]" +Toggle 0to1 dout [194] "logic dout[588:0]" +Toggle 1to0 dout [194] "logic dout[588:0]" +Toggle 0to1 dout [195] "logic dout[588:0]" +Toggle 1to0 dout [195] "logic dout[588:0]" +Toggle 0to1 dout [196] "logic dout[588:0]" +Toggle 1to0 dout [196] "logic dout[588:0]" +Toggle 0to1 dout [197] "logic dout[588:0]" +Toggle 1to0 dout [197] "logic dout[588:0]" +Toggle 0to1 dout [198] "logic dout[588:0]" +Toggle 1to0 dout [198] "logic dout[588:0]" +Toggle 0to1 dout [199] "logic dout[588:0]" +Toggle 1to0 dout [199] "logic dout[588:0]" +Toggle 0to1 dout [200] "logic dout[588:0]" +Toggle 1to0 dout [200] "logic dout[588:0]" +Toggle 0to1 dout [201] "logic dout[588:0]" +Toggle 1to0 dout [201] "logic dout[588:0]" +Toggle 0to1 dout [202] "logic dout[588:0]" +Toggle 1to0 dout [202] "logic dout[588:0]" +Toggle 0to1 dout [203] "logic dout[588:0]" +Toggle 1to0 dout [203] "logic dout[588:0]" +Toggle 0to1 dout [204] "logic dout[588:0]" +Toggle 1to0 dout [204] "logic dout[588:0]" +Toggle 0to1 dout [205] "logic dout[588:0]" +Toggle 1to0 dout [205] "logic dout[588:0]" +Toggle 0to1 dout [206] "logic dout[588:0]" +Toggle 1to0 dout [206] "logic dout[588:0]" +Toggle 0to1 dout [207] "logic dout[588:0]" +Toggle 1to0 dout [207] "logic dout[588:0]" +Toggle 0to1 dout [208] "logic dout[588:0]" +Toggle 1to0 dout [208] "logic dout[588:0]" +Toggle 0to1 dout [209] "logic dout[588:0]" +Toggle 1to0 dout [209] "logic dout[588:0]" +Toggle 0to1 dout [210] "logic dout[588:0]" +Toggle 1to0 dout [210] "logic dout[588:0]" +Toggle 0to1 dout [211] "logic dout[588:0]" +Toggle 1to0 dout [211] "logic dout[588:0]" +Toggle 0to1 dout [212] "logic dout[588:0]" +Toggle 1to0 dout [212] "logic dout[588:0]" +Toggle 0to1 dout [213] "logic dout[588:0]" +Toggle 1to0 dout [213] "logic dout[588:0]" +Toggle 0to1 dout [214] "logic dout[588:0]" +Toggle 1to0 dout [214] "logic dout[588:0]" +Toggle 0to1 dout [215] "logic dout[588:0]" +Toggle 1to0 dout [215] "logic dout[588:0]" +Toggle 0to1 dout [216] "logic dout[588:0]" +Toggle 1to0 dout [216] "logic dout[588:0]" +Toggle 0to1 dout [217] "logic dout[588:0]" +Toggle 1to0 dout [217] "logic dout[588:0]" +Toggle 0to1 dout [218] "logic dout[588:0]" +Toggle 1to0 dout [218] "logic dout[588:0]" +Toggle 0to1 dout [219] "logic dout[588:0]" +Toggle 1to0 dout [219] "logic dout[588:0]" +Toggle 0to1 dout [220] "logic dout[588:0]" +Toggle 1to0 dout [220] "logic dout[588:0]" +Toggle 0to1 dout [221] "logic dout[588:0]" +Toggle 1to0 dout [221] "logic dout[588:0]" +Toggle 0to1 dout [222] "logic dout[588:0]" +Toggle 1to0 dout [222] "logic dout[588:0]" +Toggle 0to1 dout [223] "logic dout[588:0]" +Toggle 1to0 dout [223] "logic dout[588:0]" +Toggle 0to1 dout [224] "logic dout[588:0]" +Toggle 1to0 dout [224] "logic dout[588:0]" +Toggle 0to1 dout [225] "logic dout[588:0]" +Toggle 1to0 dout [225] "logic dout[588:0]" +Toggle 0to1 dout [226] "logic dout[588:0]" +Toggle 1to0 dout [226] "logic dout[588:0]" +Toggle 0to1 dout [227] "logic dout[588:0]" +Toggle 1to0 dout [227] "logic dout[588:0]" +Toggle 0to1 dout [228] "logic dout[588:0]" +Toggle 1to0 dout [228] "logic dout[588:0]" +Toggle 0to1 dout [229] "logic dout[588:0]" +Toggle 1to0 dout [229] "logic dout[588:0]" +Toggle 0to1 dout [230] "logic dout[588:0]" +Toggle 1to0 dout [230] "logic dout[588:0]" +Toggle 0to1 dout [231] "logic dout[588:0]" +Toggle 1to0 dout [231] "logic dout[588:0]" +Toggle 0to1 dout [232] "logic dout[588:0]" +Toggle 1to0 dout [232] "logic dout[588:0]" +Toggle 0to1 dout [233] "logic dout[588:0]" +Toggle 1to0 dout [233] "logic dout[588:0]" +Toggle 0to1 dout [234] "logic dout[588:0]" +Toggle 1to0 dout [234] "logic dout[588:0]" +Toggle 0to1 dout [235] "logic dout[588:0]" +Toggle 1to0 dout [235] "logic dout[588:0]" +Toggle 0to1 dout [236] "logic dout[588:0]" +Toggle 1to0 dout [236] "logic dout[588:0]" +Toggle 0to1 dout [237] "logic dout[588:0]" +Toggle 1to0 dout [237] "logic dout[588:0]" +Toggle 0to1 dout [238] "logic dout[588:0]" +Toggle 1to0 dout [238] "logic dout[588:0]" +Toggle 0to1 dout [239] "logic dout[588:0]" +Toggle 1to0 dout [239] "logic dout[588:0]" +Toggle 0to1 dout [240] "logic dout[588:0]" +Toggle 1to0 dout [240] "logic dout[588:0]" +Toggle 0to1 dout [241] "logic dout[588:0]" +Toggle 1to0 dout [241] "logic dout[588:0]" +Toggle 0to1 dout [242] "logic dout[588:0]" +Toggle 1to0 dout [242] "logic dout[588:0]" +Toggle 0to1 dout [243] "logic dout[588:0]" +Toggle 1to0 dout [243] "logic dout[588:0]" +Toggle 0to1 dout [244] "logic dout[588:0]" +Toggle 1to0 dout [244] "logic dout[588:0]" +Toggle 0to1 dout [245] "logic dout[588:0]" +Toggle 1to0 dout [245] "logic dout[588:0]" +Toggle 0to1 dout [246] "logic dout[588:0]" +Toggle 1to0 dout [246] "logic dout[588:0]" +Toggle 0to1 dout [247] "logic dout[588:0]" +Toggle 1to0 dout [247] "logic dout[588:0]" +Toggle 0to1 dout [248] "logic dout[588:0]" +Toggle 1to0 dout [248] "logic dout[588:0]" +Toggle 0to1 dout [249] "logic dout[588:0]" +Toggle 1to0 dout [249] "logic dout[588:0]" +Toggle 0to1 dout [250] "logic dout[588:0]" +Toggle 1to0 dout [250] "logic dout[588:0]" +Toggle 0to1 dout [251] "logic dout[588:0]" +Toggle 1to0 dout [251] "logic dout[588:0]" +Toggle 0to1 dout [252] "logic dout[588:0]" +Toggle 1to0 dout [252] "logic dout[588:0]" +Toggle 0to1 dout [253] "logic dout[588:0]" +Toggle 1to0 dout [253] "logic dout[588:0]" +Toggle 0to1 dout [254] "logic dout[588:0]" +Toggle 1to0 dout [254] "logic dout[588:0]" +Toggle 0to1 dout [255] "logic dout[588:0]" +Toggle 1to0 dout [255] "logic dout[588:0]" +Toggle 0to1 dout [372] "logic dout[588:0]" +Toggle 1to0 dout [372] "logic dout[588:0]" +Toggle 0to1 dout [373] "logic dout[588:0]" +Toggle 1to0 dout [373] "logic dout[588:0]" +Toggle 0to1 dout [374] "logic dout[588:0]" +Toggle 1to0 dout [374] "logic dout[588:0]" +Toggle 0to1 dout [95] "logic dout[588:0]" +Toggle 1to0 dout [95] "logic dout[588:0]" +Toggle 0to1 dout [77] "logic dout[588:0]" +Toggle 1to0 dout [77] "logic dout[588:0]" +Toggle 0to1 dout [78] "logic dout[588:0]" +Toggle 1to0 dout [78] "logic dout[588:0]" +Toggle 0to1 dout [79] "logic dout[588:0]" +Toggle 1to0 dout [79] "logic dout[588:0]" +Toggle 0to1 dout [80] "logic dout[588:0]" +Toggle 1to0 dout [80] "logic dout[588:0]" +Toggle 0to1 dout [81] "logic dout[588:0]" +Toggle 1to0 dout [81] "logic dout[588:0]" +Toggle 0to1 dout [82] "logic dout[588:0]" +Toggle 1to0 dout [82] "logic dout[588:0]" +Toggle 0to1 dout [83] "logic dout[588:0]" +Toggle 1to0 dout [83] "logic dout[588:0]" +Toggle 0to1 dout [84] "logic dout[588:0]" +Toggle 1to0 dout [84] "logic dout[588:0]" +Toggle 0to1 dout [85] "logic dout[588:0]" +Toggle 1to0 dout [85] "logic dout[588:0]" +Toggle 0to1 dout [86] "logic dout[588:0]" +Toggle 1to0 dout [86] "logic dout[588:0]" +Toggle 0to1 dout [87] "logic dout[588:0]" +Toggle 1to0 dout [87] "logic dout[588:0]" +Toggle 0to1 dout [88] "logic dout[588:0]" +Toggle 1to0 dout [88] "logic dout[588:0]" +Toggle 0to1 dout [89] "logic dout[588:0]" +Toggle 1to0 dout [89] "logic dout[588:0]" +Toggle 0to1 dout [90] "logic dout[588:0]" +Toggle 1to0 dout [90] "logic dout[588:0]" +Toggle 0to1 dout [91] "logic dout[588:0]" +Toggle 1to0 dout [91] "logic dout[588:0]" +Toggle 0to1 dout [92] "logic dout[588:0]" +Toggle 1to0 dout [92] "logic dout[588:0]" +Toggle 0to1 dout [93] "logic dout[588:0]" +Toggle 1to0 dout [93] "logic dout[588:0]" +Toggle 0to1 dout [94] "logic dout[588:0]" +Toggle 1to0 dout [94] "logic dout[588:0]" +Toggle 0to1 dout [75] "logic dout[588:0]" +Toggle 1to0 dout [75] "logic dout[588:0]" +Toggle 0to1 dout [71] "logic dout[588:0]" +Toggle 1to0 dout [71] "logic dout[588:0]" +Toggle 0to1 dout [72] "logic dout[588:0]" +Toggle 1to0 dout [72] "logic dout[588:0]" +Toggle 0to1 dout [73] "logic dout[588:0]" +Toggle 1to0 dout [73] "logic dout[588:0]" +Toggle 0to1 dout [74] "logic dout[588:0]" +Toggle 1to0 dout [74] "logic dout[588:0]" +Toggle 0to1 dout [65] "logic dout[588:0]" +Toggle 1to0 dout [65] "logic dout[588:0]" +Toggle 0to1 dout [2] "logic dout[588:0]" +Toggle 1to0 dout [2] "logic dout[588:0]" +Toggle 0to1 dout [3] "logic dout[588:0]" +Toggle 1to0 dout [3] "logic dout[588:0]" +Toggle 0to1 dout [4] "logic dout[588:0]" +Toggle 1to0 dout [4] "logic dout[588:0]" +Toggle 0to1 dout [5] "logic dout[588:0]" +Toggle 1to0 dout [5] "logic dout[588:0]" +Toggle 0to1 dout [6] "logic dout[588:0]" +Toggle 1to0 dout [6] "logic dout[588:0]" +Toggle 0to1 dout [7] "logic dout[588:0]" +Toggle 1to0 dout [7] "logic dout[588:0]" +Toggle 0to1 dout [8] "logic dout[588:0]" +Toggle 1to0 dout [8] "logic dout[588:0]" +Toggle 0to1 dout [9] "logic dout[588:0]" +Toggle 1to0 dout [9] "logic dout[588:0]" +Toggle 0to1 dout [10] "logic dout[588:0]" +Toggle 1to0 dout [10] "logic dout[588:0]" +Toggle 0to1 dout [11] "logic dout[588:0]" +Toggle 1to0 dout [11] "logic dout[588:0]" +Toggle 0to1 dout [12] "logic dout[588:0]" +Toggle 1to0 dout [12] "logic dout[588:0]" +Toggle 0to1 dout [13] "logic dout[588:0]" +Toggle 1to0 dout [13] "logic dout[588:0]" +Toggle 0to1 dout [14] "logic dout[588:0]" +Toggle 1to0 dout [14] "logic dout[588:0]" +Toggle 0to1 dout [15] "logic dout[588:0]" +Toggle 1to0 dout [15] "logic dout[588:0]" +Toggle 0to1 dout [16] "logic dout[588:0]" +Toggle 1to0 dout [16] "logic dout[588:0]" +Toggle 0to1 dout [17] "logic dout[588:0]" +Toggle 1to0 dout [17] "logic dout[588:0]" +Toggle 0to1 dout [18] "logic dout[588:0]" +Toggle 1to0 dout [18] "logic dout[588:0]" +Toggle 0to1 dout [19] "logic dout[588:0]" +Toggle 1to0 dout [19] "logic dout[588:0]" +Toggle 0to1 dout [20] "logic dout[588:0]" +Toggle 1to0 dout [20] "logic dout[588:0]" +Toggle 0to1 dout [21] "logic dout[588:0]" +Toggle 1to0 dout [21] "logic dout[588:0]" +Toggle 0to1 dout [22] "logic dout[588:0]" +Toggle 1to0 dout [22] "logic dout[588:0]" +Toggle 0to1 dout [23] "logic dout[588:0]" +Toggle 1to0 dout [23] "logic dout[588:0]" +Toggle 0to1 dout [24] "logic dout[588:0]" +Toggle 1to0 dout [24] "logic dout[588:0]" +Toggle 0to1 dout [25] "logic dout[588:0]" +Toggle 1to0 dout [25] "logic dout[588:0]" +Toggle 0to1 dout [26] "logic dout[588:0]" +Toggle 1to0 dout [26] "logic dout[588:0]" +Toggle 0to1 dout [27] "logic dout[588:0]" +Toggle 1to0 dout [27] "logic dout[588:0]" +Toggle 0to1 dout [28] "logic dout[588:0]" +Toggle 1to0 dout [28] "logic dout[588:0]" +Toggle 0to1 dout [29] "logic dout[588:0]" +Toggle 1to0 dout [29] "logic dout[588:0]" +Toggle 0to1 dout [31] "logic dout[588:0]" +Toggle 1to0 dout [31] "logic dout[588:0]" +Toggle 0to1 dout [32] "logic dout[588:0]" +Toggle 1to0 dout [32] "logic dout[588:0]" +Toggle 0to1 dout [33] "logic dout[588:0]" +Toggle 1to0 dout [33] "logic dout[588:0]" +Toggle 0to1 dout [34] "logic dout[588:0]" +Toggle 1to0 dout [34] "logic dout[588:0]" +Toggle 0to1 dout [35] "logic dout[588:0]" +Toggle 1to0 dout [35] "logic dout[588:0]" +Toggle 0to1 dout [48] "logic dout[588:0]" +Toggle 1to0 dout [48] "logic dout[588:0]" +Toggle 0to1 dout [49] "logic dout[588:0]" +Toggle 1to0 dout [49] "logic dout[588:0]" +Toggle 0to1 dout [50] "logic dout[588:0]" +Toggle 1to0 dout [50] "logic dout[588:0]" +Toggle 0to1 dout [51] "logic dout[588:0]" +Toggle 1to0 dout [51] "logic dout[588:0]" +Toggle 0to1 dout [52] "logic dout[588:0]" +Toggle 1to0 dout [52] "logic dout[588:0]" +Toggle 0to1 dout [53] "logic dout[588:0]" +Toggle 1to0 dout [53] "logic dout[588:0]" +Toggle 0to1 dout [54] "logic dout[588:0]" +Toggle 1to0 dout [54] "logic dout[588:0]" +Toggle 0to1 dout [55] "logic dout[588:0]" +Toggle 1to0 dout [55] "logic dout[588:0]" +Toggle 0to1 dout [56] "logic dout[588:0]" +Toggle 1to0 dout [56] "logic dout[588:0]" +Toggle 0to1 dout [57] "logic dout[588:0]" +Toggle 1to0 dout [57] "logic dout[588:0]" +Toggle 0to1 dout [58] "logic dout[588:0]" +Toggle 1to0 dout [58] "logic dout[588:0]" +Toggle 0to1 dout [59] "logic dout[588:0]" +Toggle 1to0 dout [59] "logic dout[588:0]" +Toggle 0to1 dout [60] "logic dout[588:0]" +Toggle 1to0 dout [60] "logic dout[588:0]" +Toggle 0to1 dout [61] "logic dout[588:0]" +Toggle 1to0 dout [61] "logic dout[588:0]" +Toggle 0to1 dout [62] "logic dout[588:0]" +Toggle 1to0 dout [62] "logic dout[588:0]" +Toggle 0to1 dout [63] "logic dout[588:0]" +Toggle 1to0 dout [63] "logic dout[588:0]" +Toggle 0to1 dout [64] "logic dout[588:0]" +Toggle 1to0 dout [64] "logic dout[588:0]" +CHECKSUM: "3190985420 1606079823" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_b.switch.M_mux[0].out_q.fifo_ram +Toggle 0to1 perr "logic perr" +Toggle 1to0 perr "logic perr" +Toggle perr_in "logic perr_in[18:0]" +Toggle 0to1 perr_or "logic perr_or" +Toggle 1to0 perr_or "logic perr_or" +CHECKSUM: "3190985420 1606079823" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[0].out_q.fifo_ram +Toggle 0to1 perr "logic perr" +Toggle 1to0 perr "logic perr" +Toggle perr_in "logic perr_in[18:0]" +Toggle 0to1 perr_or "logic perr_or" +Toggle 1to0 perr_or "logic perr_or" +CHECKSUM: "3190985420 1606079823" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[1].out_q.fifo_ram +Toggle 0to1 perr "logic perr" +Toggle 1to0 perr "logic perr" +Toggle perr_in "logic perr_in[18:0]" +Toggle 0to1 perr_or "logic perr_or" +Toggle 1to0 perr_or "logic perr_or" +CHECKSUM: "3190985420 1606079823" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[2].out_q.fifo_ram +Toggle 0to1 perr "logic perr" +Toggle 1to0 perr "logic perr" +Toggle perr_in "logic perr_in[18:0]" +Toggle 0to1 perr_or "logic perr_or" +Toggle 1to0 perr_or "logic perr_or" +CHECKSUM: "3190985420 1606079823" +INSTANCE: tb_top.DUT.afu_top.pf_vf_mux_b.switch.N_mux[3].out_q.fifo_ram +Toggle 0to1 perr "logic perr" +Toggle 1to0 perr "logic perr" +Toggle perr_in "logic perr_in[18:0]" +Toggle 0to1 perr_or "logic perr_or" +Toggle 1to0 perr_or "logic perr_or" diff --git a/verification/coverage/exclusion_file_list.f b/verification/coverage/exclusion_file_list.f new file mode 100644 index 0000000..2bcc0e3 --- /dev/null +++ b/verification/coverage/exclusion_file_list.f @@ -0,0 +1,20 @@ +d5005_afu_protocol.el +d5005_coverage_exclusions.el +d5005_fme_exclusions.el +d5005_he_hssi_exclusions.el +d5005_he_lpbk_exclusions.el +d5005_he_mem_exclusions.el +d5005_interface_inside_afu_exclusions.el +d5005_interface_outside_afu_exclusions.el +d5005_port_gasket_exclusions.el +d5005_quartus_exclusions.el +d5005_Tag_remap_exclusions.el +d5005_ral_exclusions.el +d5005_msix_exclusions.el +d5005_b_port_exclusions.el +d5005_a_port_exclusions.el +d5005_axis_axil_bridge.el +d5005_local_commit.el +d5005_emif_top.el +d5005_mx2ho_ab_mux.el +d5005_mx2ho_ho2mx_port_remap.el diff --git a/verification/coverage/exclusion_files.tar.gz b/verification/coverage/exclusion_files.tar.gz new file mode 100644 index 0000000..14730e1 Binary files /dev/null and b/verification/coverage/exclusion_files.tar.gz differ diff --git a/verification/coverage/fme_exclusions.el b/verification/coverage/fme_exclusions.el new file mode 100644 index 0000000..75662d2 --- /dev/null +++ b/verification/coverage/fme_exclusions.el @@ -0,0 +1,11218 @@ +//================================================== +// This file contains the Excluded objects +// Generated By User: ppawar2x +// Format Version: 2 +// Date: Wed May 11 22:01:12 2022 +// ExclMode: default +//================================================== +CHECKSUM: "931957376" +ANNOTATION: " Excluding rom/ram related blocks " +INSTANCE:tb_top.DUT.fme_top.fme_csr.fme_id_rom +CHECKSUM: "3713271326" +INSTANCE:tb_top.DUT.fme_top.fme_csr.fme_id_rom.rom_1port_0 +CHECKSUM: "3190985420" +ANNOTATION: " Excluding rom/ram related blocks " +INSTANCE:tb_top.DUT.fme_top.pfa_master.pfam_fifo.fifo_ram +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.fme_top.fme_csr.fme_id_rom.rom_1port_0.altera_syncram_component +CHECKSUM: "3589944323" +ANNOTATION: " Excluding rom/ram related blocks " +INSTANCE:tb_top.DUT.fme_top.pfa_master.pfam_fifo.fifo_ram.genblk2.inst_gram_sdp +CHECKSUM: "4144234428" +ANNOTATION: " Excluding rom/ram related blocks " +INSTANCE:tb_top.DUT.fme_top.pfa_master.pfam_fifo +CHECKSUM: "1458656250" +ANNOTATION: " Excluding as not using adapters " +INSTANCE:tb_top.DUT.fme_top.pfa_master +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.fme_top.fme_csr.fme_id_rom.rom_1port_0.altera_syncram_component.mem +CHECKSUM: "1374955797" +INSTANCE:tb_top.DUT.fme_top.pgn +CHECKSUM: "3073531733 1397263620" +INSTANCE: tb_top.DUT.fme_top.fme_csr +ANNOTATION: " ferr, nerr and err hit related signas not implmented in AC, they belong EA. " +Fsm err_hit_masked "256086001" +Fsm wr_state "3362174536" +State WR_GOT_DATA "8" +Fsm wr_state "3362174536" +State WR_RESET "1" +Fsm wr_state "3362174536" +State WR_GOT_ADDR "4" +Fsm rd_state "33073610" +State RD_RESET "1" +Fsm rom_state "1565177879" +State ROM_RESET "1" +CHECKSUM: "3073531733 1419975756" +INSTANCE: tb_top.DUT.fme_top.fme_csr +ANNOTATION: " Only port0 is being implemented. " +Branch 1 "3477445129" "(fme_csr_fab_capability.fab_capability.num_ports > 3'b1)" (0) "(fme_csr_fab_capability.fab_capability.num_ports > 3'b1) 1" +ANNOTATION: " Only port0 is being implemented. " +Branch 2 "1273991637" "(fme_csr_fab_capability.fab_capability.num_ports > 3'h2)" (0) "(fme_csr_fab_capability.fab_capability.num_ports > 3'h2) 1" +ANNOTATION: " Only port0 is being implemented. " +Branch 3 "2242732780" "(fme_csr_fab_capability.fab_capability.num_ports > 3'h3)" (0) "(fme_csr_fab_capability.fab_capability.num_ports > 3'h3) 1" +ANNOTATION: " Only port0 is being implemented. " +Branch 0 "17262896" "(fme_csr_fab_capability.fab_capability.num_ports > 3'b0)" (1) "(fme_csr_fab_capability.fab_capability.num_ports > 3'b0) 0" +ANNOTATION: " this set of conditions will not occur for the FSM " +Branch 9 "131981837" "1'b1" (4) "1'b1 wr_state[WR_READY_BIT] ,-,0,0,1,-,-,-,-" +ANNOTATION: " this set of conditions will not occur for the FSM " +Branch 9 "131981837" "1'b1" (6) "1'b1 wr_state[WR_GOT_ADDR_BIT] ,-,-,-,-,1,-,-,-" +ANNOTATION: " this set of conditions will not occur for the FSM " +Branch 9 "131981837" "1'b1" (7) "1'b1 wr_state[WR_GOT_ADDR_BIT] ,-,-,-,-,0,1,-,-" +ANNOTATION: " this set of conditions will not occur for the FSM " +Branch 9 "131981837" "1'b1" (8) "1'b1 wr_state[WR_GOT_ADDR_BIT] ,-,-,-,-,0,0,1,-" +ANNOTATION: " this set of conditions will not occur for the FSM " +Branch 9 "131981837" "1'b1" (9) "1'b1 wr_state[WR_GOT_ADDR_BIT] ,-,-,-,-,0,0,0,-" +ANNOTATION: " this set of conditions will not occur for the FSM " +Branch 9 "131981837" "1'b1" (10) "1'b1 wr_state[WR_GOT_DATA_BIT] ,-,-,-,-,-,-,-,-" +ANNOTATION: " this set of conditions will not occur for the FSM " +Branch 9 "131981837" "1'b1" (3) "1'b1 wr_state[WR_READY_BIT] ,-,0,1,-,-,-,-,-" +ANNOTATION: " ferr, nerr and err hit related signas not implmented in AC, they belong EA. " +Branch 20 "763393676" "(!pwr_good_n)" (7) "(!pwr_good_n) 0,0,-,1,3'b100 " +ANNOTATION: " ferr, nerr and err hit related signas not implmented in AC, they belong EA. " +Branch 20 "763393676" "(!pwr_good_n)" (6) "(!pwr_good_n) 0,0,-,1,3'bz10 " +ANNOTATION: " ferr, nerr and err hit related signas not implmented in AC, they belong EA. " +Branch 20 "763393676" "(!pwr_good_n)" (5) "(!pwr_good_n) 0,0,-,1,3'bzz1 " +ANNOTATION: " ferr, nerr and err hit related signas not implmented in AC, they belong EA. " +Branch 20 "763393676" "(!pwr_good_n)" (3) "(!pwr_good_n) 0,1,3'b100 ,-,-" +ANNOTATION: " ferr, nerr and err hit related signas not implmented in AC, they belong EA. " +Branch 20 "763393676" "(!pwr_good_n)" (9) "(!pwr_good_n) 0,0,-,0,-" +ANNOTATION: " ferr, nerr and err hit related signas not implmented in AC, they belong EA. " +Branch 19 "2647876750" "nerr_id" (1) "nerr_id 2'h1 " +ANNOTATION: " ferr, nerr and err hit related signas not implmented in AC, they belong EA. " +Branch 19 "2647876750" "nerr_id" (2) "nerr_id default" +ANNOTATION: " ferr, nerr and err hit related signas not implmented in AC, they belong EA. " +Branch 18 "4229135570" "ferr_id" (2) "ferr_id default" +Branch 6 "623951649" "(axi.awvalid && axi.wvalid)" (2) "(axi.awvalid && axi.wvalid) 0,-,1,1" +Branch 6 "623951649" "(axi.awvalid && axi.wvalid)" (3) "(axi.awvalid && axi.wvalid) 0,-,1,0" +Branch 7 "3236559379" "(((axi.awvalid && axi.wvalid) && wr_range_valid) && awsize_valid)" (7) "(((axi.awvalid && axi.wvalid) && wr_range_valid) && awsize_valid) 0,-,-,-,1,0,0,0" +Branch 7 "3236559379" "(((axi.awvalid && axi.wvalid) && wr_range_valid) && awsize_valid)" (4) "(((axi.awvalid && axi.wvalid) && wr_range_valid) && awsize_valid) 0,-,-,-,1,1,-,-" +Branch 7 "3236559379" "(((axi.awvalid && axi.wvalid) && wr_range_valid) && awsize_valid)" (5) "(((axi.awvalid && axi.wvalid) && wr_range_valid) && awsize_valid) 0,-,-,-,1,0,1,-" +Branch 7 "3236559379" "(((axi.awvalid && axi.wvalid) && wr_range_valid) && awsize_valid)" (6) "(((axi.awvalid && axi.wvalid) && wr_range_valid) && awsize_valid) 0,-,-,-,1,0,0,1" +Branch 18 "4229135570" "ferr_id" (1) "ferr_id 2'h1 " +Branch 20 "763393676" "(!pwr_good_n)" (1) "(!pwr_good_n) 0,1,3'bzz1 ,-,-" +Branch 20 "763393676" "(!pwr_good_n)" (8) "(!pwr_good_n) 0,0,-,1,default" +Branch 20 "763393676" "(!pwr_good_n)" (4) "(!pwr_good_n) 0,1,default,-,-" +Branch 20 "763393676" "(!pwr_good_n)" (2) "(!pwr_good_n) 0,1,3'bz10 ,-,-" +Branch 23 "2481611770" "((axi.arvalid && rd_range_valid) && arsize_valid)" (0) "((axi.arvalid && rd_range_valid) && arsize_valid) 1,1,-,-" +Branch 23 "2481611770" "((axi.arvalid && rd_range_valid) && arsize_valid)" (3) "((axi.arvalid && rd_range_valid) && arsize_valid) 1,0,0,0" +Branch 23 "2481611770" "((axi.arvalid && rd_range_valid) && arsize_valid)" (1) "((axi.arvalid && rd_range_valid) && arsize_valid) 1,0,1,-" +Branch 28 "1068382291" "(read_type_reg == FULL64)" (2) "(read_type_reg == FULL64) 0,0,1" +CHECKSUM: "3073531733 1434000337" +INSTANCE: tb_top.DUT.fme_top.fme_csr +ANNOTATION: " this set of conditions will not occur since for the FSM " +Condition 29 "769530563" "(((!axi.awvalid)) && ((!axi.wvalid))) 1 -1" +ANNOTATION: " this set of conditions will not occur since for the FSM " +Condition 30 "2846140935" "(((!axi.awvalid)) && axi.wvalid) 1 -1" +ANNOTATION: " this set of conditions will not occur since for the FSM " +Condition 31 "2788461521" "(axi.awvalid && ((!axi.wvalid))) 1 -1" +Condition 27 "559815669" "(((!axi.awvalid)) && axi.wvalid) 1 -1" (3 "11") +Condition 27 "559815669" "(((!axi.awvalid)) && axi.wvalid) 1 -1" (2 "10") +Condition 28 "137497449" "(axi.awvalid && ((!axi.wvalid))) 1 -1" (1 "01") +Condition 28 "137497449" "(axi.awvalid && ((!axi.wvalid))) 1 -1" (3 "11") +Condition 26 "3252818723" "(((!axi.awvalid)) && ((!axi.wvalid))) 1 -1" (1 "01") +Condition 26 "3252818723" "(((!axi.awvalid)) && ((!axi.wvalid))) 1 -1" (2 "10") +ANNOTATION: " Only port0 is being implemented. " +Condition 50 "4263267136" "((fme_csr_fab_capability.fab_capability.num_ports > 3'b1) ? 1'b1 : 1'b0) 1 -1" (2 "1") +ANNOTATION: " Only port0 is being implemented. " +Condition 51 "3996232626" "((fme_csr_fab_capability.fab_capability.num_ports > 3'h2) ? 1'b1 : 1'b0) 1 -1" (2 "1") +ANNOTATION: " Only port0 is being implemented. " +Condition 52 "1261870054" "((fme_csr_fab_capability.fab_capability.num_ports > 3'h3) ? 1'b1 : 1'b0) 1 -1" (2 "1") +ANNOTATION: " Only port0 is being implemented. " +Condition 49 "1528527636" "((fme_csr_fab_capability.fab_capability.num_ports > 3'b0) ? 1'b1 : 1'b0) 1 -1" (1 "0") +ANNOTATION: " this set of conditions will not occur for the FSM " +Condition 33 "3045328798" "(wr_next[WR_GOT_ADDR_BIT] || wr_next[WR_GOT_ADDR_AND_DATA_BIT]) 1 -1" (3 "10") +ANNOTATION: " this set of conditions will not occur for the FSM " +Condition 35 "654280827" "(wr_next[WR_READY_BIT] || wr_next[WR_GOT_ADDR_BIT]) 1 -1" (2 "01") +ANNOTATION: " this set of conditions will not occur for the FSM " +Condition 34 "3514420521" "(wr_next[WR_READY_BIT] || wr_next[WR_GOT_ADDR_BIT]) 1 -1" (2 "01") +ANNOTATION: " this set of conditions will not occur for the FSM " +Condition 32 "3147283386" "(wr_next[WR_GOT_DATA_BIT] || wr_next[WR_GOT_ADDR_AND_DATA_BIT]) 1 -1" (3 "10") +Condition 6 "1347767062" "(axi.awvalid && axi.wvalid) 1 -1" (2 "10") +Condition 6 "1347767062" "(axi.awvalid && axi.wvalid) 1 -1" (1 "01") +Condition 42 "3223146929" "(axi.arvalid && rd_range_valid && arsize_valid) 1 -1" (3 "110") +Condition 5 "3871529543" "((axi.awsize == 3'b011) || (axi.awsize == 3'b010)) 1 -1" (1 "00") +Condition 21 "3045819912" "((axi.awsize == 3'b011) && (axi.wstrb == 8'hff)) 1 -1" (1 "01") +Condition 21 "3045819912" "((axi.awsize == 3'b011) && (axi.wstrb == 8'hff)) 1 -1" (2 "10") +Condition 19 "2143669316" "((axi.awsize == 3'b010) && (axi.wstrb == 8'hf0) && (axi.awaddr[2] == 1'b1)) 1 -1" (1 "011") +Condition 19 "2143669316" "((axi.awsize == 3'b010) && (axi.wstrb == 8'hf0) && (axi.awaddr[2] == 1'b1)) 1 -1" (3 "110") +Condition 19 "2143669316" "((axi.awsize == 3'b010) && (axi.wstrb == 8'hf0) && (axi.awaddr[2] == 1'b1)) 1 -1" (2 "101") +Condition 20 "42602140" "((axi.awsize == 3'b010) && (axi.wstrb == 8'h0f) && (axi.awaddr[2] == 1'b0)) 1 -1" (3 "110") +Condition 20 "42602140" "((axi.awsize == 3'b010) && (axi.wstrb == 8'h0f) && (axi.awaddr[2] == 1'b0)) 1 -1" (1 "011") +Condition 43 "1916812524" "((axi.arsize == 3'b010) && (axi.araddr[2] == 1'b1)) 1 -1" +Condition 41 "1951575454" "((axi.arsize == 3'b011) || (axi.arsize == 3'b010)) 1 -1" (1 "00") +Condition 44 "4155741744" "((axi.arsize == 3'b010) && (axi.araddr[2] == 1'b0)) 1 -1" (2 "10") +Condition 44 "4155741744" "((axi.arsize == 3'b010) && (axi.araddr[2] == 1'b0)) 1 -1" (3 "11") +Condition 25 "2597141737" "((awsize_reg == 3'b011) && (axi.wstrb == 8'hff)) 1 -1" +Condition 23 "2009365633" "((awsize_reg == 3'b010) && (axi.wstrb == 8'hf0) && (awaddr_reg[2] == 1'b1)) 1 -1" +Condition 24 "1730059565" "((awsize_reg == 3'b010) && (axi.wstrb == 8'h0f) && (awaddr_reg[2] == 1'b0)) 1 -1" +Condition 9 "1106703935" "((axi.awsize == 3'b010) && (axi.wstrb == 8'h0f)) 1 -1" (1 "01") +Condition 11 "124302133" "((axi.awsize == 3'b011) && (axi.wstrb == 8'hff)) 1 -1" (1 "01") +Condition 11 "124302133" "((axi.awsize == 3'b011) && (axi.wstrb == 8'hff)) 1 -1" (2 "10") +Condition 10 "2074713568" "((axi.awsize == 3'b010) && (axi.wstrb == 8'hf0)) 1 -1" (1 "01") +Condition 13 "2687778198" "((((awsize_reg == 3'b010) && (axi.wstrb == 8'h0f)) || ((awsize_reg == 3'b010) && (axi.wstrb == 8'hf0)) || ((awsize_reg == 3'b011) && (axi.wstrb == 8'hff))) ? 1'b1 : 1'b0) 1 -1" (1 "0") +Condition 13 "2687778198" "((((awsize_reg == 3'b010) && (axi.wstrb == 8'h0f)) || ((awsize_reg == 3'b010) && (axi.wstrb == 8'hf0)) || ((awsize_reg == 3'b011) && (axi.wstrb == 8'hff))) ? 1'b1 : 1'b0) 1 -1" (2 "1") +Condition 12 "319717993" "(((!axi.awvalid)) && axi.wvalid) 1 -1" (1 "01") +Condition 12 "319717993" "(((!axi.awvalid)) && axi.wvalid) 1 -1" (3 "11") +Condition 22 "3460077996" "(((!axi.awvalid)) && axi.wvalid && wr_range_valid_reg && awsize_valid_reg) 1 -1" (1 "0111") +Condition 22 "3460077996" "(((!axi.awvalid)) && axi.wvalid && wr_range_valid_reg && awsize_valid_reg) 1 -1" (5 "1111") +Condition 22 "3460077996" "(((!axi.awvalid)) && axi.wvalid && wr_range_valid_reg && awsize_valid_reg) 1 -1" (4 "1110") +Condition 22 "3460077996" "(((!axi.awvalid)) && axi.wvalid && wr_range_valid_reg && awsize_valid_reg) 1 -1" (3 "1101") +Condition 18 "178255088" "(axi.awvalid && axi.wvalid && wr_range_valid && awsize_valid) 1 -1" (4 "1110") +Condition 18 "178255088" "(axi.awvalid && axi.wvalid && wr_range_valid && awsize_valid) 1 -1" (1 "0111") +Condition 18 "178255088" "(axi.awvalid && axi.wvalid && wr_range_valid && awsize_valid) 1 -1" (2 "1011") +Condition 13 "2687778198" "((((awsize_reg == 3'b010) && (axi.wstrb == 8'h0f)) || ((awsize_reg == 3'b010) && (axi.wstrb == 8'hf0)) || ((awsize_reg == 3'b011) && (axi.wstrb == 8'hff))) ? 1'b1 : 1'b0) 1 -1" +CHECKSUM: "3073531733 488068728" +INSTANCE: tb_top.DUT.fme_top.fme_csr +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.ras_catfat_error_mask.error_mask11 "logic fme_csr_ras_catfat_error_mask_update.ras_catfat_error_mask.error_mask11" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.ras_catfat_error_mask.error_mask11 "logic fme_csr_ras_catfat_error_mask_update.ras_catfat_error_mask.error_mask11" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [1] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [1] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [5] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [5] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [0] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [0] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.fme_error_mask0.error_mask0 "logic fme_csr_fme_error_mask0_update.fme_error_mask0.error_mask0" +Toggle 0to1 fme_csr_fme_error_mask0_update.fme_error_mask0.error_mask0 "logic fme_csr_fme_error_mask0_update.fme_error_mask0.error_mask0" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [1] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [1] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [5] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [5] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [0] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [0] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [1] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [1] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [5] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [5] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [0] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [0] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.fme_error_mask0.error_mask0 "logic fme_csr_fme_error_mask0_reset.fme_error_mask0.error_mask0" +Toggle 0to1 fme_csr_fme_error_mask0_reset.fme_error_mask0.error_mask0 "logic fme_csr_fme_error_mask0_reset.fme_error_mask0.error_mask0" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [1] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [1] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [5] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [5] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [0] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [0] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.ras_error_inj.catast_error "logic fme_csr_ras_error_inj_update.ras_error_inj.catast_error" +Toggle 0to1 fme_csr_ras_error_inj_update.ras_error_inj.catast_error "logic fme_csr_ras_error_inj_update.ras_error_inj.catast_error" +Toggle 1to0 fme_csr_ras_error_inj_update.ras_error_inj.fatal_error "logic fme_csr_ras_error_inj_update.ras_error_inj.fatal_error" +Toggle 0to1 fme_csr_ras_error_inj_update.ras_error_inj.fatal_error "logic fme_csr_ras_error_inj_update.ras_error_inj.fatal_error" +Toggle 1to0 fme_csr_ras_error_inj_update.ras_error_inj.nofatal_error "logic fme_csr_ras_error_inj_update.ras_error_inj.nofatal_error" +Toggle 0to1 fme_csr_ras_error_inj_update.ras_error_inj.nofatal_error "logic fme_csr_ras_error_inj_update.ras_error_inj.nofatal_error" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [1] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [1] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [2] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [2] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [0] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [0] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [1] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [1] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [2] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [2] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [0] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [0] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 hw_state.pwr_good_n "logic hw_state.pwr_good_n" +Toggle 0to1 hw_state.pwr_good_n "logic hw_state.pwr_good_n" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [7] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [7] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [8] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [8] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [9] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [9] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [11] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [11] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [6] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [6] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [7] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [7] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [8] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [8] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [9] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [9] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [11] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [11] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [6] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [6] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [7] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [7] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [8] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [8] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [9] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [9] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [11] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [11] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [6] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [6] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.ras_catfat_error_mask.error_mask11 "logic fme_csr_ras_catfat_error_mask_reset.ras_catfat_error_mask.error_mask11" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.ras_catfat_error_mask.error_mask11 "logic fme_csr_ras_catfat_error_mask_reset.ras_catfat_error_mask.error_mask11" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [7] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [7] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [8] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [8] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [9] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [9] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [11] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [11] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [6] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [6] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.ras_error_inj.catast_error "logic fme_csr_ras_error_inj_reset.ras_error_inj.catast_error" +Toggle 0to1 fme_csr_ras_error_inj_reset.ras_error_inj.catast_error "logic fme_csr_ras_error_inj_reset.ras_error_inj.catast_error" +Toggle 1to0 fme_csr_ras_error_inj_reset.ras_error_inj.fatal_error "logic fme_csr_ras_error_inj_reset.ras_error_inj.fatal_error" +Toggle 0to1 fme_csr_ras_error_inj_reset.ras_error_inj.fatal_error "logic fme_csr_ras_error_inj_reset.ras_error_inj.fatal_error" +Toggle 1to0 fme_csr_ras_error_inj_reset.ras_error_inj.nofatal_error "logic fme_csr_ras_error_inj_reset.ras_error_inj.nofatal_error" +Toggle 0to1 fme_csr_ras_error_inj_reset.ras_error_inj.nofatal_error "logic fme_csr_ras_error_inj_reset.ras_error_inj.nofatal_error" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [1] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [1] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [2] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [2] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [0] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [0] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle fme_error_mask0_attr.fme_error_mask0.error_mask0 "logic fme_error_mask0_attr.fme_error_mask0.error_mask0[3:0]" +Toggle 1to0 ras_bluerr_masked [9] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [9] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [9] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [9] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [9] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [9] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [9] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [9] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [9] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [9] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [7] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [7] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [6] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [6] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [9] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [9] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [1] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [1] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [5] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [5] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [1] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [1] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [5] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [5] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle ras_catfat_error_attr.ras_catfat_error.injected_fatal_error "logic ras_catfat_error_attr.ras_catfat_error.injected_fatal_error[3:0]" +Toggle ras_catfat_error_mask_attr.ras_catfat_error_mask.error_mask11 "logic ras_catfat_error_mask_attr.ras_catfat_error_mask.error_mask11[3:0]" +Toggle ras_error_inj_attr.ras_error_inj.catast_error "logic ras_error_inj_attr.ras_error_inj.catast_error[3:0]" +Toggle ras_error_inj_attr.ras_error_inj.fatal_error "logic ras_error_inj_attr.ras_error_inj.fatal_error[3:0]" +Toggle ras_error_inj_attr.ras_error_inj.nofatal_error "logic ras_error_inj_attr.ras_error_inj.nofatal_error[3:0]" +Toggle ras_nofat_error_attr.ras_nofat_error.injected_warning_error "logic ras_nofat_error_attr.ras_nofat_error.injected_warning_error[3:0]" +Toggle ras_catfat_error_attr.ras_catfat_error.injected_catast_error "logic ras_catfat_error_attr.ras_catfat_error.injected_catast_error[3:0]" +Toggle 1to0 pwr_good_n "logic pwr_good_n" +Toggle 0to1 pwr_good_n "logic pwr_good_n" +Toggle fme0_sclr_sync "logic fme0_sclr_sync[19:0]" +Toggle fme0_sclr_sync2 "logic fme0_sclr_sync2[19:0]" +Toggle ras_catfat_error_attr.ras_catfat_error.crc_catast_error "logic ras_catfat_error_attr.ras_catfat_error.crc_catast_error[3:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [6] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [6] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle fme_csr_ras_nofat_error_mask_update.ras_nofat_error_mask.error_mask2 "logic fme_csr_ras_nofat_error_mask_update.ras_nofat_error_mask.error_mask2[1:0]" +Toggle fme_csr_ras_nofat_error_mask_update.ras_nofat_error_mask.error_mask5 "logic fme_csr_ras_nofat_error_mask_update.ras_nofat_error_mask.error_mask5[1:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [3] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [3] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [5] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [5] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [6] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [6] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [2] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [2] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle fme_csr_ras_nofat_error_mask_reset.ras_nofat_error_mask.error_mask5 "logic fme_csr_ras_nofat_error_mask_reset.ras_nofat_error_mask.error_mask5[1:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [3] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [3] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [5] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [5] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [6] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [6] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [2] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [2] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle fme_csr_ras_nofat_error_mask_reset.ras_nofat_error_mask.error_mask2 "logic fme_csr_ras_nofat_error_mask_reset.ras_nofat_error_mask.error_mask2[1:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [3] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [3] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [5] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [5] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [6] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [6] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [2] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [2] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.ras_catfat_error.crc_catast_error "logic fme_csr_ras_catfat_error_update.ras_catfat_error.crc_catast_error" +Toggle 0to1 fme_csr_ras_catfat_error_update.ras_catfat_error.crc_catast_error "logic fme_csr_ras_catfat_error_update.ras_catfat_error.crc_catast_error" +Toggle 1to0 fme_csr_ras_catfat_error_reset.ras_catfat_error.crc_catast_error "logic fme_csr_ras_catfat_error_reset.ras_catfat_error.crc_catast_error" +Toggle 0to1 fme_csr_ras_catfat_error_reset.ras_catfat_error.crc_catast_error "logic fme_csr_ras_catfat_error_reset.ras_catfat_error.crc_catast_error" +Toggle fme_csr_ras_catfat_error_mask_update.ras_catfat_error_mask.error_mask6 "logic fme_csr_ras_catfat_error_mask_update.ras_catfat_error_mask.error_mask6[3:0]" +Toggle fme_csr_ras_catfat_error_mask_reset.ras_catfat_error_mask.error_mask6 "logic fme_csr_ras_catfat_error_mask_reset.ras_catfat_error_mask.error_mask6[3:0]" +Toggle 1to0 fme_csr_ras_catfat_error.ras_catfat_error.crc_catast_error "logic fme_csr_ras_catfat_error.ras_catfat_error.crc_catast_error" +Toggle 0to1 fme_csr_ras_catfat_error.ras_catfat_error.crc_catast_error "logic fme_csr_ras_catfat_error.ras_catfat_error.crc_catast_error" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [1] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [1] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [2] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [2] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [3] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [3] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [4] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [4] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [5] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [5] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [6] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [6] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [7] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [7] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [8] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [8] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [9] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [9] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [10] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [10] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [11] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [11] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [12] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [12] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [0] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [0] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [1] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [1] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [2] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [2] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [3] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [3] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [4] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [4] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [5] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [5] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [6] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [6] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [7] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [7] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [8] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [8] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [9] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [9] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [10] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [10] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [11] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [11] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [12] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [12] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [0] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [0] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle fme_csr_fme_error_mask0_update.fme_error_mask0.reserved1 "logic fme_csr_fme_error_mask0_update.fme_error_mask0.reserved1[62:0]" +Toggle fme_csr_fme_error_mask0_reset.fme_error_mask0.reserved1 "logic fme_csr_fme_error_mask0_reset.fme_error_mask0.reserved1[62:0]" +Toggle fme_csr_fme_error_mask0.fme_error_mask0.reserved1 "logic fme_csr_fme_error_mask0.fme_error_mask0.reserved1[62:0]" +Toggle fme_csr_fme_error0_reset.fme_error0.reserved1 "logic fme_csr_fme_error0_reset.fme_error0.reserved1[62:0]" +Toggle fme_csr_fme_error0_update.fme_error0.reserved1 "logic fme_csr_fme_error0_update.fme_error0.reserved1[62:0]" +Toggle fme_csr_fme_error0.fme_error0.reserved1 "logic fme_csr_fme_error0.fme_error0.reserved1[62:0]" +Toggle 1to0 nerr_lock "logic nerr_lock" +Toggle 0to1 nerr_lock "logic nerr_lock" +Toggle nerr_id "logic nerr_id[1:0]" +Toggle fme_ferr_comb "logic fme_ferr_comb[63:0]" +Toggle ferr_id "logic ferr_id[1:0]" +Toggle err_hit "logic err_hit[2:0]" +Toggle err_hit_mask "logic err_hit_mask[2:0]" +Toggle err_hit_masked "logic err_hit_masked[2:0]" +Toggle pcie0_sclr_sync "logic pcie0_sclr_sync[12:0]" +Toggle pcie0_sclr_sync2 "logic pcie0_sclr_sync2[12:0]" +Toggle 1to0 rd_reg_offset [7] "logic rd_reg_offset[8:0]" +Toggle 0to1 rd_reg_offset [7] "logic rd_reg_offset[8:0]" +Toggle 1to0 rd_reg_offset [6] "logic rd_reg_offset[8:0]" +Toggle 0to1 rd_reg_offset [6] "logic rd_reg_offset[8:0]" +Toggle 1to0 rd_reg_offset [8] "logic rd_reg_offset[8:0]" +Toggle 0to1 rd_reg_offset [8] "logic rd_reg_offset[8:0]" +Toggle fme_nerr_comb "logic fme_nerr_comb[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fpmon_fab_ctl_update.fpmon_fab_ctl.fabric_event_code "logic fme_csr_fpmon_fab_ctl_update.fpmon_fab_ctl.fabric_event_code[3:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.fpmon_fab_ctl.freeze_counters "logic fme_csr_fpmon_fab_ctl_update.fpmon_fab_ctl.freeze_counters" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.fpmon_fab_ctl.freeze_counters "logic fme_csr_fpmon_fab_ctl_update.fpmon_fab_ctl.freeze_counters" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.fpmon_fab_ctl.port_filter "logic fme_csr_fpmon_fab_ctl_update.fpmon_fab_ctl.port_filter" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.fpmon_fab_ctl.port_filter "logic fme_csr_fpmon_fab_ctl_update.fpmon_fab_ctl.port_filter" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fpmon_fab_ctl_update.fpmon_fab_ctl.port_id "logic fme_csr_fpmon_fab_ctl_update.fpmon_fab_ctl.port_id[1:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [16] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [16] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [17] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [17] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [18] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [18] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [19] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [19] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [20] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [20] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [21] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [21] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [23] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [23] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [8] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [8] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [17] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [17] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [18] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [18] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [19] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [19] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [20] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [20] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [21] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [21] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [23] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [23] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [16] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [16] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fpmon_fab_ctl_reset.fpmon_fab_ctl.fabric_event_code "logic fme_csr_fpmon_fab_ctl_reset.fpmon_fab_ctl.fabric_event_code[3:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.fpmon_fab_ctl.freeze_counters "logic fme_csr_fpmon_fab_ctl_reset.fpmon_fab_ctl.freeze_counters" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.fpmon_fab_ctl.freeze_counters "logic fme_csr_fpmon_fab_ctl_reset.fpmon_fab_ctl.freeze_counters" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.fpmon_fab_ctl.port_filter "logic fme_csr_fpmon_fab_ctl_reset.fpmon_fab_ctl.port_filter" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.fpmon_fab_ctl.port_filter "logic fme_csr_fpmon_fab_ctl_reset.fpmon_fab_ctl.port_filter" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fpmon_fab_ctl_reset.fpmon_fab_ctl.port_id "logic fme_csr_fpmon_fab_ctl_reset.fpmon_fab_ctl.port_id[1:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [16] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [16] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [17] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [17] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [18] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [18] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [19] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [19] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [20] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [20] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [21] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [21] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [23] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [23] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [8] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [8] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fpmon_fab_ctl_attr.fpmon_fab_ctl.freeze_counters "logic fpmon_fab_ctl_attr.fpmon_fab_ctl.freeze_counters[3:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [16] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [16] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [17] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [17] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [18] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [18] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [19] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [19] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [20] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [20] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [21] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [21] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [23] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [23] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [8] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [8] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fpmon_fab_ctl_attr.fpmon_fab_ctl.port_filter "logic fpmon_fab_ctl_attr.fpmon_fab_ctl.port_filter[3:0]" +ANNOTATION: " Excluding rom/ram related blocks " +Toggle 0to1 rom_next [0] "logic rom_next[5:0]" +Toggle 1to0 wr_state [2] "logic wr_state[6:0]" +Toggle 0to1 wr_state [2] "logic wr_state[6:0]" +Toggle 0to1 wr_state [0] "logic wr_state[6:0]" +Toggle 1to0 wr_state [3] "logic wr_state[6:0]" +Toggle 0to1 wr_state [3] "logic wr_state[6:0]" +Toggle 1to0 wr_next [2] "logic wr_next[6:0]" +Toggle 0to1 wr_next [2] "logic wr_next[6:0]" +Toggle 0to1 wr_next [0] "logic wr_next[6:0]" +Toggle 1to0 wr_next [3] "logic wr_next[6:0]" +Toggle 0to1 wr_next [3] "logic wr_next[6:0]" +Toggle 0to1 rom_state [0] "logic rom_state[5:0]" +Toggle 1to0 rd_next [0] "logic rd_next[4:0]" +Toggle 1to0 rd_state [0] "logic rd_state[4:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [30] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [30] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [29] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [29] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [28] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [28] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [27] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [27] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [26] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [26] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [25] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [25] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [24] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [24] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [23] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [23] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [22] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [22] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [21] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [21] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [20] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [20] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [19] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [19] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [18] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [18] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [17] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [17] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [16] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [16] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [15] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [15] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [14] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [14] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [13] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [13] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [12] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [12] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [11] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [11] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [10] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [10] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [9] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [9] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [8] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [8] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [7] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [7] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [4] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [4] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [1] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [1] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [0] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [0] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [31] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [31] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [62] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [62] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [61] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [61] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [60] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [60] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [59] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [59] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [58] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [58] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [57] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [57] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [56] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [56] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [55] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [55] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [54] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [54] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [53] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [53] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [52] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [52] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [51] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [51] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [50] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [50] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [49] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [49] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [48] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [48] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [47] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [47] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [46] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [46] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [45] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [45] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [44] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [44] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [43] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [43] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [42] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [42] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [41] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [41] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [40] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [40] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [39] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [39] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [38] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [38] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [37] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [37] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [36] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [36] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [35] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [35] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [34] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [34] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [33] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [33] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [32] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [32] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [31] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [31] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [30] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [30] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [29] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [29] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [28] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [28] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [27] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [27] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [26] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [26] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [25] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [25] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [24] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [24] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [23] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [23] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [22] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [22] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [21] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [21] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [20] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [20] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [19] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [19] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [18] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [18] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [17] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [17] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [16] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [16] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [15] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [15] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [14] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [14] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [13] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [13] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [12] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [12] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [11] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [11] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [10] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [10] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [9] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [9] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [8] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [8] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [7] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [7] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [4] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [4] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [1] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [1] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [0] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [0] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [63] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [63] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.ras_nofat_error.afu_access_mode_error "logic fme_csr_ras_nofat_error_reset.ras_nofat_error.afu_access_mode_error" +Toggle 0to1 fme_csr_ras_nofat_error_reset.ras_nofat_error.afu_access_mode_error "logic fme_csr_ras_nofat_error_reset.ras_nofat_error.afu_access_mode_error" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_nofat_error_mask_update.word.upper32 "logic fme_csr_ras_nofat_error_mask_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [62] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [62] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [61] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [61] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [60] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [60] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [59] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [59] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [58] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [58] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [57] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [57] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [56] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [56] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [55] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [55] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [54] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [54] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [53] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [53] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [52] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [52] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [51] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [51] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [50] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [50] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [49] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [49] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [48] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [48] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [47] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [47] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [46] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [46] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [45] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [45] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [44] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [44] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [43] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [43] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [42] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [42] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [41] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [41] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [40] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [40] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [39] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [39] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [38] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [38] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [37] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [37] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [36] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [36] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [35] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [35] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [34] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [34] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [33] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [33] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [32] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [32] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [31] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [31] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [30] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [30] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [29] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [29] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [28] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [28] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [27] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [27] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [26] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [26] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [25] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [25] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [24] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [24] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [23] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [23] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [22] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [22] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [21] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [21] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [20] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [20] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [19] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [19] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [18] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [18] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [17] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [17] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [16] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [16] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [15] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [15] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [14] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [14] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [13] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [13] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [12] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [12] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [11] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [11] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [10] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [10] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [9] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [9] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [8] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [8] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [7] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [7] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [4] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [4] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [1] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [1] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [0] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [0] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.data [63] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.data [63] "logic fme_csr_ras_nofat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [30] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [30] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [29] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [29] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [28] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [28] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [27] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [27] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [26] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [26] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [25] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [25] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [24] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [24] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [23] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [23] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [22] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [22] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [21] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [21] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [20] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [20] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [19] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [19] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [18] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [18] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [17] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [17] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [16] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [16] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [15] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [15] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [14] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [14] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [13] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [13] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [12] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [12] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [11] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [11] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [10] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [10] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [9] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [9] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [8] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [8] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [7] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [7] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [4] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [4] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [1] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [1] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [0] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [0] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.word.lower32 [31] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.word.lower32 [31] "logic fme_csr_ras_nofat_error_mask_reset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_nofat_error_mask_reset.word.upper32 "logic fme_csr_ras_nofat_error_mask_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [62] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [62] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [61] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [61] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [60] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [60] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [59] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [59] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [58] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [58] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [57] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [57] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [56] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [56] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [55] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [55] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [54] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [54] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [53] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [53] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [52] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [52] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [51] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [51] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [50] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [50] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [49] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [49] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [48] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [48] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [47] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [47] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [46] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [46] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [45] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [45] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [44] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [44] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [43] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [43] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [42] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [42] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [41] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [41] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [40] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [40] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [39] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [39] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [38] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [38] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [37] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [37] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [36] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [36] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [35] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [35] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [34] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [34] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [33] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [33] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [32] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [32] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [31] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [31] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [30] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [30] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [29] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [29] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [28] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [28] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [27] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [27] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [26] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [26] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [25] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [25] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [24] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [24] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [23] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [23] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [22] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [22] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [21] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [21] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [20] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [20] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [19] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [19] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [18] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [18] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [17] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [17] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [16] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [16] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [15] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [15] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [14] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [14] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [13] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [13] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [12] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [12] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [11] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [11] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [10] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [10] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [9] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [9] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [8] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [8] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [7] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [7] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [4] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [4] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [1] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [1] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [0] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [0] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.data [63] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.data [63] "logic fme_csr_ras_nofat_error_mask_reset.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_nofat_error_mask.word.upper32 "logic fme_csr_ras_nofat_error_mask.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [30] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [30] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [29] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [29] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [28] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [28] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [27] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [27] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [26] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [26] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [25] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [25] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [24] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [24] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [23] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [23] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [22] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [22] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [21] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [21] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [20] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [20] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [19] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [19] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [18] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [18] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [17] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [17] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [16] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [16] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [15] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [15] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [14] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [14] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [13] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [13] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [12] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [12] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [10] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [10] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [5] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [5] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [4] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [4] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [3] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [3] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [2] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [2] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [1] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [1] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [0] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [0] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.word.lower32 [31] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.word.lower32 [31] "logic fme_csr_ras_catfat_error_mask_update.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_catfat_error_mask_update.word.upper32 "logic fme_csr_ras_catfat_error_mask_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [30] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [30] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [29] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [29] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [28] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [28] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [27] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [27] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [26] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [26] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [25] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [25] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [24] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [24] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [23] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [23] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [22] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [22] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [21] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [21] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [20] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [20] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [19] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [19] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [18] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [18] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [17] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [17] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [16] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [16] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [15] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [15] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [14] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [14] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [13] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [13] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [12] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [12] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [10] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [10] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [5] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [5] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [4] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [4] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [3] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [3] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [2] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [2] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [1] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [1] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [0] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [0] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.word.lower32 [31] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.word.lower32 [31] "logic fme_csr_ras_catfat_error_mask_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [62] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [62] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [61] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [61] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [60] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [60] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [59] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [59] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [58] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [58] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [57] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [57] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [56] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [56] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [55] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [55] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [54] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [54] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [53] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [53] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [52] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [52] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [51] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [51] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [50] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [50] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [49] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [49] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [48] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [48] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [47] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [47] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [46] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [46] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [45] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [45] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [44] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [44] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [43] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [43] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [42] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [42] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [41] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [41] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [40] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [40] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [39] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [39] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [38] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [38] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [37] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [37] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [36] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [36] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [35] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [35] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [34] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [34] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [33] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [33] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [32] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [32] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [31] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [31] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [30] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [30] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [29] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [29] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [28] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [28] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [27] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [27] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [26] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [26] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [25] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [25] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [24] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [24] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [23] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [23] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [22] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [22] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [21] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [21] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [20] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [20] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [19] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [19] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [18] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [18] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [17] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [17] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [16] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [16] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [15] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [15] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [14] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [14] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [13] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [13] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [12] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [12] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [10] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [10] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [5] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [5] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [4] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [4] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [3] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [3] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [2] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [2] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [1] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [1] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [0] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [0] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.data [63] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.data [63] "logic fme_csr_ras_catfat_error_mask_update.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_catfat_error_mask_reset.word.upper32 "logic fme_csr_ras_catfat_error_mask_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [30] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [30] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [29] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [29] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [28] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [28] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [27] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [27] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [26] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [26] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [25] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [25] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [24] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [24] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [23] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [23] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [22] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [22] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [21] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [21] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [20] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [20] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [19] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [19] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [18] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [18] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [17] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [17] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [16] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [16] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [15] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [15] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [14] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [14] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [13] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [13] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [12] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [12] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [10] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [10] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [5] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [5] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [4] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [4] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [3] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [3] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [2] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [2] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [1] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [1] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [0] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [0] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error.word.lower32 [31] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error.word.lower32 [31] "logic fme_csr_ras_catfat_error.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_catfat_error.word.upper32 "logic fme_csr_ras_catfat_error.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [62] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [62] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [61] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [61] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [60] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [60] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [59] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [59] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [58] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [58] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [57] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [57] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [56] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [56] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [55] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [55] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [54] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [54] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [53] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [53] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [52] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [52] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [51] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [51] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [50] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [50] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [49] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [49] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [48] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [48] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [47] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [47] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [46] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [46] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [45] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [45] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [44] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [44] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [43] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [43] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [42] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [42] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [41] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [41] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [40] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [40] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [39] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [39] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [38] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [38] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [37] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [37] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [36] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [36] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [35] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [35] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [34] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [34] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [33] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [33] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [32] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [32] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [31] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [31] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [30] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [30] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [29] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [29] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [28] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [28] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [27] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [27] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [26] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [26] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [25] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [25] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [24] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [24] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [23] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [23] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [22] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [22] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [21] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [21] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [20] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [20] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [19] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [19] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [18] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [18] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [17] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [17] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [16] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [16] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [15] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [15] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [14] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [14] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [13] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [13] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [12] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [12] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [10] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [10] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [5] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [5] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [4] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [4] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [3] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [3] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [2] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [2] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [1] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [1] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [0] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [0] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.data [63] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.data [63] "logic fme_csr_ras_catfat_error_mask_reset.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_catfat_error_mask.word.upper32 "logic fme_csr_ras_catfat_error_mask.word.upper32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [30] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [30] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [29] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [29] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [28] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [28] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [27] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [27] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [26] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [26] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [25] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [25] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [24] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [24] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [22] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [22] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [15] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [15] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [14] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [14] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [13] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [13] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [12] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [12] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [11] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [11] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [10] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [10] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [9] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [9] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [7] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [7] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [6] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [6] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [5] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [5] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [4] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [4] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [3] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [3] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [2] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [2] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [1] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [1] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [0] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [0] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.word.lower32 [31] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.word.lower32 [31] "logic fme_csr_fpmon_fab_ctl_update.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fpmon_fab_ctl_update.word.upper32 "logic fme_csr_fpmon_fab_ctl_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [62] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [62] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [61] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [61] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [60] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [60] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [59] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [59] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [58] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [58] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [57] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [57] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [56] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [56] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [55] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [55] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [54] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [54] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [53] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [53] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [52] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [52] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [51] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [51] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [50] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [50] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [49] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [49] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [48] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [48] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [47] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [47] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [46] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [46] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [45] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [45] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [44] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [44] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [43] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [43] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [42] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [42] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [41] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [41] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [40] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [40] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [39] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [39] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [38] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [38] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [37] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [37] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [36] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [36] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [35] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [35] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [34] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [34] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [33] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [33] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [32] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [32] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [31] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [31] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [30] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [30] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [29] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [29] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [28] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [28] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [27] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [27] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [26] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [26] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [25] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [25] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [24] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [24] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [22] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [22] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [15] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [15] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [14] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [14] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [13] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [13] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [12] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [12] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [11] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [11] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [10] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [10] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [9] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [9] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [7] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [7] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [6] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [6] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [5] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [5] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [4] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [4] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [3] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [3] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [2] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [2] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [1] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [1] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [0] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [0] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.data [63] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.data [63] "logic fme_csr_fpmon_fab_ctl_update.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fpmon_fab_ctl_reset.word.upper32 "logic fme_csr_fpmon_fab_ctl_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [62] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [62] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [61] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [61] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [60] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [60] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [59] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [59] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [58] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [58] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [57] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [57] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [56] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [56] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [55] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [55] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [54] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [54] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [53] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [53] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [52] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [52] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [51] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [51] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [50] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [50] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [49] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [49] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [48] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [48] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [47] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [47] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [46] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [46] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [45] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [45] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [44] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [44] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [43] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [43] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [42] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [42] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [41] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [41] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [40] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [40] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [39] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [39] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [38] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [38] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [37] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [37] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [36] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [36] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [35] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [35] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [34] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [34] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [33] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [33] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [32] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [32] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [31] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [31] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [30] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [30] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [29] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [29] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [28] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [28] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [27] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [27] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [26] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [26] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [25] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [25] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [24] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [24] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [22] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [22] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [63] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [63] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [7] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [7] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [6] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [6] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [5] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [5] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [4] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [4] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [3] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [3] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [2] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [2] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [1] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [1] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [0] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [0] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [15] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [15] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [14] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [14] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [13] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [13] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [12] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [12] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [11] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [11] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [10] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [10] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.data [9] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.data [9] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +Toggle fme_csr_fpmon_fab_ctl_reset.data [8] "logic fme_csr_fpmon_fab_ctl_reset.data[63:0]" +ANNOTATION: " Covered in Ral coverage " +Toggle fme_csr_fme_scratchpad0_reset.word.lower32 "logic fme_csr_fme_scratchpad0_reset.word.lower32[31:0]" +ANNOTATION: " Covered in Ral coverage " +Toggle fme_csr_fme_scratchpad0_reset.word.upper32 "logic fme_csr_fme_scratchpad0_reset.word.upper32[31:0]" +ANNOTATION: " Covered in Ral coverage " +Toggle fme_csr_fme_scratchpad0_update.data "logic fme_csr_fme_scratchpad0_update.data[63:0]" +ANNOTATION: " Covered in Ral coverage " +Toggle fme_csr_fme_scratchpad0_update.word.lower32 "logic fme_csr_fme_scratchpad0_update.word.lower32[31:0]" +ANNOTATION: " Covered in Ral coverage " +Toggle fme_csr_fme_scratchpad0_update.word.upper32 "logic fme_csr_fme_scratchpad0_update.word.upper32[31:0]" +ANNOTATION: " Covered in Ral coverage " +Toggle fme_csr_fme_scratchpad0_reset.data "logic fme_csr_fme_scratchpad0_reset.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_error_mask0_reset.word.upper32 "logic fme_csr_fme_error_mask0_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [62] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [62] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [61] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [61] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [60] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [60] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [59] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [59] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [58] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [58] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [57] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [57] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [56] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [56] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [55] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [55] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [54] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [54] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [53] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [53] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [52] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [52] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [51] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [51] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [50] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [50] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [49] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [49] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [48] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [48] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [47] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [47] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [46] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [46] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [45] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [45] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [44] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [44] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [43] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [43] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [42] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [42] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [41] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [41] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [40] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [40] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [39] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [39] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [38] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [38] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [37] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [37] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [36] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [36] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [35] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [35] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [34] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [34] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [33] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [33] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [32] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [32] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [31] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [31] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [30] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [30] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [29] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [29] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [28] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [28] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [27] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [27] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [26] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [26] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [25] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [25] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [24] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [24] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [23] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [23] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [22] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [22] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [21] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [21] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [20] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [20] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [19] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [19] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [18] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [18] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [17] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [17] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [16] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [16] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [15] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [15] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [14] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [14] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [13] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [13] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [12] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [12] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [11] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [11] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [10] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [10] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [9] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [9] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [8] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [8] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [7] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [7] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [6] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [6] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [4] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [4] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [3] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [3] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [2] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [2] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.data [63] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.data [63] "logic fme_csr_fme_error_mask0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [62] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [62] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [61] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [61] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [60] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [60] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [59] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [59] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [58] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [58] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [57] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [57] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [56] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [56] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [55] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [55] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [54] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [54] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [53] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [53] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [52] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [52] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [51] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [51] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [50] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [50] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [49] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [49] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [48] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [48] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [47] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [47] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [46] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [46] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [45] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [45] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [44] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [44] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [43] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [43] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [42] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [42] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [41] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [41] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [40] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [40] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [39] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [39] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [38] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [38] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [37] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [37] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [36] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [36] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [35] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [35] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [34] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [34] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [33] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [33] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [32] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [32] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [31] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [31] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [30] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [30] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [29] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [29] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [28] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [28] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [27] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [27] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [26] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [26] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [25] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [25] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [24] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [24] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [23] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [23] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [22] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [22] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [21] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [21] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [20] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [20] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [19] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [19] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [18] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [18] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [17] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [17] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [16] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [16] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [15] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [15] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [14] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [14] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [13] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [13] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [12] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [12] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [11] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [11] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [10] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [10] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [9] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [9] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [8] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [8] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [7] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [7] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [6] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [6] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [4] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [4] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [3] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [3] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [2] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [2] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.data [63] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.data [63] "logic fme_csr_fme_error_mask0_reset.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_error_mask0.word.upper32 "logic fme_csr_fme_error_mask0.word.upper32[31:0]" +Toggle 1to0 arsize_valid "logic arsize_valid" +Toggle 0to1 arsize_valid "logic arsize_valid" +ANNOTATION: " Axi related signals that are not used, so excluding " +Toggle arid_reg "logic arid_reg[5:0]" +Toggle 1to0 awsize_valid "logic awsize_valid" +Toggle 0to1 awsize_valid "logic awsize_valid" +Toggle 1to0 debug_awsize_valid "logic debug_awsize_valid" +Toggle 0to1 debug_awsize_valid "logic debug_awsize_valid" +ANNOTATION: " Axi related signals that are not used, so excluding " +Toggle awid_reg "logic awid_reg[5:0]" +Toggle 1to0 fme_csr_ras_nofat_error.ras_nofat_error.afu_access_mode_error "logic fme_csr_ras_nofat_error.ras_nofat_error.afu_access_mode_error" +Toggle 0to1 fme_csr_ras_nofat_error.ras_nofat_error.afu_access_mode_error "logic fme_csr_ras_nofat_error.ras_nofat_error.afu_access_mode_error" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_error_mask0_update.word.upper32 "logic fme_csr_fme_error_mask0_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [30] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [30] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [29] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [29] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [28] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [28] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [27] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [27] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [26] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [26] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [25] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [25] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [24] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [24] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [23] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [23] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [22] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [22] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [21] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [21] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [20] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [20] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [19] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [19] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [18] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [18] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [17] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [17] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [16] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [16] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [15] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [15] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [14] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [14] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [13] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [13] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [12] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [12] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [11] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [11] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [10] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [10] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [9] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [9] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [8] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [8] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [7] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [7] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [6] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [6] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [4] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [4] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [3] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [3] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [2] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [2] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_update.word.lower32 [31] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_update.word.lower32 [31] "logic fme_csr_fme_error_mask0_update.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle ras_nofat_error_attr.ras_nofat_error.afu_access_mode_error "logic ras_nofat_error_attr.ras_nofat_error.afu_access_mode_error[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_bitstream_id_reset.bitstream_id.ver_major "logic fme_csr_bitstream_id_reset.bitstream_id.ver_major[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset_reset.port_offset.bar_id "logic fme_csr_port1_offset_reset.port_offset.bar_id[2:0]" +Toggle 1to0 fme_csr_port1_offset.port_offset.port_implemented "logic fme_csr_port1_offset.port_offset.port_implemented" +Toggle 0to1 fme_csr_port1_offset.port_offset.port_implemented "logic fme_csr_port1_offset.port_offset.port_implemented" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset.port_offset.bar_id "logic fme_csr_port1_offset.port_offset.bar_id[2:0]" +Toggle 1to0 fme_csr_port0_offset_update.port_offset.port_implemented "logic fme_csr_port0_offset_update.port_offset.port_implemented" +Toggle 0to1 fme_csr_port0_offset_update.port_offset.port_implemented "logic fme_csr_port0_offset_update.port_offset.port_implemented" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset_update.port_offset.bar_id "logic fme_csr_port0_offset_update.port_offset.bar_id[2:0]" +Toggle 1to0 fme_csr_port0_offset_reset.port_offset.port_implemented "logic fme_csr_port0_offset_reset.port_offset.port_implemented" +Toggle 0to1 fme_csr_port0_offset_reset.port_offset.port_implemented "logic fme_csr_port0_offset_reset.port_offset.port_implemented" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset_reset.port_offset.bar_id "logic fme_csr_port0_offset_reset.port_offset.bar_id[2:0]" +Toggle 1to0 fme_csr_port0_offset.port_offset.port_implemented "logic fme_csr_port0_offset.port_offset.port_implemented" +Toggle 0to1 fme_csr_port0_offset.port_offset.port_implemented "logic fme_csr_port0_offset.port_offset.port_implemented" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset.port_offset.bar_id "logic fme_csr_port0_offset.port_offset.bar_id[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_bitstream_id_update.bitstream_id.ver_major "logic fme_csr_bitstream_id_update.bitstream_id.ver_major[3:0]" +Toggle 1to0 fme_csr_port1_offset_reset.port_offset.port_implemented "logic fme_csr_port1_offset_reset.port_offset.port_implemented" +Toggle 0to1 fme_csr_port1_offset_reset.port_offset.port_implemented "logic fme_csr_port1_offset_reset.port_offset.port_implemented" +Toggle 1to0 fme_csr_port3_offset.port_offset.port_implemented "logic fme_csr_port3_offset.port_offset.port_implemented" +Toggle 0to1 fme_csr_port3_offset.port_offset.port_implemented "logic fme_csr_port3_offset.port_offset.port_implemented" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset.port_offset.bar_id "logic fme_csr_port3_offset.port_offset.bar_id[2:0]" +Toggle 1to0 fme_csr_port2_offset_reset.port_offset.port_implemented "logic fme_csr_port2_offset_reset.port_offset.port_implemented" +Toggle 0to1 fme_csr_port2_offset_reset.port_offset.port_implemented "logic fme_csr_port2_offset_reset.port_offset.port_implemented" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset_reset.port_offset.bar_id "logic fme_csr_port2_offset_reset.port_offset.bar_id[2:0]" +Toggle 1to0 fme_csr_port2_offset.port_offset.port_implemented "logic fme_csr_port2_offset.port_offset.port_implemented" +Toggle 0to1 fme_csr_port2_offset.port_offset.port_implemented "logic fme_csr_port2_offset.port_offset.port_implemented" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset.port_offset.bar_id "logic fme_csr_port2_offset.port_offset.bar_id[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset_reset.port_offset.bar_id "logic fme_csr_port3_offset_reset.port_offset.bar_id[2:0]" +Toggle 1to0 fme_csr_ras_catfat_error.ras_catfat_error.fabric_fatal_error "logic fme_csr_ras_catfat_error.ras_catfat_error.fabric_fatal_error" +Toggle 0to1 fme_csr_ras_catfat_error.ras_catfat_error.fabric_fatal_error "logic fme_csr_ras_catfat_error.ras_catfat_error.fabric_fatal_error" +Toggle 1to0 fme_csr_ras_catfat_error.ras_catfat_error.pcie_poison_error "logic fme_csr_ras_catfat_error.ras_catfat_error.pcie_poison_error" +Toggle 0to1 fme_csr_ras_catfat_error.ras_catfat_error.pcie_poison_error "logic fme_csr_ras_catfat_error.ras_catfat_error.pcie_poison_error" +Toggle 1to0 fme_csr_ras_nofat_error.ras_nofat_error.pcie_error "logic fme_csr_ras_nofat_error.ras_nofat_error.pcie_error" +Toggle 0to1 fme_csr_ras_nofat_error.ras_nofat_error.pcie_error "logic fme_csr_ras_nofat_error.ras_nofat_error.pcie_error" +Toggle 1to0 fme_csr_tmp_threshold.tmp_threshold.threshold2_status "logic fme_csr_tmp_threshold.tmp_threshold.threshold2_status" +Toggle 0to1 fme_csr_tmp_threshold.tmp_threshold.threshold2_status "logic fme_csr_tmp_threshold.tmp_threshold.threshold2_status" +Toggle 1to0 fme_csr_tmp_threshold.tmp_threshold.therm_trip_status "logic fme_csr_tmp_threshold.tmp_threshold.therm_trip_status" +Toggle 0to1 fme_csr_tmp_threshold.tmp_threshold.therm_trip_status "logic fme_csr_tmp_threshold.tmp_threshold.therm_trip_status" +Toggle 1to0 fme_csr_ras_nofat_error_reset.ras_nofat_error.pcie_error "logic fme_csr_ras_nofat_error_reset.ras_nofat_error.pcie_error" +Toggle 0to1 fme_csr_ras_nofat_error_reset.ras_nofat_error.pcie_error "logic fme_csr_ras_nofat_error_reset.ras_nofat_error.pcie_error" +Toggle 1to0 fme_csr_tmp_threshold.tmp_threshold.threshold1_status "logic fme_csr_tmp_threshold.tmp_threshold.threshold1_status" +Toggle 0to1 fme_csr_tmp_threshold.tmp_threshold.threshold1_status "logic fme_csr_tmp_threshold.tmp_threshold.threshold1_status" +Toggle 1to0 fme_csr_tmp_threshold_capability_reset.tmp_threshold_capability.disable_tmp_thresh_report "logic fme_csr_tmp_threshold_capability_reset.tmp_threshold_capability.disable_tmp_thresh_report" +Toggle 0to1 fme_csr_tmp_threshold_capability_reset.tmp_threshold_capability.disable_tmp_thresh_report "logic fme_csr_tmp_threshold_capability_reset.tmp_threshold_capability.disable_tmp_thresh_report" +Toggle 1to0 fme_csr_tmp_threshold_capability_update.tmp_threshold_capability.disable_tmp_thresh_report "logic fme_csr_tmp_threshold_capability_update.tmp_threshold_capability.disable_tmp_thresh_report" +Toggle 0to1 fme_csr_tmp_threshold_capability_update.tmp_threshold_capability.disable_tmp_thresh_report "logic fme_csr_tmp_threshold_capability_update.tmp_threshold_capability.disable_tmp_thresh_report" +Toggle fme_dfh_attr.fme_dfh.end_of_list "logic fme_dfh_attr.fme_dfh.end_of_list[3:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle glbl_error_capability_attr.glbl_error_capability.supports_interrupt "logic glbl_error_capability_attr.glbl_error_capability.supports_interrupt[3:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle glbl_perf_dfh_attr.dfh.end_of_list "logic glbl_perf_dfh_attr.dfh.end_of_list[3:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle glbl_error_dfh_attr.dfh.end_of_list "logic glbl_error_dfh_attr.dfh.end_of_list[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle tmp_rdsensor_fmt1_attr.tmp_rdsensor_fmt1.temp_valid "logic tmp_rdsensor_fmt1_attr.tmp_rdsensor_fmt1.temp_valid[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle tmp_threshold_attr.tmp_threshold.therm_trip_status "logic tmp_threshold_attr.tmp_threshold.therm_trip_status[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle tmp_threshold_attr.tmp_threshold.threshold1_status "logic tmp_threshold_attr.tmp_threshold.threshold1_status[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle tmp_threshold_attr.tmp_threshold.threshold2_status "logic tmp_threshold_attr.tmp_threshold.threshold2_status[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle therm_mngm_dfh_attr.dfh.end_of_list "logic therm_mngm_dfh_attr.dfh.end_of_list[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle ras_nofat_error_attr.ras_nofat_error.pcie_error "logic ras_nofat_error_attr.ras_nofat_error.pcie_error[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle port1_offset_attr.port_offset.port_implemented "logic port1_offset_attr.port_offset.port_implemented[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle port2_offset_attr.port_offset.port_implemented "logic port2_offset_attr.port_offset.port_implemented[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle port3_offset_attr.port_offset.port_implemented "logic port3_offset_attr.port_offset.port_implemented[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle port0_offset_attr.port_offset.port_implemented "logic port0_offset_attr.port_offset.port_implemented[3:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_4030_update.word.upper32 "logic fme_csr_dummy_4030_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_4030_update.word.lower32 "logic fme_csr_dummy_4030_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_4030_update.data "logic fme_csr_dummy_4030_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_4030_reset.word.upper32 "logic fme_csr_dummy_4030_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_4030_reset.word.lower32 "logic fme_csr_dummy_4030_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_4030_reset.data "logic fme_csr_dummy_4030_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_4028_update.word.upper32 "logic fme_csr_dummy_4028_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_4028_update.word.lower32 "logic fme_csr_dummy_4028_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_4028_update.data "logic fme_csr_dummy_4028_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_4028_reset.word.upper32 "logic fme_csr_dummy_4028_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_4028_reset.word.lower32 "logic fme_csr_dummy_4028_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_4028_reset.data "logic fme_csr_dummy_4028_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_3018_update.word.upper32 "logic fme_csr_dummy_3018_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_3018_update.word.lower32 "logic fme_csr_dummy_3018_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_3018_update.data "logic fme_csr_dummy_3018_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_3018_reset.word.upper32 "logic fme_csr_dummy_3018_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_3018_reset.word.lower32 "logic fme_csr_dummy_3018_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_3018_reset.data "logic fme_csr_dummy_3018_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_3010_update.word.upper32 "logic fme_csr_dummy_3010_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_3010_update.word.lower32 "logic fme_csr_dummy_3010_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_3010_update.data "logic fme_csr_dummy_3010_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_3010_reset.word.upper32 "logic fme_csr_dummy_3010_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_3010_reset.word.lower32 "logic fme_csr_dummy_3010_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_3010_reset.data "logic fme_csr_dummy_3010_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_3008_update.word.upper32 "logic fme_csr_dummy_3008_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_3008_update.word.lower32 "logic fme_csr_dummy_3008_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_3008_update.data "logic fme_csr_dummy_3008_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_3008_reset.word.upper32 "logic fme_csr_dummy_3008_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_3008_reset.word.lower32 "logic fme_csr_dummy_3008_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_3008_reset.data "logic fme_csr_dummy_3008_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_0020_update.word.upper32 "logic fme_csr_dummy_0020_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_0020_update.word.lower32 "logic fme_csr_dummy_0020_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_0020_update.data "logic fme_csr_dummy_0020_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_0020_reset.word.upper32 "logic fme_csr_dummy_0020_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_0020_reset.word.lower32 "logic fme_csr_dummy_0020_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_0020_reset.data "logic fme_csr_dummy_0020_reset.data[63:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability_update.word.lower32 "logic fme_csr_fab_capability_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fab_capability_update.fab_capability.pcie0_link "logic fme_csr_fab_capability_update.fab_capability.pcie0_link" +Toggle 0to1 fme_csr_fab_capability_update.fab_capability.pcie0_link "logic fme_csr_fab_capability_update.fab_capability.pcie0_link" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability_update.fab_capability.num_ports "logic fme_csr_fab_capability_update.fab_capability.num_ports[2:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability_update.fab_capability.fabric_version "logic fme_csr_fab_capability_update.fab_capability.fabric_version[7:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability_update.fab_capability.addr_width "logic fme_csr_fab_capability_update.fab_capability.addr_width[5:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability_update.data "logic fme_csr_fab_capability_update.data[63:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability_reset.word.upper32 "logic fme_csr_fab_capability_reset.word.upper32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability_reset.word.lower32 "logic fme_csr_fab_capability_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fab_capability_reset.fab_capability.pcie0_link "logic fme_csr_fab_capability_reset.fab_capability.pcie0_link" +Toggle 0to1 fme_csr_fab_capability_reset.fab_capability.pcie0_link "logic fme_csr_fab_capability_reset.fab_capability.pcie0_link" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability_reset.fab_capability.num_ports "logic fme_csr_fab_capability_reset.fab_capability.num_ports[2:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability_reset.fab_capability.fabric_version "logic fme_csr_fab_capability_reset.fab_capability.fabric_version[7:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability_reset.fab_capability.addr_width "logic fme_csr_fab_capability_reset.fab_capability.addr_width[5:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability_reset.data "logic fme_csr_fab_capability_reset.data[63:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability.word.upper32 "logic fme_csr_fab_capability.word.upper32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability.word.lower32 "logic fme_csr_fab_capability.word.lower32[31:0]" +Toggle 1to0 fme_csr_fab_capability.fab_capability.pcie0_link "logic fme_csr_fab_capability.fab_capability.pcie0_link" +Toggle 0to1 fme_csr_fab_capability.fab_capability.pcie0_link "logic fme_csr_fab_capability.fab_capability.pcie0_link" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability.fab_capability.num_ports "logic fme_csr_fab_capability.fab_capability.num_ports[2:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability.fab_capability.fabric_version "logic fme_csr_fab_capability.fab_capability.fabric_version[7:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability.fab_capability.addr_width "logic fme_csr_fab_capability.fab_capability.addr_width[5:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability.data "logic fme_csr_fab_capability.data[63:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability_update.word.upper32 "logic fme_csr_fab_capability_update.word.upper32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fme_dfh_update.word.lower32 "logic fme_csr_fme_dfh_update.word.lower32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fme_dfh_update.fme_dfh.next_dfh_offset "logic fme_csr_fme_dfh_update.fme_dfh.next_dfh_offset[23:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fme_dfh_update.fme_dfh.feature_type "logic fme_csr_fme_dfh_update.fme_dfh.feature_type[3:0]" +Toggle 1to0 fme_csr_fme_dfh_update.fme_dfh.end_of_list "logic fme_csr_fme_dfh_update.fme_dfh.end_of_list" +Toggle 0to1 fme_csr_fme_dfh_update.fme_dfh.end_of_list "logic fme_csr_fme_dfh_update.fme_dfh.end_of_list" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fme_dfh_update.fme_dfh.corefim_version "logic fme_csr_fme_dfh_update.fme_dfh.corefim_version[11:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fme_dfh_update.fme_dfh.afu_maj_version "logic fme_csr_fme_dfh_update.fme_dfh.afu_maj_version[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fme_dfh_update.data "logic fme_csr_fme_dfh_update.data[63:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fme_dfh_reset.word.upper32 "logic fme_csr_fme_dfh_reset.word.upper32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fme_dfh_reset.word.lower32 "logic fme_csr_fme_dfh_reset.word.lower32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fme_dfh_reset.fme_dfh.next_dfh_offset "logic fme_csr_fme_dfh_reset.fme_dfh.next_dfh_offset[23:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fme_dfh_reset.fme_dfh.feature_type "logic fme_csr_fme_dfh_reset.fme_dfh.feature_type[3:0]" +Toggle 1to0 fme_csr_fme_dfh_reset.fme_dfh.end_of_list "logic fme_csr_fme_dfh_reset.fme_dfh.end_of_list" +Toggle 0to1 fme_csr_fme_dfh_reset.fme_dfh.end_of_list "logic fme_csr_fme_dfh_reset.fme_dfh.end_of_list" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fme_dfh_reset.fme_dfh.corefim_version "logic fme_csr_fme_dfh_reset.fme_dfh.corefim_version[11:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fme_dfh_reset.fme_dfh.afu_maj_version "logic fme_csr_fme_dfh_reset.fme_dfh.afu_maj_version[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fme_dfh_reset.data "logic fme_csr_fme_dfh_reset.data[63:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle " +Toggle fme_csr_fme_afu_id_l_update.word.upper32 "logic fme_csr_fme_afu_id_l_update.word.upper32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle " +Toggle fme_csr_fme_afu_id_l_update.word.lower32 "logic fme_csr_fme_afu_id_l_update.word.lower32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle " +Toggle fme_csr_fme_afu_id_l_update.fme_afu_id_l.afu_id_l "logic fme_csr_fme_afu_id_l_update.fme_afu_id_l.afu_id_l[63:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle " +Toggle fme_csr_fme_afu_id_l_update.data "logic fme_csr_fme_afu_id_l_update.data[63:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle " +Toggle fme_csr_fme_afu_id_l_reset.word.upper32 "logic fme_csr_fme_afu_id_l_reset.word.upper32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle " +Toggle fme_csr_fme_afu_id_l_reset.word.lower32 "logic fme_csr_fme_afu_id_l_reset.word.lower32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle " +Toggle fme_csr_fme_afu_id_l_reset.fme_afu_id_l.afu_id_l "logic fme_csr_fme_afu_id_l_reset.fme_afu_id_l.afu_id_l[63:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle " +Toggle fme_csr_fme_afu_id_l_reset.data "logic fme_csr_fme_afu_id_l_reset.data[63:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle " +Toggle fme_csr_fme_afu_id_h_update.word.upper32 "logic fme_csr_fme_afu_id_h_update.word.upper32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle " +Toggle fme_csr_fme_afu_id_h_update.word.lower32 "logic fme_csr_fme_afu_id_h_update.word.lower32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle " +Toggle fme_csr_fme_afu_id_h_update.fme_afu_id_h.afu_id_h "logic fme_csr_fme_afu_id_h_update.fme_afu_id_h.afu_id_h[63:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle " +Toggle fme_csr_fme_afu_id_h_update.data "logic fme_csr_fme_afu_id_h_update.data[63:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle " +Toggle fme_csr_fme_afu_id_h_reset.word.upper32 "logic fme_csr_fme_afu_id_h_reset.word.upper32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle " +Toggle fme_csr_fme_afu_id_h_reset.word.lower32 "logic fme_csr_fme_afu_id_h_reset.word.lower32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle " +Toggle fme_csr_fme_afu_id_h_reset.fme_afu_id_h.afu_id_h "logic fme_csr_fme_afu_id_h_reset.fme_afu_id_h.afu_id_h[63:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle " +Toggle fme_csr_fme_afu_id_h_reset.data "logic fme_csr_fme_afu_id_h_reset.data[63:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_status_update.word.upper32 "logic fme_csr_fab_status_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_status_update.word.lower32 "logic fme_csr_fab_status_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fab_status_update.fab_status.pcie0_link_status "logic fme_csr_fab_status_update.fab_status.pcie0_link_status" +Toggle 0to1 fme_csr_fab_status_update.fab_status.pcie0_link_status "logic fme_csr_fab_status_update.fab_status.pcie0_link_status" +Toggle 1to0 fme_csr_fab_status_reset.fab_status.pcie0_link_status "logic fme_csr_fab_status_reset.fab_status.pcie0_link_status" +Toggle 0to1 fme_csr_fab_status_reset.fab_status.pcie0_link_status "logic fme_csr_fab_status_reset.fab_status.pcie0_link_status" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fme_dfh_update.word.upper32 "logic fme_csr_fme_dfh_update.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_first_error_update.word.lower32 "logic fme_csr_fme_first_error_update.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_first_error_update.fme_first_next_error.error_reg_status "logic fme_csr_fme_first_error_update.fme_first_next_error.error_reg_status[59:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_first_error_update.fme_first_next_error.error_reg_id "logic fme_csr_fme_first_error_update.fme_first_next_error.error_reg_id[1:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_first_error_update.data "logic fme_csr_fme_first_error_update.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_first_error_reset.word.upper32 "logic fme_csr_fme_first_error_reset.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_first_error_reset.word.lower32 "logic fme_csr_fme_first_error_reset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_first_error_reset.fme_first_next_error.error_reg_status "logic fme_csr_fme_first_error_reset.fme_first_next_error.error_reg_status[59:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_first_error_reset.fme_first_next_error.error_reg_id "logic fme_csr_fme_first_error_reset.fme_first_next_error.error_reg_id[1:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_first_error_reset.data "logic fme_csr_fme_first_error_reset.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_first_error_update.word.upper32 "logic fme_csr_fme_first_error_update.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_next_afu_update.word.lower32 "logic fme_csr_fme_next_afu_update.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_next_afu_update.fme_next_afu.next_afu_dfh_offset "logic fme_csr_fme_next_afu_update.fme_next_afu.next_afu_dfh_offset[23:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_next_afu_update.data "logic fme_csr_fme_next_afu_update.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_next_afu_reset.word.upper32 "logic fme_csr_fme_next_afu_reset.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_next_afu_reset.word.lower32 "logic fme_csr_fme_next_afu_reset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_next_afu_reset.fme_next_afu.next_afu_dfh_offset "logic fme_csr_fme_next_afu_reset.fme_next_afu.next_afu_dfh_offset[23:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_next_afu_reset.data "logic fme_csr_fme_next_afu_reset.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_next_afu_update.word.upper32 "logic fme_csr_fme_next_afu_update.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_next_error_update.word.lower32 "logic fme_csr_fme_next_error_update.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_next_error_update.fme_first_next_error.error_reg_status "logic fme_csr_fme_next_error_update.fme_first_next_error.error_reg_status[59:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_next_error_update.fme_first_next_error.error_reg_id "logic fme_csr_fme_next_error_update.fme_first_next_error.error_reg_id[1:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_next_error_update.data "logic fme_csr_fme_next_error_update.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_next_error_reset.word.upper32 "logic fme_csr_fme_next_error_reset.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_next_error_reset.word.lower32 "logic fme_csr_fme_next_error_reset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_next_error_reset.fme_first_next_error.error_reg_status "logic fme_csr_fme_next_error_reset.fme_first_next_error.error_reg_status[59:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_next_error_reset.fme_first_next_error.error_reg_id "logic fme_csr_fme_next_error_reset.fme_first_next_error.error_reg_id[1:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_next_error_reset.data "logic fme_csr_fme_next_error_reset.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_next_error_update.word.upper32 "logic fme_csr_fme_next_error_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_fpmon_clk_ctr_update.word.lower32 "logic fme_csr_fpmon_clk_ctr_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_fpmon_clk_ctr_update.fpmon_clk_ctr.clock_counter "logic fme_csr_fpmon_clk_ctr_update.fpmon_clk_ctr.clock_counter[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_fpmon_clk_ctr_update.data "logic fme_csr_fpmon_clk_ctr_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_fpmon_clk_ctr_reset.word.upper32 "logic fme_csr_fpmon_clk_ctr_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_fpmon_clk_ctr_reset.word.lower32 "logic fme_csr_fpmon_clk_ctr_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_fpmon_clk_ctr_reset.fpmon_clk_ctr.clock_counter "logic fme_csr_fpmon_clk_ctr_reset.fpmon_clk_ctr.clock_counter[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_fpmon_clk_ctr_reset.data "logic fme_csr_fpmon_clk_ctr_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_fpmon_clk_ctr_update.word.upper32 "logic fme_csr_fpmon_clk_ctr_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_fpmon_fab_ctr_update.fpmon_fab_ctr.fabric_event_counter "logic fme_csr_fpmon_fab_ctr_update.fpmon_fab_ctr.fabric_event_counter[59:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_fpmon_fab_ctr_update.fpmon_fab_ctr.fabric_event_code "logic fme_csr_fpmon_fab_ctr_update.fpmon_fab_ctr.fabric_event_code[3:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_fpmon_fab_ctr_update.data "logic fme_csr_fpmon_fab_ctr_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_fpmon_fab_ctr_reset.word.upper32 "logic fme_csr_fpmon_fab_ctr_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_fpmon_fab_ctr_reset.word.lower32 "logic fme_csr_fpmon_fab_ctr_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_fpmon_fab_ctr_reset.fpmon_fab_ctr.fabric_event_counter "logic fme_csr_fpmon_fab_ctr_reset.fpmon_fab_ctr.fabric_event_counter[59:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_fpmon_fab_ctr_reset.fpmon_fab_ctr.fabric_event_code "logic fme_csr_fpmon_fab_ctr_reset.fpmon_fab_ctr.fabric_event_code[3:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_fpmon_fab_ctr_reset.data "logic fme_csr_fpmon_fab_ctr_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_fpmon_fab_ctr_update.word.lower32 "logic fme_csr_fpmon_fab_ctr_update.word.lower32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_capability_update.word.lower32 "logic fme_csr_glbl_error_capability_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_glbl_error_capability_update.glbl_error_capability.supports_interrupt "logic fme_csr_glbl_error_capability_update.glbl_error_capability.supports_interrupt" +Toggle 0to1 fme_csr_glbl_error_capability_update.glbl_error_capability.supports_interrupt "logic fme_csr_glbl_error_capability_update.glbl_error_capability.supports_interrupt" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_capability_update.glbl_error_capability.interrupt_vector_number "logic fme_csr_glbl_error_capability_update.glbl_error_capability.interrupt_vector_number[11:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_capability_update.data "logic fme_csr_glbl_error_capability_update.data[63:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_capability_reset.word.upper32 "logic fme_csr_glbl_error_capability_reset.word.upper32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_capability_reset.word.lower32 "logic fme_csr_glbl_error_capability_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_glbl_error_capability_reset.glbl_error_capability.supports_interrupt "logic fme_csr_glbl_error_capability_reset.glbl_error_capability.supports_interrupt" +Toggle 0to1 fme_csr_glbl_error_capability_reset.glbl_error_capability.supports_interrupt "logic fme_csr_glbl_error_capability_reset.glbl_error_capability.supports_interrupt" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_capability_reset.glbl_error_capability.interrupt_vector_number "logic fme_csr_glbl_error_capability_reset.glbl_error_capability.interrupt_vector_number[11:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_capability_reset.data "logic fme_csr_glbl_error_capability_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_fpmon_fab_ctr_update.word.upper32 "logic fme_csr_fpmon_fab_ctr_update.word.upper32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_capability_update.word.upper32 "logic fme_csr_glbl_error_capability_update.word.upper32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_dfh_update.word.lower32 "logic fme_csr_glbl_error_dfh_update.word.lower32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_dfh_update.dfh.next_dfh_offset "logic fme_csr_glbl_error_dfh_update.dfh.next_dfh_offset[23:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_dfh_update.dfh.feature_type "logic fme_csr_glbl_error_dfh_update.dfh.feature_type[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_dfh_update.dfh.feature_rev "logic fme_csr_glbl_error_dfh_update.dfh.feature_rev[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_dfh_update.dfh.feature_id "logic fme_csr_glbl_error_dfh_update.dfh.feature_id[11:0]" +Toggle 1to0 fme_csr_glbl_error_dfh_update.dfh.end_of_list "logic fme_csr_glbl_error_dfh_update.dfh.end_of_list" +Toggle 0to1 fme_csr_glbl_error_dfh_update.dfh.end_of_list "logic fme_csr_glbl_error_dfh_update.dfh.end_of_list" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_dfh_update.data "logic fme_csr_glbl_error_dfh_update.data[63:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_dfh_reset.word.upper32 "logic fme_csr_glbl_error_dfh_reset.word.upper32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_dfh_reset.word.lower32 "logic fme_csr_glbl_error_dfh_reset.word.lower32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_dfh_reset.dfh.next_dfh_offset "logic fme_csr_glbl_error_dfh_reset.dfh.next_dfh_offset[23:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_dfh_reset.dfh.feature_type "logic fme_csr_glbl_error_dfh_reset.dfh.feature_type[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_dfh_reset.dfh.feature_rev "logic fme_csr_glbl_error_dfh_reset.dfh.feature_rev[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_dfh_reset.dfh.feature_id "logic fme_csr_glbl_error_dfh_reset.dfh.feature_id[11:0]" +Toggle 1to0 fme_csr_glbl_error_dfh_reset.dfh.end_of_list "logic fme_csr_glbl_error_dfh_reset.dfh.end_of_list" +Toggle 0to1 fme_csr_glbl_error_dfh_reset.dfh.end_of_list "logic fme_csr_glbl_error_dfh_reset.dfh.end_of_list" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_dfh_reset.data "logic fme_csr_glbl_error_dfh_reset.data[63:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_dfh_update.word.upper32 "logic fme_csr_glbl_error_dfh_update.word.upper32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_perf_dfh_update.word.lower32 "logic fme_csr_glbl_perf_dfh_update.word.lower32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_perf_dfh_update.dfh.next_dfh_offset "logic fme_csr_glbl_perf_dfh_update.dfh.next_dfh_offset[23:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_perf_dfh_update.dfh.feature_type "logic fme_csr_glbl_perf_dfh_update.dfh.feature_type[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_perf_dfh_update.dfh.feature_rev "logic fme_csr_glbl_perf_dfh_update.dfh.feature_rev[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_perf_dfh_update.dfh.feature_id "logic fme_csr_glbl_perf_dfh_update.dfh.feature_id[11:0]" +Toggle 1to0 fme_csr_glbl_perf_dfh_update.dfh.end_of_list "logic fme_csr_glbl_perf_dfh_update.dfh.end_of_list" +Toggle 0to1 fme_csr_glbl_perf_dfh_update.dfh.end_of_list "logic fme_csr_glbl_perf_dfh_update.dfh.end_of_list" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_perf_dfh_update.data "logic fme_csr_glbl_perf_dfh_update.data[63:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_perf_dfh_reset.word.upper32 "logic fme_csr_glbl_perf_dfh_reset.word.upper32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_perf_dfh_reset.word.lower32 "logic fme_csr_glbl_perf_dfh_reset.word.lower32[31:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_perf_dfh_reset.dfh.next_dfh_offset "logic fme_csr_glbl_perf_dfh_reset.dfh.next_dfh_offset[23:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_perf_dfh_reset.dfh.feature_type "logic fme_csr_glbl_perf_dfh_reset.dfh.feature_type[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_perf_dfh_reset.dfh.feature_rev "logic fme_csr_glbl_perf_dfh_reset.dfh.feature_rev[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_perf_dfh_reset.dfh.feature_id "logic fme_csr_glbl_perf_dfh_reset.dfh.feature_id[11:0]" +Toggle 1to0 fme_csr_glbl_perf_dfh_reset.dfh.end_of_list "logic fme_csr_glbl_perf_dfh_reset.dfh.end_of_list" +Toggle 0to1 fme_csr_glbl_perf_dfh_reset.dfh.end_of_list "logic fme_csr_glbl_perf_dfh_reset.dfh.end_of_list" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_perf_dfh_reset.data "logic fme_csr_glbl_perf_dfh_reset.data[63:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_perf_dfh_update.word.upper32 "logic fme_csr_glbl_perf_dfh_update.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset_update.port_offset.bar_id "logic fme_csr_port1_offset_update.port_offset.bar_id[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset_reset.port_offset.port_byte_offset "logic fme_csr_port1_offset_reset.port_offset.port_byte_offset[23:0]" +Toggle 1to0 fme_csr_port1_offset_update.port_offset.port_implemented "logic fme_csr_port1_offset_update.port_offset.port_implemented" +Toggle 0to1 fme_csr_port1_offset_update.port_offset.port_implemented "logic fme_csr_port1_offset_update.port_offset.port_implemented" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset_update.port_offset.bar_id "logic fme_csr_port3_offset_update.port_offset.bar_id[2:0]" +Toggle 1to0 fme_csr_port3_offset_update.port_offset.afu_access_ctrl "logic fme_csr_port3_offset_update.port_offset.afu_access_ctrl" +Toggle 0to1 fme_csr_port3_offset_update.port_offset.afu_access_ctrl "logic fme_csr_port3_offset_update.port_offset.afu_access_ctrl" +Toggle 1to0 fme_csr_port3_offset_reset.port_offset.port_implemented "logic fme_csr_port3_offset_reset.port_offset.port_implemented" +Toggle 0to1 fme_csr_port3_offset_reset.port_offset.port_implemented "logic fme_csr_port3_offset_reset.port_offset.port_implemented" +Toggle 1to0 fme_csr_port2_offset_update.port_offset.port_implemented "logic fme_csr_port2_offset_update.port_offset.port_implemented" +Toggle 0to1 fme_csr_port2_offset_update.port_offset.port_implemented "logic fme_csr_port2_offset_update.port_offset.port_implemented" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset_update.port_offset.bar_id "logic fme_csr_port2_offset_update.port_offset.bar_id[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset_reset.port_offset.port_byte_offset "logic fme_csr_port2_offset_reset.port_offset.port_byte_offset[23:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset_update.port_offset.port_byte_offset "logic fme_csr_port3_offset_update.port_offset.port_byte_offset[23:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.ras_catfat_error.pcie_poison_error "logic fme_csr_ras_catfat_error_update.ras_catfat_error.pcie_poison_error" +Toggle 0to1 fme_csr_ras_catfat_error_update.ras_catfat_error.pcie_poison_error "logic fme_csr_ras_catfat_error_update.ras_catfat_error.pcie_poison_error" +Toggle 1to0 fme_csr_ras_catfat_error_update.ras_catfat_error.fabric_fatal_error "logic fme_csr_ras_catfat_error_update.ras_catfat_error.fabric_fatal_error" +Toggle 0to1 fme_csr_ras_catfat_error_update.ras_catfat_error.fabric_fatal_error "logic fme_csr_ras_catfat_error_update.ras_catfat_error.fabric_fatal_error" +Toggle 1to0 fme_csr_ras_catfat_error_reset.ras_catfat_error.pcie_poison_error "logic fme_csr_ras_catfat_error_reset.ras_catfat_error.pcie_poison_error" +Toggle 0to1 fme_csr_ras_catfat_error_reset.ras_catfat_error.pcie_poison_error "logic fme_csr_ras_catfat_error_reset.ras_catfat_error.pcie_poison_error" +Toggle 1to0 fme_csr_ras_catfat_error_reset.ras_catfat_error.fabric_fatal_error "logic fme_csr_ras_catfat_error_reset.ras_catfat_error.fabric_fatal_error" +Toggle 0to1 fme_csr_ras_catfat_error_reset.ras_catfat_error.fabric_fatal_error "logic fme_csr_ras_catfat_error_reset.ras_catfat_error.fabric_fatal_error" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_catfat_error_update.word.upper32 "logic fme_csr_ras_catfat_error_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.ras_nofat_error.pcie_error "logic fme_csr_ras_nofat_error_update.ras_nofat_error.pcie_error" +Toggle 0to1 fme_csr_ras_nofat_error_update.ras_nofat_error.pcie_error "logic fme_csr_ras_nofat_error_update.ras_nofat_error.pcie_error" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_therm_mngm_dfh_reset.word.lower32 "logic fme_csr_therm_mngm_dfh_reset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_therm_mngm_dfh_reset.dfh.next_dfh_offset "logic fme_csr_therm_mngm_dfh_reset.dfh.next_dfh_offset[23:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_therm_mngm_dfh_reset.dfh.feature_type "logic fme_csr_therm_mngm_dfh_reset.dfh.feature_type[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_therm_mngm_dfh_reset.dfh.feature_rev "logic fme_csr_therm_mngm_dfh_reset.dfh.feature_rev[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_therm_mngm_dfh_reset.dfh.feature_id "logic fme_csr_therm_mngm_dfh_reset.dfh.feature_id[11:0]" +Toggle 1to0 fme_csr_therm_mngm_dfh_reset.dfh.end_of_list "logic fme_csr_therm_mngm_dfh_reset.dfh.end_of_list" +Toggle 0to1 fme_csr_therm_mngm_dfh_reset.dfh.end_of_list "logic fme_csr_therm_mngm_dfh_reset.dfh.end_of_list" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_therm_mngm_dfh_reset.data "logic fme_csr_therm_mngm_dfh_reset.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_therm_mngm_dfh_reset.word.upper32 "logic fme_csr_therm_mngm_dfh_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_tmp_rdsensor_fmt1_update.word.lower32 "logic fme_csr_tmp_rdsensor_fmt1_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_rdsensor_fmt1_update.tmp_rdsensor_fmt1.temp_valid "logic fme_csr_tmp_rdsensor_fmt1_update.tmp_rdsensor_fmt1.temp_valid" +Toggle 0to1 fme_csr_tmp_rdsensor_fmt1_update.tmp_rdsensor_fmt1.temp_valid "logic fme_csr_tmp_rdsensor_fmt1_update.tmp_rdsensor_fmt1.temp_valid" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_tmp_rdsensor_fmt1_update.tmp_rdsensor_fmt1.temp_thermal_sensor "logic fme_csr_tmp_rdsensor_fmt1_update.tmp_rdsensor_fmt1.temp_thermal_sensor[9:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_tmp_rdsensor_fmt1_update.tmp_rdsensor_fmt1.numb_temp_reads "logic fme_csr_tmp_rdsensor_fmt1_update.tmp_rdsensor_fmt1.numb_temp_reads[15:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_tmp_rdsensor_fmt1_update.tmp_rdsensor_fmt1.fpga_temp "logic fme_csr_tmp_rdsensor_fmt1_update.tmp_rdsensor_fmt1.fpga_temp[6:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_tmp_rdsensor_fmt1_update.data "logic fme_csr_tmp_rdsensor_fmt1_update.data[63:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_tmp_rdsensor_fmt1_reset.word.upper32 "logic fme_csr_tmp_rdsensor_fmt1_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_tmp_rdsensor_fmt1_reset.word.lower32 "logic fme_csr_tmp_rdsensor_fmt1_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_rdsensor_fmt1_reset.tmp_rdsensor_fmt1.temp_valid "logic fme_csr_tmp_rdsensor_fmt1_reset.tmp_rdsensor_fmt1.temp_valid" +Toggle 0to1 fme_csr_tmp_rdsensor_fmt1_reset.tmp_rdsensor_fmt1.temp_valid "logic fme_csr_tmp_rdsensor_fmt1_reset.tmp_rdsensor_fmt1.temp_valid" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_tmp_rdsensor_fmt1_reset.tmp_rdsensor_fmt1.temp_thermal_sensor "logic fme_csr_tmp_rdsensor_fmt1_reset.tmp_rdsensor_fmt1.temp_thermal_sensor[9:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_tmp_rdsensor_fmt1_reset.tmp_rdsensor_fmt1.numb_temp_reads "logic fme_csr_tmp_rdsensor_fmt1_reset.tmp_rdsensor_fmt1.numb_temp_reads[15:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_tmp_rdsensor_fmt1_reset.tmp_rdsensor_fmt1.fpga_temp "logic fme_csr_tmp_rdsensor_fmt1_reset.tmp_rdsensor_fmt1.fpga_temp[6:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_tmp_rdsensor_fmt1_reset.data "logic fme_csr_tmp_rdsensor_fmt1_reset.data[63:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_tmp_rdsensor_fmt1_update.word.upper32 "logic fme_csr_tmp_rdsensor_fmt1_update.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_therm_mngm_dfh_update.dfh.feature_type "logic fme_csr_therm_mngm_dfh_update.dfh.feature_type[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_therm_mngm_dfh_update.dfh.feature_id "logic fme_csr_therm_mngm_dfh_update.dfh.feature_id[11:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_therm_mngm_dfh_update.data "logic fme_csr_therm_mngm_dfh_update.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_therm_mngm_dfh_update.word.upper32 "logic fme_csr_therm_mngm_dfh_update.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_therm_mngm_dfh_update.word.lower32 "logic fme_csr_therm_mngm_dfh_update.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_therm_mngm_dfh_update.dfh.next_dfh_offset "logic fme_csr_therm_mngm_dfh_update.dfh.next_dfh_offset[23:0]" +Toggle 1to0 fme_csr_therm_mngm_dfh_update.dfh.end_of_list "logic fme_csr_therm_mngm_dfh_update.dfh.end_of_list" +Toggle 0to1 fme_csr_therm_mngm_dfh_update.dfh.end_of_list "logic fme_csr_therm_mngm_dfh_update.dfh.end_of_list" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_therm_mngm_dfh_update.dfh.feature_rev "logic fme_csr_therm_mngm_dfh_update.dfh.feature_rev[3:0]" +Toggle 1to0 fme_csr_tmp_threshold_update.tmp_threshold.threshold1_status "logic fme_csr_tmp_threshold_update.tmp_threshold.threshold1_status" +Toggle 0to1 fme_csr_tmp_threshold_update.tmp_threshold.threshold1_status "logic fme_csr_tmp_threshold_update.tmp_threshold.threshold1_status" +Toggle 1to0 fme_csr_tmp_threshold_update.tmp_threshold.therm_trip_status "logic fme_csr_tmp_threshold_update.tmp_threshold.therm_trip_status" +Toggle 0to1 fme_csr_tmp_threshold_update.tmp_threshold.therm_trip_status "logic fme_csr_tmp_threshold_update.tmp_threshold.therm_trip_status" +Toggle 1to0 fme_csr_tmp_threshold_reset.tmp_threshold.threshold2_status "logic fme_csr_tmp_threshold_reset.tmp_threshold.threshold2_status" +Toggle 0to1 fme_csr_tmp_threshold_reset.tmp_threshold.threshold2_status "logic fme_csr_tmp_threshold_reset.tmp_threshold.threshold2_status" +Toggle 1to0 fme_csr_tmp_threshold_reset.tmp_threshold.threshold1_status "logic fme_csr_tmp_threshold_reset.tmp_threshold.threshold1_status" +Toggle 0to1 fme_csr_tmp_threshold_reset.tmp_threshold.threshold1_status "logic fme_csr_tmp_threshold_reset.tmp_threshold.threshold1_status" +Toggle 1to0 fme_csr_tmp_threshold_reset.tmp_threshold.therm_trip_status "logic fme_csr_tmp_threshold_reset.tmp_threshold.therm_trip_status" +Toggle 0to1 fme_csr_tmp_threshold_reset.tmp_threshold.therm_trip_status "logic fme_csr_tmp_threshold_reset.tmp_threshold.therm_trip_status" +Toggle 1to0 fme_csr_tmp_threshold_update.tmp_threshold.threshold2_status "logic fme_csr_tmp_threshold_update.tmp_threshold.threshold2_status" +Toggle 0to1 fme_csr_tmp_threshold_update.tmp_threshold.threshold2_status "logic fme_csr_tmp_threshold_update.tmp_threshold.threshold2_status" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [62] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [62] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [61] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [61] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [60] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [60] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [59] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [59] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [58] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [58] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [57] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [57] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [56] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [56] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [55] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [55] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [54] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [54] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [53] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [53] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [52] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [52] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [51] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [51] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [50] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [50] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [49] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [49] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [48] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [48] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [47] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [47] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [46] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [46] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [45] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [45] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [44] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [44] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [43] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [43] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [42] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [42] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [41] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [41] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [40] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [40] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [39] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [39] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [38] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [38] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [37] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [37] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [36] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [36] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [35] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [35] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [34] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [34] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [33] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [33] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [32] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [32] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [31] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [31] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [30] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [30] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [29] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [29] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [28] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [28] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [27] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [27] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [26] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [26] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [25] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [25] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [24] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [24] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [23] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [23] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [22] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [22] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [21] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [21] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [20] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [20] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [19] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [19] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [18] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [18] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [17] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [17] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [16] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [16] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [15] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [15] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [14] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [14] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [13] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [13] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [12] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [12] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [10] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [10] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [5] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [5] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [4] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [4] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [3] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [3] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [2] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [2] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [1] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [1] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [0] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [0] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.data [63] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.data [63] "logic fme_csr_ras_catfat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [62] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [62] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [61] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [61] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [60] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [60] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [59] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [59] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [58] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [58] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [57] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [57] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [56] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [56] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [55] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [55] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [54] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [54] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [53] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [53] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [52] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [52] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [51] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [51] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [50] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [50] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [49] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [49] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [48] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [48] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [47] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [47] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [46] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [46] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [45] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [45] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [44] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [44] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [43] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [43] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [42] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [42] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [41] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [41] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [40] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [40] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [39] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [39] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [38] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [38] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [37] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [37] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [36] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [36] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [35] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [35] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [34] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [34] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [33] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [33] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [32] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [32] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [31] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [31] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [30] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [30] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [29] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [29] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [28] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [28] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [27] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [27] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [26] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [26] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [25] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [25] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [24] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [24] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [23] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [23] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [22] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [22] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [21] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [21] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [15] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [15] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [14] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [14] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [13] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [13] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [12] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [12] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [11] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [11] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [10] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [10] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [9] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [9] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [7] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [7] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [6] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [6] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [5] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [5] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [4] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [4] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [3] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [3] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [2] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [2] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [1] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [1] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [0] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [0] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.data [63] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.data [63] "logic fme_csr_fpmon_fab_ctl.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [3] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [3] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [2] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [2] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [63] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [63] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [62] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [62] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [61] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [61] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [60] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [60] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [59] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [59] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [58] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [58] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [57] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [57] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [56] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [56] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [55] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [55] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [54] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [54] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [53] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [53] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [52] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [52] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [51] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [51] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [50] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [50] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [49] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [49] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [48] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [48] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [47] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [47] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [46] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [46] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [45] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [45] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [44] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [44] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [43] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [43] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [42] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [42] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [41] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [41] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [40] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [40] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [39] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [39] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [38] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [38] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [37] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [37] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [36] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [36] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [35] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [35] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [34] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [34] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [33] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [33] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [32] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [32] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [31] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [31] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [30] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [30] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [29] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [29] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [28] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [28] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [27] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [27] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [26] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [26] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [25] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [25] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [24] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [24] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [23] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [23] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [22] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [22] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [21] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [21] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [20] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [20] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [19] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [19] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [18] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [18] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [17] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [17] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [16] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [16] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [15] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [15] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [14] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [14] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [13] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [13] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [12] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [12] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [11] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [11] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [10] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [10] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [9] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [9] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [8] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [8] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [7] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [7] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [6] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [6] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_fme_error_mask0.data [4] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 0to1 fme_csr_fme_error_mask0.data [4] "logic fme_csr_fme_error_mask0.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [62] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [62] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [61] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [61] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [60] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [60] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [59] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [59] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [58] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [58] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [57] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [57] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [56] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [56] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [55] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [55] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [54] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [54] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [53] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [53] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [52] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [52] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [51] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [51] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [50] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [50] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [49] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [49] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [48] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [48] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [47] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [47] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [46] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [46] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [45] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [45] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [44] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [44] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [43] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [43] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [42] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [42] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [41] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [41] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [40] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [40] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [39] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [39] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [38] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [38] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [37] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [37] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [36] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [36] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [35] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [35] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [34] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [34] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [33] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [33] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [32] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [32] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [31] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [31] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [30] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [30] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [29] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [29] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [28] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [28] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [27] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [27] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [26] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [26] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [25] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [25] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [24] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [24] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [23] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [23] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [22] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [22] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [21] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [21] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [20] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [20] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [19] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [19] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [18] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [18] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [17] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [17] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [16] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [16] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [15] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [15] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [14] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [14] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [13] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [13] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [12] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [12] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [11] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [11] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [10] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [10] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [9] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [9] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [8] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [8] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [7] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [7] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [4] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [4] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [1] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [1] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [0] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [0] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.data [63] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.data [63] "logic fme_csr_ras_nofat_error_mask.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.ver_minor [2] "logic fme_csr_bitstream_id_update.bitstream_id.ver_minor[3:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.ver_minor [2] "logic fme_csr_bitstream_id_update.bitstream_id.ver_minor[3:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.ver_minor [1] "logic fme_csr_bitstream_id_update.bitstream_id.ver_minor[3:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.ver_minor [1] "logic fme_csr_bitstream_id_update.bitstream_id.ver_minor[3:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.ver_minor [3] "logic fme_csr_bitstream_id_update.bitstream_id.ver_minor[3:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.ver_minor [3] "logic fme_csr_bitstream_id_update.bitstream_id.ver_minor[3:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.ver_patch [2] "logic fme_csr_bitstream_id_reset.bitstream_id.ver_patch[3:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.ver_patch [2] "logic fme_csr_bitstream_id_reset.bitstream_id.ver_patch[3:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.ver_patch [0] "logic fme_csr_bitstream_id_reset.bitstream_id.ver_patch[3:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.ver_patch [0] "logic fme_csr_bitstream_id_reset.bitstream_id.ver_patch[3:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.ver_patch [3] "logic fme_csr_bitstream_id_reset.bitstream_id.ver_patch[3:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.ver_patch [3] "logic fme_csr_bitstream_id_reset.bitstream_id.ver_patch[3:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.ver_minor [2] "logic fme_csr_bitstream_id_reset.bitstream_id.ver_minor[3:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.ver_minor [2] "logic fme_csr_bitstream_id_reset.bitstream_id.ver_minor[3:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.ver_minor [1] "logic fme_csr_bitstream_id_reset.bitstream_id.ver_minor[3:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.ver_minor [1] "logic fme_csr_bitstream_id_reset.bitstream_id.ver_minor[3:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.ver_minor [3] "logic fme_csr_bitstream_id_reset.bitstream_id.ver_minor[3:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.ver_minor [3] "logic fme_csr_bitstream_id_reset.bitstream_id.ver_minor[3:0]" +Toggle 1to0 fme_csr_port3_offset.data [62] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [62] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [61] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [61] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [60] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [60] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [59] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [59] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [58] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [58] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [57] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [57] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [54] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [54] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [53] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [53] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [52] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [52] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [51] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [51] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [50] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [50] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [49] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [49] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [48] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [48] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [47] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [47] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [46] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [46] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [45] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [45] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [44] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [44] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [43] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [43] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [42] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [42] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [41] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [41] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [40] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [40] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [39] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [39] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [38] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [38] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [37] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [37] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [36] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [36] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [35] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [35] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [34] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [34] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [33] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [33] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [32] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [32] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [31] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [31] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [30] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [30] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [29] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [29] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [28] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [28] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [27] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [27] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [26] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [26] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [25] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [25] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [24] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [24] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [23] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [23] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [22] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [22] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [21] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [21] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [20] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [20] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [19] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [19] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [18] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [18] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [17] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [17] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [16] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [16] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [15] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [15] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [14] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [14] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [13] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [13] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [12] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [12] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [11] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [11] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [10] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [10] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [9] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [9] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [8] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [8] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [7] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [7] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [6] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [6] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [5] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [5] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [4] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [4] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [3] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [3] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [2] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [2] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [1] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [1] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [0] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [0] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port3_offset.data [63] "logic fme_csr_port3_offset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset.data [63] "logic fme_csr_port3_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [62] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [62] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [61] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [61] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [60] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [60] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [59] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [59] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [58] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [58] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [57] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [57] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [54] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [54] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [53] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [53] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [52] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [52] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [51] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [51] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [50] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [50] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [49] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [49] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [48] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [48] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [47] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [47] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [46] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [46] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [45] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [45] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [44] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [44] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [43] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [43] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [42] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [42] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [41] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [41] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [40] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [40] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [39] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [39] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [38] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [38] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [37] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [37] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [36] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [36] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [35] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [35] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [34] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [34] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [33] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [33] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [32] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [32] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [31] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [31] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [30] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [30] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [29] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [29] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [28] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [28] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [27] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [27] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [26] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [26] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [25] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [25] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [24] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [24] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [23] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [23] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [22] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [22] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [21] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [21] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [20] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [20] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [19] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [19] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [18] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [18] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [17] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [17] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [16] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [16] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [15] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [15] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [14] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [14] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [13] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [13] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [12] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [12] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [11] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [11] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [10] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [10] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [9] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [9] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [8] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [8] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [7] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [7] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [6] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [6] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [5] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [5] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [4] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [4] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [3] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [3] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [2] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [2] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [1] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [1] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [0] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [0] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port2_offset.data [63] "logic fme_csr_port2_offset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset.data [63] "logic fme_csr_port2_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [62] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [62] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [61] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [61] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [60] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [60] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [59] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [59] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [58] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [58] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [57] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [57] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [54] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [54] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [53] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [53] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [52] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [52] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [51] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [51] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [50] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [50] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [49] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [49] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [48] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [48] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [47] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [47] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [46] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [46] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [45] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [45] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [44] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [44] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [43] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [43] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [42] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [42] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [41] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [41] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [40] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [40] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [39] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [39] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [38] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [38] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [37] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [37] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [36] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [36] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [35] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [35] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [34] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [34] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [33] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [33] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [32] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [32] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [31] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [31] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [30] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [30] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [29] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [29] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [28] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [28] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [27] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [27] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [26] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [26] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [25] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [25] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [24] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [24] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [23] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [23] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [22] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [22] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [21] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [21] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [20] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [20] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [19] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [19] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [18] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [18] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [17] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [17] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [16] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [16] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [15] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [15] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [14] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [14] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [13] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [13] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [12] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [12] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [11] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [11] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [10] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [10] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [9] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [9] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [8] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [8] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [7] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [7] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [6] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [6] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [5] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [5] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [4] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [4] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [3] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [3] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [2] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [2] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [1] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [1] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [0] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [0] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.data [63] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset.data [63] "logic fme_csr_port1_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [62] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [62] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [61] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [61] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [60] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [60] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [59] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [59] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [58] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [58] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [57] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [57] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [54] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [54] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [53] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [53] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [52] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [52] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [51] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [51] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [50] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [50] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [49] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [49] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [48] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [48] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [47] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [47] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [46] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [46] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [45] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [45] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [44] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [44] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [43] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [43] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [42] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [42] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [41] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [41] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [40] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [40] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [39] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [39] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [38] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [38] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [37] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [37] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [36] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [36] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [35] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [35] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [34] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [34] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [33] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [33] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [32] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [32] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [31] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [31] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [30] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [30] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [29] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [29] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [28] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [28] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [27] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [27] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [26] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [26] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [25] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [25] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [24] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [24] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [23] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [23] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [22] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [22] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [21] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [21] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [20] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [20] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [19] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [19] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [18] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [18] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [17] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [17] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [16] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [16] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [15] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [15] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [14] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [14] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [13] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [13] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [12] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [12] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [11] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [11] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [10] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [10] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [9] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [9] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [8] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [8] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [7] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [7] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [6] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [6] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [5] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [5] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [4] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [4] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [3] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [3] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [2] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [2] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [1] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [1] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [0] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [0] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [63] "logic fme_csr_port0_offset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset.data [63] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.ver_patch [2] "logic fme_csr_bitstream_id_update.bitstream_id.ver_patch[3:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.ver_patch [2] "logic fme_csr_bitstream_id_update.bitstream_id.ver_patch[3:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.ver_patch [0] "logic fme_csr_bitstream_id_update.bitstream_id.ver_patch[3:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.ver_patch [0] "logic fme_csr_bitstream_id_update.bitstream_id.ver_patch[3:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.ver_patch [3] "logic fme_csr_bitstream_id_update.bitstream_id.ver_patch[3:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.ver_patch [3] "logic fme_csr_bitstream_id_update.bitstream_id.ver_patch[3:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [30] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [30] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [29] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [29] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [28] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [28] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [27] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [27] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [26] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [26] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [25] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [25] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [24] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [24] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [23] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [23] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [22] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [22] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [21] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [21] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [20] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [20] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [19] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [19] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [18] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [18] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [17] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [17] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [16] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [16] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [15] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [15] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [14] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [14] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [13] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [13] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [12] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [12] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [10] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [10] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [5] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [5] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [4] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [4] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [3] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [3] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [2] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [2] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [1] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [1] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [0] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [0] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_mask.word.lower32 [31] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.word.lower32 [31] "logic fme_csr_ras_catfat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.fim_variant [5] "logic fme_csr_bitstream_id_update.bitstream_id.fim_variant[7:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.fim_variant [5] "logic fme_csr_bitstream_id_update.bitstream_id.fim_variant[7:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.fim_variant [4] "logic fme_csr_bitstream_id_update.bitstream_id.fim_variant[7:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.fim_variant [4] "logic fme_csr_bitstream_id_update.bitstream_id.fim_variant[7:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.fim_variant [3] "logic fme_csr_bitstream_id_update.bitstream_id.fim_variant[7:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.fim_variant [3] "logic fme_csr_bitstream_id_update.bitstream_id.fim_variant[7:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.fim_variant [1] "logic fme_csr_bitstream_id_update.bitstream_id.fim_variant[7:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.fim_variant [1] "logic fme_csr_bitstream_id_update.bitstream_id.fim_variant[7:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.fim_variant [7] "logic fme_csr_bitstream_id_update.bitstream_id.fim_variant[7:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.fim_variant [7] "logic fme_csr_bitstream_id_update.bitstream_id.fim_variant[7:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [30] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.upper32 [30] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [29] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.upper32 [29] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [28] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.upper32 [28] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [27] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.upper32 [27] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [26] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.upper32 [26] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [25] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.upper32 [25] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [23] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.upper32 [23] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [22] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.upper32 [22] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [20] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.upper32 [20] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [19] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.upper32 [19] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [18] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.upper32 [18] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [15] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.upper32 [15] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [13] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.upper32 [13] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [12] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.upper32 [12] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [11] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.upper32 [11] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [9] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.upper32 [9] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [7] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.upper32 [7] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [4] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.upper32 [4] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [3] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.upper32 [3] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [31] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.upper32 [31] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.fim_variant [5] "logic fme_csr_bitstream_id_reset.bitstream_id.fim_variant[7:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.fim_variant [5] "logic fme_csr_bitstream_id_reset.bitstream_id.fim_variant[7:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.fim_variant [4] "logic fme_csr_bitstream_id_reset.bitstream_id.fim_variant[7:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.fim_variant [4] "logic fme_csr_bitstream_id_reset.bitstream_id.fim_variant[7:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.fim_variant [3] "logic fme_csr_bitstream_id_reset.bitstream_id.fim_variant[7:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.fim_variant [3] "logic fme_csr_bitstream_id_reset.bitstream_id.fim_variant[7:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.fim_variant [1] "logic fme_csr_bitstream_id_reset.bitstream_id.fim_variant[7:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.fim_variant [1] "logic fme_csr_bitstream_id_reset.bitstream_id.fim_variant[7:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.fim_variant [7] "logic fme_csr_bitstream_id_reset.bitstream_id.fim_variant[7:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.fim_variant [7] "logic fme_csr_bitstream_id_reset.bitstream_id.fim_variant[7:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [30] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.upper32 [30] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [29] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.upper32 [29] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [28] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.upper32 [28] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [27] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.upper32 [27] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [26] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.upper32 [26] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [25] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.upper32 [25] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [23] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.upper32 [23] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [22] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.upper32 [22] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [20] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.upper32 [20] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [19] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.upper32 [19] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [18] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.upper32 [18] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [15] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.upper32 [15] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [13] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.upper32 [13] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [12] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.upper32 [12] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [11] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.upper32 [11] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [9] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.upper32 [9] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [7] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.upper32 [7] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [4] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.upper32 [4] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [3] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.upper32 [3] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [31] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.upper32 [31] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [62] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [62] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [61] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [61] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [60] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [60] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [59] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [59] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [58] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [58] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [57] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [57] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [56] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [56] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [55] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [55] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [54] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [54] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [53] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [53] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [52] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [52] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [51] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [51] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [50] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [50] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [49] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [49] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [48] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [48] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [47] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [47] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [46] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [46] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [45] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [45] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [44] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [44] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [43] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [43] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [42] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [42] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [41] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [41] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [40] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [40] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [39] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [39] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [38] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [38] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [37] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [37] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [36] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [36] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [35] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [35] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [34] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [34] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [33] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [33] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [32] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [32] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [31] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [31] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [30] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [30] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [29] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [29] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [28] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [28] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [27] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [27] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [26] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [26] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [25] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [25] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [24] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [24] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [23] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [23] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [22] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [22] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [21] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [21] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [20] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [20] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [19] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [19] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [18] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [18] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [17] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [17] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [16] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [16] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [15] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [15] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [14] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [14] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [13] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [13] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.data [63] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.data [63] "logic fme_csr_pcie0_error_mask.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [62] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [62] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [61] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [61] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [60] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [60] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [59] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [59] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [58] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [58] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [57] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [57] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [56] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [56] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [55] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [55] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [54] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [54] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [53] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [53] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [52] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [52] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [51] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [51] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [50] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [50] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [49] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [49] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [48] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [48] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [47] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [47] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [46] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [46] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [45] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [45] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [43] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [43] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [42] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [42] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [40] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [40] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [39] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [39] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [38] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [38] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [37] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [37] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [36] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [36] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [35] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [35] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [34] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [34] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [33] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [33] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [32] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [32] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [31] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [31] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [23] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [23] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [22] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [22] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [21] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [21] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [20] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [20] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [19] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [19] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [18] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [18] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [17] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [17] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [16] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [16] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_tmp_threshold.data [63] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [63] "logic fme_csr_tmp_threshold.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_bitstream_id_reset.bitstream_id.reserved36 "logic fme_csr_bitstream_id_reset.bitstream_id.reserved36[3:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.ver_debug [2] "logic fme_csr_bitstream_id_reset.bitstream_id.ver_debug[3:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.ver_debug [2] "logic fme_csr_bitstream_id_reset.bitstream_id.ver_debug[3:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.ver_debug [3] "logic fme_csr_bitstream_id_reset.bitstream_id.ver_debug[3:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.ver_debug [3] "logic fme_csr_bitstream_id_reset.bitstream_id.ver_debug[3:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [60] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [60] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [58] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [58] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [56] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [56] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [54] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [54] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [52] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [52] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [50] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [50] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [48] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [48] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [46] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [46] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [44] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [44] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [42] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [42] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [40] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [40] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [38] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [38] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [36] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [36] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [34] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [34] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [32] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [32] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [30] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [30] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [28] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [28] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [26] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [26] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [24] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [24] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [22] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [22] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [20] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [20] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [18] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [18] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [16] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [16] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [14] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [14] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [12] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [12] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [10] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [10] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [8] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [8] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [6] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [6] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [4] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [4] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [2] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [2] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [0] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [0] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [62] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_update.data [62] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_year [4] "logic fme_csr_bitstream_md_update.bitstream_md.synth_year[7:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.synth_year [4] "logic fme_csr_bitstream_md_update.bitstream_md.synth_year[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_year [2] "logic fme_csr_bitstream_md_update.bitstream_md.synth_year[7:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.synth_year [2] "logic fme_csr_bitstream_md_update.bitstream_md.synth_year[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_year [0] "logic fme_csr_bitstream_md_update.bitstream_md.synth_year[7:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.synth_year [0] "logic fme_csr_bitstream_md_update.bitstream_md.synth_year[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_year [6] "logic fme_csr_bitstream_md_update.bitstream_md.synth_year[7:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.synth_year [6] "logic fme_csr_bitstream_md_update.bitstream_md.synth_year[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_seed [0] "logic fme_csr_bitstream_md_update.bitstream_md.synth_seed[3:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.synth_seed [0] "logic fme_csr_bitstream_md_update.bitstream_md.synth_seed[3:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_seed [2] "logic fme_csr_bitstream_md_update.bitstream_md.synth_seed[3:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.synth_seed [2] "logic fme_csr_bitstream_md_update.bitstream_md.synth_seed[3:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_month [4] "logic fme_csr_bitstream_md_update.bitstream_md.synth_month[7:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.synth_month [4] "logic fme_csr_bitstream_md_update.bitstream_md.synth_month[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_month [2] "logic fme_csr_bitstream_md_update.bitstream_md.synth_month[7:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.synth_month [2] "logic fme_csr_bitstream_md_update.bitstream_md.synth_month[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_month [0] "logic fme_csr_bitstream_md_update.bitstream_md.synth_month[7:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.synth_month [0] "logic fme_csr_bitstream_md_update.bitstream_md.synth_month[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_month [6] "logic fme_csr_bitstream_md_update.bitstream_md.synth_month[7:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.synth_month [6] "logic fme_csr_bitstream_md_update.bitstream_md.synth_month[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_day [4] "logic fme_csr_bitstream_md_update.bitstream_md.synth_day[7:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.synth_day [4] "logic fme_csr_bitstream_md_update.bitstream_md.synth_day[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_day [2] "logic fme_csr_bitstream_md_update.bitstream_md.synth_day[7:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.synth_day [2] "logic fme_csr_bitstream_md_update.bitstream_md.synth_day[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_day [0] "logic fme_csr_bitstream_md_update.bitstream_md.synth_day[7:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.synth_day [0] "logic fme_csr_bitstream_md_update.bitstream_md.synth_day[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_day [6] "logic fme_csr_bitstream_md_update.bitstream_md.synth_day[7:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.synth_day [6] "logic fme_csr_bitstream_md_update.bitstream_md.synth_day[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [32] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [32] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [30] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [30] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [28] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [28] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [26] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [26] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [24] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [24] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [22] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [22] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [20] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [20] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [18] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [18] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [16] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [16] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [14] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [14] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [12] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [12] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [10] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [10] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [8] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [8] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [6] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [6] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [4] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [4] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [2] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [2] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [0] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [0] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [34] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [34] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [28] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.upper32 [28] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [26] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.upper32 [26] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [24] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.upper32 [24] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [22] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.upper32 [22] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [20] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.upper32 [20] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [18] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.upper32 [18] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [16] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.upper32 [16] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [14] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.upper32 [14] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [12] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.upper32 [12] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [10] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.upper32 [10] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [8] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.upper32 [8] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [6] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.upper32 [6] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [4] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.upper32 [4] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [2] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.upper32 [2] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [0] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.upper32 [0] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [30] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.upper32 [30] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [28] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.lower32 [28] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [26] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.lower32 [26] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [24] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.lower32 [24] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [22] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.lower32 [22] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [20] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.lower32 [20] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [18] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.lower32 [18] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [16] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.lower32 [16] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [14] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.lower32 [14] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [12] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.lower32 [12] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [10] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.lower32 [10] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [8] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.lower32 [8] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [6] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.lower32 [6] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [4] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.lower32 [4] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [2] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.lower32 [2] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [0] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.lower32 [0] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [30] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.word.lower32 [30] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [60] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [60] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [58] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [58] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [56] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [56] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [54] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [54] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [52] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [52] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [50] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [50] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [48] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [48] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [46] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [46] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [44] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [44] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [42] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [42] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [40] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [40] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [38] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [38] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [36] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [36] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [34] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [34] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [32] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [32] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [30] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [30] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [28] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [28] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [26] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [26] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [24] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [24] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [22] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [22] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [20] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [20] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [18] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [18] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [16] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [16] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [14] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [14] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [12] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [12] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [10] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [10] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [8] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [8] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [6] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [6] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [4] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [4] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [2] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [2] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [0] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [0] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [62] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.data [62] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_year [4] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_year[7:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.bitstream_md.synth_year [4] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_year[7:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_year [2] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_year[7:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.bitstream_md.synth_year [2] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_year[7:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_year [0] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_year[7:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.bitstream_md.synth_year [0] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_year[7:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_year [6] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_year[7:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.bitstream_md.synth_year [6] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_year[7:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_seed [0] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_seed[3:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.bitstream_md.synth_seed [0] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_seed[3:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_seed [2] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_seed[3:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.bitstream_md.synth_seed [2] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_seed[3:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_month [4] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_month[7:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.bitstream_md.synth_month [4] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_month[7:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_month [2] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_month[7:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.bitstream_md.synth_month [2] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_month[7:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_month [0] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_month[7:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.bitstream_md.synth_month [0] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_month[7:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_month [6] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_month[7:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.bitstream_md.synth_month [6] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_month[7:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_day [4] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_day[7:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.bitstream_md.synth_day [4] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_day[7:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_day [2] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_day[7:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.bitstream_md.synth_day [2] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_day[7:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_day [0] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_day[7:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.bitstream_md.synth_day [0] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_day[7:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_day [6] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_day[7:0]" +Toggle 0to1 fme_csr_bitstream_md_reset.bitstream_md.synth_day [6] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_day[7:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_bitstream_md_reset.bitstream_md.reserved28 "logic fme_csr_bitstream_md_reset.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [62] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [62] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [61] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [61] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [60] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [60] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [59] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [59] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [58] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [58] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [57] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [57] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [55] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [55] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [54] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [54] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [52] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [52] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [51] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [51] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [50] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [50] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [47] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [47] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [45] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [45] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [44] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [44] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [43] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [43] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [41] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [41] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [39] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [39] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [36] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [36] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [35] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [35] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [30] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [30] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [29] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [29] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [28] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [28] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [26] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [26] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [25] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [25] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [22] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [22] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [20] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [20] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [18] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [18] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [13] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [13] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [12] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [12] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [9] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [9] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [4] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [4] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [63] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_update.data [63] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.ver_debug [2] "logic fme_csr_bitstream_id_update.bitstream_id.ver_debug[3:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.ver_debug [2] "logic fme_csr_bitstream_id_update.bitstream_id.ver_debug[3:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.ver_debug [3] "logic fme_csr_bitstream_id_update.bitstream_id.ver_debug[3:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.ver_debug [3] "logic fme_csr_bitstream_id_update.bitstream_id.ver_debug[3:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.reserved36 [0] "logic fme_csr_bitstream_id_update.bitstream_id.reserved36[3:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.reserved36 [0] "logic fme_csr_bitstream_id_update.bitstream_id.reserved36[3:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.reserved36 [3] "logic fme_csr_bitstream_id_update.bitstream_id.reserved36[3:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.reserved36 [3] "logic fme_csr_bitstream_id_update.bitstream_id.reserved36[3:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [62] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [62] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [61] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [61] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [60] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [60] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [59] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [59] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [58] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [58] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [57] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [57] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [55] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [55] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [54] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [54] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [52] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [52] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [51] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [51] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [50] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [50] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [47] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [47] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [45] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [45] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [44] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [44] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [43] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [43] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [41] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [41] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [39] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [39] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [36] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [36] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [35] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [35] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [30] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [30] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [29] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [29] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [28] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [28] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [26] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [26] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [25] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [25] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [22] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [22] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [20] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [20] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [18] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [18] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [13] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [13] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [12] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [12] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [9] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [9] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [4] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [4] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [63] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.data [63] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [28] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.lower32 [28] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [26] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.lower32 [26] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [24] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.lower32 [24] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [22] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.lower32 [22] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [20] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.lower32 [20] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [18] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.lower32 [18] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [16] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.lower32 [16] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [14] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.lower32 [14] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [12] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.lower32 [12] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [10] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.lower32 [10] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [8] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.lower32 [8] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [6] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.lower32 [6] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [4] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.lower32 [4] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [2] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.lower32 [2] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [0] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.lower32 [0] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [30] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.lower32 [30] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [29] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.lower32 [29] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [28] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.lower32 [28] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [26] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.lower32 [26] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [25] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.lower32 [25] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [22] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.lower32 [22] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [20] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.lower32 [20] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [18] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.lower32 [18] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [13] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.lower32 [13] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [12] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.lower32 [12] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [9] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.lower32 [9] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [4] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.lower32 [4] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [30] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.word.lower32 [30] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [29] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.git_hash [29] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [28] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.git_hash [28] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [26] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.git_hash [26] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [25] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.git_hash [25] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [22] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.git_hash [22] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [20] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.git_hash [20] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [18] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.git_hash [18] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [13] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.git_hash [13] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [12] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.git_hash [12] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [9] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.git_hash [9] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [4] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.git_hash [4] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [30] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.git_hash [30] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [29] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.lower32 [29] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [28] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.lower32 [28] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [26] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.lower32 [26] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [25] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.lower32 [25] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [22] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.lower32 [22] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [20] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.lower32 [20] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [18] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.lower32 [18] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [13] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.lower32 [13] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [12] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.lower32 [12] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [9] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.lower32 [9] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [4] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.lower32 [4] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [30] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.word.lower32 [30] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [29] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.git_hash [29] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [28] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.git_hash [28] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [26] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.git_hash [26] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [25] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.git_hash [25] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [22] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.git_hash [22] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [20] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.git_hash [20] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [18] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.git_hash [18] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [13] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.git_hash [13] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [12] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.git_hash [12] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [9] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.git_hash [9] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [4] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.git_hash [4] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [30] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.git_hash [30] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [28] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.upper32 [28] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [26] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.upper32 [26] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [24] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.upper32 [24] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [22] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.upper32 [22] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [20] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.upper32 [20] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [18] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.upper32 [18] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [16] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.upper32 [16] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [14] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.upper32 [14] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [12] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.upper32 [12] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [10] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.upper32 [10] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [8] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.upper32 [8] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [6] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.upper32 [6] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [4] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.upper32 [4] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [2] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.upper32 [2] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [0] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.upper32 [0] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [30] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_bitstream_md_update.word.upper32 [30] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.hssi_id [3] "logic fme_csr_bitstream_id_reset.bitstream_id.hssi_id[3:0]" +Toggle 0to1 fme_csr_bitstream_id_reset.bitstream_id.hssi_id [3] "logic fme_csr_bitstream_id_reset.bitstream_id.hssi_id[3:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.hssi_id [3] "logic fme_csr_bitstream_id_update.bitstream_id.hssi_id[3:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.hssi_id [3] "logic fme_csr_bitstream_id_update.bitstream_id.hssi_id[3:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [31] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [1] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [3] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [5] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [7] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [9] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [11] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [13] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [15] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [17] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [19] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [21] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [23] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [25] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [27] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.upper32 [29] "logic fme_csr_bitstream_md_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [63] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [1] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [3] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [5] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [7] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [9] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [11] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [13] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [15] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [17] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [19] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [21] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [23] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [25] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [27] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [29] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [31] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [33] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [35] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [37] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [39] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [41] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [43] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [45] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [47] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [49] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [51] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [53] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [55] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [57] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [59] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.data [61] "logic fme_csr_bitstream_md_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [31] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [1] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [3] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [5] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [7] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [9] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [11] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [13] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [15] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [17] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [19] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [21] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [23] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [25] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [27] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.lower32 [29] "logic fme_csr_bitstream_md_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [31] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [1] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [3] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [5] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [7] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [9] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [11] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [13] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [15] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [17] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [19] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [21] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [23] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [25] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [27] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.word.upper32 [29] "logic fme_csr_bitstream_md_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_day [7] "logic fme_csr_bitstream_md_update.bitstream_md.synth_day[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_day [1] "logic fme_csr_bitstream_md_update.bitstream_md.synth_day[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_day [3] "logic fme_csr_bitstream_md_update.bitstream_md.synth_day[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_day [5] "logic fme_csr_bitstream_md_update.bitstream_md.synth_day[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_month [7] "logic fme_csr_bitstream_md_update.bitstream_md.synth_month[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_month [1] "logic fme_csr_bitstream_md_update.bitstream_md.synth_month[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_month [3] "logic fme_csr_bitstream_md_update.bitstream_md.synth_month[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_month [5] "logic fme_csr_bitstream_md_update.bitstream_md.synth_month[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_seed [3] "logic fme_csr_bitstream_md_update.bitstream_md.synth_seed[3:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_seed [1] "logic fme_csr_bitstream_md_update.bitstream_md.synth_seed[3:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_year [7] "logic fme_csr_bitstream_md_update.bitstream_md.synth_year[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_year [1] "logic fme_csr_bitstream_md_update.bitstream_md.synth_year[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_year [3] "logic fme_csr_bitstream_md_update.bitstream_md.synth_year[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.synth_year [5] "logic fme_csr_bitstream_md_update.bitstream_md.synth_year[7:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [63] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [1] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [3] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [5] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [7] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [9] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [11] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [13] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [15] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [17] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [19] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [21] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [23] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [25] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [27] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [29] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [31] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [33] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [35] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [37] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [39] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [41] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [43] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [45] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [47] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [49] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [51] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [53] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [55] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [57] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [59] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.data [61] "logic fme_csr_bitstream_md_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [27] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [1] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [3] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [5] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [7] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [9] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [11] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [13] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [15] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [17] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [19] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [21] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [23] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [25] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [31] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_update.word.lower32 [29] "logic fme_csr_bitstream_md_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_year [7] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_year[7:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_year [1] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_year[7:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_year [3] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_year[7:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_year [5] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_year[7:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [56] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [0] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [1] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [2] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [3] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [5] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [6] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [7] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [8] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [10] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [11] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [14] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [15] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [16] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [17] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [19] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [21] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [23] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [24] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [27] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [31] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [32] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [33] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [34] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [37] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [38] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [40] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [42] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [46] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [48] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [49] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.data [53] "logic fme_csr_bitstream_id_reset.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [31] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [0] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [1] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [2] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [3] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [5] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [6] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [7] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [8] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [10] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [11] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [14] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [15] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [16] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [17] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [19] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [21] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [23] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [24] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.lower32 [27] "logic fme_csr_bitstream_id_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [24] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [0] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [1] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [2] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [5] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [6] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [8] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [10] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [14] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [16] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [17] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.word.upper32 [21] "logic fme_csr_bitstream_id_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.fim_variant [6] "logic fme_csr_bitstream_id_update.bitstream_id.fim_variant[7:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.fim_variant [0] "logic fme_csr_bitstream_id_update.bitstream_id.fim_variant[7:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.fim_variant [2] "logic fme_csr_bitstream_id_update.bitstream_id.fim_variant[7:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [31] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [0] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [1] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [2] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [3] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [5] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [6] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [7] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [8] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [10] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [11] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [14] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [15] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [16] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [17] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [19] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [21] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [23] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [24] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.git_hash [27] "logic fme_csr_bitstream_id_update.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.hssi_id [2] "logic fme_csr_bitstream_id_update.bitstream_id.hssi_id[3:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.hssi_id [0] "logic fme_csr_bitstream_id_update.bitstream_id.hssi_id[3:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.hssi_id [1] "logic fme_csr_bitstream_id_update.bitstream_id.hssi_id[3:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.ver_debug [1] "logic fme_csr_bitstream_id_update.bitstream_id.ver_debug[3:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.ver_debug [0] "logic fme_csr_bitstream_id_update.bitstream_id.ver_debug[3:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.ver_minor [0] "logic fme_csr_bitstream_id_update.bitstream_id.ver_minor[3:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.ver_patch [1] "logic fme_csr_bitstream_id_update.bitstream_id.ver_patch[3:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [56] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [0] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [1] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [2] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [3] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [5] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [6] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [7] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [8] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [10] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [11] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [14] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [15] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [16] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [17] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [19] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [21] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [23] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [24] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [27] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [31] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [32] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [33] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [34] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [37] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [38] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [40] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [42] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [46] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [48] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [49] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.data [53] "logic fme_csr_bitstream_id_update.data[63:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [31] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [0] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [1] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [2] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [3] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [5] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [6] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [7] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [8] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [10] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [11] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [14] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [15] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [16] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [17] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [19] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [21] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [23] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [24] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.lower32 [27] "logic fme_csr_bitstream_id_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [24] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [0] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [1] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [2] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [5] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [6] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [8] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [10] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [14] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [16] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [17] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_id_update.word.upper32 [21] "logic fme_csr_bitstream_id_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_day [7] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_day[7:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_day [1] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_day[7:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_day [3] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_day[7:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_day [5] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_day[7:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_month [7] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_month[7:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_month [1] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_month[7:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_month [3] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_month[7:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_month [5] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_month[7:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_seed [3] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_seed[3:0]" +Toggle 1to0 fme_csr_bitstream_md_reset.bitstream_md.synth_seed [1] "logic fme_csr_bitstream_md_reset.bitstream_md.synth_seed[3:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.ver_patch [1] "logic fme_csr_bitstream_id_reset.bitstream_id.ver_patch[3:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.fim_variant [6] "logic fme_csr_bitstream_id_reset.bitstream_id.fim_variant[7:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.fim_variant [0] "logic fme_csr_bitstream_id_reset.bitstream_id.fim_variant[7:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.fim_variant [2] "logic fme_csr_bitstream_id_reset.bitstream_id.fim_variant[7:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [31] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [0] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [1] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [2] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [3] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [5] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [6] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [7] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [8] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [10] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [11] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [14] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [15] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [16] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [17] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [19] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [21] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [23] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [24] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.git_hash [27] "logic fme_csr_bitstream_id_reset.bitstream_id.git_hash[31:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.hssi_id [2] "logic fme_csr_bitstream_id_reset.bitstream_id.hssi_id[3:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.hssi_id [0] "logic fme_csr_bitstream_id_reset.bitstream_id.hssi_id[3:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.hssi_id [1] "logic fme_csr_bitstream_id_reset.bitstream_id.hssi_id[3:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.ver_debug [1] "logic fme_csr_bitstream_id_reset.bitstream_id.ver_debug[3:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.ver_debug [0] "logic fme_csr_bitstream_id_reset.bitstream_id.ver_debug[3:0]" +Toggle 1to0 fme_csr_bitstream_id_reset.bitstream_id.ver_minor [0] "logic fme_csr_bitstream_id_reset.bitstream_id.ver_minor[3:0]" +Toggle 0to1 tmp_threshold_capability_attr.tmp_threshold_capability.disable_tmp_thresh_report [3] "logic tmp_threshold_capability_attr.tmp_threshold_capability.disable_tmp_thresh_report[3:0]" +Toggle 1to0 tmp_threshold_capability_attr.tmp_threshold_capability.disable_tmp_thresh_report [3] "logic tmp_threshold_capability_attr.tmp_threshold_capability.disable_tmp_thresh_report[3:0]" +Toggle 0to1 tmp_threshold_capability_attr.tmp_threshold_capability.disable_tmp_thresh_report [0] "logic tmp_threshold_capability_attr.tmp_threshold_capability.disable_tmp_thresh_report[3:0]" +Toggle 1to0 tmp_threshold_capability_attr.tmp_threshold_capability.disable_tmp_thresh_report [0] "logic tmp_threshold_capability_attr.tmp_threshold_capability.disable_tmp_thresh_report[3:0]" +Toggle 0to1 tmp_threshold_capability_attr.tmp_threshold_capability.disable_tmp_thresh_report [1] "logic tmp_threshold_capability_attr.tmp_threshold_capability.disable_tmp_thresh_report[3:0]" +Toggle 1to0 tmp_threshold_capability_attr.tmp_threshold_capability.disable_tmp_thresh_report [1] "logic tmp_threshold_capability_attr.tmp_threshold_capability.disable_tmp_thresh_report[3:0]" +Toggle 0to1 tmp_threshold_capability_attr.tmp_threshold_capability.disable_tmp_thresh_report [2] "logic tmp_threshold_capability_attr.tmp_threshold_capability.disable_tmp_thresh_report[3:0]" +Toggle 1to0 tmp_threshold_capability_attr.tmp_threshold_capability.disable_tmp_thresh_report [2] "logic tmp_threshold_capability_attr.tmp_threshold_capability.disable_tmp_thresh_report[3:0]" +Toggle 0to1 fme_csr_tmp_threshold.tmp_threshold.temp_threshold1 [6] "logic fme_csr_tmp_threshold.tmp_threshold.temp_threshold1[6:0]" +Toggle 0to1 fme_csr_tmp_threshold.tmp_threshold.temp_threshold1 [1] "logic fme_csr_tmp_threshold.tmp_threshold.temp_threshold1[6:0]" +Toggle 0to1 fme_csr_tmp_threshold.tmp_threshold.temp_threshold1 [3] "logic fme_csr_tmp_threshold.tmp_threshold.temp_threshold1[6:0]" +Toggle 0to1 fme_csr_tmp_threshold.tmp_threshold.temp_threshold1 [4] "logic fme_csr_tmp_threshold.tmp_threshold.temp_threshold1[6:0]" +Toggle 0to1 fme_csr_tmp_threshold.tmp_threshold.temp_threshold2 [6] "logic fme_csr_tmp_threshold.tmp_threshold.temp_threshold2[6:0]" +Toggle 0to1 fme_csr_tmp_threshold.tmp_threshold.temp_threshold2 [0] "logic fme_csr_tmp_threshold.tmp_threshold.temp_threshold2[6:0]" +Toggle 0to1 fme_csr_tmp_threshold.tmp_threshold.temp_threshold2 [1] "logic fme_csr_tmp_threshold.tmp_threshold.temp_threshold2[6:0]" +Toggle 0to1 fme_csr_tmp_threshold.tmp_threshold.temp_threshold2 [2] "logic fme_csr_tmp_threshold.tmp_threshold.temp_threshold2[6:0]" +Toggle 0to1 fme_csr_tmp_threshold.tmp_threshold.temp_threshold2 [3] "logic fme_csr_tmp_threshold.tmp_threshold.temp_threshold2[6:0]" +Toggle 0to1 fme_csr_tmp_threshold.tmp_threshold.temp_threshold2 [4] "logic fme_csr_tmp_threshold.tmp_threshold.temp_threshold2[6:0]" +Toggle 0to1 fme_csr_tmp_threshold.tmp_threshold.therm_trip_threshold [6] "logic fme_csr_tmp_threshold.tmp_threshold.therm_trip_threshold[6:0]" +Toggle 0to1 fme_csr_tmp_threshold.tmp_threshold.therm_trip_threshold [0] "logic fme_csr_tmp_threshold.tmp_threshold.therm_trip_threshold[6:0]" +Toggle 0to1 fme_csr_tmp_threshold.tmp_threshold.therm_trip_threshold [2] "logic fme_csr_tmp_threshold.tmp_threshold.therm_trip_threshold[6:0]" +Toggle 0to1 fme_csr_tmp_threshold.tmp_threshold.therm_trip_threshold [3] "logic fme_csr_tmp_threshold.tmp_threshold.therm_trip_threshold[6:0]" +Toggle 0to1 fme_csr_tmp_threshold.tmp_threshold.therm_trip_threshold [4] "logic fme_csr_tmp_threshold.tmp_threshold.therm_trip_threshold[6:0]" +Toggle 1to0 fme_csr_port1_offset.data [56] "logic fme_csr_port1_offset.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [30] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [1] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [3] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [4] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [6] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [8] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [9] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [10] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [11] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [12] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [14] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [24] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [26] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [27] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 0to1 fme_csr_tmp_threshold.data [28] "logic fme_csr_tmp_threshold.data[63:0]" +Toggle 1to0 fme_csr_port0_offset.data [55] "logic fme_csr_port0_offset.data[63:0]" +Toggle 1to0 fme_csr_port1_offset.port_offset.decouple_port_csr "logic fme_csr_port1_offset.port_offset.decouple_port_csr" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.reserved36 [1] "logic fme_csr_bitstream_id_update.bitstream_id.reserved36[3:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.reserved36 [1] "logic fme_csr_bitstream_id_update.bitstream_id.reserved36[3:0]" +Toggle 0to1 fme_csr_bitstream_id_update.bitstream_id.reserved36 [2] "logic fme_csr_bitstream_id_update.bitstream_id.reserved36[3:0]" +Toggle 1to0 fme_csr_bitstream_id_update.bitstream_id.reserved36 [2] "logic fme_csr_bitstream_id_update.bitstream_id.reserved36[3:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [1] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [1] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [35] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [35] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [33] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [33] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [31] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [31] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [29] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [29] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [27] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [27] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [25] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [25] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [23] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [23] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [21] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [21] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [19] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [19] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [17] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [17] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [15] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [15] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [13] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [13] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [11] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [11] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [9] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [9] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [7] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [7] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [5] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [5] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 0to1 fme_csr_bitstream_md_update.bitstream_md.reserved28 [3] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_bitstream_md_update.bitstream_md.reserved28 [3] "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +Toggle 1to0 fme_csr_port0_offset.port_offset.afu_access_ctrl "logic fme_csr_port0_offset.port_offset.afu_access_ctrl" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [30] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [30] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [16] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [16] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [17] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [17] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [18] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [18] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [19] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [19] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [20] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [20] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [21] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [21] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [22] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [22] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [23] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [23] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [31] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [31] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [1] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [1] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [3] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [3] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [4] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [4] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [6] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [6] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [8] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [8] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [9] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [9] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [10] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [10] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [11] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [11] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [12] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [12] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [14] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [14] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [24] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [24] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [26] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [26] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [27] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [27] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.lower32 [28] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.lower32 [28] "logic fme_csr_tmp_threshold.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [31] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [31] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [13] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [13] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [14] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [14] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [15] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [15] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [16] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [16] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [17] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [17] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [18] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [18] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [19] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [19] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [20] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [20] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [21] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [21] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [22] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [22] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [23] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [23] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [24] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [24] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [25] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [25] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [26] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [26] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [27] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [27] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [28] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [28] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [29] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [29] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_pcie0_error_mask.word.lower32 [30] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_pcie0_error_mask.word.lower32 [30] "logic fme_csr_pcie0_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [31] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [31] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [0] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [0] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [1] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [1] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [2] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [2] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [3] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [3] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [4] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [4] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [5] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [5] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [6] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [6] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [7] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [7] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [9] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [9] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [10] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [10] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [11] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [11] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [12] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [12] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [13] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [13] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [14] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [14] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [15] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [15] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [22] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [22] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [24] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [24] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [25] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [25] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [26] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [26] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [27] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [27] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [28] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [28] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [29] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [29] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.word.lower32 [30] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl.word.lower32 [30] "logic fme_csr_fpmon_fab_ctl.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [31] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [31] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [0] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [0] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [1] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [1] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [4] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [4] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [7] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [7] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [8] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [8] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [9] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [9] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [10] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [10] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [11] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [11] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [12] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [12] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [13] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [13] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [14] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [14] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [15] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [15] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [16] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [16] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [17] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [17] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [18] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [18] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [19] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [19] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [20] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [20] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [21] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [21] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [22] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [22] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [23] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [23] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [24] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [24] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [25] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [25] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [26] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [26] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [27] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [27] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [28] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [28] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [29] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [29] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.word.lower32 [30] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask.word.lower32 [30] "logic fme_csr_ras_nofat_error_mask.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [31] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [31] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [3] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [3] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [4] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [4] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [5] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [5] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [6] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [6] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [7] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [7] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [8] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [8] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [9] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [9] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [10] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [10] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [11] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [11] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [12] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [12] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [13] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [13] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [14] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [14] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [15] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [15] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [16] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [16] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [17] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [17] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [18] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [18] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [19] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [19] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [20] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [20] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [21] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [21] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [22] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [22] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [23] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [23] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [24] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [24] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [25] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [25] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [26] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [26] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [27] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [27] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [28] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [28] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [29] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [29] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj.word.lower32 [30] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj.word.lower32 [30] "logic fme_csr_ras_error_inj.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [4] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [4] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [6] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [6] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [7] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [7] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [8] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [8] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [9] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [9] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [10] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [10] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [11] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [11] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [12] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [12] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [13] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [13] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [14] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [14] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [15] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [15] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [16] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [16] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [17] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [17] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [18] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [18] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [19] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [19] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [20] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [20] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [21] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [21] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [22] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [22] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [23] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [23] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [24] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [24] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [25] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [25] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [26] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [26] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [27] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [27] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [28] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [28] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [29] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [29] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [30] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [30] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [31] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [31] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [2] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [2] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0.word.lower32 [3] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0.word.lower32 [3] "logic fme_csr_fme_error_mask0.word.lower32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [31] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [31] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [0] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [0] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [1] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [1] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [2] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [2] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [3] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [3] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [4] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [4] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [5] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [5] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [6] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [6] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [7] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [7] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [8] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [8] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [10] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [10] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [11] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [11] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [13] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [13] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [14] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [14] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [15] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [15] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [16] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [16] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [17] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [17] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [18] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [18] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [19] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [19] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [20] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [20] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [21] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [21] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [22] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [22] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [23] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [23] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [24] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [24] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [25] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [25] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [26] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [26] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [27] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [27] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [28] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [28] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [29] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [29] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_tmp_threshold.word.upper32 [30] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 1to0 fme_csr_tmp_threshold.word.upper32 [30] "logic fme_csr_tmp_threshold.word.upper32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [31] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [31] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [1] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [1] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [2] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [2] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [3] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [3] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [4] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [4] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [5] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [5] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [6] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [6] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [7] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [7] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [8] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [8] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [9] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [9] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [10] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [10] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [11] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [11] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [12] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [12] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [13] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [13] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [14] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [14] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [15] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [15] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [16] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [16] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [17] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [17] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [18] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [18] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [19] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [19] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [20] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [20] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [21] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [21] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [22] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [22] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [23] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [23] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [24] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [24] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [25] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [25] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [26] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [26] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [27] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [27] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [28] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [28] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [29] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [29] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_update.word.lower32 [30] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0_update.word.lower32 [30] "logic fme_csr_fme_error0_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [31] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [31] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [23] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [0] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [0] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [1] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [1] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [2] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [2] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [3] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [3] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [4] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [4] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [5] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [5] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [6] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [6] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [7] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [7] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [8] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [8] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [9] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [9] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [10] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [10] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [11] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [11] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [12] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [12] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [13] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [13] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [14] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [14] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [15] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [15] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [16] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [16] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [17] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [17] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [18] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [18] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [19] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [19] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [20] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [20] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [21] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [21] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [22] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [22] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [25] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [25] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [26] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [26] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [27] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [27] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [28] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [28] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [29] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [29] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port0_offset.word.upper32 [30] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port0_offset.word.upper32 [30] "logic fme_csr_port0_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [31] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [31] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [24] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [0] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [0] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [1] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [1] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [2] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [2] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [3] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [3] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [4] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [4] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [5] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [5] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [6] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [6] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [7] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [7] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [8] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [8] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [9] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [9] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [10] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [10] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [11] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [11] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [12] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [12] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [13] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [13] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [14] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [14] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [15] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [15] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [16] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [16] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [17] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [17] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [18] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [18] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [19] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [19] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [20] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [20] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [21] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [21] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [22] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [22] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [25] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [25] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [26] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [26] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [27] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [27] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [28] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [28] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [29] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [29] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port1_offset.word.upper32 [30] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port1_offset.word.upper32 [30] "logic fme_csr_port1_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [31] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [31] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [0] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [0] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [1] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [1] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [2] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [2] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [3] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [3] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [4] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [4] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [5] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [5] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [6] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [6] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [7] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [7] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [8] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [8] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [9] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [9] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [10] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [10] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [11] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [11] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [12] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [12] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [13] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [13] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [14] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [14] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [15] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [15] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [16] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [16] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [17] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [17] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [18] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [18] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [19] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [19] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [20] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [20] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [21] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [21] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [22] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [22] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [25] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [25] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [26] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [26] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [27] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [27] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [28] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [28] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [29] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [29] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port2_offset.word.upper32 [30] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port2_offset.word.upper32 [30] "logic fme_csr_port2_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [31] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [31] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [0] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [0] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [1] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [1] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [2] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [2] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [3] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [3] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [4] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [4] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [5] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [5] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [6] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [6] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [7] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [7] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [8] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [8] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [9] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [9] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [10] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [10] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [11] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [11] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [12] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [12] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [13] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [13] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [14] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [14] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [15] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [15] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [16] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [16] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [17] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [17] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [18] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [18] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [19] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [19] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [20] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [20] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [21] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [21] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [22] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [22] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [25] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [25] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [26] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [26] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [27] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [27] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [28] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [28] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [29] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [29] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_port3_offset.word.upper32 [30] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 1to0 fme_csr_port3_offset.word.upper32 [30] "logic fme_csr_port3_offset.word.upper32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [31] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [31] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [1] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [1] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [2] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [2] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [3] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [3] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [4] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [4] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [5] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [5] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [6] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [6] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [7] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [7] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [8] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [8] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [9] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [9] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [10] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [10] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [11] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [11] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [12] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [12] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [13] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [13] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [14] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [14] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [15] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [15] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [16] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [16] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [17] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [17] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [18] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [18] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [19] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [19] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [20] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [20] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [21] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [21] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [22] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [22] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [23] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [23] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [24] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [24] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [25] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [25] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [26] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [26] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [27] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [27] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [28] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [28] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [29] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [29] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0.word.lower32 [30] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error0.word.lower32 [30] "logic fme_csr_fme_error0.word.lower32[31:0]" +Toggle 0to1 tmp_threshold_attr.tmp_threshold.temp_threshold2_enable [3] "logic tmp_threshold_attr.tmp_threshold.temp_threshold2_enable[3:0]" +Toggle 1to0 tmp_threshold_attr.tmp_threshold.temp_threshold2_enable [3] "logic tmp_threshold_attr.tmp_threshold.temp_threshold2_enable[3:0]" +Toggle 0to1 tmp_threshold_attr.tmp_threshold.temp_threshold2_enable [0] "logic tmp_threshold_attr.tmp_threshold.temp_threshold2_enable[3:0]" +Toggle 1to0 tmp_threshold_attr.tmp_threshold.temp_threshold2_enable [0] "logic tmp_threshold_attr.tmp_threshold.temp_threshold2_enable[3:0]" +Toggle 0to1 tmp_threshold_attr.tmp_threshold.temp_threshold2_enable [1] "logic tmp_threshold_attr.tmp_threshold.temp_threshold2_enable[3:0]" +Toggle 1to0 tmp_threshold_attr.tmp_threshold.temp_threshold2_enable [1] "logic tmp_threshold_attr.tmp_threshold.temp_threshold2_enable[3:0]" +Toggle 0to1 tmp_threshold_attr.tmp_threshold.temp_threshold2_enable [2] "logic tmp_threshold_attr.tmp_threshold.temp_threshold2_enable[3:0]" +Toggle 1to0 tmp_threshold_attr.tmp_threshold.temp_threshold2_enable [2] "logic tmp_threshold_attr.tmp_threshold.temp_threshold2_enable[3:0]" +Toggle 0to1 tmp_threshold_attr.tmp_threshold.temp_threshold1_enable [3] "logic tmp_threshold_attr.tmp_threshold.temp_threshold1_enable[3:0]" +Toggle 1to0 tmp_threshold_attr.tmp_threshold.temp_threshold1_enable [3] "logic tmp_threshold_attr.tmp_threshold.temp_threshold1_enable[3:0]" +Toggle 0to1 tmp_threshold_attr.tmp_threshold.temp_threshold1_enable [0] "logic tmp_threshold_attr.tmp_threshold.temp_threshold1_enable[3:0]" +Toggle 1to0 tmp_threshold_attr.tmp_threshold.temp_threshold1_enable [0] "logic tmp_threshold_attr.tmp_threshold.temp_threshold1_enable[3:0]" +Toggle 0to1 tmp_threshold_attr.tmp_threshold.temp_threshold1_enable [1] "logic tmp_threshold_attr.tmp_threshold.temp_threshold1_enable[3:0]" +Toggle 1to0 tmp_threshold_attr.tmp_threshold.temp_threshold1_enable [1] "logic tmp_threshold_attr.tmp_threshold.temp_threshold1_enable[3:0]" +Toggle 0to1 tmp_threshold_attr.tmp_threshold.temp_threshold1_enable [2] "logic tmp_threshold_attr.tmp_threshold.temp_threshold1_enable[3:0]" +Toggle 1to0 tmp_threshold_attr.tmp_threshold.temp_threshold1_enable [2] "logic tmp_threshold_attr.tmp_threshold.temp_threshold1_enable[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle tmp_threshold_attr.tmp_threshold.threshold_policy "logic tmp_threshold_attr.tmp_threshold.threshold_policy[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle tmp_threshold_attr.tmp_threshold.val_mode_therm "logic tmp_threshold_attr.tmp_threshold.val_mode_therm[3:0]" +Toggle 0to1 fme_csr_fme_error0.data [63] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [63] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [1] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [1] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [2] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [2] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [3] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [3] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [4] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [4] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [5] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [5] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [6] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [6] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [7] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [7] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [8] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [8] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [9] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [9] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [10] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [10] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [11] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [11] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [12] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [12] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [13] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [13] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [14] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [14] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [15] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [15] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [16] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [16] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [17] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [17] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [18] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [18] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [19] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [19] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [20] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [20] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [21] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [21] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [22] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [22] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [23] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [23] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [24] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [24] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [25] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [25] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [26] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [26] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [27] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [27] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [28] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [28] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [29] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [29] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [30] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [30] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [31] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [31] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [32] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [32] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [33] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [33] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [34] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [34] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [35] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [35] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [36] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [36] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [37] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [37] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [38] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [38] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [39] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [39] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [40] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [40] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [41] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [41] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [42] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [42] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [43] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [43] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [44] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [44] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [45] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [45] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [46] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [46] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [47] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [47] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [48] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [48] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [49] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [49] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [50] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [50] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [51] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [51] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [52] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [52] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [53] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [53] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [54] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [54] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [55] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [55] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [56] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [56] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [57] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [57] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [58] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [58] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [59] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [59] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [60] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [60] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [61] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [61] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.data [62] "logic fme_csr_fme_error0.data[63:0]" +Toggle 1to0 fme_csr_fme_error0.data [62] "logic fme_csr_fme_error0.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [63] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [63] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [1] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [1] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [2] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [2] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [3] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [3] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [4] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [4] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [5] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [5] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [6] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [6] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [7] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [7] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [8] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [8] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [9] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [9] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [10] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [10] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [11] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [11] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [12] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [12] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [13] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [13] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [14] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [14] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [15] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [15] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [16] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [16] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [17] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [17] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [18] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [18] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [19] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [19] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [20] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [20] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [21] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [21] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [22] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [22] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [23] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [23] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [24] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [24] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [25] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [25] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [26] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [26] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [27] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [27] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [28] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [28] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [29] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [29] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [30] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [30] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [31] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [31] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [32] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [32] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [33] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [33] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [34] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [34] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [35] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [35] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [36] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [36] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [37] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [37] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [38] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [38] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [39] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [39] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [40] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [40] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [41] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [41] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [42] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [42] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [43] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [43] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [44] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [44] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [45] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [45] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [46] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [46] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [47] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [47] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [48] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [48] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [49] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [49] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [50] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [50] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [51] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [51] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [52] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [52] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [53] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [53] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [54] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [54] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [55] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [55] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [56] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [56] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [57] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [57] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [58] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [58] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [59] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [59] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [60] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [60] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [61] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [61] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 0to1 fme_csr_fme_error0_update.data [62] "logic fme_csr_fme_error0_update.data[63:0]" +Toggle 1to0 fme_csr_fme_error0_update.data [62] "logic fme_csr_fme_error0_update.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle ras_nofat_error_attr.ras_nofat_error.port_fatal_error "logic ras_nofat_error_attr.ras_nofat_error.port_fatal_error[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle ras_catfat_error_attr.ras_catfat_error.pcie_poison_error "logic ras_catfat_error_attr.ras_catfat_error.pcie_poison_error[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle ras_catfat_error_attr.ras_catfat_error.fabric_fatal_error "logic ras_catfat_error_attr.ras_catfat_error.fabric_fatal_error[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle port3_offset_attr.port_offset.decouple_port_csr "logic port3_offset_attr.port_offset.decouple_port_csr[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle port0_offset_attr.port_offset.afu_access_ctrl "logic port0_offset_attr.port_offset.afu_access_ctrl[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle port0_offset_attr.port_offset.decouple_port_csr "logic port0_offset_attr.port_offset.decouple_port_csr[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle port1_offset_attr.port_offset.afu_access_ctrl "logic port1_offset_attr.port_offset.afu_access_ctrl[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle port1_offset_attr.port_offset.decouple_port_csr "logic port1_offset_attr.port_offset.decouple_port_csr[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle port2_offset_attr.port_offset.afu_access_ctrl "logic port2_offset_attr.port_offset.afu_access_ctrl[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle port2_offset_attr.port_offset.decouple_port_csr "logic port2_offset_attr.port_offset.decouple_port_csr[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle port3_offset_attr.port_offset.afu_access_ctrl "logic port3_offset_attr.port_offset.afu_access_ctrl[3:0]" +ANNOTATION: " excluding reserved fields " +Toggle fme_csr_tmp_rdsensor_fmt2_reset.data "logic fme_csr_tmp_rdsensor_fmt2_reset.data[63:0]" +ANNOTATION: " excluding reserved fields " +Toggle fme_csr_tmp_rdsensor_fmt2_reset.word.lower32 "logic fme_csr_tmp_rdsensor_fmt2_reset.word.lower32[31:0]" +ANNOTATION: " excluding reserved fields " +Toggle fme_csr_tmp_rdsensor_fmt2_reset.word.upper32 "logic fme_csr_tmp_rdsensor_fmt2_reset.word.upper32[31:0]" +ANNOTATION: " excluding reserved fields " +Toggle fme_csr_tmp_rdsensor_fmt2_update.data "logic fme_csr_tmp_rdsensor_fmt2_update.data[63:0]" +ANNOTATION: " excluding reserved fields " +Toggle fme_csr_tmp_rdsensor_fmt2_update.word.lower32 "logic fme_csr_tmp_rdsensor_fmt2_update.word.lower32[31:0]" +ANNOTATION: " excluding reserved fields " +Toggle fme_csr_tmp_rdsensor_fmt2_update.word.upper32 "logic fme_csr_tmp_rdsensor_fmt2_update.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_capability_reset.data "logic fme_csr_tmp_threshold_capability_reset.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_capability_reset.word.lower32 "logic fme_csr_tmp_threshold_capability_reset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_capability_reset.word.upper32 "logic fme_csr_tmp_threshold_capability_reset.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_capability_update.data "logic fme_csr_tmp_threshold_capability_update.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_capability_update.word.lower32 "logic fme_csr_tmp_threshold_capability_update.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_capability_update.word.upper32 "logic fme_csr_tmp_threshold_capability_update.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_reset.data "logic fme_csr_tmp_threshold_reset.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_reset.tmp_threshold.temp_threshold1 "logic fme_csr_tmp_threshold_reset.tmp_threshold.temp_threshold1[6:0]" +Toggle 0to1 fme_csr_tmp_threshold_reset.tmp_threshold.temp_threshold1_enable "logic fme_csr_tmp_threshold_reset.tmp_threshold.temp_threshold1_enable" +Toggle 1to0 fme_csr_tmp_threshold_reset.tmp_threshold.temp_threshold1_enable "logic fme_csr_tmp_threshold_reset.tmp_threshold.temp_threshold1_enable" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_reset.tmp_threshold.temp_threshold2 "logic fme_csr_tmp_threshold_reset.tmp_threshold.temp_threshold2[6:0]" +Toggle 0to1 fme_csr_tmp_threshold_reset.tmp_threshold.temp_threshold2_enable "logic fme_csr_tmp_threshold_reset.tmp_threshold.temp_threshold2_enable" +Toggle 1to0 fme_csr_tmp_threshold_reset.tmp_threshold.temp_threshold2_enable "logic fme_csr_tmp_threshold_reset.tmp_threshold.temp_threshold2_enable" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_reset.tmp_threshold.therm_trip_threshold "logic fme_csr_tmp_threshold_reset.tmp_threshold.therm_trip_threshold[6:0]" +Toggle 0to1 fme_csr_tmp_threshold_reset.tmp_threshold.threshold_policy "logic fme_csr_tmp_threshold_reset.tmp_threshold.threshold_policy" +Toggle 1to0 fme_csr_tmp_threshold_reset.tmp_threshold.threshold_policy "logic fme_csr_tmp_threshold_reset.tmp_threshold.threshold_policy" +Toggle 0to1 fme_csr_tmp_threshold_reset.tmp_threshold.val_mode_therm "logic fme_csr_tmp_threshold_reset.tmp_threshold.val_mode_therm" +Toggle 1to0 fme_csr_tmp_threshold_reset.tmp_threshold.val_mode_therm "logic fme_csr_tmp_threshold_reset.tmp_threshold.val_mode_therm" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_reset.word.lower32 "logic fme_csr_tmp_threshold_reset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_reset.word.upper32 "logic fme_csr_tmp_threshold_reset.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_update.data "logic fme_csr_tmp_threshold_update.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_update.tmp_threshold.temp_threshold1 "logic fme_csr_tmp_threshold_update.tmp_threshold.temp_threshold1[6:0]" +Toggle 0to1 fme_csr_tmp_threshold_update.tmp_threshold.temp_threshold1_enable "logic fme_csr_tmp_threshold_update.tmp_threshold.temp_threshold1_enable" +Toggle 1to0 fme_csr_tmp_threshold_update.tmp_threshold.temp_threshold1_enable "logic fme_csr_tmp_threshold_update.tmp_threshold.temp_threshold1_enable" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_update.tmp_threshold.temp_threshold2 "logic fme_csr_tmp_threshold_update.tmp_threshold.temp_threshold2[6:0]" +Toggle 0to1 fme_csr_tmp_threshold_update.tmp_threshold.temp_threshold2_enable "logic fme_csr_tmp_threshold_update.tmp_threshold.temp_threshold2_enable" +Toggle 1to0 fme_csr_tmp_threshold_update.tmp_threshold.temp_threshold2_enable "logic fme_csr_tmp_threshold_update.tmp_threshold.temp_threshold2_enable" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_update.tmp_threshold.therm_trip_threshold "logic fme_csr_tmp_threshold_update.tmp_threshold.therm_trip_threshold[6:0]" +Toggle 0to1 fme_csr_tmp_threshold_update.tmp_threshold.threshold_policy "logic fme_csr_tmp_threshold_update.tmp_threshold.threshold_policy" +Toggle 1to0 fme_csr_tmp_threshold_update.tmp_threshold.threshold_policy "logic fme_csr_tmp_threshold_update.tmp_threshold.threshold_policy" +Toggle 0to1 fme_csr_tmp_threshold_update.tmp_threshold.val_mode_therm "logic fme_csr_tmp_threshold_update.tmp_threshold.val_mode_therm" +Toggle 1to0 fme_csr_tmp_threshold_update.tmp_threshold.val_mode_therm "logic fme_csr_tmp_threshold_update.tmp_threshold.val_mode_therm" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_update.word.lower32 "logic fme_csr_tmp_threshold_update.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_update.word.upper32 "logic fme_csr_tmp_threshold_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.ras_nofat_error.port_fatal_error "logic fme_csr_ras_nofat_error_update.ras_nofat_error.port_fatal_error" +Toggle 1to0 fme_csr_ras_nofat_error_update.ras_nofat_error.port_fatal_error "logic fme_csr_ras_nofat_error_update.ras_nofat_error.port_fatal_error" +Toggle 0to1 fme_csr_ras_nofat_error_reset.ras_nofat_error.port_fatal_error "logic fme_csr_ras_nofat_error_reset.ras_nofat_error.port_fatal_error" +Toggle 1to0 fme_csr_ras_nofat_error_reset.ras_nofat_error.port_fatal_error "logic fme_csr_ras_nofat_error_reset.ras_nofat_error.port_fatal_error" +Toggle 0to1 fme_csr_ras_nofat_error.ras_nofat_error.port_fatal_error "logic fme_csr_ras_nofat_error.ras_nofat_error.port_fatal_error" +Toggle 1to0 fme_csr_ras_nofat_error.ras_nofat_error.port_fatal_error "logic fme_csr_ras_nofat_error.ras_nofat_error.port_fatal_error" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset_update.word.upper32 "logic fme_csr_port3_offset_update.word.upper32[31:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error_update.word.upper32 "logic fme_csr_pcie0_error_update.word.upper32[31:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error_update.word.lower32 "logic fme_csr_pcie0_error_update.word.lower32[31:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error_update.data "logic fme_csr_pcie0_error_update.data[63:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error_reset.word.upper32 "logic fme_csr_pcie0_error_reset.word.upper32[31:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error_reset.word.lower32 "logic fme_csr_pcie0_error_reset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset.port_offset.port_byte_offset "logic fme_csr_port0_offset.port_offset.port_byte_offset[23:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset.word.lower32 "logic fme_csr_port0_offset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset_reset.data "logic fme_csr_port0_offset_reset.data[63:0]" +Toggle 0to1 fme_csr_port0_offset_reset.port_offset.decouple_port_csr "logic fme_csr_port0_offset_reset.port_offset.decouple_port_csr" +Toggle 1to0 fme_csr_port0_offset_reset.port_offset.decouple_port_csr "logic fme_csr_port0_offset_reset.port_offset.decouple_port_csr" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset_reset.port_offset.port_byte_offset "logic fme_csr_port0_offset_reset.port_offset.port_byte_offset[23:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset_reset.word.lower32 "logic fme_csr_port0_offset_reset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset_reset.word.upper32 "logic fme_csr_port0_offset_reset.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset_update.data "logic fme_csr_port0_offset_update.data[63:0]" +Toggle 0to1 fme_csr_port0_offset_update.port_offset.afu_access_ctrl "logic fme_csr_port0_offset_update.port_offset.afu_access_ctrl" +Toggle 1to0 fme_csr_port0_offset_update.port_offset.afu_access_ctrl "logic fme_csr_port0_offset_update.port_offset.afu_access_ctrl" +Toggle 0to1 fme_csr_port0_offset_update.port_offset.decouple_port_csr "logic fme_csr_port0_offset_update.port_offset.decouple_port_csr" +Toggle 1to0 fme_csr_port0_offset_update.port_offset.decouple_port_csr "logic fme_csr_port0_offset_update.port_offset.decouple_port_csr" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset_update.port_offset.port_byte_offset "logic fme_csr_port0_offset_update.port_offset.port_byte_offset[23:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset_update.word.lower32 "logic fme_csr_port0_offset_update.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset_update.word.upper32 "logic fme_csr_port0_offset_update.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset.port_offset.port_byte_offset "logic fme_csr_port1_offset.port_offset.port_byte_offset[23:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset.word.lower32 "logic fme_csr_port1_offset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset_reset.data "logic fme_csr_port1_offset_reset.data[63:0]" +Toggle 0to1 fme_csr_port1_offset_reset.port_offset.afu_access_ctrl "logic fme_csr_port1_offset_reset.port_offset.afu_access_ctrl" +Toggle 1to0 fme_csr_port1_offset_reset.port_offset.afu_access_ctrl "logic fme_csr_port1_offset_reset.port_offset.afu_access_ctrl" +Toggle 0to1 fme_csr_port1_offset_reset.port_offset.decouple_port_csr "logic fme_csr_port1_offset_reset.port_offset.decouple_port_csr" +Toggle 1to0 fme_csr_port1_offset_reset.port_offset.decouple_port_csr "logic fme_csr_port1_offset_reset.port_offset.decouple_port_csr" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset_reset.word.lower32 "logic fme_csr_port1_offset_reset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset_reset.word.upper32 "logic fme_csr_port1_offset_reset.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset_update.data "logic fme_csr_port1_offset_update.data[63:0]" +Toggle 0to1 fme_csr_port1_offset_update.port_offset.afu_access_ctrl "logic fme_csr_port1_offset_update.port_offset.afu_access_ctrl" +Toggle 1to0 fme_csr_port1_offset_update.port_offset.afu_access_ctrl "logic fme_csr_port1_offset_update.port_offset.afu_access_ctrl" +Toggle 0to1 fme_csr_port1_offset_update.port_offset.decouple_port_csr "logic fme_csr_port1_offset_update.port_offset.decouple_port_csr" +Toggle 1to0 fme_csr_port1_offset_update.port_offset.decouple_port_csr "logic fme_csr_port1_offset_update.port_offset.decouple_port_csr" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset_update.port_offset.port_byte_offset "logic fme_csr_port1_offset_update.port_offset.port_byte_offset[23:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset_update.word.lower32 "logic fme_csr_port1_offset_update.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset_update.word.upper32 "logic fme_csr_port1_offset_update.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset.port_offset.port_byte_offset "logic fme_csr_port2_offset.port_offset.port_byte_offset[23:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset.word.lower32 "logic fme_csr_port2_offset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset_reset.data "logic fme_csr_port2_offset_reset.data[63:0]" +Toggle 0to1 fme_csr_port2_offset_reset.port_offset.afu_access_ctrl "logic fme_csr_port2_offset_reset.port_offset.afu_access_ctrl" +Toggle 1to0 fme_csr_port2_offset_reset.port_offset.afu_access_ctrl "logic fme_csr_port2_offset_reset.port_offset.afu_access_ctrl" +Toggle 0to1 fme_csr_port2_offset_reset.port_offset.decouple_port_csr "logic fme_csr_port2_offset_reset.port_offset.decouple_port_csr" +Toggle 1to0 fme_csr_port2_offset_reset.port_offset.decouple_port_csr "logic fme_csr_port2_offset_reset.port_offset.decouple_port_csr" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset_reset.word.lower32 "logic fme_csr_port2_offset_reset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset_reset.word.upper32 "logic fme_csr_port2_offset_reset.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset_update.data "logic fme_csr_port2_offset_update.data[63:0]" +Toggle 0to1 fme_csr_port2_offset_update.port_offset.afu_access_ctrl "logic fme_csr_port2_offset_update.port_offset.afu_access_ctrl" +Toggle 1to0 fme_csr_port2_offset_update.port_offset.afu_access_ctrl "logic fme_csr_port2_offset_update.port_offset.afu_access_ctrl" +Toggle 0to1 fme_csr_port2_offset_update.port_offset.decouple_port_csr "logic fme_csr_port2_offset_update.port_offset.decouple_port_csr" +Toggle 1to0 fme_csr_port2_offset_update.port_offset.decouple_port_csr "logic fme_csr_port2_offset_update.port_offset.decouple_port_csr" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset_update.port_offset.port_byte_offset "logic fme_csr_port2_offset_update.port_offset.port_byte_offset[23:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset_update.word.lower32 "logic fme_csr_port2_offset_update.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset_update.word.upper32 "logic fme_csr_port2_offset_update.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset.port_offset.port_byte_offset "logic fme_csr_port3_offset.port_offset.port_byte_offset[23:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset.word.lower32 "logic fme_csr_port3_offset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset_reset.data "logic fme_csr_port3_offset_reset.data[63:0]" +Toggle 0to1 fme_csr_port3_offset_reset.port_offset.afu_access_ctrl "logic fme_csr_port3_offset_reset.port_offset.afu_access_ctrl" +Toggle 1to0 fme_csr_port3_offset_reset.port_offset.afu_access_ctrl "logic fme_csr_port3_offset_reset.port_offset.afu_access_ctrl" +Toggle 0to1 fme_csr_port3_offset_reset.port_offset.decouple_port_csr "logic fme_csr_port3_offset_reset.port_offset.decouple_port_csr" +Toggle 1to0 fme_csr_port3_offset_reset.port_offset.decouple_port_csr "logic fme_csr_port3_offset_reset.port_offset.decouple_port_csr" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset_reset.port_offset.port_byte_offset "logic fme_csr_port3_offset_reset.port_offset.port_byte_offset[23:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset_reset.word.lower32 "logic fme_csr_port3_offset_reset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset_reset.word.upper32 "logic fme_csr_port3_offset_reset.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset_update.data "logic fme_csr_port3_offset_update.data[63:0]" +Toggle 0to1 fme_csr_port3_offset_update.port_offset.decouple_port_csr "logic fme_csr_port3_offset_update.port_offset.decouple_port_csr" +Toggle 1to0 fme_csr_port3_offset_update.port_offset.decouple_port_csr "logic fme_csr_port3_offset_update.port_offset.decouple_port_csr" +Toggle 0to1 fme_csr_port3_offset_update.port_offset.port_implemented "logic fme_csr_port3_offset_update.port_offset.port_implemented" +Toggle 1to0 fme_csr_port3_offset_update.port_offset.port_implemented "logic fme_csr_port3_offset_update.port_offset.port_implemented" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset_update.word.lower32 "logic fme_csr_port3_offset_update.word.lower32[31:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error_mask_update.word.lower32 "logic fme_csr_pcie0_error_mask_update.word.lower32[31:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error.word.upper32 "logic fme_csr_pcie0_error.word.upper32[31:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error.word.lower32 "logic fme_csr_pcie0_error.word.lower32[31:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error.data "logic fme_csr_pcie0_error.data[63:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error_mask_reset.data "logic fme_csr_pcie0_error_mask_reset.data[63:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error_mask.word.upper32 "logic fme_csr_pcie0_error_mask.word.upper32[31:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error_mask_update.data "logic fme_csr_pcie0_error_mask_update.data[63:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error_mask_reset.word.upper32 "logic fme_csr_pcie0_error_mask_reset.word.upper32[31:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error_mask_reset.word.lower32 "logic fme_csr_pcie0_error_mask_reset.word.lower32[31:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error_reset.data "logic fme_csr_pcie0_error_reset.data[63:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error_mask_update.word.upper32 "logic fme_csr_pcie0_error_mask_update.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_error0_reset.word.upper32 "logic fme_csr_fme_error0_reset.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_error0_reset.word.lower32 "logic fme_csr_fme_error0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error0_reset.fme_error0.partial_reconfig_fifo_parity_error "logic fme_csr_fme_error0_reset.fme_error0.partial_reconfig_fifo_parity_error" +Toggle 1to0 fme_csr_fme_error0_reset.fme_error0.partial_reconfig_fifo_parity_error "logic fme_csr_fme_error0_reset.fme_error0.partial_reconfig_fifo_parity_error" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_error0_reset.data "logic fme_csr_fme_error0_reset.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_error0.word.upper32 "logic fme_csr_fme_error0.word.upper32[31:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_status_update.data "logic fme_csr_fab_status_update.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fab_status_attr.fab_status.pcie0_link_status "logic fab_status_attr.fab_status.pcie0_link_status[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fab_capability_attr.fab_capability.pcie0_link "logic fab_capability_attr.fab_capability.pcie0_link[3:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_status_reset.data "logic fme_csr_fab_status_reset.data[63:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_status_reset.word.lower32 "logic fme_csr_fab_status_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_status_reset.word.upper32 "logic fme_csr_fab_status_reset.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_error0_update.word.upper32 "logic fme_csr_fme_error0_update.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle tmp_threshold_attr.tmp_threshold.reserved34 "logic tmp_threshold_attr.tmp_threshold.reserved34[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle ras_catfat_error_attr.ras_catfat_error.reserved10 "logic ras_catfat_error_attr.ras_catfat_error.reserved10[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle ras_catfat_error_mask_attr.ras_catfat_error_mask.reserved10 "logic ras_catfat_error_mask_attr.ras_catfat_error_mask.reserved10[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle ras_nofat_error_attr.ras_nofat_error.reserved4 "logic ras_nofat_error_attr.ras_nofat_error.reserved4[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle ras_nofat_error_mask_attr.ras_nofat_error_mask.reserved4 "logic ras_nofat_error_mask_attr.ras_nofat_error_mask.reserved4[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle tmp_rdsensor_fmt1_attr.tmp_rdsensor_fmt1.reserved7 "logic tmp_rdsensor_fmt1_attr.tmp_rdsensor_fmt1.reserved7[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle tmp_threshold_attr.tmp_threshold.reserved31 "logic tmp_threshold_attr.tmp_threshold.reserved31[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fpmon_fab_ctl_attr.fpmon_fab_ctl.reserved22 "logic fpmon_fab_ctl_attr.fpmon_fab_ctl.reserved22[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold.tmp_threshold.reserved16 "logic fme_csr_tmp_threshold.tmp_threshold.reserved16[7:0]" +Toggle 0to1 fme_csr_tmp_threshold.tmp_threshold.reserved31 "logic fme_csr_tmp_threshold.tmp_threshold.reserved31" +Toggle 1to0 fme_csr_tmp_threshold.tmp_threshold.reserved31 "logic fme_csr_tmp_threshold.tmp_threshold.reserved31" +Toggle 0to1 fme_csr_tmp_threshold.tmp_threshold.reserved34 "logic fme_csr_tmp_threshold.tmp_threshold.reserved34" +Toggle 1to0 fme_csr_tmp_threshold.tmp_threshold.reserved34 "logic fme_csr_tmp_threshold.tmp_threshold.reserved34" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold.tmp_threshold.reserved36 "logic fme_csr_tmp_threshold.tmp_threshold.reserved36[4:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold.tmp_threshold.reserved42 "logic fme_csr_tmp_threshold.tmp_threshold.reserved42[1:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold.tmp_threshold.reserved45 "logic fme_csr_tmp_threshold.tmp_threshold.reserved45[18:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_capability_reset.tmp_threshold_capability.reserved "logic fme_csr_tmp_threshold_capability_reset.tmp_threshold_capability.reserved[62:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_capability_update.tmp_threshold_capability.reserved "logic fme_csr_tmp_threshold_capability_update.tmp_threshold_capability.reserved[62:0]" +Toggle 0to1 fme_csr_tmp_threshold_reset.tmp_threshold.reserved31 "logic fme_csr_tmp_threshold_reset.tmp_threshold.reserved31" +Toggle 1to0 fme_csr_tmp_threshold_reset.tmp_threshold.reserved31 "logic fme_csr_tmp_threshold_reset.tmp_threshold.reserved31" +Toggle 0to1 fme_csr_tmp_threshold_reset.tmp_threshold.reserved34 "logic fme_csr_tmp_threshold_reset.tmp_threshold.reserved34" +Toggle 1to0 fme_csr_tmp_threshold_reset.tmp_threshold.reserved34 "logic fme_csr_tmp_threshold_reset.tmp_threshold.reserved34" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_reset.tmp_threshold.reserved36 "logic fme_csr_tmp_threshold_reset.tmp_threshold.reserved36[4:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_reset.tmp_threshold.reserved42 "logic fme_csr_tmp_threshold_reset.tmp_threshold.reserved42[1:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_reset.tmp_threshold.reserved45 "logic fme_csr_tmp_threshold_reset.tmp_threshold.reserved45[18:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_update.tmp_threshold.reserved16 "logic fme_csr_tmp_threshold_update.tmp_threshold.reserved16[7:0]" +Toggle 0to1 fme_csr_tmp_threshold_update.tmp_threshold.reserved31 "logic fme_csr_tmp_threshold_update.tmp_threshold.reserved31" +Toggle 1to0 fme_csr_tmp_threshold_update.tmp_threshold.reserved31 "logic fme_csr_tmp_threshold_update.tmp_threshold.reserved31" +Toggle 0to1 fme_csr_tmp_threshold_update.tmp_threshold.reserved34 "logic fme_csr_tmp_threshold_update.tmp_threshold.reserved34" +Toggle 1to0 fme_csr_tmp_threshold_update.tmp_threshold.reserved34 "logic fme_csr_tmp_threshold_update.tmp_threshold.reserved34" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_update.tmp_threshold.reserved36 "logic fme_csr_tmp_threshold_update.tmp_threshold.reserved36[4:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_update.tmp_threshold.reserved42 "logic fme_csr_tmp_threshold_update.tmp_threshold.reserved42[1:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_update.tmp_threshold.reserved45 "logic fme_csr_tmp_threshold_update.tmp_threshold.reserved45[18:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_tmp_rdsensor_fmt1_update.tmp_rdsensor_fmt1.reserved42 "logic fme_csr_tmp_rdsensor_fmt1_update.tmp_rdsensor_fmt1.reserved42[21:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset.port_offset.reserved24 "logic fme_csr_port0_offset.port_offset.reserved24[7:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset.port_offset.reserved35 "logic fme_csr_port0_offset.port_offset.reserved35[19:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset.port_offset.reserved57 "logic fme_csr_port0_offset.port_offset.reserved57[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset.port_offset.reserved61 "logic fme_csr_port0_offset.port_offset.reserved61[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset_reset.port_offset.reserved24 "logic fme_csr_port0_offset_reset.port_offset.reserved24[7:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset_reset.port_offset.reserved35 "logic fme_csr_port0_offset_reset.port_offset.reserved35[19:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset_reset.port_offset.reserved57 "logic fme_csr_port0_offset_reset.port_offset.reserved57[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset_reset.port_offset.reserved61 "logic fme_csr_port0_offset_reset.port_offset.reserved61[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset_update.port_offset.reserved24 "logic fme_csr_port0_offset_update.port_offset.reserved24[7:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset_update.port_offset.reserved35 "logic fme_csr_port0_offset_update.port_offset.reserved35[19:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset_update.port_offset.reserved57 "logic fme_csr_port0_offset_update.port_offset.reserved57[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port0_offset_update.port_offset.reserved61 "logic fme_csr_port0_offset_update.port_offset.reserved61[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset.port_offset.reserved24 "logic fme_csr_port1_offset.port_offset.reserved24[7:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset.port_offset.reserved35 "logic fme_csr_port1_offset.port_offset.reserved35[19:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset.port_offset.reserved57 "logic fme_csr_port1_offset.port_offset.reserved57[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset.port_offset.reserved61 "logic fme_csr_port1_offset.port_offset.reserved61[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset_reset.port_offset.reserved24 "logic fme_csr_port1_offset_reset.port_offset.reserved24[7:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset_reset.port_offset.reserved35 "logic fme_csr_port1_offset_reset.port_offset.reserved35[19:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset_reset.port_offset.reserved57 "logic fme_csr_port1_offset_reset.port_offset.reserved57[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset_reset.port_offset.reserved61 "logic fme_csr_port1_offset_reset.port_offset.reserved61[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset_update.port_offset.reserved24 "logic fme_csr_port1_offset_update.port_offset.reserved24[7:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset_update.port_offset.reserved35 "logic fme_csr_port1_offset_update.port_offset.reserved35[19:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset_update.port_offset.reserved57 "logic fme_csr_port1_offset_update.port_offset.reserved57[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port1_offset_update.port_offset.reserved61 "logic fme_csr_port1_offset_update.port_offset.reserved61[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset.port_offset.reserved24 "logic fme_csr_port2_offset.port_offset.reserved24[7:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset.port_offset.reserved35 "logic fme_csr_port2_offset.port_offset.reserved35[19:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset.port_offset.reserved57 "logic fme_csr_port2_offset.port_offset.reserved57[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset.port_offset.reserved61 "logic fme_csr_port2_offset.port_offset.reserved61[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset_reset.port_offset.reserved24 "logic fme_csr_port2_offset_reset.port_offset.reserved24[7:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset_reset.port_offset.reserved35 "logic fme_csr_port2_offset_reset.port_offset.reserved35[19:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset_reset.port_offset.reserved57 "logic fme_csr_port2_offset_reset.port_offset.reserved57[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset_reset.port_offset.reserved61 "logic fme_csr_port2_offset_reset.port_offset.reserved61[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset_update.port_offset.reserved24 "logic fme_csr_port2_offset_update.port_offset.reserved24[7:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset_update.port_offset.reserved35 "logic fme_csr_port2_offset_update.port_offset.reserved35[19:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset_update.port_offset.reserved57 "logic fme_csr_port2_offset_update.port_offset.reserved57[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port2_offset_update.port_offset.reserved61 "logic fme_csr_port2_offset_update.port_offset.reserved61[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset.port_offset.reserved24 "logic fme_csr_port3_offset.port_offset.reserved24[7:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset.port_offset.reserved35 "logic fme_csr_port3_offset.port_offset.reserved35[19:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset.port_offset.reserved57 "logic fme_csr_port3_offset.port_offset.reserved57[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset.port_offset.reserved61 "logic fme_csr_port3_offset.port_offset.reserved61[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset_reset.port_offset.reserved24 "logic fme_csr_port3_offset_reset.port_offset.reserved24[7:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset_reset.port_offset.reserved35 "logic fme_csr_port3_offset_reset.port_offset.reserved35[19:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset_reset.port_offset.reserved57 "logic fme_csr_port3_offset_reset.port_offset.reserved57[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset_reset.port_offset.reserved61 "logic fme_csr_port3_offset_reset.port_offset.reserved61[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset_update.port_offset.reserved24 "logic fme_csr_port3_offset_update.port_offset.reserved24[7:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset_update.port_offset.reserved35 "logic fme_csr_port3_offset_update.port_offset.reserved35[19:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset_update.port_offset.reserved57 "logic fme_csr_port3_offset_update.port_offset.reserved57[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_port3_offset_update.port_offset.reserved61 "logic fme_csr_port3_offset_update.port_offset.reserved61[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_catfat_error.ras_catfat_error.reserved0 "logic fme_csr_ras_catfat_error.ras_catfat_error.reserved0[5:0]" +Toggle 0to1 fme_csr_ras_catfat_error.ras_catfat_error.reserved10 "logic fme_csr_ras_catfat_error.ras_catfat_error.reserved10" +Toggle 1to0 fme_csr_ras_catfat_error.ras_catfat_error.reserved10 "logic fme_csr_ras_catfat_error.ras_catfat_error.reserved10" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_catfat_error.ras_catfat_error.reserved12 "logic fme_csr_ras_catfat_error.ras_catfat_error.reserved12[51:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_catfat_error_mask.ras_catfat_error_mask.reserved0 "logic fme_csr_ras_catfat_error_mask.ras_catfat_error_mask.reserved0[5:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask.ras_catfat_error_mask.reserved10 "logic fme_csr_ras_catfat_error_mask.ras_catfat_error_mask.reserved10" +Toggle 1to0 fme_csr_ras_catfat_error_mask.ras_catfat_error_mask.reserved10 "logic fme_csr_ras_catfat_error_mask.ras_catfat_error_mask.reserved10" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_catfat_error_mask.ras_catfat_error_mask.reserved12 "logic fme_csr_ras_catfat_error_mask.ras_catfat_error_mask.reserved12[51:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_catfat_error_mask_reset.ras_catfat_error_mask.reserved0 "logic fme_csr_ras_catfat_error_mask_reset.ras_catfat_error_mask.reserved0[5:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_reset.ras_catfat_error_mask.reserved10 "logic fme_csr_ras_catfat_error_mask_reset.ras_catfat_error_mask.reserved10" +Toggle 1to0 fme_csr_ras_catfat_error_mask_reset.ras_catfat_error_mask.reserved10 "logic fme_csr_ras_catfat_error_mask_reset.ras_catfat_error_mask.reserved10" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_catfat_error_mask_reset.ras_catfat_error_mask.reserved12 "logic fme_csr_ras_catfat_error_mask_reset.ras_catfat_error_mask.reserved12[51:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_catfat_error_mask_update.ras_catfat_error_mask.reserved0 "logic fme_csr_ras_catfat_error_mask_update.ras_catfat_error_mask.reserved0[5:0]" +Toggle 0to1 fme_csr_ras_catfat_error_mask_update.ras_catfat_error_mask.reserved10 "logic fme_csr_ras_catfat_error_mask_update.ras_catfat_error_mask.reserved10" +Toggle 1to0 fme_csr_ras_catfat_error_mask_update.ras_catfat_error_mask.reserved10 "logic fme_csr_ras_catfat_error_mask_update.ras_catfat_error_mask.reserved10" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_catfat_error_mask_update.ras_catfat_error_mask.reserved12 "logic fme_csr_ras_catfat_error_mask_update.ras_catfat_error_mask.reserved12[51:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_catfat_error_reset.ras_catfat_error.reserved0 "logic fme_csr_ras_catfat_error_reset.ras_catfat_error.reserved0[5:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.ras_catfat_error.reserved10 "logic fme_csr_ras_catfat_error_reset.ras_catfat_error.reserved10" +Toggle 1to0 fme_csr_ras_catfat_error_reset.ras_catfat_error.reserved10 "logic fme_csr_ras_catfat_error_reset.ras_catfat_error.reserved10" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_catfat_error_reset.ras_catfat_error.reserved12 "logic fme_csr_ras_catfat_error_reset.ras_catfat_error.reserved12[51:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_catfat_error_update.ras_catfat_error.reserved0 "logic fme_csr_ras_catfat_error_update.ras_catfat_error.reserved0[5:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.ras_catfat_error.reserved10 "logic fme_csr_ras_catfat_error_update.ras_catfat_error.reserved10" +Toggle 1to0 fme_csr_ras_catfat_error_update.ras_catfat_error.reserved10 "logic fme_csr_ras_catfat_error_update.ras_catfat_error.reserved10" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_catfat_error_update.ras_catfat_error.reserved12 "logic fme_csr_ras_catfat_error_update.ras_catfat_error.reserved12[51:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_error_inj.ras_error_inj.reserved3 "logic fme_csr_ras_error_inj.ras_error_inj.reserved3[60:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_error_inj_reset.ras_error_inj.reserved3 "logic fme_csr_ras_error_inj_reset.ras_error_inj.reserved3[60:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_error_inj_update.ras_error_inj.reserved3 "logic fme_csr_ras_error_inj_update.ras_error_inj.reserved3[60:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_nofat_error.ras_nofat_error.reserved0 "logic fme_csr_ras_nofat_error.ras_nofat_error.reserved0[1:0]" +Toggle 0to1 fme_csr_ras_nofat_error.ras_nofat_error.reserved4 "logic fme_csr_ras_nofat_error.ras_nofat_error.reserved4" +Toggle 1to0 fme_csr_ras_nofat_error.ras_nofat_error.reserved4 "logic fme_csr_ras_nofat_error.ras_nofat_error.reserved4" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_nofat_error.ras_nofat_error.reserved7 "logic fme_csr_ras_nofat_error.ras_nofat_error.reserved7[56:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_nofat_error_mask.ras_nofat_error_mask.reserved0 "logic fme_csr_ras_nofat_error_mask.ras_nofat_error_mask.reserved0[1:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask.ras_nofat_error_mask.reserved4 "logic fme_csr_ras_nofat_error_mask.ras_nofat_error_mask.reserved4" +Toggle 1to0 fme_csr_ras_nofat_error_mask.ras_nofat_error_mask.reserved4 "logic fme_csr_ras_nofat_error_mask.ras_nofat_error_mask.reserved4" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_nofat_error_mask.ras_nofat_error_mask.reserved7 "logic fme_csr_ras_nofat_error_mask.ras_nofat_error_mask.reserved7[56:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_nofat_error_mask_reset.ras_nofat_error_mask.reserved0 "logic fme_csr_ras_nofat_error_mask_reset.ras_nofat_error_mask.reserved0[1:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_reset.ras_nofat_error_mask.reserved4 "logic fme_csr_ras_nofat_error_mask_reset.ras_nofat_error_mask.reserved4" +Toggle 1to0 fme_csr_ras_nofat_error_mask_reset.ras_nofat_error_mask.reserved4 "logic fme_csr_ras_nofat_error_mask_reset.ras_nofat_error_mask.reserved4" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_nofat_error_mask_reset.ras_nofat_error_mask.reserved7 "logic fme_csr_ras_nofat_error_mask_reset.ras_nofat_error_mask.reserved7[56:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_nofat_error_mask_update.ras_nofat_error_mask.reserved0 "logic fme_csr_ras_nofat_error_mask_update.ras_nofat_error_mask.reserved0[1:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.ras_nofat_error_mask.reserved4 "logic fme_csr_ras_nofat_error_mask_update.ras_nofat_error_mask.reserved4" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.ras_nofat_error_mask.reserved4 "logic fme_csr_ras_nofat_error_mask_update.ras_nofat_error_mask.reserved4" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_nofat_error_mask_update.ras_nofat_error_mask.reserved7 "logic fme_csr_ras_nofat_error_mask_update.ras_nofat_error_mask.reserved7[56:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_nofat_error_reset.ras_nofat_error.reserved0 "logic fme_csr_ras_nofat_error_reset.ras_nofat_error.reserved0[1:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.ras_nofat_error.reserved4 "logic fme_csr_ras_nofat_error_reset.ras_nofat_error.reserved4" +Toggle 1to0 fme_csr_ras_nofat_error_reset.ras_nofat_error.reserved4 "logic fme_csr_ras_nofat_error_reset.ras_nofat_error.reserved4" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_nofat_error_reset.ras_nofat_error.reserved7 "logic fme_csr_ras_nofat_error_reset.ras_nofat_error.reserved7[56:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_nofat_error_update.ras_nofat_error.reserved0 "logic fme_csr_ras_nofat_error_update.ras_nofat_error.reserved0[1:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.ras_nofat_error.reserved4 "logic fme_csr_ras_nofat_error_update.ras_nofat_error.reserved4" +Toggle 1to0 fme_csr_ras_nofat_error_update.ras_nofat_error.reserved4 "logic fme_csr_ras_nofat_error_update.ras_nofat_error.reserved4" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_nofat_error_update.ras_nofat_error.reserved7 "logic fme_csr_ras_nofat_error_update.ras_nofat_error.reserved7[56:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_therm_mngm_dfh_reset.dfh.reserved "logic fme_csr_therm_mngm_dfh_reset.dfh.reserved[18:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_therm_mngm_dfh_update.dfh.reserved "logic fme_csr_therm_mngm_dfh_update.dfh.reserved[18:0]" +Toggle 0to1 fme_csr_tmp_rdsensor_fmt1_reset.tmp_rdsensor_fmt1.reserved7 "logic fme_csr_tmp_rdsensor_fmt1_reset.tmp_rdsensor_fmt1.reserved7" +Toggle 1to0 fme_csr_tmp_rdsensor_fmt1_reset.tmp_rdsensor_fmt1.reserved7 "logic fme_csr_tmp_rdsensor_fmt1_reset.tmp_rdsensor_fmt1.reserved7" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_tmp_rdsensor_fmt1_reset.tmp_rdsensor_fmt1.reserved25 "logic fme_csr_tmp_rdsensor_fmt1_reset.tmp_rdsensor_fmt1.reserved25[6:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_tmp_rdsensor_fmt1_reset.tmp_rdsensor_fmt1.reserved42 "logic fme_csr_tmp_rdsensor_fmt1_reset.tmp_rdsensor_fmt1.reserved42[21:0]" +Toggle 0to1 fme_csr_tmp_rdsensor_fmt1_update.tmp_rdsensor_fmt1.reserved7 "logic fme_csr_tmp_rdsensor_fmt1_update.tmp_rdsensor_fmt1.reserved7" +Toggle 1to0 fme_csr_tmp_rdsensor_fmt1_update.tmp_rdsensor_fmt1.reserved7 "logic fme_csr_tmp_rdsensor_fmt1_update.tmp_rdsensor_fmt1.reserved7" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_tmp_rdsensor_fmt1_update.tmp_rdsensor_fmt1.reserved25 "logic fme_csr_tmp_rdsensor_fmt1_update.tmp_rdsensor_fmt1.reserved25[6:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_first_error_reset.fme_first_next_error.reserved "logic fme_csr_fme_first_error_reset.fme_first_next_error.reserved[1:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_first_error_update.fme_first_next_error.reserved "logic fme_csr_fme_first_error_update.fme_first_next_error.reserved[1:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_next_afu_reset.fme_next_afu.reserved "logic fme_csr_fme_next_afu_reset.fme_next_afu.reserved[39:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_next_afu_update.fme_next_afu.reserved "logic fme_csr_fme_next_afu_update.fme_next_afu.reserved[39:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_next_error_reset.fme_first_next_error.reserved "logic fme_csr_fme_next_error_reset.fme_first_next_error.reserved[1:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_next_error_update.fme_first_next_error.reserved "logic fme_csr_fme_next_error_update.fme_first_next_error.reserved[1:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fpmon_fab_ctl.fpmon_fab_ctl.reserved0 "logic fme_csr_fpmon_fab_ctl.fpmon_fab_ctl.reserved0[7:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fpmon_fab_ctl.fpmon_fab_ctl.reserved9 "logic fme_csr_fpmon_fab_ctl.fpmon_fab_ctl.reserved9[6:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl.fpmon_fab_ctl.reserved22 "logic fme_csr_fpmon_fab_ctl.fpmon_fab_ctl.reserved22" +Toggle 1to0 fme_csr_fpmon_fab_ctl.fpmon_fab_ctl.reserved22 "logic fme_csr_fpmon_fab_ctl.fpmon_fab_ctl.reserved22" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fpmon_fab_ctl.fpmon_fab_ctl.reserved24 "logic fme_csr_fpmon_fab_ctl.fpmon_fab_ctl.reserved24[39:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fpmon_fab_ctl_reset.fpmon_fab_ctl.reserved0 "logic fme_csr_fpmon_fab_ctl_reset.fpmon_fab_ctl.reserved0[7:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fpmon_fab_ctl_reset.fpmon_fab_ctl.reserved9 "logic fme_csr_fpmon_fab_ctl_reset.fpmon_fab_ctl.reserved9[6:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.fpmon_fab_ctl.reserved22 "logic fme_csr_fpmon_fab_ctl_reset.fpmon_fab_ctl.reserved22" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.fpmon_fab_ctl.reserved22 "logic fme_csr_fpmon_fab_ctl_reset.fpmon_fab_ctl.reserved22" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fpmon_fab_ctl_reset.fpmon_fab_ctl.reserved24 "logic fme_csr_fpmon_fab_ctl_reset.fpmon_fab_ctl.reserved24[39:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fpmon_fab_ctl_update.fpmon_fab_ctl.reserved0 "logic fme_csr_fpmon_fab_ctl_update.fpmon_fab_ctl.reserved0[7:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fpmon_fab_ctl_update.fpmon_fab_ctl.reserved9 "logic fme_csr_fpmon_fab_ctl_update.fpmon_fab_ctl.reserved9[6:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_update.fpmon_fab_ctl.reserved22 "logic fme_csr_fpmon_fab_ctl_update.fpmon_fab_ctl.reserved22" +Toggle 1to0 fme_csr_fpmon_fab_ctl_update.fpmon_fab_ctl.reserved22 "logic fme_csr_fpmon_fab_ctl_update.fpmon_fab_ctl.reserved22" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fpmon_fab_ctl_update.fpmon_fab_ctl.reserved24 "logic fme_csr_fpmon_fab_ctl_update.fpmon_fab_ctl.reserved24[39:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_capability_reset.glbl_error_capability.reserved13 "logic fme_csr_glbl_error_capability_reset.glbl_error_capability.reserved13[50:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_capability_update.glbl_error_capability.reserved13 "logic fme_csr_glbl_error_capability_update.glbl_error_capability.reserved13[50:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability.fab_capability.reserved8 "logic fme_csr_fab_capability.fab_capability.reserved8[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability.fab_capability.reserved13 "logic fme_csr_fab_capability.fab_capability.reserved13[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability.fab_capability.reserved20 "logic fme_csr_fab_capability.fab_capability.reserved20[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability.fab_capability.reserved30 "logic fme_csr_fab_capability.fab_capability.reserved30[33:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability_reset.fab_capability.reserved8 "logic fme_csr_fab_capability_reset.fab_capability.reserved8[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability_reset.fab_capability.reserved13 "logic fme_csr_fab_capability_reset.fab_capability.reserved13[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability_reset.fab_capability.reserved20 "logic fme_csr_fab_capability_reset.fab_capability.reserved20[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability_reset.fab_capability.reserved30 "logic fme_csr_fab_capability_reset.fab_capability.reserved30[33:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability_update.fab_capability.reserved8 "logic fme_csr_fab_capability_update.fab_capability.reserved8[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability_update.fab_capability.reserved13 "logic fme_csr_fab_capability_update.fab_capability.reserved13[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability_update.fab_capability.reserved20 "logic fme_csr_fab_capability_update.fab_capability.reserved20[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_capability_update.fab_capability.reserved30 "logic fme_csr_fab_capability_update.fab_capability.reserved30[33:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_status_reset.fab_status.reserved0 "logic fme_csr_fab_status_reset.fab_status.reserved0[7:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_status_reset.fab_status.reserved9 "logic fme_csr_fab_status_reset.fab_status.reserved9[54:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_status_update.fab_status.reserved0 "logic fme_csr_fab_status_update.fab_status.reserved0[7:0]" +ANNOTATION: " Read only register whose dafault values are zeros, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fab_status_update.fab_status.reserved9 "logic fme_csr_fab_status_update.fab_status.reserved9[54:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fme_dfh_update.fme_dfh.reserved "logic fme_csr_fme_dfh_update.fme_dfh.reserved[18:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_tmp_threshold_reset.tmp_threshold.reserved16 "logic fme_csr_tmp_threshold_reset.tmp_threshold.reserved16[7:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_fme_dfh_reset.fme_dfh.reserved "logic fme_csr_fme_dfh_reset.fme_dfh.reserved[18:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_bitstream_md_update.bitstream_md.reserved28 "logic fme_csr_bitstream_md_update.bitstream_md.reserved28[35:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_bitstream_id_update.bitstream_id.reserved36 "logic fme_csr_bitstream_id_update.bitstream_id.reserved36[3:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_perf_dfh_update.dfh.reserved "logic fme_csr_glbl_perf_dfh_update.dfh.reserved[18:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_dfh_update.dfh.reserved "logic fme_csr_glbl_error_dfh_update.dfh.reserved[18:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_error_dfh_reset.dfh.reserved "logic fme_csr_glbl_error_dfh_reset.dfh.reserved[18:0]" +ANNOTATION: " Read only register with dafault values, cannot toggle and reserved fields are excluded. " +Toggle fme_csr_glbl_perf_dfh_reset.dfh.reserved "logic fme_csr_glbl_perf_dfh_reset.dfh.reserved[18:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle rom_data "logic rom_data[63:0]" +Toggle 1to0 wr_reg_offset [7] "logic wr_reg_offset[8:0]" +Toggle 0to1 wr_reg_offset [7] "logic wr_reg_offset[8:0]" +Toggle 1to0 wr_reg_offset [6] "logic wr_reg_offset[8:0]" +Toggle 0to1 wr_reg_offset [6] "logic wr_reg_offset[8:0]" +Toggle 1to0 wr_reg_offset [5] "logic wr_reg_offset[8:0]" +Toggle 0to1 wr_reg_offset [5] "logic wr_reg_offset[8:0]" +Toggle 1to0 wr_reg_offset [8] "logic wr_reg_offset[8:0]" +Toggle 0to1 wr_reg_offset [8] "logic wr_reg_offset[8:0]" +Toggle 1to0 araddr_reg [0] "logic araddr_reg[19:0]" +Toggle 0to1 araddr_reg [0] "logic araddr_reg[19:0]" +Toggle 1to0 araddr_reg [11] "logic araddr_reg[19:0]" +Toggle 0to1 araddr_reg [11] "logic araddr_reg[19:0]" +Toggle 1to0 araddr_reg [10] "logic araddr_reg[19:0]" +Toggle 0to1 araddr_reg [10] "logic araddr_reg[19:0]" +Toggle 1to0 araddr_reg [9] "logic araddr_reg[19:0]" +Toggle 0to1 araddr_reg [9] "logic araddr_reg[19:0]" +Toggle 1to0 araddr_reg [19] "logic araddr_reg[19:0]" +Toggle 0to1 araddr_reg [19] "logic araddr_reg[19:0]" +Toggle 1to0 araddr_reg [18] "logic araddr_reg[19:0]" +Toggle 0to1 araddr_reg [18] "logic araddr_reg[19:0]" +Toggle 1to0 araddr_reg [17] "logic araddr_reg[19:0]" +Toggle 0to1 araddr_reg [17] "logic araddr_reg[19:0]" +Toggle 1to0 araddr_reg [16] "logic araddr_reg[19:0]" +Toggle 0to1 araddr_reg [16] "logic araddr_reg[19:0]" +Toggle 1to0 araddr_reg [15] "logic araddr_reg[19:0]" +Toggle 0to1 araddr_reg [15] "logic araddr_reg[19:0]" +Toggle 1to0 araddr_reg [1] "logic araddr_reg[19:0]" +Toggle 0to1 araddr_reg [1] "logic araddr_reg[19:0]" +Toggle 1to0 awaddr_reg [0] "logic awaddr_reg[19:0]" +Toggle 0to1 awaddr_reg [0] "logic awaddr_reg[19:0]" +Toggle 1to0 awaddr_reg [11] "logic awaddr_reg[19:0]" +Toggle 0to1 awaddr_reg [11] "logic awaddr_reg[19:0]" +Toggle 1to0 awaddr_reg [10] "logic awaddr_reg[19:0]" +Toggle 0to1 awaddr_reg [10] "logic awaddr_reg[19:0]" +Toggle 1to0 awaddr_reg [9] "logic awaddr_reg[19:0]" +Toggle 0to1 awaddr_reg [9] "logic awaddr_reg[19:0]" +Toggle 1to0 awaddr_reg [8] "logic awaddr_reg[19:0]" +Toggle 0to1 awaddr_reg [8] "logic awaddr_reg[19:0]" +Toggle 1to0 awaddr_reg [19] "logic awaddr_reg[19:0]" +Toggle 0to1 awaddr_reg [19] "logic awaddr_reg[19:0]" +Toggle 1to0 awaddr_reg [18] "logic awaddr_reg[19:0]" +Toggle 0to1 awaddr_reg [18] "logic awaddr_reg[19:0]" +Toggle 1to0 awaddr_reg [17] "logic awaddr_reg[19:0]" +Toggle 0to1 awaddr_reg [17] "logic awaddr_reg[19:0]" +Toggle 1to0 awaddr_reg [16] "logic awaddr_reg[19:0]" +Toggle 0to1 awaddr_reg [16] "logic awaddr_reg[19:0]" +Toggle 1to0 awaddr_reg [15] "logic awaddr_reg[19:0]" +Toggle 0to1 awaddr_reg [15] "logic awaddr_reg[19:0]" +Toggle 1to0 awaddr_reg [1] "logic awaddr_reg[19:0]" +Toggle 0to1 awaddr_reg [1] "logic awaddr_reg[19:0]" +Toggle 1to0 arsize_reg [2] "logic arsize_reg[2:0]" +Toggle 0to1 arsize_reg [2] "logic arsize_reg[2:0]" +Toggle 1to0 awsize_reg [2] "logic awsize_reg[2:0]" +Toggle 0to1 awsize_reg [2] "logic awsize_reg[2:0]" +Toggle 1to0 wr_feature_id [3] "logic wr_feature_id[3:0]" +Toggle 0to1 wr_feature_id [3] "logic wr_feature_id[3:0]" +Toggle 1to0 rd_feature_id [3] "logic rd_feature_id[3:0]" +Toggle 0to1 rd_feature_id [3] "logic rd_feature_id[3:0]" +Toggle 0to1 fme_csr_port0_offset_reset.port_offset.afu_access_ctrl "logic fme_csr_port0_offset_reset.port_offset.afu_access_ctrl" +Toggle 1to0 fme_csr_port0_offset_reset.port_offset.afu_access_ctrl "logic fme_csr_port0_offset_reset.port_offset.afu_access_ctrl" +Toggle 0to1 rd_next [0] "logic rd_next[4:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [63] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [63] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [3] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [3] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [4] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [4] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [5] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [5] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [6] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [6] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [7] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [7] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [8] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [8] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [9] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [9] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [10] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [10] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [11] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [11] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [12] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [12] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [13] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [13] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [14] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [14] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [15] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [15] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [16] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [16] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [17] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [17] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [18] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [18] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [19] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [19] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [20] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [20] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [21] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [21] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [22] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [22] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [23] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [23] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [24] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [24] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [25] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [25] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [26] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [26] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [27] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [27] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [28] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [28] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [29] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [29] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [30] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [30] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [31] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [31] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [32] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [32] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [33] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [33] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [34] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [34] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [35] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [35] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [36] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [36] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [37] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [37] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [38] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [38] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [39] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [39] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [40] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [40] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [41] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [41] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [42] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [42] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [43] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [43] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [44] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [44] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [45] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [45] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [46] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [46] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [47] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [47] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [48] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [48] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [49] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [49] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [50] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [50] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [51] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [51] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [52] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [52] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [53] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [53] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [54] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [54] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [55] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [55] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [56] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [56] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [57] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [57] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [58] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [58] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [59] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [59] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [60] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [60] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [61] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [61] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj.data [62] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj.data [62] "logic fme_csr_ras_error_inj.data[63:0]" +Toggle 0to1 ras_grnerr_masked [63] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [63] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [0] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [0] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [1] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [1] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [2] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [2] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [3] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [3] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [4] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [4] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [5] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [5] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [7] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [7] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [8] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [8] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [9] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [9] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [10] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [10] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [11] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [11] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [12] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [12] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [13] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [13] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [14] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [14] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [15] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [15] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [16] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [16] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [17] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [17] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [18] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [18] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [19] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [19] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [20] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [20] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [21] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [21] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [22] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [22] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [23] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [23] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [24] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [24] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [25] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [25] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [26] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [26] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [27] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [27] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [28] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [28] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [29] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [29] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [30] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [30] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [31] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [31] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [32] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [32] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [33] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [33] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [34] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [34] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [35] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [35] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [36] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [36] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [37] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [37] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [38] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [38] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [39] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [39] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [40] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [40] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [41] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [41] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [42] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [42] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [43] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [43] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [44] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [44] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [45] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [45] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [46] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [46] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [47] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [47] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [48] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [48] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [49] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [49] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [50] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [50] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [51] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [51] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [52] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [52] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [53] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [53] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [54] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [54] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [55] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [55] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [56] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [56] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [57] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [57] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [58] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [58] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [59] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [59] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [60] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [60] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [61] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [61] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_grnerr_masked [62] "logic ras_grnerr_masked[63:0]" +Toggle 1to0 ras_grnerr_masked [62] "logic ras_grnerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [63] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [63] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [0] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [0] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [1] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [1] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [2] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [2] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [3] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [3] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [4] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [4] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [5] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [5] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [6] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [6] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [7] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [7] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [10] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [10] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [12] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [12] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [13] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [13] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [14] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [14] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [15] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [15] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [16] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [16] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [17] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [17] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [18] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [18] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [19] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [19] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [20] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [20] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [21] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [21] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [22] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [22] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [23] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [23] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [24] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [24] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [25] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [25] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [26] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [26] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [27] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [27] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [28] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [28] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [29] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [29] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [30] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [30] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [31] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [31] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [32] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [32] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [33] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [33] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [34] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [34] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [35] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [35] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [36] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [36] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [37] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [37] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [38] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [38] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [39] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [39] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [40] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [40] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [41] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [41] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [42] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [42] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [43] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [43] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [44] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [44] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [45] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [45] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [46] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [46] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [47] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [47] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [48] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [48] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [49] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [49] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [50] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [50] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [51] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [51] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [52] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [52] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [53] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [53] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [54] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [54] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [55] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [55] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [56] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [56] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [57] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [57] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [58] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [58] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [59] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [59] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [60] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [60] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [61] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [61] "logic ras_bluerr_masked[63:0]" +Toggle 0to1 ras_bluerr_masked [62] "logic ras_bluerr_masked[63:0]" +Toggle 1to0 ras_bluerr_masked [62] "logic ras_bluerr_masked[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_nofat_error_update.word.upper32 "logic fme_csr_ras_nofat_error_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [31] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [31] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [0] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [0] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [1] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [1] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [2] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [2] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [3] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [3] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [4] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [4] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [5] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [5] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [7] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [7] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [8] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [8] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [9] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [9] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [10] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [10] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [11] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [11] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [12] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [12] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [13] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [13] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [14] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [14] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [15] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [15] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [16] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [16] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [17] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [17] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [18] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [18] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [19] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [19] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [20] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [20] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [21] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [21] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [22] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [22] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [23] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [23] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [24] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [24] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [25] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [25] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [26] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [26] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [27] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [27] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [28] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [28] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [29] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [29] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.word.lower32 [30] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.word.lower32 [30] "logic fme_csr_ras_nofat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.ras_nofat_error.afu_access_mode_error "logic fme_csr_ras_nofat_error_update.ras_nofat_error.afu_access_mode_error" +Toggle 1to0 fme_csr_ras_nofat_error_update.ras_nofat_error.afu_access_mode_error "logic fme_csr_ras_nofat_error_update.ras_nofat_error.afu_access_mode_error" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [63] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [63] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [0] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [0] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [1] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [1] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [2] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [2] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [3] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [3] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [4] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [4] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [5] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [5] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [7] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [7] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [8] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [8] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [9] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [9] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [10] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [10] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [11] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [11] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [12] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [12] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [13] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [13] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [14] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [14] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [15] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [15] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [16] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [16] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [17] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [17] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [18] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [18] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [19] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [19] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [20] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [20] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [21] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [21] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [22] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [22] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [23] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [23] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [24] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [24] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [25] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [25] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [26] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [26] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [27] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [27] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [28] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [28] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [29] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [29] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [30] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [30] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [31] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [31] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [32] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [32] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [33] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [33] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [34] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [34] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [35] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [35] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [36] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [36] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [37] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [37] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [38] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [38] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [39] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [39] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [40] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [40] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [41] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [41] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [42] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [42] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [43] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [43] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [44] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [44] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [45] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [45] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [46] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [46] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [47] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [47] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [48] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [48] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [49] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [49] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [50] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [50] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [51] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [51] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [52] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [52] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [53] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [53] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [54] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [54] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [55] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [55] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [56] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [56] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [57] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [57] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [58] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [58] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [59] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [59] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [60] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [60] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [61] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [61] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_update.data [62] "logic fme_csr_ras_nofat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_update.data [62] "logic fme_csr_ras_nofat_error_update.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_nofat_error_reset.word.upper32 "logic fme_csr_ras_nofat_error_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [31] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [31] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [0] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [0] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [1] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [1] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [2] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [2] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [3] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [3] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [4] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [4] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [5] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [5] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [7] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [7] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [8] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [8] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [9] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [9] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [10] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [10] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [11] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [11] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [12] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [12] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [13] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [13] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [14] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [14] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [15] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [15] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [16] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [16] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [17] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [17] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [18] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [18] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [19] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [19] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [20] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [20] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [21] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [21] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [22] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [22] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [23] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [23] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [24] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [24] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [25] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [25] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [26] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [26] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [27] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [27] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [28] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [28] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [29] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [29] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.word.lower32 [30] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.word.lower32 [30] "logic fme_csr_ras_nofat_error_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [3] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [3] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [5] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [5] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_reset.data [2] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error_reset.data [2] "logic fme_csr_ras_nofat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [3] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [3] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [5] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [5] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error_mask_update.word.lower32 [2] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error_mask_update.word.lower32 [2] "logic fme_csr_ras_nofat_error_mask_update.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_nofat_error.word.upper32 "logic fme_csr_ras_nofat_error.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [31] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [31] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [0] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [0] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [1] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [1] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [2] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [2] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [3] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [3] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [4] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [4] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [5] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [5] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [7] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [7] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [8] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [8] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [9] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [9] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [10] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [10] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [11] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [11] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [12] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [12] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [13] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [13] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [14] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [14] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [15] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [15] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [16] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [16] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [17] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [17] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [18] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [18] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [19] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [19] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [20] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [20] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [21] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [21] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [22] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [22] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [23] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [23] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [24] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [24] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [25] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [25] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [26] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [26] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [27] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [27] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [28] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [28] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [29] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [29] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.word.lower32 [30] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_nofat_error.word.lower32 [30] "logic fme_csr_ras_nofat_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [63] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [63] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [0] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [0] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [1] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [1] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [2] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [2] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [3] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [3] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [4] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [4] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [5] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [5] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [7] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [7] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [8] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [8] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [9] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [9] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [10] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [10] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [11] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [11] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [12] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [12] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [13] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [13] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [14] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [14] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [15] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [15] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [16] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [16] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [17] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [17] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [18] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [18] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [19] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [19] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [20] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [20] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [21] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [21] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [22] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [22] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [23] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [23] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [24] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [24] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [25] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [25] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [26] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [26] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [27] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [27] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [28] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [28] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [29] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [29] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [30] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [30] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [31] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [31] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [32] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [32] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [33] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [33] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [34] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [34] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [35] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [35] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [36] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [36] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [37] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [37] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [38] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [38] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [39] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [39] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [40] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [40] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [41] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [41] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [42] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [42] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [43] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [43] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [44] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [44] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [45] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [45] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [46] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [46] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [47] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [47] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [48] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [48] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [49] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [49] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [50] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [50] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [51] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [51] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [52] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [52] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [53] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [53] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [54] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [54] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [55] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [55] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [56] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [56] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [57] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [57] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [58] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [58] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [59] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [59] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [60] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [60] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [61] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [61] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_nofat_error.data [62] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_nofat_error.data [62] "logic fme_csr_ras_nofat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [31] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [31] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [0] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [0] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [1] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [1] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [2] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [2] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [3] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [3] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [4] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [4] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [5] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [5] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [6] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [6] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [7] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [7] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [8] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [8] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [9] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [9] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [10] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [10] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [11] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [11] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [12] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [12] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [13] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [13] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [14] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [14] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [15] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [15] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [16] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [16] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [17] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [17] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [18] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [18] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [19] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [19] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [20] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [20] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [21] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [21] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [22] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [22] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [23] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [23] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [24] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [24] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [25] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [25] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [26] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [26] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [27] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [27] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [28] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [28] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [29] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [29] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.upper32 [30] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.upper32 [30] "logic fme_csr_ras_error_inj_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [31] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [31] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [3] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [3] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [4] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [4] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [5] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [5] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [6] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [6] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [7] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [7] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [8] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [8] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [9] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [9] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [10] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [10] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [11] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [11] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [12] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [12] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [13] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [13] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [14] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [14] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [15] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [15] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [16] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [16] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [17] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [17] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [18] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [18] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [19] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [19] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [20] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [20] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [21] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [21] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [22] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [22] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [23] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [23] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [24] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [24] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [25] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [25] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [26] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [26] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [27] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [27] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [28] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [28] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [29] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [29] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.word.lower32 [30] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.word.lower32 [30] "logic fme_csr_ras_error_inj_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [63] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [63] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [3] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [3] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [4] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [4] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [5] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [5] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [6] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [6] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [7] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [7] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [8] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [8] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [9] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [9] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [10] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [10] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [11] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [11] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [12] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [12] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [13] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [13] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [14] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [14] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [15] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [15] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [16] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [16] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [17] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [17] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [18] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [18] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [19] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [19] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [20] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [20] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [21] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [21] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [22] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [22] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [23] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [23] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [24] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [24] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [25] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [25] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [26] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [26] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [27] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [27] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [28] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [28] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [29] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [29] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [30] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [30] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [31] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [31] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [32] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [32] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [33] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [33] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [34] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [34] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [35] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [35] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [36] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [36] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [37] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [37] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [38] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [38] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [39] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [39] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [40] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [40] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [41] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [41] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [42] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [42] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [43] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [43] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [44] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [44] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [45] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [45] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [46] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [46] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [47] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [47] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [48] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [48] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [49] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [49] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [50] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [50] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [51] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [51] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [52] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [52] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [53] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [53] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [54] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [54] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [55] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [55] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [56] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [56] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [57] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [57] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [58] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [58] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [59] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [59] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [60] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [60] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [61] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [61] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_update.data [62] "logic fme_csr_ras_error_inj_update.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_update.data [62] "logic fme_csr_ras_error_inj_update.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_error_inj_reset.word.upper32 "logic fme_csr_ras_error_inj_reset.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_error_inj_reset.word.lower32 "logic fme_csr_ras_error_inj_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [63] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [63] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [3] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [3] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [4] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [4] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [5] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [5] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [6] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [6] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [7] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [7] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [8] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [8] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [9] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [9] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [10] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [10] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [11] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [11] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [12] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [12] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [13] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [13] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [14] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [14] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [15] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [15] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [16] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [16] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [17] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [17] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [18] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [18] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [19] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [19] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [20] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [20] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [21] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [21] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [22] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [22] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [23] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [23] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [24] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [24] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [25] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [25] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [26] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [26] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [27] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [27] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [28] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [28] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [29] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [29] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [30] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [30] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [31] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [31] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [32] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [32] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [33] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [33] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [34] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [34] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [35] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [35] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [36] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [36] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [37] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [37] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [38] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [38] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [39] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [39] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [40] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [40] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [41] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [41] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [42] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [42] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [43] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [43] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [44] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [44] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [45] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [45] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [46] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [46] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [47] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [47] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [48] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [48] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [49] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [49] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [50] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [50] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [51] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [51] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [52] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [52] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [53] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [53] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [54] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [54] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [55] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [55] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [56] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [56] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [57] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [57] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [58] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [58] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [59] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [59] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [60] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [60] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [61] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [61] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_error_inj_reset.data [62] "logic fme_csr_ras_error_inj_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_error_inj_reset.data [62] "logic fme_csr_ras_error_inj_reset.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_error_inj.word.upper32 "logic fme_csr_ras_error_inj.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [31] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [31] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [0] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [0] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [1] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [1] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [2] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [2] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [3] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [3] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [4] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [4] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [5] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [5] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [6] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [6] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [7] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [7] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [10] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [10] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [12] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [12] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [13] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [13] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [14] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [14] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [15] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [15] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [16] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [16] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [17] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [17] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [18] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [18] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [19] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [19] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [20] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [20] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [21] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [21] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [22] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [22] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [23] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [23] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [24] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [24] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [25] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [25] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [26] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [26] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [27] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [27] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [28] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [28] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [29] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [29] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.word.lower32 [30] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.word.lower32 [30] "logic fme_csr_ras_catfat_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [63] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [63] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [0] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [0] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [1] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [1] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [2] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [2] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [3] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [3] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [4] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [4] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [5] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [5] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [6] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [6] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [7] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [7] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [10] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [10] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [12] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [12] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [13] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [13] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [14] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [14] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [15] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [15] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [16] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [16] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [17] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [17] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [18] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [18] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [19] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [19] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [20] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [20] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [21] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [21] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [22] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [22] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [23] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [23] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [24] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [24] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [25] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [25] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [26] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [26] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [27] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [27] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [28] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [28] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [29] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [29] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [30] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [30] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [31] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [31] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [32] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [32] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [33] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [33] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [34] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [34] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [35] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [35] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [36] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [36] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [37] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [37] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [38] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [38] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [39] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [39] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [40] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [40] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [41] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [41] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [42] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [42] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [43] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [43] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [44] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [44] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [45] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [45] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [46] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [46] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [47] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [47] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [48] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [48] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [49] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [49] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [50] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [50] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [51] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [51] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [52] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [52] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [53] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [53] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [54] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [54] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [55] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [55] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [56] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [56] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [57] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [57] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [58] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [58] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [59] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [59] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [60] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [60] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [61] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [61] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_update.data [62] "logic fme_csr_ras_catfat_error_update.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_update.data [62] "logic fme_csr_ras_catfat_error_update.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_catfat_error_reset.word.lower32 "logic fme_csr_ras_catfat_error_reset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_ras_catfat_error_reset.word.upper32 "logic fme_csr_ras_catfat_error_reset.word.upper32[31:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [63] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [63] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [0] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [0] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [1] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [1] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [2] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [2] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [3] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [3] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [4] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [4] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [5] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [5] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [6] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [6] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [7] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [7] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [10] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [10] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [12] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [12] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [13] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [13] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [14] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [14] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [15] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [15] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [16] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [16] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [17] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [17] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [18] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [18] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [19] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [19] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [20] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [20] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [21] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [21] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [22] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [22] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [23] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [23] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [24] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [24] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [25] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [25] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [26] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [26] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [27] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [27] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [28] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [28] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [29] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [29] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [30] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [30] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [31] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [31] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [32] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [32] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [33] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [33] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [34] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [34] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [35] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [35] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [36] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [36] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [37] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [37] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [38] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [38] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [39] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [39] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [40] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [40] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [41] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [41] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [42] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [42] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [43] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [43] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [44] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [44] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [45] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [45] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [46] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [46] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [47] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [47] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [48] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [48] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [49] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [49] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [50] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [50] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [51] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [51] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [52] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [52] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [53] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [53] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [54] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [54] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [55] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [55] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [56] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [56] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [57] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [57] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [58] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [58] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [59] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [59] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [60] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [60] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [61] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [61] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error_reset.data [62] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error_reset.data [62] "logic fme_csr_ras_catfat_error_reset.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [63] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [63] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [0] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [0] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [1] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [1] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [2] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [2] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [3] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [3] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [4] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [4] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [5] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [5] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [6] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [6] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [7] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [7] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [10] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [10] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [12] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [12] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [13] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [13] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [14] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [14] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [15] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [15] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [16] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [16] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [17] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [17] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [18] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [18] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [19] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [19] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [20] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [20] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [21] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [21] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [22] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [22] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [23] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [23] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [24] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [24] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [25] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [25] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [26] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [26] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [27] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [27] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [28] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [28] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [29] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [29] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [30] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [30] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [31] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [31] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [32] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [32] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [33] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [33] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [34] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [34] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [35] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [35] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [36] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [36] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [37] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [37] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [38] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [38] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [39] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [39] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [40] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [40] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [41] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [41] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [42] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [42] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [43] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [43] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [44] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [44] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [45] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [45] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [46] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [46] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [47] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [47] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [48] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [48] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [49] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [49] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [50] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [50] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [51] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [51] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [52] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [52] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [53] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [53] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [54] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [54] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [55] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [55] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [56] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [56] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [57] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [57] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [58] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [58] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [59] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [59] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [60] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [60] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [61] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [61] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_ras_catfat_error.data [62] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 1to0 fme_csr_ras_catfat_error.data [62] "logic fme_csr_ras_catfat_error.data[63:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [31] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [31] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [0] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [0] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [1] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [1] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [2] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [2] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [3] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [3] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [4] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [4] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [5] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [5] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [6] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [6] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [7] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [7] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [9] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [9] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [10] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [10] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [11] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [11] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [12] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [12] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [13] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [13] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [14] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [14] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [15] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [15] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [22] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [22] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [24] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [24] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [25] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [25] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [26] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [26] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [27] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [27] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [28] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [28] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [29] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [29] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fpmon_fab_ctl_reset.word.lower32 [30] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fpmon_fab_ctl_reset.word.lower32 [30] "logic fme_csr_fpmon_fab_ctl_reset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fpmon_fab_ctl.word.upper32 "logic fme_csr_fpmon_fab_ctl.word.upper32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [31] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [31] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [2] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [2] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [3] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [3] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [4] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [4] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [6] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [6] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [7] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [7] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [8] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [8] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [9] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [9] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [10] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [10] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [11] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [11] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [12] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [12] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [13] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [13] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [14] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [14] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [15] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [15] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [16] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [16] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [17] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [17] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [18] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [18] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [19] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [19] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [20] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [20] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [21] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [21] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [22] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [22] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [23] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [23] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [24] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [24] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [25] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [25] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [26] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [26] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [27] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [27] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [28] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [28] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [29] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [29] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_error_mask0_reset.word.lower32 [30] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_error_mask0_reset.word.lower32 [30] "logic fme_csr_fme_error_mask0_reset.word.lower32[31:0]" +Toggle 0to1 rd_state [0] "logic rd_state[4:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error_update.pcie0_error.reserved "logic fme_csr_pcie0_error_update.pcie0_error.reserved[63:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error.pcie0_error.reserved "logic fme_csr_pcie0_error.pcie0_error.reserved[63:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error_mask.pcie0_error_mask.reserved "logic fme_csr_pcie0_error_mask.pcie0_error_mask.reserved[63:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error_mask_reset.pcie0_error_mask.reserved "logic fme_csr_pcie0_error_mask_reset.pcie0_error_mask.reserved[63:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error_mask_update.pcie0_error_mask.reserved "logic fme_csr_pcie0_error_mask_update.pcie0_error_mask.reserved[63:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error_reset.pcie0_error.reserved "logic fme_csr_pcie0_error_reset.pcie0_error.reserved[63:0]" +ANNOTATION: " Assigned to RESERVED_2_IDX " +Toggle FME_ID_MEM_MAX "bit FME_ID_MEM_MAX[2:0]" +Toggle fme_csr_bitstream_info_reset.bitstream_info.reserved32 "logic fme_csr_bitstream_info_reset.bitstream_info.reserved32[31:0]" +Toggle fme_csr_bitstream_info_reset.bitstream_info.fim_variant_revision "logic fme_csr_bitstream_info_reset.bitstream_info.fim_variant_revision[31:0]" +ANNOTATION: " Upper32 bits of bitstream info register are rsvd and lower 32 bits are R0 " +Toggle fme_csr_bitstream_info_reset.data "logic fme_csr_bitstream_info_reset.data[63:0]" +ANNOTATION: " Upper32 bits of bitstream info register are rsvd and lower 32 bits are R0 " +Toggle fme_csr_bitstream_info_update.word.upper32 "logic fme_csr_bitstream_info_update.word.upper32[31:0]" +ANNOTATION: " Upper32 bits of bitstream info register are rsvd and lower 32 bits are R0 " +Toggle fme_csr_bitstream_info_update.word.lower32 "logic fme_csr_bitstream_info_update.word.lower32[31:0]" +ANNOTATION: " Upper32 bits of bitstream info register are rsvd and lower 32 bits are R0 " +Toggle fme_csr_bitstream_info_update.data "logic fme_csr_bitstream_info_update.data[63:0]" +ANNOTATION: " Upper32 bits of bitstream info register are rsvd and lower 32 bits are R0 " +Toggle fme_csr_bitstream_info_update.bitstream_info.reserved32 "logic fme_csr_bitstream_info_update.bitstream_info.reserved32[31:0]" +ANNOTATION: " Upper32 bits of bitstream info register are rsvd and lower 32 bits are R0 " +Toggle fme_csr_bitstream_info_update.bitstream_info.fim_variant_revision "logic fme_csr_bitstream_info_update.bitstream_info.fim_variant_revision[31:0]" +ANNOTATION: " Upper32 bits of bitstream info register are rsvd and lower 32 bits are R0 " +Toggle fme_csr_bitstream_info_reset.word.upper32 "logic fme_csr_bitstream_info_reset.word.upper32[31:0]" +ANNOTATION: " Upper32 bits of bitstream info register are rsvd and lower 32 bits are R0 " +Toggle fme_csr_bitstream_info_reset.word.lower32 "logic fme_csr_bitstream_info_reset.word.lower32[31:0]" +CHECKSUM: "2402049597 748327626" +INSTANCE: tb_top.DUT.fme_top.axi_mmio_if +Toggle 1to0 rresp [1] "logic rresp[1:0]" +Toggle 0to1 rresp [1] "logic rresp[1:0]" +Toggle 1to0 bresp [1] "logic bresp[1:0]" +Toggle 0to1 bresp [1] "logic bresp[1:0]" +Toggle arprot "logic arprot[2:0]" +Toggle awprot "logic awprot[2:0]" +ANNOTATION: " Axi related signals that are not used, so excluding " +Toggle arlen "logic arlen[7:0]" +ANNOTATION: " Axi related signals that are not used, so excluding " +Toggle arqos "logic arqos[3:0]" +ANNOTATION: " Axi related signals that are not used, so excluding " +Toggle awid "logic awid[9:0]" +ANNOTATION: " Axi related signals that are not used, so excluding " +Toggle awqos "logic awqos[3:0]" +ANNOTATION: " Axi related signals that are not used, so excluding " +Toggle bid "logic bid[9:0]" +ANNOTATION: " Axi related signals that are not used, so excluding " +Toggle rid "logic rid[9:0]" +ANNOTATION: " Axi related signals that are not used, so excluding " +Toggle arid "logic arid[9:0]" +ANNOTATION: " Axi related signals that are not used, so excluding " +Toggle arcache "logic arcache[3:0]" +Toggle 1to0 arlock "logic arlock" +Toggle 0to1 arlock "logic arlock" +Toggle 1to0 aruser [0] "logic aruser[0:0]" +Toggle 0to1 aruser [0] "logic aruser[0:0]" +ANNOTATION: " Axi related signals that are not used, so excluding " +Toggle awburst "logic awburst[1:0]" +ANNOTATION: " Axi related signals that are not used, so excluding " +Toggle awcache "logic awcache[3:0]" +ANNOTATION: " Axi related signals that are not used, so excluding " +Toggle awlen "logic awlen[7:0]" +Toggle 1to0 awlock "logic awlock" +Toggle 0to1 awlock "logic awlock" +Toggle 1to0 awuser [0] "logic awuser[0:0]" +Toggle 0to1 awuser [0] "logic awuser[0:0]" +Toggle 1to0 buser [0] "logic buser[0:0]" +Toggle 0to1 buser [0] "logic buser[0:0]" +Toggle 1to0 ruser [0] "logic ruser[0:0]" +Toggle 0to1 ruser [0] "logic ruser[0:0]" +Toggle 1to0 wlast "logic wlast" +Toggle 0to1 wlast "logic wlast" +Toggle 1to0 wuser [0] "logic wuser[0:0]" +Toggle 0to1 wuser [0] "logic wuser[0:0]" +ANNOTATION: " Axi related signals that are not used, so excluding " +Toggle arburst "logic arburst[1:0]" +Toggle 1to0 arsize [1] "logic arsize[2:0]" +Toggle 0to1 arsize [1] "logic arsize[2:0]" +Toggle 1to0 arsize [2] "logic arsize[2:0]" +Toggle 0to1 arsize [2] "logic arsize[2:0]" +Toggle 1to0 awsize [1] "logic awsize[2:0]" +Toggle 0to1 awsize [1] "logic awsize[2:0]" +Toggle 1to0 awsize [2] "logic awsize[2:0]" +Toggle 0to1 awsize [2] "logic awsize[2:0]" +Toggle 1to0 rresp [0] "logic rresp[1:0]" +Toggle 0to1 rresp [0] "logic rresp[1:0]" +Toggle 1to0 bresp [0] "logic bresp[1:0]" +Toggle 0to1 bresp [0] "logic bresp[1:0]" +Toggle 1to0 araddr [19] "logic araddr[20:0]" +Toggle 0to1 araddr [19] "logic araddr[20:0]" +Toggle 1to0 araddr [18] "logic araddr[20:0]" +Toggle 0to1 araddr [18] "logic araddr[20:0]" +Toggle 1to0 araddr [17] "logic araddr[20:0]" +Toggle 0to1 araddr [17] "logic araddr[20:0]" +Toggle 1to0 araddr [16] "logic araddr[20:0]" +Toggle 0to1 araddr [16] "logic araddr[20:0]" +Toggle 1to0 araddr [15] "logic araddr[20:0]" +Toggle 0to1 araddr [15] "logic araddr[20:0]" +Toggle 1to0 araddr [11] "logic araddr[20:0]" +Toggle 0to1 araddr [11] "logic araddr[20:0]" +Toggle 1to0 araddr [10] "logic araddr[20:0]" +Toggle 0to1 araddr [10] "logic araddr[20:0]" +Toggle 1to0 araddr [9] "logic araddr[20:0]" +Toggle 0to1 araddr [9] "logic araddr[20:0]" +Toggle 1to0 araddr [1] "logic araddr[20:0]" +Toggle 0to1 araddr [1] "logic araddr[20:0]" +Toggle 1to0 araddr [0] "logic araddr[20:0]" +Toggle 0to1 araddr [0] "logic araddr[20:0]" +Toggle 1to0 araddr [20] "logic araddr[20:0]" +Toggle 0to1 araddr [20] "logic araddr[20:0]" +Toggle 1to0 awaddr [19] "logic awaddr[20:0]" +Toggle 0to1 awaddr [19] "logic awaddr[20:0]" +Toggle 1to0 awaddr [18] "logic awaddr[20:0]" +Toggle 0to1 awaddr [18] "logic awaddr[20:0]" +Toggle 1to0 awaddr [17] "logic awaddr[20:0]" +Toggle 0to1 awaddr [17] "logic awaddr[20:0]" +Toggle 1to0 awaddr [16] "logic awaddr[20:0]" +Toggle 0to1 awaddr [16] "logic awaddr[20:0]" +Toggle 1to0 awaddr [15] "logic awaddr[20:0]" +Toggle 0to1 awaddr [15] "logic awaddr[20:0]" +Toggle 1to0 awaddr [11] "logic awaddr[20:0]" +Toggle 0to1 awaddr [11] "logic awaddr[20:0]" +Toggle 1to0 awaddr [10] "logic awaddr[20:0]" +Toggle 0to1 awaddr [10] "logic awaddr[20:0]" +Toggle 1to0 awaddr [9] "logic awaddr[20:0]" +Toggle 0to1 awaddr [9] "logic awaddr[20:0]" +Toggle 1to0 awaddr [8] "logic awaddr[20:0]" +Toggle 0to1 awaddr [8] "logic awaddr[20:0]" +Toggle 1to0 awaddr [1] "logic awaddr[20:0]" +Toggle 0to1 awaddr [1] "logic awaddr[20:0]" +Toggle 1to0 awaddr [0] "logic awaddr[20:0]" +Toggle 0to1 awaddr [0] "logic awaddr[20:0]" +Toggle 1to0 awaddr [20] "logic awaddr[20:0]" +Toggle 0to1 awaddr [20] "logic awaddr[20:0]" +CHECKSUM: "694569773 1330229756" +INSTANCE: tb_top.DUT.fme_top +Toggle 1to0 fme_err_regs [5] "logic fme_err_regs[6:0]" +Toggle 0to1 fme_err_regs [5] "logic fme_err_regs[6:0]" +Toggle 1to0 i_pcie_error [1] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [1] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [2] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [2] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [3] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [3] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [4] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [4] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [5] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [5] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [6] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [6] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [7] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [7] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [8] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [8] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [9] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [9] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [10] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [10] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [11] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [11] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [12] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [12] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [13] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [13] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [14] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [14] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [15] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [15] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [0] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [0] "logic i_pcie_error[31:0]" +Toggle 1to0 ras2csr_bluerr [9] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [9] "logic ras2csr_bluerr[63:0]" +Toggle cr2out_fme_sclr "logic cr2out_fme_sclr[19:0]" +Toggle 1to0 fme_sclr "logic fme_sclr" +Toggle 0to1 fme_sclr "logic fme_sclr" +Toggle 1to0 i_pcie_error [30] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [30] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [29] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [29] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [28] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [28] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [27] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [27] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [26] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [26] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [25] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [25] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [24] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [24] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [23] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [23] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [22] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [22] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [21] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [21] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [20] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [20] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [19] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [19] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [18] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [18] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [17] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [17] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [16] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [16] "logic i_pcie_error[31:0]" +Toggle 1to0 i_pcie_error [31] "logic i_pcie_error[31:0]" +Toggle 0to1 i_pcie_error [31] "logic i_pcie_error[31:0]" +Toggle 1to0 pr_parity_error "net pr_parity_error" +Toggle 0to1 pr_parity_error "net pr_parity_error" +Toggle 1to0 cr2out_nonfat_sclr "logic cr2out_nonfat_sclr" +Toggle 0to1 cr2out_nonfat_sclr "logic cr2out_nonfat_sclr" +Toggle fme_sclr_regs "logic fme_sclr_regs[3:0]" +Toggle cr2out_pcie0_sclr "logic cr2out_pcie0_sclr[12:0]" +Toggle 1to0 cr2out_fat_sclr "logic cr2out_fat_sclr" +Toggle 0to1 cr2out_fat_sclr "logic cr2out_fat_sclr" +Toggle 1to0 ras2csr_grnerr [62] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [62] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [61] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [61] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [60] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [60] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [59] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [59] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [58] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [58] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [57] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [57] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [56] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [56] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [55] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [55] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [54] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [54] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [53] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [53] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [52] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [52] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [51] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [51] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [50] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [50] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [49] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [49] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [48] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [48] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [47] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [47] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [46] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [46] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [45] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [45] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [44] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [44] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [43] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [43] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [42] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [42] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [41] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [41] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [40] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [40] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [39] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [39] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [38] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [38] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [37] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [37] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [36] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [36] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [35] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [35] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [34] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [34] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [33] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [33] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [32] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [32] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [31] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [31] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [30] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [30] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [29] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [29] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [28] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [28] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [27] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [27] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [26] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [26] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [25] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [25] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [24] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [24] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [23] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [23] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [22] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [22] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [21] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [21] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [20] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [20] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [19] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [19] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [18] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [18] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [17] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [17] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [16] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [16] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [15] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [15] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [14] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [14] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [13] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [13] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [12] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [12] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [11] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [11] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [10] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [10] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [9] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [9] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [8] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [8] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [7] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [7] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [5] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [5] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [4] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [4] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [3] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [3] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [2] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [2] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [1] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [1] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [0] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [0] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_grnerr [63] "logic ras2csr_grnerr[63:0]" +Toggle 0to1 ras2csr_grnerr [63] "logic ras2csr_grnerr[63:0]" +Toggle 1to0 ras2csr_bluerr [62] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [62] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [61] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [61] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [60] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [60] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [59] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [59] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [58] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [58] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [57] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [57] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [56] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [56] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [55] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [55] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [54] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [54] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [53] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [53] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [52] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [52] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [51] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [51] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [50] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [50] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [49] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [49] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [48] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [48] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [47] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [47] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [46] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [46] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [45] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [45] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [44] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [44] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [43] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [43] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [42] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [42] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [41] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [41] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [40] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [40] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [39] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [39] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [38] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [38] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [37] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [37] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [36] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [36] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [35] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [35] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [34] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [34] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [33] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [33] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [32] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [32] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [31] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [31] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [30] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [30] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [29] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [29] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [28] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [28] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [27] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [27] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [26] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [26] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [25] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [25] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [24] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [24] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [23] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [23] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [22] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [22] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [21] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [21] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [20] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [20] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [19] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [19] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [18] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [18] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [17] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [17] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [16] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [16] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [15] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [15] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [14] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [14] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [13] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [13] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [12] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [12] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [10] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [10] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [7] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [7] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [6] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [6] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [5] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [5] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [4] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [4] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [3] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [3] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [2] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [2] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [1] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [1] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [0] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [0] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 ras2csr_bluerr [63] "logic ras2csr_bluerr[63:0]" +Toggle 0to1 ras2csr_bluerr [63] "logic ras2csr_bluerr[63:0]" +Toggle 1to0 avmm_s2m_waitrequest "logic avmm_s2m_waitrequest" +Toggle 0to1 avmm_s2m_waitrequest "logic avmm_s2m_waitrequest" +Toggle 0to1 c32ui_port0_offset [54] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [54] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [57] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [57] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [58] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [58] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [59] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [59] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [60] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [60] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [61] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [61] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [62] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [62] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [63] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [63] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [0] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [0] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [1] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [1] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [2] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [2] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [3] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [3] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [4] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [4] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [5] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [5] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [6] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [6] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [7] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [7] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [8] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [8] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [9] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [9] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [10] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [10] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [11] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [11] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [12] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [12] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [13] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [13] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [14] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [14] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [15] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [15] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [16] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [16] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [17] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [17] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [18] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [18] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [19] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [19] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [20] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [20] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [21] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [21] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [22] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [22] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [23] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [23] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [24] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [24] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [25] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [25] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [26] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [26] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [27] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [27] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [28] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [28] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [29] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [29] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [30] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [30] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [31] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [31] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [32] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [32] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [33] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [33] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [34] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [34] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [35] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [35] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [36] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [36] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [37] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [37] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [38] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [38] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [39] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [39] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [40] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [40] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [41] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [41] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [42] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [42] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [43] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [43] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [44] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [44] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [45] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [45] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [46] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [46] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [47] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [47] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [48] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [48] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [49] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [49] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [50] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [50] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [51] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [51] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [52] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [52] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 c32ui_port0_offset [53] "logic c32ui_port0_offset[63:0]" +Toggle 1to0 c32ui_port0_offset [53] "logic c32ui_port0_offset[63:0]" +Toggle 0to1 pwr_good_n "net pwr_good_n" +Toggle 1to0 pwr_good_n "net pwr_good_n" +CHECKSUM: "1626184270 437670030" +INSTANCE: tb_top.DUT.fme_top.fme_io +Toggle inp2cr_fme_error "logic inp2cr_fme_error[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [9] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [9] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [9] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [9] "logic cr2out_ras_bluerr[63:0]" +Toggle cr2out_fme_sclr "logic cr2out_fme_sclr[19:0]" +Toggle 1to0 cr2out_pcie0_sclr [1] "logic cr2out_pcie0_sclr[12:0]" +Toggle 0to1 cr2out_pcie0_sclr [1] "logic cr2out_pcie0_sclr[12:0]" +Toggle 1to0 cr2out_pcie0_sclr [2] "logic cr2out_pcie0_sclr[12:0]" +Toggle 0to1 cr2out_pcie0_sclr [2] "logic cr2out_pcie0_sclr[12:0]" +Toggle 1to0 cr2out_pcie0_sclr [3] "logic cr2out_pcie0_sclr[12:0]" +Toggle 0to1 cr2out_pcie0_sclr [3] "logic cr2out_pcie0_sclr[12:0]" +Toggle 1to0 cr2out_pcie0_sclr [4] "logic cr2out_pcie0_sclr[12:0]" +Toggle 0to1 cr2out_pcie0_sclr [4] "logic cr2out_pcie0_sclr[12:0]" +Toggle 1to0 cr2out_pcie0_sclr [5] "logic cr2out_pcie0_sclr[12:0]" +Toggle 0to1 cr2out_pcie0_sclr [5] "logic cr2out_pcie0_sclr[12:0]" +Toggle 1to0 cr2out_pcie0_sclr [6] "logic cr2out_pcie0_sclr[12:0]" +Toggle 0to1 cr2out_pcie0_sclr [6] "logic cr2out_pcie0_sclr[12:0]" +Toggle 1to0 cr2out_pcie0_sclr [7] "logic cr2out_pcie0_sclr[12:0]" +Toggle 0to1 cr2out_pcie0_sclr [7] "logic cr2out_pcie0_sclr[12:0]" +Toggle 1to0 cr2out_pcie0_sclr [8] "logic cr2out_pcie0_sclr[12:0]" +Toggle 0to1 cr2out_pcie0_sclr [8] "logic cr2out_pcie0_sclr[12:0]" +Toggle 1to0 cr2out_pcie0_sclr [0] "logic cr2out_pcie0_sclr[12:0]" +Toggle 0to1 cr2out_pcie0_sclr [0] "logic cr2out_pcie0_sclr[12:0]" +Toggle 1to0 cr2out_pcie0_sclr [11] "logic cr2out_pcie0_sclr[12:0]" +Toggle 0to1 cr2out_pcie0_sclr [11] "logic cr2out_pcie0_sclr[12:0]" +Toggle 1to0 cr2out_pcie0_sclr [10] "logic cr2out_pcie0_sclr[12:0]" +Toggle 0to1 cr2out_pcie0_sclr [10] "logic cr2out_pcie0_sclr[12:0]" +Toggle 1to0 cr2out_pcie0_sclr [9] "logic cr2out_pcie0_sclr[12:0]" +Toggle 0to1 cr2out_pcie0_sclr [9] "logic cr2out_pcie0_sclr[12:0]" +Toggle 1to0 cr2out_pcie0_sclr [12] "logic cr2out_pcie0_sclr[12:0]" +Toggle 0to1 cr2out_pcie0_sclr [12] "logic cr2out_pcie0_sclr[12:0]" +Toggle 1to0 cr2out_fat_sclr "logic cr2out_fat_sclr" +Toggle 0to1 cr2out_fat_sclr "logic cr2out_fat_sclr" +Toggle 1to0 cr2out_nonfat_sclr "logic cr2out_nonfat_sclr" +Toggle 0to1 cr2out_nonfat_sclr "logic cr2out_nonfat_sclr" +Toggle 1to0 cr2out_gbsErrMask [0] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [0] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [4] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [4] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [63] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [63] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [62] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [62] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [61] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [61] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [60] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [60] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [59] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [59] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [58] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [58] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [57] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [57] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [56] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [56] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [55] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [55] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [54] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [54] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [53] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [53] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [52] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [52] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [51] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [51] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [50] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [50] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [49] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [49] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [48] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [48] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [47] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [47] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [46] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [46] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [45] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [45] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [44] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [44] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [43] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [43] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [42] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [42] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [41] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [41] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [40] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [40] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [39] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [39] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [38] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [38] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [37] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [37] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [36] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [36] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [35] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [35] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [34] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [34] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [33] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [33] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [32] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [32] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [31] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [31] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [30] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [30] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [29] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [29] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [28] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [28] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [27] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [27] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [26] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [26] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [25] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [25] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [24] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [24] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [23] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [23] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [22] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [22] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [21] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [21] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [20] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [20] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [19] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [19] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [18] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [18] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [17] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [17] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [16] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [16] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [15] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [15] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [14] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [14] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [13] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [13] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [12] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [12] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [11] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [11] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [10] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [10] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [9] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [9] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [8] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [8] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [7] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [7] "logic cr2out_gbsErrMask[63:0]" +Toggle 1to0 cr2out_gbsErrMask [1] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_gbsErrMask [1] "logic cr2out_gbsErrMask[63:0]" +Toggle 0to1 cr2out_port3_offset [54] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [54] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [57] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [57] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [58] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [58] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [59] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [59] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [60] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [60] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [61] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [61] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [62] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [62] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [63] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [63] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [0] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [0] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [1] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [1] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [2] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [2] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [3] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [3] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [4] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [4] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [5] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [5] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [6] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [6] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [7] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [7] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [8] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [8] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [9] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [9] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [10] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [10] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [11] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [11] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [12] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [12] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [13] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [13] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [14] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [14] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [15] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [15] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [16] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [16] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [17] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [17] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [18] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [18] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [19] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [19] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [20] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [20] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [21] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [21] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [22] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [22] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [23] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [23] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [24] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [24] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [25] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [25] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [26] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [26] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [27] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [27] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [28] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [28] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [29] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [29] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [30] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [30] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [31] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [31] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [32] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [32] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [33] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [33] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [34] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [34] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [35] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [35] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [36] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [36] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [37] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [37] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [38] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [38] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [39] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [39] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [40] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [40] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [41] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [41] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [42] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [42] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [43] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [43] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [44] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [44] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [45] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [45] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [46] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [46] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [47] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [47] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [48] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [48] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [49] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [49] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [50] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [50] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [51] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [51] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [52] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [52] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port3_offset [53] "logic cr2out_port3_offset[63:0]" +Toggle 1to0 cr2out_port3_offset [53] "logic cr2out_port3_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [54] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [54] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [57] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [57] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [58] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [58] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [59] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [59] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [60] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [60] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [61] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [61] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [62] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [62] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [63] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [63] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [0] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [0] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [1] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [1] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [2] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [2] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [3] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [3] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [4] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [4] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [5] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [5] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [6] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [6] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [7] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [7] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [8] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [8] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [9] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [9] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [10] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [10] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [11] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [11] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [12] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [12] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [13] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [13] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [14] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [14] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [15] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [15] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [16] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [16] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [17] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [17] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [18] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [18] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [19] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [19] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [20] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [20] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [21] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [21] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [22] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [22] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [23] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [23] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [24] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [24] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [25] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [25] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [26] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [26] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [27] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [27] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [28] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [28] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [29] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [29] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [30] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [30] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [31] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [31] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [32] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [32] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [33] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [33] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [34] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [34] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [35] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [35] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [36] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [36] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [37] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [37] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [38] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [38] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [39] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [39] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [40] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [40] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [41] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [41] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [42] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [42] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [43] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [43] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [44] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [44] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [45] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [45] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [46] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [46] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [47] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [47] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [48] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [48] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [49] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [49] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [50] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [50] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [51] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [51] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [52] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [52] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port2_offset [53] "logic cr2out_port2_offset[63:0]" +Toggle 1to0 cr2out_port2_offset [53] "logic cr2out_port2_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [63] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [63] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [56] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [0] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [0] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [1] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [1] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [2] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [2] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [3] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [3] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [4] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [4] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [5] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [5] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [6] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [6] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [7] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [7] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [8] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [8] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [9] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [9] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [10] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [10] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [11] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [11] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [12] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [12] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [13] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [13] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [14] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [14] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [15] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [15] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [16] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [16] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [17] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [17] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [18] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [18] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [19] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [19] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [20] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [20] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [21] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [21] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [22] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [22] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [23] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [23] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [24] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [24] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [25] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [25] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [26] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [26] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [27] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [27] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [28] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [28] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [29] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [29] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [30] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [30] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [31] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [31] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [32] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [32] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [33] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [33] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [34] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [34] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [35] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [35] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [36] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [36] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [37] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [37] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [38] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [38] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [39] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [39] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [40] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [40] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [41] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [41] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [42] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [42] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [43] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [43] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [44] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [44] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [45] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [45] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [46] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [46] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [47] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [47] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [48] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [48] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [49] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [49] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [50] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [50] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [51] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [51] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [52] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [52] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [53] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [53] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [54] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [54] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [57] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [57] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [58] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [58] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [59] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [59] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [60] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [60] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [61] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [61] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port1_offset [62] "logic cr2out_port1_offset[63:0]" +Toggle 1to0 cr2out_port1_offset [62] "logic cr2out_port1_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [54] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [54] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [55] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [57] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [57] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [58] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [58] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [59] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [59] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [60] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [60] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [61] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [61] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [62] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [62] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [63] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [63] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [0] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [0] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [1] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [1] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [2] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [2] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [3] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [3] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [4] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [4] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [5] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [5] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [6] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [6] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [7] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [7] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [8] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [8] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [9] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [9] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [10] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [10] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [11] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [11] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [12] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [12] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [13] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [13] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [14] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [14] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [15] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [15] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [16] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [16] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [17] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [17] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [18] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [18] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [19] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [19] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [20] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [20] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [21] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [21] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [22] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [22] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [23] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [23] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [24] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [24] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [25] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [25] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [26] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [26] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [27] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [27] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [28] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [28] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [29] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [29] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [30] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [30] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [31] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [31] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [32] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [32] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [33] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [33] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [34] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [34] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [35] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [35] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [36] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [36] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [37] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [37] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [38] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [38] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [39] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [39] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [40] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [40] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [41] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [41] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [42] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [42] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [43] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [43] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [44] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [44] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [45] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [45] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [46] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [46] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [47] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [47] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [48] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [48] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [49] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [49] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [50] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [50] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [51] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [51] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [52] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [52] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_port0_offset [53] "logic cr2out_port0_offset[63:0]" +Toggle 1to0 cr2out_port0_offset [53] "logic cr2out_port0_offset[63:0]" +Toggle 0to1 cr2out_ras_bluerr [63] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [63] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [0] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [0] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [1] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [1] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [2] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [2] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [3] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [3] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [4] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [4] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [5] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [5] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [6] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [6] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [7] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [7] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [10] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [10] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [12] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [12] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [13] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [13] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [14] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [14] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [15] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [15] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [16] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [16] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [17] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [17] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [18] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [18] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [19] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [19] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [20] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [20] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [21] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [21] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [22] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [22] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [23] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [23] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [24] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [24] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [25] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [25] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [26] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [26] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [27] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [27] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [28] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [28] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [29] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [29] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [30] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [30] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [31] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [31] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [32] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [32] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [33] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [33] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [34] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [34] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [35] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [35] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [36] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [36] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [37] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [37] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [38] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [38] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [39] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [39] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [40] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [40] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [41] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [41] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [42] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [42] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [43] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [43] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [44] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [44] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [45] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [45] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [46] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [46] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [47] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [47] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [48] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [48] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [49] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [49] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [50] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [50] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [51] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [51] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [52] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [52] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [53] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [53] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [54] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [54] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [55] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [55] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [56] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [56] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [57] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [57] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [58] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [58] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [59] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [59] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [60] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [60] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [61] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [61] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_bluerr [62] "logic cr2out_ras_bluerr[63:0]" +Toggle 1to0 cr2out_ras_bluerr [62] "logic cr2out_ras_bluerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [63] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [63] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [0] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [0] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [1] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [1] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [2] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [2] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [3] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [3] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [4] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [4] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [5] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [5] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [7] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [7] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [8] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [8] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [9] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [9] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [10] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [10] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [11] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [11] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [12] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [12] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [13] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [13] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [14] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [14] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [15] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [15] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [16] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [16] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [17] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [17] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [18] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [18] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [19] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [19] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [20] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [20] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [21] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [21] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [22] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [22] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [23] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [23] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [24] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [24] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [25] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [25] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [26] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [26] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [27] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [27] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [28] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [28] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [29] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [29] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [30] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [30] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [31] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [31] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [32] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [32] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [33] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [33] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [34] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [34] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [35] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [35] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [36] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [36] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [37] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [37] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [38] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [38] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [39] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [39] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [40] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [40] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [41] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [41] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [42] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [42] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [43] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [43] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [44] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [44] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [45] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [45] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [46] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [46] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [47] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [47] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [48] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [48] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [49] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [49] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [50] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [50] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [51] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [51] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [52] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [52] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [53] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [53] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [54] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [54] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [55] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [55] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [56] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [56] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [57] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [57] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [58] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [58] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [59] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [59] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [60] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [60] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [61] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [61] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 cr2out_ras_grnerr [62] "logic cr2out_ras_grnerr[63:0]" +Toggle 1to0 cr2out_ras_grnerr [62] "logic cr2out_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [63] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [63] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [0] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [0] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [1] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [1] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [2] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [2] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [3] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [3] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [4] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [4] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [5] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [5] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [7] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [7] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [8] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [8] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [9] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [9] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [10] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [10] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [11] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [11] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [12] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [12] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [13] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [13] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [14] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [14] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [15] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [15] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [16] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [16] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [17] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [17] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [18] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [18] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [19] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [19] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [20] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [20] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [21] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [21] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [22] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [22] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [23] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [23] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [24] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [24] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [25] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [25] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [26] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [26] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [27] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [27] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [28] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [28] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [29] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [29] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [30] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [30] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [31] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [31] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [32] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [32] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [33] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [33] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [34] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [34] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [35] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [35] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [36] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [36] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [37] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [37] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [38] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [38] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [39] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [39] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [40] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [40] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [41] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [41] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [42] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [42] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [43] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [43] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [44] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [44] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [45] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [45] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [46] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [46] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [47] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [47] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [48] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [48] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [49] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [49] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [50] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [50] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [51] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [51] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [52] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [52] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [53] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [53] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [54] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [54] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [55] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [55] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [56] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [56] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [57] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [57] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [58] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [58] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [59] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [59] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [60] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [60] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [61] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [61] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_grnerr [62] "logic inp2cr_ras_grnerr[63:0]" +Toggle 1to0 inp2cr_ras_grnerr [62] "logic inp2cr_ras_grnerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [63] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [63] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [0] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [0] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [1] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [1] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [2] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [2] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [3] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [3] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [4] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [4] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [5] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [5] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [6] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [6] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [7] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [7] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [10] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [10] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [12] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [12] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [13] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [13] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [14] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [14] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [15] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [15] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [16] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [16] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [17] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [17] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [18] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [18] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [19] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [19] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [20] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [20] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [21] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [21] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [22] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [22] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [23] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [23] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [24] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [24] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [25] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [25] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [26] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [26] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [27] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [27] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [28] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [28] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [29] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [29] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [30] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [30] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [31] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [31] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [32] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [32] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [33] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [33] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [34] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [34] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [35] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [35] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [36] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [36] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [37] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [37] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [38] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [38] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [39] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [39] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [40] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [40] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [41] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [41] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [42] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [42] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [43] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [43] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [44] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [44] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [45] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [45] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [46] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [46] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [47] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [47] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [48] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [48] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [49] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [49] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [50] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [50] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [51] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [51] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [52] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [52] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [53] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [53] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [54] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [54] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [55] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [55] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [56] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [56] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [57] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [57] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [58] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [58] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [59] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [59] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [60] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [60] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [61] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [61] "logic inp2cr_ras_bluerr[63:0]" +Toggle 0to1 inp2cr_ras_bluerr [62] "logic inp2cr_ras_bluerr[63:0]" +Toggle 1to0 inp2cr_ras_bluerr [62] "logic inp2cr_ras_bluerr[63:0]" +CHECKSUM: "1771855867 1865882998" +INSTANCE: tb_top.DUT.fme_top.fme_csr +Toggle FME_PR_IF_ID_MAX "bit FME_PR_IF_ID_MAX[1:0]" +CHECKSUM: "1969380418 433130349" +INSTANCE: tb_top.DUT.fme_top +Toggle 1to0 cr2ras_afu_access_err "logic cr2ras_afu_access_err" +Toggle 0to1 cr2out_pcie_error "logic cr2out_pcie_error" +Toggle 0to1 cr2ras_pcie_poison "logic cr2ras_pcie_poison" +Toggle 0to1 cr2ras_mbp_err "logic cr2ras_mbp_err" +CHECKSUM: "3317404973 4202687390" +INSTANCE: tb_top.DUT.fme_top.fme_io +Toggle cr2out_fpmon_fab_ctl "logic cr2out_fpmon_fab_ctl[63:0]" +Toggle 1to0 cr2out_bbsErrMask [4:4]"logic cr2out_bbsErrMask[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle inp2cr_fpmon_clk_ctr "logic inp2cr_fpmon_clk_ctr[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle inp2cr_fpmon_fab_ctr "logic inp2cr_fpmon_fab_ctr[63:0]" +Toggle 1to0 cr2out_afu_access_err "logic cr2out_afu_access_err" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle cr2out_fme_pr_status "logic cr2out_fme_pr_status[63:0]" +Toggle 0to1 inp2cr_pcie0_err_vf_num "logic inp2cr_pcie0_err_vf_num" +Toggle 0to1 inp2cr_pcie0_err_vf_active "logic inp2cr_pcie0_err_vf_active" +ANNOTATION: " Excluding pcie error related siganls " +Toggle inp2cr_pcie0_err_code "logic inp2cr_pcie0_err_code[12:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle inp2cr_msix_pba "logic inp2cr_msix_pba[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle inp2cr_msix_count_vector "logic inp2cr_msix_count_vector[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle inp2cr_fme_pr_status "logic inp2cr_fme_pr_status[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle inp2cr_fme_pr_error "logic inp2cr_fme_pr_error[63:0]" +Toggle 0to1 cr2out_pcie_poison_err "logic cr2out_pcie_poison_err" +Toggle 0to1 cr2out_pcie_error "logic cr2out_pcie_error" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle cr2out_msix_pba "logic cr2out_msix_pba[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle cr2out_msix_ctldat7 "logic cr2out_msix_ctldat7[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle cr2out_msix_ctldat6 "logic cr2out_msix_ctldat6[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle cr2out_msix_ctldat5 "logic cr2out_msix_ctldat5[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle cr2out_msix_ctldat4 "logic cr2out_msix_ctldat4[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle cr2out_msix_ctldat3 "logic cr2out_msix_ctldat3[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle cr2out_msix_ctldat2 "logic cr2out_msix_ctldat2[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle cr2out_msix_ctldat1 "logic cr2out_msix_ctldat1[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle cr2out_msix_ctldat0 "logic cr2out_msix_ctldat0[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle cr2out_msix_addr7 "logic cr2out_msix_addr7[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle cr2out_msix_addr6 "logic cr2out_msix_addr6[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle cr2out_msix_addr5 "logic cr2out_msix_addr5[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle cr2out_msix_addr4 "logic cr2out_msix_addr4[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle cr2out_msix_addr3 "logic cr2out_msix_addr3[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle cr2out_msix_addr2 "logic cr2out_msix_addr2[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle cr2out_msix_addr1 "logic cr2out_msix_addr1[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle cr2out_msix_addr0 "logic cr2out_msix_addr0[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle inp2cr_tmp_rdsensor_fmt1 "logic inp2cr_tmp_rdsensor_fmt1[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle inp2cr_tmp_threshold "logic inp2cr_tmp_threshold[63:0]" +Toggle 0to1 cr2out_fme_pr_ctrl [31:31]"logic cr2out_fme_pr_ctrl[63:0]" +Toggle 0to1 cr2out_tmp_threshold [30:30]"logic cr2out_tmp_threshold[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle inp2cr_fme_pr_ctrl "logic inp2cr_fme_pr_ctrl[63:0]" +Toggle 0to1 inp2cr_fab_status [63:63]"logic inp2cr_fab_status[63:0]" +CHECKSUM: "4183828556 3679289198" +INSTANCE: tb_top.DUT.fme_top.fme_csr +ANNOTATION: " Msix is moved to pciess. " +Condition 48 "1284074946" "((rd_reg_offset < 9'h002) ? 1'b1 : 1'b0) 1 -1" +ANNOTATION: " Msix is moved to pciess. " +Condition 47 "3852086095" "((rd_reg_offset < 9'h010) ? 1'b1 : 1'b0) 1 -1" +ANNOTATION: " Msix is moved to pciess. " +Condition 7 "189413905" "((wr_reg_offset < 9'h002) ? 1'b1 : 1'b0) 1 -1" +ANNOTATION: " Msix is moved to pciess. " +Condition 6 "200621328" "((wr_reg_offset < 9'h010) ? 1'b1 : 1'b0) 1 -1" +CHECKSUM: "4183828556 79200855" +INSTANCE: tb_top.DUT.fme_top.fme_csr +Toggle 1to0 afu_access_error_reg "logic afu_access_error_reg" +Toggle 1to0 fme_csr_fme_pr_ctrl.data [8:8]"logic fme_csr_fme_pr_ctrl.data[63:0]" +Toggle 1to0 fme_csr_fme_pr_ctrl.word.lower32 [8:8]"logic fme_csr_fme_pr_ctrl.word.lower32[31:0]" +Toggle 1to0 pcie_error_reg "logic pcie_error_reg" +Toggle 1to0 pcie_poison_error_reg "logic pcie_poison_error_reg" +Toggle 1to0 fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_reset_ack "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_reset_ack" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_pr_status_attr.fme_pr_status.pr_status "logic fme_pr_status_attr.fme_pr_status.pr_status[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_pr_dfh_attr.dfh.end_of_list "logic fme_pr_dfh_attr.dfh.end_of_list[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_pr_ctrl_attr.fme_pr_ctrl.pr_reset_ack "logic fme_pr_ctrl_attr.fme_pr_ctrl.pr_reset_ack[3:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_50A0_update.word.lower32 "logic fme_csr_dummy_50A0_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_50A0_update.data "logic fme_csr_dummy_50A0_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_50A0_reset.word.upper32 "logic fme_csr_dummy_50A0_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_50A0_reset.word.lower32 "logic fme_csr_dummy_50A0_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_50A0_reset.data "logic fme_csr_dummy_50A0_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_50A0_update.word.upper32 "logic fme_csr_dummy_50A0_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5080_update.word.upper32 "logic fme_csr_dummy_5080_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5080_update.word.lower32 "logic fme_csr_dummy_5080_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5080_update.data "logic fme_csr_dummy_5080_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5080_reset.word.upper32 "logic fme_csr_dummy_5080_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5080_reset.word.lower32 "logic fme_csr_dummy_5080_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5080_reset.data "logic fme_csr_dummy_5080_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5078_update.word.upper32 "logic fme_csr_dummy_5078_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5078_update.word.lower32 "logic fme_csr_dummy_5078_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5078_update.data "logic fme_csr_dummy_5078_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5078_reset.word.upper32 "logic fme_csr_dummy_5078_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5078_reset.word.lower32 "logic fme_csr_dummy_5078_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5078_reset.data "logic fme_csr_dummy_5078_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5070_update.word.upper32 "logic fme_csr_dummy_5070_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5070_update.word.lower32 "logic fme_csr_dummy_5070_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5070_update.data "logic fme_csr_dummy_5070_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5070_reset.word.upper32 "logic fme_csr_dummy_5070_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5070_reset.word.lower32 "logic fme_csr_dummy_5070_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5070_reset.data "logic fme_csr_dummy_5070_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5068_update.word.upper32 "logic fme_csr_dummy_5068_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5068_update.word.lower32 "logic fme_csr_dummy_5068_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5068_update.data "logic fme_csr_dummy_5068_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5068_reset.word.upper32 "logic fme_csr_dummy_5068_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5068_reset.word.lower32 "logic fme_csr_dummy_5068_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5068_reset.data "logic fme_csr_dummy_5068_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5060_update.word.upper32 "logic fme_csr_dummy_5060_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5060_update.word.lower32 "logic fme_csr_dummy_5060_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5060_update.data "logic fme_csr_dummy_5060_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5060_reset.word.upper32 "logic fme_csr_dummy_5060_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5060_reset.word.lower32 "logic fme_csr_dummy_5060_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5060_reset.data "logic fme_csr_dummy_5060_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5058_update.word.upper32 "logic fme_csr_dummy_5058_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5058_update.word.lower32 "logic fme_csr_dummy_5058_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5058_update.data "logic fme_csr_dummy_5058_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5058_reset.word.upper32 "logic fme_csr_dummy_5058_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5058_reset.word.lower32 "logic fme_csr_dummy_5058_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5058_reset.data "logic fme_csr_dummy_5058_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5050_update.word.upper32 "logic fme_csr_dummy_5050_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5050_update.word.lower32 "logic fme_csr_dummy_5050_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5050_update.data "logic fme_csr_dummy_5050_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5050_reset.word.upper32 "logic fme_csr_dummy_5050_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5050_reset.word.lower32 "logic fme_csr_dummy_5050_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5050_reset.data "logic fme_csr_dummy_5050_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5048_update.word.upper32 "logic fme_csr_dummy_5048_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5048_update.word.lower32 "logic fme_csr_dummy_5048_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5048_update.data "logic fme_csr_dummy_5048_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5048_reset.word.upper32 "logic fme_csr_dummy_5048_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5048_reset.word.lower32 "logic fme_csr_dummy_5048_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5048_reset.data "logic fme_csr_dummy_5048_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5040_update.word.upper32 "logic fme_csr_dummy_5040_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5040_update.word.lower32 "logic fme_csr_dummy_5040_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5040_update.data "logic fme_csr_dummy_5040_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5040_reset.word.upper32 "logic fme_csr_dummy_5040_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5040_reset.word.lower32 "logic fme_csr_dummy_5040_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5040_reset.data "logic fme_csr_dummy_5040_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5038_update.word.upper32 "logic fme_csr_dummy_5038_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5038_update.word.lower32 "logic fme_csr_dummy_5038_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5038_update.data "logic fme_csr_dummy_5038_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5038_reset.word.upper32 "logic fme_csr_dummy_5038_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5038_reset.word.lower32 "logic fme_csr_dummy_5038_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5038_reset.data "logic fme_csr_dummy_5038_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5030_update.word.upper32 "logic fme_csr_dummy_5030_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5030_update.word.lower32 "logic fme_csr_dummy_5030_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5030_update.data "logic fme_csr_dummy_5030_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5030_reset.word.upper32 "logic fme_csr_dummy_5030_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5030_reset.word.lower32 "logic fme_csr_dummy_5030_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5030_reset.data "logic fme_csr_dummy_5030_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5028_update.word.upper32 "logic fme_csr_dummy_5028_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5028_update.word.lower32 "logic fme_csr_dummy_5028_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5028_update.data "logic fme_csr_dummy_5028_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5028_reset.word.upper32 "logic fme_csr_dummy_5028_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5028_reset.word.lower32 "logic fme_csr_dummy_5028_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5028_reset.data "logic fme_csr_dummy_5028_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5088_reset.data "logic fme_csr_dummy_5088_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5098_update.word.lower32 "logic fme_csr_dummy_5098_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5098_update.data "logic fme_csr_dummy_5098_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5098_reset.word.upper32 "logic fme_csr_dummy_5098_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5098_reset.word.lower32 "logic fme_csr_dummy_5098_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5098_reset.data "logic fme_csr_dummy_5098_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5090_update.word.upper32 "logic fme_csr_dummy_5090_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5090_update.word.lower32 "logic fme_csr_dummy_5090_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5090_update.data "logic fme_csr_dummy_5090_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5090_reset.word.upper32 "logic fme_csr_dummy_5090_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5090_reset.word.lower32 "logic fme_csr_dummy_5090_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5090_reset.data "logic fme_csr_dummy_5090_reset.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5088_update.word.upper32 "logic fme_csr_dummy_5088_update.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5088_update.word.lower32 "logic fme_csr_dummy_5088_update.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5088_update.data "logic fme_csr_dummy_5088_update.data[63:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5088_reset.word.upper32 "logic fme_csr_dummy_5088_reset.word.upper32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5088_reset.word.lower32 "logic fme_csr_dummy_5088_reset.word.lower32[31:0]" +ANNOTATION: " Read only register whose defaut values are zeros, cannot toggle " +Toggle fme_csr_dummy_5098_update.word.upper32 "logic fme_csr_dummy_5098_update.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_dfh_update.word.lower32 "logic fme_csr_fme_pr_dfh_update.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_dfh_update.dfh.next_dfh_offset "logic fme_csr_fme_pr_dfh_update.dfh.next_dfh_offset[23:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_dfh_update.dfh.feature_type "logic fme_csr_fme_pr_dfh_update.dfh.feature_type[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_dfh_update.dfh.feature_rev "logic fme_csr_fme_pr_dfh_update.dfh.feature_rev[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_dfh_update.dfh.feature_id "logic fme_csr_fme_pr_dfh_update.dfh.feature_id[11:0]" +Toggle 1to0 fme_csr_fme_pr_dfh_update.dfh.end_of_list "logic fme_csr_fme_pr_dfh_update.dfh.end_of_list" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_dfh_update.data "logic fme_csr_fme_pr_dfh_update.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_dfh_reset.word.upper32 "logic fme_csr_fme_pr_dfh_reset.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_dfh_reset.word.lower32 "logic fme_csr_fme_pr_dfh_reset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_dfh_reset.dfh.next_dfh_offset "logic fme_csr_fme_pr_dfh_reset.dfh.next_dfh_offset[23:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_dfh_reset.dfh.feature_type "logic fme_csr_fme_pr_dfh_reset.dfh.feature_type[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_dfh_reset.dfh.feature_rev "logic fme_csr_fme_pr_dfh_reset.dfh.feature_rev[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_dfh_reset.dfh.feature_id "logic fme_csr_fme_pr_dfh_reset.dfh.feature_id[11:0]" +Toggle 1to0 fme_csr_fme_pr_dfh_reset.dfh.end_of_list "logic fme_csr_fme_pr_dfh_reset.dfh.end_of_list" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_dfh_reset.data "logic fme_csr_fme_pr_dfh_reset.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_dfh_update.word.upper32 "logic fme_csr_fme_pr_dfh_update.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status_update.word.lower32 "logic fme_csr_fme_pr_status_update.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status_update.fme_pr_status.security_block_status "logic fme_csr_fme_pr_status_update.fme_pr_status.security_block_status[31:0]" +Toggle 1to0 fme_csr_fme_pr_status_update.fme_pr_status.pr_status "logic fme_csr_fme_pr_status_update.fme_pr_status.pr_status" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status_update.fme_pr_status.pr_host_status "logic fme_csr_fme_pr_status_update.fme_pr_status.pr_host_status[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status_update.fme_pr_status.numb_credits "logic fme_csr_fme_pr_status_update.fme_pr_status.numb_credits[8:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status_update.fme_pr_status.altera_pr_ctrl_status "logic fme_csr_fme_pr_status_update.fme_pr_status.altera_pr_ctrl_status[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status_update.data "logic fme_csr_fme_pr_status_update.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status_reset.word.upper32 "logic fme_csr_fme_pr_status_reset.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status_reset.word.lower32 "logic fme_csr_fme_pr_status_reset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status_reset.fme_pr_status.security_block_status "logic fme_csr_fme_pr_status_reset.fme_pr_status.security_block_status[31:0]" +Toggle 1to0 fme_csr_fme_pr_status_reset.fme_pr_status.pr_status "logic fme_csr_fme_pr_status_reset.fme_pr_status.pr_status" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status_reset.fme_pr_status.pr_host_status "logic fme_csr_fme_pr_status_reset.fme_pr_status.pr_host_status[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status_reset.fme_pr_status.numb_credits "logic fme_csr_fme_pr_status_reset.fme_pr_status.numb_credits[8:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status_reset.fme_pr_status.altera_pr_ctrl_status "logic fme_csr_fme_pr_status_reset.fme_pr_status.altera_pr_ctrl_status[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status_reset.data "logic fme_csr_fme_pr_status_reset.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status.word.upper32 "logic fme_csr_fme_pr_status.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status.word.lower32 "logic fme_csr_fme_pr_status.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status.fme_pr_status.security_block_status "logic fme_csr_fme_pr_status.fme_pr_status.security_block_status[31:0]" +Toggle 1to0 fme_csr_fme_pr_status.fme_pr_status.pr_status "logic fme_csr_fme_pr_status.fme_pr_status.pr_status" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status.fme_pr_status.pr_host_status "logic fme_csr_fme_pr_status.fme_pr_status.pr_host_status[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status.fme_pr_status.numb_credits "logic fme_csr_fme_pr_status.fme_pr_status.numb_credits[8:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status.fme_pr_status.altera_pr_ctrl_status "logic fme_csr_fme_pr_status.fme_pr_status.altera_pr_ctrl_status[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status.data "logic fme_csr_fme_pr_status.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status_update.word.upper32 "logic fme_csr_fme_pr_status_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_fme_pr_intfc_id_l_update.word.upper32 [30:30]"logic fme_csr_fme_pr_intfc_id_l_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_fme_pr_intfc_id_l_update.word.lower32 [30:30]"logic fme_csr_fme_pr_intfc_id_l_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_pr_intfc_id_l_update.data [62:62]"logic fme_csr_fme_pr_intfc_id_l_update.data[63:0]" +Toggle 1to0 fme_csr_fme_pr_intfc_id_l_reset.word.upper32 [30:30]"logic fme_csr_fme_pr_intfc_id_l_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_fme_pr_intfc_id_l_reset.word.lower32 [30:30]"logic fme_csr_fme_pr_intfc_id_l_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_pr_intfc_id_l_reset.data [62:62]"logic fme_csr_fme_pr_intfc_id_l_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_pr_intfc_id_h_reset.data [56:56]"logic fme_csr_fme_pr_intfc_id_h_reset.data[63:0]" +Toggle 1to0 fme_csr_fme_pr_intfc_id_h_reset.word.lower32 [24:24]"logic fme_csr_fme_pr_intfc_id_h_reset.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_pr_intfc_id_h_reset.word.upper32 [24:24]"logic fme_csr_fme_pr_intfc_id_h_reset.word.upper32[31:0]" +Toggle 1to0 fme_csr_fme_pr_intfc_id_h_update.data [56:56]"logic fme_csr_fme_pr_intfc_id_h_update.data[63:0]" +Toggle 1to0 fme_csr_fme_pr_intfc_id_h_update.word.lower32 [24:24]"logic fme_csr_fme_pr_intfc_id_h_update.word.lower32[31:0]" +Toggle 1to0 fme_csr_fme_pr_intfc_id_h_update.word.upper32 [4:4]"logic fme_csr_fme_pr_intfc_id_h_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_fme_pr_ctrl.fme_pr_ctrl.pr_reset_ack "logic fme_csr_fme_pr_ctrl.fme_pr_ctrl.pr_reset_ack" +Toggle 1to0 fme_csr_fme_pr_ctrl.fme_pr_ctrl.pr_data_push_complete "logic fme_csr_fme_pr_ctrl.fme_pr_ctrl.pr_data_push_complete" +Toggle 1to0 fme_csr_fme_pr_ctrl.fme_pr_ctrl.pr_start_request "logic fme_csr_fme_pr_ctrl.fme_pr_ctrl.pr_start_request" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_pr_error_attr.fme_pr_error.secure_load_failed "logic fme_pr_error_attr.fme_pr_error.secure_load_failed[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_pr_ctrl_attr.fme_pr_ctrl.pr_data_push_complete "logic fme_pr_ctrl_attr.fme_pr_ctrl.pr_data_push_complete[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_pr_ctrl_attr.fme_pr_ctrl.pr_kind "logic fme_pr_ctrl_attr.fme_pr_ctrl.pr_kind[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_pr_ctrl_attr.fme_pr_ctrl.pr_reset "logic fme_pr_ctrl_attr.fme_pr_ctrl.pr_reset[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_pr_ctrl_attr.fme_pr_ctrl.pr_start_request "logic fme_pr_ctrl_attr.fme_pr_ctrl.pr_start_request[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_pr_error_attr.fme_pr_error.host_init_fifo_overflow "logic fme_pr_error_attr.fme_pr_error.host_init_fifo_overflow[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_pr_error_attr.fme_pr_error.host_init_operation_error "logic fme_pr_error_attr.fme_pr_error.host_init_operation_error[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_pr_error_attr.fme_pr_error.host_init_timeout "logic fme_pr_error_attr.fme_pr_error.host_init_timeout[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_pr_error_attr.fme_pr_error.ip_init_crc_error "logic fme_pr_error_attr.fme_pr_error.ip_init_crc_error[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_pr_error_attr.fme_pr_error.ip_init_incompatible_bitstream "logic fme_pr_error_attr.fme_pr_error.ip_init_incompatible_bitstream[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_pr_error_attr.fme_pr_error.ip_init_protocol_error "logic fme_pr_error_attr.fme_pr_error.ip_init_protocol_error[3:0]" +Toggle 0to1 fme_csr_pcie0_error_update.pcie0_error.vf_num "logic fme_csr_pcie0_error_update.pcie0_error.vf_num" +Toggle 0to1 fme_csr_pcie0_error_update.pcie0_error.rx_poison_tlp_error "logic fme_csr_pcie0_error_update.pcie0_error.rx_poison_tlp_error" +Toggle 0to1 fme_csr_pcie0_error_update.pcie0_error.rx_fifo_oflow_error "logic fme_csr_pcie0_error_update.pcie0_error.rx_fifo_oflow_error" +Toggle 0to1 fme_csr_pcie0_error_update.pcie0_error.parity_error "logic fme_csr_pcie0_error_update.pcie0_error.parity_error" +Toggle 0to1 fme_csr_pcie0_error_update.pcie0_error.mw_length_error "logic fme_csr_pcie0_error_update.pcie0_error.mw_length_error" +Toggle 0to1 fme_csr_pcie0_error_update.pcie0_error.mw_addr_error "logic fme_csr_pcie0_error_update.pcie0_error.mw_addr_error" +Toggle 0to1 fme_csr_pcie0_error_update.pcie0_error.mr_length_error "logic fme_csr_pcie0_error_update.pcie0_error.mr_length_error" +Toggle 0to1 fme_csr_pcie0_error_update.pcie0_error.mr_addr_error "logic fme_csr_pcie0_error_update.pcie0_error.mr_addr_error" +Toggle 0to1 fme_csr_pcie0_error_update.pcie0_error.malformed_sop_error "logic fme_csr_pcie0_error_update.pcie0_error.malformed_sop_error" +Toggle 0to1 fme_csr_pcie0_error_update.pcie0_error.malformed_eop_error "logic fme_csr_pcie0_error_update.pcie0_error.malformed_eop_error" +Toggle 0to1 fme_csr_pcie0_error_update.pcie0_error.function_type_error "logic fme_csr_pcie0_error_update.pcie0_error.function_type_error" +Toggle 0to1 fme_csr_pcie0_error_update.pcie0_error.format_type_error "logic fme_csr_pcie0_error_update.pcie0_error.format_type_error" +Toggle 0to1 fme_csr_pcie0_error_update.pcie0_error.comp_time_out_error "logic fme_csr_pcie0_error_update.pcie0_error.comp_time_out_error" +Toggle 0to1 fme_csr_pcie0_error_update.pcie0_error.comp_tag_error "logic fme_csr_pcie0_error_update.pcie0_error.comp_tag_error" +Toggle 0to1 fme_csr_pcie0_error_update.pcie0_error.comp_stat_error "logic fme_csr_pcie0_error_update.pcie0_error.comp_stat_error" +Toggle 0to1 fme_csr_pcie0_error_reset.pcie0_error.vf_num "logic fme_csr_pcie0_error_reset.pcie0_error.vf_num" +Toggle 0to1 fme_csr_pcie0_error_reset.pcie0_error.rx_poison_tlp_error "logic fme_csr_pcie0_error_reset.pcie0_error.rx_poison_tlp_error" +Toggle 0to1 fme_csr_pcie0_error_reset.pcie0_error.rx_fifo_oflow_error "logic fme_csr_pcie0_error_reset.pcie0_error.rx_fifo_oflow_error" +Toggle 0to1 fme_csr_pcie0_error.pcie0_error.vf_num "logic fme_csr_pcie0_error.pcie0_error.vf_num" +Toggle 0to1 fme_csr_pcie0_error.pcie0_error.rx_poison_tlp_error "logic fme_csr_pcie0_error.pcie0_error.rx_poison_tlp_error" +Toggle 0to1 fme_csr_pcie0_error.pcie0_error.rx_fifo_oflow_error "logic fme_csr_pcie0_error.pcie0_error.rx_fifo_oflow_error" +Toggle 0to1 fme_csr_pcie0_error.pcie0_error.parity_error "logic fme_csr_pcie0_error.pcie0_error.parity_error" +Toggle 0to1 fme_csr_pcie0_error.pcie0_error.mw_length_error "logic fme_csr_pcie0_error.pcie0_error.mw_length_error" +Toggle 0to1 fme_csr_pcie0_error.pcie0_error.mw_addr_error "logic fme_csr_pcie0_error.pcie0_error.mw_addr_error" +Toggle 0to1 fme_csr_pcie0_error.pcie0_error.mr_length_error "logic fme_csr_pcie0_error.pcie0_error.mr_length_error" +Toggle 0to1 fme_csr_pcie0_error.pcie0_error.mr_addr_error "logic fme_csr_pcie0_error.pcie0_error.mr_addr_error" +Toggle 0to1 fme_csr_pcie0_error.pcie0_error.malformed_sop_error "logic fme_csr_pcie0_error.pcie0_error.malformed_sop_error" +Toggle 0to1 fme_csr_pcie0_error.pcie0_error.malformed_eop_error "logic fme_csr_pcie0_error.pcie0_error.malformed_eop_error" +Toggle 0to1 fme_csr_pcie0_error.pcie0_error.function_type_error "logic fme_csr_pcie0_error.pcie0_error.function_type_error" +Toggle 0to1 fme_csr_pcie0_error.pcie0_error.format_type_error "logic fme_csr_pcie0_error.pcie0_error.format_type_error" +Toggle 0to1 fme_csr_pcie0_error.pcie0_error.comp_time_out_error "logic fme_csr_pcie0_error.pcie0_error.comp_time_out_error" +Toggle 0to1 fme_csr_pcie0_error.pcie0_error.comp_tag_error "logic fme_csr_pcie0_error.pcie0_error.comp_tag_error" +Toggle 0to1 fme_csr_pcie0_error.pcie0_error.comp_stat_error "logic fme_csr_pcie0_error.pcie0_error.comp_stat_error" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error_mask_reset.pcie0_error_mask.error_mask "logic fme_csr_pcie0_error_mask_reset.pcie0_error_mask.error_mask[12:0]" +ANNOTATION: " Excluding pcie error related siganls " +Toggle fme_csr_pcie0_error_mask_update.pcie0_error_mask.error_mask "logic fme_csr_pcie0_error_mask_update.pcie0_error_mask.error_mask[12:0]" +Toggle 0to1 fme_csr_pcie0_error_reset.pcie0_error.parity_error "logic fme_csr_pcie0_error_reset.pcie0_error.parity_error" +Toggle 0to1 fme_csr_pcie0_error_reset.pcie0_error.mw_length_error "logic fme_csr_pcie0_error_reset.pcie0_error.mw_length_error" +Toggle 0to1 fme_csr_pcie0_error_reset.pcie0_error.mw_addr_error "logic fme_csr_pcie0_error_reset.pcie0_error.mw_addr_error" +Toggle 0to1 fme_csr_pcie0_error_reset.pcie0_error.mr_length_error "logic fme_csr_pcie0_error_reset.pcie0_error.mr_length_error" +Toggle 0to1 fme_csr_pcie0_error_reset.pcie0_error.mr_addr_error "logic fme_csr_pcie0_error_reset.pcie0_error.mr_addr_error" +Toggle 0to1 fme_csr_pcie0_error_reset.pcie0_error.malformed_sop_error "logic fme_csr_pcie0_error_reset.pcie0_error.malformed_sop_error" +Toggle 0to1 fme_csr_pcie0_error_reset.pcie0_error.malformed_eop_error "logic fme_csr_pcie0_error_reset.pcie0_error.malformed_eop_error" +Toggle 0to1 fme_csr_pcie0_error_reset.pcie0_error.function_type_error "logic fme_csr_pcie0_error_reset.pcie0_error.function_type_error" +Toggle 0to1 fme_csr_pcie0_error_reset.pcie0_error.format_type_error "logic fme_csr_pcie0_error_reset.pcie0_error.format_type_error" +Toggle 0to1 fme_csr_pcie0_error_reset.pcie0_error.comp_time_out_error "logic fme_csr_pcie0_error_reset.pcie0_error.comp_time_out_error" +Toggle 0to1 fme_csr_pcie0_error_reset.pcie0_error.comp_tag_error "logic fme_csr_pcie0_error_reset.pcie0_error.comp_tag_error" +Toggle 0to1 fme_csr_pcie0_error_reset.pcie0_error.comp_stat_error "logic fme_csr_pcie0_error_reset.pcie0_error.comp_stat_error" +Toggle 0to1 fme_csr_fme_pr_error_reset.fme_pr_error.secure_load_failed "logic fme_csr_fme_pr_error_reset.fme_pr_error.secure_load_failed" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_error_update.word.upper32 "logic fme_csr_fme_pr_error_update.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_error_update.word.lower32 "logic fme_csr_fme_pr_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_pr_error_update.fme_pr_error.secure_load_failed "logic fme_csr_fme_pr_error_update.fme_pr_error.secure_load_failed" +Toggle 0to1 fme_csr_fme_pr_error_update.fme_pr_error.ip_init_protocol_error "logic fme_csr_fme_pr_error_update.fme_pr_error.ip_init_protocol_error" +Toggle 0to1 fme_csr_fme_pr_error_update.fme_pr_error.ip_init_incompatible_bitstream "logic fme_csr_fme_pr_error_update.fme_pr_error.ip_init_incompatible_bitstream" +Toggle 0to1 fme_csr_fme_pr_error_update.fme_pr_error.ip_init_crc_error "logic fme_csr_fme_pr_error_update.fme_pr_error.ip_init_crc_error" +Toggle 0to1 fme_csr_fme_pr_error_update.fme_pr_error.host_init_timeout "logic fme_csr_fme_pr_error_update.fme_pr_error.host_init_timeout" +Toggle 0to1 fme_csr_fme_pr_error_update.fme_pr_error.host_init_operation_error "logic fme_csr_fme_pr_error_update.fme_pr_error.host_init_operation_error" +Toggle 0to1 fme_csr_fme_pr_error_update.fme_pr_error.host_init_fifo_overflow "logic fme_csr_fme_pr_error_update.fme_pr_error.host_init_fifo_overflow" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_error_update.data "logic fme_csr_fme_pr_error_update.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_error_reset.word.upper32 "logic fme_csr_fme_pr_error_reset.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_error_reset.word.lower32 "logic fme_csr_fme_pr_error_reset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_error.data "logic fme_csr_fme_pr_error.data[63:0]" +Toggle 0to1 fme_csr_fme_pr_error_reset.fme_pr_error.ip_init_protocol_error "logic fme_csr_fme_pr_error_reset.fme_pr_error.ip_init_protocol_error" +Toggle 0to1 fme_csr_fme_pr_error_reset.fme_pr_error.ip_init_incompatible_bitstream "logic fme_csr_fme_pr_error_reset.fme_pr_error.ip_init_incompatible_bitstream" +Toggle 0to1 fme_csr_fme_pr_error_reset.fme_pr_error.ip_init_crc_error "logic fme_csr_fme_pr_error_reset.fme_pr_error.ip_init_crc_error" +Toggle 0to1 fme_csr_fme_pr_error_reset.fme_pr_error.host_init_timeout "logic fme_csr_fme_pr_error_reset.fme_pr_error.host_init_timeout" +Toggle 0to1 fme_csr_fme_pr_error_reset.fme_pr_error.host_init_operation_error "logic fme_csr_fme_pr_error_reset.fme_pr_error.host_init_operation_error" +Toggle 0to1 fme_csr_fme_pr_error_reset.fme_pr_error.host_init_fifo_overflow "logic fme_csr_fme_pr_error_reset.fme_pr_error.host_init_fifo_overflow" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_error_reset.data "logic fme_csr_fme_pr_error_reset.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_error.word.upper32 "logic fme_csr_fme_pr_error.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_error.word.lower32 "logic fme_csr_fme_pr_error.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_pr_error.fme_pr_error.secure_load_failed "logic fme_csr_fme_pr_error.fme_pr_error.secure_load_failed" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_error.fme_pr_error.reserved7 "logic fme_csr_fme_pr_error.fme_pr_error.reserved7[56:0]" +Toggle 0to1 fme_csr_fme_pr_error.fme_pr_error.ip_init_protocol_error "logic fme_csr_fme_pr_error.fme_pr_error.ip_init_protocol_error" +Toggle 0to1 fme_csr_fme_pr_error.fme_pr_error.ip_init_incompatible_bitstream "logic fme_csr_fme_pr_error.fme_pr_error.ip_init_incompatible_bitstream" +Toggle 0to1 fme_csr_fme_pr_error.fme_pr_error.ip_init_crc_error "logic fme_csr_fme_pr_error.fme_pr_error.ip_init_crc_error" +Toggle 0to1 fme_csr_fme_pr_error.fme_pr_error.host_init_timeout "logic fme_csr_fme_pr_error.fme_pr_error.host_init_timeout" +Toggle 0to1 fme_csr_fme_pr_error.fme_pr_error.host_init_operation_error "logic fme_csr_fme_pr_error.fme_pr_error.host_init_operation_error" +Toggle 0to1 fme_csr_fme_pr_error.fme_pr_error.host_init_fifo_overflow "logic fme_csr_fme_pr_error.fme_pr_error.host_init_fifo_overflow" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl_update.word.lower32 "logic fme_csr_fme_pr_ctrl_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_start_request "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_start_request" +Toggle 0to1 fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_reset_ack "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_reset_ack" +Toggle 0to1 fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_reset "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_reset" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_region_id "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_region_id[1:0]" +Toggle 0to1 fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_kind "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_kind" +Toggle 0to1 fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_data_push_complete "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_data_push_complete" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.config_data "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.config_data[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl_update.data "logic fme_csr_fme_pr_ctrl_update.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl_reset.word.upper32 "logic fme_csr_fme_pr_ctrl_reset.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl_reset.word.lower32 "logic fme_csr_fme_pr_ctrl_reset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_data_update.word.upper32 "logic fme_csr_fme_pr_data_update.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_data_update.word.lower32 "logic fme_csr_fme_pr_data_update.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_data_update.data "logic fme_csr_fme_pr_data_update.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_data_reset.word.upper32 "logic fme_csr_fme_pr_data_reset.word.upper32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_data_reset.word.lower32 "logic fme_csr_fme_pr_data_reset.word.lower32[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_data_reset.data "logic fme_csr_fme_pr_data_reset.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl_update.word.upper32 "logic fme_csr_fme_pr_ctrl_update.word.upper32[31:0]" +Toggle 0to1 fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_start_request "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_start_request" +Toggle 0to1 fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_reset "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_reset" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_region_id "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_region_id[1:0]" +Toggle 0to1 fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_kind "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_kind" +Toggle 0to1 fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_data_push_complete "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_data_push_complete" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.config_data "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.config_data[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl_reset.data "logic fme_csr_fme_pr_ctrl_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_error0.fme_error0.afu_access_mode_err "logic fme_csr_fme_error0.fme_error0.afu_access_mode_err" +Toggle 0to1 fme_csr_fme_error0_update.fme_error0.remote_stp_parity_error "logic fme_csr_fme_error0_update.fme_error0.remote_stp_parity_error" +Toggle 0to1 fme_csr_fme_error0_update.fme_error0.afu_access_mode_err "logic fme_csr_fme_error0_update.fme_error0.afu_access_mode_err" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_error0_reset.fme_error0.reserved6 "logic fme_csr_fme_error0_reset.fme_error0.reserved6[57:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_error0_reset.fme_error0.reserved2 "logic fme_csr_fme_error0_reset.fme_error0.reserved2[2:0]" +Toggle 0to1 fme_csr_fme_error0_reset.fme_error0.remote_stp_parity_error "logic fme_csr_fme_error0_reset.fme_error0.remote_stp_parity_error" +Toggle 0to1 fme_csr_fme_error0_reset.fme_error0.afu_access_mode_err "logic fme_csr_fme_error0_reset.fme_error0.afu_access_mode_err" +Toggle 0to1 fme_csr_fme_error0.fme_error0.remote_stp_parity_error "logic fme_csr_fme_error0.fme_error0.remote_stp_parity_error" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl.fme_pr_ctrl.config_data "logic fme_csr_fme_pr_ctrl.fme_pr_ctrl.config_data[31:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl.word.upper32 "logic fme_csr_fme_pr_ctrl.word.upper32[31:0]" +Toggle 0to1 fme_csr_fme_pr_ctrl.fme_pr_ctrl.pr_reset "logic fme_csr_fme_pr_ctrl.fme_pr_ctrl.pr_reset" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl.fme_pr_ctrl.pr_region_id "logic fme_csr_fme_pr_ctrl.fme_pr_ctrl.pr_region_id[1:0]" +Toggle 0to1 fme_csr_fme_pr_ctrl.fme_pr_ctrl.pr_kind "logic fme_csr_fme_pr_ctrl.fme_pr_ctrl.pr_kind" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_count_csr_reset.msix_count_csr.afu_2_sync_fifo_msix_count "logic fme_csr_msix_count_csr_reset.msix_count_csr.afu_2_sync_fifo_msix_count[7:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_count_csr_reset.msix_count_csr.cdc_2_avl_msix_count "logic fme_csr_msix_count_csr_reset.msix_count_csr.cdc_2_avl_msix_count[7:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_count_csr_reset.msix_count_csr.msix_2_cdc_msix_count "logic fme_csr_msix_count_csr_reset.msix_count_csr.msix_2_cdc_msix_count[7:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_count_csr_reset.msix_count_csr.reserved32 "logic fme_csr_msix_count_csr_reset.msix_count_csr.reserved32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_count_csr_reset.msix_count_csr.sync_fifo_2_msix_count "logic fme_csr_msix_count_csr_reset.msix_count_csr.sync_fifo_2_msix_count[7:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_count_csr_reset.word.lower32 "logic fme_csr_msix_count_csr_reset.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_count_csr_reset.word.upper32 "logic fme_csr_msix_count_csr_reset.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_count_csr_update.data "logic fme_csr_msix_count_csr_update.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_count_csr_update.msix_count_csr.afu_2_sync_fifo_msix_count "logic fme_csr_msix_count_csr_update.msix_count_csr.afu_2_sync_fifo_msix_count[7:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_count_csr_update.msix_count_csr.cdc_2_avl_msix_count "logic fme_csr_msix_count_csr_update.msix_count_csr.cdc_2_avl_msix_count[7:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_count_csr_update.msix_count_csr.msix_2_cdc_msix_count "logic fme_csr_msix_count_csr_update.msix_count_csr.msix_2_cdc_msix_count[7:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_count_csr_update.msix_count_csr.sync_fifo_2_msix_count "logic fme_csr_msix_count_csr_update.msix_count_csr.sync_fifo_2_msix_count[7:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_count_csr_update.word.lower32 "logic fme_csr_msix_count_csr_update.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_count_csr_update.word.upper32 "logic fme_csr_msix_count_csr_update.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat0.data "logic fme_csr_msix_ctldat0.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat0.msix_ctldat.msg_control "logic fme_csr_msix_ctldat0.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat0.msix_ctldat.msg_data "logic fme_csr_msix_ctldat0.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat0.word.lower32 "logic fme_csr_msix_ctldat0.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat0.word.upper32 "logic fme_csr_msix_ctldat0.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat0_reset.data "logic fme_csr_msix_ctldat0_reset.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat0_reset.msix_ctldat.msg_control "logic fme_csr_msix_ctldat0_reset.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat0_reset.msix_ctldat.msg_data "logic fme_csr_msix_ctldat0_reset.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat0_reset.word.lower32 "logic fme_csr_msix_ctldat0_reset.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat0_reset.word.upper32 "logic fme_csr_msix_ctldat0_reset.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat0_update.data "logic fme_csr_msix_ctldat0_update.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat0_update.msix_ctldat.msg_control "logic fme_csr_msix_ctldat0_update.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat0_update.msix_ctldat.msg_data "logic fme_csr_msix_ctldat0_update.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat0_update.word.lower32 "logic fme_csr_msix_ctldat0_update.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat0_update.word.upper32 "logic fme_csr_msix_ctldat0_update.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat1.data "logic fme_csr_msix_ctldat1.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat1.msix_ctldat.msg_control "logic fme_csr_msix_ctldat1.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat1.msix_ctldat.msg_data "logic fme_csr_msix_ctldat1.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat1.word.lower32 "logic fme_csr_msix_ctldat1.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat1.word.upper32 "logic fme_csr_msix_ctldat1.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat1_reset.data "logic fme_csr_msix_ctldat1_reset.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat1_reset.msix_ctldat.msg_control "logic fme_csr_msix_ctldat1_reset.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat1_reset.msix_ctldat.msg_data "logic fme_csr_msix_ctldat1_reset.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat1_reset.word.lower32 "logic fme_csr_msix_ctldat1_reset.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat1_reset.word.upper32 "logic fme_csr_msix_ctldat1_reset.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat1_update.data "logic fme_csr_msix_ctldat1_update.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat1_update.msix_ctldat.msg_control "logic fme_csr_msix_ctldat1_update.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat1_update.msix_ctldat.msg_data "logic fme_csr_msix_ctldat1_update.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat1_update.word.lower32 "logic fme_csr_msix_ctldat1_update.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat1_update.word.upper32 "logic fme_csr_msix_ctldat1_update.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat2.data "logic fme_csr_msix_ctldat2.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat2.msix_ctldat.msg_control "logic fme_csr_msix_ctldat2.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat2.msix_ctldat.msg_data "logic fme_csr_msix_ctldat2.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat2.word.lower32 "logic fme_csr_msix_ctldat2.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat2.word.upper32 "logic fme_csr_msix_ctldat2.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat2_reset.data "logic fme_csr_msix_ctldat2_reset.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat2_reset.msix_ctldat.msg_control "logic fme_csr_msix_ctldat2_reset.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat2_reset.msix_ctldat.msg_data "logic fme_csr_msix_ctldat2_reset.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat2_reset.word.lower32 "logic fme_csr_msix_ctldat2_reset.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat2_reset.word.upper32 "logic fme_csr_msix_ctldat2_reset.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat2_update.data "logic fme_csr_msix_ctldat2_update.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat2_update.msix_ctldat.msg_control "logic fme_csr_msix_ctldat2_update.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat2_update.msix_ctldat.msg_data "logic fme_csr_msix_ctldat2_update.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat2_update.word.lower32 "logic fme_csr_msix_ctldat2_update.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat2_update.word.upper32 "logic fme_csr_msix_ctldat2_update.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat3.data "logic fme_csr_msix_ctldat3.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat3.msix_ctldat.msg_control "logic fme_csr_msix_ctldat3.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat3.msix_ctldat.msg_data "logic fme_csr_msix_ctldat3.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat3.word.lower32 "logic fme_csr_msix_ctldat3.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat3.word.upper32 "logic fme_csr_msix_ctldat3.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat3_reset.data "logic fme_csr_msix_ctldat3_reset.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat3_reset.msix_ctldat.msg_control "logic fme_csr_msix_ctldat3_reset.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat3_reset.msix_ctldat.msg_data "logic fme_csr_msix_ctldat3_reset.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat3_reset.word.lower32 "logic fme_csr_msix_ctldat3_reset.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat3_reset.word.upper32 "logic fme_csr_msix_ctldat3_reset.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat3_update.data "logic fme_csr_msix_ctldat3_update.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat3_update.msix_ctldat.msg_control "logic fme_csr_msix_ctldat3_update.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat3_update.msix_ctldat.msg_data "logic fme_csr_msix_ctldat3_update.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat3_update.word.lower32 "logic fme_csr_msix_ctldat3_update.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat3_update.word.upper32 "logic fme_csr_msix_ctldat3_update.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat4.data "logic fme_csr_msix_ctldat4.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat4.msix_ctldat.msg_control "logic fme_csr_msix_ctldat4.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat4.msix_ctldat.msg_data "logic fme_csr_msix_ctldat4.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat4.word.lower32 "logic fme_csr_msix_ctldat4.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat4.word.upper32 "logic fme_csr_msix_ctldat4.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat4_reset.data "logic fme_csr_msix_ctldat4_reset.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat4_reset.msix_ctldat.msg_control "logic fme_csr_msix_ctldat4_reset.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat4_reset.msix_ctldat.msg_data "logic fme_csr_msix_ctldat4_reset.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat4_reset.word.lower32 "logic fme_csr_msix_ctldat4_reset.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat4_reset.word.upper32 "logic fme_csr_msix_ctldat4_reset.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat4_update.data "logic fme_csr_msix_ctldat4_update.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat4_update.msix_ctldat.msg_control "logic fme_csr_msix_ctldat4_update.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat4_update.msix_ctldat.msg_data "logic fme_csr_msix_ctldat4_update.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat4_update.word.lower32 "logic fme_csr_msix_ctldat4_update.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat4_update.word.upper32 "logic fme_csr_msix_ctldat4_update.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat5.data "logic fme_csr_msix_ctldat5.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat5.msix_ctldat.msg_control "logic fme_csr_msix_ctldat5.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat5.msix_ctldat.msg_data "logic fme_csr_msix_ctldat5.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat5.word.lower32 "logic fme_csr_msix_ctldat5.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat5.word.upper32 "logic fme_csr_msix_ctldat5.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat5_reset.data "logic fme_csr_msix_ctldat5_reset.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat5_reset.msix_ctldat.msg_control "logic fme_csr_msix_ctldat5_reset.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat5_reset.msix_ctldat.msg_data "logic fme_csr_msix_ctldat5_reset.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat5_reset.word.lower32 "logic fme_csr_msix_ctldat5_reset.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat5_reset.word.upper32 "logic fme_csr_msix_ctldat5_reset.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat5_update.data "logic fme_csr_msix_ctldat5_update.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat5_update.msix_ctldat.msg_control "logic fme_csr_msix_ctldat5_update.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat5_update.msix_ctldat.msg_data "logic fme_csr_msix_ctldat5_update.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat5_update.word.lower32 "logic fme_csr_msix_ctldat5_update.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat5_update.word.upper32 "logic fme_csr_msix_ctldat5_update.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat6.data "logic fme_csr_msix_ctldat6.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat6.msix_ctldat.msg_control "logic fme_csr_msix_ctldat6.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat6.msix_ctldat.msg_data "logic fme_csr_msix_ctldat6.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat6.word.lower32 "logic fme_csr_msix_ctldat6.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat6.word.upper32 "logic fme_csr_msix_ctldat6.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat6_reset.data "logic fme_csr_msix_ctldat6_reset.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat6_reset.msix_ctldat.msg_control "logic fme_csr_msix_ctldat6_reset.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat6_reset.msix_ctldat.msg_data "logic fme_csr_msix_ctldat6_reset.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat6_reset.word.lower32 "logic fme_csr_msix_ctldat6_reset.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat6_reset.word.upper32 "logic fme_csr_msix_ctldat6_reset.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat6_update.data "logic fme_csr_msix_ctldat6_update.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat6_update.msix_ctldat.msg_control "logic fme_csr_msix_ctldat6_update.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat6_update.msix_ctldat.msg_data "logic fme_csr_msix_ctldat6_update.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat6_update.word.lower32 "logic fme_csr_msix_ctldat6_update.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat6_update.word.upper32 "logic fme_csr_msix_ctldat6_update.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat7.data "logic fme_csr_msix_ctldat7.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat7.msix_ctldat.msg_control "logic fme_csr_msix_ctldat7.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat7.msix_ctldat.msg_data "logic fme_csr_msix_ctldat7.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat7.word.lower32 "logic fme_csr_msix_ctldat7.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat7.word.upper32 "logic fme_csr_msix_ctldat7.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat7_reset.data "logic fme_csr_msix_ctldat7_reset.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat7_reset.msix_ctldat.msg_control "logic fme_csr_msix_ctldat7_reset.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat7_reset.msix_ctldat.msg_data "logic fme_csr_msix_ctldat7_reset.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat7_reset.word.lower32 "logic fme_csr_msix_ctldat7_reset.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat7_reset.word.upper32 "logic fme_csr_msix_ctldat7_reset.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat7_update.data "logic fme_csr_msix_ctldat7_update.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat7_update.msix_ctldat.msg_control "logic fme_csr_msix_ctldat7_update.msix_ctldat.msg_control[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat7_update.msix_ctldat.msg_data "logic fme_csr_msix_ctldat7_update.msix_ctldat.msg_data[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat7_update.word.lower32 "logic fme_csr_msix_ctldat7_update.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_ctldat7_update.word.upper32 "logic fme_csr_msix_ctldat7_update.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_pba.data "logic fme_csr_msix_pba.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_pba.msix_pba.msix_pba "logic fme_csr_msix_pba.msix_pba.msix_pba[6:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_pba.word.lower32 "logic fme_csr_msix_pba.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_pba.word.upper32 "logic fme_csr_msix_pba.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_pba_reset.data "logic fme_csr_msix_pba_reset.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_pba_reset.msix_pba.msix_pba "logic fme_csr_msix_pba_reset.msix_pba.msix_pba[6:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_pba_reset.word.lower32 "logic fme_csr_msix_pba_reset.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_pba_reset.word.upper32 "logic fme_csr_msix_pba_reset.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_pba_update.data "logic fme_csr_msix_pba_update.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_pba_update.msix_pba.msix_pba "logic fme_csr_msix_pba_update.msix_pba.msix_pba[6:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_pba_update.word.lower32 "logic fme_csr_msix_pba_update.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_pba_update.word.upper32 "logic fme_csr_msix_pba_update.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_count_csr_reset.data "logic fme_csr_msix_count_csr_reset.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr0.msix_addr.msg_addr_low "logic fme_csr_msix_addr0.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr0.msix_addr.msg_addr_upp "logic fme_csr_msix_addr0.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr0.word.lower32 "logic fme_csr_msix_addr0.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr0.word.upper32 "logic fme_csr_msix_addr0.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr0_reset.data "logic fme_csr_msix_addr0_reset.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr0_reset.msix_addr.msg_addr_low "logic fme_csr_msix_addr0_reset.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr0_reset.msix_addr.msg_addr_upp "logic fme_csr_msix_addr0_reset.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr0_reset.word.lower32 "logic fme_csr_msix_addr0_reset.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr0_reset.word.upper32 "logic fme_csr_msix_addr0_reset.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr0_update.data "logic fme_csr_msix_addr0_update.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr0_update.msix_addr.msg_addr_low "logic fme_csr_msix_addr0_update.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr0_update.msix_addr.msg_addr_upp "logic fme_csr_msix_addr0_update.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr0_update.word.lower32 "logic fme_csr_msix_addr0_update.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr0_update.word.upper32 "logic fme_csr_msix_addr0_update.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr1.data "logic fme_csr_msix_addr1.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr1.msix_addr.msg_addr_low "logic fme_csr_msix_addr1.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr1.msix_addr.msg_addr_upp "logic fme_csr_msix_addr1.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr1.word.lower32 "logic fme_csr_msix_addr1.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr1.word.upper32 "logic fme_csr_msix_addr1.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr1_reset.data "logic fme_csr_msix_addr1_reset.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr1_reset.msix_addr.msg_addr_low "logic fme_csr_msix_addr1_reset.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr1_reset.msix_addr.msg_addr_upp "logic fme_csr_msix_addr1_reset.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr1_reset.word.lower32 "logic fme_csr_msix_addr1_reset.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr1_reset.word.upper32 "logic fme_csr_msix_addr1_reset.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr1_update.data "logic fme_csr_msix_addr1_update.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr1_update.msix_addr.msg_addr_low "logic fme_csr_msix_addr1_update.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr1_update.msix_addr.msg_addr_upp "logic fme_csr_msix_addr1_update.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr1_update.word.lower32 "logic fme_csr_msix_addr1_update.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr1_update.word.upper32 "logic fme_csr_msix_addr1_update.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr2.data "logic fme_csr_msix_addr2.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr2.msix_addr.msg_addr_low "logic fme_csr_msix_addr2.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr2.msix_addr.msg_addr_upp "logic fme_csr_msix_addr2.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr2.word.lower32 "logic fme_csr_msix_addr2.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr2.word.upper32 "logic fme_csr_msix_addr2.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr2_reset.data "logic fme_csr_msix_addr2_reset.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr2_reset.msix_addr.msg_addr_low "logic fme_csr_msix_addr2_reset.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr2_reset.msix_addr.msg_addr_upp "logic fme_csr_msix_addr2_reset.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr2_reset.word.lower32 "logic fme_csr_msix_addr2_reset.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr2_reset.word.upper32 "logic fme_csr_msix_addr2_reset.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr2_update.data "logic fme_csr_msix_addr2_update.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr2_update.msix_addr.msg_addr_low "logic fme_csr_msix_addr2_update.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr2_update.msix_addr.msg_addr_upp "logic fme_csr_msix_addr2_update.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr2_update.word.lower32 "logic fme_csr_msix_addr2_update.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr2_update.word.upper32 "logic fme_csr_msix_addr2_update.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr3.data "logic fme_csr_msix_addr3.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr3.msix_addr.msg_addr_low "logic fme_csr_msix_addr3.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr3.msix_addr.msg_addr_upp "logic fme_csr_msix_addr3.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr3.word.lower32 "logic fme_csr_msix_addr3.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr3.word.upper32 "logic fme_csr_msix_addr3.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr3_reset.data "logic fme_csr_msix_addr3_reset.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr3_reset.msix_addr.msg_addr_low "logic fme_csr_msix_addr3_reset.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr3_reset.msix_addr.msg_addr_upp "logic fme_csr_msix_addr3_reset.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr3_reset.word.lower32 "logic fme_csr_msix_addr3_reset.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr3_reset.word.upper32 "logic fme_csr_msix_addr3_reset.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr3_update.data "logic fme_csr_msix_addr3_update.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr3_update.msix_addr.msg_addr_low "logic fme_csr_msix_addr3_update.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr3_update.msix_addr.msg_addr_upp "logic fme_csr_msix_addr3_update.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr3_update.word.lower32 "logic fme_csr_msix_addr3_update.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr3_update.word.upper32 "logic fme_csr_msix_addr3_update.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr4.data "logic fme_csr_msix_addr4.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr4.msix_addr.msg_addr_low "logic fme_csr_msix_addr4.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr4.msix_addr.msg_addr_upp "logic fme_csr_msix_addr4.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr4.word.lower32 "logic fme_csr_msix_addr4.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr4.word.upper32 "logic fme_csr_msix_addr4.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr4_reset.data "logic fme_csr_msix_addr4_reset.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr4_reset.msix_addr.msg_addr_low "logic fme_csr_msix_addr4_reset.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr4_reset.msix_addr.msg_addr_upp "logic fme_csr_msix_addr4_reset.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr4_reset.word.lower32 "logic fme_csr_msix_addr4_reset.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr4_reset.word.upper32 "logic fme_csr_msix_addr4_reset.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr4_update.data "logic fme_csr_msix_addr4_update.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr4_update.msix_addr.msg_addr_low "logic fme_csr_msix_addr4_update.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr4_update.msix_addr.msg_addr_upp "logic fme_csr_msix_addr4_update.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr4_update.word.lower32 "logic fme_csr_msix_addr4_update.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr4_update.word.upper32 "logic fme_csr_msix_addr4_update.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr5.data "logic fme_csr_msix_addr5.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr5.msix_addr.msg_addr_low "logic fme_csr_msix_addr5.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr5.msix_addr.msg_addr_upp "logic fme_csr_msix_addr5.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr5.word.lower32 "logic fme_csr_msix_addr5.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr5.word.upper32 "logic fme_csr_msix_addr5.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr5_reset.data "logic fme_csr_msix_addr5_reset.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr5_reset.msix_addr.msg_addr_low "logic fme_csr_msix_addr5_reset.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr5_reset.msix_addr.msg_addr_upp "logic fme_csr_msix_addr5_reset.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr5_reset.word.lower32 "logic fme_csr_msix_addr5_reset.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr5_reset.word.upper32 "logic fme_csr_msix_addr5_reset.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr5_update.data "logic fme_csr_msix_addr5_update.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr5_update.msix_addr.msg_addr_low "logic fme_csr_msix_addr5_update.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr5_update.msix_addr.msg_addr_upp "logic fme_csr_msix_addr5_update.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr5_update.word.lower32 "logic fme_csr_msix_addr5_update.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr5_update.word.upper32 "logic fme_csr_msix_addr5_update.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr6.data "logic fme_csr_msix_addr6.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr6.msix_addr.msg_addr_low "logic fme_csr_msix_addr6.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr6.msix_addr.msg_addr_upp "logic fme_csr_msix_addr6.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr6.word.lower32 "logic fme_csr_msix_addr6.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr6.word.upper32 "logic fme_csr_msix_addr6.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr6_reset.data "logic fme_csr_msix_addr6_reset.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr6_reset.msix_addr.msg_addr_low "logic fme_csr_msix_addr6_reset.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr6_reset.msix_addr.msg_addr_upp "logic fme_csr_msix_addr6_reset.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr6_reset.word.lower32 "logic fme_csr_msix_addr6_reset.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr6_reset.word.upper32 "logic fme_csr_msix_addr6_reset.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr6_update.data "logic fme_csr_msix_addr6_update.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr6_update.msix_addr.msg_addr_low "logic fme_csr_msix_addr6_update.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr6_update.msix_addr.msg_addr_upp "logic fme_csr_msix_addr6_update.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr6_update.word.lower32 "logic fme_csr_msix_addr6_update.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr6_update.word.upper32 "logic fme_csr_msix_addr6_update.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr7.data "logic fme_csr_msix_addr7.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr7.msix_addr.msg_addr_low "logic fme_csr_msix_addr7.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr7.msix_addr.msg_addr_upp "logic fme_csr_msix_addr7.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr7.word.lower32 "logic fme_csr_msix_addr7.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr7.word.upper32 "logic fme_csr_msix_addr7.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr7_reset.data "logic fme_csr_msix_addr7_reset.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr7_reset.msix_addr.msg_addr_low "logic fme_csr_msix_addr7_reset.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr7_reset.msix_addr.msg_addr_upp "logic fme_csr_msix_addr7_reset.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr7_reset.word.lower32 "logic fme_csr_msix_addr7_reset.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr7_reset.word.upper32 "logic fme_csr_msix_addr7_reset.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr7_update.data "logic fme_csr_msix_addr7_update.data[63:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr7_update.msix_addr.msg_addr_low "logic fme_csr_msix_addr7_update.msix_addr.msg_addr_low[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr7_update.msix_addr.msg_addr_upp "logic fme_csr_msix_addr7_update.msix_addr.msg_addr_upp[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr7_update.word.lower32 "logic fme_csr_msix_addr7_update.word.lower32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr7_update.word.upper32 "logic fme_csr_msix_addr7_update.word.upper32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_addr0.data "logic fme_csr_msix_addr0.data[63:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_pr_status_attr.fme_pr_status.reserved23 "logic fme_pr_status_attr.fme_pr_status.reserved23[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_error0_update.fme_error0.reserved2 "logic fme_csr_fme_error0_update.fme_error0.reserved2[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_error0_update.fme_error0.reserved6 "logic fme_csr_fme_error0_update.fme_error0.reserved6[57:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_error_mask0.fme_error_mask0.reserved2 "logic fme_csr_fme_error_mask0.fme_error_mask0.reserved2[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_error_mask0.fme_error_mask0.reserved6 "logic fme_csr_fme_error_mask0.fme_error_mask0.reserved6[57:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_error_mask0_reset.fme_error_mask0.reserved2 "logic fme_csr_fme_error_mask0_reset.fme_error_mask0.reserved2[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_error_mask0_reset.fme_error_mask0.reserved6 "logic fme_csr_fme_error_mask0_reset.fme_error_mask0.reserved6[57:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_error_mask0_update.fme_error_mask0.reserved2 "logic fme_csr_fme_error_mask0_update.fme_error_mask0.reserved2[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_error_mask0_update.fme_error_mask0.reserved6 "logic fme_csr_fme_error_mask0_update.fme_error_mask0.reserved6[57:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl.fme_pr_ctrl.reserved1 "logic fme_csr_fme_pr_ctrl.fme_pr_ctrl.reserved1[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl.fme_pr_ctrl.reserved5 "logic fme_csr_fme_pr_ctrl.fme_pr_ctrl.reserved5[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl.fme_pr_ctrl.reserved10 "logic fme_csr_fme_pr_ctrl.fme_pr_ctrl.reserved10[1:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl.fme_pr_ctrl.reserved15 "logic fme_csr_fme_pr_ctrl.fme_pr_ctrl.reserved15[16:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.reserved1 "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.reserved1[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.reserved5 "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.reserved5[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.reserved10 "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.reserved10[1:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.reserved15 "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.reserved15[16:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.reserved1 "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.reserved1[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.reserved5 "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.reserved5[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.reserved10 "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.reserved10[1:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.reserved15 "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.reserved15[16:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status.fme_pr_status.reserved9 "logic fme_csr_fme_pr_status.fme_pr_status.reserved9[6:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status.fme_pr_status.reserved17 "logic fme_csr_fme_pr_status.fme_pr_status.reserved17[2:0]" +Toggle 0to1 fme_csr_fme_pr_status.fme_pr_status.reserved23 "logic fme_csr_fme_pr_status.fme_pr_status.reserved23" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status.fme_pr_status.reserved28 "logic fme_csr_fme_pr_status.fme_pr_status.reserved28[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status_reset.fme_pr_status.reserved9 "logic fme_csr_fme_pr_status_reset.fme_pr_status.reserved9[6:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status_reset.fme_pr_status.reserved17 "logic fme_csr_fme_pr_status_reset.fme_pr_status.reserved17[2:0]" +Toggle 0to1 fme_csr_fme_pr_status_reset.fme_pr_status.reserved23 "logic fme_csr_fme_pr_status_reset.fme_pr_status.reserved23" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status_reset.fme_pr_status.reserved28 "logic fme_csr_fme_pr_status_reset.fme_pr_status.reserved28[3:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status_update.fme_pr_status.reserved9 "logic fme_csr_fme_pr_status_update.fme_pr_status.reserved9[6:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status_update.fme_pr_status.reserved17 "logic fme_csr_fme_pr_status_update.fme_pr_status.reserved17[2:0]" +Toggle 0to1 fme_csr_fme_pr_status_update.fme_pr_status.reserved23 "logic fme_csr_fme_pr_status_update.fme_pr_status.reserved23" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_status_update.fme_pr_status.reserved28 "logic fme_csr_fme_pr_status_update.fme_pr_status.reserved28[3:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_count_csr_update.msix_count_csr.reserved32 "logic fme_csr_msix_count_csr_update.msix_count_csr.reserved32[31:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_pba.msix_pba.reserved7 "logic fme_csr_msix_pba.msix_pba.reserved7[56:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_pba_reset.msix_pba.reserved7 "logic fme_csr_msix_pba_reset.msix_pba.reserved7[56:0]" +ANNOTATION: " Excluding MSIX signals as it is moved to pciess " +Toggle fme_csr_msix_pba_update.msix_pba.reserved7 "logic fme_csr_msix_pba_update.msix_pba.reserved7[56:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_error0.fme_error0.reserved2 "logic fme_csr_fme_error0.fme_error0.reserved2[2:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_error0.fme_error0.reserved6 "logic fme_csr_fme_error0.fme_error0.reserved6[57:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_dfh_update.dfh.reserved "logic fme_csr_fme_pr_dfh_update.dfh.reserved[18:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_dfh_reset.dfh.reserved "logic fme_csr_fme_pr_dfh_reset.dfh.reserved[18:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_error_reset.fme_pr_error.reserved7 "logic fme_csr_fme_pr_error_reset.fme_pr_error.reserved7[56:0]" +ANNOTATION: " Excluding as mentioned in the FME Excel sheet comment section located in the Coverage directory " +Toggle fme_csr_fme_pr_error_update.fme_pr_error.reserved7 "logic fme_csr_fme_pr_error_update.fme_pr_error.reserved7[56:0]" diff --git a/verification/coverage/he_hssi_exclusions.el b/verification/coverage/he_hssi_exclusions.el new file mode 100644 index 0000000..07a2652 --- /dev/null +++ b/verification/coverage/he_hssi_exclusions.el @@ -0,0 +1,3604 @@ +//================================================== +// This file contains the Excluded objects +// Generated By User: srudrarx +// Format Version: 2 +// Date: Wed May 4 00:41:03 2022 +// ExclMode: default +//================================================== +CHECKSUM: "3630569307" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.pcie_tlp_to_csr_no_dma_inst.axis_tx_mmio_bridge.rsp_fifo.dev +CHECKSUM: "3630569307" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.pcie_tlp_to_csr_no_dma_inst.axis_tx_mmio_bridge.ctt_fifo.dev +CHECKSUM: "2100166288" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.pcie_tlp_to_csr_no_dma_inst.axis_tx_mmio_bridge.rsp_fifo +CHECKSUM: "2100166288" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.pcie_tlp_to_csr_no_dma_inst.axis_tx_mmio_bridge.ctt_fifo +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.read_sync.sr.resync_chains[0].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.write_sync.sr.resync_chains[0].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_waitrequest_sync.sr.resync_chains[0].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_address_sync.resync_chains[0].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_address_sync.resync_chains[1].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_address_sync.resync_chains[2].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_address_sync.resync_chains[3].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_address_sync.resync_chains[4].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_address_sync.resync_chains[5].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_address_sync.resync_chains[6].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_address_sync.resync_chains[7].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_address_sync.resync_chains[8].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_address_sync.resync_chains[9].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_address_sync.resync_chains[10].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_address_sync.resync_chains[11].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_address_sync.resync_chains[12].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_address_sync.resync_chains[13].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_address_sync.resync_chains[14].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_address_sync.resync_chains[15].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[0].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[1].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[2].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[3].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[4].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[5].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[6].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[7].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[8].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[9].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[10].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[11].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[12].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[13].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[14].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[15].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[16].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[17].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[18].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[19].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[20].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[21].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[22].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[23].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[24].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[25].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[26].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[27].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[28].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[29].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[30].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_writedata_sync.resync_chains[31].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[0].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[1].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[2].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[3].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[4].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[5].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[6].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[7].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[8].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[9].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[10].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[11].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[12].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[13].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[14].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[15].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[16].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[17].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[18].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[19].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[20].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[21].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[22].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[23].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[24].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[25].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[26].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[27].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[28].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[29].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[30].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.csr_readdata_sync.resync_chains[31].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.GenRstSync[0].tx_reset_synchronizer.resync_chains[0].genblk1.synchronizer +CHECKSUM: "3815094446" +ANNOTATION: " Supported in R1 ,not used in AC " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.afu_eth_sideband_rx[0] +CHECKSUM: "3815094446" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.afu_eth_sideband_rx[0] +CHECKSUM: "3013853906" +ANNOTATION: " Supported in R1 ,not used in AC " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.afu_eth_sideband_tx[0] +CHECKSUM: "3013853906" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.afu_eth_sideband_tx[0] +CHECKSUM: "850135230" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.GEN.GenCRC.shiftreg_data_inst.altshift_taps_component +CHECKSUM: "850135230" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.GEN.GenCRC.shiftreg_ctrl_inst.altshift_taps_component +CHECKSUM: "2434476486" +ANNOTATION: " Supported in R1 ,not used in AC " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.s_eth_sb_rx_avst[0] +CHECKSUM: "2434476486" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.s_eth_sb_rx_avst[0] +CHECKSUM: "2557330075" +ANNOTATION: " Supported in R1 ,not used in AC " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.s_eth_sb_tx_avst[0] +CHECKSUM: "2557330075" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.s_eth_sb_tx_avst[0] +CHECKSUM: "1942594609 953055103" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.GenBrdg[0].axis_to_avst_bridge_inst +ANNOTATION: " tready is tied to 1 " +Condition 1 "1862443070" "(axi_rx_st.rx.tvalid && axi_rx_st.tready) 1 -1" (2 "10") +CHECKSUM: "1269902960 3446797902" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.GEN +Branch 26 "1906110039" "ps" (3) "ps state_dest_src ,-,0,-,-,-,-,-" +Branch 26 "1906110039" "ps" (6) "ps state_src_len_seq ,-,-,0,0,-,-,-" +Branch 26 "1906110039" "ps" (11) "ps state_transition ,-,-,-,-,-,0,0" +Branch 26 "1906110039" "ps" (12) "ps default,-,-,-,-,-,-,-" +CHECKSUM: "620743534 4163208780" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.MON +Branch 3 "3782849332" "reset" (3) "reset 0,1,8'h80 " +Branch 3 "3782849332" "reset" (4) "reset 0,1,8'h81 " +Branch 3 "3782849332" "reset" (5) "reset 0,1,8'h82 " +Branch 3 "3782849332" "reset" (6) "reset 0,1,default" +Branch 3 "3782849332" "reset" (2) "reset 0,1,8'h0a " +CHECKSUM: "1269902960 227287185" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.GEN +Toggle config_setting "reg config_setting[31:0]" +CHECKSUM: "1432213158 2031660678" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.afu_eth_rx_st[0] +Toggle 1to0 rx.tuser.error [5] "logic rx.tuser.error[5:0]" +Toggle 0to1 rx.tuser.error [5] "logic rx.tuser.error[5:0]" +Toggle 1to0 enable_assertion "logic enable_assertion" +CHECKSUM: "3434828227 1634887101" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst +Toggle 0to1 o_avmm_addr [15] "logic o_avmm_addr[15:0]" +Toggle 1to0 o_avmm_addr [15] "logic o_avmm_addr[15:0]" +Toggle 0to1 o_avmm_addr [4] "logic o_avmm_addr[15:0]" +Toggle 1to0 o_avmm_addr [4] "logic o_avmm_addr[15:0]" +Toggle 0to1 o_avmm_addr [5] "logic o_avmm_addr[15:0]" +Toggle 1to0 o_avmm_addr [5] "logic o_avmm_addr[15:0]" +Toggle 0to1 o_avmm_addr [6] "logic o_avmm_addr[15:0]" +Toggle 1to0 o_avmm_addr [6] "logic o_avmm_addr[15:0]" +Toggle 0to1 o_avmm_addr [7] "logic o_avmm_addr[15:0]" +Toggle 1to0 o_avmm_addr [7] "logic o_avmm_addr[15:0]" +Toggle 0to1 o_avmm_addr [14] "logic o_avmm_addr[15:0]" +Toggle 1to0 o_avmm_addr [14] "logic o_avmm_addr[15:0]" +Toggle 1to0 o_avmm_addr [13] "logic o_avmm_addr[15:0]" +Toggle 1to0 o_avmm_addr [11] "logic o_avmm_addr[15:0]" +Toggle 1to0 o_avmm_addr [12] "logic o_avmm_addr[15:0]" +Toggle 0to1 o_avmm_addr [10] "logic o_avmm_addr[15:0]" +Toggle 1to0 o_avmm_addr [10] "logic o_avmm_addr[15:0]" +Toggle 0to1 cmd_csr_addr [1] "logic cmd_csr_addr[11:0]" +Toggle 1to0 cmd_csr_addr [1] "logic cmd_csr_addr[11:0]" +Toggle 0to1 cmd_csr_addr [0] "logic cmd_csr_addr[11:0]" +Toggle 1to0 cmd_csr_addr [0] "logic cmd_csr_addr[11:0]" +Toggle 0to1 cmd_csr_addr [11] "logic cmd_csr_addr[11:0]" +Toggle 1to0 cmd_csr_addr [11] "logic cmd_csr_addr[11:0]" +Toggle 0to1 cmd_csr_addr [7] "logic cmd_csr_addr[11:0]" +Toggle 1to0 cmd_csr_addr [7] "logic cmd_csr_addr[11:0]" +Toggle 0to1 cmd_csr_addr [8] "logic cmd_csr_addr[11:0]" +Toggle 1to0 cmd_csr_addr [8] "logic cmd_csr_addr[11:0]" +Toggle 0to1 cmd_csr_addr [9] "logic cmd_csr_addr[11:0]" +Toggle 1to0 cmd_csr_addr [9] "logic cmd_csr_addr[11:0]" +Toggle 0to1 cmd_csr_addr [10] "logic cmd_csr_addr[11:0]" +Toggle 1to0 cmd_csr_addr [10] "logic cmd_csr_addr[11:0]" +Toggle csr_wr_type "logic csr_wr_type[1:0]" +Toggle axis_rx_length "logic axis_rx_length[13:0]" +Toggle axis_rx_length_q "logic axis_rx_length_q[13:0]" +CHECKSUM: "145423899 686185349" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.pcie_tlp_to_csr_no_dma_inst.axis_rx_mmio_bridge +Block 38 "3616434657" "RxReadyNextState = ST_WAIT_FOR_VALID;" +Block 42 "154345823" "RxReadyNextState = ST_READY;" +CHECKSUM: "3559185232 3561088615" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.avalon_st_loopback_u0.avalon_st_loopback_ena_csr_inst +Toggle 1to0 avalon_st_loopback_ena "reg avalon_st_loopback_ena" +Toggle 1to0 readdata [0] "reg readdata[31:0]" +Toggle 1to0 readdata [1] "reg readdata[31:0]" +Toggle 1to0 readdata [30] "reg readdata[31:0]" +Toggle 0to1 readdata [30] "reg readdata[31:0]" +Toggle 1to0 readdata [29] "reg readdata[31:0]" +Toggle 0to1 readdata [29] "reg readdata[31:0]" +Toggle 1to0 readdata [28] "reg readdata[31:0]" +Toggle 0to1 readdata [28] "reg readdata[31:0]" +Toggle 1to0 readdata [27] "reg readdata[31:0]" +Toggle 0to1 readdata [27] "reg readdata[31:0]" +Toggle 1to0 readdata [26] "reg readdata[31:0]" +Toggle 0to1 readdata [26] "reg readdata[31:0]" +Toggle 1to0 readdata [25] "reg readdata[31:0]" +Toggle 0to1 readdata [25] "reg readdata[31:0]" +Toggle 1to0 readdata [24] "reg readdata[31:0]" +Toggle 0to1 readdata [24] "reg readdata[31:0]" +Toggle 1to0 readdata [23] "reg readdata[31:0]" +Toggle 0to1 readdata [23] "reg readdata[31:0]" +Toggle 1to0 readdata [22] "reg readdata[31:0]" +Toggle 0to1 readdata [22] "reg readdata[31:0]" +Toggle 1to0 readdata [21] "reg readdata[31:0]" +Toggle 0to1 readdata [21] "reg readdata[31:0]" +Toggle 1to0 readdata [20] "reg readdata[31:0]" +Toggle 0to1 readdata [20] "reg readdata[31:0]" +Toggle 1to0 readdata [19] "reg readdata[31:0]" +Toggle 0to1 readdata [19] "reg readdata[31:0]" +Toggle 1to0 readdata [18] "reg readdata[31:0]" +Toggle 0to1 readdata [18] "reg readdata[31:0]" +Toggle 1to0 readdata [17] "reg readdata[31:0]" +Toggle 0to1 readdata [17] "reg readdata[31:0]" +Toggle 1to0 readdata [16] "reg readdata[31:0]" +Toggle 0to1 readdata [16] "reg readdata[31:0]" +Toggle 1to0 readdata [15] "reg readdata[31:0]" +Toggle 0to1 readdata [15] "reg readdata[31:0]" +Toggle 1to0 readdata [14] "reg readdata[31:0]" +Toggle 0to1 readdata [14] "reg readdata[31:0]" +Toggle 1to0 readdata [13] "reg readdata[31:0]" +Toggle 0to1 readdata [13] "reg readdata[31:0]" +Toggle 1to0 readdata [12] "reg readdata[31:0]" +Toggle 0to1 readdata [12] "reg readdata[31:0]" +Toggle 1to0 readdata [11] "reg readdata[31:0]" +Toggle 0to1 readdata [11] "reg readdata[31:0]" +Toggle 1to0 readdata [10] "reg readdata[31:0]" +Toggle 0to1 readdata [10] "reg readdata[31:0]" +Toggle 1to0 readdata [9] "reg readdata[31:0]" +Toggle 0to1 readdata [9] "reg readdata[31:0]" +Toggle 1to0 readdata [8] "reg readdata[31:0]" +Toggle 0to1 readdata [8] "reg readdata[31:0]" +Toggle 1to0 readdata [7] "reg readdata[31:0]" +Toggle 0to1 readdata [7] "reg readdata[31:0]" +Toggle 1to0 readdata [6] "reg readdata[31:0]" +Toggle 0to1 readdata [6] "reg readdata[31:0]" +Toggle 1to0 readdata [5] "reg readdata[31:0]" +Toggle 0to1 readdata [5] "reg readdata[31:0]" +Toggle 1to0 readdata [4] "reg readdata[31:0]" +Toggle 0to1 readdata [4] "reg readdata[31:0]" +Toggle 1to0 readdata [3] "reg readdata[31:0]" +Toggle 0to1 readdata [3] "reg readdata[31:0]" +Toggle 1to0 readdata [2] "reg readdata[31:0]" +Toggle 0to1 readdata [2] "reg readdata[31:0]" +Toggle 1to0 readdata [31] "reg readdata[31:0]" +Toggle 0to1 readdata [31] "reg readdata[31:0]" +CHECKSUM: "213962853 4164642680" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.reset_sync +Toggle 0to1 data_in "net data_in" +Toggle 1to0 data_in "net data_in" +CHECKSUM: "145423899 2338823494" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.pcie_tlp_to_csr_no_dma_inst.axis_rx_mmio_bridge +Branch 4 "1515566115" "RxReadyState" (10) "RxReadyState ST_WAIT_FOR_VALID ,-,-,-,-,-,-,1,0,-,-,-" +Branch 2 "2203450435" "(!rst_n)" (4) "(!rst_n) 0,2'b11 " +Branch 5 "2925719553" "(!rst_n)" (4) "(!rst_n) 0,0,-,-" +Branch 2 "2203450435" "(!rst_n)" (5) "(!rst_n) 0,MISSING_DEFAULT" +Branch 4 "1515566115" "RxReadyState" (15) "RxReadyState ST_WAIT_FOR_RESPONSE ,-,-,-,-,-,-,-,-,-,1,0" +Branch 4 "1515566115" "RxReadyState" (17) "RxReadyState MISSING_DEFAULT,-,-,-,-,-,-,-,-,-,-,-" +Branch 4 "1515566115" "RxReadyState" (1) "RxReadyState ST_RESET ,0,-,-,-,-,-,-,-,-,-,-" +Branch 4 "1515566115" "RxReadyState" (5) "RxReadyState ST_READY ,-,0,0,1,0,-,-,-,-,-,-" +Branch 4 "1515566115" "RxReadyState" (8) "RxReadyState ST_WAIT_FOR_READ ,-,-,-,-,-,0,-,-,-,-,-" +Branch 4 "1515566115" "RxReadyState" (11) "RxReadyState ST_WAIT_FOR_VALID ,-,-,-,-,-,-,0,-,-,-,-" +Branch 4 "1515566115" "RxReadyState" (13) "RxReadyState ST_WAIT_FOR_WRITE ,-,-,-,-,-,-,-,-,0,-,-" +Branch 4 "1515566115" "RxReadyState" (16) "RxReadyState ST_WAIT_FOR_RESPONSE ,-,-,-,-,-,-,-,-,-,0,-" +Branch 4 "1515566115" "RxReadyState" (2) "RxReadyState ST_READY ,-,1,-,-,-,-,-,-,-,-,-" +CHECKSUM: "1637254405 1891435013" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr +Branch 0 "912017437" "(i_cmd_csr_addr[(AFU_CSR_ADDR_WIDTH - 1):3] < CSR_NUM_REG)" (1) "(i_cmd_csr_addr[(AFU_CSR_ADDR_WIDTH - 1):3] < CSR_NUM_REG) 0" +Branch 1 "3817651161" "range_valid" (1) "range_valid 0" +CHECKSUM: "145423899 3222461173" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.pcie_tlp_to_csr_no_dma_inst.axis_rx_mmio_bridge +Condition 2 "1681113788" "(axis_rx_write && axis_rx_if.tready) 1 -1" (2 "10") +Condition 1 "2739845729" "((axis_rx_length > (AVMM_DATA_WIDTH / 'd8)) ? ((AVMM_DATA_WIDTH / 'd8)) : axis_rx_length[13:0]) 1 -1" (2 "1") +CHECKSUM: "1768182563 2167025511" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.pcie_tlp_to_csr_no_dma_inst.axis_tx_mmio_bridge +ANNOTATION: " eccstatus tied in design " +Condition 4 "2005616570" "(ctt_fifo_rdack && ctt_fifo_eccstatus[0]) 1 -1" (3 "11") +Condition 4 "2005616570" "(ctt_fifo_rdack && ctt_fifo_eccstatus[0]) 1 -1" (1 "01") +Condition 1 "3429234141" "(ctt_fifo_error_pipe[2] || rsp_fifo_eccstatus[0]) 1 -1" (2 "01") +Condition 1 "3429234141" "(ctt_fifo_error_pipe[2] || rsp_fifo_eccstatus[0]) 1 -1" (3 "10") +Condition 2 "2923823078" "(axis_tx_if.tready && axis_tx_if.tvalid) 1 -1" (1 "01") +CHECKSUM: "1637254405 1861988852" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr +Condition 1 "4177735008" "((i_cmd_csr_addr[(AFU_CSR_ADDR_WIDTH - 1):3] < CSR_NUM_REG) ? 1'b1 : 1'b0) 1 -1" (1 "0") +Condition 2 "3319243356" "(range_valid ? csr_reg[(i_cmd_csr_addr >> CSR_ADDR_SHIFT)] : 64'b0) 1 -1" (1 "0") +CHECKSUM: "1117319907 1347865916" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.MON.GenCRCCheck.crc32_chk_inst.crc_comparator_u0 +Toggle 1to0 pkt_crc_checksum [22] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [20] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [19] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [18] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [17] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [16] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [14] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [10] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [5] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [0] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [23] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [24] "reg pkt_crc_checksum[31:0]" +Toggle 0to1 pkt_crc_checksum [24] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [21] "reg pkt_crc_checksum[31:0]" +Toggle 0to1 pkt_crc_checksum [21] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [15] "reg pkt_crc_checksum[31:0]" +Toggle 0to1 pkt_crc_checksum [15] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [13] "reg pkt_crc_checksum[31:0]" +Toggle 0to1 pkt_crc_checksum [13] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [12] "reg pkt_crc_checksum[31:0]" +Toggle 0to1 pkt_crc_checksum [12] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [11] "reg pkt_crc_checksum[31:0]" +Toggle 0to1 pkt_crc_checksum [11] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [9] "reg pkt_crc_checksum[31:0]" +Toggle 0to1 pkt_crc_checksum [9] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [8] "reg pkt_crc_checksum[31:0]" +Toggle 0to1 pkt_crc_checksum [8] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [7] "reg pkt_crc_checksum[31:0]" +Toggle 0to1 pkt_crc_checksum [7] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [6] "reg pkt_crc_checksum[31:0]" +Toggle 0to1 pkt_crc_checksum [6] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [4] "reg pkt_crc_checksum[31:0]" +Toggle 0to1 pkt_crc_checksum [4] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [3] "reg pkt_crc_checksum[31:0]" +Toggle 0to1 pkt_crc_checksum [3] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [2] "reg pkt_crc_checksum[31:0]" +Toggle 0to1 pkt_crc_checksum [2] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [1] "reg pkt_crc_checksum[31:0]" +Toggle 0to1 pkt_crc_checksum [1] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [25] "reg pkt_crc_checksum[31:0]" +Toggle 0to1 pkt_crc_checksum [25] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [30] "reg pkt_crc_checksum[31:0]" +Toggle 0to1 pkt_crc_checksum [30] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [29] "reg pkt_crc_checksum[31:0]" +Toggle 0to1 pkt_crc_checksum [29] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [28] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [27] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [26] "reg pkt_crc_checksum[31:0]" +Toggle 1to0 pkt_crc_checksum [31] "reg pkt_crc_checksum[31:0]" +Toggle 0to1 pkt_crc_checksum [31] "reg pkt_crc_checksum[31:0]" +Toggle PKT_CRC_CHECKSUM_IN "net PKT_CRC_CHECKSUM_IN[31:0]" +CHECKSUM: "3863186091 3420071869" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.avalon_st_loopback_u0.tx_sc_fifo +Toggle 1to0 out_channel [0] "net out_channel[0:0]" +Toggle 0to1 out_channel [0] "net out_channel[0:0]" +Toggle max_fifo_size "net max_fifo_size[31:0]" +Toggle mem_used "reg mem_used[2047:0]" +Toggle 1to0 in_ready "net in_ready" +Toggle 0to1 in_ready "net in_ready" +Toggle 1to0 in_channel [0] "net in_channel[0:0]" +Toggle 0to1 in_channel [0] "net in_channel[0:0]" +Toggle gen_blk16.depth32 "net gen_blk16.depth32[31:0]" +Toggle 1to0 fifo_too_small "net fifo_too_small" +Toggle 0to1 fifo_too_small "net fifo_too_small" +Toggle 1to0 fifo_too_small_r "reg fifo_too_small_r" +Toggle 0to1 fifo_too_small_r "reg fifo_too_small_r" +Toggle 1to0 csr_readdata [30] "reg csr_readdata[31:0]" +Toggle 0to1 csr_readdata [30] "reg csr_readdata[31:0]" +Toggle 1to0 csr_readdata [29] "reg csr_readdata[31:0]" +Toggle 0to1 csr_readdata [29] "reg csr_readdata[31:0]" +Toggle 1to0 csr_readdata [28] "reg csr_readdata[31:0]" +Toggle 0to1 csr_readdata [28] "reg csr_readdata[31:0]" +Toggle 1to0 csr_readdata [27] "reg csr_readdata[31:0]" +Toggle 0to1 csr_readdata [27] "reg csr_readdata[31:0]" +Toggle 1to0 csr_readdata [26] "reg csr_readdata[31:0]" +Toggle 0to1 csr_readdata [26] "reg csr_readdata[31:0]" +Toggle 1to0 csr_readdata [25] "reg csr_readdata[31:0]" +Toggle 0to1 csr_readdata [25] "reg csr_readdata[31:0]" +Toggle 1to0 csr_readdata [24] "reg csr_readdata[31:0]" +Toggle 0to1 csr_readdata [24] "reg csr_readdata[31:0]" +Toggle 1to0 csr_readdata [31] "reg csr_readdata[31:0]" +Toggle 0to1 csr_readdata [31] "reg csr_readdata[31:0]" +CHECKSUM: "3520614059 870887363" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr +Fsm avmm_state "1825289578" +Transition AVMM_FSM_ACK->AVMM_FSM_RESET "5->1" +Fsm user_state "2590655792" +Transition USER_FSM_ACK->USER_FSM_RESET "4->1" +Fsm user_state "2590655792" +Transition USER_FSM_WAIT->USER_FSM_RESET "3->1" +CHECKSUM: "1269902960 1004382444" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.GEN +Fsm ps "1004382444" +Transition state_src_len_seq->state_dest_src "2->1" +Fsm ps "1004382444" +Transition state_src_len_seq->state_idle "2->0" +Fsm ps "1004382444" +Transition state_dest_src->state_idle "1->0" +Fsm ps "1004382444" +Transition state_data->state_dest_src "3->1" +Fsm ps "1004382444" +Transition state_data->state_idle "3->0" +CHECKSUM: "145423899 1798057957" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.pcie_tlp_to_csr_no_dma_inst.axis_rx_mmio_bridge +Fsm RxReadyState "1798057957" +Transition ST_WAIT_FOR_READ->ST_RESET "2->0" +Fsm RxReadyState "1798057957" +Transition ST_WAIT_FOR_RESPONSE->ST_RESET "5->0" +Fsm RxReadyState "1798057957" +Transition ST_WAIT_FOR_VALID->ST_RESET "3->0" +Fsm RxReadyState "1798057957" +Transition ST_WAIT_FOR_WRITE->ST_RESET "4->0" +Fsm RxReadyState "1798057957" +Transition ST_READY->ST_WAIT_FOR_READ "1->2" +Fsm RxReadyState "1798057957" +Transition ST_WAIT_FOR_READ->ST_WAIT_FOR_VALID "2->3" +Fsm RxReadyState "1798057957" +Transition ST_WAIT_FOR_VALID->ST_READY "3->1" +CHECKSUM: "620743534 3317163787" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.MON +Fsm monstate "3317163787" +Transition MONACTIVE->MONIDLE "1->0" +Fsm monstate "3317163787" +Transition MONDONE->MONIDLE "2->0" +Fsm monstate "3317163787" +Transition MONACTIVE->MONDONE "1->2" +CHECKSUM: "3895138721 3122168983" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.GEN.GenCRC.crc32_gen_inst.crc32_calculator_u0.crc_bridge_u0 +Fsm state "3122168983" +Transition init->rst "1->0" +CHECKSUM: "3895138721 3122168983" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.MON.GenCRCCheck.crc32_chk_inst.crc32_calculator_u0.crc_bridge_u0 +Fsm state "3122168983" +Transition init->rst "1->0" +CHECKSUM: "145423899 1160477253" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.pcie_tlp_to_csr_no_dma_inst.axis_rx_mmio_bridge +Toggle tlp_rd_req_id "logic tlp_rd_req_id[15:0]" +Toggle 1to0 avmm_m2s_address [10] "logic avmm_m2s_address[11:0]" +Toggle 0to1 avmm_m2s_address [10] "logic avmm_m2s_address[11:0]" +Toggle 1to0 avmm_m2s_address [9] "logic avmm_m2s_address[11:0]" +Toggle 0to1 avmm_m2s_address [9] "logic avmm_m2s_address[11:0]" +Toggle 1to0 avmm_m2s_address [8] "logic avmm_m2s_address[11:0]" +Toggle 0to1 avmm_m2s_address [8] "logic avmm_m2s_address[11:0]" +Toggle 1to0 avmm_m2s_address [7] "logic avmm_m2s_address[11:0]" +Toggle 0to1 avmm_m2s_address [7] "logic avmm_m2s_address[11:0]" +Toggle 1to0 avmm_m2s_address [1] "logic avmm_m2s_address[11:0]" +Toggle 0to1 avmm_m2s_address [1] "logic avmm_m2s_address[11:0]" +Toggle 1to0 avmm_m2s_address [0] "logic avmm_m2s_address[11:0]" +Toggle 0to1 avmm_m2s_address [0] "logic avmm_m2s_address[11:0]" +Toggle 1to0 avmm_m2s_address [11] "logic avmm_m2s_address[11:0]" +Toggle 0to1 avmm_m2s_address [11] "logic avmm_m2s_address[11:0]" +Toggle 1to0 avmm_s2m_waitrequest "logic avmm_s2m_waitrequest" +Toggle 0to1 avmm_s2m_waitrequest "logic avmm_s2m_waitrequest" +CHECKSUM: "3559185232 344196957" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.avalon_st_loopback_u0.avalon_st_loopback_ena_csr_inst +Branch 2 "2818403456" "reset" (3) "reset 0,1,default" +CHECKSUM: "1768182563 3337303171" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.pcie_tlp_to_csr_no_dma_inst.axis_tx_mmio_bridge +Toggle 0to1 ctt_fifo_din.low_addr [4] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 0to1 ctt_fifo_din.low_addr [5] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 1to0 ctt_fifo_din.low_addr [4] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 1to0 ctt_fifo_din.low_addr [5] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 1to0 cpl_hdr.byte_count [10] "logic cpl_hdr.byte_count[11:0]" +Toggle 0to1 cpl_hdr.byte_count [10] "logic cpl_hdr.byte_count[11:0]" +Toggle 1to0 cpl_hdr.byte_count [9] "logic cpl_hdr.byte_count[11:0]" +Toggle 0to1 cpl_hdr.byte_count [9] "logic cpl_hdr.byte_count[11:0]" +Toggle 1to0 cpl_hdr.byte_count [8] "logic cpl_hdr.byte_count[11:0]" +Toggle 0to1 cpl_hdr.byte_count [8] "logic cpl_hdr.byte_count[11:0]" +Toggle 1to0 cpl_hdr.byte_count [7] "logic cpl_hdr.byte_count[11:0]" +Toggle 0to1 cpl_hdr.byte_count [7] "logic cpl_hdr.byte_count[11:0]" +Toggle 1to0 cpl_hdr.byte_count [6] "logic cpl_hdr.byte_count[11:0]" +Toggle 0to1 cpl_hdr.byte_count [6] "logic cpl_hdr.byte_count[11:0]" +Toggle 1to0 cpl_hdr.byte_count [5] "logic cpl_hdr.byte_count[11:0]" +Toggle 0to1 cpl_hdr.byte_count [5] "logic cpl_hdr.byte_count[11:0]" +Toggle 1to0 cpl_hdr.byte_count [4] "logic cpl_hdr.byte_count[11:0]" +Toggle 0to1 cpl_hdr.byte_count [4] "logic cpl_hdr.byte_count[11:0]" +Toggle 1to0 cpl_hdr.byte_count [1] "logic cpl_hdr.byte_count[11:0]" +Toggle 0to1 cpl_hdr.byte_count [1] "logic cpl_hdr.byte_count[11:0]" +Toggle 1to0 cpl_hdr.byte_count [0] "logic cpl_hdr.byte_count[11:0]" +Toggle 0to1 cpl_hdr.byte_count [0] "logic cpl_hdr.byte_count[11:0]" +Toggle 1to0 cpl_hdr.byte_count [11] "logic cpl_hdr.byte_count[11:0]" +Toggle 0to1 cpl_hdr.byte_count [11] "logic cpl_hdr.byte_count[11:0]" +Toggle 1to0 cpl_hdr.length [8] "logic cpl_hdr.length[9:0]" +Toggle 0to1 cpl_hdr.length [8] "logic cpl_hdr.length[9:0]" +Toggle 1to0 cpl_hdr.length [7] "logic cpl_hdr.length[9:0]" +Toggle 0to1 cpl_hdr.length [7] "logic cpl_hdr.length[9:0]" +Toggle 1to0 cpl_hdr.length [6] "logic cpl_hdr.length[9:0]" +Toggle 0to1 cpl_hdr.length [6] "logic cpl_hdr.length[9:0]" +Toggle 1to0 cpl_hdr.length [5] "logic cpl_hdr.length[9:0]" +Toggle 0to1 cpl_hdr.length [5] "logic cpl_hdr.length[9:0]" +Toggle 1to0 cpl_hdr.length [4] "logic cpl_hdr.length[9:0]" +Toggle 0to1 cpl_hdr.length [4] "logic cpl_hdr.length[9:0]" +Toggle 1to0 cpl_hdr.length [3] "logic cpl_hdr.length[9:0]" +Toggle 0to1 cpl_hdr.length [3] "logic cpl_hdr.length[9:0]" +Toggle 1to0 cpl_hdr.length [2] "logic cpl_hdr.length[9:0]" +Toggle 0to1 cpl_hdr.length [2] "logic cpl_hdr.length[9:0]" +Toggle 1to0 cpl_hdr.length [9] "logic cpl_hdr.length[9:0]" +Toggle 0to1 cpl_hdr.length [9] "logic cpl_hdr.length[9:0]" +Toggle tlp_rd_req_id "logic tlp_rd_req_id[15:0]" +Toggle ctt_fifo_error_pipe "logic ctt_fifo_error_pipe[2:0]" +Toggle ctt_fifo_eccstatus "logic ctt_fifo_eccstatus[1:0]" +Toggle ctt_fifo_din.req_id "logic ctt_fifo_din.req_id[15:0]" +Toggle rsp_fifo_eccstatus "logic rsp_fifo_eccstatus[1:0]" +Toggle 1to0 cpl_hdr.mm_mode "logic cpl_hdr.mm_mode" +Toggle 0to1 cpl_hdr.mm_mode "logic cpl_hdr.mm_mode" +Toggle cpl_hdr.pref "logic cpl_hdr.pref[23:0]" +Toggle 1to0 cpl_hdr.pref_present "logic cpl_hdr.pref_present" +Toggle 0to1 cpl_hdr.pref_present "logic cpl_hdr.pref_present" +Toggle cpl_hdr.pref_type "logic cpl_hdr.pref_type[4:0]" +Toggle cpl_hdr.rsvd1 "logic cpl_hdr.rsvd1[6:0]" +Toggle cpl_hdr.rsvd2 "logic cpl_hdr.rsvd2[3:0]" +Toggle cpl_hdr.rsvd3 "logic cpl_hdr.rsvd3[1:0]" +Toggle cpl_hdr.rsvd4 "logic cpl_hdr.rsvd4[31:0]" +Toggle 1to0 cpl_hdr.rsvd5 "logic cpl_hdr.rsvd5" +Toggle 0to1 cpl_hdr.rsvd5 "logic cpl_hdr.rsvd5" +Toggle cpl_hdr.slot_num "logic cpl_hdr.slot_num[4:0]" +Toggle 1to0 cpl_hdr.vf_active "logic cpl_hdr.vf_active" +Toggle 0to1 cpl_hdr.vf_active "logic cpl_hdr.vf_active" +Toggle cpl_hdr.vf_num "logic cpl_hdr.vf_num[10:0]" +Toggle cpl_hdr.pf_num "logic cpl_hdr.pf_num[2:0]" +Toggle cpl_hdr.metadata_l "logic cpl_hdr.metadata_l[31:0]" +Toggle cpl_hdr.metadata_h "logic cpl_hdr.metadata_h[31:0]" +Toggle cpl_hdr.cpl_status "logic cpl_hdr.cpl_status[2:0]" +Toggle cpl_hdr.fmt_type "logic cpl_hdr.fmt_type[7:0]" +Toggle cpl_hdr.comp_id "logic cpl_hdr.comp_id[15:0]" +Toggle 1to0 cpl_hdr.bcm "logic cpl_hdr.bcm" +Toggle 0to1 cpl_hdr.bcm "logic cpl_hdr.bcm" +Toggle cpl_hdr.attr.AT "logic cpl_hdr.attr.AT[1:0]" +Toggle 1to0 cpl_hdr.attr.EP "logic cpl_hdr.attr.EP" +Toggle 0to1 cpl_hdr.attr.EP "logic cpl_hdr.attr.EP" +Toggle 1to0 cpl_hdr.attr.LN "logic cpl_hdr.attr.LN" +Toggle 0to1 cpl_hdr.attr.LN "logic cpl_hdr.attr.LN" +Toggle 1to0 cpl_hdr.attr.TD "logic cpl_hdr.attr.TD" +Toggle 0to1 cpl_hdr.attr.TD "logic cpl_hdr.attr.TD" +Toggle 1to0 cpl_hdr.attr.TH "logic cpl_hdr.attr.TH" +Toggle 0to1 cpl_hdr.attr.TH "logic cpl_hdr.attr.TH" +Toggle 1to0 cpl_hdr.attr.rsvd1 "logic cpl_hdr.attr.rsvd1" +Toggle 0to1 cpl_hdr.attr.rsvd1 "logic cpl_hdr.attr.rsvd1" +Toggle cpl_hdr.attr.rsvd2 "logic cpl_hdr.attr.rsvd2[1:0]" +Toggle cpl_hdr.TC "logic cpl_hdr.TC[2:0]" +Toggle 1to0 axis_tx_error "logic axis_tx_error" +Toggle 0to1 axis_tx_error "logic axis_tx_error" +Toggle 0to1 cpl_hdr.req_id [15] "logic cpl_hdr.req_id[15:0]" +Toggle 1to0 cpl_hdr.req_id [15] "logic cpl_hdr.req_id[15:0]" +Toggle 0to1 cpl_hdr.req_id [1] "logic cpl_hdr.req_id[15:0]" +Toggle 1to0 cpl_hdr.req_id [1] "logic cpl_hdr.req_id[15:0]" +Toggle 0to1 cpl_hdr.req_id [2] "logic cpl_hdr.req_id[15:0]" +Toggle 1to0 cpl_hdr.req_id [2] "logic cpl_hdr.req_id[15:0]" +Toggle 0to1 cpl_hdr.req_id [3] "logic cpl_hdr.req_id[15:0]" +Toggle 1to0 cpl_hdr.req_id [3] "logic cpl_hdr.req_id[15:0]" +Toggle 0to1 cpl_hdr.req_id [4] "logic cpl_hdr.req_id[15:0]" +Toggle 1to0 cpl_hdr.req_id [4] "logic cpl_hdr.req_id[15:0]" +Toggle 0to1 cpl_hdr.req_id [5] "logic cpl_hdr.req_id[15:0]" +Toggle 1to0 cpl_hdr.req_id [5] "logic cpl_hdr.req_id[15:0]" +Toggle 0to1 cpl_hdr.req_id [6] "logic cpl_hdr.req_id[15:0]" +Toggle 1to0 cpl_hdr.req_id [6] "logic cpl_hdr.req_id[15:0]" +Toggle 0to1 cpl_hdr.req_id [7] "logic cpl_hdr.req_id[15:0]" +Toggle 1to0 cpl_hdr.req_id [7] "logic cpl_hdr.req_id[15:0]" +Toggle 0to1 cpl_hdr.req_id [8] "logic cpl_hdr.req_id[15:0]" +Toggle 1to0 cpl_hdr.req_id [8] "logic cpl_hdr.req_id[15:0]" +Toggle 0to1 cpl_hdr.req_id [9] "logic cpl_hdr.req_id[15:0]" +Toggle 1to0 cpl_hdr.req_id [9] "logic cpl_hdr.req_id[15:0]" +Toggle 0to1 cpl_hdr.req_id [10] "logic cpl_hdr.req_id[15:0]" +Toggle 1to0 cpl_hdr.req_id [10] "logic cpl_hdr.req_id[15:0]" +Toggle 0to1 cpl_hdr.req_id [11] "logic cpl_hdr.req_id[15:0]" +Toggle 1to0 cpl_hdr.req_id [11] "logic cpl_hdr.req_id[15:0]" +Toggle 0to1 cpl_hdr.req_id [12] "logic cpl_hdr.req_id[15:0]" +Toggle 1to0 cpl_hdr.req_id [12] "logic cpl_hdr.req_id[15:0]" +Toggle 0to1 cpl_hdr.req_id [13] "logic cpl_hdr.req_id[15:0]" +Toggle 1to0 cpl_hdr.req_id [13] "logic cpl_hdr.req_id[15:0]" +Toggle 0to1 cpl_hdr.req_id [14] "logic cpl_hdr.req_id[15:0]" +Toggle 1to0 cpl_hdr.req_id [14] "logic cpl_hdr.req_id[15:0]" +Toggle 1to0 cpl_hdr.req_id [0] "logic cpl_hdr.req_id[15:0]" +Toggle 0to1 cpl_hdr.tag_h "logic cpl_hdr.tag_h" +Toggle 1to0 cpl_hdr.tag_h "logic cpl_hdr.tag_h" +Toggle 0to1 cpl_hdr.tag_m "logic cpl_hdr.tag_m" +Toggle 1to0 cpl_hdr.tag_m "logic cpl_hdr.tag_m" +Toggle 0to1 ctt_fifo_din.length [13] "logic ctt_fifo_din.length[13:0]" +Toggle 1to0 ctt_fifo_din.length [13] "logic ctt_fifo_din.length[13:0]" +Toggle 0to1 ctt_fifo_din.length [0] "logic ctt_fifo_din.length[13:0]" +Toggle 1to0 ctt_fifo_din.length [0] "logic ctt_fifo_din.length[13:0]" +Toggle 0to1 ctt_fifo_din.length [1] "logic ctt_fifo_din.length[13:0]" +Toggle 1to0 ctt_fifo_din.length [1] "logic ctt_fifo_din.length[13:0]" +Toggle 0to1 ctt_fifo_din.length [4] "logic ctt_fifo_din.length[13:0]" +Toggle 1to0 ctt_fifo_din.length [4] "logic ctt_fifo_din.length[13:0]" +Toggle 0to1 ctt_fifo_din.length [5] "logic ctt_fifo_din.length[13:0]" +Toggle 1to0 ctt_fifo_din.length [5] "logic ctt_fifo_din.length[13:0]" +Toggle 0to1 ctt_fifo_din.length [6] "logic ctt_fifo_din.length[13:0]" +Toggle 1to0 ctt_fifo_din.length [6] "logic ctt_fifo_din.length[13:0]" +Toggle 0to1 ctt_fifo_din.length [7] "logic ctt_fifo_din.length[13:0]" +Toggle 1to0 ctt_fifo_din.length [7] "logic ctt_fifo_din.length[13:0]" +Toggle 0to1 ctt_fifo_din.length [8] "logic ctt_fifo_din.length[13:0]" +Toggle 1to0 ctt_fifo_din.length [8] "logic ctt_fifo_din.length[13:0]" +Toggle 0to1 ctt_fifo_din.length [9] "logic ctt_fifo_din.length[13:0]" +Toggle 1to0 ctt_fifo_din.length [9] "logic ctt_fifo_din.length[13:0]" +Toggle 0to1 ctt_fifo_din.length [10] "logic ctt_fifo_din.length[13:0]" +Toggle 1to0 ctt_fifo_din.length [10] "logic ctt_fifo_din.length[13:0]" +Toggle 0to1 ctt_fifo_din.length [11] "logic ctt_fifo_din.length[13:0]" +Toggle 1to0 ctt_fifo_din.length [11] "logic ctt_fifo_din.length[13:0]" +Toggle 0to1 ctt_fifo_din.length [12] "logic ctt_fifo_din.length[13:0]" +Toggle 1to0 ctt_fifo_din.length [12] "logic ctt_fifo_din.length[13:0]" +Toggle 0to1 ctt_fifo_din.low_addr [23] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 1to0 ctt_fifo_din.low_addr [23] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 0to1 ctt_fifo_din.low_addr [0] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 1to0 ctt_fifo_din.low_addr [0] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 0to1 ctt_fifo_din.low_addr [1] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 1to0 ctt_fifo_din.low_addr [1] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 0to1 ctt_fifo_din.low_addr [7] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 1to0 ctt_fifo_din.low_addr [7] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 0to1 ctt_fifo_din.low_addr [8] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 1to0 ctt_fifo_din.low_addr [8] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 0to1 ctt_fifo_din.low_addr [9] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 1to0 ctt_fifo_din.low_addr [9] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 0to1 ctt_fifo_din.low_addr [10] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 1to0 ctt_fifo_din.low_addr [10] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 0to1 ctt_fifo_din.low_addr [11] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 1to0 ctt_fifo_din.low_addr [11] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 0to1 ctt_fifo_din.low_addr [12] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 1to0 ctt_fifo_din.low_addr [12] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 0to1 ctt_fifo_din.low_addr [13] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 1to0 ctt_fifo_din.low_addr [13] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 0to1 ctt_fifo_din.low_addr [14] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 1to0 ctt_fifo_din.low_addr [14] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 0to1 ctt_fifo_din.low_addr [15] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 1to0 ctt_fifo_din.low_addr [15] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 0to1 ctt_fifo_din.low_addr [16] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 1to0 ctt_fifo_din.low_addr [16] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 0to1 ctt_fifo_din.low_addr [17] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 1to0 ctt_fifo_din.low_addr [17] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 0to1 ctt_fifo_din.low_addr [18] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 1to0 ctt_fifo_din.low_addr [18] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 0to1 ctt_fifo_din.low_addr [19] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 1to0 ctt_fifo_din.low_addr [19] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 0to1 ctt_fifo_din.low_addr [20] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 1to0 ctt_fifo_din.low_addr [20] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 0to1 ctt_fifo_din.low_addr [21] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 1to0 ctt_fifo_din.low_addr [21] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 0to1 ctt_fifo_din.low_addr [22] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 1to0 ctt_fifo_din.low_addr [22] "logic ctt_fifo_din.low_addr[23:0]" +Toggle 0to1 ctt_fifo_dout.length [13] "logic ctt_fifo_dout.length[13:0]" +Toggle 1to0 ctt_fifo_dout.length [13] "logic ctt_fifo_dout.length[13:0]" +Toggle 0to1 ctt_fifo_dout.length [0] "logic ctt_fifo_dout.length[13:0]" +Toggle 1to0 ctt_fifo_dout.length [0] "logic ctt_fifo_dout.length[13:0]" +Toggle 0to1 ctt_fifo_dout.length [1] "logic ctt_fifo_dout.length[13:0]" +Toggle 1to0 ctt_fifo_dout.length [1] "logic ctt_fifo_dout.length[13:0]" +Toggle 0to1 ctt_fifo_dout.length [4] "logic ctt_fifo_dout.length[13:0]" +Toggle 1to0 ctt_fifo_dout.length [4] "logic ctt_fifo_dout.length[13:0]" +Toggle 0to1 ctt_fifo_dout.length [5] "logic ctt_fifo_dout.length[13:0]" +Toggle 1to0 ctt_fifo_dout.length [5] "logic ctt_fifo_dout.length[13:0]" +Toggle 0to1 ctt_fifo_dout.length [6] "logic ctt_fifo_dout.length[13:0]" +Toggle 1to0 ctt_fifo_dout.length [6] "logic ctt_fifo_dout.length[13:0]" +Toggle 0to1 ctt_fifo_dout.length [7] "logic ctt_fifo_dout.length[13:0]" +Toggle 1to0 ctt_fifo_dout.length [7] "logic ctt_fifo_dout.length[13:0]" +Toggle 0to1 ctt_fifo_dout.length [8] "logic ctt_fifo_dout.length[13:0]" +Toggle 1to0 ctt_fifo_dout.length [8] "logic ctt_fifo_dout.length[13:0]" +Toggle 0to1 ctt_fifo_dout.length [9] "logic ctt_fifo_dout.length[13:0]" +Toggle 1to0 ctt_fifo_dout.length [9] "logic ctt_fifo_dout.length[13:0]" +Toggle 0to1 ctt_fifo_dout.length [10] "logic ctt_fifo_dout.length[13:0]" +Toggle 1to0 ctt_fifo_dout.length [10] "logic ctt_fifo_dout.length[13:0]" +Toggle 0to1 ctt_fifo_dout.length [11] "logic ctt_fifo_dout.length[13:0]" +Toggle 1to0 ctt_fifo_dout.length [11] "logic ctt_fifo_dout.length[13:0]" +Toggle 0to1 ctt_fifo_dout.length [12] "logic ctt_fifo_dout.length[13:0]" +Toggle 1to0 ctt_fifo_dout.length [12] "logic ctt_fifo_dout.length[13:0]" +Toggle 0to1 ctt_fifo_dout.low_addr [23] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 1to0 ctt_fifo_dout.low_addr [23] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 0to1 ctt_fifo_dout.low_addr [0] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 1to0 ctt_fifo_dout.low_addr [0] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 0to1 ctt_fifo_dout.low_addr [1] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 1to0 ctt_fifo_dout.low_addr [1] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 0to1 ctt_fifo_dout.low_addr [7] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 1to0 ctt_fifo_dout.low_addr [7] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 0to1 ctt_fifo_dout.low_addr [8] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 1to0 ctt_fifo_dout.low_addr [8] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 0to1 ctt_fifo_dout.low_addr [9] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 1to0 ctt_fifo_dout.low_addr [9] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 0to1 ctt_fifo_dout.low_addr [10] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 1to0 ctt_fifo_dout.low_addr [10] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 0to1 ctt_fifo_dout.low_addr [11] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 1to0 ctt_fifo_dout.low_addr [11] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 0to1 ctt_fifo_dout.low_addr [12] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 1to0 ctt_fifo_dout.low_addr [12] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 0to1 ctt_fifo_dout.low_addr [13] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 1to0 ctt_fifo_dout.low_addr [13] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 0to1 ctt_fifo_dout.low_addr [14] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 1to0 ctt_fifo_dout.low_addr [14] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 0to1 ctt_fifo_dout.low_addr [15] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 1to0 ctt_fifo_dout.low_addr [15] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 0to1 ctt_fifo_dout.low_addr [16] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 1to0 ctt_fifo_dout.low_addr [16] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 0to1 ctt_fifo_dout.low_addr [17] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 1to0 ctt_fifo_dout.low_addr [17] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 0to1 ctt_fifo_dout.low_addr [18] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 1to0 ctt_fifo_dout.low_addr [18] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 0to1 ctt_fifo_dout.low_addr [19] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 1to0 ctt_fifo_dout.low_addr [19] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 0to1 ctt_fifo_dout.low_addr [20] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 1to0 ctt_fifo_dout.low_addr [20] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 0to1 ctt_fifo_dout.low_addr [21] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 1to0 ctt_fifo_dout.low_addr [21] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 0to1 ctt_fifo_dout.low_addr [22] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 1to0 ctt_fifo_dout.low_addr [22] "logic ctt_fifo_dout.low_addr[23:0]" +Toggle 0to1 ctt_fifo_dout.req_id [15] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 1to0 ctt_fifo_dout.req_id [15] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 0to1 ctt_fifo_dout.req_id [1] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 1to0 ctt_fifo_dout.req_id [1] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 0to1 ctt_fifo_dout.req_id [2] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 1to0 ctt_fifo_dout.req_id [2] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 0to1 ctt_fifo_dout.req_id [3] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 1to0 ctt_fifo_dout.req_id [3] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 0to1 ctt_fifo_dout.req_id [4] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 1to0 ctt_fifo_dout.req_id [4] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 0to1 ctt_fifo_dout.req_id [5] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 1to0 ctt_fifo_dout.req_id [5] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 0to1 ctt_fifo_dout.req_id [6] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 1to0 ctt_fifo_dout.req_id [6] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 0to1 ctt_fifo_dout.req_id [7] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 1to0 ctt_fifo_dout.req_id [7] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 0to1 ctt_fifo_dout.req_id [8] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 1to0 ctt_fifo_dout.req_id [8] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 0to1 ctt_fifo_dout.req_id [9] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 1to0 ctt_fifo_dout.req_id [9] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 0to1 ctt_fifo_dout.req_id [10] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 1to0 ctt_fifo_dout.req_id [10] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 0to1 ctt_fifo_dout.req_id [11] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 1to0 ctt_fifo_dout.req_id [11] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 0to1 ctt_fifo_dout.req_id [12] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 1to0 ctt_fifo_dout.req_id [12] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 0to1 ctt_fifo_dout.req_id [13] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 1to0 ctt_fifo_dout.req_id [13] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 0to1 ctt_fifo_dout.req_id [14] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 1to0 ctt_fifo_dout.req_id [14] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 1to0 ctt_fifo_dout.req_id [0] "logic ctt_fifo_dout.req_id[15:0]" +Toggle 0to1 ctt_fifo_dout.tag [9] "logic ctt_fifo_dout.tag[9:0]" +Toggle 1to0 ctt_fifo_dout.tag [9] "logic ctt_fifo_dout.tag[9:0]" +Toggle 0to1 ctt_fifo_dout.tag [5] "logic ctt_fifo_dout.tag[9:0]" +Toggle 1to0 ctt_fifo_dout.tag [5] "logic ctt_fifo_dout.tag[9:0]" +Toggle 0to1 ctt_fifo_dout.tag [6] "logic ctt_fifo_dout.tag[9:0]" +Toggle 1to0 ctt_fifo_dout.tag [6] "logic ctt_fifo_dout.tag[9:0]" +Toggle 0to1 ctt_fifo_dout.tag [7] "logic ctt_fifo_dout.tag[9:0]" +Toggle 1to0 ctt_fifo_dout.tag [7] "logic ctt_fifo_dout.tag[9:0]" +Toggle 0to1 ctt_fifo_dout.tag [8] "logic ctt_fifo_dout.tag[9:0]" +Toggle 1to0 ctt_fifo_dout.tag [8] "logic ctt_fifo_dout.tag[9:0]" +Toggle rsp_fifo_din "logic rsp_fifo_din[511:0]" +Toggle rsp_fifo_dout "logic rsp_fifo_dout[511:0]" +Toggle 0to1 tlp_rd_length [13] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [13] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [0] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [0] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [1] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [1] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [4] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [4] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [5] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [5] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [6] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [6] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [7] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [7] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [8] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [8] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [9] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [9] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [10] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [10] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [11] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [11] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [12] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [12] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_low_addr [23] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [23] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [0] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [0] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [1] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [1] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [7] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [7] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [8] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [8] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [9] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [9] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [10] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [10] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [11] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [11] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [12] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [12] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [13] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [13] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [14] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [14] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [15] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [15] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [16] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [16] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [17] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [17] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [18] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [18] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [19] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [19] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [20] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [20] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [21] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [21] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [22] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [22] "logic tlp_rd_low_addr[23:0]" +CHECKSUM: "3773840602 288191784" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.GEN.GenCRC.crc32_gen_inst.crc32_calculator_u0.crc32_u0.rg +Toggle 0to1 sclr "net sclr" +Toggle 1to0 sclr "net sclr" +CHECKSUM: "1700546831 2306020150" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.afu_eth_tx_st[0] +Toggle 0to1 enable_assertion "logic enable_assertion" +Toggle 1to0 enable_assertion "logic enable_assertion" +CHECKSUM: "2725671737 2081015623" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata +Toggle 0to1 reset "logic reset" +Toggle 1to0 reset "logic reset" +CHECKSUM: "2725671737 2081015623" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata +Toggle 0to1 reset "logic reset" +Toggle 1to0 reset "logic reset" +CHECKSUM: "2725671737 528591274" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_rdwr_usrack +Toggle 0to1 reset "logic reset" +Toggle 1to0 reset "logic reset" +CHECKSUM: "2725671737 1763230933" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.read_sync.sr +Toggle 0to1 reset "logic reset" +Toggle 1to0 reset "logic reset" +CHECKSUM: "2725671737 1763230933" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.write_sync.sr +Toggle 0to1 reset "logic reset" +Toggle 1to0 reset "logic reset" +CHECKSUM: "2725671737 1763230933" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.GenRstSync[0].tx_reset_synchronizer +Toggle 0to1 d [0] "logic d[0:0]" +Toggle 1to0 d [0] "logic d[0:0]" +Toggle 0to1 resync_chains[0].sync_d_in "net resync_chains[0].sync_d_in" +Toggle 1to0 resync_chains[0].sync_d_in "net resync_chains[0].sync_d_in" +Toggle 0to1 resync_chains[0].d_in "net resync_chains[0].d_in" +Toggle 1to0 resync_chains[0].d_in "net resync_chains[0].d_in" +CHECKSUM: "2725671737 1763230933" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.GenRstSync[0].rx_reset_synchronizer +Toggle 1to0 resync_chains[0].d_in "net resync_chains[0].d_in" +Toggle 0to1 resync_chains[0].d_in "net resync_chains[0].d_in" +Toggle 1to0 d [0] "logic d[0:0]" +Toggle 0to1 d [0] "logic d[0:0]" +Toggle 1to0 resync_chains[0].sync_d_in "net resync_chains[0].sync_d_in" +Toggle 0to1 resync_chains[0].sync_d_in "net resync_chains[0].sync_d_in" +CHECKSUM: "2725671737 2222722032" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_rst_finish +Toggle 0to1 reset "logic reset" +Toggle 1to0 reset "logic reset" +CHECKSUM: "2725671737 490696940" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr +Toggle 0to1 reset "logic reset" +Toggle 1to0 reset "logic reset" +CHECKSUM: "3520614059 2717948486" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr +Toggle 0to1 i_avmm_readdata_valid "logic i_avmm_readdata_valid" +Toggle 1to0 i_avmm_readdata_valid "logic i_avmm_readdata_valid" +CHECKSUM: "2116389927 1287531766" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.GEN.GenCRC.crc32_gen_inst.crc32_calculator_u0.byte_endian_converter_u0 +Condition 1 "2388167038" "(ENABLE ? ({DATA_IN[7:0], DATA_IN[15:8], DATA_IN[23:16], DATA_IN[31:24], DATA_IN[39:32], DATA_IN[47:40], DATA_IN[55:48], DATA_IN[63:56]}) : DATA_IN) 1 -1" (1 "0") +CHECKSUM: "2116389927 1287531766" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.MON.GenCRCCheck.crc32_chk_inst.crc32_calculator_u0.byte_endian_converter_u0 +Condition 1 "2388167038" "(ENABLE ? ({DATA_IN[7:0], DATA_IN[15:8], DATA_IN[23:16], DATA_IN[31:24], DATA_IN[39:32], DATA_IN[47:40], DATA_IN[55:48], DATA_IN[63:56]}) : DATA_IN) 1 -1" (1 "0") +CHECKSUM: "2116389927 2973822728" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.GEN.GenCRC.crc32_gen_inst.crc32_calculator_u0.byte_endian_converter_u1 +Condition 1 "3808204714" "(ENABLE ? ({DATA_IN[7:0], DATA_IN[15:8], DATA_IN[23:16], DATA_IN[31:24]}) : DATA_IN) 1 -1" (1 "0") +CHECKSUM: "2116389927 2973822728" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.MON.GenCRCCheck.crc32_chk_inst.crc32_calculator_u0.byte_endian_converter_u1 +Condition 1 "3808204714" "(ENABLE ? ({DATA_IN[7:0], DATA_IN[15:8], DATA_IN[23:16], DATA_IN[31:24]}) : DATA_IN) 1 -1" (1 "0") +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[13].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[14].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[15].genblk1.synchronizer +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[16].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[17].genblk1.synchronizer +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[18].genblk1.synchronizer +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[19].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[20].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[21].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[22].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[23].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[24].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[25].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[26].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[27].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[28].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[29].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[30].genblk1.synchronizer +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[31].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_rst_finish.resync_chains[0].genblk1.synchronizer +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_rst_finish.resync_chains[1].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[0].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[1].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[2].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[3].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[4].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[5].genblk1.synchronizer +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[6].genblk1.synchronizer +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[7].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[8].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[9].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[10].genblk1.synchronizer +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[11].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[12].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[13].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[14].genblk1.synchronizer +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[15].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[16].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[17].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[18].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[19].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[20].genblk1.synchronizer +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[21].genblk1.synchronizer +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[22].genblk1.synchronizer +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[23].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[24].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[25].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[26].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[27].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[28].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[29].genblk1.synchronizer +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[30].genblk1.synchronizer +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[31].genblk1.synchronizer +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[0].genblk1.synchronizer +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[1].genblk1.synchronizer +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[2].genblk1.synchronizer +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[3].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[4].genblk1.synchronizer +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[5].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[6].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[7].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[8].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[9].genblk1.synchronizer +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[10].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[11].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[12].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[13].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[14].genblk1.synchronizer +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[15].genblk1.synchronizer +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_rdwr_usrack.resync_chains[0].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_rdwr_usrack.resync_chains[1].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_rdwr_usrack.resync_chains[2].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[0].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[1].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[2].genblk1.synchronizer +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[3].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[4].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[5].genblk1.synchronizer +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[6].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[7].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[8].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[9].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[10].genblk1.synchronizer +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[11].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[12].genblk1.synchronizer +Branch 5 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 2 "2661514523" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 3 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 4 "3323665428" "(reset_n == 1'b0)" (0) "(reset_n == 1'b0) 1" +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "809561450 3570990682" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.GenRstSync[0].rx_reset_synchronizer.resync_chains[0].genblk1.synchronizer +Branch 1 "1431651965" "(depth < 2)" (0) "(depth < 2) 1" +CHECKSUM: "3895138721 4197512930" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.GEN.GenCRC.crc32_gen_inst.crc32_calculator_u0.crc_bridge_u0 +Branch 2 "2381639420" "state" (3) "state default" +CHECKSUM: "3895138721 4197512930" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.MON.GenCRCCheck.crc32_chk_inst.crc32_calculator_u0.crc_bridge_u0 +Branch 2 "2381639420" "state" (3) "state default" +CHECKSUM: "2116389927 1504626651" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.GEN.GenCRC.crc32_gen_inst.crc32_calculator_u0.byte_endian_converter_u0 +Branch 0 "2947310992" "ENABLE" (1) "ENABLE 0" +CHECKSUM: "2116389927 1504626651" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.GEN.GenCRC.crc32_gen_inst.crc32_calculator_u0.byte_endian_converter_u1 +Branch 0 "2947310992" "ENABLE" (1) "ENABLE 0" +CHECKSUM: "2116389927 1504626651" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.MON.GenCRCCheck.crc32_chk_inst.crc32_calculator_u0.byte_endian_converter_u0 +Branch 0 "2947310992" "ENABLE" (1) "ENABLE 0" +CHECKSUM: "2116389927 1504626651" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.MON.GenCRCCheck.crc32_chk_inst.crc32_calculator_u0.byte_endian_converter_u1 +Branch 0 "2947310992" "ENABLE" (1) "ENABLE 0" +CHECKSUM: "3773840602 1330866351" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.GEN.GenCRC.crc32_gen_inst.crc32_calculator_u0.crc32_u0.rg +Branch 0 "687008787" "aclr" (1) "aclr 0,1,1,-" +CHECKSUM: "1637254405 3168784749" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr +Toggle 1to0 hw_state.pwr_good_n "logic hw_state.pwr_good_n" +Toggle 0to1 hw_state.pwr_good_n "logic hw_state.pwr_good_n" +Toggle 1to0 o_port_swap_en "logic o_port_swap_en" +Toggle 0to1 o_port_swap_en "logic o_port_swap_en" +Toggle 1to0 s_traffic_ctrl_addr [14] "logic s_traffic_ctrl_addr[15:0]" +Toggle 0to1 s_traffic_ctrl_addr [14] "logic s_traffic_ctrl_addr[15:0]" +Toggle 1to0 s_traffic_ctrl_addr [7] "logic s_traffic_ctrl_addr[15:0]" +Toggle 0to1 s_traffic_ctrl_addr [7] "logic s_traffic_ctrl_addr[15:0]" +Toggle 1to0 s_traffic_ctrl_addr [6] "logic s_traffic_ctrl_addr[15:0]" +Toggle 0to1 s_traffic_ctrl_addr [6] "logic s_traffic_ctrl_addr[15:0]" +Toggle 1to0 s_traffic_ctrl_addr [5] "logic s_traffic_ctrl_addr[15:0]" +Toggle 0to1 s_traffic_ctrl_addr [5] "logic s_traffic_ctrl_addr[15:0]" +Toggle 1to0 s_traffic_ctrl_addr [4] "logic s_traffic_ctrl_addr[15:0]" +Toggle 0to1 s_traffic_ctrl_addr [4] "logic s_traffic_ctrl_addr[15:0]" +Toggle 1to0 s_traffic_ctrl_addr [10] "logic s_traffic_ctrl_addr[15:0]" +Toggle 0to1 s_traffic_ctrl_addr [10] "logic s_traffic_ctrl_addr[15:0]" +Toggle 1to0 s_traffic_ctrl_addr [13] "logic s_traffic_ctrl_addr[15:0]" +Toggle 1to0 s_traffic_ctrl_addr [12] "logic s_traffic_ctrl_addr[15:0]" +Toggle 1to0 s_traffic_ctrl_addr [11] "logic s_traffic_ctrl_addr[15:0]" +Toggle 1to0 s_traffic_ctrl_addr [15] "logic s_traffic_ctrl_addr[15:0]" +Toggle 0to1 s_traffic_ctrl_addr [15] "logic s_traffic_ctrl_addr[15:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_id_h_update.data "logic afu_csr_afu_id_h_update.data[63:0]" +Toggle afu_csr_afu_id_h_update.data "logic afu_csr_afu_id_h_update.data[63:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_id_l_update.data "logic afu_csr_afu_id_l_update.data[63:0]" +Toggle afu_csr_afu_id_l_update.data "logic afu_csr_afu_id_l_update.data[63:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_init_update.data "logic afu_csr_afu_init_update.data[63:0]" +Toggle afu_csr_afu_init_update.data "logic afu_csr_afu_init_update.data[63:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_dfh_update.afu_dfh.afu_maj_version "logic afu_csr_dfh_update.afu_dfh.afu_maj_version[3:0]" +Toggle afu_csr_dfh_update.afu_dfh.afu_maj_version "logic afu_csr_dfh_update.afu_dfh.afu_maj_version[3:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_dfh_update.data "logic afu_csr_dfh_update.data[63:0]" +Toggle afu_csr_dfh_update.data "logic afu_csr_dfh_update.data[63:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_dfh_update.afu_dfh.reserved1 "logic afu_csr_dfh_update.afu_dfh.reserved1[7:0]" +Toggle afu_csr_dfh_update.afu_dfh.reserved1 "logic afu_csr_dfh_update.afu_dfh.reserved1[7:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_dfh_update.afu_dfh.reserved0 "logic afu_csr_dfh_update.afu_dfh.reserved0[6:0]" +Toggle afu_csr_dfh_update.afu_dfh.reserved0 "logic afu_csr_dfh_update.afu_dfh.reserved0[6:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_dfh_update.afu_dfh.next_dfh_offset "logic afu_csr_dfh_update.afu_dfh.next_dfh_offset[23:0]" +Toggle afu_csr_dfh_update.afu_dfh.next_dfh_offset "logic afu_csr_dfh_update.afu_dfh.next_dfh_offset[23:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_dfh_update.afu_dfh.feature_type "logic afu_csr_dfh_update.afu_dfh.feature_type[3:0]" +Toggle afu_csr_dfh_update.afu_dfh.feature_type "logic afu_csr_dfh_update.afu_dfh.feature_type[3:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_dfh_update.afu_dfh.feature_id "logic afu_csr_dfh_update.afu_dfh.feature_id[11:0]" +Toggle afu_csr_dfh_update.afu_dfh.feature_id "logic afu_csr_dfh_update.afu_dfh.feature_id[11:0]" +Toggle 0to1 afu_csr_dfh_update.afu_dfh.end_of_list "logic afu_csr_dfh_update.afu_dfh.end_of_list" +Toggle 1to0 afu_csr_dfh_update.afu_dfh.end_of_list "logic afu_csr_dfh_update.afu_dfh.end_of_list" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_dfh_update.afu_dfh.afu_min_version "logic afu_csr_dfh_update.afu_dfh.afu_min_version[3:0]" +Toggle afu_csr_dfh_update.afu_dfh.afu_min_version "logic afu_csr_dfh_update.afu_dfh.afu_min_version[3:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_id_h_update.csr_afu_id_h.afu_id_h "logic afu_csr_afu_id_h_update.csr_afu_id_h.afu_id_h[63:0]" +Toggle afu_csr_afu_id_h_update.csr_afu_id_h.afu_id_h "logic afu_csr_afu_id_h_update.csr_afu_id_h.afu_id_h[63:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_id_h_update.word.lower32 "logic afu_csr_afu_id_h_update.word.lower32[31:0]" +Toggle afu_csr_afu_id_h_update.word.lower32 "logic afu_csr_afu_id_h_update.word.lower32[31:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_scratchpad_update.word.upper32 "logic afu_csr_afu_scratchpad_update.word.upper32[31:0]" +Toggle afu_csr_afu_scratchpad_update.word.upper32 "logic afu_csr_afu_scratchpad_update.word.upper32[31:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_scratchpad_update.word.lower32 "logic afu_csr_afu_scratchpad_update.word.lower32[31:0]" +Toggle afu_csr_afu_scratchpad_update.word.lower32 "logic afu_csr_afu_scratchpad_update.word.lower32[31:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_scratchpad_update.data "logic afu_csr_afu_scratchpad_update.data[63:0]" +Toggle afu_csr_afu_scratchpad_update.data "logic afu_csr_afu_scratchpad_update.data[63:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_scratchpad_reset.word.upper32 "logic afu_csr_afu_scratchpad_reset.word.upper32[31:0]" +Toggle afu_csr_afu_scratchpad_reset.word.upper32 "logic afu_csr_afu_scratchpad_reset.word.upper32[31:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_scratchpad_reset.word.lower32 "logic afu_csr_afu_scratchpad_reset.word.lower32[31:0]" +Toggle afu_csr_afu_scratchpad_reset.word.lower32 "logic afu_csr_afu_scratchpad_reset.word.lower32[31:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_scratchpad_reset.data "logic afu_csr_afu_scratchpad_reset.data[63:0]" +Toggle afu_csr_afu_scratchpad_reset.data "logic afu_csr_afu_scratchpad_reset.data[63:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_init_update.word.upper32 "logic afu_csr_afu_init_update.word.upper32[31:0]" +Toggle afu_csr_afu_init_update.word.upper32 "logic afu_csr_afu_init_update.word.upper32[31:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_init_update.word.lower32 "logic afu_csr_afu_init_update.word.lower32[31:0]" +Toggle afu_csr_afu_init_update.word.lower32 "logic afu_csr_afu_init_update.word.lower32[31:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_init_update.afu_init.reserved "logic afu_csr_afu_init_update.afu_init.reserved[61:0]" +Toggle afu_csr_afu_init_update.afu_init.reserved "logic afu_csr_afu_init_update.afu_init.reserved[61:0]" +Toggle 0to1 afu_csr_afu_init_update.afu_init.init_start "logic afu_csr_afu_init_update.afu_init.init_start" +Toggle 1to0 afu_csr_afu_init_update.afu_init.init_start "logic afu_csr_afu_init_update.afu_init.init_start" +Toggle 0to1 afu_csr_afu_init_update.afu_init.init_done "logic afu_csr_afu_init_update.afu_init.init_done" +Toggle 1to0 afu_csr_afu_init_update.afu_init.init_done "logic afu_csr_afu_init_update.afu_init.init_done" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_id_l_update.word.upper32 "logic afu_csr_afu_id_l_update.word.upper32[31:0]" +Toggle afu_csr_afu_id_l_update.word.upper32 "logic afu_csr_afu_id_l_update.word.upper32[31:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_id_l_update.word.lower32 "logic afu_csr_afu_id_l_update.word.lower32[31:0]" +Toggle afu_csr_afu_id_l_update.word.lower32 "logic afu_csr_afu_id_l_update.word.lower32[31:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_id_l_update.csr_afu_id_l.afu_id_l "logic afu_csr_afu_id_l_update.csr_afu_id_l.afu_id_l[63:0]" +Toggle afu_csr_afu_id_l_update.csr_afu_id_l.afu_id_l "logic afu_csr_afu_id_l_update.csr_afu_id_l.afu_id_l[63:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_id_h_update.word.upper32 "logic afu_csr_afu_id_h_update.word.upper32[31:0]" +Toggle afu_csr_afu_id_h_update.word.upper32 "logic afu_csr_afu_id_h_update.word.upper32[31:0]" +Toggle 0to1 afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.ack_trans "logic afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.ack_trans" +Toggle 1to0 afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.ack_trans "logic afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.ack_trans" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_traffic_ctrl_cmd_reset.word.upper32 "logic afu_csr_afu_traffic_ctrl_cmd_reset.word.upper32[31:0]" +Toggle afu_csr_afu_traffic_ctrl_cmd_reset.word.upper32 "logic afu_csr_afu_traffic_ctrl_cmd_reset.word.upper32[31:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_traffic_ctrl_cmd_reset.word.lower32 "logic afu_csr_afu_traffic_ctrl_cmd_reset.word.lower32[31:0]" +Toggle afu_csr_afu_traffic_ctrl_cmd_reset.word.lower32 "logic afu_csr_afu_traffic_ctrl_cmd_reset.word.lower32[31:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_traffic_ctrl_cmd_reset.data "logic afu_csr_afu_traffic_ctrl_cmd_reset.data[63:0]" +Toggle afu_csr_afu_traffic_ctrl_cmd_reset.data "logic afu_csr_afu_traffic_ctrl_cmd_reset.data[63:0]" +Toggle 0to1 afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.wr_cmd "logic afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.wr_cmd" +Toggle 1to0 afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.wr_cmd "logic afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.wr_cmd" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.reserved1 "logic afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.reserved1[15:0]" +Toggle afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.reserved1 "logic afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.reserved1[15:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.reserved0 "logic afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.reserved0[28:0]" +Toggle afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.reserved0 "logic afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.reserved0[28:0]" +Toggle 0to1 afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.rd_cmd "logic afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.rd_cmd" +Toggle 1to0 afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.rd_cmd "logic afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.rd_cmd" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.addr "logic afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.addr[15:0]" +Toggle afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.addr "logic afu_csr_afu_traffic_ctrl_cmd_reset.afu_traffic_ctrl_cmd.addr[15:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_traffic_ctrl_cmd_update.afu_traffic_ctrl_cmd.addr "logic afu_csr_afu_traffic_ctrl_cmd_update.afu_traffic_ctrl_cmd.addr[15:0]" +Toggle afu_csr_afu_traffic_ctrl_cmd_update.afu_traffic_ctrl_cmd.addr "logic afu_csr_afu_traffic_ctrl_cmd_update.afu_traffic_ctrl_cmd.addr[15:0]" +Toggle 0to1 afu_csr_afu_traffic_ctrl_cmd_update.afu_traffic_ctrl_cmd.wr_cmd "logic afu_csr_afu_traffic_ctrl_cmd_update.afu_traffic_ctrl_cmd.wr_cmd" +Toggle 1to0 afu_csr_afu_traffic_ctrl_cmd_update.afu_traffic_ctrl_cmd.wr_cmd "logic afu_csr_afu_traffic_ctrl_cmd_update.afu_traffic_ctrl_cmd.wr_cmd" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_traffic_ctrl_cmd_update.afu_traffic_ctrl_cmd.reserved1 "logic afu_csr_afu_traffic_ctrl_cmd_update.afu_traffic_ctrl_cmd.reserved1[15:0]" +Toggle afu_csr_afu_traffic_ctrl_cmd_update.afu_traffic_ctrl_cmd.reserved1 "logic afu_csr_afu_traffic_ctrl_cmd_update.afu_traffic_ctrl_cmd.reserved1[15:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_traffic_ctrl_cmd_update.afu_traffic_ctrl_cmd.reserved0 "logic afu_csr_afu_traffic_ctrl_cmd_update.afu_traffic_ctrl_cmd.reserved0[28:0]" +Toggle afu_csr_afu_traffic_ctrl_cmd_update.afu_traffic_ctrl_cmd.reserved0 "logic afu_csr_afu_traffic_ctrl_cmd_update.afu_traffic_ctrl_cmd.reserved0[28:0]" +Toggle 0to1 afu_csr_afu_traffic_ctrl_cmd_update.afu_traffic_ctrl_cmd.rd_cmd "logic afu_csr_afu_traffic_ctrl_cmd_update.afu_traffic_ctrl_cmd.rd_cmd" +Toggle 1to0 afu_csr_afu_traffic_ctrl_cmd_update.afu_traffic_ctrl_cmd.rd_cmd "logic afu_csr_afu_traffic_ctrl_cmd_update.afu_traffic_ctrl_cmd.rd_cmd" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_traffic_ctrl_cmd_update.word.upper32 "logic afu_csr_afu_traffic_ctrl_cmd_update.word.upper32[31:0]" +Toggle afu_csr_afu_traffic_ctrl_cmd_update.word.upper32 "logic afu_csr_afu_traffic_ctrl_cmd_update.word.upper32[31:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_traffic_ctrl_data_reset.word.upper32 "logic afu_csr_afu_traffic_ctrl_data_reset.word.upper32[31:0]" +Toggle afu_csr_afu_traffic_ctrl_data_reset.word.upper32 "logic afu_csr_afu_traffic_ctrl_data_reset.word.upper32[31:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_traffic_ctrl_data_reset.word.lower32 "logic afu_csr_afu_traffic_ctrl_data_reset.word.lower32[31:0]" +Toggle afu_csr_afu_traffic_ctrl_data_reset.word.lower32 "logic afu_csr_afu_traffic_ctrl_data_reset.word.lower32[31:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_traffic_ctrl_data_reset.data "logic afu_csr_afu_traffic_ctrl_data_reset.data[63:0]" +Toggle afu_csr_afu_traffic_ctrl_data_reset.data "logic afu_csr_afu_traffic_ctrl_data_reset.data[63:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_traffic_ctrl_data_reset.afu_traffic_ctrl_data.wr_data "logic afu_csr_afu_traffic_ctrl_data_reset.afu_traffic_ctrl_data.wr_data[31:0]" +Toggle afu_csr_afu_traffic_ctrl_data_reset.afu_traffic_ctrl_data.wr_data "logic afu_csr_afu_traffic_ctrl_data_reset.afu_traffic_ctrl_data.wr_data[31:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_traffic_ctrl_data_reset.afu_traffic_ctrl_data.rd_data "logic afu_csr_afu_traffic_ctrl_data_reset.afu_traffic_ctrl_data.rd_data[31:0]" +Toggle afu_csr_afu_traffic_ctrl_data_reset.afu_traffic_ctrl_data.rd_data "logic afu_csr_afu_traffic_ctrl_data_reset.afu_traffic_ctrl_data.rd_data[31:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_traffic_ctrl_port_update.afu_traffic_ctrl_port.reserved "logic afu_csr_afu_traffic_ctrl_port_update.afu_traffic_ctrl_port.reserved[59:0]" +Toggle afu_csr_afu_traffic_ctrl_port_update.afu_traffic_ctrl_port.reserved "logic afu_csr_afu_traffic_ctrl_port_update.afu_traffic_ctrl_port.reserved[59:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_traffic_ctrl_port_update.word.upper32 "logic afu_csr_afu_traffic_ctrl_port_update.word.upper32[31:0]" +Toggle afu_csr_afu_traffic_ctrl_port_update.word.upper32 "logic afu_csr_afu_traffic_ctrl_port_update.word.upper32[31:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_traffic_ctrl_port_update.word.lower32 "logic afu_csr_afu_traffic_ctrl_port_update.word.lower32[31:0]" +Toggle afu_csr_afu_traffic_ctrl_port_update.word.lower32 "logic afu_csr_afu_traffic_ctrl_port_update.word.lower32[31:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_afu_traffic_ctrl_port_update.data "logic afu_csr_afu_traffic_ctrl_port_update.data[63:0]" +Toggle afu_csr_afu_traffic_ctrl_port_update.data "logic afu_csr_afu_traffic_ctrl_port_update.data[63:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_dfh_update.word.lower32 "logic afu_csr_dfh_update.word.lower32[31:0]" +Toggle afu_csr_dfh_update.word.lower32 "logic afu_csr_dfh_update.word.lower32[31:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_dfh_update.word.upper32 "logic afu_csr_dfh_update.word.upper32[31:0]" +Toggle afu_csr_dfh_update.word.upper32 "logic afu_csr_dfh_update.word.upper32[31:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle scratch "logic scratch[31:0]" +Toggle scratch "logic scratch[31:0]" +Toggle 0to1 range_valid "logic range_valid" +Toggle 1to0 range_valid "logic range_valid" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_port_swap_en_update.data "logic afu_csr_port_swap_en_update.data[63:0]" +Toggle afu_csr_port_swap_en_update.data "logic afu_csr_port_swap_en_update.data[63:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_port_swap_en_update.word.upper32 "logic afu_csr_port_swap_en_update.word.upper32[31:0]" +Toggle afu_csr_port_swap_en_update.word.upper32 "logic afu_csr_port_swap_en_update.word.upper32[31:0]" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_port_swap_en_update.word.lower32 "logic afu_csr_port_swap_en_update.word.lower32[31:0]" +Toggle afu_csr_port_swap_en_update.word.lower32 "logic afu_csr_port_swap_en_update.word.lower32[31:0]" +Toggle 0to1 afu_csr_port_swap_en_update.port_swap_en.swap_en "logic afu_csr_port_swap_en_update.port_swap_en.swap_en" +Toggle 1to0 afu_csr_port_swap_en_update.port_swap_en.swap_en "logic afu_csr_port_swap_en_update.port_swap_en.swap_en" +ANNOTATION: " Values are fixed/tied in design " +Toggle afu_csr_port_swap_en_update.port_swap_en.reserved "logic afu_csr_port_swap_en_update.port_swap_en.reserved[62:0]" +Toggle afu_csr_port_swap_en_update.port_swap_en.reserved "logic afu_csr_port_swap_en_update.port_swap_en.reserved[62:0]" +Toggle 1to0 i_cmd_csr_addr [10] "logic i_cmd_csr_addr[11:0]" +Toggle 0to1 i_cmd_csr_addr [10] "logic i_cmd_csr_addr[11:0]" +Toggle 1to0 i_cmd_csr_addr [9] "logic i_cmd_csr_addr[11:0]" +Toggle 0to1 i_cmd_csr_addr [9] "logic i_cmd_csr_addr[11:0]" +Toggle 1to0 i_cmd_csr_addr [8] "logic i_cmd_csr_addr[11:0]" +Toggle 0to1 i_cmd_csr_addr [8] "logic i_cmd_csr_addr[11:0]" +Toggle 1to0 i_cmd_csr_addr [7] "logic i_cmd_csr_addr[11:0]" +Toggle 0to1 i_cmd_csr_addr [7] "logic i_cmd_csr_addr[11:0]" +Toggle 1to0 i_cmd_csr_addr [1] "logic i_cmd_csr_addr[11:0]" +Toggle 0to1 i_cmd_csr_addr [1] "logic i_cmd_csr_addr[11:0]" +Toggle 1to0 i_cmd_csr_addr [0] "logic i_cmd_csr_addr[11:0]" +Toggle 0to1 i_cmd_csr_addr [0] "logic i_cmd_csr_addr[11:0]" +Toggle 1to0 i_cmd_csr_addr [11] "logic i_cmd_csr_addr[11:0]" +Toggle 0to1 i_cmd_csr_addr [11] "logic i_cmd_csr_addr[11:0]" +Toggle afu_csr_afu_traffic_ctrl_cmd_update.word.lower32 "logic afu_csr_afu_traffic_ctrl_cmd_update.word.lower32[31:0]" +Toggle afu_csr_afu_traffic_ctrl_data_update.afu_traffic_ctrl_data.wr_data "logic afu_csr_afu_traffic_ctrl_data_update.afu_traffic_ctrl_data.wr_data[31:0]" +Toggle afu_csr_afu_traffic_ctrl_data_update.data "logic afu_csr_afu_traffic_ctrl_data_update.data[63:0]" +Toggle afu_csr_afu_traffic_ctrl_data_update.word.upper32 "logic afu_csr_afu_traffic_ctrl_data_update.word.upper32[31:0]" +Toggle afu_csr_afu_traffic_ctrl_port_update.afu_traffic_ctrl_port.port_sel "logic afu_csr_afu_traffic_ctrl_port_update.afu_traffic_ctrl_port.port_sel[3:0]" +Toggle afu_csr_afu_traffic_ctrl_cmd_update.data "logic afu_csr_afu_traffic_ctrl_cmd_update.data[63:0]" +CHECKSUM: "2102680912 36850973" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst +Toggle 1to0 avl_mm_readdata_loopback [0] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [1] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [30] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [30] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [29] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [29] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [28] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [28] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [27] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [27] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [26] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [26] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [25] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [25] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [24] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [24] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [23] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [23] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [22] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [22] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [21] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [21] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [20] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [20] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [19] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [19] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [18] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [18] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [17] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [17] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [16] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [16] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [15] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [15] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [14] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [14] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [13] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [13] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [12] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [12] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [11] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [11] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [10] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [10] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [9] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [9] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [8] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [8] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [7] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [7] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [6] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [6] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [5] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [5] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [4] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [4] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [3] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [3] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [2] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [2] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 avl_mm_readdata_loopback [31] "net avl_mm_readdata_loopback[31:0]" +Toggle 0to1 avl_mm_readdata_loopback [31] "net avl_mm_readdata_loopback[31:0]" +Toggle 1to0 mon_active "net mon_active" +Toggle 1to0 to_mon_rx_error [5] "net to_mon_rx_error[5:0]" +Toggle 0to1 to_mon_rx_error [5] "net to_mon_rx_error[5:0]" +Toggle 1to0 mon_done "net mon_done" +Toggle 0to1 mon_done "net mon_done" +Toggle 1to0 stop_mon "net stop_mon" +Toggle 0to1 stop_mon "net stop_mon" +Toggle 1to0 mac_rx_status_error "net mac_rx_status_error" +Toggle 0to1 mac_rx_status_error "net mac_rx_status_error" +Toggle 1to0 mac_rx_status_valid "net mac_rx_status_valid" +Toggle 0to1 mac_rx_status_valid "net mac_rx_status_valid" +Toggle 1to0 mon_error "net mon_error" +Toggle 0to1 mon_error "net mon_error" +Toggle mac_rx_status_data "net mac_rx_status_data[39:0]" +Toggle 1to0 from_gen_tx_error "net from_gen_tx_error" +Toggle 0to1 from_gen_tx_error "net from_gen_tx_error" +Toggle 1to0 avl_st_tx_error "net avl_st_tx_error" +Toggle 0to1 avl_st_tx_error "net avl_st_tx_error" +Toggle 1to0 avl_st_rx_error [5] "net avl_st_rx_error[5:0]" +Toggle 0to1 avl_st_rx_error [5] "net avl_st_rx_error[5:0]" +Toggle 1to0 avl_st_rx_mon_lpmx_ready "net avl_st_rx_mon_lpmx_ready" +Toggle 0to1 avl_st_rx_mon_lpmx_ready "net avl_st_rx_mon_lpmx_ready" +Toggle avl_st_rx_lpmx_mon_empty "net avl_st_rx_lpmx_mon_empty[2:0]" +Toggle 1to0 avl_st_rx_lpmx_mon_eop "net avl_st_rx_lpmx_mon_eop" +Toggle 0to1 avl_st_rx_lpmx_mon_eop "net avl_st_rx_lpmx_mon_eop" +Toggle avl_st_rx_lpmx_mon_error "net avl_st_rx_lpmx_mon_error[5:0]" +Toggle 1to0 avl_st_rx_lpmx_mon_sop "net avl_st_rx_lpmx_mon_sop" +Toggle 0to1 avl_st_rx_lpmx_mon_sop "net avl_st_rx_lpmx_mon_sop" +Toggle 1to0 avl_st_rx_lpmx_mon_val "net avl_st_rx_lpmx_mon_val" +Toggle 0to1 avl_st_rx_lpmx_mon_val "net avl_st_rx_lpmx_mon_val" +Toggle avl_st_rx_lpmx_mon_data "net avl_st_rx_lpmx_mon_data[63:0]" +CHECKSUM: "2931995947 3499845320" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.pcie_tlp_to_csr_no_dma_inst +Toggle 1to0 axis_rx_length [12] "logic axis_rx_length[13:0]" +Toggle 0to1 axis_rx_length [12] "logic axis_rx_length[13:0]" +Toggle 1to0 axis_rx_length [1] "logic axis_rx_length[13:0]" +Toggle 0to1 axis_rx_length [1] "logic axis_rx_length[13:0]" +Toggle 1to0 axis_rx_length [0] "logic axis_rx_length[13:0]" +Toggle 0to1 axis_rx_length [0] "logic axis_rx_length[13:0]" +Toggle 1to0 axis_rx_length [13] "logic axis_rx_length[13:0]" +Toggle 0to1 axis_rx_length [13] "logic axis_rx_length[13:0]" +Toggle 1to0 tlp_rd_length [12] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [12] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [11] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [11] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [10] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [10] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [9] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [9] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [8] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [8] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [7] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [7] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [6] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [6] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [5] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [5] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [4] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [4] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [1] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [1] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [0] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [0] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_length [13] "logic tlp_rd_length[13:0]" +Toggle 0to1 tlp_rd_length [13] "logic tlp_rd_length[13:0]" +Toggle 1to0 tlp_rd_low_addr [22] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [22] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [21] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [21] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [20] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [20] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [19] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [19] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [18] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [18] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [17] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [17] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [16] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [16] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [15] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [15] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [14] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [14] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [13] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [13] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [12] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [12] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [11] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [11] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [10] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [10] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [9] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [9] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [8] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [8] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [7] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [7] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [1] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [1] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [0] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [0] "logic tlp_rd_low_addr[23:0]" +Toggle 1to0 tlp_rd_low_addr [23] "logic tlp_rd_low_addr[23:0]" +Toggle 0to1 tlp_rd_low_addr [23] "logic tlp_rd_low_addr[23:0]" +Toggle tlp_rd_req_id "logic tlp_rd_req_id[15:0]" +Toggle 1to0 avmm_m2s_address [10] "logic avmm_m2s_address[11:0]" +Toggle 0to1 avmm_m2s_address [10] "logic avmm_m2s_address[11:0]" +Toggle 1to0 avmm_m2s_address [9] "logic avmm_m2s_address[11:0]" +Toggle 0to1 avmm_m2s_address [9] "logic avmm_m2s_address[11:0]" +Toggle 1to0 avmm_m2s_address [8] "logic avmm_m2s_address[11:0]" +Toggle 0to1 avmm_m2s_address [8] "logic avmm_m2s_address[11:0]" +Toggle 1to0 avmm_m2s_address [7] "logic avmm_m2s_address[11:0]" +Toggle 0to1 avmm_m2s_address [7] "logic avmm_m2s_address[11:0]" +Toggle 1to0 avmm_m2s_address [1] "logic avmm_m2s_address[11:0]" +Toggle 0to1 avmm_m2s_address [1] "logic avmm_m2s_address[11:0]" +Toggle 1to0 avmm_m2s_address [0] "logic avmm_m2s_address[11:0]" +Toggle 0to1 avmm_m2s_address [0] "logic avmm_m2s_address[11:0]" +Toggle 1to0 avmm_m2s_address [11] "logic avmm_m2s_address[11:0]" +Toggle 0to1 avmm_m2s_address [11] "logic avmm_m2s_address[11:0]" +Toggle 1to0 avmm_s2m_waitrequest "logic avmm_s2m_waitrequest" +Toggle 0to1 avmm_s2m_waitrequest "logic avmm_s2m_waitrequest" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[0].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[1].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[2].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[3].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[4].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[5].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[6].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[7].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[8].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[9].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[10].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[11].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[12].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[13].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[14].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[15].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[16].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[17].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[18].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[19].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[20].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[21].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[22].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[23].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[24].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[25].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[26].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[27].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[28].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[29].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[30].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[31].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[0].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[1].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[2].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[3].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[4].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[5].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[6].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[7].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[8].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[9].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[10].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[11].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[12].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[13].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[14].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[15].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_rdwr_usrack.resync_chains[0].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_rdwr_usrack.resync_chains[1].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_rdwr_usrack.resync_chains[2].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[0].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[1].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[2].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[3].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[4].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[5].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[6].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[7].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[8].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[9].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[10].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[11].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[12].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[13].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[14].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[15].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[16].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[17].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[18].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[19].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[20].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[21].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[22].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[23].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[24].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[25].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[26].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[27].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[28].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[29].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[30].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[31].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_rst_finish.resync_chains[0].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 2652052405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_rst_finish.resync_chains[1].genblk1.synchronizer +Toggle 1to0 reset_n "net reset_n" +Toggle 0to1 reset_n "net reset_n" +Toggle RANDOM_SEED "reg RANDOM_SEED[31:0]" +CHECKSUM: "809561450 156040868" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.GenRstSync[0].rx_reset_synchronizer.resync_chains[0].genblk1.synchronizer +Toggle 1to0 din "net din" +Toggle 0to1 din "net din" +CHECKSUM: "620743534 3448981415" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.MON +Condition 2 "1939629898" "(mon_done && ((|bad_pkts))) 1 -1" (3 "11") +Condition 2 "1939629898" "(mon_done && ((|bad_pkts))) 1 -1" (2 "10") +CHECKSUM: "1117319907 17875405" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.MON.GenCRCCheck.crc32_chk_inst.crc_comparator_u0 +Condition 4 "3312630553" "(pkt_crc_ready && crc_gen_ready) 1 -1" (2 "10") +Condition 4 "3312630553" "(pkt_crc_ready && crc_gen_ready) 1 -1" (1 "01") +Condition 3 "3312630553" "(pkt_crc_ready && crc_gen_ready) 1 -1" (2 "10") +Condition 3 "3312630553" "(pkt_crc_ready && crc_gen_ready) 1 -1" (1 "01") +Condition 2 "2639725220" "(pkt_crc_ready && crc_gen_ready) 1 -1" (2 "10") +Condition 2 "2639725220" "(pkt_crc_ready && crc_gen_ready) 1 -1" (1 "01") +Condition 1 "3067245414" "(pkt_crc_ready && crc_gen_ready) 1 -1" (2 "10") +Condition 1 "3067245414" "(pkt_crc_ready && crc_gen_ready) 1 -1" (1 "01") +CHECKSUM: "3863186091 1435923241" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.avalon_st_loopback_u0.tx_sc_fifo +Condition 1 "2613928562" "(in_valid && in_ready) 1 -1" (2 "10") +Condition 10 "3242417888" "(out_ready || ((!out_valid))) 1 -1" (1 "00") +Condition 5 "849229920" "(write && read && drop_on_error) 1 -1" (2 "101") +Condition 5 "849229920" "(write && read && drop_on_error) 1 -1" (4 "111") +Condition 5 "849229920" "(write && read && drop_on_error) 1 -1" (1 "011") +CHECKSUM: "4093924741 198605532" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.avalon_st_loopback_u0 +Toggle 1to0 readdata_loopback_ena [0] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [1] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata [0] "net readdata[31:0]" +Toggle 1to0 readdata [1] "net readdata[31:0]" +Toggle 1to0 avalon_st_loopback_ena "net avalon_st_loopback_ena" +Toggle 1to0 to_mon_rx_error [5] "reg to_mon_rx_error[5:0]" +Toggle 0to1 to_mon_rx_error [5] "reg to_mon_rx_error[5:0]" +Toggle 1to0 readdata_loopback_ena [30] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [30] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [29] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [29] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [28] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [28] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [27] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [27] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [26] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [26] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [25] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [25] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [24] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [24] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [23] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [23] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [22] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [22] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [21] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [21] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [20] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [20] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [19] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [19] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [18] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [18] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [17] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [17] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [16] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [16] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [15] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [15] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [14] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [14] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [13] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [13] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [12] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [12] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [11] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [11] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [10] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [10] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [9] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [9] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [8] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [8] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [7] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [7] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [6] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [6] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [5] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [5] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [4] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [4] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [3] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [3] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [2] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [2] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata_loopback_ena [31] "net readdata_loopback_ena[31:0]" +Toggle 0to1 readdata_loopback_ena [31] "net readdata_loopback_ena[31:0]" +Toggle 1to0 readdata [30] "net readdata[31:0]" +Toggle 0to1 readdata [30] "net readdata[31:0]" +Toggle 1to0 readdata [29] "net readdata[31:0]" +Toggle 0to1 readdata [29] "net readdata[31:0]" +Toggle 1to0 readdata [28] "net readdata[31:0]" +Toggle 0to1 readdata [28] "net readdata[31:0]" +Toggle 1to0 readdata [27] "net readdata[31:0]" +Toggle 0to1 readdata [27] "net readdata[31:0]" +Toggle 1to0 readdata [26] "net readdata[31:0]" +Toggle 0to1 readdata [26] "net readdata[31:0]" +Toggle 1to0 readdata [25] "net readdata[31:0]" +Toggle 0to1 readdata [25] "net readdata[31:0]" +Toggle 1to0 readdata [24] "net readdata[31:0]" +Toggle 0to1 readdata [24] "net readdata[31:0]" +Toggle 1to0 readdata [23] "net readdata[31:0]" +Toggle 0to1 readdata [23] "net readdata[31:0]" +Toggle 1to0 readdata [22] "net readdata[31:0]" +Toggle 0to1 readdata [22] "net readdata[31:0]" +Toggle 1to0 readdata [21] "net readdata[31:0]" +Toggle 0to1 readdata [21] "net readdata[31:0]" +Toggle 1to0 readdata [20] "net readdata[31:0]" +Toggle 0to1 readdata [20] "net readdata[31:0]" +Toggle 1to0 readdata [19] "net readdata[31:0]" +Toggle 0to1 readdata [19] "net readdata[31:0]" +Toggle 1to0 readdata [18] "net readdata[31:0]" +Toggle 0to1 readdata [18] "net readdata[31:0]" +Toggle 1to0 readdata [17] "net readdata[31:0]" +Toggle 0to1 readdata [17] "net readdata[31:0]" +Toggle 1to0 readdata [16] "net readdata[31:0]" +Toggle 0to1 readdata [16] "net readdata[31:0]" +Toggle 1to0 readdata [15] "net readdata[31:0]" +Toggle 0to1 readdata [15] "net readdata[31:0]" +Toggle 1to0 readdata [14] "net readdata[31:0]" +Toggle 0to1 readdata [14] "net readdata[31:0]" +Toggle 1to0 readdata [13] "net readdata[31:0]" +Toggle 0to1 readdata [13] "net readdata[31:0]" +Toggle 1to0 readdata [12] "net readdata[31:0]" +Toggle 0to1 readdata [12] "net readdata[31:0]" +Toggle 1to0 readdata [11] "net readdata[31:0]" +Toggle 0to1 readdata [11] "net readdata[31:0]" +Toggle 1to0 readdata [10] "net readdata[31:0]" +Toggle 0to1 readdata [10] "net readdata[31:0]" +Toggle 1to0 readdata [9] "net readdata[31:0]" +Toggle 0to1 readdata [9] "net readdata[31:0]" +Toggle 1to0 readdata [8] "net readdata[31:0]" +Toggle 0to1 readdata [8] "net readdata[31:0]" +Toggle 1to0 readdata [7] "net readdata[31:0]" +Toggle 0to1 readdata [7] "net readdata[31:0]" +Toggle 1to0 readdata [6] "net readdata[31:0]" +Toggle 0to1 readdata [6] "net readdata[31:0]" +Toggle 1to0 readdata [5] "net readdata[31:0]" +Toggle 0to1 readdata [5] "net readdata[31:0]" +Toggle 1to0 readdata [4] "net readdata[31:0]" +Toggle 0to1 readdata [4] "net readdata[31:0]" +Toggle 1to0 readdata [3] "net readdata[31:0]" +Toggle 0to1 readdata [3] "net readdata[31:0]" +Toggle 1to0 readdata [2] "net readdata[31:0]" +Toggle 0to1 readdata [2] "net readdata[31:0]" +Toggle 1to0 readdata [31] "net readdata[31:0]" +Toggle 0to1 readdata [31] "net readdata[31:0]" +Toggle 1to0 from_mac_rx_error [5] "net from_mac_rx_error[5:0]" +Toggle 0to1 from_mac_rx_error [5] "net from_mac_rx_error[5:0]" +Toggle 1to0 to_mac_tx_error "reg to_mac_tx_error" +Toggle 0to1 to_mac_tx_error "reg to_mac_tx_error" +Toggle 1to0 from_gen_tx_error "net from_gen_tx_error" +Toggle 0to1 from_gen_tx_error "net from_gen_tx_error" +CHECKSUM: "620743534 750313388" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.multi_port_axi_traffic_ctrl_inst.multi_port_traffic_ctrl_inst.GenTrafWrap[0].traffic_controller_wrapper.gen_mon_inst.MON +Toggle 1to0 time_stamp_counter [30] "reg time_stamp_counter[31:0]" +Toggle 0to1 time_stamp_counter [30] "reg time_stamp_counter[31:0]" +Toggle 1to0 time_stamp_counter [29] "reg time_stamp_counter[31:0]" +Toggle 0to1 time_stamp_counter [29] "reg time_stamp_counter[31:0]" +Toggle 1to0 time_stamp_counter [28] "reg time_stamp_counter[31:0]" +Toggle 0to1 time_stamp_counter [28] "reg time_stamp_counter[31:0]" +Toggle 1to0 time_stamp_counter [27] "reg time_stamp_counter[31:0]" +Toggle 0to1 time_stamp_counter [27] "reg time_stamp_counter[31:0]" +Toggle 1to0 time_stamp_counter [26] "reg time_stamp_counter[31:0]" +Toggle 0to1 time_stamp_counter [26] "reg time_stamp_counter[31:0]" +Toggle 1to0 time_stamp_counter [25] "reg time_stamp_counter[31:0]" +Toggle 0to1 time_stamp_counter [25] "reg time_stamp_counter[31:0]" +Toggle 1to0 time_stamp_counter [24] "reg time_stamp_counter[31:0]" +Toggle 0to1 time_stamp_counter [24] "reg time_stamp_counter[31:0]" +Toggle 1to0 time_stamp_counter [23] "reg time_stamp_counter[31:0]" +Toggle 0to1 time_stamp_counter [23] "reg time_stamp_counter[31:0]" +Toggle 1to0 time_stamp_counter [22] "reg time_stamp_counter[31:0]" +Toggle 0to1 time_stamp_counter [22] "reg time_stamp_counter[31:0]" +Toggle 1to0 time_stamp_counter [21] "reg time_stamp_counter[31:0]" +Toggle 0to1 time_stamp_counter [21] "reg time_stamp_counter[31:0]" +Toggle 1to0 time_stamp_counter [20] "reg time_stamp_counter[31:0]" +Toggle 0to1 time_stamp_counter [20] "reg time_stamp_counter[31:0]" +Toggle 1to0 time_stamp_counter [19] "reg time_stamp_counter[31:0]" +Toggle 0to1 time_stamp_counter [19] "reg time_stamp_counter[31:0]" +Toggle 1to0 time_stamp_counter [18] "reg time_stamp_counter[31:0]" +Toggle 0to1 time_stamp_counter [18] "reg time_stamp_counter[31:0]" +Toggle 1to0 time_stamp_counter [17] "reg time_stamp_counter[31:0]" +Toggle 0to1 time_stamp_counter [17] "reg time_stamp_counter[31:0]" +Toggle 1to0 time_stamp_counter [31] "reg time_stamp_counter[31:0]" +Toggle 0to1 time_stamp_counter [31] "reg time_stamp_counter[31:0]" +Toggle 1to0 start_time_stamp [30] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [30] "reg start_time_stamp[31:0]" +Toggle 1to0 start_time_stamp [29] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [29] "reg start_time_stamp[31:0]" +Toggle 1to0 start_time_stamp [28] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [28] "reg start_time_stamp[31:0]" +Toggle 1to0 start_time_stamp [27] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [27] "reg start_time_stamp[31:0]" +Toggle 1to0 start_time_stamp [26] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [26] "reg start_time_stamp[31:0]" +Toggle 1to0 start_time_stamp [25] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [25] "reg start_time_stamp[31:0]" +Toggle 1to0 start_time_stamp [24] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [24] "reg start_time_stamp[31:0]" +Toggle 1to0 start_time_stamp [23] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [23] "reg start_time_stamp[31:0]" +Toggle 1to0 start_time_stamp [22] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [22] "reg start_time_stamp[31:0]" +Toggle 1to0 start_time_stamp [21] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [21] "reg start_time_stamp[31:0]" +Toggle 1to0 start_time_stamp [20] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [20] "reg start_time_stamp[31:0]" +Toggle 1to0 start_time_stamp [19] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [19] "reg start_time_stamp[31:0]" +Toggle 1to0 start_time_stamp [18] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [18] "reg start_time_stamp[31:0]" +Toggle 1to0 start_time_stamp [17] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [17] "reg start_time_stamp[31:0]" +Toggle 1to0 start_time_stamp [16] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [16] "reg start_time_stamp[31:0]" +Toggle 1to0 start_time_stamp [15] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [15] "reg start_time_stamp[31:0]" +Toggle 1to0 start_time_stamp [14] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [14] "reg start_time_stamp[31:0]" +Toggle 1to0 start_time_stamp [13] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [13] "reg start_time_stamp[31:0]" +Toggle 1to0 start_time_stamp [12] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [12] "reg start_time_stamp[31:0]" +Toggle 1to0 start_time_stamp [11] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [11] "reg start_time_stamp[31:0]" +Toggle 1to0 start_time_stamp [10] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [10] "reg start_time_stamp[31:0]" +Toggle 1to0 start_time_stamp [9] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [9] "reg start_time_stamp[31:0]" +Toggle 1to0 start_time_stamp [31] "reg start_time_stamp[31:0]" +Toggle 0to1 start_time_stamp [31] "reg start_time_stamp[31:0]" +Toggle number_packet "reg number_packet[31:0]" +Toggle 1to0 inspection_cycle_count [6] "reg inspection_cycle_count[7:0]" +Toggle 0to1 inspection_cycle_count [6] "reg inspection_cycle_count[7:0]" +Toggle 1to0 inspection_cycle_count [5] "reg inspection_cycle_count[7:0]" +Toggle 0to1 inspection_cycle_count [5] "reg inspection_cycle_count[7:0]" +Toggle 1to0 inspection_cycle_count [4] "reg inspection_cycle_count[7:0]" +Toggle 0to1 inspection_cycle_count [4] "reg inspection_cycle_count[7:0]" +Toggle 1to0 inspection_cycle_count [3] "reg inspection_cycle_count[7:0]" +Toggle 0to1 inspection_cycle_count [3] "reg inspection_cycle_count[7:0]" +Toggle 1to0 inspection_cycle_count [2] "reg inspection_cycle_count[7:0]" +Toggle 0to1 inspection_cycle_count [2] "reg inspection_cycle_count[7:0]" +Toggle 1to0 inspection_cycle_count [1] "reg inspection_cycle_count[7:0]" +Toggle 0to1 inspection_cycle_count [1] "reg inspection_cycle_count[7:0]" +Toggle 1to0 inspection_cycle_count [7] "reg inspection_cycle_count[7:0]" +Toggle 0to1 inspection_cycle_count [7] "reg inspection_cycle_count[7:0]" +Toggle 1to0 good_pkts [30] "reg good_pkts[31:0]" +Toggle 0to1 good_pkts [30] "reg good_pkts[31:0]" +Toggle 1to0 good_pkts [29] "reg good_pkts[31:0]" +Toggle 0to1 good_pkts [29] "reg good_pkts[31:0]" +Toggle 1to0 good_pkts [28] "reg good_pkts[31:0]" +Toggle 0to1 good_pkts [28] "reg good_pkts[31:0]" +Toggle 1to0 good_pkts [27] "reg good_pkts[31:0]" +Toggle 0to1 good_pkts [27] "reg good_pkts[31:0]" +Toggle 1to0 good_pkts [26] "reg good_pkts[31:0]" +Toggle 0to1 good_pkts [26] "reg good_pkts[31:0]" +Toggle 1to0 good_pkts [25] "reg good_pkts[31:0]" +Toggle 0to1 good_pkts [25] "reg good_pkts[31:0]" +Toggle 1to0 good_pkts [24] "reg good_pkts[31:0]" +Toggle 0to1 good_pkts [24] "reg good_pkts[31:0]" +Toggle 1to0 good_pkts [23] "reg good_pkts[31:0]" +Toggle 0to1 good_pkts [23] "reg good_pkts[31:0]" +Toggle 1to0 good_pkts [22] "reg good_pkts[31:0]" +Toggle 0to1 good_pkts [22] "reg good_pkts[31:0]" +Toggle 1to0 good_pkts [21] "reg good_pkts[31:0]" +Toggle 0to1 good_pkts [21] "reg good_pkts[31:0]" +Toggle 1to0 good_pkts [20] "reg good_pkts[31:0]" +Toggle 0to1 good_pkts [20] "reg good_pkts[31:0]" +Toggle 1to0 good_pkts [19] "reg good_pkts[31:0]" +Toggle 0to1 good_pkts [19] "reg good_pkts[31:0]" +Toggle 1to0 good_pkts [18] "reg good_pkts[31:0]" +Toggle 0to1 good_pkts [18] "reg good_pkts[31:0]" +Toggle 1to0 good_pkts [17] "reg good_pkts[31:0]" +Toggle 0to1 good_pkts [17] "reg good_pkts[31:0]" +Toggle 1to0 good_pkts [16] "reg good_pkts[31:0]" +Toggle 0to1 good_pkts [16] "reg good_pkts[31:0]" +Toggle 1to0 good_pkts [15] "reg good_pkts[31:0]" +Toggle 0to1 good_pkts [15] "reg good_pkts[31:0]" +Toggle 1to0 good_pkts [14] "reg good_pkts[31:0]" +Toggle 0to1 good_pkts [14] "reg good_pkts[31:0]" +Toggle 1to0 good_pkts [31] "reg good_pkts[31:0]" +Toggle 0to1 good_pkts [31] "reg good_pkts[31:0]" +Toggle 1to0 gen_lpbk "reg gen_lpbk" +Toggle 0to1 gen_lpbk "reg gen_lpbk" +Toggle 1to0 end_time_stamp [30] "reg end_time_stamp[31:0]" +Toggle 0to1 end_time_stamp [30] "reg end_time_stamp[31:0]" +Toggle 1to0 end_time_stamp [29] "reg end_time_stamp[31:0]" +Toggle 0to1 end_time_stamp [29] "reg end_time_stamp[31:0]" +Toggle 1to0 end_time_stamp [28] "reg end_time_stamp[31:0]" +Toggle 0to1 end_time_stamp [28] "reg end_time_stamp[31:0]" +Toggle 1to0 end_time_stamp [27] "reg end_time_stamp[31:0]" +Toggle 0to1 end_time_stamp [27] "reg end_time_stamp[31:0]" +Toggle 1to0 end_time_stamp [26] "reg end_time_stamp[31:0]" +Toggle 0to1 end_time_stamp [26] "reg end_time_stamp[31:0]" +Toggle 1to0 end_time_stamp [25] "reg end_time_stamp[31:0]" +Toggle 0to1 end_time_stamp [25] "reg end_time_stamp[31:0]" +Toggle 1to0 end_time_stamp [24] "reg end_time_stamp[31:0]" +Toggle 0to1 end_time_stamp [24] "reg end_time_stamp[31:0]" +Toggle 1to0 end_time_stamp [23] "reg end_time_stamp[31:0]" +Toggle 0to1 end_time_stamp [23] "reg end_time_stamp[31:0]" +Toggle 1to0 end_time_stamp [22] "reg end_time_stamp[31:0]" +Toggle 0to1 end_time_stamp [22] "reg end_time_stamp[31:0]" +Toggle 1to0 end_time_stamp [21] "reg end_time_stamp[31:0]" +Toggle 0to1 end_time_stamp [21] "reg end_time_stamp[31:0]" +Toggle 1to0 end_time_stamp [20] "reg end_time_stamp[31:0]" +Toggle 0to1 end_time_stamp [20] "reg end_time_stamp[31:0]" +Toggle 1to0 end_time_stamp [19] "reg end_time_stamp[31:0]" +Toggle 0to1 end_time_stamp [19] "reg end_time_stamp[31:0]" +Toggle 1to0 end_time_stamp [18] "reg end_time_stamp[31:0]" +Toggle 0to1 end_time_stamp [18] "reg end_time_stamp[31:0]" +Toggle 1to0 end_time_stamp [17] "reg end_time_stamp[31:0]" +Toggle 0to1 end_time_stamp [17] "reg end_time_stamp[31:0]" +Toggle 1to0 end_time_stamp [31] "reg end_time_stamp[31:0]" +Toggle 0to1 end_time_stamp [31] "reg end_time_stamp[31:0]" +Toggle 1to0 cycle_rx_count [62] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [62] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [61] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [61] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [60] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [60] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [59] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [59] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [58] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [58] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [57] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [57] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [56] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [56] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [55] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [55] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [54] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [54] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [53] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [53] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [52] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [52] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [51] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [51] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [50] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [50] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [49] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [49] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [48] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [48] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [47] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [47] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [46] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [46] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [45] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [45] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [44] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [44] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [43] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [43] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [42] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [42] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [41] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [41] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [40] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [40] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [39] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [39] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [38] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [38] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [37] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [37] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [36] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [36] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [35] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [35] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [34] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [34] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [33] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [33] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [32] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [32] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [31] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [31] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [30] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [30] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [29] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [29] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [28] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [28] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [27] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [27] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [26] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [26] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [25] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [25] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [24] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [24] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [23] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [23] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [22] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [22] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [21] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [21] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [20] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [20] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [19] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [19] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [18] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [18] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [17] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [17] "reg cycle_rx_count[63:0]" +Toggle 1to0 cycle_rx_count [63] "reg cycle_rx_count[63:0]" +Toggle 0to1 cycle_rx_count [63] "reg cycle_rx_count[63:0]" +Toggle 1to0 byte_count [62] "reg byte_count[63:0]" +Toggle 0to1 byte_count [62] "reg byte_count[63:0]" +Toggle 1to0 byte_count [61] "reg byte_count[63:0]" +Toggle 0to1 byte_count [61] "reg byte_count[63:0]" +Toggle 1to0 byte_count [60] "reg byte_count[63:0]" +Toggle 0to1 byte_count [60] "reg byte_count[63:0]" +Toggle 1to0 byte_count [59] "reg byte_count[63:0]" +Toggle 0to1 byte_count [59] "reg byte_count[63:0]" +Toggle 1to0 byte_count [58] "reg byte_count[63:0]" +Toggle 0to1 byte_count [58] "reg byte_count[63:0]" +Toggle 1to0 byte_count [57] "reg byte_count[63:0]" +Toggle 0to1 byte_count [57] "reg byte_count[63:0]" +Toggle 1to0 byte_count [56] "reg byte_count[63:0]" +Toggle 0to1 byte_count [56] "reg byte_count[63:0]" +Toggle 1to0 byte_count [55] "reg byte_count[63:0]" +Toggle 0to1 byte_count [55] "reg byte_count[63:0]" +Toggle 1to0 byte_count [54] "reg byte_count[63:0]" +Toggle 0to1 byte_count [54] "reg byte_count[63:0]" +Toggle 1to0 byte_count [53] "reg byte_count[63:0]" +Toggle 0to1 byte_count [53] "reg byte_count[63:0]" +Toggle 1to0 byte_count [52] "reg byte_count[63:0]" +Toggle 0to1 byte_count [52] "reg byte_count[63:0]" +Toggle 1to0 byte_count [51] "reg byte_count[63:0]" +Toggle 0to1 byte_count [51] "reg byte_count[63:0]" +Toggle 1to0 byte_count [50] "reg byte_count[63:0]" +Toggle 0to1 byte_count [50] "reg byte_count[63:0]" +Toggle 1to0 byte_count [49] "reg byte_count[63:0]" +Toggle 0to1 byte_count [49] "reg byte_count[63:0]" +Toggle 1to0 byte_count [48] "reg byte_count[63:0]" +Toggle 0to1 byte_count [48] "reg byte_count[63:0]" +Toggle 1to0 byte_count [47] "reg byte_count[63:0]" +Toggle 0to1 byte_count [47] "reg byte_count[63:0]" +Toggle 1to0 byte_count [46] "reg byte_count[63:0]" +Toggle 0to1 byte_count [46] "reg byte_count[63:0]" +Toggle 1to0 byte_count [45] "reg byte_count[63:0]" +Toggle 0to1 byte_count [45] "reg byte_count[63:0]" +Toggle 1to0 byte_count [44] "reg byte_count[63:0]" +Toggle 0to1 byte_count [44] "reg byte_count[63:0]" +Toggle 1to0 byte_count [43] "reg byte_count[63:0]" +Toggle 0to1 byte_count [43] "reg byte_count[63:0]" +Toggle 1to0 byte_count [42] "reg byte_count[63:0]" +Toggle 0to1 byte_count [42] "reg byte_count[63:0]" +Toggle 1to0 byte_count [41] "reg byte_count[63:0]" +Toggle 0to1 byte_count [41] "reg byte_count[63:0]" +Toggle 1to0 byte_count [40] "reg byte_count[63:0]" +Toggle 0to1 byte_count [40] "reg byte_count[63:0]" +Toggle 1to0 byte_count [39] "reg byte_count[63:0]" +Toggle 0to1 byte_count [39] "reg byte_count[63:0]" +Toggle 1to0 byte_count [38] "reg byte_count[63:0]" +Toggle 0to1 byte_count [38] "reg byte_count[63:0]" +Toggle 1to0 byte_count [37] "reg byte_count[63:0]" +Toggle 0to1 byte_count [37] "reg byte_count[63:0]" +Toggle 1to0 byte_count [36] "reg byte_count[63:0]" +Toggle 0to1 byte_count [36] "reg byte_count[63:0]" +Toggle 1to0 byte_count [35] "reg byte_count[63:0]" +Toggle 0to1 byte_count [35] "reg byte_count[63:0]" +Toggle 1to0 byte_count [34] "reg byte_count[63:0]" +Toggle 0to1 byte_count [34] "reg byte_count[63:0]" +Toggle 1to0 byte_count [33] "reg byte_count[63:0]" +Toggle 0to1 byte_count [33] "reg byte_count[63:0]" +Toggle 1to0 byte_count [32] "reg byte_count[63:0]" +Toggle 0to1 byte_count [32] "reg byte_count[63:0]" +Toggle 1to0 byte_count [31] "reg byte_count[63:0]" +Toggle 0to1 byte_count [31] "reg byte_count[63:0]" +Toggle 1to0 byte_count [30] "reg byte_count[63:0]" +Toggle 0to1 byte_count [30] "reg byte_count[63:0]" +Toggle 1to0 byte_count [29] "reg byte_count[63:0]" +Toggle 0to1 byte_count [29] "reg byte_count[63:0]" +Toggle 1to0 byte_count [28] "reg byte_count[63:0]" +Toggle 0to1 byte_count [28] "reg byte_count[63:0]" +Toggle 1to0 byte_count [27] "reg byte_count[63:0]" +Toggle 0to1 byte_count [27] "reg byte_count[63:0]" +Toggle 1to0 byte_count [26] "reg byte_count[63:0]" +Toggle 0to1 byte_count [26] "reg byte_count[63:0]" +Toggle 1to0 byte_count [25] "reg byte_count[63:0]" +Toggle 0to1 byte_count [25] "reg byte_count[63:0]" +Toggle 1to0 byte_count [24] "reg byte_count[63:0]" +Toggle 0to1 byte_count [24] "reg byte_count[63:0]" +Toggle 1to0 byte_count [23] "reg byte_count[63:0]" +Toggle 0to1 byte_count [23] "reg byte_count[63:0]" +Toggle 1to0 byte_count [22] "reg byte_count[63:0]" +Toggle 0to1 byte_count [22] "reg byte_count[63:0]" +Toggle 1to0 byte_count [21] "reg byte_count[63:0]" +Toggle 0to1 byte_count [21] "reg byte_count[63:0]" +Toggle 1to0 byte_count [20] "reg byte_count[63:0]" +Toggle 0to1 byte_count [20] "reg byte_count[63:0]" +Toggle 1to0 byte_count [19] "reg byte_count[63:0]" +Toggle 0to1 byte_count [19] "reg byte_count[63:0]" +Toggle 1to0 byte_count [63] "reg byte_count[63:0]" +Toggle 0to1 byte_count [63] "reg byte_count[63:0]" +Toggle 1to0 bad_pkts [30] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [30] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [29] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [29] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [28] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [28] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [27] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [27] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [26] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [26] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [25] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [25] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [24] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [24] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [23] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [23] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [22] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [22] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [21] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [21] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [20] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [20] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [19] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [19] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [18] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [18] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [17] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [17] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [16] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [16] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [15] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [15] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [14] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [14] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [13] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [13] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [12] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [12] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [11] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [11] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [10] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [10] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [9] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [9] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [8] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [8] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [7] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [7] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [6] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [6] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [5] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [5] "reg bad_pkts[31:0]" +Toggle 1to0 bad_pkts [31] "reg bad_pkts[31:0]" +Toggle 0to1 bad_pkts [31] "reg bad_pkts[31:0]" +Toggle rx_frame_words_45 "reg rx_frame_words_45[63:0]" +Toggle rx_frame_words_67 "reg rx_frame_words_67[63:0]" +Toggle rx_frame_words_89 "reg rx_frame_words_89[63:0]" +Toggle rx_frame_words_ab "reg rx_frame_words_ab[63:0]" +Toggle rx_frame_words_cd "reg rx_frame_words_cd[63:0]" +Toggle rx_frame_words_ef "reg rx_frame_words_ef[63:0]" +Toggle rx_frame_words_23 "reg rx_frame_words_23[63:0]" +Toggle 1to0 stop_pedge "net stop_pedge" +Toggle 0to1 stop_pedge "net stop_pedge" +Toggle stop_sync "reg stop_sync[3:0]" +Toggle 1to0 stop_mon "net stop_mon" +Toggle 0to1 stop_mon "net stop_mon" +Toggle 1to0 mon_csr [9] "reg mon_csr[9:0]" +Toggle 0to1 mon_csr [9] "reg mon_csr[9:0]" +Toggle 1to0 mon_csr [1] "reg mon_csr[9:0]" +Toggle 0to1 mon_csr [1] "reg mon_csr[9:0]" +Toggle 1to0 mon_csr [0] "reg mon_csr[9:0]" +Toggle 0to1 mon_csr [0] "reg mon_csr[9:0]" +Toggle 1to0 mon_csr [2] "reg mon_csr[9:0]" +Toggle 0to1 mon_csr [2] "reg mon_csr[9:0]" +Toggle 1to0 mon_active "net mon_active" +Toggle inspection_start_cycle "reg inspection_start_cycle[31:0]" +Toggle inspection_start_frame "reg inspection_start_frame[31:0]" +Toggle inspection_number_cycles "reg inspection_number_cycles[31:0]" +Toggle 1to0 next_monstate [0] "reg next_monstate[1:0]" +Toggle 1to0 next_monstate [1] "reg next_monstate[1:0]" +Toggle 0to1 next_monstate [1] "reg next_monstate[1:0]" +Toggle 1to0 monstate [0] "reg monstate[1:0]" +Toggle 1to0 monstate [1] "reg monstate[1:0]" +Toggle 0to1 monstate [1] "reg monstate[1:0]" +Toggle 1to0 mac_rx_status_error "net mac_rx_status_error" +Toggle 0to1 mac_rx_status_error "net mac_rx_status_error" +Toggle 1to0 mac_rx_status_valid "net mac_rx_status_valid" +Toggle 0to1 mac_rx_status_valid "net mac_rx_status_valid" +Toggle 1to0 mon_done "net mon_done" +Toggle 0to1 mon_done "net mon_done" +Toggle 1to0 mon_error "reg mon_error" +Toggle 0to1 mon_error "reg mon_error" +Toggle 1to0 mon_init "net mon_init" +Toggle 0to1 mon_init "net mon_init" +Toggle mac_rx_status_data "net mac_rx_status_data[39:0]" +Toggle 1to0 init_reg "net init_reg" +Toggle 0to1 init_reg "net init_reg" +Toggle 1to0 init_dly "reg init_dly" +Toggle 0to1 init_dly "reg init_dly" +Toggle 0to1 avalon_st_rx_error [5] "net avalon_st_rx_error[5:0]" +Toggle 1to0 avalon_st_rx_error [5] "net avalon_st_rx_error[5:0]" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.GenRstSync[0].rx_reset_synchronizer.resync_chains[0].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 1 "1521658384" "if ((depth < 2))" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_rst_finish.resync_chains[1].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_rst_finish.resync_chains[0].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[31].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[30].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[29].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[28].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[27].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +Block 9 "177874314" "din_last <= 1'b0;" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[26].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[25].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[24].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[23].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[22].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[21].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[20].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[19].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[18].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[17].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[16].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[15].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[14].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[13].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[12].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[11].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[10].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[9].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[8].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +Block 12 "2265797376" "din_s1 <= 1'b0;" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[7].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[6].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[5].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[4].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[3].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[2].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 9 "177874314" "din_last <= 1'b0;" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[1].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_readdata.resync_chains[0].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_rdwr_usrack.resync_chains[2].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_rdwr_usrack.resync_chains[1].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +Block 12 "2265797376" "din_s1 <= 1'b0;" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_rdwr_usrack.resync_chains[0].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[15].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +Block 12 "2265797376" "din_s1 <= 1'b0;" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[14].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[13].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[12].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[11].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[10].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[9].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[8].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[7].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[6].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[5].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[4].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[3].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[2].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +Block 9 "177874314" "din_last <= 1'b0;" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[1].genblk1.synchronizer +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +Block 9 "177874314" "din_last <= 1'b0;" +Block 12 "2265797376" "din_s1 <= 1'b0;" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_addr.resync_chains[0].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +Block 9 "177874314" "din_last <= 1'b0;" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[31].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[30].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[29].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[28].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 9 "177874314" "din_last <= 1'b0;" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[27].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[26].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[25].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[24].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[23].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[22].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[21].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[20].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[19].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +Block 9 "177874314" "din_last <= 1'b0;" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[18].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[17].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[16].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[15].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 9 "177874314" "din_last <= 1'b0;" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[14].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[13].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[12].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[11].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[10].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 9 "177874314" "din_last <= 1'b0;" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[9].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[8].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[7].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[6].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[5].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 9 "177874314" "din_last <= 1'b0;" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[4].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[3].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[2].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[1].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" +CHECKSUM: "809561450 1861434223" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.eth_traffic_pcie_tlp_to_csr_inst.inst_eth_traffic_csr.inst_mm_ctrl_xcvr.genblk1.inst_sync_writedata.resync_chains[0].genblk1.synchronizer +Block 2 "98597039" "$display(\"%m: Error: synchronizer length: %0d less than 2.\", depth);" +Block 15 "3112052122" "dreg <= {(depth - 1) {1'b0}};" +Block 12 "2265797376" "din_s1 <= 1'b0;" +Block 9 "177874314" "din_last <= 1'b0;" +Block 6 "138464234" "random <= $random(RANDOM_SEED);" diff --git a/verification/coverage/he_lpbk_exclusions.el b/verification/coverage/he_lpbk_exclusions.el new file mode 100644 index 0000000..ce0e7c6 --- /dev/null +++ b/verification/coverage/he_lpbk_exclusions.el @@ -0,0 +1,5511 @@ +//================================================== +// This file contains the Excluded objects +// Generated By User: srudrarx +// Format Version: 2 +// Date: Fri Apr 22 08:32:46 2022 +// ExclMode: default +//================================================== +CHECKSUM: "3630569307" +INSTANCE:tb_top.DUT.afu_top.he_lb_inst.he_lb_req.mmio_rsp_q.genblk1.scfifo_component.dev +CHECKSUM: "2100166288" +INSTANCE:tb_top.DUT.afu_top.he_lb_inst.he_lb_req.mmio_rsp_q.genblk1.scfifo_component +CHECKSUM: "2948434777" +ANNOTATION: " mem blocks are not functional in he_lpbk " +INSTANCE:tb_top.DUT.afu_top.he_lb_mem_if +CHECKSUM: "2948434777" +ANNOTATION: " mem blocks are not functional in he_lpbk " +INSTANCE:tb_top.DUT.afu_top.he_lb_inst.mem_lb_if +CHECKSUM: "2948434777" +ANNOTATION: " mem blocks are not functional in he_lpbk " +INSTANCE:tb_top.DUT.afu_top.he_lb_inst.mem_rw_if +CHECKSUM: "2948434777" +ANNOTATION: " mem blocks are not functional in he_lpbk " +INSTANCE:tb_top.DUT.afu_top.he_lb_inst.mode_lpbk.mem_if +CHECKSUM: "599439132" +ANNOTATION: " emif signals are invalid in he_lpbk " +INSTANCE:tb_top.DUT.afu_top.he_lb_inst.mode_lpbk.emif_req_q +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.he_lb_inst.mode_lpbk.clnum_ram +CHECKSUM: "3572029108" +ANNOTATION: " emif signals are invalid in he_lpbk " +INSTANCE:tb_top.DUT.afu_top.he_lb_inst.mode_lpbk.emif_trk_ram +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.he_lb_inst.mode_lpbk.clnum_ram.mem +CHECKSUM: "2618233009 166614001" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req +Toggle 1to0 tx_req_dout_pcie_dm_hdr.host_addr_h [19] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.host_addr_h [18] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.host_addr_h [17] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.host_addr_h [20] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.host_addr_h [20] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.host_addr_h [22] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.host_addr_h [21] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.host_addr_h [24] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.host_addr_h [24] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.host_addr_h [23] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.host_addr_h [23] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.host_addr_h [27] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.host_addr_h [26] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.host_addr_h [25] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.host_addr_h [28] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.host_addr_h [28] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.host_addr_h [29] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.host_addr_h [31] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.host_addr_h [31] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.host_addr_h [30] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.host_addr_h [30] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.host_addr_h [16] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.host_addr_h [16] "logic tx_req_dout_pcie_dm_hdr.host_addr_h[31:0]" +Toggle pf_id "logic pf_id[2:0]" +Toggle 1to0 ab_error_valid "logic ab_error_valid" +Toggle 0to1 ab_error_valid "logic ab_error_valid" +Toggle 1to0 ab_rx_rsp_ready "logic ab_rx_rsp_ready" +Toggle 0to1 ab_rx_rsp_ready "logic ab_rx_rsp_ready" +Toggle 1to0 ab_error_info [1] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [1] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [2] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [2] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [3] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [3] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [4] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [4] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [0] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [0] "logic ab_error_info[31:0]" +Toggle 1to0 use_dm_encoding "logic use_dm_encoding" +Toggle 0to1 use_dm_encoding "logic use_dm_encoding" +ANNOTATION: " Randomized value " +Toggle num_writes "logic num_writes[39:0]" +ANNOTATION: " Randomized value " +Toggle num_reads "logic num_reads[39:0]" +ANNOTATION: " Randomized value " +Toggle re2csr_num_writes "logic re2csr_num_writes[31:0]" +ANNOTATION: " Randomized value " +Toggle re2csr_num_reads "logic re2csr_num_reads[31:0]" +ANNOTATION: " Randomized value " +Toggle host_addr "logic host_addr[63:0]" +ANNOTATION: " Randomized value " +Toggle csr_dsm_addr "logic csr_dsm_addr[63:0]" +ANNOTATION: " Randomized value " +Toggle tx_if_pcie_len "logic tx_if_pcie_len[23:0]" +ANNOTATION: " Randomized value " +Toggle csr2re_num_lines "logic csr2re_num_lines[31:0]" +ANNOTATION: " Randomized value " +Toggle csr_num_lines "logic csr_num_lines[31:0]" +ANNOTATION: " Randomized value " +Toggle num_reads_pend "logic num_reads_pend[31:0]" +ANNOTATION: " Randomized value " +Toggle re2csr_num_rdpend "logic re2csr_num_rdpend[31:0]" +ANNOTATION: " Randomized value " +Toggle tx_if_pcie_addr "logic tx_if_pcie_addr[63:0]" +Toggle MmioCplData "logic MmioCplData[255:0]" +ANNOTATION: " Randomized value " +Toggle mmio_rsp_dout "logic mmio_rsp_dout[511:0]" +ANNOTATION: " Randomized value " +Toggle mmio_rsp_din "logic mmio_rsp_din[511:0]" +Toggle 1to0 dsm_status [126] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [126] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [125] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [125] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [124] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [124] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [123] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [123] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [122] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [122] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [121] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [121] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [120] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [120] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [119] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [119] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [118] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [118] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [117] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [117] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [116] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [116] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [115] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [115] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [114] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [114] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [113] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [113] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [112] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [112] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [111] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [111] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [110] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [110] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [109] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [109] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [108] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [108] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [107] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [107] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [106] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [106] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [105] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [105] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [104] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [104] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [127] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [127] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [62] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [62] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [61] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [61] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [60] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [60] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [59] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [59] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [58] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [58] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [57] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [57] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [56] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [56] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [55] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [55] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [54] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [54] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [53] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [53] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [52] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [52] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [51] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [51] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [50] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [50] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [49] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [49] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [48] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [48] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [47] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [47] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [46] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [46] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [45] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [45] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [44] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [44] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [43] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [43] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [42] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [42] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [41] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [41] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [40] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [40] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [39] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [39] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [38] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [38] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [37] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [37] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [63] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [63] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [30] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [30] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [29] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [29] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [28] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [28] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [27] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [27] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [26] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [26] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [25] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [25] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [24] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [24] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [23] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [23] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [22] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [22] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [21] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [21] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [20] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [20] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [19] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [19] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [18] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [18] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [17] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [17] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [16] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [16] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [31] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [31] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [14] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [14] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [13] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [13] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [12] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [12] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [11] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [11] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [10] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [10] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [9] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [9] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [8] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [8] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [7] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [7] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [6] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [6] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [5] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [5] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [4] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [4] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [3] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [3] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [2] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [2] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [15] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [15] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [222] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [222] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [221] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [221] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [220] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [220] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [219] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [219] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [218] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [218] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [217] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [217] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [216] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [216] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [215] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [215] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [214] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [214] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [213] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [213] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [212] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [212] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [211] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [211] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [210] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [210] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [209] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [209] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [208] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [208] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [223] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [223] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [510] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [510] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [509] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [509] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [508] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [508] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [507] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [507] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [506] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [506] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [505] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [505] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [504] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [504] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [503] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [503] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [502] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [502] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [501] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [501] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [500] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [500] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [499] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [499] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [498] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [498] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [497] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [497] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [496] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [496] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [495] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [495] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [494] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [494] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [493] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [493] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [492] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [492] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [491] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [491] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [490] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [490] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [489] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [489] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [488] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [488] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [487] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [487] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [486] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [486] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [485] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [485] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [484] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [484] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [483] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [483] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [482] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [482] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [481] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [481] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [480] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [480] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [479] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [479] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [478] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [478] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [477] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [477] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [476] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [476] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [475] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [475] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [474] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [474] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [473] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [473] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [472] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [472] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [471] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [471] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [470] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [470] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [469] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [469] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [468] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [468] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [467] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [467] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [466] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [466] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [465] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [465] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [464] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [464] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [463] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [463] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [462] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [462] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [461] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [461] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [460] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [460] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [459] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [459] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [458] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [458] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [457] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [457] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [456] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [456] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [455] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [455] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [454] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [454] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [453] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [453] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [452] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [452] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [451] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [451] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [450] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [450] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [449] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [449] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [448] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [448] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [447] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [447] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [446] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [446] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [445] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [445] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [444] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [444] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [443] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [443] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [442] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [442] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [441] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [441] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [440] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [440] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [439] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [439] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [438] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [438] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [437] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [437] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [436] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [436] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [435] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [435] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [434] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [434] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [433] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [433] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [432] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [432] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [431] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [431] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [430] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [430] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [429] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [429] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [428] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [428] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [427] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [427] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [426] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [426] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [425] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [425] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [424] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [424] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [423] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [423] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [422] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [422] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [421] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [421] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [420] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [420] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [419] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [419] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [418] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [418] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [417] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [417] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [416] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [416] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [415] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [415] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [414] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [414] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [413] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [413] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [412] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [412] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [411] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [411] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [410] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [410] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [409] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [409] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [408] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [408] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [407] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [407] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [406] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [406] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [405] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [405] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [404] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [404] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [403] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [403] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [402] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [402] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [401] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [401] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [400] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [400] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [399] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [399] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [398] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [398] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [397] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [397] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [396] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [396] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [395] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [395] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [394] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [394] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [393] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [393] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [392] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [392] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [391] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [391] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [390] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [390] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [389] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [389] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [388] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [388] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [387] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [387] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [386] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [386] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [385] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [385] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [384] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [384] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [383] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [383] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [382] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [382] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [381] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [381] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [380] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [380] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [379] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [379] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [378] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [378] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [377] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [377] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [376] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [376] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [375] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [375] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [374] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [374] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [373] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [373] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [372] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [372] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [371] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [371] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [370] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [370] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [369] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [369] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [368] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [368] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [367] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [367] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [366] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [366] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [365] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [365] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [364] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [364] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [363] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [363] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [362] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [362] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [361] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [361] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [360] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [360] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [359] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [359] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [358] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [358] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [357] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [357] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [356] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [356] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [355] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [355] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [354] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [354] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [353] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [353] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [352] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [352] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [351] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [351] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [350] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [350] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [349] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [349] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [348] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [348] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [347] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [347] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [346] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [346] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [345] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [345] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [344] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [344] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [343] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [343] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [342] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [342] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [341] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [341] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [340] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [340] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [339] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [339] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [338] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [338] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [337] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [337] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [336] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [336] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [335] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [335] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [334] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [334] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [333] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [333] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [332] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [332] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [331] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [331] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [330] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [330] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [329] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [329] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [328] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [328] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [327] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [327] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [326] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [326] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [325] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [325] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [324] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [324] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [323] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [323] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [322] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [322] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [321] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [321] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [320] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [320] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [319] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [319] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [318] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [318] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [317] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [317] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [316] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [316] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [315] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [315] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [314] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [314] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [313] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [313] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [312] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [312] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [311] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [311] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [310] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [310] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [309] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [309] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [308] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [308] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [307] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [307] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [306] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [306] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [305] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [305] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [304] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [304] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [303] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [303] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [302] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [302] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [301] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [301] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [300] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [300] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [299] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [299] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [298] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [298] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [297] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [297] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [296] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [296] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [295] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [295] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [294] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [294] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [293] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [293] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [292] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [292] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [291] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [291] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [290] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [290] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [289] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [289] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [288] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [288] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [287] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [287] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [286] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [286] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [285] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [285] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [284] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [284] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [283] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [283] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [282] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [282] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [281] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [281] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [280] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [280] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [279] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [279] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [278] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [278] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [277] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [277] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [276] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [276] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [275] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [275] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [274] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [274] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [273] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [273] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [272] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [272] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [271] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [271] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [270] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [270] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [269] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [269] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [268] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [268] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [267] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [267] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [266] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [266] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [265] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [265] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [264] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [264] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [263] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [263] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [262] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [262] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [261] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [261] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [260] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [260] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [259] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [259] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [258] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [258] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [257] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [257] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [256] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [256] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [255] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [255] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [254] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [254] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [253] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [253] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [252] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [252] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [251] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [251] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [250] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [250] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [249] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [249] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [248] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [248] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [247] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [247] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [246] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [246] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [245] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [245] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [244] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [244] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [243] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [243] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [242] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [242] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [241] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [241] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [240] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [240] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [239] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [239] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [238] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [238] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [237] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [237] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [236] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [236] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [235] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [235] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [234] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [234] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [233] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [233] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [232] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [232] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [231] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [231] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [230] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [230] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [229] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [229] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [228] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [228] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [227] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [227] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [511] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [511] "logic dsm_status[511:0]" +Toggle 1to0 dsm_number [13] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [13] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [12] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [12] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [11] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [11] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [10] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [10] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [9] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [9] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [8] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [8] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [7] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [7] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [6] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [6] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [5] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [5] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [4] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [4] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [3] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [3] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [2] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [2] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [1] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [1] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [14] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [14] "logic dsm_number[14:0]" +ANNOTATION: " Randomized value " +Toggle re2csr_num_wrpend "logic re2csr_num_wrpend[31:0]" +ANNOTATION: " Randomized value " +Toggle num_writes_pend "logic num_writes_pend[31:0]" +Toggle dm_pu_enc_mode "logic dm_pu_enc_mode[1:0]" +Toggle 1to0 csr_intr [14] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [14] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [13] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [13] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [12] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [12] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [11] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [11] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [10] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [10] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [9] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [9] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [8] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [8] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [7] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [7] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [6] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [6] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [5] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [5] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [4] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [4] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [3] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [3] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [2] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [2] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [1] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [1] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [0] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [0] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [15] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [15] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [30] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [30] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [29] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [29] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [28] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [28] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [27] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [27] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [26] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [26] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [25] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [25] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [24] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [24] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [23] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [23] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [22] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [22] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [21] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [21] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [20] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [20] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [19] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [19] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [18] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [18] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [31] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [31] "logic csr_intr[31:0]" +Toggle 1to0 csr2re_interrupt0 [30] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [30] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [29] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [29] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [28] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [28] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [27] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [27] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [26] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [26] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [25] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [25] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [24] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [24] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [23] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [23] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [22] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [22] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [21] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [21] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [20] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [20] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [19] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [19] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [18] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [18] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [15] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [15] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [14] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [14] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [13] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [13] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [12] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [12] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [11] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [11] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [10] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [10] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [9] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [9] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [8] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [8] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [7] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [7] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [6] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [6] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [5] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [5] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [4] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [4] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [3] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [3] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [2] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [2] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [1] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [1] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [0] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [0] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [31] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [31] "logic csr2re_interrupt0[31:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.pf_num "logic tx_intr_dm_hdr.pf_num[2:0]" +Toggle 1to0 ab_error_info [30] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [30] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [29] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [29] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [28] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [28] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [27] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [27] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [26] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [26] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [25] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [25] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [24] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [24] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [23] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [23] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [22] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [22] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [21] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [21] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [20] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [20] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [19] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [19] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [18] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [18] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [17] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [17] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [16] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [16] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [15] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [15] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [14] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [14] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [13] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [13] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [12] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [12] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [11] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [11] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [10] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [10] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [9] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [9] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [8] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [8] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [7] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [7] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [6] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [6] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [5] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [5] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [31] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [31] "logic ab_error_info[31:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.attr.AT "logic MmioCplHdr.attr.AT[1:0]" +ANNOTATION: " emif signals are invalid in he_lpbk " +Toggle avmm_num_reads "net avmm_num_reads[39:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.vf_num "logic MmioCplHdr.vf_num[10:0]" +Toggle 0to1 MmioCplHdr.vf_active "logic MmioCplHdr.vf_active" +Toggle 1to0 MmioCplHdr.vf_active "logic MmioCplHdr.vf_active" +ANNOTATION: " Header " +Toggle MmioCplHdr.slot_num "logic MmioCplHdr.slot_num[4:0]" +Toggle 0to1 MmioCplHdr.rsvd5 "logic MmioCplHdr.rsvd5" +Toggle 1to0 MmioCplHdr.rsvd5 "logic MmioCplHdr.rsvd5" +ANNOTATION: " Header " +Toggle MmioCplHdr.rsvd4 "logic MmioCplHdr.rsvd4[31:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.rsvd3 "logic MmioCplHdr.rsvd3[1:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.rsvd2 "logic MmioCplHdr.rsvd2[3:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.rsvd1 "logic MmioCplHdr.rsvd1[6:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.pref_type "logic MmioCplHdr.pref_type[4:0]" +Toggle 0to1 MmioCplHdr.pref_present "logic MmioCplHdr.pref_present" +Toggle 1to0 MmioCplHdr.pref_present "logic MmioCplHdr.pref_present" +ANNOTATION: " Header " +Toggle MmioCplHdr.pref "logic MmioCplHdr.pref[23:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.pf_num "logic MmioCplHdr.pf_num[2:0]" +Toggle 0to1 MmioCplHdr.mm_mode "logic MmioCplHdr.mm_mode" +Toggle 1to0 MmioCplHdr.mm_mode "logic MmioCplHdr.mm_mode" +ANNOTATION: " Header " +Toggle MmioCplHdr.metadata_l "logic MmioCplHdr.metadata_l[31:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.metadata_h "logic MmioCplHdr.metadata_h[31:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.fmt_type "logic MmioCplHdr.fmt_type[7:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.cpl_status "logic MmioCplHdr.cpl_status[2:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.comp_id "logic MmioCplHdr.comp_id[15:0]" +Toggle 0to1 MmioCplHdr.bcm "logic MmioCplHdr.bcm" +Toggle 1to0 MmioCplHdr.bcm "logic MmioCplHdr.bcm" +Toggle 0to1 MmioCplHdr.attr.TH "logic MmioCplHdr.attr.TH" +Toggle 1to0 MmioCplHdr.attr.TH "logic MmioCplHdr.attr.TH" +Toggle 0to1 MmioCplHdr.attr.TD "logic MmioCplHdr.attr.TD" +Toggle 1to0 MmioCplHdr.attr.TD "logic MmioCplHdr.attr.TD" +Toggle 0to1 MmioCplHdr.attr.LN "logic MmioCplHdr.attr.LN" +Toggle 1to0 MmioCplHdr.attr.LN "logic MmioCplHdr.attr.LN" +Toggle 0to1 MmioCplHdr.attr.EP "logic MmioCplHdr.attr.EP" +Toggle 1to0 MmioCplHdr.attr.EP "logic MmioCplHdr.attr.EP" +ANNOTATION: " emif signals are invalid in he_lpbk " +Toggle avmm_num_ticks_h "net avmm_num_ticks_h[19:0]" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.mm_mode "logic tx_req_dout_pcie_dm_hdr.mm_mode" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.mm_mode "logic tx_req_dout_pcie_dm_hdr.mm_mode" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.metadata_l "logic tx_req_dout_pcie_dm_hdr.metadata_l[31:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.metadata_h "logic tx_req_dout_pcie_dm_hdr.metadata_h[31:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.host_addr_l "logic tx_req_dout_pcie_dm_hdr.host_addr_l[1:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.attr.rsvd2 "logic tx_req_dout_pcie_dm_hdr.attr.rsvd2[1:0]" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.attr.rsvd1 "logic tx_req_dout_pcie_dm_hdr.attr.rsvd1" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.attr.rsvd1 "logic tx_req_dout_pcie_dm_hdr.attr.rsvd1" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.attr.TH "logic tx_req_dout_pcie_dm_hdr.attr.TH" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.attr.TH "logic tx_req_dout_pcie_dm_hdr.attr.TH" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.attr.TD "logic tx_req_dout_pcie_dm_hdr.attr.TD" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.attr.TD "logic tx_req_dout_pcie_dm_hdr.attr.TD" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.attr.LN "logic tx_req_dout_pcie_dm_hdr.attr.LN" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.attr.LN "logic tx_req_dout_pcie_dm_hdr.attr.LN" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.attr.EP "logic tx_req_dout_pcie_dm_hdr.attr.EP" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.attr.EP "logic tx_req_dout_pcie_dm_hdr.attr.EP" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.attr.AT "logic tx_req_dout_pcie_dm_hdr.attr.AT[1:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.TC "logic tx_req_dout_pcie_dm_hdr.TC[2:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.PH "logic tx_req_dout_pcie_dm_hdr.PH[1:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.vf_num "logic tx_intr_dm_hdr.vf_num[10:0]" +Toggle 0to1 tx_intr_dm_hdr.vf_active "logic tx_intr_dm_hdr.vf_active" +Toggle 1to0 tx_intr_dm_hdr.vf_active "logic tx_intr_dm_hdr.vf_active" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.vector_num "logic tx_intr_dm_hdr.vector_num[15:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.slot_num "logic tx_intr_dm_hdr.slot_num[4:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.rsvd9 "logic tx_intr_dm_hdr.rsvd9[23:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.rsvd8 "logic tx_intr_dm_hdr.rsvd8[31:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.rsvd7 "logic tx_intr_dm_hdr.rsvd7[15:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.rsvd6 "logic tx_intr_dm_hdr.rsvd6[31:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.rsvd5 "logic tx_intr_dm_hdr.rsvd5[1:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.rsvd4 "logic tx_intr_dm_hdr.rsvd4[3:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.rsvd3 "logic tx_intr_dm_hdr.rsvd3[6:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.rsvd2 "logic tx_intr_dm_hdr.rsvd2[31:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.rsvd1 "logic tx_intr_dm_hdr.rsvd1[31:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.pref_type "logic tx_intr_dm_hdr.pref_type[4:0]" +Toggle 0to1 tx_intr_dm_hdr.pref_present "logic tx_intr_dm_hdr.pref_present" +Toggle 1to0 tx_intr_dm_hdr.pref_present "logic tx_intr_dm_hdr.pref_present" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.pref "logic tx_intr_dm_hdr.pref[23:0]" +Toggle 0to1 tx_intr_dm_hdr.mm_mode "logic tx_intr_dm_hdr.mm_mode" +Toggle 1to0 tx_intr_dm_hdr.mm_mode "logic tx_intr_dm_hdr.mm_mode" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.fmt_type "logic tx_intr_dm_hdr.fmt_type[7:0]" +Toggle 0to1 rx_rsp_perr "logic rx_rsp_perr" +Toggle 1to0 rx_rsp_perr "logic rx_rsp_perr" +Toggle 0to1 rx_rsp_full "logic rx_rsp_full" +Toggle 1to0 rx_rsp_full "logic rx_rsp_full" +Toggle 0to1 rx_rsp_err "logic rx_rsp_err" +Toggle 1to0 rx_rsp_err "logic rx_rsp_err" +Toggle 0to1 rx_rsp_data1_in.sop "logic rx_rsp_data1_in.sop" +Toggle 1to0 rx_rsp_data1_in.sop "logic rx_rsp_data1_in.sop" +Toggle 0to1 rx_rsp_data1_in.eop "logic rx_rsp_data1_in.eop" +Toggle 1to0 rx_rsp_data1_in.eop "logic rx_rsp_data1_in.eop" +Toggle 0to1 rx_rsp_data1_in.dm_encoded "logic rx_rsp_data1_in.dm_encoded" +Toggle 1to0 rx_rsp_data1_in.dm_encoded "logic rx_rsp_data1_in.dm_encoded" +ANNOTATION: " Cannot be covered functionally " +Toggle num_ticks_h "logic num_ticks_h[19:0]" +Toggle 0to1 mmio_rsp_full "logic mmio_rsp_full" +Toggle 1to0 mmio_rsp_full "logic mmio_rsp_full" +Toggle 0to1 mmio_rsp_err "logic mmio_rsp_err" +Toggle 1to0 mmio_rsp_err "logic mmio_rsp_err" +ANNOTATION: " Connected to fifo signals " +Toggle mmio_rsp_ecc "logic mmio_rsp_ecc[1:0]" +ANNOTATION: " Not connected " +Toggle csr2re_stride "logic csr2re_stride[31:0]" +Toggle 0to1 axi_rx_if_T2.sop "logic axi_rx_if_T2.sop" +Toggle 1to0 axi_rx_if_T2.sop "logic axi_rx_if_T2.sop" +Toggle 0to1 axi_rx_if_T2.ready "logic axi_rx_if_T2.ready" +Toggle 1to0 axi_rx_if_T2.ready "logic axi_rx_if_T2.ready" +ANNOTATION: " emif signals are invalid in he_lpbk " +Toggle avmm_num_writes "net avmm_num_writes[39:0]" +ANNOTATION: " emif signals are invalid in he_lpbk " +Toggle avmm_num_ticks_l "net avmm_num_ticks_l[19:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.pf_num "logic tx_req_dout_pcie_dm_hdr.pf_num[2:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.metadata_l "logic tx_req_dout_pcie_pu_hdr.metadata_l[31:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.metadata_h "logic tx_req_dout_pcie_pu_hdr.metadata_h[31:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.bar_number "logic tx_req_dout_pcie_pu_hdr.bar_number[6:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.attr.rsvd2 "logic tx_req_dout_pcie_pu_hdr.attr.rsvd2[1:0]" +Toggle 0to1 tx_req_dout_pcie_pu_hdr.attr.rsvd1 "logic tx_req_dout_pcie_pu_hdr.attr.rsvd1" +Toggle 1to0 tx_req_dout_pcie_pu_hdr.attr.rsvd1 "logic tx_req_dout_pcie_pu_hdr.attr.rsvd1" +Toggle 0to1 tx_req_dout_pcie_pu_hdr.attr.TH "logic tx_req_dout_pcie_pu_hdr.attr.TH" +Toggle 1to0 tx_req_dout_pcie_pu_hdr.attr.TH "logic tx_req_dout_pcie_pu_hdr.attr.TH" +Toggle 0to1 tx_req_dout_pcie_pu_hdr.attr.TD "logic tx_req_dout_pcie_pu_hdr.attr.TD" +Toggle 1to0 tx_req_dout_pcie_pu_hdr.attr.TD "logic tx_req_dout_pcie_pu_hdr.attr.TD" +Toggle 0to1 tx_req_dout_pcie_pu_hdr.attr.LN "logic tx_req_dout_pcie_pu_hdr.attr.LN" +Toggle 1to0 tx_req_dout_pcie_pu_hdr.attr.LN "logic tx_req_dout_pcie_pu_hdr.attr.LN" +Toggle 0to1 tx_req_dout_pcie_pu_hdr.attr.EP "logic tx_req_dout_pcie_pu_hdr.attr.EP" +Toggle 1to0 tx_req_dout_pcie_pu_hdr.attr.EP "logic tx_req_dout_pcie_pu_hdr.attr.EP" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.attr.AT "logic tx_req_dout_pcie_pu_hdr.attr.AT[1:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.TC "logic tx_req_dout_pcie_pu_hdr.TC[2:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.PH "logic tx_req_dout_pcie_pu_hdr.PH[1:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.vf_num "logic tx_req_dout_pcie_dm_hdr.vf_num[10:0]" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.vf_active "logic tx_req_dout_pcie_dm_hdr.vf_active" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.vf_active "logic tx_req_dout_pcie_dm_hdr.vf_active" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.slot_num "logic tx_req_dout_pcie_dm_hdr.slot_num[4:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.rsvd6 "logic tx_req_dout_pcie_dm_hdr.rsvd6[7:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.rsvd5 "logic tx_req_dout_pcie_dm_hdr.rsvd5[1:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.rsvd4 "logic tx_req_dout_pcie_dm_hdr.rsvd4[3:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.rsvd3 "logic tx_req_dout_pcie_dm_hdr.rsvd3[6:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.pref_type "logic tx_req_dout_pcie_dm_hdr.pref_type[4:0]" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.pref_present "logic tx_req_dout_pcie_dm_hdr.pref_present" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.pref_present "logic tx_req_dout_pcie_dm_hdr.pref_present" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.pref "logic tx_req_dout_pcie_dm_hdr.pref[23:0]" +Toggle 0to1 tx_req_dout_pcie_pu_hdr.mm_mode "logic tx_req_dout_pcie_pu_hdr.mm_mode" +Toggle 1to0 tx_req_dout_pcie_pu_hdr.mm_mode "logic tx_req_dout_pcie_pu_hdr.mm_mode" +Toggle 0to1 tx_req_perr "logic tx_req_perr" +Toggle 1to0 tx_req_perr "logic tx_req_perr" +Toggle 0to1 tx_req_err "logic tx_req_err" +Toggle 1to0 tx_req_err "logic tx_req_err" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.vf_num "logic tx_req_dout_pcie_pu_hdr.vf_num[10:0]" +Toggle 0to1 tx_req_dout_pcie_pu_hdr.vf_active "logic tx_req_dout_pcie_pu_hdr.vf_active" +Toggle 1to0 tx_req_dout_pcie_pu_hdr.vf_active "logic tx_req_dout_pcie_pu_hdr.vf_active" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.slot_num "logic tx_req_dout_pcie_pu_hdr.slot_num[4:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.rsvd3 "logic tx_req_dout_pcie_pu_hdr.rsvd3[1:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.rsvd2 "logic tx_req_dout_pcie_pu_hdr.rsvd2[3:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.req_id "logic tx_req_dout_pcie_pu_hdr.req_id[15:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.pref_type "logic tx_req_dout_pcie_pu_hdr.pref_type[4:0]" +Toggle 0to1 tx_req_dout_pcie_pu_hdr.pref_present "logic tx_req_dout_pcie_pu_hdr.pref_present" +Toggle 1to0 tx_req_dout_pcie_pu_hdr.pref_present "logic tx_req_dout_pcie_pu_hdr.pref_present" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.pref "logic tx_req_dout_pcie_pu_hdr.pref[23:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.pf_num "logic tx_req_dout_pcie_pu_hdr.pf_num[2:0]" +Toggle vf_id "logic vf_id[10:0]" +Toggle 0to1 ErrorVector [31] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [31] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [5] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [5] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [6] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [6] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [7] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [7] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [8] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [8] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [9] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [9] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [10] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [10] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [11] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [11] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [12] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [12] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [13] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [13] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [14] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [14] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [15] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [15] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [16] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [16] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [17] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [17] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [18] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [18] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [19] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [19] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [20] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [20] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [21] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [21] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [22] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [22] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [23] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [23] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [24] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [24] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [25] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [25] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [26] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [26] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [27] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [27] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [28] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [28] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [29] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [29] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [30] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [30] "logic ErrorVector[31:0]" +Toggle 0to1 re2csr_error [31] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [31] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [5] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [5] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [6] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [6] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [7] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [7] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [8] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [8] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [9] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [9] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [10] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [10] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [11] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [11] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [12] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [12] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [13] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [13] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [14] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [14] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [15] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [15] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [16] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [16] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [17] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [17] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [18] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [18] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [19] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [19] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [20] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [20] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [21] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [21] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [22] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [22] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [23] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [23] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [24] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [24] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [25] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [25] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [26] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [26] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [27] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [27] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [28] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [28] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [29] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [29] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [30] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [30] "logic re2csr_error[31:0]" +Toggle 0to1 csr2re_ctl [31] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [31] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [3] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [3] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [4] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [4] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [5] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [5] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [6] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [6] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [7] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [7] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [8] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [8] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [9] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [9] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [10] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [10] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [11] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [11] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [12] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [12] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [13] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [13] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [14] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [14] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [15] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [15] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [16] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [16] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [17] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [17] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [18] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [18] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [19] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [19] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [20] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [20] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [21] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [21] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [22] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [22] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [23] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [23] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [24] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [24] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [25] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [25] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [26] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [26] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [27] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [27] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [28] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [28] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [29] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [29] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [30] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [30] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr_ctl [31] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [31] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [3] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [3] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [4] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [4] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [5] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [5] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [6] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [6] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [7] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [7] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [8] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [8] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [9] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [9] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [10] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [10] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [11] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [11] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [12] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [12] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [13] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [13] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [14] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [14] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [15] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [15] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [16] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [16] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [17] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [17] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [18] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [18] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [19] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [19] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [20] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [20] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [21] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [21] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [22] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [22] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [23] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [23] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [24] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [24] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [25] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [25] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [26] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [26] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [27] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [27] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [28] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [28] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [29] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [29] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [30] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [30] "logic csr_ctl[31:0]" +ANNOTATION: " axi signals " +Toggle axi_rx_if_T2.user "logic axi_rx_if_T2.user[9:0]" +ANNOTATION: " axi signals " +Toggle axi_tx_if_p.user "logic axi_tx_if_p.user[9:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.byte_count "logic MmioCplHdr.byte_count[11:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.length_h "logic tx_req_dout_pcie_dm_hdr.length_h[11:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.length "logic MmioCplHdr.length[9:0]" +Toggle 0to1 csr2re_cfg [63] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [63] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [30] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [30] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [31] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [31] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [32] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [32] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [33] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [33] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [34] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [34] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [35] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [35] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [36] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [36] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [37] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [37] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [38] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [38] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [39] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [39] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [40] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [40] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [41] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [41] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [42] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [42] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [43] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [43] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [44] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [44] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [45] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [45] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [46] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [46] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [47] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [47] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [48] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [48] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [49] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [49] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [50] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [50] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [51] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [51] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [52] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [52] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [53] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [53] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [54] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [54] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [55] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [55] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [56] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [56] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [57] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [57] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [58] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [58] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [59] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [59] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [60] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [60] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [61] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [61] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [62] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [62] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [19] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [19] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [7] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [7] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [8] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [8] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [9] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [9] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [10] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [10] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [11] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [11] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [12] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [12] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [13] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [13] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [14] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [14] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [15] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [15] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [16] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [16] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [17] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [17] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [18] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [18] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr_cfg [63] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [63] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [7] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [7] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [8] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [8] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [9] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [9] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [10] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [10] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [11] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [11] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [12] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [12] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [13] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [13] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [14] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [14] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [15] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [15] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [16] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [16] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [17] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [17] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [18] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [18] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [19] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [19] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [30] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [30] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [31] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [31] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [32] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [32] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [33] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [33] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [34] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [34] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [35] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [35] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [36] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [36] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [37] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [37] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [38] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [38] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [39] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [39] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [40] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [40] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [41] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [41] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [42] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [42] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [43] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [43] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [44] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [44] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [45] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [45] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [46] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [46] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [47] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [47] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [48] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [48] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [49] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [49] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [50] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [50] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [51] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [51] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [52] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [52] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [53] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [53] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [54] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [54] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [55] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [55] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [56] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [56] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [57] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [57] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [58] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [58] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [59] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [59] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [60] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [60] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [61] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [61] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [62] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [62] "logic csr_cfg[63:0]" +Toggle 0to1 req_len_b2 [4] "logic req_len_b2[4:0]" +Toggle 1to0 req_len_b2 [4] "logic req_len_b2[4:0]" +Toggle 0to1 req_len_b2 [2] "logic req_len_b2[4:0]" +Toggle 1to0 req_len_b2 [2] "logic req_len_b2[4:0]" +Toggle 0to1 req_len_b2 [3] "logic req_len_b2[4:0]" +Toggle 1to0 req_len_b2 [3] "logic req_len_b2[4:0]" +ANNOTATION: " axi signals " +Toggle axi_tx_if_p.keep "logic axi_tx_if_p.keep[63:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.low_addr "logic MmioCplHdr.low_addr[6:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.host_addr_m "logic tx_req_dout_pcie_dm_hdr.host_addr_m[29:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.host_addr_l "logic tx_req_dout_pcie_pu_hdr.host_addr_l[29:0]" +ANNOTATION: " Cannot be covered functionally " +Toggle num_ticks_l "logic num_ticks_l[19:0]" +CHECKSUM: "1575787188 3552759914" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.mode_lpbk +ANNOTATION: " EMIF is not connected in he_lpbk " +Condition 2 "3972006383" "(({emif_trk_rad_co, emif_trk_rad} == rd_addr) && ((emif_readdatavalid_T1 & emif_trk_dout[1]))) 1 -1" +CHECKSUM: "599439132 1849783068" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.mmio_rsp_q +ANNOTATION: " Quartus fifo " +Branch 0 "233563799" "(!Resetb)" (1) "(!Resetb) 0,(fifo_ren & (fifo_count == 4'b0)) " +ANNOTATION: " Quartus fifo " +Branch 0 "233563799" "(!Resetb)" (2) "(!Resetb) 0,((fifo_wen & (!fifo_ren)) & full) " +CHECKSUM: "599439132 2687758089" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.mode_lpbk.tx_q +ANNOTATION: " Quartus fifo- need not be generated " +Branch 0 "1362767249" "(!Resetb)" (1) "(!Resetb) 0,(fifo_ren & (fifo_count == 11'b0)) " +ANNOTATION: " Quartus fifo- need not be generated " +Branch 0 "1362767249" "(!Resetb)" (2) "(!Resetb) 0,((fifo_wen & (!fifo_ren)) & full) " +CHECKSUM: "599439132 2687758089" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.host_rw.mode_rdwr.tx_q +ANNOTATION: " Quartus fifo- need not be generated " +Branch 0 "1362767249" "(!Resetb)" (1) "(!Resetb) 0,(fifo_ren & (fifo_count == 11'b0)) " +ANNOTATION: " Quartus fifo- need not be generated " +Branch 0 "1362767249" "(!Resetb)" (2) "(!Resetb) 0,((fifo_wen & (!fifo_ren)) & full) " +CHECKSUM: "599439132 2687758089" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.mode_lpbk.rx_q +ANNOTATION: " Quartus fifo- need not be generated " +Branch 0 "1362767249" "(!Resetb)" (2) "(!Resetb) 0,((fifo_wen & (!fifo_ren)) & full) " +ANNOTATION: " Quartus fifo- need not be generated " +Branch 0 "1362767249" "(!Resetb)" (1) "(!Resetb) 0,(fifo_ren & (fifo_count == 11'b0)) " +CHECKSUM: "3520213052 291490293" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.he_rx_rsp_q +Block 2 "4108503805" "out0 = (raddr0[0] ? odd_out : even_out);" +Block 5 "2211809701" "even_din = even_in_q;" +CHECKSUM: "3520213052 291490293" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.he_tx_req_q +Block 2 "4108503805" "out0 = (raddr0[0] ? odd_out : even_out);" +Block 6 "724266113" "even_din = (((!w_odd_even[0]) & wen0) ? din0 : din1);" +CHECKSUM: "599439132 1844698467" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.mode_lpbk.rx_q +ANNOTATION: " Not connected " +Toggle fifo_eccstatus "net fifo_eccstatus[1:0]" +Toggle 1to0 fifo_err "logic fifo_err" +Toggle 0to1 fifo_err "logic fifo_err" +Toggle 1to0 full "net full" +Toggle 0to1 full "net full" +Toggle 1to0 almost_empty "net almost_empty" +Toggle 0to1 almost_empty "net almost_empty" +ANNOTATION: " Data signals " +Toggle fifo_din "net fifo_din[513:0]" +ANNOTATION: " Data signals " +Toggle fifo_dout "net fifo_dout[513:0]" +CHECKSUM: "599439132 1418678335" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.mmio_rsp_q +Toggle fifo_count "net fifo_count[3:0]" +Toggle fifo_dout "net fifo_dout[511:0]" +ANNOTATION: " Data signals " +Toggle fifo_dout "net fifo_dout[511:0]" +Toggle fifo_din "net fifo_din[511:0]" +ANNOTATION: " Data signals " +Toggle fifo_din "net fifo_din[511:0]" +Toggle 0to1 almost_empty "net almost_empty" +Toggle 1to0 almost_empty "net almost_empty" +Toggle 0to1 full "net full" +Toggle 1to0 full "net full" +Toggle 0to1 fifo_err "logic fifo_err" +Toggle 1to0 fifo_err "logic fifo_err" +ANNOTATION: " Not connected " +Toggle fifo_eccstatus "net fifo_eccstatus[1:0]" +CHECKSUM: "599439132 2723442098" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.mode_lpbk.tx_q +ANNOTATION: " Data signals " +Toggle fifo_din "net fifo_din[514:0]" +ANNOTATION: " Data signals " +Toggle fifo_dout "net fifo_dout[514:0]" +ANNOTATION: " Not connected " +Toggle fifo_eccstatus "net fifo_eccstatus[1:0]" +Toggle 1to0 fifo_err "logic fifo_err" +Toggle 0to1 fifo_err "logic fifo_err" +Toggle 1to0 full "net full" +Toggle 0to1 full "net full" +Toggle 1to0 almost_empty "net almost_empty" +Toggle 0to1 almost_empty "net almost_empty" +CHECKSUM: "599439132 2723442098" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.host_rw.mode_rdwr.tx_q +ANNOTATION: " Quartus fifo- need not be generated " +Toggle fifo_count "net fifo_count[10:0]" +ANNOTATION: " Quartus fifo- need not be generated " +Toggle fifo_din "net fifo_din[514:0]" +ANNOTATION: " Quartus fifo- need not be generated " +Toggle fifo_dout "net fifo_dout[514:0]" +ANNOTATION: " Quartus fifo- need not be generated " +Toggle fifo_eccstatus "net fifo_eccstatus[1:0]" +Toggle 1to0 fifo_err "logic fifo_err" +Toggle 0to1 fifo_err "logic fifo_err" +Toggle 1to0 full "net full" +Toggle 0to1 full "net full" +Toggle 1to0 almost_empty "net almost_empty" +Toggle 0to1 almost_empty "net almost_empty" +CHECKSUM: "1575787188 784985182" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.mode_lpbk +Block 132 "2657744755" ";" +Block 136 "4132693144" ";" +Block 140 "3499880051" ";" +Block 144 "4204325147" ";" +Block 149 "3524869349" ";" +Block 153 "2818050566" ";" +Block 157 "3230578631" ";" +Block 161 "157836716" ";" +Block 65 "426961957" "mem_if.writedata <= {'0, rx_rsp_pld_q};" +Block 101 "774788384" "rx_rsp_wen <= 1'b0;" +Block 100 "2356339917" "if ((!test_resetb_q))" +Block 98 "134004304" "rd_rsp_cnt <= (rd_rsp_cnt + recent_rx_rsp_pld_len);" +Block 97 "2060305715" "if ((emif_readdatavalid_T1 & emif_trk_dout[1]))" +Block 96 "3892776937" "rd_rsp_cnt <= 0;" +Block 95 "4020820216" "if ((state == IDLE))" +Block 93 "283939854" "recent_rx_rsp_pld_len <= (emif_readdata_T1[31:24] + (|emif_readdata_T1[23:18]));" +Block 92 "3104536608" "emif_readdatavalid_T1 <= emif.readdatavalid;" +Block 90 "1475334661" "emif_state <= EMIF_IDLE;" +Block 89 "3896216580" "mem_if.read <= '0;" +Block 86 "2352347785" "emif_state <= EMIF_READ_RSP;" +Block 85 "1734724613" "mem_if.read <= ((!rx_rsp_full) & (!mem_if.waitrequest));" +Block 84 "4118909365" "mem_if.write <= 1'b0;" +Block 82 "4131075661" "emif_state <= EMIF_READ;" +Block 81 "2279458603" "if ((emif_wr_cnt == total_len))" +Block 79 "2862277079" "mem_if.write <= 1'b1;" +Block 78 "799279031" "if (rx_rsp_valid_q)" +Block 76 "4155046176" "emif_state <= EMIF_WRITE;" +Block 75 "4051341689" "if (emif_start)" +Block 73 "1205353479" "emif_wr_ack_cnt <= 'b0;" +Block 72 "1989175347" "mem_if.write <= 1'b0;" +Block 71 "3307984645" "case (emif_state)" +Block 69 "607230221" "emif_wr_ack_cnt <= (emif_wr_ack_cnt + emif.writeresponsevalid);" +Block 68 "3281111933" "mem_if.write <= 1'b0;" +Block 66 "457876672" "mem_if.writedata[47:32] <= clnum_ram_dout;" +Block 105 "3560153718" "{emif_trk_rad_co, emif_trk_rad} <= 'b0;" +Block 131 "3956740591" "ErrorVector[0] <= 1;" +Block 160 "853555128" "#100" +Block 156 "2725329329" "$display(\"======================================================================================================\");" +Block 152 "3995717433" "$display(\"======================================================================================================\");" +Block 148 "1629689826" "$display(\"======================================================================================================\");" +Block 143 "3600159615" "ErrorVector[3] <= 1;" +Block 139 "1412364358" "ErrorVector[2] <= 1;" +Block 135 "2307788477" "ErrorVector[1] <= 1;" +CHECKSUM: "4144234428 2624707494" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.he_rx_rsp_q.even_que +ANNOTATION: " Depends on parameter " +Branch 1 "3108923996" "REG_OUT" (1) "REG_OUT 0,1" +ANNOTATION: " Depends on parameter " +Branch 1 "3108923996" "REG_OUT" (0) "REG_OUT 1,-" +ANNOTATION: " Quartus fifo " +Branch 3 "120570168" "1" (0) "1 ((fifo_ren & fifo_gt_2) & (DEPTH > 1)) " +ANNOTATION: " Quartus fifo " +Branch 6 "2342593151" "(DEPTH > 1)" (1) "(DEPTH > 1) 0" +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (2) "(!Resetb) 0,(fifo_w & (fifo_cntr == (2 ** DEPTH))) ,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (19) "(!Resetb) 0,-,-,-,-,-,1,2'b10 ,-,-,1,-" +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (21) "(!Resetb) 0,-,-,-,-,-,1,2'b11 ,-,-,-,1" +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (22) "(!Resetb) 0,-,-,-,-,-,1,2'b11 ,-,-,-,0" +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (23) "(!Resetb) 0,-,-,-,-,-,1,default,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (1) "(!Resetb) 0,(fifo_ren & (!valid[3])) ,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 0 "2726336106" "REG_IN" (0) "REG_IN 1" +CHECKSUM: "4144234428 2624707494" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.he_rx_rsp_q.odd_que +ANNOTATION: " Quartus fifo " +Branch 9 "3296052676" "(!Resetb)" (21) "(!Resetb) 0,-,-,-,-,-,1,2'b11 ,-,-,-,1" +ANNOTATION: " Quartus fifo " +Branch 9 "3296052676" "(!Resetb)" (22) "(!Resetb) 0,-,-,-,-,-,1,2'b11 ,-,-,-,0" +ANNOTATION: " Quartus fifo " +Branch 9 "3296052676" "(!Resetb)" (23) "(!Resetb) 0,-,-,-,-,-,1,default,-,-,-,-" +ANNOTATION: " Quartus fifo " +Branch 9 "3296052676" "(!Resetb)" (19) "(!Resetb) 0,-,-,-,-,-,1,2'b10 ,-,-,1,-" +ANNOTATION: " Quartus fifo " +Branch 9 "3296052676" "(!Resetb)" (2) "(!Resetb) 0,(fifo_w & (fifo_cntr == (2 ** DEPTH))) ,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Quartus fifo " +Branch 9 "3296052676" "(!Resetb)" (1) "(!Resetb) 0,(fifo_ren & (!valid[3])) ,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Quartus fifo " +Branch 6 "2342593151" "(DEPTH > 1)" (1) "(DEPTH > 1) 0" +ANNOTATION: " Depends on parameter " +Branch 3 "120570168" "1" (0) "1 ((fifo_ren & fifo_gt_2) & (DEPTH > 1)) " +ANNOTATION: " Depends on parameter " +Branch 1 "3108923996" "REG_OUT" (1) "REG_OUT 0,1" +ANNOTATION: " Depends on parameter " +Branch 1 "3108923996" "REG_OUT" (0) "REG_OUT 1,-" +ANNOTATION: " Depends on parameter " +Branch 0 "2726336106" "REG_IN" (0) "REG_IN 1" +CHECKSUM: "4144234428 2624707494" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.he_tx_req_q.even_que +ANNOTATION: " Depends on parameter " +Branch 1 "3108923996" "REG_OUT" (0) "REG_OUT 1,-" +ANNOTATION: " Depends on parameter " +Branch 6 "2342593151" "(DEPTH > 1)" (1) "(DEPTH > 1) 0" +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (2) "(!Resetb) 0,(fifo_w & (fifo_cntr == (2 ** DEPTH))) ,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (23) "(!Resetb) 0,-,-,-,-,-,1,default,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (1) "(!Resetb) 0,(fifo_ren & (!valid[3])) ,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 0 "2726336106" "REG_IN" (0) "REG_IN 1" +CHECKSUM: "4144234428 2624707494" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.he_tx_req_q.odd_que +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (2) "(!Resetb) 0,(fifo_w & (fifo_cntr == (2 ** DEPTH))) ,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (23) "(!Resetb) 0,-,-,-,-,-,1,default,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (1) "(!Resetb) 0,(fifo_ren & (!valid[3])) ,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 1 "3108923996" "REG_OUT" (0) "REG_OUT 1,-" +ANNOTATION: " Depends on parameter " +Branch 6 "2342593151" "(DEPTH > 1)" (1) "(DEPTH > 1) 0" +Branch 0 "2726336106" "REG_IN" (0) "REG_IN 1" +CHECKSUM: "3520213052 1995093083" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.he_rx_rsp_q +Branch 2 "4210727352" "REG_OUT" (1) "REG_OUT 1,0,-,-,-,-,-,-,-,-,-" +Branch 2 "4210727352" "REG_OUT" (2) "REG_OUT 1,-,1,-,-,-,-,-,-,-,-" +Branch 2 "4210727352" "REG_OUT" (3) "REG_OUT 1,-,0,-,-,-,-,-,-,-,-" +Branch 2 "4210727352" "REG_OUT" (0) "REG_OUT 1,1,-,-,-,-,-,-,-,-,-" +Branch 3 "2924126281" "REG_IN" (0) "REG_IN 1,-,-,-,-" +CHECKSUM: "3520213052 1995093083" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.he_tx_req_q +ANNOTATION: " Depends on parameter " +Branch 3 "2924126281" "REG_IN" (2) "REG_IN 0,0,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 3 "2924126281" "REG_IN" (3) "REG_IN 0,-,1,-,-" +ANNOTATION: " Depends on parameter " +Branch 3 "2924126281" "REG_IN" (4) "REG_IN 0,-,0,-,-" +ANNOTATION: " Depends on parameter " +Branch 3 "2924126281" "REG_IN" (5) "REG_IN 0,-,-,1,-" +ANNOTATION: " Depends on parameter " +Branch 3 "2924126281" "REG_IN" (6) "REG_IN 0,-,-,0,-" +ANNOTATION: " Depends on parameter " +Branch 3 "2924126281" "REG_IN" (7) "REG_IN 0,-,-,-,1" +ANNOTATION: " Depends on parameter " +Branch 3 "2924126281" "REG_IN" (8) "REG_IN 0,-,-,-,0" +ANNOTATION: " Depends on parameter " +Branch 3 "2924126281" "REG_IN" (1) "REG_IN 0,1,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 2 "4210727352" "REG_OUT" (1) "REG_OUT 1,0,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 2 "4210727352" "REG_OUT" (2) "REG_OUT 1,-,1,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 2 "4210727352" "REG_OUT" (3) "REG_OUT 1,-,0,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 2 "4210727352" "REG_OUT" (0) "REG_OUT 1,1,-,-,-,-,-,-,-,-,-" +CHECKSUM: "3520213052 2433635046" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.he_rx_rsp_q +Condition 2 "2816528903" "(raddr0[1] ? even_out : odd_out) 1 -1" +Condition 1 "3741229492" "(raddr0[0] ? odd_out : even_out) 1 -1" +CHECKSUM: "3520213052 2433635046" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.he_tx_req_q +Condition 12 "566936974" "(w_odd_even[0] ? ((wen0 & wen1)) : ((wen0 | wen1))) 1 -1" +ANNOTATION: " Depends on parameter " +Condition 13 "2184218986" "(((w_odd_even[1] & wen0)) ? din0 : din1) 1 -1" +Condition 14 "946017004" "(w_odd_even[1] ? ((wen0 | wen1)) : ((wen0 & wen1))) 1 -1" +ANNOTATION: " Depends on parameter " +Condition 11 "1114358066" "((((!w_odd_even[0]) & wen0)) ? din0 : din1) 1 -1" +ANNOTATION: " Depends on parameter " +Condition 2 "2816528903" "(raddr0[1] ? even_out : odd_out) 1 -1" +ANNOTATION: " Depends on parameter " +Condition 1 "3741229492" "(raddr0[0] ? odd_out : even_out) 1 -1" +CHECKSUM: "1772701634 1308845629" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.host_rw.mode_rdwr +ANNOTATION: " Randomized value " +Toggle num_wr "logic num_wr[10:0]" +Toggle 1to0 atomic_req_en "logic atomic_req_en" +Toggle 0to1 atomic_req_en "logic atomic_req_en" +Toggle 1to0 atomic_size "logic atomic_size" +Toggle 0to1 atomic_size "logic atomic_size" +Toggle atomic_func "logic atomic_func[1:0]" +Toggle 1to0 rx_rsp_eop "logic rx_rsp_eop" +Toggle 0to1 rx_rsp_eop "logic rx_rsp_eop" +Toggle 1to0 rx_rsp_sop "logic rx_rsp_sop" +Toggle 0to1 rx_rsp_sop "logic rx_rsp_sop" +Toggle 0to1 ErrorVector [31] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [31] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [5] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [5] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [6] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [6] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [7] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [7] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [8] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [8] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [9] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [9] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [10] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [10] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [11] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [11] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [12] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [12] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [13] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [13] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [14] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [14] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [15] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [15] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [16] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [16] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [17] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [17] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [18] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [18] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [19] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [19] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [20] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [20] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [21] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [21] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [22] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [22] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [23] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [23] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [24] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [24] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [25] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [25] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [26] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [26] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [27] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [27] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [28] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [28] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [29] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [29] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [30] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [30] "logic ErrorVector[31:0]" +Toggle 0to1 error_info [31] "logic error_info[31:0]" +Toggle 1to0 error_info [31] "logic error_info[31:0]" +Toggle 0to1 error_info [5] "logic error_info[31:0]" +Toggle 1to0 error_info [5] "logic error_info[31:0]" +Toggle 0to1 error_info [6] "logic error_info[31:0]" +Toggle 1to0 error_info [6] "logic error_info[31:0]" +Toggle 0to1 error_info [7] "logic error_info[31:0]" +Toggle 1to0 error_info [7] "logic error_info[31:0]" +Toggle 0to1 error_info [8] "logic error_info[31:0]" +Toggle 1to0 error_info [8] "logic error_info[31:0]" +Toggle 0to1 error_info [9] "logic error_info[31:0]" +Toggle 1to0 error_info [9] "logic error_info[31:0]" +Toggle 0to1 error_info [10] "logic error_info[31:0]" +Toggle 1to0 error_info [10] "logic error_info[31:0]" +Toggle 0to1 error_info [11] "logic error_info[31:0]" +Toggle 1to0 error_info [11] "logic error_info[31:0]" +Toggle 0to1 error_info [12] "logic error_info[31:0]" +Toggle 1to0 error_info [12] "logic error_info[31:0]" +Toggle 0to1 error_info [13] "logic error_info[31:0]" +Toggle 1to0 error_info [13] "logic error_info[31:0]" +Toggle 0to1 error_info [14] "logic error_info[31:0]" +Toggle 1to0 error_info [14] "logic error_info[31:0]" +Toggle 0to1 error_info [15] "logic error_info[31:0]" +Toggle 1to0 error_info [15] "logic error_info[31:0]" +Toggle 0to1 error_info [16] "logic error_info[31:0]" +Toggle 1to0 error_info [16] "logic error_info[31:0]" +Toggle 0to1 error_info [17] "logic error_info[31:0]" +Toggle 1to0 error_info [17] "logic error_info[31:0]" +Toggle 0to1 error_info [18] "logic error_info[31:0]" +Toggle 1to0 error_info [18] "logic error_info[31:0]" +Toggle 0to1 error_info [19] "logic error_info[31:0]" +Toggle 1to0 error_info [19] "logic error_info[31:0]" +Toggle 0to1 error_info [20] "logic error_info[31:0]" +Toggle 1to0 error_info [20] "logic error_info[31:0]" +Toggle 0to1 error_info [21] "logic error_info[31:0]" +Toggle 1to0 error_info [21] "logic error_info[31:0]" +Toggle 0to1 error_info [22] "logic error_info[31:0]" +Toggle 1to0 error_info [22] "logic error_info[31:0]" +Toggle 0to1 error_info [23] "logic error_info[31:0]" +Toggle 1to0 error_info [23] "logic error_info[31:0]" +Toggle 0to1 error_info [24] "logic error_info[31:0]" +Toggle 1to0 error_info [24] "logic error_info[31:0]" +Toggle 0to1 error_info [25] "logic error_info[31:0]" +Toggle 1to0 error_info [25] "logic error_info[31:0]" +Toggle 0to1 error_info [26] "logic error_info[31:0]" +Toggle 1to0 error_info [26] "logic error_info[31:0]" +Toggle 0to1 error_info [27] "logic error_info[31:0]" +Toggle 1to0 error_info [27] "logic error_info[31:0]" +Toggle 0to1 error_info [28] "logic error_info[31:0]" +Toggle 1to0 error_info [28] "logic error_info[31:0]" +Toggle 0to1 error_info [29] "logic error_info[31:0]" +Toggle 1to0 error_info [29] "logic error_info[31:0]" +Toggle 0to1 error_info [30] "logic error_info[31:0]" +Toggle 1to0 error_info [30] "logic error_info[31:0]" +ANNOTATION: " Connected to fifo signals " +Toggle tx_req_pld "logic tx_req_pld[511:0]" +ANNOTATION: " Header " +Toggle recent_tx_req_fmttype_p "logic recent_tx_req_fmttype_p[7:0]" +ANNOTATION: " Connected to fifo signals " +Toggle tx_req_dout "logic tx_req_dout[513:0]" +ANNOTATION: " Connected to fifo signals " +Toggle tx_req_din "logic tx_req_din[513:0]" +ANNOTATION: " Connected to fifo signals " +Toggle tx_req_pld_p "logic tx_req_pld_p[511:0]" +ANNOTATION: " Connected to fifo signals " +Toggle tx_req_ecc "logic tx_req_ecc[1:0]" +Toggle 0to1 tx_req_full "logic tx_req_full" +Toggle 1to0 tx_req_full "logic tx_req_full" +Toggle 0to1 tx_req_err "logic tx_req_err" +Toggle 1to0 tx_req_err "logic tx_req_err" +Toggle 0to1 csr2re_cfg [63] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [63] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [7] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [7] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [8] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [8] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [9] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [9] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [10] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [10] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [11] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [11] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [12] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [12] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [13] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [13] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [14] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [14] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [15] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [15] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [16] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [16] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [17] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [17] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [18] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [18] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [19] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [19] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [30] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [30] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [31] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [31] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [32] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [32] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [33] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [33] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [34] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [34] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [35] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [35] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [36] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [36] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [37] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [37] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [38] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [38] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [39] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [39] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [40] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [40] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [41] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [41] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [42] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [42] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [43] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [43] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [44] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [44] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [45] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [45] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [46] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [46] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [47] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [47] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [48] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [48] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [49] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [49] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [50] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [50] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [51] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [51] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [52] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [52] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [53] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [53] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [54] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [54] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [55] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [55] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [56] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [56] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [57] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [57] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [58] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [58] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [59] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [59] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [60] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [60] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [61] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [61] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [62] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [62] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr_cfg [63] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [63] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [7] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [7] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [8] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [8] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [9] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [9] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [10] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [10] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [11] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [11] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [12] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [12] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [13] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [13] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [14] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [14] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [15] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [15] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [16] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [16] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [17] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [17] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [18] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [18] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [19] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [19] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [30] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [30] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [31] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [31] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [32] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [32] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [33] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [33] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [34] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [34] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [35] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [35] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [36] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [36] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [37] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [37] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [38] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [38] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [39] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [39] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [40] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [40] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [41] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [41] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [42] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [42] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [43] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [43] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [44] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [44] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [45] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [45] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [46] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [46] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [47] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [47] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [48] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [48] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [49] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [49] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [50] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [50] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [51] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [51] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [52] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [52] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [53] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [53] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [54] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [54] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [55] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [55] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [56] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [56] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [57] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [57] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [58] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [58] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [59] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [59] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [60] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [60] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [61] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [61] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [62] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [62] "logic csr_cfg[63:0]" +Toggle 0to1 req_len_b2 [4] "logic req_len_b2[4:0]" +Toggle 1to0 req_len_b2 [4] "logic req_len_b2[4:0]" +Toggle 0to1 req_len_b2 [2] "logic req_len_b2[4:0]" +Toggle 1to0 req_len_b2 [2] "logic req_len_b2[4:0]" +Toggle 0to1 req_len_b2 [3] "logic req_len_b2[4:0]" +Toggle 1to0 req_len_b2 [3] "logic req_len_b2[4:0]" +Toggle 1to0 test_complete "logic test_complete" +Toggle 0to1 req_len [4] "logic req_len[4:0]" +Toggle 1to0 req_len [4] "logic req_len[4:0]" +Toggle 1to0 test_started "logic test_started" +Toggle 0to1 tx_req_eot "logic tx_req_eot" +Toggle 1to0 tx_req_eot "logic tx_req_eot" +Toggle 0to1 tx_req_eot_out "logic tx_req_eot_out" +Toggle 1to0 tx_req_eot_out "logic tx_req_eot_out" +Toggle 0to1 error_info [4] "logic error_info[31:0]" +Toggle 1to0 error_info [4] "logic error_info[31:0]" +Toggle 0to1 error_info [0] "logic error_info[31:0]" +Toggle 1to0 error_info [0] "logic error_info[31:0]" +Toggle 0to1 error_info [1] "logic error_info[31:0]" +Toggle 1to0 error_info [1] "logic error_info[31:0]" +Toggle 0to1 error_info [2] "logic error_info[31:0]" +Toggle 1to0 error_info [2] "logic error_info[31:0]" +Toggle 0to1 error_info [3] "logic error_info[31:0]" +Toggle 1to0 error_info [3] "logic error_info[31:0]" +CHECKSUM: "1575787188 1860823143" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.mode_lpbk +ANNOTATION: " Emif is not connected in he_lpbk " +Fsm emif_state "961834838" +CHECKSUM: "1575787188 2328894433" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.mode_lpbk +ANNOTATION: " Does not toggle " +Toggle ram_rad "logic ram_rad[6:0]" +Toggle ram_rad "logic ram_rad[6:0]" +Toggle 1to0 ErrorVector [3] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [3] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [2] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [2] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [1] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [1] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [0] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [0] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [4] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [4] "logic ErrorVector[31:0]" +ANNOTATION: " Does not toggle " +Toggle rd_addr "logic rd_addr[45:0]" +Toggle 1to0 error_info [1] "logic error_info[31:0]" +Toggle 0to1 error_info [1] "logic error_info[31:0]" +Toggle 1to0 error_info [2] "logic error_info[31:0]" +Toggle 0to1 error_info [2] "logic error_info[31:0]" +Toggle 1to0 error_info [3] "logic error_info[31:0]" +Toggle 0to1 error_info [3] "logic error_info[31:0]" +Toggle 1to0 error_info [4] "logic error_info[31:0]" +Toggle 0to1 error_info [4] "logic error_info[31:0]" +Toggle 1to0 error_info [0] "logic error_info[31:0]" +Toggle 0to1 error_info [0] "logic error_info[31:0]" +Toggle 1to0 error_valid "logic error_valid" +Toggle 0to1 error_valid "logic error_valid" +ANNOTATION: " Does not toggle " +Toggle ram_din "logic ram_din[15:0]" +ANNOTATION: " Randomly toggles " +Toggle clnum_ram_dout "logic clnum_ram_dout[15:0]" +ANNOTATION: " Randomly toggles " +Toggle clnum_ram_dout_ram "logic clnum_ram_dout_ram[15:0]" +ANNOTATION: " Randomly toggles " +Toggle clnum_ram_din "logic clnum_ram_din[15:0]" +ANNOTATION: " Randomly toggles " +Toggle clnum_ram_dout_byp "logic clnum_ram_dout_byp[15:0]" +ANNOTATION: " Randomly toggles " +Toggle clnum_ram_dout_byp_d "logic clnum_ram_dout_byp_d[15:0]" +ANNOTATION: " Does not toggle " +Toggle wr_addr "logic wr_addr[45:0]" +Toggle 0to1 ErrorVector [31] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [31] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [5] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [5] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [6] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [6] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [7] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [7] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [8] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [8] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [9] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [9] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [10] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [10] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [11] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [11] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [12] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [12] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [13] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [13] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [14] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [14] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [15] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [15] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [16] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [16] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [17] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [17] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [18] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [18] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [19] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [19] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [20] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [20] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [21] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [21] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [22] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [22] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [23] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [23] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [24] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [24] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [25] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [25] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [26] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [26] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [27] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [27] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [28] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [28] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [29] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [29] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [30] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [30] "logic ErrorVector[31:0]" +ANNOTATION: " Emif is not connected in he_lpbk " +Toggle emif_eop_tracker "logic emif_eop_tracker[2047:0]" +Toggle 0to1 clnum_ram_perr "logic clnum_ram_perr" +Toggle 1to0 clnum_ram_perr "logic clnum_ram_perr" +Toggle 0to1 emif_req_full "logic emif_req_full" +Toggle 1to0 emif_req_full "logic emif_req_full" +Toggle 0to1 emif_req_err "logic emif_req_err" +Toggle 1to0 emif_req_err "logic emif_req_err" +ANNOTATION: " Emif is not connected in he_lpbk " +Toggle emif_req_ecc "logic emif_req_ecc[1:0]" +Toggle 0to1 clnum_ram_ren "logic clnum_ram_ren" +Toggle 1to0 clnum_ram_ren "logic clnum_ram_ren" +ANNOTATION: " Emif is not connected in he_lpbk " +Toggle emif_sop_tracker "logic emif_sop_tracker[2047:0]" +ANNOTATION: " Emif is not connected in he_lpbk " +Toggle emif_readdata_T1 "logic emif_readdata_T1[511:0]" +ANNOTATION: " Emif is not connected in he_lpbk " +Toggle emif_wr_cnt "logic emif_wr_cnt[10:0]" +ANNOTATION: " Emif is not connected in he_lpbk " +Toggle emif_wr_ack_cnt "logic emif_wr_ack_cnt[11:0]" +Toggle 0to1 emif_trk_wen "logic emif_trk_wen" +Toggle 1to0 emif_trk_wen "logic emif_trk_wen" +ANNOTATION: " Emif is not connected in he_lpbk " +Toggle emif_trk_wad "logic emif_trk_wad[10:0]" +Toggle 0to1 emif_trk_rad_co "logic emif_trk_rad_co" +Toggle 1to0 emif_trk_rad_co "logic emif_trk_rad_co" +ANNOTATION: " Emif is not connected in he_lpbk " +Toggle emif_trk_rad "logic emif_trk_rad[10:0]" +ANNOTATION: " Emif is not connected in he_lpbk " +Toggle emif_trk_dout "logic emif_trk_dout[1:0]" +ANNOTATION: " Emif is not connected in he_lpbk " +Toggle emif_trk_din "logic emif_trk_din[1:0]" +ANNOTATION: " Emif is not connected in he_lpbk " +Toggle emif_state "logic emif_state[1:0]" +Toggle 0to1 emif_start "logic emif_start" +Toggle 1to0 emif_start "logic emif_start" +ANNOTATION: " Emif is not connected in he_lpbk " +Toggle emif_rsp_mdata_T1 "logic emif_rsp_mdata_T1[10:0]" +Toggle 0to1 emif_req_wen "logic emif_req_wen" +Toggle 1to0 emif_req_wen "logic emif_req_wen" +Toggle 0to1 emif_req_ren "logic emif_req_ren" +Toggle 1to0 emif_req_ren "logic emif_req_ren" +Toggle 0to1 emif_req_nemp "logic emif_req_nemp" +Toggle 1to0 emif_req_nemp "logic emif_req_nemp" +ANNOTATION: " Emif is not connected in he_lpbk " +Toggle emif_req_dout "logic emif_req_dout[604:0]" +ANNOTATION: " Emif is not connected in he_lpbk " +Toggle emif_req_din "logic emif_req_din[604:0]" +Toggle 0to1 emif_readdatavalid_T1 "logic emif_readdatavalid_T1" +Toggle 1to0 emif_readdatavalid_T1 "logic emif_readdatavalid_T1" +Toggle 0to1 error_info [31] "logic error_info[31:0]" +Toggle 1to0 error_info [31] "logic error_info[31:0]" +Toggle 0to1 error_info [5] "logic error_info[31:0]" +Toggle 1to0 error_info [5] "logic error_info[31:0]" +Toggle 0to1 error_info [6] "logic error_info[31:0]" +Toggle 1to0 error_info [6] "logic error_info[31:0]" +Toggle 0to1 error_info [7] "logic error_info[31:0]" +Toggle 1to0 error_info [7] "logic error_info[31:0]" +Toggle 0to1 error_info [8] "logic error_info[31:0]" +Toggle 1to0 error_info [8] "logic error_info[31:0]" +Toggle 0to1 error_info [9] "logic error_info[31:0]" +Toggle 1to0 error_info [9] "logic error_info[31:0]" +Toggle 0to1 error_info [10] "logic error_info[31:0]" +Toggle 1to0 error_info [10] "logic error_info[31:0]" +Toggle 0to1 error_info [11] "logic error_info[31:0]" +Toggle 1to0 error_info [11] "logic error_info[31:0]" +Toggle 0to1 error_info [12] "logic error_info[31:0]" +Toggle 1to0 error_info [12] "logic error_info[31:0]" +Toggle 0to1 error_info [13] "logic error_info[31:0]" +Toggle 1to0 error_info [13] "logic error_info[31:0]" +Toggle 0to1 error_info [14] "logic error_info[31:0]" +Toggle 1to0 error_info [14] "logic error_info[31:0]" +Toggle 0to1 error_info [15] "logic error_info[31:0]" +Toggle 1to0 error_info [15] "logic error_info[31:0]" +Toggle 0to1 error_info [16] "logic error_info[31:0]" +Toggle 1to0 error_info [16] "logic error_info[31:0]" +Toggle 0to1 error_info [17] "logic error_info[31:0]" +Toggle 1to0 error_info [17] "logic error_info[31:0]" +Toggle 0to1 error_info [18] "logic error_info[31:0]" +Toggle 1to0 error_info [18] "logic error_info[31:0]" +Toggle 0to1 error_info [19] "logic error_info[31:0]" +Toggle 1to0 error_info [19] "logic error_info[31:0]" +Toggle 0to1 error_info [20] "logic error_info[31:0]" +Toggle 1to0 error_info [20] "logic error_info[31:0]" +Toggle 0to1 error_info [21] "logic error_info[31:0]" +Toggle 1to0 error_info [21] "logic error_info[31:0]" +Toggle 0to1 error_info [22] "logic error_info[31:0]" +Toggle 1to0 error_info [22] "logic error_info[31:0]" +Toggle 0to1 error_info [23] "logic error_info[31:0]" +Toggle 1to0 error_info [23] "logic error_info[31:0]" +Toggle 0to1 error_info [24] "logic error_info[31:0]" +Toggle 1to0 error_info [24] "logic error_info[31:0]" +Toggle 0to1 error_info [25] "logic error_info[31:0]" +Toggle 1to0 error_info [25] "logic error_info[31:0]" +Toggle 0to1 error_info [26] "logic error_info[31:0]" +Toggle 1to0 error_info [26] "logic error_info[31:0]" +Toggle 0to1 error_info [27] "logic error_info[31:0]" +Toggle 1to0 error_info [27] "logic error_info[31:0]" +Toggle 0to1 error_info [28] "logic error_info[31:0]" +Toggle 1to0 error_info [28] "logic error_info[31:0]" +Toggle 0to1 error_info [29] "logic error_info[31:0]" +Toggle 1to0 error_info [29] "logic error_info[31:0]" +Toggle 0to1 error_info [30] "logic error_info[31:0]" +Toggle 1to0 error_info [30] "logic error_info[31:0]" +ANNOTATION: " Does not toggle " +Toggle rx_rsp_ecc "logic rx_rsp_ecc[1:0]" +Toggle 0to1 tx_req_full "logic tx_req_full" +Toggle 1to0 tx_req_full "logic tx_req_full" +Toggle 0to1 tx_req_err "logic tx_req_err" +Toggle 1to0 tx_req_err "logic tx_req_err" +ANNOTATION: " Does not toggle " +Toggle tx_req_ecc "logic tx_req_ecc[1:0]" +Toggle 0to1 rx_rsp_ready "logic rx_rsp_ready" +Toggle 1to0 rx_rsp_ready "logic rx_rsp_ready" +Toggle 0to1 rx_rsp_full "logic rx_rsp_full" +Toggle 1to0 rx_rsp_full "logic rx_rsp_full" +Toggle 0to1 rx_rsp_err "logic rx_rsp_err" +Toggle 1to0 rx_rsp_err "logic rx_rsp_err" +Toggle 0to1 csr2re_cfg [63] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [63] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [7] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [7] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [8] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [8] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [9] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [9] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [10] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [10] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [11] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [11] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [12] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [12] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [13] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [13] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [14] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [14] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [15] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [15] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [16] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [16] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [17] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [17] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [18] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [18] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [19] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [19] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [30] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [30] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [31] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [31] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [32] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [32] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [33] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [33] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [34] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [34] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [35] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [35] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [36] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [36] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [37] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [37] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [38] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [38] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [39] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [39] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [40] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [40] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [41] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [41] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [42] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [42] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [43] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [43] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [44] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [44] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [45] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [45] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [46] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [46] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [47] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [47] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [48] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [48] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [49] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [49] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [50] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [50] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [51] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [51] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [52] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [52] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [53] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [53] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [54] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [54] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [55] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [55] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [56] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [56] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [57] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [57] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [58] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [58] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [59] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [59] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [60] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [60] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [61] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [61] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [62] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [62] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr_cfg [63] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [63] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [7] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [7] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [8] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [8] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [9] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [9] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [10] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [10] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [11] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [11] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [12] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [12] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [13] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [13] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [14] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [14] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [15] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [15] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [16] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [16] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [17] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [17] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [18] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [18] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [19] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [19] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [30] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [30] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [31] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [31] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [32] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [32] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [33] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [33] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [34] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [34] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [35] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [35] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [36] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [36] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [37] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [37] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [38] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [38] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [39] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [39] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [40] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [40] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [41] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [41] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [42] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [42] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [43] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [43] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [44] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [44] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [45] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [45] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [46] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [46] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [47] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [47] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [48] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [48] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [49] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [49] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [50] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [50] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [51] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [51] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [52] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [52] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [53] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [53] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [54] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [54] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [55] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [55] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [56] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [56] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [57] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [57] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [58] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [58] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [59] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [59] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [60] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [60] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [61] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [61] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [62] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [62] "logic csr_cfg[63:0]" +ANNOTATION: " Does not toggle " +Toggle recent_fmttype "logic recent_fmttype[7:0]" +Toggle 0to1 tx_req_eot "logic tx_req_eot" +Toggle 1to0 tx_req_eot "logic tx_req_eot" +Toggle 0to1 tx_req_eot_out "logic tx_req_eot_out" +Toggle 1to0 tx_req_eot_out "logic tx_req_eot_out" +Toggle 0to1 req_len_b2 [4] "logic req_len_b2[4:0]" +Toggle 1to0 req_len_b2 [4] "logic req_len_b2[4:0]" +Toggle 0to1 req_len_b2 [2] "logic req_len_b2[4:0]" +Toggle 1to0 req_len_b2 [2] "logic req_len_b2[4:0]" +Toggle 0to1 req_len_b2 [3] "logic req_len_b2[4:0]" +Toggle 1to0 req_len_b2 [3] "logic req_len_b2[4:0]" +Toggle 0to1 req_len [4] "logic req_len[4:0]" +Toggle 1to0 req_len [4] "logic req_len[4:0]" +CHECKSUM: "4144234428 3046614582" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.he_rx_rsp_q.even_que +Block 2 "2974956466" "fifo_in = fifo_din_q;" +Block 70 "1663007339" ";" +Block 68 "3454825183" "fifo_gt_2 <= 0;" +Block 67 "248473116" "if (((!fifo_w) & fifo_ren))" +Block 65 "3781602218" "fifo_gt_2 <= 1'b1;" +Block 64 "1101485692" "if ((fifo_w & (!fifo_ren)))" +Block 39 "189190586" "fifo_err <= 1'b1;" +Block 38 "2294665107" "fifo_err <= 1'b1;" +Block 13 "726338920" "fifo_out = ram_out;" +Block 7 "308262062" "fifo_dout = ram_out_q;" +Block 6 "2186128943" "if (fifo_dout_sel)" +Block 5 "3868310358" "fifo_dout = fifo_out_q;" +CHECKSUM: "4144234428 3046614582" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.he_rx_rsp_q.odd_que +Block 2 "2974956466" "fifo_in = fifo_din_q;" +Block 70 "1663007339" ";" +Block 68 "3454825183" "fifo_gt_2 <= 0;" +Block 67 "248473116" "if (((!fifo_w) & fifo_ren))" +Block 65 "3781602218" "fifo_gt_2 <= 1'b1;" +Block 64 "1101485692" "if ((fifo_w & (!fifo_ren)))" +Block 39 "189190586" "fifo_err <= 1'b1;" +Block 38 "2294665107" "fifo_err <= 1'b1;" +Block 13 "726338920" "fifo_out = ram_out;" +Block 7 "308262062" "fifo_dout = ram_out_q;" +Block 6 "2186128943" "if (fifo_dout_sel)" +Block 5 "3868310358" "fifo_dout = fifo_out_q;" +CHECKSUM: "4144234428 3046614582" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.he_tx_req_q.even_que +Block 2 "2974956466" "fifo_in = fifo_din_q;" +Block 5 "3868310358" "fifo_dout = fifo_out_q;" +Block 38 "2294665107" "fifo_err <= 1'b1;" +Block 39 "189190586" "fifo_err <= 1'b1;" +Block 70 "1663007339" ";" +CHECKSUM: "4144234428 3046614582" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.he_tx_req_q.odd_que +Block 2 "2974956466" "fifo_in = fifo_din_q;" +Block 39 "189190586" "fifo_err <= 1'b1;" +Block 38 "2294665107" "fifo_err <= 1'b1;" +Block 5 "3868310358" "fifo_dout = fifo_out_q;" +Block 70 "1663007339" ";" +CHECKSUM: "3589944323 3241579962" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.he_rx_rsp_q.even_que.fifo_ram.genblk2.inst_gram_sdp +Toggle ram_dout "reg ram_dout[259:0]" +Toggle raddr_q "reg raddr_q[2:0]" +CHECKSUM: "3589944323 3241579962" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.he_rx_rsp_q.odd_que.fifo_ram.genblk2.inst_gram_sdp +Toggle ram_dout "reg ram_dout[259:0]" +Toggle raddr_q "reg raddr_q[2:0]" +CHECKSUM: "3589944323 262393654" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.he_tx_req_q.even_que.fifo_ram.genblk2.inst_gram_sdp +Toggle ram_dout "reg ram_dout[259:0]" +Toggle raddr_q "reg raddr_q[3:0]" +CHECKSUM: "3589944323 262393654" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.he_tx_req_q.odd_que.fifo_ram.genblk2.inst_gram_sdp +Toggle ram_dout "reg ram_dout[259:0]" +Toggle raddr_q "reg raddr_q[3:0]" +CHECKSUM: "3697671760 3623767598" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst +ANNOTATION: " Errors are not generated " +Branch 3 "2662216083" "(axi_tx_if.tvalid & (axi_tx_if.tdata === 'x))" (1) "(axi_tx_if.tvalid & (axi_tx_if.tdata === 'x)) 0,1,-,-" +ANNOTATION: " Errors are not generated " +Branch 3 "2662216083" "(axi_tx_if.tvalid & (axi_tx_if.tdata === 'x))" (2) "(axi_tx_if.tvalid & (axi_tx_if.tdata === 'x)) 0,0,1,-" +ANNOTATION: " Errors are not generated " +Branch 3 "2662216083" "(axi_tx_if.tvalid & (axi_tx_if.tdata === 'x))" (3) "(axi_tx_if.tvalid & (axi_tx_if.tdata === 'x)) 0,0,0,1" +ANNOTATION: " Errors are not generated " +Branch 3 "2662216083" "(axi_tx_if.tvalid & (axi_tx_if.tdata === 'x))" (0) "(axi_tx_if.tvalid & (axi_tx_if.tdata === 'x)) 1,-,-,-" +ANNOTATION: " Errors are not generated " +Branch 4 "3409136147" "(axi_rx_if.tvalid & (axi_rx_if.tdata === 'x))" (1) "(axi_rx_if.tvalid & (axi_rx_if.tdata === 'x)) 0,1,-,-" +ANNOTATION: " Errors are not generated " +Branch 4 "3409136147" "(axi_rx_if.tvalid & (axi_rx_if.tdata === 'x))" (2) "(axi_rx_if.tvalid & (axi_rx_if.tdata === 'x)) 0,0,1,-" +ANNOTATION: " Errors are not generated " +Branch 4 "3409136147" "(axi_rx_if.tvalid & (axi_rx_if.tdata === 'x))" (3) "(axi_rx_if.tvalid & (axi_rx_if.tdata === 'x)) 0,0,0,1" +ANNOTATION: " Errors are not generated " +Branch 4 "3409136147" "(axi_rx_if.tvalid & (axi_rx_if.tdata === 'x))" (0) "(axi_rx_if.tvalid & (axi_rx_if.tdata === 'x)) 1,-,-,-" +ANNOTATION: " Errors are not generated " +Branch 2 "2688943399" "(!test_resetb)" (3) "(!test_resetb) 0,-,1" +ANNOTATION: " Errors are not generated " +Branch 2 "2688943399" "(!test_resetb)" (1) "(!test_resetb) 0,1,-" +CHECKSUM: "1772701634 3333002143" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.host_rw.mode_rdwr +Branch 16 "2459171571" "(|ErrorVector)" (0) "(|ErrorVector) 1" +Branch 15 "1946039810" "(test_start & (total_len == 11'b0))" (0) "(test_start & (total_len == 11'b0)) 1" +Branch 14 "1239589818" "(test_start & ((total_len % req_len) != 0))" (0) "(test_start & ((total_len % req_len) != 0)) 1" +Branch 13 "1083443347" "(!test_resetb)" (1) "(!test_resetb) 0,1" +CHECKSUM: "1575787188 369815844" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.mode_lpbk +ANNOTATION: " Errors are not generated " +Branch 21 "1239589818" "(test_start & ((total_len % req_len) != 0))" (0) "(test_start & ((total_len % req_len) != 0)) 1" +ANNOTATION: " Errors are not generated " +Branch 22 "1006867801" "(tx_req_valid & $isunknown({tx_req_sop, tx_req_eop, tx_req_pld}))" (0) "(tx_req_valid & $isunknown({tx_req_sop, tx_req_eop, tx_req_pld})) 1" +ANNOTATION: " Errors are not generated " +Branch 23 "1534404760" "(rx_rsp_valid & $isunknown({rx_rsp_sop, rx_rsp_eop, rx_rsp_pld}))" (0) "(rx_rsp_valid & $isunknown({rx_rsp_sop, rx_rsp_eop, rx_rsp_pld})) 1" +ANNOTATION: " Errors are not generated " +Branch 24 "2459171571" "(|ErrorVector)" (0) "(|ErrorVector) 1" +ANNOTATION: " Errors are not generated " +Branch 20 "3335143965" "(!test_resetb_q)" (3) "(!test_resetb_q) 0,-,1,-,-" +ANNOTATION: " Errors are not generated " +Branch 20 "3335143965" "(!test_resetb_q)" (5) "(!test_resetb_q) 0,-,-,1,-" +ANNOTATION: " Errors are not generated " +Branch 20 "3335143965" "(!test_resetb_q)" (7) "(!test_resetb_q) 0,-,-,-,1" +ANNOTATION: " Errors are not generated " +Branch 20 "3335143965" "(!test_resetb_q)" (1) "(!test_resetb_q) 0,1,-,-,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 12 "2557750059" "(emif_state == EMIF_IDLE)" (0) "(emif_state == EMIF_IDLE) 1" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (10) "(EMIF == 0) 0,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (11) "(EMIF == 0) 0,-,-,-,-,-,-,1,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (12) "(EMIF == 0) 0,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (13) "(EMIF == 0) 0,-,-,-,-,-,-,-,EMIF_IDLE ,1,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (14) "(EMIF == 0) 0,-,-,-,-,-,-,-,EMIF_IDLE ,0,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (15) "(EMIF == 0) 0,-,-,-,-,-,-,-,EMIF_IDLE ,-,1,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (16) "(EMIF == 0) 0,-,-,-,-,-,-,-,EMIF_IDLE ,-,0,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (17) "(EMIF == 0) 0,-,-,-,-,-,-,-,EMIF_WRITE ,-,-,1,-,-,-,-,-,-,-,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (18) "(EMIF == 0) 0,-,-,-,-,-,-,-,EMIF_WRITE ,-,-,0,-,-,-,-,-,-,-,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (19) "(EMIF == 0) 0,-,-,-,-,-,-,-,EMIF_WRITE ,-,-,-,1,-,-,-,-,-,-,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (20) "(EMIF == 0) 0,-,-,-,-,-,-,-,EMIF_WRITE ,-,-,-,0,-,-,-,-,-,-,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (21) "(EMIF == 0) 0,-,-,-,-,-,-,-,EMIF_READ ,-,-,-,-,1,1,-,-,-,-,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (22) "(EMIF == 0) 0,-,-,-,-,-,-,-,EMIF_READ ,-,-,-,-,1,0,-,-,-,-,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (23) "(EMIF == 0) 0,-,-,-,-,-,-,-,EMIF_READ ,-,-,-,-,0,-,-,-,-,-,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (24) "(EMIF == 0) 0,-,-,-,-,-,-,-,EMIF_READ_RSP ,-,-,-,-,-,-,1,-,-,-,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (25) "(EMIF == 0) 0,-,-,-,-,-,-,-,EMIF_READ_RSP ,-,-,-,-,-,-,0,-,-,-,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (26) "(EMIF == 0) 0,-,-,-,-,-,-,-,default,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (27) "(EMIF == 0) 0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,-,-,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (28) "(EMIF == 0) 0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (29) "(EMIF == 0) 0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,-,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (30) "(EMIF == 0) 0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,1,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (31) "(EMIF == 0) 0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,0,-" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (32) "(EMIF == 0) 0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (33) "(EMIF == 0) 0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0" +ANNOTATION: " Emif is not connected in he_lpbk " +Branch 11 "2535442213" "(EMIF == 0)" (9) "(EMIF == 0) 0,-,-,-,-,-,1,-,-,-,-,-,-,-,-,-,-,-,-,-" +CHECKSUM: "1259019545 1064430290" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.axi_rx_stage_1 +Toggle genblk1.m_tdest_pre "reg genblk1.m_tdest_pre[7:0]" +Toggle s_tid "net s_tid[7:0]" +Toggle s_tdest "net s_tdest[7:0]" +Toggle m_tid "net m_tid[7:0]" +Toggle genblk1.s_tid_reg "reg genblk1.s_tid_reg[7:0]" +Toggle genblk1.s_tdest_reg "reg genblk1.s_tdest_reg[7:0]" +Toggle genblk1.m_tid_reg "reg genblk1.m_tid_reg[7:0]" +Toggle genblk1.m_tid_pre "reg genblk1.m_tid_pre[7:0]" +Toggle genblk1.m_tdest_reg "reg genblk1.m_tdest_reg[7:0]" +Toggle 0to1 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 m_tuser [9] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [9] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [1] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [1] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [2] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [2] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [3] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [3] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [4] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [4] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [5] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [5] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [6] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [6] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [7] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [7] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [8] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [8] "net m_tuser[9:0]" +Toggle 0to1 s_tuser [9] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [9] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [1] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [1] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [2] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [2] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [3] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [3] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [4] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [4] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [5] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [5] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [6] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [6] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [7] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [7] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [8] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [8] "net s_tuser[9:0]" +Toggle 0to1 genblk1.m_tkeep_pre [31] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [31] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [0] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [0] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [1] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [1] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [2] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [2] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [3] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [3] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [4] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [4] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [5] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [5] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [6] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [6] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [7] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [7] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [8] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [8] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [9] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [9] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [10] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [10] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [11] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [11] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [12] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [12] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [13] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [13] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [14] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [14] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [15] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [15] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [16] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [16] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [17] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [17] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [18] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [18] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [19] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [19] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [20] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [20] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [21] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [21] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [22] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [22] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [23] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [23] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [24] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [24] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [25] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [25] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [26] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [26] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [27] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [27] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [28] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [28] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [29] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [29] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [30] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [30] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [31] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [31] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [0] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [0] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [1] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [1] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [2] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [2] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [3] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [3] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [4] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [4] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [5] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [5] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [6] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [6] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [7] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [7] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [8] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [8] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [9] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [9] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [10] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [10] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [11] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [11] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [12] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [12] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [13] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [13] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [14] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [14] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [15] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [15] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [16] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [16] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [17] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [17] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [18] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [18] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [19] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [19] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [20] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [20] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [21] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [21] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [22] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [22] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [23] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [23] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [24] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [24] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [25] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [25] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [26] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [26] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [27] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [27] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [28] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [28] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [29] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [29] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [30] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [30] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [31] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [31] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [0] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [0] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [1] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [1] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [2] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [2] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [3] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [3] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [4] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [4] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [5] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [5] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [6] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [6] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [7] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [7] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [8] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [8] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [9] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [9] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [10] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [10] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [11] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [11] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [12] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [12] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [13] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [13] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [14] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [14] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [15] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [15] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [16] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [16] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [17] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [17] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [18] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [18] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [19] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [19] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [20] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [20] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [21] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [21] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [22] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [22] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [23] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [23] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [24] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [24] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [25] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [25] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [26] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [26] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [27] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [27] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [28] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [28] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [29] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [29] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [30] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [30] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 m_tkeep [31] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [31] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [0] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [0] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [1] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [1] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [2] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [2] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [3] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [3] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [4] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [4] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [5] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [5] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [6] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [6] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [7] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [7] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [8] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [8] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [9] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [9] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [10] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [10] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [11] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [11] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [12] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [12] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [13] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [13] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [14] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [14] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [15] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [15] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [16] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [16] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [17] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [17] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [18] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [18] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [19] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [19] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [20] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [20] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [21] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [21] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [22] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [22] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [23] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [23] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [24] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [24] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [25] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [25] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [26] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [26] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [27] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [27] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [28] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [28] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [29] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [29] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [30] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [30] "net m_tkeep[63:0]" +Toggle 0to1 s_tkeep [31] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [31] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [0] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [0] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [1] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [1] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [2] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [2] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [3] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [3] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [4] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [4] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [5] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [5] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [6] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [6] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [7] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [7] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [8] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [8] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [9] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [9] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [10] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [10] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [11] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [11] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [12] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [12] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [13] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [13] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [14] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [14] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [15] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [15] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [16] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [16] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [17] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [17] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [18] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [18] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [19] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [19] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [20] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [20] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [21] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [21] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [22] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [22] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [23] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [23] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [24] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [24] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [25] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [25] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [26] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [26] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [27] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [27] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [28] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [28] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [29] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [29] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [30] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [30] "net s_tkeep[63:0]" +CHECKSUM: "1259019545 1064430290" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.axi_rx_stage_2 +Toggle genblk1.m_tdest_pre "reg genblk1.m_tdest_pre[7:0]" +Toggle s_tid "net s_tid[7:0]" +Toggle s_tdest "net s_tdest[7:0]" +Toggle m_tid "net m_tid[7:0]" +Toggle genblk1.s_tid_reg "reg genblk1.s_tid_reg[7:0]" +Toggle genblk1.s_tdest_reg "reg genblk1.s_tdest_reg[7:0]" +Toggle genblk1.m_tid_reg "reg genblk1.m_tid_reg[7:0]" +Toggle genblk1.m_tid_pre "reg genblk1.m_tid_pre[7:0]" +Toggle genblk1.m_tdest_reg "reg genblk1.m_tdest_reg[7:0]" +Toggle 0to1 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 s_tuser [9] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [9] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [1] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [1] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [2] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [2] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [3] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [3] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [4] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [4] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [5] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [5] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [6] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [6] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [7] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [7] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [8] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [8] "net s_tuser[9:0]" +Toggle 0to1 m_tuser [9] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [9] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [1] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [1] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [2] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [2] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [3] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [3] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [4] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [4] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [5] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [5] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [6] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [6] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [7] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [7] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [8] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [8] "net m_tuser[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tkeep_pre [31] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [31] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [0] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [0] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [1] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [1] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [2] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [2] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [3] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [3] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [4] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [4] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [5] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [5] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [6] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [6] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [7] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [7] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [8] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [8] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [9] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [9] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [10] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [10] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [11] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [11] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [12] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [12] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [13] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [13] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [14] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [14] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [15] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [15] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [16] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [16] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [17] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [17] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [18] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [18] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [19] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [19] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [20] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [20] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [21] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [21] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [22] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [22] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [23] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [23] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [24] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [24] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [25] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [25] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [26] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [26] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [27] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [27] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [28] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [28] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [29] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [29] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [30] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [30] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [31] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [31] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [0] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [0] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [1] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [1] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [2] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [2] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [3] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [3] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [4] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [4] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [5] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [5] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [6] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [6] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [7] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [7] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [8] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [8] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [9] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [9] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [10] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [10] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [11] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [11] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [12] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [12] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [13] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [13] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [14] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [14] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [15] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [15] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [16] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [16] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [17] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [17] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [18] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [18] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [19] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [19] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [20] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [20] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [21] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [21] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [22] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [22] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [23] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [23] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [24] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [24] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [25] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [25] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [26] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [26] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [27] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [27] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [28] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [28] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [29] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [29] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [30] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [30] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [31] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [31] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [0] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [0] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [1] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [1] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [2] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [2] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [3] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [3] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [4] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [4] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [5] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [5] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [6] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [6] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [7] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [7] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [8] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [8] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [9] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [9] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [10] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [10] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [11] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [11] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [12] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [12] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [13] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [13] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [14] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [14] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [15] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [15] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [16] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [16] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [17] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [17] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [18] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [18] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [19] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [19] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [20] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [20] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [21] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [21] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [22] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [22] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [23] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [23] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [24] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [24] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [25] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [25] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [26] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [26] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [27] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [27] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [28] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [28] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [29] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [29] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [30] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [30] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 m_tkeep [31] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [31] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [0] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [0] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [1] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [1] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [2] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [2] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [3] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [3] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [4] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [4] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [5] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [5] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [6] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [6] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [7] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [7] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [8] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [8] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [9] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [9] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [10] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [10] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [11] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [11] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [12] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [12] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [13] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [13] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [14] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [14] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [15] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [15] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [16] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [16] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [17] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [17] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [18] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [18] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [19] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [19] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [20] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [20] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [21] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [21] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [22] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [22] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [23] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [23] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [24] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [24] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [25] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [25] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [26] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [26] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [27] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [27] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [28] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [28] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [29] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [29] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [30] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [30] "net m_tkeep[63:0]" +Toggle 0to1 s_tkeep [31] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [31] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [0] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [0] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [1] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [1] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [2] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [2] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [3] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [3] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [4] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [4] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [5] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [5] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [6] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [6] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [7] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [7] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [8] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [8] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [9] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [9] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [10] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [10] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [11] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [11] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [12] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [12] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [13] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [13] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [14] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [14] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [15] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [15] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [16] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [16] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [17] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [17] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [18] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [18] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [19] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [19] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [20] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [20] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [21] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [21] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [22] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [22] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [23] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [23] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [24] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [24] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [25] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [25] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [26] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [26] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [27] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [27] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [28] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [28] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [29] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [29] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [30] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [30] "net s_tkeep[63:0]" +CHECKSUM: "1259019545 1064430290" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.axi_tx_stage_1 +Toggle genblk1.m_tdest_pre "reg genblk1.m_tdest_pre[7:0]" +Toggle s_tid "net s_tid[7:0]" +Toggle s_tdest "net s_tdest[7:0]" +Toggle m_tid "net m_tid[7:0]" +Toggle genblk1.s_tid_reg "reg genblk1.s_tid_reg[7:0]" +Toggle genblk1.s_tdest_reg "reg genblk1.s_tdest_reg[7:0]" +Toggle genblk1.m_tid_reg "reg genblk1.m_tid_reg[7:0]" +Toggle genblk1.m_tid_pre "reg genblk1.m_tid_pre[7:0]" +Toggle genblk1.m_tdest_reg "reg genblk1.m_tdest_reg[7:0]" +Toggle 0to1 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 s_tuser [9] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [9] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [1] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [1] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [2] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [2] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [3] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [3] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [4] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [4] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [5] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [5] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [6] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [6] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [7] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [7] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [8] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [8] "net s_tuser[9:0]" +Toggle 0to1 m_tuser [9] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [9] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [1] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [1] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [2] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [2] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [3] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [3] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [4] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [4] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [5] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [5] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [6] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [6] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [7] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [7] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [8] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [8] "net m_tuser[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 m_tkeep [31] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [31] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [0] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [0] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [1] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [1] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [2] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [2] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [3] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [3] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [4] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [4] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [5] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [5] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [6] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [6] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [7] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [7] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [8] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [8] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [9] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [9] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [10] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [10] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [11] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [11] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [12] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [12] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [13] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [13] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [14] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [14] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [15] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [15] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [16] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [16] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [17] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [17] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [18] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [18] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [19] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [19] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [20] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [20] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [21] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [21] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [22] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [22] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [23] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [23] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [24] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [24] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [25] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [25] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [26] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [26] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [27] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [27] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [28] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [28] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [29] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [29] "net m_tkeep[63:0]" +Toggle 0to1 m_tkeep [30] "net m_tkeep[63:0]" +Toggle 1to0 m_tkeep [30] "net m_tkeep[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [31] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [31] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [0] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [0] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [1] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [1] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [2] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [2] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [3] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [3] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [4] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [4] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [5] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [5] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [6] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [6] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [7] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [7] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [8] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [8] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [9] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [9] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [10] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [10] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [11] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [11] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [12] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [12] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [13] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [13] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [14] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [14] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [15] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [15] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [16] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [16] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [17] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [17] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [18] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [18] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [19] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [19] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [20] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [20] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [21] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [21] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [22] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [22] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [23] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [23] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [24] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [24] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [25] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [25] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [26] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [26] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [27] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [27] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [28] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [28] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [29] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [29] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_pre [30] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 1to0 genblk1.m_tkeep_pre [30] "reg genblk1.m_tkeep_pre[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [31] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [31] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [0] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [0] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [1] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [1] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [2] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [2] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [3] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [3] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [4] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [4] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [5] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [5] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [6] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [6] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [7] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [7] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [8] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [8] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [9] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [9] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [10] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [10] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [11] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [11] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [12] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [12] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [13] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [13] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [14] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [14] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [15] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [15] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [16] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [16] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [17] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [17] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [18] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [18] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [19] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [19] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [20] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [20] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [21] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [21] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [22] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [22] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [23] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [23] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [24] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [24] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [25] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [25] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [26] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [26] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [27] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [27] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [28] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [28] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [29] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [29] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tkeep_reg [30] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tkeep_reg [30] "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [31] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [31] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [0] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [0] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [1] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [1] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [2] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [2] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [3] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [3] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [4] "reg genblk1.s_tkeep_reg[63:0]" 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genblk1.s_tkeep_reg [11] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [12] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [12] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [13] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [13] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [14] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [14] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [15] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [15] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [16] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [16] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [17] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [17] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [18] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [18] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [19] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [19] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [20] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [20] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [21] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [21] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [22] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [22] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [23] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [23] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [24] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [24] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [25] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [25] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [26] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [26] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [27] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [27] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [28] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [28] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [29] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [29] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tkeep_reg [30] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.s_tkeep_reg [30] "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 s_tkeep [31] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [31] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [0] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [0] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [1] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [1] "net s_tkeep[63:0]" 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s_tkeep[63:0]" +Toggle 0to1 s_tkeep [24] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [24] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [25] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [25] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [26] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [26] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [27] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [27] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [28] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [28] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [29] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [29] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [30] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [30] "net s_tkeep[63:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.axi_rx_if_T1 +Toggle 1to0 tkeep [30] "logic tkeep[63:0]" +Toggle 0to1 tkeep [30] "logic tkeep[63:0]" +Toggle 1to0 tkeep [29] "logic tkeep[63:0]" +Toggle 0to1 tkeep [29] "logic tkeep[63:0]" +Toggle 1to0 tkeep [28] "logic tkeep[63:0]" +Toggle 0to1 tkeep [28] "logic tkeep[63:0]" +Toggle 1to0 tkeep [27] "logic tkeep[63:0]" +Toggle 0to1 tkeep [27] "logic tkeep[63:0]" +Toggle 1to0 tkeep [26] "logic tkeep[63:0]" +Toggle 0to1 tkeep [26] "logic tkeep[63:0]" +Toggle 1to0 tkeep [25] "logic tkeep[63:0]" +Toggle 0to1 tkeep [25] "logic tkeep[63:0]" +Toggle 1to0 tkeep [24] "logic tkeep[63:0]" +Toggle 0to1 tkeep [24] "logic tkeep[63:0]" +Toggle 1to0 tkeep [23] "logic tkeep[63:0]" +Toggle 0to1 tkeep [23] "logic tkeep[63:0]" +Toggle 1to0 tkeep [22] "logic tkeep[63:0]" +Toggle 0to1 tkeep [22] "logic tkeep[63:0]" +Toggle 1to0 tkeep [21] "logic tkeep[63:0]" +Toggle 0to1 tkeep [21] "logic tkeep[63:0]" +Toggle 1to0 tkeep [20] "logic tkeep[63:0]" +Toggle 0to1 tkeep [20] "logic tkeep[63:0]" +Toggle 1to0 tkeep [19] "logic tkeep[63:0]" +Toggle 0to1 tkeep [19] "logic tkeep[63:0]" +Toggle 1to0 tkeep [18] "logic tkeep[63:0]" +Toggle 0to1 tkeep [18] "logic tkeep[63:0]" +Toggle 1to0 tkeep [17] "logic tkeep[63:0]" +Toggle 0to1 tkeep [17] "logic tkeep[63:0]" +Toggle 1to0 tkeep [16] "logic tkeep[63:0]" +Toggle 0to1 tkeep [16] "logic tkeep[63:0]" +Toggle 1to0 tkeep [15] "logic tkeep[63:0]" +Toggle 0to1 tkeep [15] "logic tkeep[63:0]" +Toggle 1to0 tkeep [14] "logic tkeep[63:0]" +Toggle 0to1 tkeep [14] "logic tkeep[63:0]" +Toggle 1to0 tkeep [13] "logic tkeep[63:0]" +Toggle 0to1 tkeep [13] "logic tkeep[63:0]" +Toggle 1to0 tkeep [12] "logic tkeep[63:0]" +Toggle 0to1 tkeep [12] "logic tkeep[63:0]" +Toggle 1to0 tkeep [11] "logic tkeep[63:0]" +Toggle 0to1 tkeep [11] "logic tkeep[63:0]" +Toggle 1to0 tkeep [10] "logic tkeep[63:0]" +Toggle 0to1 tkeep [10] "logic tkeep[63:0]" +Toggle 1to0 tkeep [9] "logic tkeep[63:0]" +Toggle 0to1 tkeep [9] "logic tkeep[63:0]" +Toggle 1to0 tkeep [8] "logic tkeep[63:0]" +Toggle 0to1 tkeep [8] "logic tkeep[63:0]" +Toggle 1to0 tkeep [7] "logic tkeep[63:0]" +Toggle 0to1 tkeep [7] "logic tkeep[63:0]" +Toggle 1to0 tkeep [6] "logic tkeep[63:0]" +Toggle 0to1 tkeep [6] "logic tkeep[63:0]" +Toggle 1to0 tkeep [5] "logic tkeep[63:0]" +Toggle 0to1 tkeep [5] "logic tkeep[63:0]" +Toggle 1to0 tkeep [4] "logic tkeep[63:0]" +Toggle 0to1 tkeep [4] "logic tkeep[63:0]" +Toggle 1to0 tkeep [3] "logic tkeep[63:0]" +Toggle 0to1 tkeep [3] "logic tkeep[63:0]" +Toggle 1to0 tkeep [2] "logic tkeep[63:0]" +Toggle 0to1 tkeep [2] "logic tkeep[63:0]" +Toggle 1to0 tkeep [1] "logic tkeep[63:0]" +Toggle 0to1 tkeep [1] "logic tkeep[63:0]" +Toggle 1to0 tkeep [0] "logic tkeep[63:0]" +Toggle 0to1 tkeep [0] "logic tkeep[63:0]" +Toggle 1to0 tkeep [31] "logic tkeep[63:0]" +Toggle 0to1 tkeep [31] "logic tkeep[63:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "3814588975 2678712067" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_csr +Toggle 1to0 csr2re_ctl [2] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_dsm_base [62] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [62] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [61] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [61] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [60] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [60] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [59] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [59] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [58] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [58] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [57] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [57] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [56] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [56] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [55] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [55] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [54] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [54] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [53] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [53] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [52] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [52] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [51] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [51] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [50] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [50] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [49] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [49] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [48] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [48] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [63] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [63] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 re2csr_error [4] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [2] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [2] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [1] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [1] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [0] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [0] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [3] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [3] "logic re2csr_error[31:0]" +ANNOTATION: " Header value " +Toggle afu_csr_addr_8B "logic afu_csr_addr_8B[14:0]" +ANNOTATION: " Header value " +Toggle afu_csr_addr_8B_T1 "logic afu_csr_addr_8B_T1[14:0]" +ANNOTATION: " Header value " +Toggle afu_csr_addr_4B "logic afu_csr_addr_4B[15:0]" +ANNOTATION: " Header value " +Toggle feature_0_addr_offset_8B_T1 "logic feature_0_addr_offset_8B_T1[14:0]" +Toggle 1to0 csr2re_interrupt0 [30] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [30] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [29] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [29] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [28] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [28] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [27] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [27] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [26] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [26] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [25] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [25] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [24] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [24] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [23] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [23] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [22] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [22] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [21] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [21] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [20] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [20] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [19] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [19] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [18] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [18] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [31] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [31] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [14] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [14] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [13] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [13] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [12] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [12] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [11] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [11] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [10] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [10] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [9] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [9] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [8] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [8] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [7] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [7] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [6] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [6] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [5] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [5] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [4] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [4] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [3] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [3] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [2] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [2] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [1] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [1] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [0] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [0] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [15] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [15] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 re2csr_error [30] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [30] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [29] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [29] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [28] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [28] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [27] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [27] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [26] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [26] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [25] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [25] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [24] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [24] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [23] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [23] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [22] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [22] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [21] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [21] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [20] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [20] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [19] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [19] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [18] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [18] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [17] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [17] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [16] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [16] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [15] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [15] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [14] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [14] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [13] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [13] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [12] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [12] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [11] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [11] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [10] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [10] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [9] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [9] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [8] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [8] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [7] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [7] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [6] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [6] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [5] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [5] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [31] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [31] "logic re2csr_error[31:0]" +Toggle 0to1 csr2re_num_lines [31] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [31] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [10] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [10] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [11] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [11] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [12] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [12] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [13] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [13] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [14] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [14] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [15] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [15] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [16] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [16] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [17] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [17] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [18] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [18] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [19] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [19] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [20] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [20] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [21] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [21] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [22] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [22] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [23] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [23] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [24] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [24] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [25] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [25] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [26] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [26] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [27] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [27] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [28] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [28] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [29] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [29] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [30] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [30] "logic csr2re_num_lines[31:0]" +ANNOTATION: " Not connected " +Toggle csr2re_stride "logic csr2re_stride[31:0]" +ANNOTATION: " Randomized value " +Toggle re2csr_num_wrpend "logic re2csr_num_wrpend[31:0]" +ANNOTATION: " Randomized value " +Toggle re2csr_num_rdpend "logic re2csr_num_rdpend[31:0]" +ANNOTATION: " Randomized value " +Toggle re2csr_num_reads "logic re2csr_num_reads[31:0]" +ANNOTATION: " Randomized value " +Toggle re2csr_num_writes "logic re2csr_num_writes[31:0]" +Toggle 0to1 range_valid "logic range_valid" +Toggle 1to0 range_valid "logic range_valid" +Toggle 0to1 csr2re_cfg [63] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [63] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [14] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [14] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [15] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [15] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [16] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [16] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [17] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [17] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [18] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [18] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [19] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [19] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [30] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [30] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [31] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [31] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [32] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [32] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [33] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [33] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [34] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [34] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [35] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [35] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [36] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [36] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [37] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [37] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [38] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [38] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [39] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [39] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [40] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [40] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [41] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [41] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [42] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [42] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [43] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [43] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [44] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [44] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [45] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [45] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [46] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [46] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [47] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [47] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [48] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [48] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [49] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [49] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [50] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [50] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [51] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [51] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [52] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [52] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [53] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [53] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [54] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [54] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [55] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [55] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [56] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [56] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [57] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [57] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [58] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [58] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [59] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [59] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [60] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [60] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [61] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [61] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [62] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [62] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_ctl [31] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [31] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [3] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [3] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [4] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [4] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [5] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [5] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [6] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [6] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [7] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [7] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [8] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [8] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [9] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [9] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [10] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [10] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [11] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [11] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [12] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [12] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [13] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [13] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [14] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [14] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [15] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [15] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [16] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [16] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [17] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [17] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [18] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [18] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [19] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [19] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [20] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [20] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [21] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [21] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [22] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [22] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [23] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [23] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [24] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [24] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [25] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [25] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [26] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [26] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [27] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [27] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [28] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [28] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [29] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [29] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [30] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [30] "logic csr2re_ctl[31:0]" +ANNOTATION: " Header " +Toggle feature_id_T2 "logic feature_id_T2[1:0]" +CHECKSUM: "3697671760 2902293516" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst +Toggle 1to0 tput_interleave [2] "logic tput_interleave[2:0]" +Toggle 0to1 tput_interleave [2] "logic tput_interleave[2:0]" +Toggle 1to0 csr2re_ctl [2] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_dsm_base [62] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [62] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [61] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [61] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [60] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [60] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [59] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [59] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [58] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [58] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [57] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [57] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [56] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [56] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [55] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [55] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [54] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [54] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [53] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [53] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [52] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [52] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [51] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [51] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [50] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [50] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [49] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [49] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [48] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [48] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [63] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [63] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 rw_error_valid "logic rw_error_valid" +Toggle 0to1 rw_error_valid "logic rw_error_valid" +Toggle 1to0 rw_rx_rsp_ready "logic rw_rx_rsp_ready" +Toggle 0to1 rw_rx_rsp_ready "logic rw_rx_rsp_ready" +ANNOTATION: " Randomly toggles " +Toggle rw_tx_req_pld "logic rw_tx_req_pld[511:0]" +Toggle 1to0 re2csr_error [2] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [2] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [1] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [1] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [0] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [0] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [4] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [3] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [3] "logic re2csr_error[31:0]" +Toggle 1to0 rw_error_info [1] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [1] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [2] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [2] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [3] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [3] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [4] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [4] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [0] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [0] "logic rw_error_info[31:0]" +Toggle 1to0 lb_error_valid "logic lb_error_valid" +Toggle 0to1 lb_error_valid "logic lb_error_valid" +Toggle 1to0 lb_rx_rsp_ready "logic lb_rx_rsp_ready" +Toggle 0to1 lb_rx_rsp_ready "logic lb_rx_rsp_ready" +Toggle 1to0 lb_error_info [1] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [1] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [2] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [2] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [3] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [3] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [4] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [4] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [0] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [0] "logic lb_error_info[31:0]" +Toggle 1to0 csr2re_interrupt0 [14] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [14] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [13] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [13] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [12] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [12] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [11] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [11] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [10] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [10] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [9] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [9] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [8] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [8] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [7] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [7] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [6] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [6] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [5] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [5] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [4] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [4] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [3] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [3] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [2] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [2] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [1] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [1] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [0] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [0] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [15] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [15] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 ab_error_info [1] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [1] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [2] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [2] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [3] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [3] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [4] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [4] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [0] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [0] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_valid "logic ab_error_valid" +Toggle 0to1 ab_error_valid "logic ab_error_valid" +Toggle 1to0 ab_rx_rsp_ready "logic ab_rx_rsp_ready" +Toggle 0to1 ab_rx_rsp_ready "logic ab_rx_rsp_ready" +Toggle 1to0 csr2re_interrupt0 [30] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [30] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [29] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [29] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [28] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [28] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [27] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [27] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [26] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [26] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [25] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [25] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [24] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [24] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [23] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [23] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [22] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [22] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [21] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [21] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [20] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [20] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [19] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [19] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [18] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [18] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [31] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [31] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 ErrorVector [1] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [1] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [2] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [2] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [3] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [3] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [4] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [4] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [0] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [0] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [31] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [31] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [5] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [5] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [6] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [6] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [7] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [7] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [8] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [8] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [9] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [9] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [10] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [10] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [11] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [11] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [12] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [12] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [13] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [13] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [14] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [14] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [15] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [15] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [16] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [16] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [17] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [17] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [18] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [18] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [19] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [19] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [20] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [20] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [21] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [21] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [22] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [22] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [23] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [23] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [24] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [24] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [25] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [25] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [26] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [26] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [27] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [27] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [28] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [28] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [29] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [29] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [30] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [30] "logic ErrorVector[31:0]" +Toggle 0to1 ab_error_info [31] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [31] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [5] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [5] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [6] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [6] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [7] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [7] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [8] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [8] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [9] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [9] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [10] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [10] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [11] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [11] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [12] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [12] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [13] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [13] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [14] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [14] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [15] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [15] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [16] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [16] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [17] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [17] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [18] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [18] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [19] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [19] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [20] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [20] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [21] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [21] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [22] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [22] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [23] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [23] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [24] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [24] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [25] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [25] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [26] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [26] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [27] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [27] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [28] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [28] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [29] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [29] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [30] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [30] "logic ab_error_info[31:0]" +ANNOTATION: " Randomized value " +Toggle avmm_num_ticks_h "logic avmm_num_ticks_h[19:0]" +ANNOTATION: " Randomized value " +Toggle avmm_num_ticks_l "logic avmm_num_ticks_l[19:0]" +ANNOTATION: " Randomized value " +Toggle avmm_num_reads "logic avmm_num_reads[39:0]" +ANNOTATION: " Randomized value " +Toggle avmm_num_writes "logic avmm_num_writes[39:0]" +ANNOTATION: " Not connected " +Toggle csr2re_stride "logic csr2re_stride[31:0]" +Toggle 0to1 lb_error_info [31] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [31] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [5] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [5] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [6] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [6] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [7] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [7] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [8] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [8] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [9] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [9] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [10] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [10] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [11] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [11] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [12] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [12] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [13] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [13] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [14] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [14] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [15] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [15] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [16] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [16] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [17] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [17] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [18] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [18] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [19] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [19] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [20] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [20] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [21] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [21] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [22] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [22] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [23] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [23] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [24] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [24] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [25] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [25] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [26] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [26] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [27] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [27] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [28] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [28] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [29] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [29] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [30] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [30] "logic lb_error_info[31:0]" +Toggle 0to1 re2csr_error [31] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [31] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [5] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [5] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [6] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [6] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [7] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [7] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [8] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [8] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [9] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [9] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [10] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [10] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [11] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [11] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [12] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [12] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [13] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [13] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [14] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [14] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [15] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [15] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [16] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [16] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [17] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [17] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [18] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [18] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [19] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [19] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [20] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [20] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [21] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [21] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [22] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [22] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [23] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [23] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [24] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [24] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [25] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [25] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [26] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [26] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [27] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [27] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [28] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [28] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [29] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [29] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [30] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [30] "logic re2csr_error[31:0]" +Toggle 0to1 csr2re_ctl [31] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [31] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [3] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [3] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [4] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [4] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [5] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [5] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [6] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [6] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [7] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [7] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [8] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [8] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [9] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [9] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [10] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [10] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [11] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [11] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [12] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [12] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [13] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [13] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [14] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [14] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [15] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [15] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [16] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [16] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [17] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [17] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [18] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [18] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [19] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [19] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [20] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [20] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [21] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [21] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [22] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [22] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [23] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [23] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [24] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [24] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [25] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [25] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [26] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [26] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [27] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [27] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [28] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [28] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [29] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [29] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [30] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [30] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_cfg [63] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [63] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [30] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [30] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [31] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [31] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [32] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [32] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [33] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [33] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [34] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [34] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [35] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [35] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [36] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [36] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [37] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [37] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [38] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [38] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [39] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [39] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [40] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [40] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [41] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [41] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [42] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [42] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [43] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [43] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [44] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [44] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [45] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [45] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [46] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [46] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [47] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [47] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [48] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [48] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [49] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [49] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [50] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [50] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [51] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [51] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [52] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [52] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [53] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [53] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [54] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [54] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [55] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [55] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [56] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [56] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [57] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [57] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [58] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [58] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [59] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [59] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [60] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [60] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [61] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [61] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [62] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [62] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [19] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [19] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [7] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [7] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [8] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [8] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [9] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [9] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [10] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [10] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [11] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [11] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [12] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [12] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [13] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [13] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [14] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [14] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [15] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [15] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [16] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [16] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [17] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [17] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [18] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [18] "logic csr2re_cfg[63:0]" +Toggle 0to1 req_len_b2 [4] "logic req_len_b2[4:0]" +Toggle 1to0 req_len_b2 [4] "logic req_len_b2[4:0]" +Toggle 0to1 req_len_b2 [2] "logic req_len_b2[4:0]" +Toggle 1to0 req_len_b2 [2] "logic req_len_b2[4:0]" +Toggle 0to1 req_len_b2 [3] "logic req_len_b2[4:0]" +Toggle 1to0 req_len_b2 [3] "logic req_len_b2[4:0]" +Toggle 1to0 test_complete_rw "logic test_complete_rw" +Toggle 1to0 test_started_rw "logic test_started_rw" +ANNOTATION: " Does not toggle " +Toggle csr_raddr "logic csr_raddr[9:0]" +Toggle 0to1 csr_read "logic csr_read" +Toggle 1to0 csr_read "logic csr_read" +Toggle 0to1 csr_read_32b "logic csr_read_32b" +Toggle 1to0 csr_read_32b "logic csr_read_32b" +ANNOTATION: " Does not toggle " +Toggle csr_wstrb "logic csr_wstrb[7:0]" +Toggle 0to1 csr_write "logic csr_write" +Toggle 1to0 csr_write "logic csr_write" +ANNOTATION: " Does not toggle " +Toggle csr_wdata "logic csr_wdata[63:0]" +ANNOTATION: " Does not toggle " +Toggle csr_waddr "logic csr_waddr[9:0]" +Toggle 0to1 csr_readdata_valid "logic csr_readdata_valid" +Toggle 1to0 csr_readdata_valid "logic csr_readdata_valid" +ANNOTATION: " Does not toggle " +Toggle csr_readdata "logic csr_readdata[63:0]" +ANNOTATION: " Randomized value " +Toggle re2csr_num_wrpend "logic re2csr_num_wrpend[31:0]" +Toggle 0to1 rw_error_info [31] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [31] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [5] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [5] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [6] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [6] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [7] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [7] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [8] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [8] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [9] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [9] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [10] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [10] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [11] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [11] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [12] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [12] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [13] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [13] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [14] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [14] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [15] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [15] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [16] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [16] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [17] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [17] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [18] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [18] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [19] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [19] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [20] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [20] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [21] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [21] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [22] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [22] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [23] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [23] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [24] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [24] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [25] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [25] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [26] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [26] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [27] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [27] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [28] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [28] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [29] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [29] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [30] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [30] "logic rw_error_info[31:0]" +ANNOTATION: " Randomized value " +Toggle re2csr_num_reads "logic re2csr_num_reads[31:0]" +ANNOTATION: " Randomized value " +Toggle re2csr_num_rdpend "logic re2csr_num_rdpend[31:0]" +ANNOTATION: " Randomized value " +Toggle csr2re_num_lines "logic csr2re_num_lines[31:0]" +ANNOTATION: " Randomized value " +Toggle re2csr_num_writes "logic re2csr_num_writes[31:0]" +CHECKSUM: "1259019545 702362531" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.axi_tx_stage_1 +ANNOTATION: " Not valid condition " +Condition 1 "4206754987" "(((~genblk1.s_tready_pre)) && genblk1.s_tready_reg) 1 -1" (1 "01") +CHECKSUM: "3697671760 4180572418" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst +Block 13 "4095289818" ";" +Block 17 "541319598" ";" +Block 21 "1529306131" ";" +Block 24 "3321253388" ";" +Block 27 "446168645" ";" +Block 30 "89501388" ";" +Block 34 "2625678669" ";" +Block 37 "1196186585" ";" +Block 40 "3722362545" ";" +Block 43 "1355339084" ";" +Block 12 "3419118685" "ErrorVector[0] <= 1'b1;" +Block 16 "2010279672" "ErrorVector[1] <= 1'b1;" +Block 20 "2199004750" "$display(\"======================================================================================================\");" +Block 42 "3389147320" "$display(\"======================================================================================================\");" +Block 39 "3206555465" "$display(\"======================================================================================================\");" +Block 36 "3655214768" "$display(\"======================================================================================================\");" +Block 33 "3025113060" "$display(\"======================================================================================================\");" +Block 29 "3255931853" "$display(\"======================================================================================================\");" +Block 26 "2550033116" "$display(\"======================================================================================================\");" +Block 23 "562796791" "$display(\"======================================================================================================\");" +CHECKSUM: "2618233009 1440168460" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req +Block 155 "157836716" ";" +Block 154 "853555128" "#100" +ANNOTATION: "ErrorVector[4] is 0" +Block 151 "2400460436" "ErrorVector[4] <= 1;" +ANNOTATION: "ErrorVector[3] is 0" +Block 148 "2228869873" "ErrorVector[3] <= 1;" +ANNOTATION: "ErrorVector[2] is 0" +Block 145 "3910752870" "ErrorVector[2] <= 1;" +ANNOTATION: "ErrorVector[1] is 0" +Block 142 "268819500" "ErrorVector[1] <= 1;" +ANNOTATION: "ErrorVector[0] is 0" +Block 139 "1901327212" "ErrorVector[0] <= 1;" +CHECKSUM: "599439132 3833084147" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.host_rw.mode_rdwr.tx_q +Block 5 "1895881913" "fifo_err <= 1'b1;" +Block 4 "2246164006" "fifo_err <= 1'b1;" +CHECKSUM: "599439132 3833084147" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.mode_lpbk.rx_q +Block 4 "2246164006" "fifo_err <= 1'b1;" +Block 5 "1895881913" "fifo_err <= 1'b1;" +CHECKSUM: "599439132 3833084147" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.mode_lpbk.tx_q +Block 4 "2246164006" "fifo_err <= 1'b1;" +Block 5 "1895881913" "fifo_err <= 1'b1;" +CHECKSUM: "599439132 3833084147" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.mmio_rsp_q +Block 5 "1895881913" "fifo_err <= 1'b1;" +Block 4 "2246164006" "fifo_err <= 1'b1;" +CHECKSUM: "1772701634 733746646" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.host_rw.mode_rdwr +ANNOTATION: "Ewrror is 0" +Block 71 "2245356259" "ErrorVector[1] <= 1;" +ANNOTATION: "Error is 0" +Block 75 "676313567" "$display(\"======================================================================================================\");" +Block 80 "2371758446" ";" +Block 79 "3842708538" "$display(\"======================================================================================================\");" +ANNOTATION: "Error is 0" +Block 76 "1604857731" ";" +ANNOTATION: "Error is 0" +Block 84 "145859954" ";" +ANNOTATION: "Error is 0" +Block 83 "853555128" "#100" +CHECKSUM: "3190985420 273527257" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.he_rx_rsp_q.odd_que.fifo_ram +Block 3 "3564767746" "perr_or = 0;" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.axi_rx_if_T1 +Assert assert_tvalid_tready_handshake "assertion" +CHECKSUM: "1684972762 369815844" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.mode_lpbk +Block 132 "1608699120" ";" +Block 136 "977391136" ";" +Block 140 "1084742192" ";" +Block 144 "1354075342" ";" +Block 149 "1604857731" ";" +Block 153 "2392870434" ";" +Block 157 "201305867" ";" +Block 161 "145859954" ";" +Block 132 "1608699120" ";" +Block 136 "977391136" ";" +Block 140 "1084742192" ";" +Block 144 "1354075342" ";" +Block 149 "1604857731" ";" +Block 153 "2392870434" ";" +Block 157 "201305867" ";" +Block 161 "145859954" ";" +Block 132 "1608699120" ";" +Block 136 "977391136" ";" +Block 140 "1084742192" ";" +Block 144 "1354075342" ";" +Block 149 "1604857731" ";" +Block 153 "2392870434" ";" +Block 157 "201305867" ";" +Block 161 "145859954" ";" +Block 132 "1608699120" ";" +Block 136 "977391136" ";" +Block 140 "1084742192" ";" +Block 144 "1354075342" ";" +Block 149 "1604857731" ";" +Block 153 "2392870434" ";" +Block 157 "201305867" ";" +Block 161 "145859954" ";" +Block 132 "1608699120" ";" +Block 136 "977391136" ";" +Block 140 "1084742192" ";" +Block 144 "1354075342" ";" +Block 149 "1604857731" ";" +Block 153 "2392870434" ";" +Block 157 "201305867" ";" +Block 161 "145859954" ";" +Block 132 "1608699120" ";" +Block 136 "977391136" ";" +Block 140 "1084742192" ";" +Block 144 "1354075342" ";" +Block 149 "1604857731" ";" +Block 153 "2392870434" ";" +Block 157 "201305867" ";" +Block 161 "145859954" ";" +Block 132 "1608699120" ";" +Block 136 "977391136" ";" +Block 140 "1084742192" ";" +Block 144 "1354075342" ";" +Block 149 "1604857731" ";" +Block 153 "2392870434" ";" +Block 157 "201305867" ";" +Block 161 "145859954" ";" +Block 132 "1608699120" ";" +Block 136 "977391136" ";" +Block 140 "1084742192" ";" +Block 144 "1354075342" ";" +Block 149 "1604857731" ";" +Block 153 "2392870434" ";" +Block 157 "201305867" ";" +Block 161 "145859954" ";" +CHECKSUM: "2604824649 3623767598" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst +Block 13 "515876581" ";" +Block 17 "1045176880" ";" +Block 21 "43724104" ";" +Block 24 "683582534" ";" +Block 27 "2782964414" ";" +Block 30 "880950668" ";" +Block 34 "3734780334" ";" +Block 37 "1959644224" ";" +Block 40 "1817966459" ";" +Block 43 "2879756941" ";" +Block 13 "515876581" ";" +Block 17 "1045176880" ";" +Block 21 "43724104" ";" +Block 24 "683582534" ";" +Block 27 "2782964414" ";" +Block 30 "880950668" ";" +Block 34 "3734780334" ";" +Block 37 "1959644224" ";" +Block 40 "1817966459" ";" +Block 43 "2879756941" ";" +Block 13 "515876581" ";" +Block 17 "1045176880" ";" +Block 21 "43724104" ";" +Block 24 "683582534" ";" +Block 27 "2782964414" ";" +Block 30 "880950668" ";" +Block 34 "3734780334" ";" +Block 37 "1959644224" ";" +Block 40 "1817966459" ";" +Block 43 "2879756941" ";" +Block 13 "515876581" ";" +Block 17 "1045176880" ";" +Block 21 "43724104" ";" +Block 24 "683582534" ";" +Block 27 "2782964414" ";" +Block 30 "880950668" ";" +Block 34 "3734780334" ";" +Block 37 "1959644224" ";" +Block 40 "1817966459" ";" +Block 43 "2879756941" ";" +Block 13 "515876581" ";" +Block 17 "1045176880" ";" +Block 21 "43724104" ";" +Block 24 "683582534" ";" +Block 27 "2782964414" ";" +Block 30 "880950668" ";" +Block 34 "3734780334" ";" +Block 37 "1959644224" ";" +Block 40 "1817966459" ";" +Block 43 "2879756941" ";" +Block 13 "515876581" ";" +Block 17 "1045176880" ";" +Block 21 "43724104" ";" +Block 24 "683582534" ";" +Block 27 "2782964414" ";" +Block 30 "880950668" ";" +Block 34 "3734780334" ";" +Block 37 "1959644224" ";" +Block 40 "1817966459" ";" +Block 43 "2879756941" ";" +Block 13 "515876581" ";" +Block 17 "1045176880" ";" +Block 21 "43724104" ";" +Block 24 "683582534" ";" +Block 27 "2782964414" ";" +Block 30 "880950668" ";" +Block 34 "3734780334" ";" +Block 37 "1959644224" ";" +Block 40 "1817966459" ";" +Block 43 "2879756941" ";" +Block 13 "515876581" ";" +Block 17 "1045176880" ";" +Block 21 "43724104" ";" +Block 24 "683582534" ";" +Block 27 "2782964414" ";" +Block 30 "880950668" ";" +Block 34 "3734780334" ";" +Block 37 "1959644224" ";" +Block 40 "1817966459" ";" +Block 43 "2879756941" ";" +Block 13 "515876581" ";" +Block 17 "1045176880" ";" +Block 21 "43724104" ";" +Block 24 "683582534" ";" +Block 27 "2782964414" ";" +Block 30 "880950668" ";" +Block 34 "3734780334" ";" +Block 37 "1959644224" ";" +Block 40 "1817966459" ";" +Block 43 "2879756941" ";" +Block 13 "515876581" ";" +Block 17 "1045176880" ";" +Block 21 "43724104" ";" +Block 24 "683582534" ";" +Block 27 "2782964414" ";" +Block 30 "880950668" ";" +Block 34 "3734780334" ";" +Block 37 "1959644224" ";" +Block 40 "1817966459" ";" +Block 43 "2879756941" ";" +CHECKSUM: "3704842485 166614001" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req +Block 155 "145859954" ";" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.axi_rx_if_T1 +Assert assert_tvalid_tready_handshake "assertion" diff --git a/verification/coverage/he_mem_exclusions.el b/verification/coverage/he_mem_exclusions.el new file mode 100644 index 0000000..074532b --- /dev/null +++ b/verification/coverage/he_mem_exclusions.el @@ -0,0 +1,7308 @@ +//================================================== +// This file contains the Excluded objects +// Generated By User: vpakax +// Format Version: 2 +// Date: Tue May 24 05:38:19 2022 +// ExclMode: default +//================================================== +CHECKSUM: "3630569307" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.mmio_rsp_q.genblk1.scfifo_component.dev +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_lpbk.clnum_ram +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_lpbk.emif_trk_ram +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_lpbk.clnum_ram.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_lpbk.emif_trk_ram.mem +CHECKSUM: "1721330791 2902293516" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst +Toggle 1to0 csr2re_ctl [2] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_dsm_base [62] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [62] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [61] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [61] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [60] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [60] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [59] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [59] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [58] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [58] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [57] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [57] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [56] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [56] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [55] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [55] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [54] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [54] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [53] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [53] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [52] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [52] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [51] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [51] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [50] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [50] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [49] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [49] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [48] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [48] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [63] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [63] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 re2csr_error [4] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [2] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [2] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [1] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [1] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [0] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [0] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [3] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [3] "logic re2csr_error[31:0]" +Toggle 1to0 rw_error_valid "logic rw_error_valid" +Toggle 0to1 rw_error_valid "logic rw_error_valid" +Toggle 1to0 rw_rx_rsp_ready "logic rw_rx_rsp_ready" +Toggle 0to1 rw_rx_rsp_ready "logic rw_rx_rsp_ready" +Toggle 1to0 rw_error_info [1] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [1] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [2] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [2] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [3] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [3] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [4] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [4] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [0] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [0] "logic rw_error_info[31:0]" +Toggle 1to0 lb_error_valid "logic lb_error_valid" +Toggle 0to1 lb_error_valid "logic lb_error_valid" +Toggle 1to0 ErrorVector [1] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [1] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [2] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [2] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [3] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [3] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [4] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [4] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [0] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [0] "logic ErrorVector[31:0]" +Toggle 1to0 ab_error_info [1] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [1] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [2] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [2] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [3] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [3] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [4] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [4] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [0] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [0] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_valid "logic ab_error_valid" +Toggle 0to1 ab_error_valid "logic ab_error_valid" +Toggle 1to0 lb_error_info [1] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [1] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [2] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [2] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [3] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [3] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [4] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [4] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [0] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [0] "logic lb_error_info[31:0]" +Toggle 0to1 ErrorVector [31] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [31] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [5] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [5] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [6] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [6] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [7] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [7] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [8] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [8] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [9] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [9] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [10] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [10] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [11] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [11] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [12] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [12] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [13] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [13] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [14] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [14] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [15] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [15] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [16] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [16] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [17] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [17] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [18] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [18] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [19] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [19] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [20] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [20] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [21] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [21] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [22] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [22] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [23] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [23] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [24] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [24] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [25] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [25] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [26] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [26] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [27] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [27] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [28] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [28] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [29] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [29] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [30] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [30] "logic ErrorVector[31:0]" +Toggle 0to1 ab_error_info [31] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [31] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [5] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [5] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [6] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [6] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [7] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [7] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [8] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [8] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [9] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [9] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [10] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [10] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [11] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [11] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [12] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [12] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [13] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [13] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [14] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [14] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [15] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [15] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [16] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [16] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [17] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [17] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [18] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [18] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [19] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [19] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [20] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [20] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [21] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [21] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [22] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [22] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [23] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [23] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [24] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [24] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [25] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [25] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [26] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [26] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [27] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [27] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [28] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [28] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [29] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [29] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [30] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [30] "logic ab_error_info[31:0]" +ANNOTATION: " Randomly toggles " +Toggle avmm_num_ticks_h "logic avmm_num_ticks_h[19:0]" +ANNOTATION: " Randomly toggles " +Toggle csr_raddr "logic csr_raddr[9:0]" +ANNOTATION: " Randomly toggles " +Toggle csr2re_stride "logic csr2re_stride[31:0]" +ANNOTATION: " Randomly toggles " +Toggle csr_waddr "logic csr_waddr[9:0]" +ANNOTATION: " Randomly toggles " +Toggle csr_wstrb "logic csr_wstrb[7:0]" +Toggle 0to1 csr_write "logic csr_write" +Toggle 1to0 csr_write "logic csr_write" +ANNOTATION: " Randomly toggles " +Toggle csr_wdata "logic csr_wdata[63:0]" +Toggle 0to1 csr_read "logic csr_read" +Toggle 1to0 csr_read "logic csr_read" +Toggle 0to1 csr_readdata_valid "logic csr_readdata_valid" +Toggle 1to0 csr_readdata_valid "logic csr_readdata_valid" +ANNOTATION: " Randomly toggles " +Toggle csr_readdata "logic csr_readdata[63:0]" +Toggle 0to1 csr_read_32b "logic csr_read_32b" +Toggle 1to0 csr_read_32b "logic csr_read_32b" +Toggle 0to1 lb_error_info [31] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [31] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [5] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [5] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [6] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [6] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [7] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [7] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [8] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [8] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [9] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [9] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [10] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [10] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [11] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [11] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [12] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [12] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [13] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [13] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [14] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [14] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [15] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [15] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [16] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [16] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [17] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [17] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [18] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [18] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [19] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [19] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [20] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [20] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [21] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [21] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [22] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [22] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [23] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [23] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [24] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [24] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [25] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [25] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [26] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [26] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [27] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [27] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [28] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [28] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [29] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [29] "logic lb_error_info[31:0]" +Toggle 0to1 lb_error_info [30] "logic lb_error_info[31:0]" +Toggle 1to0 lb_error_info [30] "logic lb_error_info[31:0]" +ANNOTATION: " Randomly toggles " +Toggle re2csr_num_wrpend "logic re2csr_num_wrpend[31:0]" +Toggle 0to1 rw_error_info [31] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [31] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [5] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [5] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [6] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [6] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [7] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [7] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [8] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [8] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [9] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [9] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [10] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [10] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [11] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [11] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [12] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [12] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [13] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [13] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [14] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [14] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [15] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [15] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [16] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [16] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [17] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [17] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [18] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [18] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [19] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [19] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [20] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [20] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [21] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [21] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [22] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [22] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [23] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [23] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [24] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [24] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [25] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [25] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [26] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [26] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [27] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [27] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [28] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [28] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [29] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [29] "logic rw_error_info[31:0]" +Toggle 0to1 rw_error_info [30] "logic rw_error_info[31:0]" +Toggle 1to0 rw_error_info [30] "logic rw_error_info[31:0]" +Toggle 0to1 re2csr_error [31] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [31] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [5] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [5] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [6] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [6] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [7] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [7] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [8] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [8] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [9] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [9] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [10] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [10] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [11] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [11] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [12] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [12] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [13] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [13] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [14] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [14] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [15] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [15] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [16] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [16] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [17] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [17] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [18] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [18] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [19] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [19] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [20] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [20] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [21] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [21] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [22] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [22] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [23] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [23] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [24] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [24] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [25] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [25] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [26] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [26] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [27] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [27] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [28] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [28] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [29] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [29] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [30] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [30] "logic re2csr_error[31:0]" +ANNOTATION: " Randomly toggles " +Toggle rw_tx_req_pld "logic rw_tx_req_pld[511:0]" +Toggle 0to1 csr2re_interrupt0 [31] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [31] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [18] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [18] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [19] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [19] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [20] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [20] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [21] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [21] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [22] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [22] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [23] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [23] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [24] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [24] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [25] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [25] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [26] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [26] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [27] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [27] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [28] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [28] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [29] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [29] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [30] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [30] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [15] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [15] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [0] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [0] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [1] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [1] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [2] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [2] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [3] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [3] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [4] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [4] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [5] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [5] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [6] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [6] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [7] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [7] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [8] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [8] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [9] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [9] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [10] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [10] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [11] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [11] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [12] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [12] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [13] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [13] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [14] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [14] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_ctl [31] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [31] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [3] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [3] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [4] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [4] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [5] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [5] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [6] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [6] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [7] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [7] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [8] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [8] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [9] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [9] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [10] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [10] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [11] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [11] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [12] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [12] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [13] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [13] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [14] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [14] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [15] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [15] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [16] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [16] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [17] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [17] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [18] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [18] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [19] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [19] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [20] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [20] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [21] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [21] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [22] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [22] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [23] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [23] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [24] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [24] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [25] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [25] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [26] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [26] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [27] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [27] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [28] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [28] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [29] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [29] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [30] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [30] "logic csr2re_ctl[31:0]" +ANNOTATION: " Randomly toggles " +Toggle re2csr_num_rdpend "logic re2csr_num_rdpend[31:0]" +ANNOTATION: " Randomly toggles " +Toggle avmm_num_reads "logic avmm_num_reads[39:0]" +ANNOTATION: " Randomly toggles " +Toggle re2csr_num_writes "logic re2csr_num_writes[31:0]" +ANNOTATION: " Randomly toggles " +Toggle re2csr_num_reads "logic re2csr_num_reads[31:0]" +ANNOTATION: " Randomly toggles " +Toggle avmm_num_writes "logic avmm_num_writes[39:0]" +Toggle 0to1 csr2re_cfg [63] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [63] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [30] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [30] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [31] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [31] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [32] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [32] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [33] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [33] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [34] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [34] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [35] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [35] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [36] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [36] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [37] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [37] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [38] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [38] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [39] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [39] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [40] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [40] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [41] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [41] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [42] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [42] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [43] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [43] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [44] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [44] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [45] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [45] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [46] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [46] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [47] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [47] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [48] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [48] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [49] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [49] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [50] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [50] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [51] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [51] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [52] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [52] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [53] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [53] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [54] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [54] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [55] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [55] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [56] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [56] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [57] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [57] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [58] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [58] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [59] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [59] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [60] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [60] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [61] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [61] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [62] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [62] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [19] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [19] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [14] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [14] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [15] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [15] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [16] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [16] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [17] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [17] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [18] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [18] "logic csr2re_cfg[63:0]" +Toggle 0to1 req_len_b2 [4] "logic req_len_b2[4:0]" +Toggle 1to0 req_len_b2 [4] "logic req_len_b2[4:0]" +Toggle 0to1 req_len_b2 [2] "logic req_len_b2[4:0]" +Toggle 1to0 req_len_b2 [2] "logic req_len_b2[4:0]" +Toggle 0to1 req_len_b2 [3] "logic req_len_b2[4:0]" +Toggle 1to0 req_len_b2 [3] "logic req_len_b2[4:0]" +ANNOTATION: " Randomly toggles " +Toggle csr2re_num_lines "logic csr2re_num_lines[31:0]" +ANNOTATION: " Randomly toggles " +Toggle avmm_num_ticks_l "logic avmm_num_ticks_l[19:0]" +Toggle 1to0 test_complete_rw "logic test_complete_rw" +Toggle 1to0 test_started_rw "logic test_started_rw" +CHECKSUM: "3572029108 4025737348" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_lpbk.emif_trk_ram +Branch 20 "431396299" "((operation_mode == \"DUAL_PORT\") && ((i_numwords_a * width_a) != (i_numwords_b * width_b)))" (0) "((operation_mode == \"DUAL_PORT\") && ((i_numwords_a * width_a) != (i_numwords_b * width_b))) 1" +Branch 27 "161741860" "((((operation_mode == \"DUAL_PORT\") && (outdata_reg_b != \"CLOCK0\")) && (is_lutram == 1)) && (read_during_write_mode_mixed_ports == \"OLD_DATA\"))" (0) "((((operation_mode == \"DUAL_PORT\") && (outdata_reg_b != \"CLOCK0\")) && (is_lutram == 1)) && (read_during_write_mode_mixed_ports == \"OLD_DATA\")) 1" +CHECKSUM: "599439132 1849783068" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.mmio_rsp_q +ANNOTATION: " Quartus fifo- need not be generated " +Branch 0 "233563799" "(!Resetb)" (1) "(!Resetb) 0,(fifo_ren & (fifo_count == 4'b0)) " +ANNOTATION: " Quartus fifo- need not be generated " +Branch 0 "233563799" "(!Resetb)" (2) "(!Resetb) 0,((fifo_wen & (!fifo_ren)) & full) " +CHECKSUM: "599439132 1849783068" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_lpbk.emif_req_q +Branch 0 "233563799" "(!Resetb)" (1) "(!Resetb) 0,(fifo_ren & (fifo_count == 4'b0)) " +Branch 0 "233563799" "(!Resetb)" (2) "(!Resetb) 0,((fifo_wen & (!fifo_ren)) & full) " +CHECKSUM: "599439132 1849783068" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_rdwr.tx_q +Branch 0 "233563799" "(!Resetb)" (1) "(!Resetb) 0,(fifo_ren & (fifo_count == 4'b0)) " +Branch 0 "233563799" "(!Resetb)" (2) "(!Resetb) 0,((fifo_wen & (!fifo_ren)) & full) " +CHECKSUM: "599439132 2687758089" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_lpbk.tx_q +ANNOTATION: " Quartus fifo- need not be generated " +Branch 0 "1362767249" "(!Resetb)" (1) "(!Resetb) 0,(fifo_ren & (fifo_count == 11'b0)) " +ANNOTATION: " Quartus fifo- need not be generated " +Branch 0 "1362767249" "(!Resetb)" (2) "(!Resetb) 0,((fifo_wen & (!fifo_ren)) & full) " +CHECKSUM: "599439132 2687758089" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_lpbk.rx_q +ANNOTATION: " Quartus fifo- need not be generated " +Branch 0 "1362767249" "(!Resetb)" (1) "(!Resetb) 0,(fifo_ren & (fifo_count == 11'b0)) " +ANNOTATION: " Quartus fifo- need not be generated " +Branch 0 "1362767249" "(!Resetb)" (2) "(!Resetb) 0,((fifo_wen & (!fifo_ren)) & full) " +CHECKSUM: "2139909825 784985182" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_lpbk +Block 132 "2657744755" ";" +Block 136 "4132693144" ";" +Block 140 "3499880051" ";" +Block 144 "4204325147" ";" +Block 149 "3524869349" ";" +Block 153 "2818050566" ";" +Block 157 "3230578631" ";" +Block 161 "157836716" ";" +Block 131 "3956740591" "ErrorVector[0] <= 1;" +Block 143 "3600159615" "ErrorVector[3] <= 1;" +Block 139 "1412364358" "ErrorVector[2] <= 1;" +Block 135 "2307788477" "ErrorVector[1] <= 1;" +Block 148 "1629689826" "$display(\"======================================================================================================\");" +Block 152 "3995717433" "$display(\"======================================================================================================\");" +Block 156 "2725329329" "$display(\"======================================================================================================\");" +Block 160 "853555128" "#100" +Block 51 "3115081520" "rx_rsp_wen <= rx_rsp_valid_q;" +ANNOTATION: "EMIF IS 1" +Block 63 "3733844856" "rx_rsp_wen <= 1'b0;" +Block 62 "1808023560" "if ((!test_resetb_q))" +Block 60 "3861210068" "rd_rsp_cnt <= (rd_rsp_cnt + recent_rx_rsp_pld_len);" +Block 59 "3905754821" "if ((rx_rsp_valid_q & rx_rsp_eop_q))" +Block 58 "1071395757" "rd_rsp_cnt <= 0;" +Block 57 "136215613" "if ((state == IDLE))" +Block 55 "1257455142" "recent_rx_rsp_pld_len <= rx_rsp_len_q;" +Block 54 "4187183248" "if ((rx_rsp_valid_q & rx_rsp_sop_q))" +Block 52 "635457386" "rx_rsp_din[49:34] <= clnum_ram_dout;" +CHECKSUM: "2618233009 166614001" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req +Toggle 1to0 dsm_status [206] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [206] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [205] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [205] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [204] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [204] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [203] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [203] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [202] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [202] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [201] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [201] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [200] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [200] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [199] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [199] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [198] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [198] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [197] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [197] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [196] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [196] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [195] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [195] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [194] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [194] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [193] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [193] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [192] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [192] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [207] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [207] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [102] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [102] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [101] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [101] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [100] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [100] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [99] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [99] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [98] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [98] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [97] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [97] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [96] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [96] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [95] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [95] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [94] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [94] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [93] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [93] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [92] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [92] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [91] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [91] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [90] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [90] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [89] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [89] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [88] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [88] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [87] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [87] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [86] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [86] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [85] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [85] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [84] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [84] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [83] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [83] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [82] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [82] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [81] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [81] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [103] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [103] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [158] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [158] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [157] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [157] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [156] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [156] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [155] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [155] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [154] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [154] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [153] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [153] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [152] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [152] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [151] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [151] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [150] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [150] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [149] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [149] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [148] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [148] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [147] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [147] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [146] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [146] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [145] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [145] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [144] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [144] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [143] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [143] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [142] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [142] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [141] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [141] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [140] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [140] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [139] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [139] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [159] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [159] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [190] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [190] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [189] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [189] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [188] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [188] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [187] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [187] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [186] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [186] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [185] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [185] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [184] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [184] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [183] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [183] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [182] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [182] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [181] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [181] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [180] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [180] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [179] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [179] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [178] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [178] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [177] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [177] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [176] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [176] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [175] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [175] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [174] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [174] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [173] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [173] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [172] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [172] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [171] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [171] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [191] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [191] "logic dsm_status[511:0]" +Toggle 1to0 csr2re_dsm_base [62] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [62] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [61] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [61] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [60] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [60] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [59] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [59] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [58] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [58] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [57] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [57] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [56] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [56] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [55] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [55] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [54] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [54] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [53] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [53] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [52] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [52] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [51] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [51] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [50] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [50] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [49] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [49] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [48] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [48] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [63] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [63] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 re2csr_error [4] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [2] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [2] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [1] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [1] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [0] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [0] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [3] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [3] "logic re2csr_error[31:0]" +Toggle 1to0 ErrorVector [2] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [2] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [1] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [1] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [0] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [0] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [4] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [3] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [3] "logic ErrorVector[31:0]" +Toggle re2csr_num_wrpend "logic re2csr_num_wrpend[31:0]" +Toggle 1to0 rx_rsp_data1_in.dm_encoded "logic rx_rsp_data1_in.dm_encoded" +Toggle 0to1 rx_rsp_data1_in.dm_encoded "logic rx_rsp_data1_in.dm_encoded" +Toggle 1to0 rx_rsp_err "logic rx_rsp_err" +Toggle 0to1 rx_rsp_err "logic rx_rsp_err" +Toggle num_writes_pend "logic num_writes_pend[31:0]" +Toggle 1to0 ab_error_valid "logic ab_error_valid" +Toggle 0to1 ab_error_valid "logic ab_error_valid" +Toggle 1to0 ab_error_info [1] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [1] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [2] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [2] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [3] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [3] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [4] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [4] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [0] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [0] "logic ab_error_info[31:0]" +Toggle re2csr_num_rdpend "logic re2csr_num_rdpend[31:0]" +Toggle num_reads "logic num_reads[39:0]" +Toggle num_writes "logic num_writes[39:0]" +Toggle avmm_num_reads "net avmm_num_reads[39:0]" +Toggle avmm_num_writes "net avmm_num_writes[39:0]" +Toggle re2csr_num_reads "logic re2csr_num_reads[31:0]" +Toggle re2csr_num_writes "logic re2csr_num_writes[31:0]" +Toggle tx_if_pcie_len "logic tx_if_pcie_len[23:0]" +Toggle csr2re_num_lines "logic csr2re_num_lines[31:0]" +Toggle csr_num_lines "logic csr_num_lines[31:0]" +Toggle csr_dsm_addr "logic csr_dsm_addr[63:0]" +Toggle MmioCplHdr.low_addr "logic MmioCplHdr.low_addr[6:0]" +Toggle tx_req_dout_pcie_dm_hdr.host_addr_m "logic tx_req_dout_pcie_dm_hdr.host_addr_m[29:0]" +Toggle tx_req_dout_pcie_pu_hdr.host_addr_l "logic tx_req_dout_pcie_pu_hdr.host_addr_l[29:0]" +Toggle host_addr "logic host_addr[63:0]" +Toggle tx_if_pcie_addr "logic tx_if_pcie_addr[63:0]" +Toggle num_reads_pend "logic num_reads_pend[31:0]" +Toggle MmioCplData "logic MmioCplData[255:0]" +Toggle mmio_rsp_din "logic mmio_rsp_din[511:0]" +Toggle mmio_rsp_dout "logic mmio_rsp_dout[511:0]" +Toggle 1to0 intr_vec_num [14] "logic intr_vec_num[15:0]" +Toggle 0to1 intr_vec_num [14] "logic intr_vec_num[15:0]" +Toggle 1to0 intr_vec_num [13] "logic intr_vec_num[15:0]" +Toggle 0to1 intr_vec_num [13] "logic intr_vec_num[15:0]" +Toggle 1to0 intr_vec_num [12] "logic intr_vec_num[15:0]" +Toggle 0to1 intr_vec_num [12] "logic intr_vec_num[15:0]" +Toggle 1to0 intr_vec_num [11] "logic intr_vec_num[15:0]" +Toggle 0to1 intr_vec_num [11] "logic intr_vec_num[15:0]" +Toggle 1to0 intr_vec_num [10] "logic intr_vec_num[15:0]" +Toggle 0to1 intr_vec_num [10] "logic intr_vec_num[15:0]" +Toggle 1to0 intr_vec_num [9] "logic intr_vec_num[15:0]" +Toggle 0to1 intr_vec_num [9] "logic intr_vec_num[15:0]" +Toggle 1to0 intr_vec_num [8] "logic intr_vec_num[15:0]" +Toggle 0to1 intr_vec_num [8] "logic intr_vec_num[15:0]" +Toggle 1to0 intr_vec_num [7] "logic intr_vec_num[15:0]" +Toggle 0to1 intr_vec_num [7] "logic intr_vec_num[15:0]" +Toggle 1to0 intr_vec_num [6] "logic intr_vec_num[15:0]" +Toggle 0to1 intr_vec_num [6] "logic intr_vec_num[15:0]" +Toggle 1to0 intr_vec_num [5] "logic intr_vec_num[15:0]" +Toggle 0to1 intr_vec_num [5] "logic intr_vec_num[15:0]" +Toggle 1to0 intr_vec_num [4] "logic intr_vec_num[15:0]" +Toggle 0to1 intr_vec_num [4] "logic intr_vec_num[15:0]" +Toggle 1to0 intr_vec_num [3] "logic intr_vec_num[15:0]" +Toggle 0to1 intr_vec_num [3] "logic intr_vec_num[15:0]" +Toggle 1to0 intr_vec_num [2] "logic intr_vec_num[15:0]" +Toggle 0to1 intr_vec_num [2] "logic intr_vec_num[15:0]" +Toggle 1to0 intr_vec_num [15] "logic intr_vec_num[15:0]" +Toggle 0to1 intr_vec_num [15] "logic intr_vec_num[15:0]" +Toggle 1to0 dsm_number [13] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [13] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [12] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [12] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [11] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [11] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [10] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [10] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [9] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [9] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [8] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [8] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [7] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [7] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [6] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [6] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [5] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [5] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [4] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [4] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [3] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [3] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [2] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [2] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [1] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [1] "logic dsm_number[14:0]" +Toggle 1to0 dsm_number [14] "logic dsm_number[14:0]" +Toggle 0to1 dsm_number [14] "logic dsm_number[14:0]" +Toggle 1to0 csr_intr [30] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [30] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [29] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [29] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [28] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [28] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [27] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [27] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [26] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [26] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [25] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [25] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [24] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [24] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [23] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [23] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [22] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [22] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [21] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [21] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [20] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [20] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [19] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [19] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [18] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [18] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [15] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [15] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [14] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [14] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [13] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [13] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [12] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [12] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [11] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [11] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [10] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [10] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [9] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [9] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [8] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [8] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [7] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [7] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [6] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [6] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [5] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [5] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [4] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [4] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [3] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [3] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [2] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [2] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [1] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [1] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [0] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [0] "logic csr_intr[31:0]" +Toggle 1to0 csr_intr [31] "logic csr_intr[31:0]" +Toggle 0to1 csr_intr [31] "logic csr_intr[31:0]" +Toggle 1to0 csr2re_interrupt0 [14] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [14] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [13] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [13] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [12] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [12] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [11] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [11] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [10] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [10] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [9] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [9] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [8] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [8] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [7] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [7] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [6] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [6] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [5] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [5] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [4] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [4] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [3] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [3] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [2] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [2] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [1] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [1] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [0] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [0] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [15] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [15] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [30] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [30] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [29] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [29] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [28] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [28] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [27] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [27] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [26] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [26] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [25] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [25] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [24] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [24] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [23] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [23] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [22] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [22] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [21] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [21] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [20] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [20] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [19] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [19] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [18] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [18] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [31] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [31] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 dsm_status [34] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [34] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [33] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [33] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [32] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [32] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [31] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [31] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [30] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [30] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [29] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [29] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [28] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [28] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [27] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [27] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [26] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [26] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [25] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [25] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [24] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [24] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [23] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [23] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [22] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [22] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [21] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [21] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [20] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [20] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [19] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [19] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [18] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [18] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [17] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [17] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [16] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [16] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [15] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [15] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [14] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [14] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [13] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [13] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [12] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [12] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [11] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [11] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [10] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [10] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [9] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [9] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [8] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [8] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [7] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [7] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [6] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [6] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [5] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [5] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [4] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [4] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [3] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [3] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [2] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [2] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [35] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [35] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [62] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [62] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [61] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [61] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [60] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [60] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [59] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [59] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [58] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [58] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [57] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [57] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [56] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [56] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [55] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [55] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [54] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [54] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [53] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [53] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [52] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [52] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [51] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [51] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [50] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [50] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [49] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [49] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [48] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [48] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [47] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [47] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [46] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [46] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [45] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [45] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [44] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [44] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [43] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [43] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [42] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [42] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [41] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [41] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [40] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [40] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [39] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [39] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [38] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [38] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [37] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [37] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [63] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [63] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [126] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [126] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [125] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [125] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [124] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [124] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [123] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [123] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [122] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [122] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [121] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [121] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [120] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [120] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [119] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [119] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [118] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [118] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [117] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [117] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [116] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [116] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [115] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [115] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [114] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [114] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [113] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [113] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [112] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [112] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [111] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [111] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [110] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [110] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [109] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [109] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [108] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [108] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [107] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [107] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [106] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [106] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [105] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [105] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [104] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [104] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [127] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [127] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [222] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [222] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [221] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [221] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [220] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [220] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [219] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [219] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [218] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [218] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [217] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [217] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [216] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [216] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [215] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [215] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [214] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [214] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [213] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [213] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [212] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [212] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [211] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [211] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [210] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [210] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [209] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [209] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [208] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [208] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [223] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [223] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [510] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [510] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [509] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [509] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [508] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [508] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [507] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [507] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [506] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [506] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [505] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [505] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [504] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [504] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [503] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [503] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [502] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [502] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [501] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [501] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [500] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [500] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [499] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [499] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [498] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [498] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [497] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [497] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [496] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [496] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [495] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [495] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [494] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [494] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [493] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [493] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [492] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [492] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [491] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [491] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [490] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [490] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [489] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [489] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [488] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [488] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [487] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [487] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [486] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [486] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [485] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [485] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [484] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [484] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [483] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [483] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [482] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [482] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [481] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [481] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [480] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [480] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [479] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [479] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [478] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [478] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [477] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [477] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [476] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [476] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [475] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [475] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [474] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [474] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [473] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [473] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [472] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [472] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [471] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [471] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [470] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [470] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [469] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [469] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [468] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [468] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [467] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [467] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [466] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [466] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [465] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [465] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [464] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [464] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [463] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [463] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [462] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [462] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [461] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [461] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [460] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [460] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [459] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [459] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [458] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [458] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [457] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [457] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [456] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [456] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [455] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [455] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [454] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [454] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [453] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [453] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [452] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [452] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [451] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [451] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [450] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [450] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [449] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [449] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [448] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [448] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [447] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [447] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [446] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [446] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [445] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [445] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [444] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [444] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [443] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [443] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [442] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [442] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [441] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [441] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [440] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [440] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [439] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [439] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [438] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [438] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [437] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [437] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [436] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [436] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [435] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [435] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [434] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [434] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [433] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [433] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [432] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [432] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [431] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [431] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [430] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [430] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [429] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [429] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [428] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [428] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [427] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [427] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [426] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [426] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [425] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [425] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [424] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [424] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [423] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [423] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [422] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [422] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [421] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [421] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [420] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [420] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [419] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [419] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [418] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [418] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [417] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [417] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [416] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [416] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [415] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [415] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [414] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [414] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [413] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [413] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [412] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [412] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [411] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [411] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [410] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [410] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [409] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [409] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [408] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [408] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [407] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [407] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [406] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [406] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [405] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [405] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [404] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [404] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [403] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [403] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [402] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [402] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [401] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [401] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [400] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [400] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [399] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [399] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [398] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [398] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [397] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [397] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [396] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [396] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [395] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [395] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [394] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [394] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [393] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [393] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [392] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [392] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [391] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [391] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [390] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [390] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [389] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [389] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [388] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [388] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [387] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [387] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [386] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [386] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [385] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [385] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [384] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [384] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [383] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [383] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [382] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [382] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [381] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [381] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [380] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [380] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [379] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [379] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [378] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [378] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [377] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [377] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [376] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [376] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [375] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [375] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [374] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [374] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [373] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [373] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [372] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [372] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [371] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [371] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [370] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [370] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [369] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [369] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [368] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [368] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [367] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [367] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [366] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [366] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [365] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [365] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [364] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [364] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [363] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [363] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [362] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [362] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [361] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [361] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [360] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [360] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [359] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [359] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [358] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [358] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [357] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [357] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [356] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [356] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [355] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [355] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [354] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [354] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [353] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [353] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [352] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [352] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [351] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [351] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [350] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [350] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [349] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [349] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [348] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [348] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [347] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [347] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [346] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [346] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [345] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [345] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [344] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [344] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [343] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [343] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [342] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [342] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [341] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [341] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [340] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [340] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [339] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [339] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [338] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [338] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [337] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [337] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [336] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [336] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [335] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [335] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [334] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [334] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [333] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [333] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [332] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [332] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [331] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [331] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [330] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [330] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [329] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [329] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [328] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [328] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [327] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [327] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [326] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [326] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [325] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [325] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [324] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [324] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [323] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [323] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [322] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [322] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [321] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [321] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [320] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [320] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [319] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [319] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [318] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [318] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [317] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [317] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [316] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [316] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [315] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [315] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [314] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [314] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [313] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [313] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [312] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [312] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [311] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [311] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [310] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [310] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [309] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [309] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [308] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [308] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [307] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [307] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [306] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [306] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [305] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [305] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [304] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [304] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [303] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [303] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [302] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [302] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [301] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [301] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [300] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [300] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [299] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [299] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [298] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [298] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [297] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [297] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [296] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [296] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [295] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [295] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [294] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [294] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [293] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [293] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [292] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [292] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [291] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [291] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [290] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [290] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [289] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [289] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [288] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [288] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [287] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [287] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [286] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [286] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [285] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [285] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [284] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [284] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [283] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [283] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [282] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [282] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [281] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [281] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [280] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [280] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [279] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [279] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [278] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [278] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [277] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [277] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [276] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [276] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [275] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [275] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [274] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [274] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [273] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [273] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [272] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [272] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [271] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [271] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [270] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [270] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [269] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [269] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [268] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [268] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [267] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [267] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [266] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [266] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [265] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [265] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [264] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [264] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [263] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [263] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [262] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [262] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [261] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [261] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [260] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [260] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [259] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [259] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [258] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [258] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [257] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [257] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [256] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [256] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [255] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [255] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [254] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [254] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [253] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [253] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [252] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [252] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [251] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [251] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [250] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [250] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [249] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [249] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [248] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [248] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [247] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [247] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [246] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [246] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [245] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [245] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [244] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [244] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [243] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [243] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [242] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [242] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [241] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [241] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [240] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [240] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [239] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [239] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [238] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [238] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [237] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [237] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [236] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [236] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [235] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [235] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [234] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [234] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [233] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [233] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [232] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [232] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [231] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [231] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [230] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [230] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [229] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [229] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [228] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [228] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [227] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [227] "logic dsm_status[511:0]" +Toggle 1to0 dsm_status [511] "logic dsm_status[511:0]" +Toggle 0to1 dsm_status [511] "logic dsm_status[511:0]" +Toggle 1to0 req_len_b2 [3] "logic req_len_b2[4:0]" +Toggle 0to1 req_len_b2 [3] "logic req_len_b2[4:0]" +Toggle 1to0 req_len_b2 [2] "logic req_len_b2[4:0]" +Toggle 0to1 req_len_b2 [2] "logic req_len_b2[4:0]" +Toggle 1to0 req_len_b2 [4] "logic req_len_b2[4:0]" +Toggle 0to1 req_len_b2 [4] "logic req_len_b2[4:0]" +ANNOTATION: " Cannot be covered functionally " +Toggle avmm_num_ticks_l "net avmm_num_ticks_l[19:0]" +Toggle 1to0 csr2re_cfg [62] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [62] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [61] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [61] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [60] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [60] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [59] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [59] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [58] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [58] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [57] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [57] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [56] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [56] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [55] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [55] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [54] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [54] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [53] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [53] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [52] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [52] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [51] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [51] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [50] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [50] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [49] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [49] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [48] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [48] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [47] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [47] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [46] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [46] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [45] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [45] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [44] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [44] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [43] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [43] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [42] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [42] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [41] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [41] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [40] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [40] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [39] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [39] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [38] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [38] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [37] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [37] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [36] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [36] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [35] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [35] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [34] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [34] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [33] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [33] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [32] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [32] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [31] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [31] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [30] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [30] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [19] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [19] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [18] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [18] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [17] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [17] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [16] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [16] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [15] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [15] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [14] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [14] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [63] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [63] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr_cfg [18] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [18] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [17] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [17] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [16] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [16] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [15] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [15] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [14] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [14] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [19] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [19] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [62] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [62] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [61] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [61] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [60] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [60] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [59] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [59] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [58] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [58] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [57] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [57] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [56] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [56] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [55] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [55] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [54] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [54] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [53] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [53] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [52] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [52] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [51] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [51] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [50] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [50] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [49] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [49] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [48] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [48] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [47] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [47] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [46] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [46] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [45] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [45] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [44] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [44] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [43] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [43] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [42] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [42] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [41] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [41] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [40] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [40] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [39] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [39] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [38] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [38] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [37] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [37] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [36] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [36] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [35] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [35] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [34] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [34] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [33] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [33] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [32] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [32] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [31] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [31] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [30] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [30] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [63] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [63] "logic csr_cfg[63:0]" +ANNOTATION: " Cannot be covered functionally " +Toggle num_ticks_l "logic num_ticks_l[19:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.length_h "logic tx_req_dout_pcie_dm_hdr.length_h[11:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.length "logic MmioCplHdr.length[9:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.vector_num "logic tx_intr_dm_hdr.vector_num[15:0]" +ANNOTATION: " Cannot be covered functionally " +Toggle axi_tx_if_p.user "logic axi_tx_if_p.user[9:0]" +ANNOTATION: " Cannot be covered functionally " +Toggle axi_rx_if_T2.user "logic axi_rx_if_T2.user[9:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.byte_count "logic MmioCplHdr.byte_count[11:0]" +Toggle 1to0 csr_ctl [30] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [30] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [29] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [29] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [28] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [28] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [27] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [27] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [26] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [26] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [25] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [25] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [24] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [24] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [23] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [23] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [22] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [22] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [21] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [21] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [20] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [20] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [19] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [19] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [18] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [18] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [17] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [17] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [16] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [16] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [15] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [15] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [14] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [14] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [13] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [13] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [12] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [12] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [11] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [11] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [10] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [10] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [9] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [9] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [8] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [8] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [7] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [7] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [6] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [6] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [5] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [5] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [4] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [4] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [3] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [3] "logic csr_ctl[31:0]" +Toggle 1to0 csr_ctl [31] "logic csr_ctl[31:0]" +Toggle 0to1 csr_ctl [31] "logic csr_ctl[31:0]" +Toggle 1to0 csr2re_ctl [30] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [30] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [29] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [29] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [28] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [28] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [27] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [27] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [26] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [26] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [25] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [25] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [24] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [24] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [23] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [23] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [22] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [22] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [21] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [21] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [20] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [20] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [19] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [19] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [18] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [18] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [17] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [17] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [16] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [16] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [15] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [15] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [14] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [14] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [13] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [13] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [12] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [12] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [11] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [11] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [10] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [10] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [9] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [9] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [8] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [8] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [7] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [7] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [6] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [6] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [5] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [5] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [4] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [4] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [3] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [3] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [31] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [31] "logic csr2re_ctl[31:0]" +Toggle 1to0 re2csr_error [30] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [30] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [29] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [29] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [28] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [28] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [27] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [27] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [26] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [26] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [25] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [25] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [24] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [24] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [23] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [23] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [22] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [22] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [21] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [21] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [20] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [20] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [19] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [19] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [18] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [18] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [17] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [17] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [16] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [16] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [15] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [15] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [14] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [14] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [13] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [13] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [12] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [12] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [11] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [11] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [10] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [10] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [9] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [9] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [8] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [8] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [7] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [7] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [6] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [6] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [5] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [5] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [31] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [31] "logic re2csr_error[31:0]" +Toggle 1to0 ErrorVector [30] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [30] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [29] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [29] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [28] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [28] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [27] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [27] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [26] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [26] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [25] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [25] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [24] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [24] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [23] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [23] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [22] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [22] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [21] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [21] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [20] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [20] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [19] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [19] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [18] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [18] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [17] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [17] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [16] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [16] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [15] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [15] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [14] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [14] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [13] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [13] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [12] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [12] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [11] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [11] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [10] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [10] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [9] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [9] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [8] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [8] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [7] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [7] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [6] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [6] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [5] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [5] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [31] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [31] "logic ErrorVector[31:0]" +Toggle 1to0 tx_req_dout_pcie_pu_hdr.attr.rsvd1 "logic tx_req_dout_pcie_pu_hdr.attr.rsvd1" +Toggle 0to1 tx_req_dout_pcie_pu_hdr.attr.rsvd1 "logic tx_req_dout_pcie_pu_hdr.attr.rsvd1" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.attr.rsvd2 "logic tx_req_dout_pcie_pu_hdr.attr.rsvd2[1:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.bar_number "logic tx_req_dout_pcie_pu_hdr.bar_number[6:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.metadata_h "logic tx_req_dout_pcie_pu_hdr.metadata_h[31:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.metadata_l "logic tx_req_dout_pcie_pu_hdr.metadata_l[31:0]" +Toggle 1to0 tx_req_dout_pcie_pu_hdr.mm_mode "logic tx_req_dout_pcie_pu_hdr.mm_mode" +Toggle 0to1 tx_req_dout_pcie_pu_hdr.mm_mode "logic tx_req_dout_pcie_pu_hdr.mm_mode" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.pf_num "logic tx_req_dout_pcie_pu_hdr.pf_num[2:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.pref "logic tx_req_dout_pcie_pu_hdr.pref[23:0]" +Toggle 1to0 tx_req_dout_pcie_pu_hdr.pref_present "logic tx_req_dout_pcie_pu_hdr.pref_present" +Toggle 0to1 tx_req_dout_pcie_pu_hdr.pref_present "logic tx_req_dout_pcie_pu_hdr.pref_present" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.pref_type "logic tx_req_dout_pcie_pu_hdr.pref_type[4:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.req_id "logic tx_req_dout_pcie_pu_hdr.req_id[15:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.rsvd2 "logic tx_req_dout_pcie_pu_hdr.rsvd2[3:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.rsvd3 "logic tx_req_dout_pcie_pu_hdr.rsvd3[1:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.slot_num "logic tx_req_dout_pcie_pu_hdr.slot_num[4:0]" +Toggle 1to0 tx_req_dout_pcie_pu_hdr.vf_active "logic tx_req_dout_pcie_pu_hdr.vf_active" +Toggle 0to1 tx_req_dout_pcie_pu_hdr.vf_active "logic tx_req_dout_pcie_pu_hdr.vf_active" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.vf_num "logic tx_req_dout_pcie_pu_hdr.vf_num[10:0]" +Toggle 1to0 tx_req_err "logic tx_req_err" +Toggle 0to1 tx_req_err "logic tx_req_err" +Toggle 1to0 tx_req_perr "logic tx_req_perr" +Toggle 0to1 tx_req_perr "logic tx_req_perr" +ANNOTATION: " Header " +Toggle vf_id "logic vf_id[10:0]" +Toggle 1to0 tx_req_dout_pcie_pu_hdr.attr.TH "logic tx_req_dout_pcie_pu_hdr.attr.TH" +Toggle 0to1 tx_req_dout_pcie_pu_hdr.attr.TH "logic tx_req_dout_pcie_pu_hdr.attr.TH" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.TC "logic tx_req_dout_pcie_dm_hdr.TC[2:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.attr.AT "logic tx_req_dout_pcie_dm_hdr.attr.AT[1:0]" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.attr.EP "logic tx_req_dout_pcie_dm_hdr.attr.EP" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.attr.EP "logic tx_req_dout_pcie_dm_hdr.attr.EP" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.attr.LN "logic tx_req_dout_pcie_dm_hdr.attr.LN" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.attr.LN "logic tx_req_dout_pcie_dm_hdr.attr.LN" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.attr.TD "logic tx_req_dout_pcie_dm_hdr.attr.TD" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.attr.TD "logic tx_req_dout_pcie_dm_hdr.attr.TD" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.attr.TH "logic tx_req_dout_pcie_dm_hdr.attr.TH" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.attr.TH "logic tx_req_dout_pcie_dm_hdr.attr.TH" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.attr.rsvd1 "logic tx_req_dout_pcie_dm_hdr.attr.rsvd1" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.attr.rsvd1 "logic tx_req_dout_pcie_dm_hdr.attr.rsvd1" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.attr.rsvd2 "logic tx_req_dout_pcie_dm_hdr.attr.rsvd2[1:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.host_addr_l "logic tx_req_dout_pcie_dm_hdr.host_addr_l[1:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.metadata_h "logic tx_req_dout_pcie_dm_hdr.metadata_h[31:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.metadata_l "logic tx_req_dout_pcie_dm_hdr.metadata_l[31:0]" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.mm_mode "logic tx_req_dout_pcie_dm_hdr.mm_mode" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.mm_mode "logic tx_req_dout_pcie_dm_hdr.mm_mode" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.pf_num "logic tx_req_dout_pcie_dm_hdr.pf_num[2:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.pref "logic tx_req_dout_pcie_dm_hdr.pref[23:0]" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.pref_present "logic tx_req_dout_pcie_dm_hdr.pref_present" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.pref_present "logic tx_req_dout_pcie_dm_hdr.pref_present" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.pref_type "logic tx_req_dout_pcie_dm_hdr.pref_type[4:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.rsvd3 "logic tx_req_dout_pcie_dm_hdr.rsvd3[6:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.rsvd4 "logic tx_req_dout_pcie_dm_hdr.rsvd4[3:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.rsvd5 "logic tx_req_dout_pcie_dm_hdr.rsvd5[1:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.rsvd6 "logic tx_req_dout_pcie_dm_hdr.rsvd6[7:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.slot_num "logic tx_req_dout_pcie_dm_hdr.slot_num[4:0]" +Toggle 1to0 tx_req_dout_pcie_dm_hdr.vf_active "logic tx_req_dout_pcie_dm_hdr.vf_active" +Toggle 0to1 tx_req_dout_pcie_dm_hdr.vf_active "logic tx_req_dout_pcie_dm_hdr.vf_active" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.vf_num "logic tx_req_dout_pcie_dm_hdr.vf_num[10:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.PH "logic tx_req_dout_pcie_pu_hdr.PH[1:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.TC "logic tx_req_dout_pcie_pu_hdr.TC[2:0]" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_pu_hdr.attr.AT "logic tx_req_dout_pcie_pu_hdr.attr.AT[1:0]" +Toggle 1to0 tx_req_dout_pcie_pu_hdr.attr.EP "logic tx_req_dout_pcie_pu_hdr.attr.EP" +Toggle 0to1 tx_req_dout_pcie_pu_hdr.attr.EP "logic tx_req_dout_pcie_pu_hdr.attr.EP" +Toggle 1to0 tx_req_dout_pcie_pu_hdr.attr.LN "logic tx_req_dout_pcie_pu_hdr.attr.LN" +Toggle 0to1 tx_req_dout_pcie_pu_hdr.attr.LN "logic tx_req_dout_pcie_pu_hdr.attr.LN" +Toggle 1to0 tx_req_dout_pcie_pu_hdr.attr.TD "logic tx_req_dout_pcie_pu_hdr.attr.TD" +Toggle 0to1 tx_req_dout_pcie_pu_hdr.attr.TD "logic tx_req_dout_pcie_pu_hdr.attr.TD" +ANNOTATION: " Header " +Toggle tx_req_dout_pcie_dm_hdr.PH "logic tx_req_dout_pcie_dm_hdr.PH[1:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.rsvd3 "logic tx_intr_dm_hdr.rsvd3[6:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.rsvd4 "logic tx_intr_dm_hdr.rsvd4[3:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.rsvd5 "logic tx_intr_dm_hdr.rsvd5[1:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.rsvd6 "logic tx_intr_dm_hdr.rsvd6[31:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.rsvd7 "logic tx_intr_dm_hdr.rsvd7[15:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.rsvd8 "logic tx_intr_dm_hdr.rsvd8[31:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.rsvd9 "logic tx_intr_dm_hdr.rsvd9[23:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.slot_num "logic tx_intr_dm_hdr.slot_num[4:0]" +Toggle 1to0 tx_intr_dm_hdr.vf_active "logic tx_intr_dm_hdr.vf_active" +Toggle 0to1 tx_intr_dm_hdr.vf_active "logic tx_intr_dm_hdr.vf_active" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.vf_num "logic tx_intr_dm_hdr.vf_num[10:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.rsvd2 "logic tx_intr_dm_hdr.rsvd2[31:0]" +Toggle 1to0 axi_rx_if_T2.sop "logic axi_rx_if_T2.sop" +Toggle 0to1 axi_rx_if_T2.sop "logic axi_rx_if_T2.sop" +ANNOTATION: " Not connected " +Toggle csr2re_stride "logic csr2re_stride[31:0]" +ANNOTATION: " Connected to fifo signals " +Toggle mmio_rsp_ecc "logic mmio_rsp_ecc[1:0]" +Toggle 1to0 mmio_rsp_err "logic mmio_rsp_err" +Toggle 0to1 mmio_rsp_err "logic mmio_rsp_err" +Toggle 1to0 mmio_rsp_full "logic mmio_rsp_full" +Toggle 0to1 mmio_rsp_full "logic mmio_rsp_full" +ANNOTATION: " Cannot be covered functionally " +Toggle num_ticks_h "logic num_ticks_h[19:0]" +ANNOTATION: " Header " +Toggle pf_id "logic pf_id[2:0]" +Toggle 1to0 rx_rsp_data1_in.eop "logic rx_rsp_data1_in.eop" +Toggle 0to1 rx_rsp_data1_in.eop "logic rx_rsp_data1_in.eop" +Toggle 1to0 rx_rsp_data1_in.sop "logic rx_rsp_data1_in.sop" +Toggle 0to1 rx_rsp_data1_in.sop "logic rx_rsp_data1_in.sop" +Toggle 1to0 rx_rsp_perr "logic rx_rsp_perr" +Toggle 0to1 rx_rsp_perr "logic rx_rsp_perr" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.fmt_type "logic tx_intr_dm_hdr.fmt_type[7:0]" +Toggle 1to0 tx_intr_dm_hdr.mm_mode "logic tx_intr_dm_hdr.mm_mode" +Toggle 0to1 tx_intr_dm_hdr.mm_mode "logic tx_intr_dm_hdr.mm_mode" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.pf_num "logic tx_intr_dm_hdr.pf_num[2:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.pref "logic tx_intr_dm_hdr.pref[23:0]" +Toggle 1to0 tx_intr_dm_hdr.pref_present "logic tx_intr_dm_hdr.pref_present" +Toggle 0to1 tx_intr_dm_hdr.pref_present "logic tx_intr_dm_hdr.pref_present" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.pref_type "logic tx_intr_dm_hdr.pref_type[4:0]" +ANNOTATION: " Header " +Toggle tx_intr_dm_hdr.rsvd1 "logic tx_intr_dm_hdr.rsvd1[31:0]" +ANNOTATION: " Cannot be covered functionally " +Toggle avmm_num_ticks_h "net avmm_num_ticks_h[19:0]" +Toggle 1to0 MmioCplHdr.attr.EP "logic MmioCplHdr.attr.EP" +Toggle 0to1 MmioCplHdr.attr.EP "logic MmioCplHdr.attr.EP" +Toggle 1to0 MmioCplHdr.attr.LN "logic MmioCplHdr.attr.LN" +Toggle 0to1 MmioCplHdr.attr.LN "logic MmioCplHdr.attr.LN" +Toggle 1to0 MmioCplHdr.attr.TD "logic MmioCplHdr.attr.TD" +Toggle 0to1 MmioCplHdr.attr.TD "logic MmioCplHdr.attr.TD" +Toggle 1to0 MmioCplHdr.attr.TH "logic MmioCplHdr.attr.TH" +Toggle 0to1 MmioCplHdr.attr.TH "logic MmioCplHdr.attr.TH" +Toggle 1to0 MmioCplHdr.bcm "logic MmioCplHdr.bcm" +Toggle 0to1 MmioCplHdr.bcm "logic MmioCplHdr.bcm" +ANNOTATION: " Header " +Toggle MmioCplHdr.comp_id "logic MmioCplHdr.comp_id[15:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.cpl_status "logic MmioCplHdr.cpl_status[2:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.fmt_type "logic MmioCplHdr.fmt_type[7:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.metadata_h "logic MmioCplHdr.metadata_h[31:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.metadata_l "logic MmioCplHdr.metadata_l[31:0]" +Toggle 1to0 MmioCplHdr.mm_mode "logic MmioCplHdr.mm_mode" +Toggle 0to1 MmioCplHdr.mm_mode "logic MmioCplHdr.mm_mode" +ANNOTATION: " Header " +Toggle MmioCplHdr.pf_num "logic MmioCplHdr.pf_num[2:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.pref "logic MmioCplHdr.pref[23:0]" +Toggle 1to0 MmioCplHdr.pref_present "logic MmioCplHdr.pref_present" +Toggle 0to1 MmioCplHdr.pref_present "logic MmioCplHdr.pref_present" +ANNOTATION: " Header " +Toggle MmioCplHdr.pref_type "logic MmioCplHdr.pref_type[4:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.rsvd1 "logic MmioCplHdr.rsvd1[6:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.rsvd2 "logic MmioCplHdr.rsvd2[3:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.rsvd3 "logic MmioCplHdr.rsvd3[1:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.rsvd4 "logic MmioCplHdr.rsvd4[31:0]" +Toggle 1to0 MmioCplHdr.rsvd5 "logic MmioCplHdr.rsvd5" +Toggle 0to1 MmioCplHdr.rsvd5 "logic MmioCplHdr.rsvd5" +ANNOTATION: " Header " +Toggle MmioCplHdr.slot_num "logic MmioCplHdr.slot_num[4:0]" +Toggle 1to0 MmioCplHdr.vf_active "logic MmioCplHdr.vf_active" +Toggle 0to1 MmioCplHdr.vf_active "logic MmioCplHdr.vf_active" +ANNOTATION: " Header " +Toggle MmioCplHdr.vf_num "logic MmioCplHdr.vf_num[10:0]" +ANNOTATION: " Header " +Toggle MmioCplHdr.attr.AT "logic MmioCplHdr.attr.AT[1:0]" +Toggle 0to1 ab_error_info [31] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [31] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [5] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [5] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [6] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [6] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [7] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [7] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [8] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [8] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [9] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [9] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [10] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [10] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [11] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [11] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [12] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [12] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [13] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [13] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [14] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [14] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [15] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [15] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [16] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [16] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [17] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [17] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [18] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [18] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [19] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [19] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [20] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [20] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [21] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [21] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [22] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [22] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [23] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [23] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [24] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [24] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [25] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [25] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [26] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [26] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [27] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [27] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [28] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [28] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [29] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [29] "logic ab_error_info[31:0]" +Toggle 0to1 ab_error_info [30] "logic ab_error_info[31:0]" +Toggle 1to0 ab_error_info [30] "logic ab_error_info[31:0]" +CHECKSUM: "4144234428 2624707494" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_rx_rsp_q.even_que +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (23) "(!Resetb) 0,-,-,-,-,-,1,default,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (2) "(!Resetb) 0,(fifo_w & (fifo_cntr == (2 ** DEPTH))) ,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (1) "(!Resetb) 0,(fifo_ren & (!valid[3])) ,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 6 "2342593151" "(DEPTH > 1)" (1) "(DEPTH > 1) 0" +ANNOTATION: " Depends on parameter " +Branch 1 "3108923996" "REG_OUT" (0) "REG_OUT 1,-" +ANNOTATION: " Depends on parameter " +Branch 0 "2726336106" "REG_IN" (0) "REG_IN 1" +CHECKSUM: "4144234428 2624707494" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_rx_rsp_q.odd_que +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (23) "(!Resetb) 0,-,-,-,-,-,1,default,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (2) "(!Resetb) 0,(fifo_w & (fifo_cntr == (2 ** DEPTH))) ,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (1) "(!Resetb) 0,(fifo_ren & (!valid[3])) ,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 6 "2342593151" "(DEPTH > 1)" (1) "(DEPTH > 1) 0" +ANNOTATION: " Depends on parameter " +Branch 1 "3108923996" "REG_OUT" (0) "REG_OUT 1,-" +ANNOTATION: " Depends on parameter " +Branch 0 "2726336106" "REG_IN" (0) "REG_IN 1" +CHECKSUM: "4144234428 2624707494" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_tx_req_q.even_que +ANNOTATION: " Depends on parameter " +Branch 1 "3108923996" "REG_OUT" (0) "REG_OUT 1,-" +ANNOTATION: " Depends on parameter " +Branch 6 "2342593151" "(DEPTH > 1)" (1) "(DEPTH > 1) 0" +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (2) "(!Resetb) 0,(fifo_w & (fifo_cntr == (2 ** DEPTH))) ,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (23) "(!Resetb) 0,-,-,-,-,-,1,default,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (1) "(!Resetb) 0,(fifo_ren & (!valid[3])) ,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 0 "2726336106" "REG_IN" (0) "REG_IN 1" +CHECKSUM: "4144234428 2624707494" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_tx_req_q.odd_que +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (23) "(!Resetb) 0,-,-,-,-,-,1,default,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 1 "3108923996" "REG_OUT" (0) "REG_OUT 1,-" +ANNOTATION: " Depends on parameter " +Branch 6 "2342593151" "(DEPTH > 1)" (1) "(DEPTH > 1) 0" +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (2) "(!Resetb) 0,(fifo_w & (fifo_cntr == (2 ** DEPTH))) ,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 9 "3296052676" "(!Resetb)" (1) "(!Resetb) 0,(fifo_ren & (!valid[3])) ,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 0 "2726336106" "REG_IN" (0) "REG_IN 1" +CHECKSUM: "3520213052 1995093083" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_rx_rsp_q +ANNOTATION: " Depends on parameter " +Branch 3 "2924126281" "REG_IN" (0) "REG_IN 1,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 2 "4210727352" "REG_OUT" (1) "REG_OUT 1,0,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 2 "4210727352" "REG_OUT" (2) "REG_OUT 1,-,1,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 2 "4210727352" "REG_OUT" (3) "REG_OUT 1,-,0,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 2 "4210727352" "REG_OUT" (0) "REG_OUT 1,1,-,-,-,-,-,-,-,-,-" +CHECKSUM: "3520213052 1995093083" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_tx_req_q +ANNOTATION: " Depends on parameter " +Branch 3 "2924126281" "REG_IN" (2) "REG_IN 0,0,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 3 "2924126281" "REG_IN" (3) "REG_IN 0,-,1,-,-" +ANNOTATION: " Depends on parameter " +Branch 3 "2924126281" "REG_IN" (4) "REG_IN 0,-,0,-,-" +ANNOTATION: " Depends on parameter " +Branch 3 "2924126281" "REG_IN" (5) "REG_IN 0,-,-,1,-" +ANNOTATION: " Depends on parameter " +Branch 3 "2924126281" "REG_IN" (6) "REG_IN 0,-,-,0,-" +ANNOTATION: " Depends on parameter " +Branch 3 "2924126281" "REG_IN" (7) "REG_IN 0,-,-,-,1" +ANNOTATION: " Depends on parameter " +Branch 3 "2924126281" "REG_IN" (8) "REG_IN 0,-,-,-,0" +ANNOTATION: " Depends on parameter " +Branch 3 "2924126281" "REG_IN" (1) "REG_IN 0,1,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 2 "4210727352" "REG_OUT" (3) "REG_OUT 1,-,0,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 2 "4210727352" "REG_OUT" (0) "REG_OUT 1,1,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 2 "4210727352" "REG_OUT" (1) "REG_OUT 1,0,-,-,-,-,-,-,-,-,-" +ANNOTATION: " Depends on parameter " +Branch 2 "4210727352" "REG_OUT" (2) "REG_OUT 1,-,1,-,-,-,-,-,-,-,-" +CHECKSUM: "965016526 494745982" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_rdwr +Branch 12 "1083443347" "(!test_resetb)" (1) "(!test_resetb) 0,1" +Branch 13 "1239589818" "(test_start & ((total_len % req_len) != 0))" (0) "(test_start & ((total_len % req_len) != 0)) 1" +Branch 14 "1946039810" "(test_start & (total_len == 11'b0))" (0) "(test_start & (total_len == 11'b0)) 1" +Branch 15 "2459171571" "(|ErrorVector)" (0) "(|ErrorVector) 1" +CHECKSUM: "3520213052 2433635046" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_rx_rsp_q +ANNOTATION: " Quartus fifo- need not be generated " +Condition 2 "2816528903" "(raddr0[1] ? even_out : odd_out) 1 -1" +ANNOTATION: " Quartus fifo- need not be generated " +Condition 1 "3741229492" "(raddr0[0] ? odd_out : even_out) 1 -1" +CHECKSUM: "3520213052 2433635046" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_tx_req_q +Condition 12 "566936974" "(w_odd_even[0] ? ((wen0 & wen1)) : ((wen0 | wen1))) 1 -1" +ANNOTATION: " Depends on parameter " +Condition 13 "2184218986" "(((w_odd_even[1] & wen0)) ? din0 : din1) 1 -1" +Condition 14 "946017004" "(w_odd_even[1] ? ((wen0 | wen1)) : ((wen0 & wen1))) 1 -1" +ANNOTATION: " Depends on parameter " +Condition 11 "1114358066" "((((!w_odd_even[0]) & wen0)) ? din0 : din1) 1 -1" +ANNOTATION: " Depends on parameter " +Condition 2 "2816528903" "(raddr0[1] ? even_out : odd_out) 1 -1" +ANNOTATION: " Depends on parameter " +Condition 1 "3741229492" "(raddr0[0] ? odd_out : even_out) 1 -1" +CHECKSUM: "2618233009 2457344362" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req +Condition 7 "3847801509" "(use_dm_encoding ? tx_req_dout_pcie_dm_hdr : tx_req_dout_pcie_pu_hdr) 1 -1" (1 "0") +CHECKSUM: "2139909825 2328894433" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_lpbk +Toggle ram_rad "logic ram_rad[6:0]" +Toggle 1to0 clnum_ram_perr "logic clnum_ram_perr" +Toggle 0to1 clnum_ram_perr "logic clnum_ram_perr" +Toggle 1to0 emif_req_din [27] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [27] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [26] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [26] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [25] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [25] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [24] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [24] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [23] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [23] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [22] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [22] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [21] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [21] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [20] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [20] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [19] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [19] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [18] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [18] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [17] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [17] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [16] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [16] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [15] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [15] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [14] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [14] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [13] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [13] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [28] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [28] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [603] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [603] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [602] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [602] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [601] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [601] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [600] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [600] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [599] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [599] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [598] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [598] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [597] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [597] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [596] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [596] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [595] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [595] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [594] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [594] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [593] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [593] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [592] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [592] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [591] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [591] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [590] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [590] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [589] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [589] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [588] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [588] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [587] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [587] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [586] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [586] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [585] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [585] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [584] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [584] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [583] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [583] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [582] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [582] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [581] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [581] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [580] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [580] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [579] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [579] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [578] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [578] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [577] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [577] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [576] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [576] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [575] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [575] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [574] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [574] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [573] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [573] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [572] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [572] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [571] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [571] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [570] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [570] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [569] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [569] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [568] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [568] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [567] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [567] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [566] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [566] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [565] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [565] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [564] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [564] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [563] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [563] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [562] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [562] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [561] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [561] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [560] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [560] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [559] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [559] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [558] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [558] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [557] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [557] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [556] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [556] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [555] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [555] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [554] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [554] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [553] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [553] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [552] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [552] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [551] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [551] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [550] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [550] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [549] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [549] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [548] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [548] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [547] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [547] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [546] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [546] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [545] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [545] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [544] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [544] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [543] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [543] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [542] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [542] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [541] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [541] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_din [604] "logic emif_req_din[604:0]" +Toggle 0to1 emif_req_din [604] "logic emif_req_din[604:0]" +Toggle 1to0 emif_req_dout [27] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [27] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [26] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [26] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [25] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [25] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [24] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [24] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [23] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [23] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [22] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [22] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [21] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [21] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [20] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [20] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [19] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [19] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [18] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [18] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [17] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [17] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [16] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [16] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [15] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [15] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [14] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [14] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [13] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [13] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [28] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [28] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [603] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [603] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [602] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [602] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [601] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [601] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [600] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [600] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [599] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [599] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [598] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [598] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [597] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [597] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [596] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [596] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [595] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [595] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [594] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [594] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [593] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [593] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [592] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [592] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [591] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [591] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [590] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [590] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [589] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [589] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [588] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [588] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [587] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [587] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [586] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [586] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [585] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [585] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [584] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [584] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [583] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [583] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [582] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [582] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [581] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [581] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [580] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [580] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [579] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [579] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [578] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [578] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [577] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [577] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [576] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [576] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [575] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [575] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [574] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [574] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [573] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [573] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [572] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [572] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [571] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [571] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [570] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [570] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [569] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [569] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [568] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [568] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [567] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [567] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [566] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [566] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [565] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [565] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [564] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [564] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [563] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [563] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [562] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [562] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [561] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [561] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [560] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [560] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [559] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [559] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [558] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [558] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [557] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [557] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [556] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [556] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [555] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [555] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [554] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [554] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [553] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [553] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [552] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [552] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [551] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [551] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [550] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [550] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [549] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [549] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [548] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [548] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [547] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [547] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [546] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [546] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [545] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [545] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [544] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [544] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [543] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [543] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [542] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [542] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [541] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [541] "logic emif_req_dout[604:0]" +Toggle 1to0 emif_req_dout [604] "logic emif_req_dout[604:0]" +Toggle 0to1 emif_req_dout [604] "logic emif_req_dout[604:0]" +Toggle 1to0 wr_addr [44] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [44] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [43] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [43] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [42] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [42] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [41] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [41] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [40] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [40] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [39] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [39] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [38] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [38] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [37] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [37] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [36] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [36] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [35] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [35] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [34] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [34] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [33] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [33] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [32] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [32] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [31] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [31] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [30] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [30] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [29] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [29] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [28] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [28] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [27] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [27] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [26] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [26] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [25] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [25] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [24] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [24] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [23] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [23] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [22] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [22] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [21] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [21] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [20] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [20] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [19] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [19] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [18] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [18] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [17] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [17] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [16] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [16] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [15] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [15] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [14] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [14] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [13] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [13] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [12] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [12] "logic wr_addr[45:0]" +Toggle 1to0 wr_addr [45] "logic wr_addr[45:0]" +Toggle 0to1 wr_addr [45] "logic wr_addr[45:0]" +Toggle 1to0 rd_addr [44] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [44] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [43] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [43] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [42] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [42] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [41] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [41] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [40] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [40] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [39] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [39] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [38] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [38] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [37] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [37] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [36] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [36] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [35] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [35] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [34] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [34] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [33] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [33] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [32] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [32] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [31] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [31] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [30] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [30] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [29] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [29] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [28] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [28] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [27] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [27] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [26] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [26] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [25] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [25] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [24] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [24] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [23] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [23] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [22] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [22] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [21] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [21] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [20] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [20] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [19] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [19] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [18] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [18] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [17] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [17] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [16] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [16] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [15] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [15] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [14] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [14] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [13] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [13] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [12] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [12] "logic rd_addr[45:0]" +Toggle 1to0 rd_addr [45] "logic rd_addr[45:0]" +Toggle 0to1 rd_addr [45] "logic rd_addr[45:0]" +Toggle 1to0 error_valid "logic error_valid" +Toggle 0to1 error_valid "logic error_valid" +Toggle 1to0 error_info [1] "logic error_info[31:0]" +Toggle 0to1 error_info [1] "logic error_info[31:0]" +Toggle 1to0 error_info [2] "logic error_info[31:0]" +Toggle 0to1 error_info [2] "logic error_info[31:0]" +Toggle 1to0 error_info [3] "logic error_info[31:0]" +Toggle 0to1 error_info [3] "logic error_info[31:0]" +Toggle 1to0 error_info [0] "logic error_info[31:0]" +Toggle 0to1 error_info [0] "logic error_info[31:0]" +Toggle 1to0 ErrorVector [1] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [1] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [2] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [2] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [3] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [3] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [0] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [0] "logic ErrorVector[31:0]" +Toggle 1to0 emif_req_err "logic emif_req_err" +Toggle 0to1 emif_req_err "logic emif_req_err" +Toggle 1to0 rx_rsp_full "logic rx_rsp_full" +Toggle 0to1 rx_rsp_full "logic rx_rsp_full" +Toggle 1to0 tx_req_err "logic tx_req_err" +Toggle 0to1 tx_req_err "logic tx_req_err" +Toggle 1to0 tx_req_full "logic tx_req_full" +Toggle 0to1 tx_req_full "logic tx_req_full" +Toggle 1to0 rx_rsp_err "logic rx_rsp_err" +Toggle 0to1 rx_rsp_err "logic rx_rsp_err" +Toggle 1to0 error_info [30] "logic error_info[31:0]" +Toggle 0to1 error_info [30] "logic error_info[31:0]" +Toggle 1to0 error_info [29] "logic error_info[31:0]" +Toggle 0to1 error_info [29] "logic error_info[31:0]" +Toggle 1to0 error_info [28] "logic error_info[31:0]" +Toggle 0to1 error_info [28] "logic error_info[31:0]" +Toggle 1to0 error_info [27] "logic error_info[31:0]" +Toggle 0to1 error_info [27] "logic error_info[31:0]" +Toggle 1to0 error_info [26] "logic error_info[31:0]" +Toggle 0to1 error_info [26] "logic error_info[31:0]" +Toggle 1to0 error_info [25] "logic error_info[31:0]" +Toggle 0to1 error_info [25] "logic error_info[31:0]" +Toggle 1to0 error_info [24] "logic error_info[31:0]" +Toggle 0to1 error_info [24] "logic error_info[31:0]" +Toggle 1to0 error_info [23] "logic error_info[31:0]" +Toggle 0to1 error_info [23] "logic error_info[31:0]" +Toggle 1to0 error_info [22] "logic error_info[31:0]" +Toggle 0to1 error_info [22] "logic error_info[31:0]" +Toggle 1to0 error_info [21] "logic error_info[31:0]" +Toggle 0to1 error_info [21] "logic error_info[31:0]" +Toggle 1to0 error_info [20] "logic error_info[31:0]" +Toggle 0to1 error_info [20] "logic error_info[31:0]" +Toggle 1to0 error_info [19] "logic error_info[31:0]" +Toggle 0to1 error_info [19] "logic error_info[31:0]" +Toggle 1to0 error_info [18] "logic error_info[31:0]" +Toggle 0to1 error_info [18] "logic error_info[31:0]" +Toggle 1to0 error_info [17] "logic error_info[31:0]" +Toggle 0to1 error_info [17] "logic error_info[31:0]" +Toggle 1to0 error_info [16] "logic error_info[31:0]" +Toggle 0to1 error_info [16] "logic error_info[31:0]" +Toggle 1to0 error_info [15] "logic error_info[31:0]" +Toggle 0to1 error_info [15] "logic error_info[31:0]" +Toggle 1to0 error_info [14] "logic error_info[31:0]" +Toggle 0to1 error_info [14] "logic error_info[31:0]" +Toggle 1to0 error_info [13] "logic error_info[31:0]" +Toggle 0to1 error_info [13] "logic error_info[31:0]" +Toggle 1to0 error_info [12] "logic error_info[31:0]" +Toggle 0to1 error_info [12] "logic error_info[31:0]" +Toggle 1to0 error_info [11] "logic error_info[31:0]" +Toggle 0to1 error_info [11] "logic error_info[31:0]" +Toggle 1to0 error_info [10] "logic error_info[31:0]" +Toggle 0to1 error_info [10] "logic error_info[31:0]" +Toggle 1to0 error_info [9] "logic error_info[31:0]" +Toggle 0to1 error_info [9] "logic error_info[31:0]" +Toggle 1to0 error_info [8] "logic error_info[31:0]" +Toggle 0to1 error_info [8] "logic error_info[31:0]" +Toggle 1to0 error_info [7] "logic error_info[31:0]" +Toggle 0to1 error_info [7] "logic error_info[31:0]" +Toggle 1to0 error_info [6] "logic error_info[31:0]" +Toggle 0to1 error_info [6] "logic error_info[31:0]" +Toggle 1to0 error_info [5] "logic error_info[31:0]" +Toggle 0to1 error_info [5] "logic error_info[31:0]" +Toggle 1to0 error_info [4] "logic error_info[31:0]" +Toggle 0to1 error_info [4] "logic error_info[31:0]" +Toggle 1to0 error_info [31] "logic error_info[31:0]" +Toggle 0to1 error_info [31] "logic error_info[31:0]" +Toggle 1to0 req_len [4] "logic req_len[4:0]" +Toggle 0to1 req_len [4] "logic req_len[4:0]" +Toggle 1to0 tx_req_eot_out "logic tx_req_eot_out" +Toggle 0to1 tx_req_eot_out "logic tx_req_eot_out" +Toggle 1to0 tx_req_eot "logic tx_req_eot" +Toggle 0to1 tx_req_eot "logic tx_req_eot" +Toggle 1to0 req_len_b2 [3] "logic req_len_b2[4:0]" +Toggle 0to1 req_len_b2 [3] "logic req_len_b2[4:0]" +Toggle 1to0 req_len_b2 [2] "logic req_len_b2[4:0]" +Toggle 0to1 req_len_b2 [2] "logic req_len_b2[4:0]" +Toggle 1to0 req_len_b2 [4] "logic req_len_b2[4:0]" +Toggle 0to1 req_len_b2 [4] "logic req_len_b2[4:0]" +Toggle 1to0 csr_cfg [18] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [18] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [17] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [17] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [16] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [16] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [15] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [15] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [14] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [14] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [19] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [19] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [62] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [62] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [61] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [61] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [60] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [60] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [59] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [59] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [58] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [58] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [57] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [57] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [56] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [56] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [55] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [55] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [54] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [54] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [53] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [53] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [52] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [52] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [51] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [51] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [50] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [50] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [49] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [49] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [48] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [48] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [47] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [47] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [46] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [46] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [45] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [45] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [44] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [44] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [43] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [43] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [42] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [42] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [41] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [41] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [40] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [40] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [39] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [39] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [38] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [38] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [37] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [37] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [36] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [36] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [35] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [35] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [34] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [34] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [33] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [33] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [32] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [32] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [31] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [31] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [30] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [30] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [63] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [63] "logic csr_cfg[63:0]" +Toggle 1to0 csr2re_cfg [18] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [18] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [17] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [17] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [16] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [16] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [15] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [15] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [14] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [14] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [19] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [19] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [62] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [62] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [61] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [61] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [60] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [60] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [59] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [59] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [58] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [58] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [57] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [57] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [56] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [56] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [55] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [55] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [54] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [54] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [53] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [53] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [52] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [52] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [51] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [51] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [50] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [50] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [49] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [49] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [48] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [48] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [47] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [47] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [46] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [46] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [45] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [45] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [44] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [44] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [43] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [43] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [42] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [42] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [41] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [41] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [40] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [40] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [39] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [39] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [38] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [38] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [37] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [37] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [36] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [36] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [35] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [35] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [34] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [34] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [33] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [33] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [32] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [32] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [31] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [31] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [30] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [30] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [63] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [63] "logic csr2re_cfg[63:0]" +ANNOTATION: " Header " +Toggle recent_fmttype "logic recent_fmttype[7:0]" +ANNOTATION: " Header " +Toggle emif_req_ecc "logic emif_req_ecc[1:0]" +ANNOTATION: " Header " +Toggle emif_rsp_mdata_T1 "logic emif_rsp_mdata_T1[10:0]" +ANNOTATION: " Header " +Toggle emif_sop_tracker "logic emif_sop_tracker[2047:0]" +ANNOTATION: " Header " +Toggle rx_rsp_ecc "logic rx_rsp_ecc[1:0]" +ANNOTATION: " Header " +Toggle tx_req_ecc "logic tx_req_ecc[1:0]" +ANNOTATION: " Header " +Toggle emif_eop_tracker "logic emif_eop_tracker[2047:0]" +Toggle 1to0 ErrorVector [4] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [4] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [30] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [30] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [29] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [29] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [28] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [28] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [27] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [27] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [26] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [26] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [25] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [25] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [24] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [24] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [23] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [23] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [22] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [22] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [21] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [21] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [20] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [20] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [19] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [19] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [18] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [18] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [17] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [17] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [16] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [16] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [15] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [15] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [14] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [14] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [13] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [13] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [12] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [12] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [11] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [11] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [10] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [10] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [9] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [9] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [8] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [8] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [7] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [7] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [6] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [6] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [5] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [5] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [31] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [31] "logic ErrorVector[31:0]" +CHECKSUM: "2139909825 369815844" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_lpbk +ANNOTATION: "EMIF is 1" +Branch 11 "2535442213" "(EMIF == 0)" (0) "(EMIF == 0) 1,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +Branch 24 "2459171571" "(|ErrorVector)" (0) "(|ErrorVector) 1" +Branch 23 "1534404760" "(rx_rsp_valid & $isunknown({rx_rsp_sop, rx_rsp_eop, rx_rsp_pld}))" (0) "(rx_rsp_valid & $isunknown({rx_rsp_sop, rx_rsp_eop, rx_rsp_pld})) 1" +Branch 22 "1006867801" "(tx_req_valid & $isunknown({tx_req_sop, tx_req_eop, tx_req_pld}))" (0) "(tx_req_valid & $isunknown({tx_req_sop, tx_req_eop, tx_req_pld})) 1" +Branch 21 "1239589818" "(test_start & ((total_len % req_len) != 0))" (1) "(test_start & ((total_len % req_len) != 0)) 0" +Branch 21 "1239589818" "(test_start & ((total_len % req_len) != 0))" (0) "(test_start & ((total_len % req_len) != 0)) 1" +Branch 20 "3335143965" "(!test_resetb_q)" (7) "(!test_resetb_q) 0,-,-,-,1" +Branch 20 "3335143965" "(!test_resetb_q)" (5) "(!test_resetb_q) 0,-,-,1,-" +Branch 20 "3335143965" "(!test_resetb_q)" (3) "(!test_resetb_q) 0,-,1,-,-" +Branch 20 "3335143965" "(!test_resetb_q)" (1) "(!test_resetb_q) 0,1,-,-,-" +CHECKSUM: "1721330791 279149633" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst +Branch 15 "631384563" "(!test_resetb)" (1) "(!test_resetb) 0,1,-" +Branch 15 "631384563" "(!test_resetb)" (3) "(!test_resetb) 0,-,1" +ANNOTATION: " Errors are not generated " +Branch 16 "2662216083" "(axi_tx_if.tvalid & (axi_tx_if.tdata === 'x))" (0) "(axi_tx_if.tvalid & (axi_tx_if.tdata === 'x)) 1,-,-,-" +ANNOTATION: " Errors are not generated " +Branch 16 "2662216083" "(axi_tx_if.tvalid & (axi_tx_if.tdata === 'x))" (3) "(axi_tx_if.tvalid & (axi_tx_if.tdata === 'x)) 0,0,0,1" +ANNOTATION: " Errors are not generated " +Branch 16 "2662216083" "(axi_tx_if.tvalid & (axi_tx_if.tdata === 'x))" (2) "(axi_tx_if.tvalid & (axi_tx_if.tdata === 'x)) 0,0,1,-" +ANNOTATION: " Errors are not generated " +Branch 16 "2662216083" "(axi_tx_if.tvalid & (axi_tx_if.tdata === 'x))" (1) "(axi_tx_if.tvalid & (axi_tx_if.tdata === 'x)) 0,1,-,-" +ANNOTATION: " Errors are not generated " +Branch 17 "3409136147" "(axi_rx_if.tvalid & (axi_rx_if.tdata === 'x))" (0) "(axi_rx_if.tvalid & (axi_rx_if.tdata === 'x)) 1,-,-,-" +ANNOTATION: " Errors are not generated " +Branch 17 "3409136147" "(axi_rx_if.tvalid & (axi_rx_if.tdata === 'x))" (3) "(axi_rx_if.tvalid & (axi_rx_if.tdata === 'x)) 0,0,0,1" +ANNOTATION: " Errors are not generated " +Branch 17 "3409136147" "(axi_rx_if.tvalid & (axi_rx_if.tdata === 'x))" (2) "(axi_rx_if.tvalid & (axi_rx_if.tdata === 'x)) 0,0,1,-" +ANNOTATION: " Errors are not generated " +Branch 17 "3409136147" "(axi_rx_if.tvalid & (axi_rx_if.tdata === 'x))" (1) "(axi_rx_if.tvalid & (axi_rx_if.tdata === 'x)) 0,1,-,-" +ANNOTATION: " Errors are not generated " +Branch 2 "976102632" "(test_mode == 3'b0)" (1) "(test_mode == 3'b0) 0" +CHECKSUM: "4144234428 1488158697" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_rx_rsp_q.even_que +Toggle 1to0 perr "net perr" +Toggle 0to1 perr "net perr" +Toggle 1to0 fifo_perr "net fifo_perr" +Toggle 0to1 fifo_perr "net fifo_perr" +Toggle 1to0 fifo_err "reg fifo_err" +Toggle 0to1 fifo_err "reg fifo_err" +CHECKSUM: "4144234428 1488158697" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_rx_rsp_q.odd_que +Toggle 1to0 perr "net perr" +Toggle 0to1 perr "net perr" +Toggle 1to0 fifo_perr "net fifo_perr" +Toggle 0to1 fifo_perr "net fifo_perr" +Toggle 1to0 fifo_err "reg fifo_err" +Toggle 0to1 fifo_err "reg fifo_err" +CHECKSUM: "4144234428 627523928" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_tx_req_q.even_que +Toggle 1to0 perr "net perr" +Toggle 0to1 perr "net perr" +Toggle 1to0 fifo_perr "net fifo_perr" +Toggle 0to1 fifo_perr "net fifo_perr" +Toggle 1to0 fifo_err "reg fifo_err" +Toggle 0to1 fifo_err "reg fifo_err" +CHECKSUM: "4144234428 627523928" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_tx_req_q.odd_que +Toggle 1to0 perr "net perr" +Toggle 0to1 perr "net perr" +Toggle 1to0 fifo_perr "net fifo_perr" +Toggle 0to1 fifo_perr "net fifo_perr" +Toggle 1to0 fifo_err "reg fifo_err" +Toggle 0to1 fifo_err "reg fifo_err" +CHECKSUM: "965016526 1021161780" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_rdwr +Toggle 1to0 req_cnt [10] "logic req_cnt[10:0]" +Toggle 0to1 req_cnt [10] "logic req_cnt[10:0]" +Toggle 1to0 req_cnt [9] "logic req_cnt[10:0]" +Toggle 0to1 req_cnt [9] "logic req_cnt[10:0]" +ANNOTATION: " Randomized value " +Toggle num_wr "logic num_wr[10:0]" +Toggle 1to0 test_stopped_hold "logic test_stopped_hold" +Toggle 1to0 error_info [1] "logic error_info[31:0]" +Toggle 0to1 error_info [1] "logic error_info[31:0]" +Toggle 1to0 error_info [2] "logic error_info[31:0]" +Toggle 0to1 error_info [2] "logic error_info[31:0]" +Toggle 1to0 error_info [3] "logic error_info[31:0]" +Toggle 0to1 error_info [3] "logic error_info[31:0]" +Toggle 1to0 error_info [4] "logic error_info[31:0]" +Toggle 0to1 error_info [4] "logic error_info[31:0]" +Toggle 1to0 error_info [0] "logic error_info[31:0]" +Toggle 0to1 error_info [0] "logic error_info[31:0]" +Toggle 1to0 error_valid "logic error_valid" +Toggle 0to1 error_valid "logic error_valid" +Toggle 1to0 rx_rsp_valid "logic rx_rsp_valid" +Toggle 0to1 rx_rsp_valid "logic rx_rsp_valid" +Toggle 1to0 tx_req_err "logic tx_req_err" +Toggle 0to1 tx_req_err "logic tx_req_err" +ANNOTATION: " Randomized value " +Toggle num_reads "logic num_reads[39:0]" +ANNOTATION: " Randomized value " +Toggle num_writes "logic num_writes[39:0]" +Toggle 1to0 ErrorVector [1] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [1] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [2] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [2] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [3] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [3] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [4] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [4] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [0] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [0] "logic ErrorVector[31:0]" +ANNOTATION: " Cannot be covered functionally " +Toggle tx_req_dout "logic tx_req_dout[37:0]" +ANNOTATION: " Cannot be covered functionally " +Toggle tx_req_pld "logic tx_req_pld[511:0]" +ANNOTATION: " Cannot be covered functionally " +Toggle tx_req_pld_p "logic tx_req_pld_p[511:0]" +ANNOTATION: " Cannot be covered functionally " +Toggle tx_req_din "logic tx_req_din[37:0]" +ANNOTATION: " Cannot be covered functionally " +Toggle num_ticks_h "logic num_ticks_h[19:0]" +Toggle 0to1 tx_req_valid_p "logic tx_req_valid_p" +Toggle 1to0 tx_req_valid_p "logic tx_req_valid_p" +Toggle 0to1 tx_req_valid "logic tx_req_valid" +Toggle 1to0 tx_req_valid "logic tx_req_valid" +Toggle 0to1 tx_req_sop_p "logic tx_req_sop_p" +Toggle 1to0 tx_req_sop_p "logic tx_req_sop_p" +Toggle 0to1 tx_req_sop "logic tx_req_sop" +Toggle 1to0 tx_req_sop "logic tx_req_sop" +Toggle 0to1 tx_req_eot_out "logic tx_req_eot_out" +Toggle 1to0 tx_req_eot_out "logic tx_req_eot_out" +Toggle 0to1 tx_req_eot "logic tx_req_eot" +Toggle 1to0 tx_req_eot "logic tx_req_eot" +Toggle 0to1 tx_req_eop_p "logic tx_req_eop_p" +Toggle 1to0 tx_req_eop_p "logic tx_req_eop_p" +Toggle 0to1 tx_req_eop "logic tx_req_eop" +Toggle 1to0 tx_req_eop "logic tx_req_eop" +Toggle 0to1 rx_rsp_sop "logic rx_rsp_sop" +Toggle 1to0 rx_rsp_sop "logic rx_rsp_sop" +Toggle 0to1 rx_rsp_eop "logic rx_rsp_eop" +Toggle 1to0 rx_rsp_eop "logic rx_rsp_eop" +ANNOTATION: " Cannot be covered functionally " +Toggle num_ticks_l "logic num_ticks_l[19:0]" +ANNOTATION: " Header " +Toggle recent_tx_req_fmttype_p "logic recent_tx_req_fmttype_p[7:0]" +Toggle 0to1 csr2re_cfg [63] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [63] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [30] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [30] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [31] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [31] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [32] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [32] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [33] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [33] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [34] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [34] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [35] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [35] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [36] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [36] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [37] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [37] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [38] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [38] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [39] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [39] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [40] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [40] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [41] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [41] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [42] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [42] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [43] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [43] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [44] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [44] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [45] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [45] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [46] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [46] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [47] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [47] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [48] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [48] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [49] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [49] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [50] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [50] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [51] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [51] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [52] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [52] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [53] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [53] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [54] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [54] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [55] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [55] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [56] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [56] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [57] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [57] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [58] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [58] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [59] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [59] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [60] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [60] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [61] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [61] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [62] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [62] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [19] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [19] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [14] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [14] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [15] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [15] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [16] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [16] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [17] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [17] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [18] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [18] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr_cfg [63] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [63] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [14] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [14] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [15] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [15] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [16] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [16] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [17] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [17] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [18] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [18] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [19] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [19] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [30] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [30] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [31] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [31] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [32] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [32] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [33] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [33] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [34] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [34] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [35] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [35] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [36] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [36] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [37] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [37] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [38] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [38] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [39] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [39] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [40] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [40] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [41] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [41] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [42] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [42] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [43] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [43] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [44] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [44] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [45] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [45] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [46] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [46] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [47] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [47] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [48] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [48] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [49] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [49] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [50] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [50] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [51] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [51] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [52] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [52] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [53] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [53] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [54] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [54] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [55] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [55] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [56] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [56] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [57] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [57] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [58] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [58] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [59] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [59] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [60] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [60] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [61] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [61] "logic csr_cfg[63:0]" +Toggle 0to1 csr_cfg [62] "logic csr_cfg[63:0]" +Toggle 1to0 csr_cfg [62] "logic csr_cfg[63:0]" +Toggle 0to1 ErrorVector [31] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [31] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [5] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [5] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [6] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [6] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [7] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [7] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [8] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [8] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [9] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [9] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [10] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [10] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [11] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [11] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [12] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [12] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [13] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [13] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [14] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [14] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [15] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [15] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [16] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [16] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [17] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [17] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [18] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [18] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [19] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [19] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [20] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [20] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [21] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [21] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [22] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [22] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [23] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [23] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [24] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [24] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [25] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [25] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [26] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [26] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [27] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [27] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [28] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [28] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [29] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [29] "logic ErrorVector[31:0]" +Toggle 0to1 ErrorVector [30] "logic ErrorVector[31:0]" +Toggle 1to0 ErrorVector [30] "logic ErrorVector[31:0]" +Toggle 0to1 req_len [4] "logic req_len[4:0]" +Toggle 1to0 req_len [4] "logic req_len[4:0]" +Toggle 0to1 req_len_b2 [4] "logic req_len_b2[4:0]" +Toggle 1to0 req_len_b2 [4] "logic req_len_b2[4:0]" +Toggle 0to1 req_len_b2 [2] "logic req_len_b2[4:0]" +Toggle 1to0 req_len_b2 [2] "logic req_len_b2[4:0]" +Toggle 0to1 req_len_b2 [3] "logic req_len_b2[4:0]" +Toggle 1to0 req_len_b2 [3] "logic req_len_b2[4:0]" +Toggle 0to1 rx_rsp_ready "logic rx_rsp_ready" +Toggle 1to0 rx_rsp_ready "logic rx_rsp_ready" +ANNOTATION: " Cannot be covered functionally " +Toggle tx_req_ecc "logic tx_req_ecc[1:0]" +Toggle 1to0 test_complete "logic test_complete" +Toggle 1to0 test_started "logic test_started" +Toggle 0to1 error_info [31] "logic error_info[31:0]" +Toggle 1to0 error_info [31] "logic error_info[31:0]" +Toggle 0to1 error_info [5] "logic error_info[31:0]" +Toggle 1to0 error_info [5] "logic error_info[31:0]" +Toggle 0to1 error_info [6] "logic error_info[31:0]" +Toggle 1to0 error_info [6] "logic error_info[31:0]" +Toggle 0to1 error_info [7] "logic error_info[31:0]" +Toggle 1to0 error_info [7] "logic error_info[31:0]" +Toggle 0to1 error_info [8] "logic error_info[31:0]" +Toggle 1to0 error_info [8] "logic error_info[31:0]" +Toggle 0to1 error_info [9] "logic error_info[31:0]" +Toggle 1to0 error_info [9] "logic error_info[31:0]" +Toggle 0to1 error_info [10] "logic error_info[31:0]" +Toggle 1to0 error_info [10] "logic error_info[31:0]" +Toggle 0to1 error_info [11] "logic error_info[31:0]" +Toggle 1to0 error_info [11] "logic error_info[31:0]" +Toggle 0to1 error_info [12] "logic error_info[31:0]" +Toggle 1to0 error_info [12] "logic error_info[31:0]" +Toggle 0to1 error_info [13] "logic error_info[31:0]" +Toggle 1to0 error_info [13] "logic error_info[31:0]" +Toggle 0to1 error_info [14] "logic error_info[31:0]" +Toggle 1to0 error_info [14] "logic error_info[31:0]" +Toggle 0to1 error_info [15] "logic error_info[31:0]" +Toggle 1to0 error_info [15] "logic error_info[31:0]" +Toggle 0to1 error_info [16] "logic error_info[31:0]" +Toggle 1to0 error_info [16] "logic error_info[31:0]" +Toggle 0to1 error_info [17] "logic error_info[31:0]" +Toggle 1to0 error_info [17] "logic error_info[31:0]" +Toggle 0to1 error_info [18] "logic error_info[31:0]" +Toggle 1to0 error_info [18] "logic error_info[31:0]" +Toggle 0to1 error_info [19] "logic error_info[31:0]" +Toggle 1to0 error_info [19] "logic error_info[31:0]" +Toggle 0to1 error_info [20] "logic error_info[31:0]" +Toggle 1to0 error_info [20] "logic error_info[31:0]" +Toggle 0to1 error_info [21] "logic error_info[31:0]" +Toggle 1to0 error_info [21] "logic error_info[31:0]" +Toggle 0to1 error_info [22] "logic error_info[31:0]" +Toggle 1to0 error_info [22] "logic error_info[31:0]" +Toggle 0to1 error_info [23] "logic error_info[31:0]" +Toggle 1to0 error_info [23] "logic error_info[31:0]" +Toggle 0to1 error_info [24] "logic error_info[31:0]" +Toggle 1to0 error_info [24] "logic error_info[31:0]" +Toggle 0to1 error_info [25] "logic error_info[31:0]" +Toggle 1to0 error_info [25] "logic error_info[31:0]" +Toggle 0to1 error_info [26] "logic error_info[31:0]" +Toggle 1to0 error_info [26] "logic error_info[31:0]" +Toggle 0to1 error_info [27] "logic error_info[31:0]" +Toggle 1to0 error_info [27] "logic error_info[31:0]" +Toggle 0to1 error_info [28] "logic error_info[31:0]" +Toggle 1to0 error_info [28] "logic error_info[31:0]" +Toggle 0to1 error_info [29] "logic error_info[31:0]" +Toggle 1to0 error_info [29] "logic error_info[31:0]" +Toggle 0to1 error_info [30] "logic error_info[31:0]" +Toggle 1to0 error_info [30] "logic error_info[31:0]" +CHECKSUM: "1259019545 1064430290" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.axi_rx_stage_1 +Toggle genblk1.m_tdest_pre "reg genblk1.m_tdest_pre[7:0]" +Toggle s_tid "net s_tid[7:0]" +Toggle s_tdest "net s_tdest[7:0]" +Toggle m_tid "net m_tid[7:0]" +Toggle genblk1.s_tid_reg "reg genblk1.s_tid_reg[7:0]" +Toggle genblk1.s_tdest_reg "reg genblk1.s_tdest_reg[7:0]" +Toggle genblk1.m_tid_reg "reg genblk1.m_tid_reg[7:0]" +Toggle genblk1.m_tid_pre "reg genblk1.m_tid_pre[7:0]" +Toggle genblk1.m_tdest_reg "reg genblk1.m_tdest_reg[7:0]" +Toggle 0to1 s_tuser [9] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [9] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [1] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [1] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [2] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [2] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [3] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [3] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [4] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [4] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [5] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [5] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [6] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [6] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [7] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [7] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [8] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [8] "net s_tuser[9:0]" +Toggle 0to1 m_tuser [9] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [9] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [1] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [1] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [2] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [2] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [3] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [3] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [4] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [4] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [5] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [5] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [6] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [6] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [7] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [7] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [8] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [8] "net m_tuser[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle m_tdest "net m_tdest[7:0]" +CHECKSUM: "1259019545 1064430290" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.axi_rx_stage_2 +Toggle genblk1.m_tdest_pre "reg genblk1.m_tdest_pre[7:0]" +Toggle s_tid "net s_tid[7:0]" +Toggle s_tdest "net s_tdest[7:0]" +Toggle m_tid "net m_tid[7:0]" +Toggle genblk1.s_tid_reg "reg genblk1.s_tid_reg[7:0]" +Toggle genblk1.s_tdest_reg "reg genblk1.s_tdest_reg[7:0]" +Toggle genblk1.m_tid_reg "reg genblk1.m_tid_reg[7:0]" +Toggle genblk1.m_tid_pre "reg genblk1.m_tid_pre[7:0]" +Toggle genblk1.m_tdest_reg "reg genblk1.m_tdest_reg[7:0]" +Toggle 0to1 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 s_tuser [9] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [9] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [1] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [1] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [2] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [2] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [3] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [3] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [4] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [4] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [5] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [5] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [6] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [6] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [7] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [7] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [8] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [8] "net s_tuser[9:0]" +Toggle 0to1 m_tuser [9] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [9] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [1] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [1] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [2] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [2] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [3] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [3] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [4] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [4] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [5] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [5] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [6] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [6] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [7] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [7] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [8] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [8] "net m_tuser[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +CHECKSUM: "1259019545 1064430290" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.axi_tx_stage_1 +Toggle s_tid "net s_tid[7:0]" +Toggle 0to1 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 s_tuser [9] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [9] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [1] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [1] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [2] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [2] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [3] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [3] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [4] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [4] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [5] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [5] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [6] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [6] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [7] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [7] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [8] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [8] "net s_tuser[9:0]" +Toggle 0to1 m_tuser [9] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [9] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [1] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [1] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [2] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [2] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [3] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [3] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [4] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [4] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [5] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [5] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [6] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [6] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [7] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [7] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [8] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [8] "net m_tuser[9:0]" +Toggle genblk1.m_tdest_pre "reg genblk1.m_tdest_pre[7:0]" +Toggle s_tdest "net s_tdest[7:0]" +Toggle m_tid "net m_tid[7:0]" +Toggle genblk1.s_tid_reg "reg genblk1.s_tid_reg[7:0]" +Toggle genblk1.m_tid_reg "reg genblk1.m_tid_reg[7:0]" +Toggle genblk1.m_tid_pre "reg genblk1.m_tid_pre[7:0]" +Toggle genblk1.m_tdest_reg "reg genblk1.m_tdest_reg[7:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.axi_rx_if_T1 +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "3814588975 2678712067" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_csr +Toggle 1to0 csr2re_dsm_base [62] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [62] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [61] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [61] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [60] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [60] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [59] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [59] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [58] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [58] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [57] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [57] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [56] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [56] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [55] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [55] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [54] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [54] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [53] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [53] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [52] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [52] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [51] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [51] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [50] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [50] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [49] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [49] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [48] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [48] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 csr2re_dsm_base [63] "logic csr2re_dsm_base[63:0]" +Toggle 0to1 csr2re_dsm_base [63] "logic csr2re_dsm_base[63:0]" +Toggle 1to0 re2csr_error [4] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [2] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [2] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [1] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [1] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [0] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [0] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [3] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [3] "logic re2csr_error[31:0]" +ANNOTATION: " Header value " +Toggle afu_csr_addr_8B_T1 "logic afu_csr_addr_8B_T1[14:0]" +ANNOTATION: " Header value " +Toggle afu_csr_addr_4B "logic afu_csr_addr_4B[15:0]" +ANNOTATION: " Header value " +Toggle afu_csr_addr_8B "logic afu_csr_addr_8B[14:0]" +Toggle 1to0 csr2re_interrupt0 [30] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [30] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [29] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [29] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [28] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [28] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [27] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [27] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [26] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [26] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [25] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [25] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [24] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [24] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [23] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [23] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [22] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [22] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [21] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [21] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [20] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [20] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [19] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [19] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [18] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [18] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [31] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [31] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [14] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [14] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [13] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [13] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [12] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [12] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [11] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [11] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [10] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [10] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [9] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [9] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [8] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [8] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [7] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [7] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [6] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [6] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [5] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [5] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [4] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [4] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [3] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [3] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [2] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [2] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [1] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [1] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [0] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [0] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 csr2re_interrupt0 [15] "logic csr2re_interrupt0[31:0]" +Toggle 0to1 csr2re_interrupt0 [15] "logic csr2re_interrupt0[31:0]" +Toggle 1to0 range_valid "logic range_valid" +Toggle 0to1 range_valid "logic range_valid" +ANNOTATION: " Randomized value " +Toggle re2csr_num_wrpend "logic re2csr_num_wrpend[31:0]" +ANNOTATION: " Randomized value " +Toggle re2csr_num_writes "logic re2csr_num_writes[31:0]" +ANNOTATION: " Randomized value " +Toggle re2csr_num_reads "logic re2csr_num_reads[31:0]" +ANNOTATION: " Randomized value " +Toggle re2csr_num_rdpend "logic re2csr_num_rdpend[31:0]" +ANNOTATION: " Not connected " +Toggle csr2re_stride "logic csr2re_stride[31:0]" +Toggle 1to0 csr2re_cfg [0] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [0] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [62] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [62] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [61] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [61] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [60] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [60] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [59] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [59] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [58] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [58] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [57] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [57] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [56] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [56] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [55] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [55] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [54] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [54] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [53] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [53] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [52] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [52] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [51] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [51] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [50] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [50] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [49] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [49] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [48] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [48] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [47] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [47] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [46] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [46] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [45] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [45] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [44] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [44] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [43] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [43] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [42] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [42] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [41] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [41] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [40] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [40] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [39] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [39] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [38] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [38] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [37] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [37] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [36] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [36] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [35] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [35] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [34] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [34] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [33] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [33] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [32] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [32] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [31] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [31] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [30] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [30] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [19] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [19] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [18] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [18] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [17] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [17] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [16] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [16] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [15] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [15] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [14] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [14] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_cfg [63] "logic csr2re_cfg[63:0]" +Toggle 0to1 csr2re_cfg [63] "logic csr2re_cfg[63:0]" +Toggle 1to0 csr2re_ctl [30] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [30] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [29] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [29] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [28] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [28] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [27] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [27] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [26] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [26] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [25] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [25] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [24] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [24] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [23] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [23] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [22] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [22] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [21] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [21] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [20] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [20] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [19] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [19] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [18] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [18] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [17] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [17] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [16] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [16] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [15] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [15] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [14] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [14] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [13] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [13] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [12] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [12] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [11] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [11] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [10] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [10] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [9] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [9] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [8] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [8] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [7] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [7] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [6] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [6] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [5] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [5] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [4] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [4] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [3] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [3] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_ctl [31] "logic csr2re_ctl[31:0]" +Toggle 0to1 csr2re_ctl [31] "logic csr2re_ctl[31:0]" +Toggle 1to0 csr2re_num_lines [30] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [30] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [29] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [29] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [28] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [28] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [27] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [27] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [26] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [26] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [25] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [25] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [24] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [24] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [23] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [23] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [22] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [22] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [21] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [21] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [20] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [20] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [19] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [19] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [18] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [18] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [17] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [17] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [16] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [16] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [15] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [15] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [14] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [14] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [13] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [13] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [12] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [12] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [11] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [11] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [10] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [10] "logic csr2re_num_lines[31:0]" +Toggle 1to0 csr2re_num_lines [31] "logic csr2re_num_lines[31:0]" +Toggle 0to1 csr2re_num_lines [31] "logic csr2re_num_lines[31:0]" +ANNOTATION: " Header " +Toggle feature_id_T2 "logic feature_id_T2[1:0]" +Toggle 0to1 re2csr_error [31] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [31] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [5] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [5] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [6] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [6] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [7] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [7] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [8] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [8] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [9] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [9] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [10] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [10] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [11] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [11] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [12] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [12] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [13] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [13] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [14] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [14] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [15] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [15] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [16] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [16] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [17] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [17] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [18] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [18] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [19] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [19] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [20] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [20] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [21] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [21] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [22] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [22] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [23] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [23] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [24] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [24] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [25] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [25] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [26] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [26] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [27] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [27] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [28] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [28] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [29] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [29] "logic re2csr_error[31:0]" +Toggle 0to1 re2csr_error [30] "logic re2csr_error[31:0]" +Toggle 1to0 re2csr_error [30] "logic re2csr_error[31:0]" +ANNOTATION: " Header " +Toggle feature_0_addr_offset_8B_T1 "logic feature_0_addr_offset_8B_T1[14:0]" +CHECKSUM: "3520213052 3573076547" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_tx_req_q +Toggle 1to0 fifo_err "reg fifo_err" +Toggle 0to1 fifo_err "reg fifo_err" +Toggle 1to0 odd_fifo_err "net odd_fifo_err" +Toggle 0to1 odd_fifo_err "net odd_fifo_err" +Toggle 1to0 even_fifo_err "net even_fifo_err" +Toggle 0to1 even_fifo_err "net even_fifo_err" +Toggle 1to0 fifo_perr "net fifo_perr" +Toggle 0to1 fifo_perr "net fifo_perr" +Toggle 1to0 odd_fifo_perr "net odd_fifo_perr" +Toggle 0to1 odd_fifo_perr "net odd_fifo_perr" +Toggle 1to0 even_fifo_perr "net even_fifo_perr" +Toggle 0to1 even_fifo_perr "net even_fifo_perr" +CHECKSUM: "3520213052 1403893845" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_rx_rsp_q +Toggle 1to0 fifo_perr "net fifo_perr" +Toggle 0to1 fifo_perr "net fifo_perr" +Toggle 1to0 odd_fifo_perr "net odd_fifo_perr" +Toggle 0to1 odd_fifo_perr "net odd_fifo_perr" +Toggle 1to0 even_fifo_perr "net even_fifo_perr" +Toggle 0to1 even_fifo_perr "net even_fifo_perr" +Toggle 1to0 fifo_err "reg fifo_err" +Toggle 0to1 fifo_err "reg fifo_err" +Toggle 1to0 odd_fifo_err "net odd_fifo_err" +Toggle 0to1 odd_fifo_err "net odd_fifo_err" +Toggle 1to0 even_fifo_err "net even_fifo_err" +Toggle 0to1 even_fifo_err "net even_fifo_err" +CHECKSUM: "4144234428 3046614582" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_rx_rsp_q.even_que +Block 2 "2974956466" "fifo_in = fifo_din_q;" +Block 5 "3868310358" "fifo_dout = fifo_out_q;" +Block 38 "2294665107" "fifo_err <= 1'b1;" +Block 39 "189190586" "fifo_err <= 1'b1;" +Block 70 "1663007339" ";" +CHECKSUM: "4144234428 3046614582" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_rx_rsp_q.odd_que +Block 2 "2974956466" "fifo_in = fifo_din_q;" +Block 5 "3868310358" "fifo_dout = fifo_out_q;" +Block 38 "2294665107" "fifo_err <= 1'b1;" +Block 39 "189190586" "fifo_err <= 1'b1;" +Block 70 "1663007339" ";" +CHECKSUM: "4144234428 3046614582" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_tx_req_q.even_que +Block 2 "2974956466" "fifo_in = fifo_din_q;" +Block 70 "1663007339" ";" +Block 39 "189190586" "fifo_err <= 1'b1;" +Block 38 "2294665107" "fifo_err <= 1'b1;" +Block 5 "3868310358" "fifo_dout = fifo_out_q;" +CHECKSUM: "4144234428 3046614582" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_tx_req_q.odd_que +Block 2 "2974956466" "fifo_in = fifo_din_q;" +Block 70 "1663007339" ";" +Block 39 "189190586" "fifo_err <= 1'b1;" +Block 38 "2294665107" "fifo_err <= 1'b1;" +Block 5 "3868310358" "fifo_dout = fifo_out_q;" +CHECKSUM: "2948434777 858782335" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.ext_mem_if_rw +Toggle 1to0 writedata [574] "logic writedata[575:0]" +Toggle 0to1 writedata [574] "logic writedata[575:0]" +Toggle 1to0 writedata [573] "logic writedata[575:0]" +Toggle 0to1 writedata [573] "logic writedata[575:0]" +Toggle 1to0 writedata [572] "logic writedata[575:0]" +Toggle 0to1 writedata [572] "logic writedata[575:0]" +Toggle 1to0 writedata [571] "logic writedata[575:0]" +Toggle 0to1 writedata [571] "logic writedata[575:0]" +Toggle 1to0 writedata [570] "logic writedata[575:0]" +Toggle 0to1 writedata [570] "logic writedata[575:0]" +Toggle 1to0 writedata [569] "logic writedata[575:0]" +Toggle 0to1 writedata [569] "logic writedata[575:0]" +Toggle 1to0 writedata [568] "logic writedata[575:0]" +Toggle 0to1 writedata [568] "logic writedata[575:0]" +Toggle 1to0 writedata [567] "logic writedata[575:0]" +Toggle 0to1 writedata [567] "logic writedata[575:0]" +Toggle 1to0 writedata [566] "logic writedata[575:0]" +Toggle 0to1 writedata [566] "logic writedata[575:0]" +Toggle 1to0 writedata [565] "logic writedata[575:0]" +Toggle 0to1 writedata [565] "logic writedata[575:0]" +Toggle 1to0 writedata [564] "logic writedata[575:0]" +Toggle 0to1 writedata [564] "logic writedata[575:0]" +Toggle 1to0 writedata [563] "logic writedata[575:0]" +Toggle 0to1 writedata [563] "logic writedata[575:0]" +Toggle 1to0 writedata [562] "logic writedata[575:0]" +Toggle 0to1 writedata [562] "logic writedata[575:0]" +Toggle 1to0 writedata [561] "logic writedata[575:0]" +Toggle 0to1 writedata [561] "logic writedata[575:0]" +Toggle 1to0 writedata [560] "logic writedata[575:0]" +Toggle 0to1 writedata [560] "logic writedata[575:0]" +Toggle 1to0 writedata [559] "logic writedata[575:0]" +Toggle 0to1 writedata [559] "logic writedata[575:0]" +Toggle 1to0 writedata [558] "logic writedata[575:0]" +Toggle 0to1 writedata [558] "logic writedata[575:0]" +Toggle 1to0 writedata [557] "logic writedata[575:0]" +Toggle 0to1 writedata [557] "logic writedata[575:0]" +Toggle 1to0 writedata [556] "logic writedata[575:0]" +Toggle 0to1 writedata [556] "logic writedata[575:0]" +Toggle 1to0 writedata [555] "logic writedata[575:0]" +Toggle 0to1 writedata [555] "logic writedata[575:0]" +Toggle 1to0 writedata [554] "logic writedata[575:0]" +Toggle 0to1 writedata [554] "logic writedata[575:0]" +Toggle 1to0 writedata [553] "logic writedata[575:0]" +Toggle 0to1 writedata [553] "logic writedata[575:0]" +Toggle 1to0 writedata [552] "logic writedata[575:0]" +Toggle 0to1 writedata [552] "logic writedata[575:0]" +Toggle 1to0 writedata [551] "logic writedata[575:0]" +Toggle 0to1 writedata [551] "logic writedata[575:0]" +Toggle 1to0 writedata [550] "logic writedata[575:0]" +Toggle 0to1 writedata [550] "logic writedata[575:0]" +Toggle 1to0 writedata [549] "logic writedata[575:0]" +Toggle 0to1 writedata [549] "logic writedata[575:0]" +Toggle 1to0 writedata [548] "logic writedata[575:0]" +Toggle 0to1 writedata [548] "logic writedata[575:0]" +Toggle 1to0 writedata [547] "logic writedata[575:0]" +Toggle 0to1 writedata [547] "logic writedata[575:0]" +Toggle 1to0 writedata [546] "logic writedata[575:0]" +Toggle 0to1 writedata [546] "logic writedata[575:0]" +Toggle 1to0 writedata [545] "logic writedata[575:0]" +Toggle 0to1 writedata [545] "logic writedata[575:0]" +Toggle 1to0 writedata [544] "logic writedata[575:0]" +Toggle 0to1 writedata [544] "logic writedata[575:0]" +Toggle 1to0 writedata [543] "logic writedata[575:0]" +Toggle 0to1 writedata [543] "logic writedata[575:0]" +Toggle 1to0 writedata [542] "logic writedata[575:0]" +Toggle 0to1 writedata [542] "logic writedata[575:0]" +Toggle 1to0 writedata [541] "logic writedata[575:0]" +Toggle 0to1 writedata [541] "logic writedata[575:0]" +Toggle 1to0 writedata [540] "logic writedata[575:0]" +Toggle 0to1 writedata [540] "logic writedata[575:0]" +Toggle 1to0 writedata [539] "logic writedata[575:0]" +Toggle 0to1 writedata [539] "logic writedata[575:0]" +Toggle 1to0 writedata [538] "logic writedata[575:0]" +Toggle 0to1 writedata [538] "logic writedata[575:0]" +Toggle 1to0 writedata [537] "logic writedata[575:0]" +Toggle 0to1 writedata [537] "logic writedata[575:0]" +Toggle 1to0 writedata [536] "logic writedata[575:0]" +Toggle 0to1 writedata [536] "logic writedata[575:0]" +Toggle 1to0 writedata [535] "logic writedata[575:0]" +Toggle 0to1 writedata [535] "logic writedata[575:0]" +Toggle 1to0 writedata [534] "logic writedata[575:0]" +Toggle 0to1 writedata [534] "logic writedata[575:0]" +Toggle 1to0 writedata [533] "logic writedata[575:0]" +Toggle 0to1 writedata [533] "logic writedata[575:0]" +Toggle 1to0 writedata [532] "logic writedata[575:0]" +Toggle 0to1 writedata [532] "logic writedata[575:0]" +Toggle 1to0 writedata [531] "logic writedata[575:0]" +Toggle 0to1 writedata [531] "logic writedata[575:0]" +Toggle 1to0 writedata [530] "logic writedata[575:0]" +Toggle 0to1 writedata [530] "logic writedata[575:0]" +Toggle 1to0 writedata [529] "logic writedata[575:0]" +Toggle 0to1 writedata [529] "logic writedata[575:0]" +Toggle 1to0 writedata [528] "logic writedata[575:0]" +Toggle 0to1 writedata [528] "logic writedata[575:0]" +Toggle 1to0 writedata [527] "logic writedata[575:0]" +Toggle 0to1 writedata [527] "logic writedata[575:0]" +Toggle 1to0 writedata [526] "logic writedata[575:0]" +Toggle 0to1 writedata [526] "logic writedata[575:0]" +Toggle 1to0 writedata [525] "logic writedata[575:0]" +Toggle 0to1 writedata [525] "logic writedata[575:0]" +Toggle 1to0 writedata [524] "logic writedata[575:0]" +Toggle 0to1 writedata [524] "logic writedata[575:0]" +Toggle 1to0 writedata [523] "logic writedata[575:0]" +Toggle 0to1 writedata [523] "logic writedata[575:0]" +Toggle 1to0 writedata [522] "logic writedata[575:0]" +Toggle 0to1 writedata [522] "logic writedata[575:0]" +Toggle 1to0 writedata [521] "logic writedata[575:0]" +Toggle 0to1 writedata [521] "logic writedata[575:0]" +Toggle 1to0 writedata [520] "logic writedata[575:0]" +Toggle 0to1 writedata [520] "logic writedata[575:0]" +Toggle 1to0 writedata [519] "logic writedata[575:0]" +Toggle 0to1 writedata [519] "logic writedata[575:0]" +Toggle 1to0 writedata [518] "logic writedata[575:0]" +Toggle 0to1 writedata [518] "logic writedata[575:0]" +Toggle 1to0 writedata [517] "logic writedata[575:0]" +Toggle 0to1 writedata [517] "logic writedata[575:0]" +Toggle 1to0 writedata [516] "logic writedata[575:0]" +Toggle 0to1 writedata [516] "logic writedata[575:0]" +Toggle 1to0 writedata [515] "logic writedata[575:0]" +Toggle 0to1 writedata [515] "logic writedata[575:0]" +Toggle 1to0 writedata [514] "logic writedata[575:0]" +Toggle 0to1 writedata [514] "logic writedata[575:0]" +Toggle 1to0 writedata [513] "logic writedata[575:0]" +Toggle 0to1 writedata [513] "logic writedata[575:0]" +Toggle 1to0 writedata [512] "logic writedata[575:0]" +Toggle 0to1 writedata [512] "logic writedata[575:0]" +Toggle 1to0 writedata [511] "logic writedata[575:0]" +Toggle 0to1 writedata [511] "logic writedata[575:0]" +Toggle 1to0 writedata [510] "logic writedata[575:0]" +Toggle 0to1 writedata [510] "logic writedata[575:0]" +Toggle 1to0 writedata [509] "logic writedata[575:0]" +Toggle 0to1 writedata [509] "logic writedata[575:0]" +Toggle 1to0 writedata [508] "logic writedata[575:0]" +Toggle 0to1 writedata [508] "logic writedata[575:0]" +Toggle 1to0 writedata [507] "logic writedata[575:0]" +Toggle 0to1 writedata [507] "logic writedata[575:0]" +Toggle 1to0 writedata [506] "logic writedata[575:0]" +Toggle 0to1 writedata [506] "logic writedata[575:0]" +Toggle 1to0 writedata [505] "logic writedata[575:0]" +Toggle 0to1 writedata [505] "logic writedata[575:0]" +Toggle 1to0 writedata [504] "logic writedata[575:0]" +Toggle 0to1 writedata [504] "logic writedata[575:0]" +Toggle 1to0 writedata [503] "logic writedata[575:0]" +Toggle 0to1 writedata [503] "logic writedata[575:0]" +Toggle 1to0 writedata [502] "logic writedata[575:0]" +Toggle 0to1 writedata [502] "logic writedata[575:0]" +Toggle 1to0 writedata [501] "logic writedata[575:0]" +Toggle 0to1 writedata [501] "logic writedata[575:0]" +Toggle 1to0 writedata [500] "logic writedata[575:0]" +Toggle 0to1 writedata [500] "logic writedata[575:0]" +Toggle 1to0 writedata [499] "logic writedata[575:0]" +Toggle 0to1 writedata [499] "logic writedata[575:0]" +Toggle 1to0 writedata [498] "logic writedata[575:0]" +Toggle 0to1 writedata [498] "logic writedata[575:0]" +Toggle 1to0 writedata [497] "logic writedata[575:0]" +Toggle 0to1 writedata [497] "logic writedata[575:0]" +Toggle 1to0 writedata [496] "logic writedata[575:0]" +Toggle 0to1 writedata [496] "logic writedata[575:0]" +Toggle 1to0 writedata [495] "logic writedata[575:0]" +Toggle 0to1 writedata [495] "logic writedata[575:0]" +Toggle 1to0 writedata [494] "logic writedata[575:0]" +Toggle 0to1 writedata [494] "logic writedata[575:0]" +Toggle 1to0 writedata [493] "logic writedata[575:0]" +Toggle 0to1 writedata [493] "logic writedata[575:0]" +Toggle 1to0 writedata [492] "logic writedata[575:0]" +Toggle 0to1 writedata [492] "logic writedata[575:0]" +Toggle 1to0 writedata [491] "logic writedata[575:0]" +Toggle 0to1 writedata [491] "logic writedata[575:0]" +Toggle 1to0 writedata [490] "logic writedata[575:0]" +Toggle 0to1 writedata [490] "logic writedata[575:0]" +Toggle 1to0 writedata [489] "logic writedata[575:0]" +Toggle 0to1 writedata [489] "logic writedata[575:0]" +Toggle 1to0 writedata [488] "logic writedata[575:0]" +Toggle 0to1 writedata [488] "logic writedata[575:0]" +Toggle 1to0 writedata [487] "logic writedata[575:0]" +Toggle 0to1 writedata [487] "logic writedata[575:0]" +Toggle 1to0 writedata [486] "logic writedata[575:0]" +Toggle 0to1 writedata [486] "logic writedata[575:0]" +Toggle 1to0 writedata [485] "logic writedata[575:0]" +Toggle 0to1 writedata [485] "logic writedata[575:0]" +Toggle 1to0 writedata [484] "logic writedata[575:0]" +Toggle 0to1 writedata [484] "logic writedata[575:0]" +Toggle 1to0 writedata [483] "logic writedata[575:0]" +Toggle 0to1 writedata [483] "logic writedata[575:0]" +Toggle 1to0 writedata [482] "logic writedata[575:0]" +Toggle 0to1 writedata [482] "logic writedata[575:0]" +Toggle 1to0 writedata [481] "logic writedata[575:0]" +Toggle 0to1 writedata [481] "logic writedata[575:0]" +Toggle 1to0 writedata [480] "logic writedata[575:0]" +Toggle 0to1 writedata [480] "logic writedata[575:0]" +Toggle 1to0 writedata [479] "logic writedata[575:0]" +Toggle 0to1 writedata [479] "logic writedata[575:0]" +Toggle 1to0 writedata [478] "logic writedata[575:0]" +Toggle 0to1 writedata [478] "logic writedata[575:0]" +Toggle 1to0 writedata [477] "logic writedata[575:0]" +Toggle 0to1 writedata [477] "logic writedata[575:0]" +Toggle 1to0 writedata [476] "logic writedata[575:0]" +Toggle 0to1 writedata [476] "logic writedata[575:0]" +Toggle 1to0 writedata [475] "logic writedata[575:0]" +Toggle 0to1 writedata [475] "logic writedata[575:0]" +Toggle 1to0 writedata [474] "logic writedata[575:0]" +Toggle 0to1 writedata [474] "logic writedata[575:0]" +Toggle 1to0 writedata [473] "logic writedata[575:0]" +Toggle 0to1 writedata [473] "logic writedata[575:0]" +Toggle 1to0 writedata [472] "logic writedata[575:0]" +Toggle 0to1 writedata [472] "logic writedata[575:0]" +Toggle 1to0 writedata [471] "logic writedata[575:0]" +Toggle 0to1 writedata [471] "logic writedata[575:0]" +Toggle 1to0 writedata [470] "logic writedata[575:0]" +Toggle 0to1 writedata [470] "logic writedata[575:0]" +Toggle 1to0 writedata [469] "logic writedata[575:0]" +Toggle 0to1 writedata [469] "logic writedata[575:0]" +Toggle 1to0 writedata [468] "logic writedata[575:0]" +Toggle 0to1 writedata [468] "logic writedata[575:0]" +Toggle 1to0 writedata [467] "logic writedata[575:0]" +Toggle 0to1 writedata [467] "logic writedata[575:0]" +Toggle 1to0 writedata [466] "logic writedata[575:0]" +Toggle 0to1 writedata [466] "logic writedata[575:0]" +Toggle 1to0 writedata [465] "logic writedata[575:0]" +Toggle 0to1 writedata [465] "logic writedata[575:0]" +Toggle 1to0 writedata [464] "logic writedata[575:0]" +Toggle 0to1 writedata [464] "logic writedata[575:0]" +Toggle 1to0 writedata [463] "logic writedata[575:0]" +Toggle 0to1 writedata [463] "logic writedata[575:0]" +Toggle 1to0 writedata [462] "logic writedata[575:0]" +Toggle 0to1 writedata [462] "logic writedata[575:0]" +Toggle 1to0 writedata [461] "logic writedata[575:0]" +Toggle 0to1 writedata [461] "logic writedata[575:0]" +Toggle 1to0 writedata [460] "logic writedata[575:0]" +Toggle 0to1 writedata [460] "logic writedata[575:0]" +Toggle 1to0 writedata [459] "logic writedata[575:0]" +Toggle 0to1 writedata [459] "logic writedata[575:0]" +Toggle 1to0 writedata [458] "logic writedata[575:0]" +Toggle 0to1 writedata [458] "logic writedata[575:0]" +Toggle 1to0 writedata [457] "logic writedata[575:0]" +Toggle 0to1 writedata [457] "logic writedata[575:0]" +Toggle 1to0 writedata [456] "logic writedata[575:0]" +Toggle 0to1 writedata [456] "logic writedata[575:0]" +Toggle 1to0 writedata [455] "logic writedata[575:0]" +Toggle 0to1 writedata [455] "logic writedata[575:0]" +Toggle 1to0 writedata [454] "logic writedata[575:0]" +Toggle 0to1 writedata [454] "logic writedata[575:0]" +Toggle 1to0 writedata [453] "logic writedata[575:0]" +Toggle 0to1 writedata [453] "logic writedata[575:0]" +Toggle 1to0 writedata [452] "logic writedata[575:0]" +Toggle 0to1 writedata [452] "logic writedata[575:0]" +Toggle 1to0 writedata [451] "logic writedata[575:0]" +Toggle 0to1 writedata [451] "logic writedata[575:0]" +Toggle 1to0 writedata [450] "logic writedata[575:0]" +Toggle 0to1 writedata [450] "logic writedata[575:0]" +Toggle 1to0 writedata [449] "logic writedata[575:0]" +Toggle 0to1 writedata [449] "logic writedata[575:0]" +Toggle 1to0 writedata [448] "logic writedata[575:0]" +Toggle 0to1 writedata [448] "logic writedata[575:0]" +Toggle 1to0 writedata [447] "logic writedata[575:0]" +Toggle 0to1 writedata [447] "logic writedata[575:0]" +Toggle 1to0 writedata [446] "logic writedata[575:0]" +Toggle 0to1 writedata [446] "logic writedata[575:0]" +Toggle 1to0 writedata [445] "logic writedata[575:0]" +Toggle 0to1 writedata [445] "logic writedata[575:0]" +Toggle 1to0 writedata [444] "logic writedata[575:0]" +Toggle 0to1 writedata [444] "logic writedata[575:0]" +Toggle 1to0 writedata [443] "logic writedata[575:0]" +Toggle 0to1 writedata [443] "logic writedata[575:0]" +Toggle 1to0 writedata [442] "logic writedata[575:0]" +Toggle 0to1 writedata [442] "logic writedata[575:0]" +Toggle 1to0 writedata [441] "logic writedata[575:0]" +Toggle 0to1 writedata [441] "logic writedata[575:0]" +Toggle 1to0 writedata [440] "logic writedata[575:0]" +Toggle 0to1 writedata [440] "logic writedata[575:0]" +Toggle 1to0 writedata [439] "logic writedata[575:0]" +Toggle 0to1 writedata [439] "logic writedata[575:0]" +Toggle 1to0 writedata [438] "logic writedata[575:0]" +Toggle 0to1 writedata [438] "logic writedata[575:0]" +Toggle 1to0 writedata [437] "logic writedata[575:0]" +Toggle 0to1 writedata [437] "logic writedata[575:0]" +Toggle 1to0 writedata [436] "logic writedata[575:0]" +Toggle 0to1 writedata [436] "logic writedata[575:0]" +Toggle 1to0 writedata [435] "logic writedata[575:0]" +Toggle 0to1 writedata [435] "logic writedata[575:0]" +Toggle 1to0 writedata [434] "logic writedata[575:0]" +Toggle 0to1 writedata [434] "logic writedata[575:0]" +Toggle 1to0 writedata [433] "logic writedata[575:0]" +Toggle 0to1 writedata [433] "logic writedata[575:0]" +Toggle 1to0 writedata [432] "logic writedata[575:0]" +Toggle 0to1 writedata [432] "logic writedata[575:0]" +Toggle 1to0 writedata [431] "logic writedata[575:0]" +Toggle 0to1 writedata [431] "logic writedata[575:0]" +Toggle 1to0 writedata [430] "logic writedata[575:0]" +Toggle 0to1 writedata [430] "logic writedata[575:0]" +Toggle 1to0 writedata [429] "logic writedata[575:0]" +Toggle 0to1 writedata [429] "logic writedata[575:0]" +Toggle 1to0 writedata [428] "logic writedata[575:0]" +Toggle 0to1 writedata [428] "logic writedata[575:0]" +Toggle 1to0 writedata [427] "logic writedata[575:0]" +Toggle 0to1 writedata [427] "logic writedata[575:0]" +Toggle 1to0 writedata [426] "logic writedata[575:0]" +Toggle 0to1 writedata [426] "logic writedata[575:0]" +Toggle 1to0 writedata [425] "logic writedata[575:0]" +Toggle 0to1 writedata [425] "logic writedata[575:0]" +Toggle 1to0 writedata [424] "logic writedata[575:0]" +Toggle 0to1 writedata [424] "logic writedata[575:0]" +Toggle 1to0 writedata [423] "logic writedata[575:0]" +Toggle 0to1 writedata [423] "logic writedata[575:0]" +Toggle 1to0 writedata [422] "logic writedata[575:0]" +Toggle 0to1 writedata [422] "logic writedata[575:0]" +Toggle 1to0 writedata [421] "logic writedata[575:0]" +Toggle 0to1 writedata [421] "logic writedata[575:0]" +Toggle 1to0 writedata [420] "logic writedata[575:0]" +Toggle 0to1 writedata [420] "logic writedata[575:0]" +Toggle 1to0 writedata [419] "logic writedata[575:0]" +Toggle 0to1 writedata [419] "logic writedata[575:0]" +Toggle 1to0 writedata [418] "logic writedata[575:0]" +Toggle 0to1 writedata [418] "logic writedata[575:0]" +Toggle 1to0 writedata [417] "logic writedata[575:0]" +Toggle 0to1 writedata [417] "logic writedata[575:0]" +Toggle 1to0 writedata [416] "logic writedata[575:0]" +Toggle 0to1 writedata [416] "logic writedata[575:0]" +Toggle 1to0 writedata [415] "logic writedata[575:0]" +Toggle 0to1 writedata [415] "logic writedata[575:0]" +Toggle 1to0 writedata [414] "logic writedata[575:0]" +Toggle 0to1 writedata [414] "logic writedata[575:0]" +Toggle 1to0 writedata [413] "logic writedata[575:0]" +Toggle 0to1 writedata [413] "logic writedata[575:0]" +Toggle 1to0 writedata [412] "logic writedata[575:0]" +Toggle 0to1 writedata [412] "logic writedata[575:0]" +Toggle 1to0 writedata [411] "logic writedata[575:0]" +Toggle 0to1 writedata [411] "logic writedata[575:0]" +Toggle 1to0 writedata [410] "logic writedata[575:0]" +Toggle 0to1 writedata [410] "logic writedata[575:0]" +Toggle 1to0 writedata [409] "logic writedata[575:0]" +Toggle 0to1 writedata [409] "logic writedata[575:0]" +Toggle 1to0 writedata [408] "logic writedata[575:0]" +Toggle 0to1 writedata [408] "logic writedata[575:0]" +Toggle 1to0 writedata [407] "logic writedata[575:0]" +Toggle 0to1 writedata [407] "logic writedata[575:0]" +Toggle 1to0 writedata [406] "logic writedata[575:0]" +Toggle 0to1 writedata [406] "logic writedata[575:0]" +Toggle 1to0 writedata [405] "logic writedata[575:0]" +Toggle 0to1 writedata [405] "logic writedata[575:0]" +Toggle 1to0 writedata [404] "logic writedata[575:0]" +Toggle 0to1 writedata [404] "logic writedata[575:0]" +Toggle 1to0 writedata [403] "logic writedata[575:0]" +Toggle 0to1 writedata [403] "logic writedata[575:0]" +Toggle 1to0 writedata [402] "logic writedata[575:0]" +Toggle 0to1 writedata [402] "logic writedata[575:0]" +Toggle 1to0 writedata [401] "logic writedata[575:0]" +Toggle 0to1 writedata [401] "logic writedata[575:0]" +Toggle 1to0 writedata [400] "logic writedata[575:0]" +Toggle 0to1 writedata [400] "logic writedata[575:0]" +Toggle 1to0 writedata [399] "logic writedata[575:0]" +Toggle 0to1 writedata [399] "logic writedata[575:0]" +Toggle 1to0 writedata [398] "logic writedata[575:0]" +Toggle 0to1 writedata [398] "logic writedata[575:0]" +Toggle 1to0 writedata [397] "logic writedata[575:0]" +Toggle 0to1 writedata [397] "logic writedata[575:0]" +Toggle 1to0 writedata [396] "logic writedata[575:0]" +Toggle 0to1 writedata [396] "logic writedata[575:0]" +Toggle 1to0 writedata [395] "logic writedata[575:0]" +Toggle 0to1 writedata [395] "logic writedata[575:0]" +Toggle 1to0 writedata [394] "logic writedata[575:0]" +Toggle 0to1 writedata [394] "logic writedata[575:0]" +Toggle 1to0 writedata [393] "logic writedata[575:0]" +Toggle 0to1 writedata [393] "logic writedata[575:0]" +Toggle 1to0 writedata [392] "logic writedata[575:0]" +Toggle 0to1 writedata [392] "logic writedata[575:0]" +Toggle 1to0 writedata [391] "logic writedata[575:0]" +Toggle 0to1 writedata [391] "logic writedata[575:0]" +Toggle 1to0 writedata [390] "logic writedata[575:0]" +Toggle 0to1 writedata [390] "logic writedata[575:0]" +Toggle 1to0 writedata [389] "logic writedata[575:0]" +Toggle 0to1 writedata [389] "logic writedata[575:0]" +Toggle 1to0 writedata [388] "logic writedata[575:0]" +Toggle 0to1 writedata [388] "logic writedata[575:0]" +Toggle 1to0 writedata [387] "logic writedata[575:0]" +Toggle 0to1 writedata [387] "logic writedata[575:0]" +Toggle 1to0 writedata [386] "logic writedata[575:0]" +Toggle 0to1 writedata [386] "logic writedata[575:0]" +Toggle 1to0 writedata [385] "logic writedata[575:0]" +Toggle 0to1 writedata [385] "logic writedata[575:0]" +Toggle 1to0 writedata [384] "logic writedata[575:0]" +Toggle 0to1 writedata [384] "logic writedata[575:0]" +Toggle 1to0 writedata [383] "logic writedata[575:0]" +Toggle 0to1 writedata [383] "logic writedata[575:0]" +Toggle 1to0 writedata [382] "logic writedata[575:0]" +Toggle 0to1 writedata [382] "logic writedata[575:0]" +Toggle 1to0 writedata [381] "logic writedata[575:0]" +Toggle 0to1 writedata [381] "logic writedata[575:0]" +Toggle 1to0 writedata [380] "logic writedata[575:0]" +Toggle 0to1 writedata [380] "logic writedata[575:0]" +Toggle 1to0 writedata [379] "logic writedata[575:0]" +Toggle 0to1 writedata [379] "logic writedata[575:0]" +Toggle 1to0 writedata [378] "logic writedata[575:0]" +Toggle 0to1 writedata [378] "logic writedata[575:0]" +Toggle 1to0 writedata [377] "logic writedata[575:0]" +Toggle 0to1 writedata [377] "logic writedata[575:0]" +Toggle 1to0 writedata [376] "logic writedata[575:0]" +Toggle 0to1 writedata [376] "logic writedata[575:0]" +Toggle 1to0 writedata [375] "logic writedata[575:0]" +Toggle 0to1 writedata [375] "logic writedata[575:0]" +Toggle 1to0 writedata [374] "logic writedata[575:0]" +Toggle 0to1 writedata [374] "logic writedata[575:0]" +Toggle 1to0 writedata [373] "logic writedata[575:0]" +Toggle 0to1 writedata [373] "logic writedata[575:0]" +Toggle 1to0 writedata [372] "logic writedata[575:0]" +Toggle 0to1 writedata [372] "logic writedata[575:0]" +Toggle 1to0 writedata [371] "logic writedata[575:0]" +Toggle 0to1 writedata [371] "logic writedata[575:0]" +Toggle 1to0 writedata [370] "logic writedata[575:0]" +Toggle 0to1 writedata [370] "logic writedata[575:0]" +Toggle 1to0 writedata [369] "logic writedata[575:0]" +Toggle 0to1 writedata [369] "logic writedata[575:0]" +Toggle 1to0 writedata [368] "logic writedata[575:0]" +Toggle 0to1 writedata [368] "logic writedata[575:0]" +Toggle 1to0 writedata [367] "logic writedata[575:0]" +Toggle 0to1 writedata [367] "logic writedata[575:0]" +Toggle 1to0 writedata [366] "logic writedata[575:0]" +Toggle 0to1 writedata [366] "logic writedata[575:0]" +Toggle 1to0 writedata [365] "logic writedata[575:0]" +Toggle 0to1 writedata [365] "logic writedata[575:0]" +Toggle 1to0 writedata [364] "logic writedata[575:0]" +Toggle 0to1 writedata [364] "logic writedata[575:0]" +Toggle 1to0 writedata [363] "logic writedata[575:0]" +Toggle 0to1 writedata [363] "logic writedata[575:0]" +Toggle 1to0 writedata [362] "logic writedata[575:0]" +Toggle 0to1 writedata [362] "logic writedata[575:0]" +Toggle 1to0 writedata [361] "logic writedata[575:0]" +Toggle 0to1 writedata [361] "logic writedata[575:0]" +Toggle 1to0 writedata [360] "logic writedata[575:0]" +Toggle 0to1 writedata [360] "logic writedata[575:0]" +Toggle 1to0 writedata [359] "logic writedata[575:0]" +Toggle 0to1 writedata [359] "logic writedata[575:0]" +Toggle 1to0 writedata [358] "logic writedata[575:0]" +Toggle 0to1 writedata [358] "logic writedata[575:0]" +Toggle 1to0 writedata [357] "logic writedata[575:0]" +Toggle 0to1 writedata [357] "logic writedata[575:0]" +Toggle 1to0 writedata [356] "logic writedata[575:0]" +Toggle 0to1 writedata [356] "logic writedata[575:0]" +Toggle 1to0 writedata [355] "logic writedata[575:0]" +Toggle 0to1 writedata [355] "logic writedata[575:0]" +Toggle 1to0 writedata [354] "logic writedata[575:0]" +Toggle 0to1 writedata [354] "logic writedata[575:0]" +Toggle 1to0 writedata [353] "logic writedata[575:0]" +Toggle 0to1 writedata [353] "logic writedata[575:0]" +Toggle 1to0 writedata [352] "logic writedata[575:0]" +Toggle 0to1 writedata [352] "logic writedata[575:0]" +Toggle 1to0 writedata [351] "logic writedata[575:0]" +Toggle 0to1 writedata [351] "logic writedata[575:0]" +Toggle 1to0 writedata [350] "logic writedata[575:0]" +Toggle 0to1 writedata [350] "logic writedata[575:0]" +Toggle 1to0 writedata [349] "logic writedata[575:0]" +Toggle 0to1 writedata [349] "logic writedata[575:0]" +Toggle 1to0 writedata [348] "logic writedata[575:0]" +Toggle 0to1 writedata [348] "logic writedata[575:0]" +Toggle 1to0 writedata [347] "logic writedata[575:0]" +Toggle 0to1 writedata [347] "logic writedata[575:0]" +Toggle 1to0 writedata [346] "logic writedata[575:0]" +Toggle 0to1 writedata [346] "logic writedata[575:0]" +Toggle 1to0 writedata [345] "logic writedata[575:0]" +Toggle 0to1 writedata [345] "logic writedata[575:0]" +Toggle 1to0 writedata [344] "logic writedata[575:0]" +Toggle 0to1 writedata [344] "logic writedata[575:0]" +Toggle 1to0 writedata [343] "logic writedata[575:0]" +Toggle 0to1 writedata [343] "logic writedata[575:0]" +Toggle 1to0 writedata [342] "logic writedata[575:0]" +Toggle 0to1 writedata [342] "logic writedata[575:0]" +Toggle 1to0 writedata [341] "logic writedata[575:0]" +Toggle 0to1 writedata [341] "logic writedata[575:0]" +Toggle 1to0 writedata [340] "logic writedata[575:0]" +Toggle 0to1 writedata [340] "logic writedata[575:0]" +Toggle 1to0 writedata [339] "logic writedata[575:0]" +Toggle 0to1 writedata [339] "logic writedata[575:0]" +Toggle 1to0 writedata [338] "logic writedata[575:0]" +Toggle 0to1 writedata [338] "logic writedata[575:0]" +Toggle 1to0 writedata [337] "logic writedata[575:0]" +Toggle 0to1 writedata [337] "logic writedata[575:0]" +Toggle 1to0 writedata [336] "logic writedata[575:0]" +Toggle 0to1 writedata [336] "logic writedata[575:0]" +Toggle 1to0 writedata [335] "logic writedata[575:0]" +Toggle 0to1 writedata [335] "logic writedata[575:0]" +Toggle 1to0 writedata [334] "logic writedata[575:0]" +Toggle 0to1 writedata [334] "logic writedata[575:0]" +Toggle 1to0 writedata [333] "logic writedata[575:0]" +Toggle 0to1 writedata [333] "logic writedata[575:0]" +Toggle 1to0 writedata [332] "logic writedata[575:0]" +Toggle 0to1 writedata [332] "logic writedata[575:0]" +Toggle 1to0 writedata [331] "logic writedata[575:0]" +Toggle 0to1 writedata [331] "logic writedata[575:0]" +Toggle 1to0 writedata [330] "logic writedata[575:0]" +Toggle 0to1 writedata [330] "logic writedata[575:0]" +Toggle 1to0 writedata [329] "logic writedata[575:0]" +Toggle 0to1 writedata [329] "logic writedata[575:0]" +Toggle 1to0 writedata [328] "logic writedata[575:0]" +Toggle 0to1 writedata [328] "logic writedata[575:0]" +Toggle 1to0 writedata [327] "logic writedata[575:0]" +Toggle 0to1 writedata [327] "logic writedata[575:0]" +Toggle 1to0 writedata [326] "logic writedata[575:0]" +Toggle 0to1 writedata [326] "logic writedata[575:0]" +Toggle 1to0 writedata [325] "logic writedata[575:0]" +Toggle 0to1 writedata [325] "logic writedata[575:0]" +Toggle 1to0 writedata [324] "logic writedata[575:0]" +Toggle 0to1 writedata [324] "logic writedata[575:0]" +Toggle 1to0 writedata [323] "logic writedata[575:0]" +Toggle 0to1 writedata [323] "logic writedata[575:0]" +Toggle 1to0 writedata [322] "logic writedata[575:0]" +Toggle 0to1 writedata [322] "logic writedata[575:0]" +Toggle 1to0 writedata [321] "logic writedata[575:0]" +Toggle 0to1 writedata [321] "logic writedata[575:0]" +Toggle 1to0 writedata [320] "logic writedata[575:0]" +Toggle 0to1 writedata [320] "logic writedata[575:0]" +Toggle 1to0 writedata [319] "logic writedata[575:0]" +Toggle 0to1 writedata [319] "logic writedata[575:0]" +Toggle 1to0 writedata [318] "logic writedata[575:0]" +Toggle 0to1 writedata [318] "logic writedata[575:0]" +Toggle 1to0 writedata [317] "logic writedata[575:0]" +Toggle 0to1 writedata [317] "logic writedata[575:0]" +Toggle 1to0 writedata [316] "logic writedata[575:0]" +Toggle 0to1 writedata [316] "logic writedata[575:0]" +Toggle 1to0 writedata [315] "logic writedata[575:0]" +Toggle 0to1 writedata [315] "logic writedata[575:0]" +Toggle 1to0 writedata [314] "logic writedata[575:0]" +Toggle 0to1 writedata [314] "logic writedata[575:0]" +Toggle 1to0 writedata [313] "logic writedata[575:0]" +Toggle 0to1 writedata [313] "logic writedata[575:0]" +Toggle 1to0 writedata [312] "logic writedata[575:0]" +Toggle 0to1 writedata [312] "logic writedata[575:0]" +Toggle 1to0 writedata [311] "logic writedata[575:0]" +Toggle 0to1 writedata [311] "logic writedata[575:0]" +Toggle 1to0 writedata [310] "logic writedata[575:0]" +Toggle 0to1 writedata [310] "logic writedata[575:0]" +Toggle 1to0 writedata [309] "logic writedata[575:0]" +Toggle 0to1 writedata [309] "logic writedata[575:0]" +Toggle 1to0 writedata [308] "logic writedata[575:0]" +Toggle 0to1 writedata [308] "logic writedata[575:0]" +Toggle 1to0 writedata [307] "logic writedata[575:0]" +Toggle 0to1 writedata [307] "logic writedata[575:0]" +Toggle 1to0 writedata [306] "logic writedata[575:0]" +Toggle 0to1 writedata [306] "logic writedata[575:0]" +Toggle 1to0 writedata [305] "logic writedata[575:0]" +Toggle 0to1 writedata [305] "logic writedata[575:0]" +Toggle 1to0 writedata [304] "logic writedata[575:0]" +Toggle 0to1 writedata [304] "logic writedata[575:0]" +Toggle 1to0 writedata [303] "logic writedata[575:0]" +Toggle 0to1 writedata [303] "logic writedata[575:0]" +Toggle 1to0 writedata [302] "logic writedata[575:0]" +Toggle 0to1 writedata [302] "logic writedata[575:0]" +Toggle 1to0 writedata [301] "logic writedata[575:0]" +Toggle 0to1 writedata [301] "logic writedata[575:0]" +Toggle 1to0 writedata [300] "logic writedata[575:0]" +Toggle 0to1 writedata [300] "logic writedata[575:0]" +Toggle 1to0 writedata [299] "logic writedata[575:0]" +Toggle 0to1 writedata [299] "logic writedata[575:0]" +Toggle 1to0 writedata [298] "logic writedata[575:0]" +Toggle 0to1 writedata [298] "logic writedata[575:0]" +Toggle 1to0 writedata [297] "logic writedata[575:0]" +Toggle 0to1 writedata [297] "logic writedata[575:0]" +Toggle 1to0 writedata [296] "logic writedata[575:0]" +Toggle 0to1 writedata [296] "logic writedata[575:0]" +Toggle 1to0 writedata [295] "logic writedata[575:0]" +Toggle 0to1 writedata [295] "logic writedata[575:0]" +Toggle 1to0 writedata [294] "logic writedata[575:0]" +Toggle 0to1 writedata [294] "logic writedata[575:0]" +Toggle 1to0 writedata [293] "logic writedata[575:0]" +Toggle 0to1 writedata [293] "logic writedata[575:0]" +Toggle 1to0 writedata [292] "logic writedata[575:0]" +Toggle 0to1 writedata [292] "logic writedata[575:0]" +Toggle 1to0 writedata [291] "logic writedata[575:0]" +Toggle 0to1 writedata [291] "logic writedata[575:0]" +Toggle 1to0 writedata [290] "logic writedata[575:0]" +Toggle 0to1 writedata [290] "logic writedata[575:0]" +Toggle 1to0 writedata [289] "logic writedata[575:0]" +Toggle 0to1 writedata [289] "logic writedata[575:0]" +Toggle 1to0 writedata [288] "logic writedata[575:0]" +Toggle 0to1 writedata [288] "logic writedata[575:0]" +Toggle 1to0 writedata [287] "logic writedata[575:0]" +Toggle 0to1 writedata [287] "logic writedata[575:0]" +Toggle 1to0 writedata [286] "logic writedata[575:0]" +Toggle 0to1 writedata [286] "logic writedata[575:0]" +Toggle 1to0 writedata [285] "logic writedata[575:0]" +Toggle 0to1 writedata [285] "logic writedata[575:0]" +Toggle 1to0 writedata [284] "logic writedata[575:0]" +Toggle 0to1 writedata [284] "logic writedata[575:0]" +Toggle 1to0 writedata [283] "logic writedata[575:0]" +Toggle 0to1 writedata [283] "logic writedata[575:0]" +Toggle 1to0 writedata [282] "logic writedata[575:0]" +Toggle 0to1 writedata [282] "logic writedata[575:0]" +Toggle 1to0 writedata [281] "logic writedata[575:0]" +Toggle 0to1 writedata [281] "logic writedata[575:0]" +Toggle 1to0 writedata [280] "logic writedata[575:0]" +Toggle 0to1 writedata [280] "logic writedata[575:0]" +Toggle 1to0 writedata [279] "logic writedata[575:0]" +Toggle 0to1 writedata [279] "logic writedata[575:0]" +Toggle 1to0 writedata [278] "logic writedata[575:0]" +Toggle 0to1 writedata [278] "logic writedata[575:0]" +Toggle 1to0 writedata [277] "logic writedata[575:0]" +Toggle 0to1 writedata [277] "logic writedata[575:0]" +Toggle 1to0 writedata [276] "logic writedata[575:0]" +Toggle 0to1 writedata [276] "logic writedata[575:0]" +Toggle 1to0 writedata [275] "logic writedata[575:0]" +Toggle 0to1 writedata [275] "logic writedata[575:0]" +Toggle 1to0 writedata [274] "logic writedata[575:0]" +Toggle 0to1 writedata [274] "logic writedata[575:0]" +Toggle 1to0 writedata [273] "logic writedata[575:0]" +Toggle 0to1 writedata [273] "logic writedata[575:0]" +Toggle 1to0 writedata [272] "logic writedata[575:0]" +Toggle 0to1 writedata [272] "logic writedata[575:0]" +Toggle 1to0 writedata [271] "logic writedata[575:0]" +Toggle 0to1 writedata [271] "logic writedata[575:0]" +Toggle 1to0 writedata [270] "logic writedata[575:0]" +Toggle 0to1 writedata [270] "logic writedata[575:0]" +Toggle 1to0 writedata [269] "logic writedata[575:0]" +Toggle 0to1 writedata [269] "logic writedata[575:0]" +Toggle 1to0 writedata [268] "logic writedata[575:0]" +Toggle 0to1 writedata [268] "logic writedata[575:0]" +Toggle 1to0 writedata [267] "logic writedata[575:0]" +Toggle 0to1 writedata [267] "logic writedata[575:0]" +Toggle 1to0 writedata [266] "logic writedata[575:0]" +Toggle 0to1 writedata [266] "logic writedata[575:0]" +Toggle 1to0 writedata [265] "logic writedata[575:0]" +Toggle 0to1 writedata [265] "logic writedata[575:0]" +Toggle 1to0 writedata [264] "logic writedata[575:0]" +Toggle 0to1 writedata [264] "logic writedata[575:0]" +Toggle 1to0 writedata [263] "logic writedata[575:0]" +Toggle 0to1 writedata [263] "logic writedata[575:0]" +Toggle 1to0 writedata [262] "logic writedata[575:0]" +Toggle 0to1 writedata [262] "logic writedata[575:0]" +Toggle 1to0 writedata [261] "logic writedata[575:0]" +Toggle 0to1 writedata [261] "logic writedata[575:0]" +Toggle 1to0 writedata [260] "logic writedata[575:0]" +Toggle 0to1 writedata [260] "logic writedata[575:0]" +Toggle 1to0 writedata [259] "logic writedata[575:0]" +Toggle 0to1 writedata [259] "logic writedata[575:0]" +Toggle 1to0 writedata [258] "logic writedata[575:0]" +Toggle 0to1 writedata [258] "logic writedata[575:0]" +Toggle 1to0 writedata [257] "logic writedata[575:0]" +Toggle 0to1 writedata [257] "logic writedata[575:0]" +Toggle 1to0 writedata [256] "logic writedata[575:0]" +Toggle 0to1 writedata [256] "logic writedata[575:0]" +Toggle 1to0 writedata [255] "logic writedata[575:0]" +Toggle 0to1 writedata [255] "logic writedata[575:0]" +Toggle 1to0 writedata [254] "logic writedata[575:0]" +Toggle 0to1 writedata [254] "logic writedata[575:0]" +Toggle 1to0 writedata [253] "logic writedata[575:0]" +Toggle 0to1 writedata [253] "logic writedata[575:0]" +Toggle 1to0 writedata [252] "logic writedata[575:0]" +Toggle 0to1 writedata [252] "logic writedata[575:0]" +Toggle 1to0 writedata [251] "logic writedata[575:0]" +Toggle 0to1 writedata [251] "logic writedata[575:0]" +Toggle 1to0 writedata [250] "logic writedata[575:0]" +Toggle 0to1 writedata [250] "logic writedata[575:0]" +Toggle 1to0 writedata [249] "logic writedata[575:0]" +Toggle 0to1 writedata [249] "logic writedata[575:0]" +Toggle 1to0 writedata [248] "logic writedata[575:0]" +Toggle 0to1 writedata [248] "logic writedata[575:0]" +Toggle 1to0 writedata [247] "logic writedata[575:0]" +Toggle 0to1 writedata [247] "logic writedata[575:0]" +Toggle 1to0 writedata [246] "logic writedata[575:0]" +Toggle 0to1 writedata [246] "logic writedata[575:0]" +Toggle 1to0 writedata [245] "logic writedata[575:0]" +Toggle 0to1 writedata [245] "logic writedata[575:0]" +Toggle 1to0 writedata [244] "logic writedata[575:0]" +Toggle 0to1 writedata [244] "logic writedata[575:0]" +Toggle 1to0 writedata [243] "logic writedata[575:0]" +Toggle 0to1 writedata [243] "logic writedata[575:0]" +Toggle 1to0 writedata [242] "logic writedata[575:0]" +Toggle 0to1 writedata [242] "logic writedata[575:0]" +Toggle 1to0 writedata [241] "logic writedata[575:0]" +Toggle 0to1 writedata [241] "logic writedata[575:0]" +Toggle 1to0 writedata [240] "logic writedata[575:0]" +Toggle 0to1 writedata [240] "logic writedata[575:0]" +Toggle 1to0 writedata [239] "logic writedata[575:0]" +Toggle 0to1 writedata [239] "logic writedata[575:0]" +Toggle 1to0 writedata [238] "logic writedata[575:0]" +Toggle 0to1 writedata [238] "logic writedata[575:0]" +Toggle 1to0 writedata [237] "logic writedata[575:0]" +Toggle 0to1 writedata [237] "logic writedata[575:0]" +Toggle 1to0 writedata [236] "logic writedata[575:0]" +Toggle 0to1 writedata [236] "logic writedata[575:0]" +Toggle 1to0 writedata [235] "logic writedata[575:0]" +Toggle 0to1 writedata [235] "logic writedata[575:0]" +Toggle 1to0 writedata [234] "logic writedata[575:0]" +Toggle 0to1 writedata [234] "logic writedata[575:0]" +Toggle 1to0 writedata [233] "logic writedata[575:0]" +Toggle 0to1 writedata [233] "logic writedata[575:0]" +Toggle 1to0 writedata [232] "logic writedata[575:0]" +Toggle 0to1 writedata [232] "logic writedata[575:0]" +Toggle 1to0 writedata [231] "logic writedata[575:0]" +Toggle 0to1 writedata [231] "logic writedata[575:0]" +Toggle 1to0 writedata [230] "logic writedata[575:0]" +Toggle 0to1 writedata [230] "logic writedata[575:0]" +Toggle 1to0 writedata [229] "logic writedata[575:0]" +Toggle 0to1 writedata [229] "logic writedata[575:0]" +Toggle 1to0 writedata [228] "logic writedata[575:0]" +Toggle 0to1 writedata [228] "logic writedata[575:0]" +Toggle 1to0 writedata [227] "logic writedata[575:0]" +Toggle 0to1 writedata [227] "logic writedata[575:0]" +Toggle 1to0 writedata [226] "logic writedata[575:0]" +Toggle 0to1 writedata [226] "logic writedata[575:0]" +Toggle 1to0 writedata [225] "logic writedata[575:0]" +Toggle 0to1 writedata [225] "logic writedata[575:0]" +Toggle 1to0 writedata [224] "logic writedata[575:0]" +Toggle 0to1 writedata [224] "logic writedata[575:0]" +Toggle 1to0 writedata [223] "logic writedata[575:0]" +Toggle 0to1 writedata [223] "logic writedata[575:0]" +Toggle 1to0 writedata [222] "logic writedata[575:0]" +Toggle 0to1 writedata [222] "logic writedata[575:0]" +Toggle 1to0 writedata [221] "logic writedata[575:0]" +Toggle 0to1 writedata [221] "logic writedata[575:0]" +Toggle 1to0 writedata [220] "logic writedata[575:0]" +Toggle 0to1 writedata [220] "logic writedata[575:0]" +Toggle 1to0 writedata [219] "logic writedata[575:0]" +Toggle 0to1 writedata [219] "logic writedata[575:0]" +Toggle 1to0 writedata [218] "logic writedata[575:0]" +Toggle 0to1 writedata [218] "logic writedata[575:0]" +Toggle 1to0 writedata [217] "logic writedata[575:0]" +Toggle 0to1 writedata [217] "logic writedata[575:0]" +Toggle 1to0 writedata [216] "logic writedata[575:0]" +Toggle 0to1 writedata [216] "logic writedata[575:0]" +Toggle 1to0 writedata [215] "logic writedata[575:0]" +Toggle 0to1 writedata [215] "logic writedata[575:0]" +Toggle 1to0 writedata [214] "logic writedata[575:0]" +Toggle 0to1 writedata [214] "logic writedata[575:0]" +Toggle 1to0 writedata [213] "logic writedata[575:0]" +Toggle 0to1 writedata [213] "logic writedata[575:0]" +Toggle 1to0 writedata [212] "logic writedata[575:0]" +Toggle 0to1 writedata [212] "logic writedata[575:0]" +Toggle 1to0 writedata [211] "logic writedata[575:0]" +Toggle 0to1 writedata [211] "logic writedata[575:0]" +Toggle 1to0 writedata [210] "logic writedata[575:0]" +Toggle 0to1 writedata [210] "logic writedata[575:0]" +Toggle 1to0 writedata [209] "logic writedata[575:0]" +Toggle 0to1 writedata [209] "logic writedata[575:0]" +Toggle 1to0 writedata [208] "logic writedata[575:0]" +Toggle 0to1 writedata [208] "logic writedata[575:0]" +Toggle 1to0 writedata [207] "logic writedata[575:0]" +Toggle 0to1 writedata [207] "logic writedata[575:0]" +Toggle 1to0 writedata [206] "logic writedata[575:0]" +Toggle 0to1 writedata [206] "logic writedata[575:0]" +Toggle 1to0 writedata [205] "logic writedata[575:0]" +Toggle 0to1 writedata [205] "logic writedata[575:0]" +Toggle 1to0 writedata [204] "logic writedata[575:0]" +Toggle 0to1 writedata [204] "logic writedata[575:0]" +Toggle 1to0 writedata [203] "logic writedata[575:0]" +Toggle 0to1 writedata [203] "logic writedata[575:0]" +Toggle 1to0 writedata [202] "logic writedata[575:0]" +Toggle 0to1 writedata [202] "logic writedata[575:0]" +Toggle 1to0 writedata [201] "logic writedata[575:0]" +Toggle 0to1 writedata [201] "logic writedata[575:0]" +Toggle 1to0 writedata [200] "logic writedata[575:0]" +Toggle 0to1 writedata [200] "logic writedata[575:0]" +Toggle 1to0 writedata [199] "logic writedata[575:0]" +Toggle 0to1 writedata [199] "logic writedata[575:0]" +Toggle 1to0 writedata [198] "logic writedata[575:0]" +Toggle 0to1 writedata [198] "logic writedata[575:0]" +Toggle 1to0 writedata [197] "logic writedata[575:0]" +Toggle 0to1 writedata [197] "logic writedata[575:0]" +Toggle 1to0 writedata [196] "logic writedata[575:0]" +Toggle 0to1 writedata [196] "logic writedata[575:0]" +Toggle 1to0 writedata [195] "logic writedata[575:0]" +Toggle 0to1 writedata [195] "logic writedata[575:0]" +Toggle 1to0 writedata [194] "logic writedata[575:0]" +Toggle 0to1 writedata [194] "logic writedata[575:0]" +Toggle 1to0 writedata [193] "logic writedata[575:0]" +Toggle 0to1 writedata [193] "logic writedata[575:0]" +Toggle 1to0 writedata [192] "logic writedata[575:0]" +Toggle 0to1 writedata [192] "logic writedata[575:0]" +Toggle 1to0 writedata [191] "logic writedata[575:0]" +Toggle 0to1 writedata [191] "logic writedata[575:0]" +Toggle 1to0 writedata [190] "logic writedata[575:0]" +Toggle 0to1 writedata [190] "logic writedata[575:0]" +Toggle 1to0 writedata [189] "logic writedata[575:0]" +Toggle 0to1 writedata [189] "logic writedata[575:0]" +Toggle 1to0 writedata [188] "logic writedata[575:0]" +Toggle 0to1 writedata [188] "logic writedata[575:0]" +Toggle 1to0 writedata [187] "logic writedata[575:0]" +Toggle 0to1 writedata [187] "logic writedata[575:0]" +Toggle 1to0 writedata [186] "logic writedata[575:0]" +Toggle 0to1 writedata [186] "logic writedata[575:0]" +Toggle 1to0 writedata [185] "logic writedata[575:0]" +Toggle 0to1 writedata [185] "logic writedata[575:0]" +Toggle 1to0 writedata [184] "logic writedata[575:0]" +Toggle 0to1 writedata [184] "logic writedata[575:0]" +Toggle 1to0 writedata [183] "logic writedata[575:0]" +Toggle 0to1 writedata [183] "logic writedata[575:0]" +Toggle 1to0 writedata [182] "logic writedata[575:0]" +Toggle 0to1 writedata [182] "logic writedata[575:0]" +Toggle 1to0 writedata [181] "logic writedata[575:0]" +Toggle 0to1 writedata [181] "logic writedata[575:0]" +Toggle 1to0 writedata [180] "logic writedata[575:0]" +Toggle 0to1 writedata [180] "logic writedata[575:0]" +Toggle 1to0 writedata [179] "logic writedata[575:0]" +Toggle 0to1 writedata [179] "logic writedata[575:0]" +Toggle 1to0 writedata [178] "logic writedata[575:0]" +Toggle 0to1 writedata [178] "logic writedata[575:0]" +Toggle 1to0 writedata [177] "logic writedata[575:0]" +Toggle 0to1 writedata [177] "logic writedata[575:0]" +Toggle 1to0 writedata [176] "logic writedata[575:0]" +Toggle 0to1 writedata [176] "logic writedata[575:0]" +Toggle 1to0 writedata [175] "logic writedata[575:0]" +Toggle 0to1 writedata [175] "logic writedata[575:0]" +Toggle 1to0 writedata [174] "logic writedata[575:0]" +Toggle 0to1 writedata [174] "logic writedata[575:0]" +Toggle 1to0 writedata [173] "logic writedata[575:0]" +Toggle 0to1 writedata [173] "logic writedata[575:0]" +Toggle 1to0 writedata [172] "logic writedata[575:0]" +Toggle 0to1 writedata [172] "logic writedata[575:0]" +Toggle 1to0 writedata [171] "logic writedata[575:0]" +Toggle 0to1 writedata [171] "logic writedata[575:0]" +Toggle 1to0 writedata [170] "logic writedata[575:0]" +Toggle 0to1 writedata [170] "logic writedata[575:0]" +Toggle 1to0 writedata [169] "logic writedata[575:0]" +Toggle 0to1 writedata [169] "logic writedata[575:0]" +Toggle 1to0 writedata [168] "logic writedata[575:0]" +Toggle 0to1 writedata [168] "logic writedata[575:0]" +Toggle 1to0 writedata [167] "logic writedata[575:0]" +Toggle 0to1 writedata [167] "logic writedata[575:0]" +Toggle 1to0 writedata [166] "logic writedata[575:0]" +Toggle 0to1 writedata [166] "logic writedata[575:0]" +Toggle 1to0 writedata [165] "logic writedata[575:0]" +Toggle 0to1 writedata [165] "logic writedata[575:0]" +Toggle 1to0 writedata [164] "logic writedata[575:0]" +Toggle 0to1 writedata [164] "logic writedata[575:0]" +Toggle 1to0 writedata [163] "logic writedata[575:0]" +Toggle 0to1 writedata [163] "logic writedata[575:0]" +Toggle 1to0 writedata [162] "logic writedata[575:0]" +Toggle 0to1 writedata [162] "logic writedata[575:0]" +Toggle 1to0 writedata [161] "logic writedata[575:0]" +Toggle 0to1 writedata [161] "logic writedata[575:0]" +Toggle 1to0 writedata [160] "logic writedata[575:0]" +Toggle 0to1 writedata [160] "logic writedata[575:0]" +Toggle 1to0 writedata [159] "logic writedata[575:0]" +Toggle 0to1 writedata [159] "logic writedata[575:0]" +Toggle 1to0 writedata [158] "logic writedata[575:0]" +Toggle 0to1 writedata [158] "logic writedata[575:0]" +Toggle 1to0 writedata [157] "logic writedata[575:0]" +Toggle 0to1 writedata [157] "logic writedata[575:0]" +Toggle 1to0 writedata [156] "logic writedata[575:0]" +Toggle 0to1 writedata [156] "logic writedata[575:0]" +Toggle 1to0 writedata [155] "logic writedata[575:0]" +Toggle 0to1 writedata [155] "logic writedata[575:0]" +Toggle 1to0 writedata [154] "logic writedata[575:0]" +Toggle 0to1 writedata [154] "logic writedata[575:0]" +Toggle 1to0 writedata [153] "logic writedata[575:0]" +Toggle 0to1 writedata [153] "logic writedata[575:0]" +Toggle 1to0 writedata [152] "logic writedata[575:0]" +Toggle 0to1 writedata [152] "logic writedata[575:0]" +Toggle 1to0 writedata [151] "logic writedata[575:0]" +Toggle 0to1 writedata [151] "logic writedata[575:0]" +Toggle 1to0 writedata [150] "logic writedata[575:0]" +Toggle 0to1 writedata [150] "logic writedata[575:0]" +Toggle 1to0 writedata [149] "logic writedata[575:0]" +Toggle 0to1 writedata [149] "logic writedata[575:0]" +Toggle 1to0 writedata [148] "logic writedata[575:0]" +Toggle 0to1 writedata [148] "logic writedata[575:0]" +Toggle 1to0 writedata [147] "logic writedata[575:0]" +Toggle 0to1 writedata [147] "logic writedata[575:0]" +Toggle 1to0 writedata [146] "logic writedata[575:0]" +Toggle 0to1 writedata [146] "logic writedata[575:0]" +Toggle 1to0 writedata [145] "logic writedata[575:0]" +Toggle 0to1 writedata [145] "logic writedata[575:0]" +Toggle 1to0 writedata [144] "logic writedata[575:0]" +Toggle 0to1 writedata [144] "logic writedata[575:0]" +Toggle 1to0 writedata [143] "logic writedata[575:0]" +Toggle 0to1 writedata [143] "logic writedata[575:0]" +Toggle 1to0 writedata [142] "logic writedata[575:0]" +Toggle 0to1 writedata [142] "logic writedata[575:0]" +Toggle 1to0 writedata [141] "logic writedata[575:0]" +Toggle 0to1 writedata [141] "logic writedata[575:0]" +Toggle 1to0 writedata [140] "logic writedata[575:0]" +Toggle 0to1 writedata [140] "logic writedata[575:0]" +Toggle 1to0 writedata [139] "logic writedata[575:0]" +Toggle 0to1 writedata [139] "logic writedata[575:0]" +Toggle 1to0 writedata [138] "logic writedata[575:0]" +Toggle 0to1 writedata [138] "logic writedata[575:0]" +Toggle 1to0 writedata [137] "logic writedata[575:0]" +Toggle 0to1 writedata [137] "logic writedata[575:0]" +Toggle 1to0 writedata [136] "logic writedata[575:0]" +Toggle 0to1 writedata [136] "logic writedata[575:0]" +Toggle 1to0 writedata [135] "logic writedata[575:0]" +Toggle 0to1 writedata [135] "logic writedata[575:0]" +Toggle 1to0 writedata [134] "logic writedata[575:0]" +Toggle 0to1 writedata [134] "logic writedata[575:0]" +Toggle 1to0 writedata [133] "logic writedata[575:0]" +Toggle 0to1 writedata [133] "logic writedata[575:0]" +Toggle 1to0 writedata [132] "logic writedata[575:0]" +Toggle 0to1 writedata [132] "logic writedata[575:0]" +Toggle 1to0 writedata [131] "logic writedata[575:0]" +Toggle 0to1 writedata [131] "logic writedata[575:0]" +Toggle 1to0 writedata [130] "logic writedata[575:0]" +Toggle 0to1 writedata [130] "logic writedata[575:0]" +Toggle 1to0 writedata [129] "logic writedata[575:0]" +Toggle 0to1 writedata [129] "logic writedata[575:0]" +Toggle 1to0 writedata [128] "logic writedata[575:0]" +Toggle 0to1 writedata [128] "logic writedata[575:0]" +Toggle 1to0 writedata [127] "logic writedata[575:0]" +Toggle 0to1 writedata [127] "logic writedata[575:0]" +Toggle 1to0 writedata [126] "logic writedata[575:0]" +Toggle 0to1 writedata [126] "logic writedata[575:0]" +Toggle 1to0 writedata [125] "logic writedata[575:0]" +Toggle 0to1 writedata [125] "logic writedata[575:0]" +Toggle 1to0 writedata [124] "logic writedata[575:0]" +Toggle 0to1 writedata [124] "logic writedata[575:0]" +Toggle 1to0 writedata [123] "logic writedata[575:0]" +Toggle 0to1 writedata [123] "logic writedata[575:0]" +Toggle 1to0 writedata [122] "logic writedata[575:0]" +Toggle 0to1 writedata [122] "logic writedata[575:0]" +Toggle 1to0 writedata [121] "logic writedata[575:0]" +Toggle 0to1 writedata [121] "logic writedata[575:0]" +Toggle 1to0 writedata [120] "logic writedata[575:0]" +Toggle 0to1 writedata [120] "logic writedata[575:0]" +Toggle 1to0 writedata [119] "logic writedata[575:0]" +Toggle 0to1 writedata [119] "logic writedata[575:0]" +Toggle 1to0 writedata [118] "logic writedata[575:0]" +Toggle 0to1 writedata [118] "logic writedata[575:0]" +Toggle 1to0 writedata [117] "logic writedata[575:0]" +Toggle 0to1 writedata [117] "logic writedata[575:0]" +Toggle 1to0 writedata [116] "logic writedata[575:0]" +Toggle 0to1 writedata [116] "logic writedata[575:0]" +Toggle 1to0 writedata [115] "logic writedata[575:0]" +Toggle 0to1 writedata [115] "logic writedata[575:0]" +Toggle 1to0 writedata [114] "logic writedata[575:0]" +Toggle 0to1 writedata [114] "logic writedata[575:0]" +Toggle 1to0 writedata [113] "logic writedata[575:0]" +Toggle 0to1 writedata [113] "logic writedata[575:0]" +Toggle 1to0 writedata [112] "logic writedata[575:0]" +Toggle 0to1 writedata [112] "logic writedata[575:0]" +Toggle 1to0 writedata [111] "logic writedata[575:0]" +Toggle 0to1 writedata [111] "logic writedata[575:0]" +Toggle 1to0 writedata [110] "logic writedata[575:0]" +Toggle 0to1 writedata [110] "logic writedata[575:0]" +Toggle 1to0 writedata [109] "logic writedata[575:0]" +Toggle 0to1 writedata [109] "logic writedata[575:0]" +Toggle 1to0 writedata [108] "logic writedata[575:0]" +Toggle 0to1 writedata [108] "logic writedata[575:0]" +Toggle 1to0 writedata [107] "logic writedata[575:0]" +Toggle 0to1 writedata [107] "logic writedata[575:0]" +Toggle 1to0 writedata [106] "logic writedata[575:0]" +Toggle 0to1 writedata [106] "logic writedata[575:0]" +Toggle 1to0 writedata [105] "logic writedata[575:0]" +Toggle 0to1 writedata [105] "logic writedata[575:0]" +Toggle 1to0 writedata [104] "logic writedata[575:0]" +Toggle 0to1 writedata [104] "logic writedata[575:0]" +Toggle 1to0 writedata [103] "logic writedata[575:0]" +Toggle 0to1 writedata [103] "logic writedata[575:0]" +Toggle 1to0 writedata [102] "logic writedata[575:0]" +Toggle 0to1 writedata [102] "logic writedata[575:0]" +Toggle 1to0 writedata [101] "logic writedata[575:0]" +Toggle 0to1 writedata [101] "logic writedata[575:0]" +Toggle 1to0 writedata [100] "logic writedata[575:0]" +Toggle 0to1 writedata [100] "logic writedata[575:0]" +Toggle 1to0 writedata [99] "logic writedata[575:0]" +Toggle 0to1 writedata [99] "logic writedata[575:0]" +Toggle 1to0 writedata [98] "logic writedata[575:0]" +Toggle 0to1 writedata [98] "logic writedata[575:0]" +Toggle 1to0 writedata [97] "logic writedata[575:0]" +Toggle 0to1 writedata [97] "logic writedata[575:0]" +Toggle 1to0 writedata [96] "logic writedata[575:0]" +Toggle 0to1 writedata [96] "logic writedata[575:0]" +Toggle 1to0 writedata [95] "logic writedata[575:0]" +Toggle 0to1 writedata [95] "logic writedata[575:0]" +Toggle 1to0 writedata [94] "logic writedata[575:0]" +Toggle 0to1 writedata [94] "logic writedata[575:0]" +Toggle 1to0 writedata [93] "logic writedata[575:0]" +Toggle 0to1 writedata [93] "logic writedata[575:0]" +Toggle 1to0 writedata [92] "logic writedata[575:0]" +Toggle 0to1 writedata [92] "logic writedata[575:0]" +Toggle 1to0 writedata [91] "logic writedata[575:0]" +Toggle 0to1 writedata [91] "logic writedata[575:0]" +Toggle 1to0 writedata [90] "logic writedata[575:0]" +Toggle 0to1 writedata [90] "logic writedata[575:0]" +Toggle 1to0 writedata [89] "logic writedata[575:0]" +Toggle 0to1 writedata [89] "logic writedata[575:0]" +Toggle 1to0 writedata [88] "logic writedata[575:0]" +Toggle 0to1 writedata [88] "logic writedata[575:0]" +Toggle 1to0 writedata [87] "logic writedata[575:0]" +Toggle 0to1 writedata [87] "logic writedata[575:0]" +Toggle 1to0 writedata [86] "logic writedata[575:0]" +Toggle 0to1 writedata [86] "logic writedata[575:0]" +Toggle 1to0 writedata [85] "logic writedata[575:0]" +Toggle 0to1 writedata [85] "logic writedata[575:0]" +Toggle 1to0 writedata [84] "logic writedata[575:0]" +Toggle 0to1 writedata [84] "logic writedata[575:0]" +Toggle 1to0 writedata [83] "logic writedata[575:0]" +Toggle 0to1 writedata [83] "logic writedata[575:0]" +Toggle 1to0 writedata [82] "logic writedata[575:0]" +Toggle 0to1 writedata [82] "logic writedata[575:0]" +Toggle 1to0 writedata [81] "logic writedata[575:0]" +Toggle 0to1 writedata [81] "logic writedata[575:0]" +Toggle 1to0 writedata [80] "logic writedata[575:0]" +Toggle 0to1 writedata [80] "logic writedata[575:0]" +Toggle 1to0 writedata [79] "logic writedata[575:0]" +Toggle 0to1 writedata [79] "logic writedata[575:0]" +Toggle 1to0 writedata [78] "logic writedata[575:0]" +Toggle 0to1 writedata [78] "logic writedata[575:0]" +Toggle 1to0 writedata [77] "logic writedata[575:0]" +Toggle 0to1 writedata [77] "logic writedata[575:0]" +Toggle 1to0 writedata [76] "logic writedata[575:0]" +Toggle 0to1 writedata [76] "logic writedata[575:0]" +Toggle 1to0 writedata [75] "logic writedata[575:0]" +Toggle 0to1 writedata [75] "logic writedata[575:0]" +Toggle 1to0 writedata [74] "logic writedata[575:0]" +Toggle 0to1 writedata [74] "logic writedata[575:0]" +Toggle 1to0 writedata [73] "logic writedata[575:0]" +Toggle 0to1 writedata [73] "logic writedata[575:0]" +Toggle 1to0 writedata [72] "logic writedata[575:0]" +Toggle 0to1 writedata [72] "logic writedata[575:0]" +Toggle 1to0 writedata [71] "logic writedata[575:0]" +Toggle 0to1 writedata [71] "logic writedata[575:0]" +Toggle 1to0 writedata [70] "logic writedata[575:0]" +Toggle 0to1 writedata [70] "logic writedata[575:0]" +Toggle 1to0 writedata [69] "logic writedata[575:0]" +Toggle 0to1 writedata [69] "logic writedata[575:0]" +Toggle 1to0 writedata [68] "logic writedata[575:0]" +Toggle 0to1 writedata [68] "logic writedata[575:0]" +Toggle 1to0 writedata [67] "logic writedata[575:0]" +Toggle 0to1 writedata [67] "logic writedata[575:0]" +Toggle 1to0 writedata [66] "logic writedata[575:0]" +Toggle 0to1 writedata [66] "logic writedata[575:0]" +Toggle 1to0 writedata [65] "logic writedata[575:0]" +Toggle 0to1 writedata [65] "logic writedata[575:0]" +Toggle 1to0 writedata [64] "logic writedata[575:0]" +Toggle 0to1 writedata [64] "logic writedata[575:0]" +Toggle 1to0 writedata [63] "logic writedata[575:0]" +Toggle 0to1 writedata [63] "logic writedata[575:0]" +Toggle 1to0 writedata [62] "logic writedata[575:0]" +Toggle 0to1 writedata [62] "logic writedata[575:0]" +Toggle 1to0 writedata [61] "logic writedata[575:0]" +Toggle 0to1 writedata [61] "logic writedata[575:0]" +Toggle 1to0 writedata [60] "logic writedata[575:0]" +Toggle 0to1 writedata [60] "logic writedata[575:0]" +Toggle 1to0 writedata [59] "logic writedata[575:0]" +Toggle 0to1 writedata [59] "logic writedata[575:0]" +Toggle 1to0 writedata [58] "logic writedata[575:0]" +Toggle 0to1 writedata [58] "logic writedata[575:0]" +Toggle 1to0 writedata [57] "logic writedata[575:0]" +Toggle 0to1 writedata [57] "logic writedata[575:0]" +Toggle 1to0 writedata [56] "logic writedata[575:0]" +Toggle 0to1 writedata [56] "logic writedata[575:0]" +Toggle 1to0 writedata [55] "logic writedata[575:0]" +Toggle 0to1 writedata [55] "logic writedata[575:0]" +Toggle 1to0 writedata [54] "logic writedata[575:0]" +Toggle 0to1 writedata [54] "logic writedata[575:0]" +Toggle 1to0 writedata [53] "logic writedata[575:0]" +Toggle 0to1 writedata [53] "logic writedata[575:0]" +Toggle 1to0 writedata [52] "logic writedata[575:0]" +Toggle 0to1 writedata [52] "logic writedata[575:0]" +Toggle 1to0 writedata [51] "logic writedata[575:0]" +Toggle 0to1 writedata [51] "logic writedata[575:0]" +Toggle 1to0 writedata [50] "logic writedata[575:0]" +Toggle 0to1 writedata [50] "logic writedata[575:0]" +Toggle 1to0 writedata [49] "logic writedata[575:0]" +Toggle 0to1 writedata [49] "logic writedata[575:0]" +Toggle 1to0 writedata [48] "logic writedata[575:0]" +Toggle 0to1 writedata [48] "logic writedata[575:0]" +Toggle 1to0 writedata [47] "logic writedata[575:0]" +Toggle 0to1 writedata [47] "logic writedata[575:0]" +Toggle 1to0 writedata [46] "logic writedata[575:0]" +Toggle 0to1 writedata [46] "logic writedata[575:0]" +Toggle 1to0 writedata [45] "logic writedata[575:0]" +Toggle 0to1 writedata [45] "logic writedata[575:0]" +Toggle 1to0 writedata [44] "logic writedata[575:0]" +Toggle 0to1 writedata [44] "logic writedata[575:0]" +Toggle 1to0 writedata [43] "logic writedata[575:0]" +Toggle 0to1 writedata [43] "logic writedata[575:0]" +Toggle 1to0 writedata [42] "logic writedata[575:0]" +Toggle 0to1 writedata [42] "logic writedata[575:0]" +Toggle 1to0 writedata [41] "logic writedata[575:0]" +Toggle 0to1 writedata [41] "logic writedata[575:0]" +Toggle 1to0 writedata [40] "logic writedata[575:0]" +Toggle 0to1 writedata [40] "logic writedata[575:0]" +Toggle 1to0 writedata [39] "logic writedata[575:0]" +Toggle 0to1 writedata [39] "logic writedata[575:0]" +Toggle 1to0 writedata [38] "logic writedata[575:0]" +Toggle 0to1 writedata [38] "logic writedata[575:0]" +Toggle 1to0 writedata [37] "logic writedata[575:0]" +Toggle 0to1 writedata [37] "logic writedata[575:0]" +Toggle 1to0 writedata [36] "logic writedata[575:0]" +Toggle 0to1 writedata [36] "logic writedata[575:0]" +Toggle 1to0 writedata [35] "logic writedata[575:0]" +Toggle 0to1 writedata [35] "logic writedata[575:0]" +Toggle 1to0 writedata [34] "logic writedata[575:0]" +Toggle 0to1 writedata [34] "logic writedata[575:0]" +Toggle 1to0 writedata [33] "logic writedata[575:0]" +Toggle 0to1 writedata [33] "logic writedata[575:0]" +Toggle 1to0 writedata [32] "logic writedata[575:0]" +Toggle 0to1 writedata [32] "logic writedata[575:0]" +Toggle 1to0 writedata [31] "logic writedata[575:0]" +Toggle 0to1 writedata [31] "logic writedata[575:0]" +Toggle 1to0 writedata [30] "logic writedata[575:0]" +Toggle 0to1 writedata [30] "logic writedata[575:0]" +Toggle 1to0 writedata [29] "logic writedata[575:0]" +Toggle 0to1 writedata [29] "logic writedata[575:0]" +Toggle 1to0 writedata [28] "logic writedata[575:0]" +Toggle 0to1 writedata [28] "logic writedata[575:0]" +Toggle 1to0 writedata [27] "logic writedata[575:0]" +Toggle 0to1 writedata [27] "logic writedata[575:0]" +Toggle 1to0 writedata [26] "logic writedata[575:0]" +Toggle 0to1 writedata [26] "logic writedata[575:0]" +Toggle 1to0 writedata [25] "logic writedata[575:0]" +Toggle 0to1 writedata [25] "logic writedata[575:0]" +Toggle 1to0 writedata [24] "logic writedata[575:0]" +Toggle 0to1 writedata [24] "logic writedata[575:0]" +Toggle 1to0 writedata [23] "logic writedata[575:0]" +Toggle 0to1 writedata [23] "logic writedata[575:0]" +Toggle 1to0 writedata [22] "logic writedata[575:0]" +Toggle 0to1 writedata [22] "logic writedata[575:0]" +Toggle 1to0 writedata [21] "logic writedata[575:0]" +Toggle 0to1 writedata [21] "logic writedata[575:0]" +Toggle 1to0 writedata [20] "logic writedata[575:0]" +Toggle 0to1 writedata [20] "logic writedata[575:0]" +Toggle 1to0 writedata [19] "logic writedata[575:0]" +Toggle 0to1 writedata [19] "logic writedata[575:0]" +Toggle 1to0 writedata [18] "logic writedata[575:0]" +Toggle 0to1 writedata [18] "logic writedata[575:0]" +Toggle 1to0 writedata [17] "logic writedata[575:0]" +Toggle 0to1 writedata [17] "logic writedata[575:0]" +Toggle 1to0 writedata [16] "logic writedata[575:0]" +Toggle 0to1 writedata [16] "logic writedata[575:0]" +Toggle 1to0 writedata [15] "logic writedata[575:0]" +Toggle 0to1 writedata [15] "logic writedata[575:0]" +Toggle 1to0 writedata [14] "logic writedata[575:0]" +Toggle 0to1 writedata [14] "logic writedata[575:0]" +Toggle 1to0 writedata [13] "logic writedata[575:0]" +Toggle 0to1 writedata [13] "logic writedata[575:0]" +Toggle 1to0 writedata [12] "logic writedata[575:0]" +Toggle 0to1 writedata [12] "logic writedata[575:0]" +Toggle 1to0 writedata [11] "logic writedata[575:0]" +Toggle 0to1 writedata [11] "logic writedata[575:0]" +Toggle 1to0 writedata [10] "logic writedata[575:0]" +Toggle 0to1 writedata [10] "logic writedata[575:0]" +Toggle 1to0 writedata [9] "logic writedata[575:0]" +Toggle 0to1 writedata [9] "logic writedata[575:0]" +Toggle 1to0 writedata [8] "logic writedata[575:0]" +Toggle 0to1 writedata [8] "logic writedata[575:0]" +Toggle 1to0 writedata [7] "logic writedata[575:0]" +Toggle 0to1 writedata [7] "logic writedata[575:0]" +Toggle 1to0 writedata [6] "logic writedata[575:0]" +Toggle 0to1 writedata [6] "logic writedata[575:0]" +Toggle 1to0 writedata [5] "logic writedata[575:0]" +Toggle 0to1 writedata [5] "logic writedata[575:0]" +Toggle 1to0 writedata [4] "logic writedata[575:0]" +Toggle 0to1 writedata [4] "logic writedata[575:0]" +Toggle 1to0 writedata [3] "logic writedata[575:0]" +Toggle 0to1 writedata [3] "logic writedata[575:0]" +Toggle 1to0 writedata [2] "logic writedata[575:0]" +Toggle 0to1 writedata [2] "logic writedata[575:0]" +Toggle 1to0 writedata [1] "logic writedata[575:0]" +Toggle 0to1 writedata [1] "logic writedata[575:0]" +Toggle 1to0 writedata [0] "logic writedata[575:0]" +Toggle 0to1 writedata [0] "logic writedata[575:0]" +Toggle 1to0 writedata [575] "logic writedata[575:0]" +Toggle 0to1 writedata [575] "logic writedata[575:0]" +Toggle 1to0 readdata [574] "logic readdata[575:0]" +Toggle 0to1 readdata [574] "logic readdata[575:0]" +Toggle 1to0 readdata [573] "logic readdata[575:0]" +Toggle 0to1 readdata [573] "logic readdata[575:0]" +Toggle 1to0 readdata [572] "logic readdata[575:0]" +Toggle 0to1 readdata [572] "logic readdata[575:0]" +Toggle 1to0 readdata [571] "logic readdata[575:0]" +Toggle 0to1 readdata [571] "logic readdata[575:0]" +Toggle 1to0 readdata [570] "logic readdata[575:0]" +Toggle 0to1 readdata [570] "logic readdata[575:0]" +Toggle 1to0 readdata [569] "logic readdata[575:0]" +Toggle 0to1 readdata [569] "logic readdata[575:0]" +Toggle 1to0 readdata [568] "logic readdata[575:0]" +Toggle 0to1 readdata [568] "logic readdata[575:0]" +Toggle 1to0 readdata [567] "logic readdata[575:0]" +Toggle 0to1 readdata [567] "logic readdata[575:0]" +Toggle 1to0 readdata [566] "logic readdata[575:0]" +Toggle 0to1 readdata [566] "logic readdata[575:0]" +Toggle 1to0 readdata [565] "logic readdata[575:0]" +Toggle 0to1 readdata [565] "logic readdata[575:0]" +Toggle 1to0 readdata [564] "logic readdata[575:0]" +Toggle 0to1 readdata [564] "logic readdata[575:0]" +Toggle 1to0 readdata [563] "logic readdata[575:0]" +Toggle 0to1 readdata [563] "logic readdata[575:0]" +Toggle 1to0 readdata [562] "logic readdata[575:0]" +Toggle 0to1 readdata [562] "logic readdata[575:0]" +Toggle 1to0 readdata [561] "logic readdata[575:0]" +Toggle 0to1 readdata [561] "logic readdata[575:0]" +Toggle 1to0 readdata [560] "logic readdata[575:0]" +Toggle 0to1 readdata [560] "logic readdata[575:0]" +Toggle 1to0 readdata [559] "logic readdata[575:0]" +Toggle 0to1 readdata [559] "logic readdata[575:0]" +Toggle 1to0 readdata [558] "logic readdata[575:0]" +Toggle 0to1 readdata [558] "logic readdata[575:0]" +Toggle 1to0 readdata [557] "logic readdata[575:0]" +Toggle 0to1 readdata [557] "logic readdata[575:0]" +Toggle 1to0 readdata [556] "logic readdata[575:0]" +Toggle 0to1 readdata [556] "logic readdata[575:0]" +Toggle 1to0 readdata [555] "logic readdata[575:0]" +Toggle 0to1 readdata [555] "logic readdata[575:0]" +Toggle 1to0 readdata [554] "logic readdata[575:0]" +Toggle 0to1 readdata [554] "logic readdata[575:0]" +Toggle 1to0 readdata [553] "logic readdata[575:0]" +Toggle 0to1 readdata [553] "logic readdata[575:0]" +Toggle 1to0 readdata [552] "logic readdata[575:0]" +Toggle 0to1 readdata [552] "logic readdata[575:0]" +Toggle 1to0 readdata [551] "logic readdata[575:0]" +Toggle 0to1 readdata [551] "logic readdata[575:0]" +Toggle 1to0 readdata [550] "logic readdata[575:0]" +Toggle 0to1 readdata [550] "logic readdata[575:0]" +Toggle 1to0 readdata [549] "logic readdata[575:0]" +Toggle 0to1 readdata [549] "logic readdata[575:0]" +Toggle 1to0 readdata [548] "logic readdata[575:0]" +Toggle 0to1 readdata [548] "logic readdata[575:0]" +Toggle 1to0 readdata [547] "logic readdata[575:0]" +Toggle 0to1 readdata [547] "logic readdata[575:0]" +Toggle 1to0 readdata [546] "logic readdata[575:0]" +Toggle 0to1 readdata [546] "logic readdata[575:0]" +Toggle 1to0 readdata [545] "logic readdata[575:0]" +Toggle 0to1 readdata [545] "logic readdata[575:0]" +Toggle 1to0 readdata [544] "logic readdata[575:0]" +Toggle 0to1 readdata [544] "logic readdata[575:0]" +Toggle 1to0 readdata [543] "logic readdata[575:0]" +Toggle 0to1 readdata [543] "logic readdata[575:0]" +Toggle 1to0 readdata [542] "logic readdata[575:0]" +Toggle 0to1 readdata [542] "logic readdata[575:0]" +Toggle 1to0 readdata [541] "logic readdata[575:0]" +Toggle 0to1 readdata [541] "logic readdata[575:0]" +Toggle 1to0 readdata [540] "logic readdata[575:0]" +Toggle 0to1 readdata [540] "logic readdata[575:0]" +Toggle 1to0 readdata [539] "logic readdata[575:0]" +Toggle 0to1 readdata [539] "logic readdata[575:0]" +Toggle 1to0 readdata [538] "logic readdata[575:0]" +Toggle 0to1 readdata [538] "logic readdata[575:0]" +Toggle 1to0 readdata [537] "logic readdata[575:0]" +Toggle 0to1 readdata [537] "logic readdata[575:0]" +Toggle 1to0 readdata [536] "logic readdata[575:0]" +Toggle 0to1 readdata [536] "logic readdata[575:0]" +Toggle 1to0 readdata [535] "logic readdata[575:0]" +Toggle 0to1 readdata [535] "logic readdata[575:0]" +Toggle 1to0 readdata [534] "logic readdata[575:0]" +Toggle 0to1 readdata [534] "logic readdata[575:0]" +Toggle 1to0 readdata [533] "logic readdata[575:0]" +Toggle 0to1 readdata [533] "logic readdata[575:0]" +Toggle 1to0 readdata [532] "logic readdata[575:0]" +Toggle 0to1 readdata [532] "logic readdata[575:0]" +Toggle 1to0 readdata [531] "logic readdata[575:0]" +Toggle 0to1 readdata [531] "logic readdata[575:0]" +Toggle 1to0 readdata [530] "logic readdata[575:0]" +Toggle 0to1 readdata [530] "logic readdata[575:0]" +Toggle 1to0 readdata [529] "logic readdata[575:0]" +Toggle 0to1 readdata [529] "logic readdata[575:0]" +Toggle 1to0 readdata [528] "logic readdata[575:0]" +Toggle 0to1 readdata [528] "logic readdata[575:0]" +Toggle 1to0 readdata [527] "logic readdata[575:0]" +Toggle 0to1 readdata [527] "logic readdata[575:0]" +Toggle 1to0 readdata [526] "logic readdata[575:0]" +Toggle 0to1 readdata [526] "logic readdata[575:0]" +Toggle 1to0 readdata [525] "logic readdata[575:0]" +Toggle 0to1 readdata [525] "logic readdata[575:0]" +Toggle 1to0 readdata [524] "logic readdata[575:0]" +Toggle 0to1 readdata [524] "logic readdata[575:0]" +Toggle 1to0 readdata [523] "logic readdata[575:0]" +Toggle 0to1 readdata [523] "logic readdata[575:0]" +Toggle 1to0 readdata [522] "logic readdata[575:0]" +Toggle 0to1 readdata [522] "logic readdata[575:0]" +Toggle 1to0 readdata [521] "logic readdata[575:0]" +Toggle 0to1 readdata [521] "logic readdata[575:0]" +Toggle 1to0 readdata [520] "logic readdata[575:0]" +Toggle 0to1 readdata [520] "logic readdata[575:0]" +Toggle 1to0 readdata [519] "logic readdata[575:0]" +Toggle 0to1 readdata [519] "logic readdata[575:0]" +Toggle 1to0 readdata [518] "logic readdata[575:0]" +Toggle 0to1 readdata [518] "logic readdata[575:0]" +Toggle 1to0 readdata [517] "logic readdata[575:0]" +Toggle 0to1 readdata [517] "logic readdata[575:0]" +Toggle 1to0 readdata [516] "logic readdata[575:0]" +Toggle 0to1 readdata [516] "logic readdata[575:0]" +Toggle 1to0 readdata [515] "logic readdata[575:0]" +Toggle 0to1 readdata [515] "logic readdata[575:0]" +Toggle 1to0 readdata [514] "logic readdata[575:0]" +Toggle 0to1 readdata [514] "logic readdata[575:0]" +Toggle 1to0 readdata [513] "logic readdata[575:0]" +Toggle 0to1 readdata [513] "logic readdata[575:0]" +Toggle 1to0 readdata [512] "logic readdata[575:0]" +Toggle 0to1 readdata [512] "logic readdata[575:0]" +Toggle 1to0 readdata [575] "logic readdata[575:0]" +Toggle 0to1 readdata [575] "logic readdata[575:0]" +Toggle 1to0 rst_n "logic rst_n" +Toggle 0to1 rst_n "logic rst_n" +Toggle 1to0 clk "logic clk" +Toggle 0to1 clk "logic clk" +Toggle 1to0 ecc_interrupt "logic ecc_interrupt" +Toggle 0to1 ecc_interrupt "logic ecc_interrupt" +Toggle 1to0 byteenable [70] "logic byteenable[71:0]" +Toggle 0to1 byteenable [70] "logic byteenable[71:0]" +Toggle 1to0 byteenable [69] "logic byteenable[71:0]" +Toggle 0to1 byteenable [69] "logic byteenable[71:0]" +Toggle 1to0 byteenable [68] "logic byteenable[71:0]" +Toggle 0to1 byteenable [68] "logic byteenable[71:0]" +Toggle 1to0 byteenable [67] "logic byteenable[71:0]" +Toggle 0to1 byteenable [67] "logic byteenable[71:0]" +Toggle 1to0 byteenable [66] "logic byteenable[71:0]" +Toggle 0to1 byteenable [66] "logic byteenable[71:0]" +Toggle 1to0 byteenable [65] "logic byteenable[71:0]" +Toggle 0to1 byteenable [65] "logic byteenable[71:0]" +Toggle 1to0 byteenable [64] "logic byteenable[71:0]" +Toggle 0to1 byteenable [64] "logic byteenable[71:0]" +Toggle 1to0 byteenable [63] "logic byteenable[71:0]" +Toggle 0to1 byteenable [63] "logic byteenable[71:0]" +Toggle 1to0 byteenable [62] "logic byteenable[71:0]" +Toggle 0to1 byteenable [62] "logic byteenable[71:0]" +Toggle 1to0 byteenable [61] "logic byteenable[71:0]" +Toggle 0to1 byteenable [61] "logic byteenable[71:0]" +Toggle 1to0 byteenable [60] "logic byteenable[71:0]" +Toggle 0to1 byteenable [60] "logic byteenable[71:0]" +Toggle 1to0 byteenable [59] "logic byteenable[71:0]" +Toggle 0to1 byteenable [59] "logic byteenable[71:0]" +Toggle 1to0 byteenable [58] "logic byteenable[71:0]" +Toggle 0to1 byteenable [58] "logic byteenable[71:0]" +Toggle 1to0 byteenable [57] "logic byteenable[71:0]" +Toggle 0to1 byteenable [57] "logic byteenable[71:0]" +Toggle 1to0 byteenable [56] "logic byteenable[71:0]" +Toggle 0to1 byteenable [56] "logic byteenable[71:0]" +Toggle 1to0 byteenable [55] "logic byteenable[71:0]" +Toggle 0to1 byteenable [55] "logic byteenable[71:0]" +Toggle 1to0 byteenable [54] "logic byteenable[71:0]" +Toggle 0to1 byteenable [54] "logic byteenable[71:0]" +Toggle 1to0 byteenable [53] "logic byteenable[71:0]" +Toggle 0to1 byteenable [53] "logic byteenable[71:0]" +Toggle 1to0 byteenable [52] "logic byteenable[71:0]" +Toggle 0to1 byteenable [52] "logic byteenable[71:0]" +Toggle 1to0 byteenable [51] "logic byteenable[71:0]" +Toggle 0to1 byteenable [51] "logic byteenable[71:0]" +Toggle 1to0 byteenable [50] "logic byteenable[71:0]" +Toggle 0to1 byteenable [50] "logic byteenable[71:0]" +Toggle 1to0 byteenable [49] "logic byteenable[71:0]" +Toggle 0to1 byteenable [49] "logic byteenable[71:0]" +Toggle 1to0 byteenable [48] "logic byteenable[71:0]" +Toggle 0to1 byteenable [48] "logic byteenable[71:0]" +Toggle 1to0 byteenable [47] "logic byteenable[71:0]" +Toggle 0to1 byteenable [47] "logic byteenable[71:0]" +Toggle 1to0 byteenable [46] "logic byteenable[71:0]" +Toggle 0to1 byteenable [46] "logic byteenable[71:0]" +Toggle 1to0 byteenable [45] "logic byteenable[71:0]" +Toggle 0to1 byteenable [45] "logic byteenable[71:0]" +Toggle 1to0 byteenable [44] "logic byteenable[71:0]" +Toggle 0to1 byteenable [44] "logic byteenable[71:0]" +Toggle 1to0 byteenable [43] "logic byteenable[71:0]" +Toggle 0to1 byteenable [43] "logic byteenable[71:0]" +Toggle 1to0 byteenable [42] "logic byteenable[71:0]" +Toggle 0to1 byteenable [42] "logic byteenable[71:0]" +Toggle 1to0 byteenable [41] "logic byteenable[71:0]" +Toggle 0to1 byteenable [41] "logic byteenable[71:0]" +Toggle 1to0 byteenable [40] "logic byteenable[71:0]" +Toggle 0to1 byteenable [40] "logic byteenable[71:0]" +Toggle 1to0 byteenable [39] "logic byteenable[71:0]" +Toggle 0to1 byteenable [39] "logic byteenable[71:0]" +Toggle 1to0 byteenable [38] "logic byteenable[71:0]" +Toggle 0to1 byteenable [38] "logic byteenable[71:0]" +Toggle 1to0 byteenable [37] "logic byteenable[71:0]" +Toggle 0to1 byteenable [37] "logic byteenable[71:0]" +Toggle 1to0 byteenable [36] "logic byteenable[71:0]" +Toggle 0to1 byteenable [36] "logic byteenable[71:0]" +Toggle 1to0 byteenable [35] "logic byteenable[71:0]" +Toggle 0to1 byteenable [35] "logic byteenable[71:0]" +Toggle 1to0 byteenable [34] "logic byteenable[71:0]" +Toggle 0to1 byteenable [34] "logic byteenable[71:0]" +Toggle 1to0 byteenable [33] "logic byteenable[71:0]" +Toggle 0to1 byteenable [33] "logic byteenable[71:0]" +Toggle 1to0 byteenable [32] "logic byteenable[71:0]" +Toggle 0to1 byteenable [32] "logic byteenable[71:0]" +Toggle 1to0 byteenable [31] "logic byteenable[71:0]" +Toggle 0to1 byteenable [31] "logic byteenable[71:0]" +Toggle 1to0 byteenable [30] "logic byteenable[71:0]" +Toggle 0to1 byteenable [30] "logic byteenable[71:0]" +Toggle 1to0 byteenable [29] "logic byteenable[71:0]" +Toggle 0to1 byteenable [29] "logic byteenable[71:0]" +Toggle 1to0 byteenable [28] "logic byteenable[71:0]" +Toggle 0to1 byteenable [28] "logic byteenable[71:0]" +Toggle 1to0 byteenable [27] "logic byteenable[71:0]" +Toggle 0to1 byteenable [27] "logic byteenable[71:0]" +Toggle 1to0 byteenable [26] "logic byteenable[71:0]" +Toggle 0to1 byteenable [26] "logic byteenable[71:0]" +Toggle 1to0 byteenable [25] "logic byteenable[71:0]" +Toggle 0to1 byteenable [25] "logic byteenable[71:0]" +Toggle 1to0 byteenable [24] "logic byteenable[71:0]" +Toggle 0to1 byteenable [24] "logic byteenable[71:0]" +Toggle 1to0 byteenable [23] "logic byteenable[71:0]" +Toggle 0to1 byteenable [23] "logic byteenable[71:0]" +Toggle 1to0 byteenable [22] "logic byteenable[71:0]" +Toggle 0to1 byteenable [22] "logic byteenable[71:0]" +Toggle 1to0 byteenable [21] "logic byteenable[71:0]" +Toggle 0to1 byteenable [21] "logic byteenable[71:0]" +Toggle 1to0 byteenable [20] "logic byteenable[71:0]" +Toggle 0to1 byteenable [20] "logic byteenable[71:0]" +Toggle 1to0 byteenable [19] "logic byteenable[71:0]" +Toggle 0to1 byteenable [19] "logic byteenable[71:0]" +Toggle 1to0 byteenable [18] "logic byteenable[71:0]" +Toggle 0to1 byteenable [18] "logic byteenable[71:0]" +Toggle 1to0 byteenable [17] "logic byteenable[71:0]" +Toggle 0to1 byteenable [17] "logic byteenable[71:0]" +Toggle 1to0 byteenable [16] "logic byteenable[71:0]" +Toggle 0to1 byteenable [16] "logic byteenable[71:0]" +Toggle 1to0 byteenable [15] "logic byteenable[71:0]" +Toggle 0to1 byteenable [15] "logic byteenable[71:0]" +Toggle 1to0 byteenable [14] "logic byteenable[71:0]" +Toggle 0to1 byteenable [14] "logic byteenable[71:0]" +Toggle 1to0 byteenable [13] "logic byteenable[71:0]" +Toggle 0to1 byteenable [13] "logic byteenable[71:0]" +Toggle 1to0 byteenable [12] "logic byteenable[71:0]" +Toggle 0to1 byteenable [12] "logic byteenable[71:0]" +Toggle 1to0 byteenable [11] "logic byteenable[71:0]" +Toggle 0to1 byteenable [11] "logic byteenable[71:0]" +Toggle 1to0 byteenable [10] "logic byteenable[71:0]" +Toggle 0to1 byteenable [10] "logic byteenable[71:0]" +Toggle 1to0 byteenable [9] "logic byteenable[71:0]" +Toggle 0to1 byteenable [9] "logic byteenable[71:0]" +Toggle 1to0 byteenable [8] "logic byteenable[71:0]" +Toggle 0to1 byteenable [8] "logic byteenable[71:0]" +Toggle 1to0 byteenable [7] "logic byteenable[71:0]" +Toggle 0to1 byteenable [7] "logic byteenable[71:0]" +Toggle 1to0 byteenable [6] "logic byteenable[71:0]" +Toggle 0to1 byteenable [6] "logic byteenable[71:0]" +Toggle 1to0 byteenable [5] "logic byteenable[71:0]" +Toggle 0to1 byteenable [5] "logic byteenable[71:0]" +Toggle 1to0 byteenable [4] "logic byteenable[71:0]" +Toggle 0to1 byteenable [4] "logic byteenable[71:0]" +Toggle 1to0 byteenable [3] "logic byteenable[71:0]" +Toggle 0to1 byteenable [3] "logic byteenable[71:0]" +Toggle 1to0 byteenable [2] "logic byteenable[71:0]" +Toggle 0to1 byteenable [2] "logic byteenable[71:0]" +Toggle 1to0 byteenable [1] "logic byteenable[71:0]" +Toggle 0to1 byteenable [1] "logic byteenable[71:0]" +Toggle 1to0 byteenable [0] "logic byteenable[71:0]" +Toggle 0to1 byteenable [0] "logic byteenable[71:0]" +Toggle 1to0 byteenable [71] "logic byteenable[71:0]" +Toggle 0to1 byteenable [71] "logic byteenable[71:0]" +Toggle 1to0 burstcount [5] "logic burstcount[6:0]" +Toggle 0to1 burstcount [5] "logic burstcount[6:0]" +Toggle 1to0 burstcount [4] "logic burstcount[6:0]" +Toggle 0to1 burstcount [4] "logic burstcount[6:0]" +Toggle 1to0 burstcount [3] "logic burstcount[6:0]" +Toggle 0to1 burstcount [3] "logic burstcount[6:0]" +Toggle 1to0 burstcount [2] "logic burstcount[6:0]" +Toggle 1to0 burstcount [1] "logic burstcount[6:0]" +Toggle 1to0 burstcount [0] "logic burstcount[6:0]" +Toggle 1to0 burstcount [6] "logic burstcount[6:0]" +Toggle 0to1 burstcount [6] "logic burstcount[6:0]" +Toggle 1to0 address [26] "logic address[26:0]" +Toggle 0to1 address [26] "logic address[26:0]" +Toggle 1to0 address [25] "logic address[26:0]" +Toggle 0to1 address [25] "logic address[26:0]" +Toggle 1to0 address [24] "logic address[26:0]" +Toggle 0to1 address [24] "logic address[26:0]" +Toggle 1to0 address [23] "logic address[26:0]" +Toggle 0to1 address [23] "logic address[26:0]" +Toggle 1to0 address [22] "logic address[26:0]" +Toggle 0to1 address [22] "logic address[26:0]" +Toggle 1to0 address [21] "logic address[26:0]" +Toggle 0to1 address [21] "logic address[26:0]" +Toggle 1to0 address [20] "logic address[26:0]" +Toggle 0to1 address [20] "logic address[26:0]" +Toggle 1to0 address [19] "logic address[26:0]" +Toggle 0to1 address [19] "logic address[26:0]" +Toggle 1to0 address [18] "logic address[26:0]" +Toggle 0to1 address [18] "logic address[26:0]" +Toggle 1to0 address [17] "logic address[26:0]" +Toggle 0to1 address [17] "logic address[26:0]" +Toggle 1to0 address [16] "logic address[26:0]" +Toggle 0to1 address [16] "logic address[26:0]" +Toggle 1to0 address [15] "logic address[26:0]" +Toggle 0to1 address [15] "logic address[26:0]" +Toggle 1to0 address [14] "logic address[26:0]" +Toggle 0to1 address [14] "logic address[26:0]" +Toggle 1to0 address [13] "logic address[26:0]" +Toggle 0to1 address [13] "logic address[26:0]" +Toggle 1to0 address [12] "logic address[26:0]" +Toggle 0to1 address [12] "logic address[26:0]" +Toggle 1to0 address [11] "logic address[26:0]" +Toggle 0to1 address [11] "logic address[26:0]" +Toggle 1to0 address [0] "logic address[26:0]" +Toggle 0to1 address [0] "logic address[26:0]" +CHECKSUM: "2948434777 858782335" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.ext_mem_if_lb +Toggle 1to0 writeresponsevalid "logic writeresponsevalid" +Toggle 0to1 writeresponsevalid "logic writeresponsevalid" +Toggle 1to0 ecc_interrupt "logic ecc_interrupt" +Toggle 0to1 ecc_interrupt "logic ecc_interrupt" +Toggle 1to0 clk "logic clk" +Toggle 0to1 clk "logic clk" +Toggle 1to0 burstcount [5] "logic burstcount[6:0]" +Toggle 0to1 burstcount [5] "logic burstcount[6:0]" +Toggle 1to0 burstcount [4] "logic burstcount[6:0]" +Toggle 0to1 burstcount [4] "logic burstcount[6:0]" +Toggle 1to0 burstcount [3] "logic burstcount[6:0]" +Toggle 0to1 burstcount [3] "logic burstcount[6:0]" +Toggle 1to0 burstcount [2] "logic burstcount[6:0]" +Toggle 0to1 burstcount [2] "logic burstcount[6:0]" +Toggle 1to0 burstcount [1] "logic burstcount[6:0]" +Toggle 0to1 burstcount [1] "logic burstcount[6:0]" +Toggle 1to0 burstcount [0] "logic burstcount[6:0]" +Toggle 0to1 burstcount [0] "logic burstcount[6:0]" +Toggle 1to0 burstcount [6] "logic burstcount[6:0]" +Toggle 0to1 burstcount [6] "logic burstcount[6:0]" +Toggle 1to0 byteenable [70] "logic byteenable[71:0]" +Toggle 0to1 byteenable [70] "logic byteenable[71:0]" +Toggle 1to0 byteenable [69] "logic byteenable[71:0]" +Toggle 0to1 byteenable [69] "logic byteenable[71:0]" +Toggle 1to0 byteenable [68] "logic byteenable[71:0]" +Toggle 0to1 byteenable [68] "logic byteenable[71:0]" +Toggle 1to0 byteenable [67] "logic byteenable[71:0]" +Toggle 0to1 byteenable [67] "logic byteenable[71:0]" +Toggle 1to0 byteenable [66] "logic byteenable[71:0]" +Toggle 0to1 byteenable [66] "logic byteenable[71:0]" +Toggle 1to0 byteenable [65] "logic byteenable[71:0]" +Toggle 0to1 byteenable [65] "logic byteenable[71:0]" +Toggle 1to0 byteenable [64] "logic byteenable[71:0]" +Toggle 0to1 byteenable [64] "logic byteenable[71:0]" +Toggle 1to0 byteenable [63] "logic byteenable[71:0]" +Toggle 0to1 byteenable [63] "logic byteenable[71:0]" +Toggle 1to0 byteenable [62] "logic byteenable[71:0]" +Toggle 0to1 byteenable [62] "logic byteenable[71:0]" +Toggle 1to0 byteenable [61] "logic byteenable[71:0]" +Toggle 0to1 byteenable [61] "logic byteenable[71:0]" +Toggle 1to0 byteenable [60] "logic byteenable[71:0]" +Toggle 0to1 byteenable [60] "logic byteenable[71:0]" +Toggle 1to0 byteenable [59] "logic byteenable[71:0]" +Toggle 0to1 byteenable [59] "logic byteenable[71:0]" +Toggle 1to0 byteenable [58] "logic byteenable[71:0]" +Toggle 0to1 byteenable [58] "logic byteenable[71:0]" +Toggle 1to0 byteenable [57] "logic byteenable[71:0]" +Toggle 0to1 byteenable [57] "logic byteenable[71:0]" +Toggle 1to0 byteenable [56] "logic byteenable[71:0]" +Toggle 0to1 byteenable [56] "logic byteenable[71:0]" +Toggle 1to0 byteenable [55] "logic byteenable[71:0]" +Toggle 0to1 byteenable [55] "logic byteenable[71:0]" +Toggle 1to0 byteenable [54] "logic byteenable[71:0]" +Toggle 0to1 byteenable [54] "logic byteenable[71:0]" +Toggle 1to0 byteenable [53] "logic byteenable[71:0]" +Toggle 0to1 byteenable [53] "logic byteenable[71:0]" +Toggle 1to0 byteenable [52] "logic byteenable[71:0]" +Toggle 0to1 byteenable [52] "logic byteenable[71:0]" +Toggle 1to0 byteenable [51] "logic byteenable[71:0]" +Toggle 0to1 byteenable [51] "logic byteenable[71:0]" +Toggle 1to0 byteenable [50] "logic byteenable[71:0]" +Toggle 0to1 byteenable [50] "logic byteenable[71:0]" +Toggle 1to0 byteenable [49] "logic byteenable[71:0]" +Toggle 0to1 byteenable [49] "logic byteenable[71:0]" +Toggle 1to0 byteenable [48] "logic byteenable[71:0]" +Toggle 0to1 byteenable [48] "logic byteenable[71:0]" +Toggle 1to0 byteenable [47] "logic byteenable[71:0]" +Toggle 0to1 byteenable [47] "logic byteenable[71:0]" +Toggle 1to0 byteenable [46] "logic byteenable[71:0]" +Toggle 0to1 byteenable [46] "logic byteenable[71:0]" +Toggle 1to0 byteenable [45] "logic byteenable[71:0]" +Toggle 0to1 byteenable [45] "logic byteenable[71:0]" +Toggle 1to0 byteenable [44] "logic byteenable[71:0]" +Toggle 0to1 byteenable [44] "logic byteenable[71:0]" +Toggle 1to0 byteenable [43] "logic byteenable[71:0]" +Toggle 0to1 byteenable [43] "logic byteenable[71:0]" +Toggle 1to0 byteenable [42] "logic byteenable[71:0]" +Toggle 0to1 byteenable [42] "logic byteenable[71:0]" +Toggle 1to0 byteenable [41] "logic byteenable[71:0]" +Toggle 0to1 byteenable [41] "logic byteenable[71:0]" +Toggle 1to0 byteenable [40] "logic byteenable[71:0]" +Toggle 0to1 byteenable [40] "logic byteenable[71:0]" +Toggle 1to0 byteenable [39] "logic byteenable[71:0]" +Toggle 0to1 byteenable [39] "logic byteenable[71:0]" +Toggle 1to0 byteenable [38] "logic byteenable[71:0]" +Toggle 0to1 byteenable [38] "logic byteenable[71:0]" +Toggle 1to0 byteenable [37] "logic byteenable[71:0]" +Toggle 0to1 byteenable [37] "logic byteenable[71:0]" +Toggle 1to0 byteenable [36] "logic byteenable[71:0]" +Toggle 0to1 byteenable [36] "logic byteenable[71:0]" +Toggle 1to0 byteenable [35] "logic byteenable[71:0]" +Toggle 0to1 byteenable [35] "logic byteenable[71:0]" +Toggle 1to0 byteenable [34] "logic byteenable[71:0]" +Toggle 0to1 byteenable [34] "logic byteenable[71:0]" +Toggle 1to0 byteenable [33] "logic byteenable[71:0]" +Toggle 0to1 byteenable [33] "logic byteenable[71:0]" +Toggle 1to0 byteenable [32] "logic byteenable[71:0]" +Toggle 0to1 byteenable [32] "logic byteenable[71:0]" +Toggle 1to0 byteenable [31] "logic byteenable[71:0]" +Toggle 0to1 byteenable [31] "logic byteenable[71:0]" +Toggle 1to0 byteenable [30] "logic byteenable[71:0]" +Toggle 0to1 byteenable [30] "logic byteenable[71:0]" +Toggle 1to0 byteenable [29] "logic byteenable[71:0]" +Toggle 0to1 byteenable [29] "logic byteenable[71:0]" +Toggle 1to0 byteenable [28] "logic byteenable[71:0]" +Toggle 0to1 byteenable [28] "logic byteenable[71:0]" +Toggle 1to0 byteenable [27] "logic byteenable[71:0]" +Toggle 0to1 byteenable [27] "logic byteenable[71:0]" +Toggle 1to0 byteenable [26] "logic byteenable[71:0]" +Toggle 0to1 byteenable [26] "logic byteenable[71:0]" +Toggle 1to0 byteenable [25] "logic byteenable[71:0]" +Toggle 0to1 byteenable [25] "logic byteenable[71:0]" +Toggle 1to0 byteenable [24] "logic byteenable[71:0]" +Toggle 0to1 byteenable [24] "logic byteenable[71:0]" +Toggle 1to0 byteenable [23] "logic byteenable[71:0]" +Toggle 0to1 byteenable [23] "logic byteenable[71:0]" +Toggle 1to0 byteenable [22] "logic byteenable[71:0]" +Toggle 0to1 byteenable [22] "logic byteenable[71:0]" +Toggle 1to0 byteenable [21] "logic byteenable[71:0]" +Toggle 0to1 byteenable [21] "logic byteenable[71:0]" +Toggle 1to0 byteenable [20] "logic byteenable[71:0]" +Toggle 0to1 byteenable [20] "logic byteenable[71:0]" +Toggle 1to0 byteenable [19] "logic byteenable[71:0]" +Toggle 0to1 byteenable [19] "logic byteenable[71:0]" +Toggle 1to0 byteenable [18] "logic byteenable[71:0]" +Toggle 0to1 byteenable [18] "logic byteenable[71:0]" +Toggle 1to0 byteenable [17] "logic byteenable[71:0]" +Toggle 0to1 byteenable [17] "logic byteenable[71:0]" +Toggle 1to0 byteenable [16] "logic byteenable[71:0]" +Toggle 0to1 byteenable [16] "logic byteenable[71:0]" +Toggle 1to0 byteenable [15] "logic byteenable[71:0]" +Toggle 0to1 byteenable [15] "logic byteenable[71:0]" +Toggle 1to0 byteenable [14] "logic byteenable[71:0]" +Toggle 0to1 byteenable [14] "logic byteenable[71:0]" +Toggle 1to0 byteenable [13] "logic byteenable[71:0]" +Toggle 0to1 byteenable [13] "logic byteenable[71:0]" +Toggle 1to0 byteenable [12] "logic byteenable[71:0]" +Toggle 0to1 byteenable [12] "logic byteenable[71:0]" +Toggle 1to0 byteenable [11] "logic byteenable[71:0]" +Toggle 0to1 byteenable [11] "logic byteenable[71:0]" +Toggle 1to0 byteenable [10] "logic byteenable[71:0]" +Toggle 0to1 byteenable [10] "logic byteenable[71:0]" +Toggle 1to0 byteenable [9] "logic byteenable[71:0]" +Toggle 0to1 byteenable [9] "logic byteenable[71:0]" +Toggle 1to0 byteenable [8] "logic byteenable[71:0]" +Toggle 0to1 byteenable [8] "logic byteenable[71:0]" +Toggle 1to0 byteenable [7] "logic byteenable[71:0]" +Toggle 0to1 byteenable [7] "logic byteenable[71:0]" +Toggle 1to0 byteenable [6] "logic byteenable[71:0]" +Toggle 0to1 byteenable [6] "logic byteenable[71:0]" +Toggle 1to0 byteenable [5] "logic byteenable[71:0]" +Toggle 0to1 byteenable [5] "logic byteenable[71:0]" +Toggle 1to0 byteenable [4] "logic byteenable[71:0]" +Toggle 0to1 byteenable [4] "logic byteenable[71:0]" +Toggle 1to0 byteenable [3] "logic byteenable[71:0]" +Toggle 0to1 byteenable [3] "logic byteenable[71:0]" +Toggle 1to0 byteenable [2] "logic byteenable[71:0]" +Toggle 0to1 byteenable [2] "logic byteenable[71:0]" +Toggle 1to0 byteenable [1] "logic byteenable[71:0]" +Toggle 0to1 byteenable [1] "logic byteenable[71:0]" +Toggle 1to0 byteenable [0] "logic byteenable[71:0]" +Toggle 0to1 byteenable [0] "logic byteenable[71:0]" +Toggle 1to0 byteenable [71] "logic byteenable[71:0]" +Toggle 0to1 byteenable [71] "logic byteenable[71:0]" +Toggle 1to0 address [25] "logic address[26:0]" +Toggle 0to1 address [25] "logic address[26:0]" +Toggle 1to0 address [24] "logic address[26:0]" +Toggle 0to1 address [24] "logic address[26:0]" +Toggle 1to0 address [23] "logic address[26:0]" +Toggle 0to1 address [23] "logic address[26:0]" +Toggle 1to0 address [22] "logic address[26:0]" +Toggle 0to1 address [22] "logic address[26:0]" +Toggle 1to0 address [21] "logic address[26:0]" +Toggle 0to1 address [21] "logic address[26:0]" +Toggle 1to0 address [20] "logic address[26:0]" +Toggle 0to1 address [20] "logic address[26:0]" +Toggle 1to0 address [19] "logic address[26:0]" +Toggle 0to1 address [19] "logic address[26:0]" +Toggle 1to0 address [18] "logic address[26:0]" +Toggle 0to1 address [18] "logic address[26:0]" +Toggle 1to0 address [17] "logic address[26:0]" +Toggle 0to1 address [17] "logic address[26:0]" +Toggle 1to0 address [16] "logic address[26:0]" +Toggle 0to1 address [16] "logic address[26:0]" +Toggle 1to0 address [15] "logic address[26:0]" +Toggle 0to1 address [15] "logic address[26:0]" +Toggle 1to0 address [14] "logic address[26:0]" +Toggle 0to1 address [14] "logic address[26:0]" +Toggle 1to0 address [13] "logic address[26:0]" +Toggle 0to1 address [13] "logic address[26:0]" +Toggle 1to0 address [12] "logic address[26:0]" +Toggle 0to1 address [12] "logic address[26:0]" +Toggle 1to0 address [11] "logic address[26:0]" +Toggle 0to1 address [11] "logic address[26:0]" +Toggle 1to0 address [26] "logic address[26:0]" +Toggle 0to1 address [26] "logic address[26:0]" +Toggle 1to0 readdata [574] "logic readdata[575:0]" +Toggle 0to1 readdata [574] "logic readdata[575:0]" +Toggle 1to0 readdata [573] "logic readdata[575:0]" +Toggle 0to1 readdata [573] "logic readdata[575:0]" +Toggle 1to0 readdata [572] "logic readdata[575:0]" +Toggle 0to1 readdata [572] "logic readdata[575:0]" +Toggle 1to0 readdata [571] "logic readdata[575:0]" +Toggle 0to1 readdata [571] "logic readdata[575:0]" +Toggle 1to0 readdata [570] "logic readdata[575:0]" +Toggle 0to1 readdata [570] "logic readdata[575:0]" +Toggle 1to0 readdata [569] "logic readdata[575:0]" +Toggle 0to1 readdata [569] "logic readdata[575:0]" +Toggle 1to0 readdata [568] "logic readdata[575:0]" +Toggle 0to1 readdata [568] "logic readdata[575:0]" +Toggle 1to0 readdata [567] "logic readdata[575:0]" +Toggle 0to1 readdata [567] "logic readdata[575:0]" +Toggle 1to0 readdata [566] "logic readdata[575:0]" +Toggle 0to1 readdata [566] "logic readdata[575:0]" +Toggle 1to0 readdata [565] "logic readdata[575:0]" +Toggle 0to1 readdata [565] "logic readdata[575:0]" +Toggle 1to0 readdata [564] "logic readdata[575:0]" +Toggle 0to1 readdata [564] "logic readdata[575:0]" +Toggle 1to0 readdata [563] "logic readdata[575:0]" +Toggle 0to1 readdata [563] "logic readdata[575:0]" +Toggle 1to0 readdata [562] "logic readdata[575:0]" +Toggle 0to1 readdata [562] "logic readdata[575:0]" +Toggle 1to0 readdata [561] "logic readdata[575:0]" +Toggle 0to1 readdata [561] "logic readdata[575:0]" +Toggle 1to0 readdata [560] "logic readdata[575:0]" +Toggle 0to1 readdata [560] "logic readdata[575:0]" +Toggle 1to0 readdata [559] "logic readdata[575:0]" +Toggle 0to1 readdata [559] "logic readdata[575:0]" +Toggle 1to0 readdata [558] "logic readdata[575:0]" +Toggle 0to1 readdata [558] "logic readdata[575:0]" +Toggle 1to0 readdata [557] "logic readdata[575:0]" +Toggle 0to1 readdata [557] "logic readdata[575:0]" +Toggle 1to0 readdata [556] "logic readdata[575:0]" +Toggle 0to1 readdata [556] "logic readdata[575:0]" +Toggle 1to0 readdata [555] "logic readdata[575:0]" +Toggle 0to1 readdata [555] "logic readdata[575:0]" +Toggle 1to0 readdata [554] "logic readdata[575:0]" +Toggle 0to1 readdata [554] "logic readdata[575:0]" +Toggle 1to0 readdata [553] "logic readdata[575:0]" +Toggle 0to1 readdata [553] "logic readdata[575:0]" +Toggle 1to0 readdata [552] "logic readdata[575:0]" +Toggle 0to1 readdata [552] "logic readdata[575:0]" +Toggle 1to0 readdata [551] "logic readdata[575:0]" +Toggle 0to1 readdata [551] "logic readdata[575:0]" +Toggle 1to0 readdata [550] "logic readdata[575:0]" +Toggle 0to1 readdata [550] "logic readdata[575:0]" +Toggle 1to0 readdata [549] "logic readdata[575:0]" +Toggle 0to1 readdata [549] "logic readdata[575:0]" +Toggle 1to0 readdata [548] "logic readdata[575:0]" +Toggle 0to1 readdata [548] "logic readdata[575:0]" +Toggle 1to0 readdata [547] "logic readdata[575:0]" +Toggle 0to1 readdata [547] "logic readdata[575:0]" +Toggle 1to0 readdata [546] "logic readdata[575:0]" +Toggle 0to1 readdata [546] "logic readdata[575:0]" +Toggle 1to0 readdata [545] "logic readdata[575:0]" +Toggle 0to1 readdata [545] "logic readdata[575:0]" +Toggle 1to0 readdata [544] "logic readdata[575:0]" +Toggle 0to1 readdata [544] "logic readdata[575:0]" +Toggle 1to0 readdata [543] "logic readdata[575:0]" +Toggle 0to1 readdata [543] "logic readdata[575:0]" +Toggle 1to0 readdata [542] "logic readdata[575:0]" +Toggle 0to1 readdata [542] "logic readdata[575:0]" +Toggle 1to0 readdata [541] "logic readdata[575:0]" +Toggle 0to1 readdata [541] "logic readdata[575:0]" +Toggle 1to0 readdata [540] "logic readdata[575:0]" +Toggle 0to1 readdata [540] "logic readdata[575:0]" +Toggle 1to0 readdata [539] "logic readdata[575:0]" +Toggle 0to1 readdata [539] "logic readdata[575:0]" +Toggle 1to0 readdata [538] "logic readdata[575:0]" +Toggle 0to1 readdata [538] "logic readdata[575:0]" +Toggle 1to0 readdata [537] "logic readdata[575:0]" +Toggle 0to1 readdata [537] "logic readdata[575:0]" +Toggle 1to0 readdata [536] "logic readdata[575:0]" +Toggle 0to1 readdata [536] "logic readdata[575:0]" +Toggle 1to0 readdata [535] "logic readdata[575:0]" +Toggle 0to1 readdata [535] "logic readdata[575:0]" +Toggle 1to0 readdata [534] "logic readdata[575:0]" +Toggle 0to1 readdata [534] "logic readdata[575:0]" +Toggle 1to0 readdata [533] "logic readdata[575:0]" +Toggle 0to1 readdata [533] "logic readdata[575:0]" +Toggle 1to0 readdata [532] "logic readdata[575:0]" +Toggle 0to1 readdata [532] "logic readdata[575:0]" +Toggle 1to0 readdata [531] "logic readdata[575:0]" +Toggle 0to1 readdata [531] "logic readdata[575:0]" +Toggle 1to0 readdata [530] "logic readdata[575:0]" +Toggle 0to1 readdata [530] "logic readdata[575:0]" +Toggle 1to0 readdata [529] "logic readdata[575:0]" +Toggle 0to1 readdata [529] "logic readdata[575:0]" +Toggle 1to0 readdata [528] "logic readdata[575:0]" +Toggle 0to1 readdata [528] "logic readdata[575:0]" +Toggle 1to0 readdata [527] "logic readdata[575:0]" +Toggle 0to1 readdata [527] "logic readdata[575:0]" +Toggle 1to0 readdata [526] "logic readdata[575:0]" +Toggle 0to1 readdata [526] "logic readdata[575:0]" +Toggle 1to0 readdata [525] "logic readdata[575:0]" +Toggle 0to1 readdata [525] "logic readdata[575:0]" +Toggle 1to0 readdata [524] "logic readdata[575:0]" +Toggle 0to1 readdata [524] "logic readdata[575:0]" +Toggle 1to0 readdata [523] "logic readdata[575:0]" +Toggle 0to1 readdata [523] "logic readdata[575:0]" +Toggle 1to0 readdata [522] "logic readdata[575:0]" +Toggle 0to1 readdata [522] "logic readdata[575:0]" +Toggle 1to0 readdata [521] "logic readdata[575:0]" +Toggle 0to1 readdata [521] "logic readdata[575:0]" +Toggle 1to0 readdata [520] "logic readdata[575:0]" +Toggle 0to1 readdata [520] "logic readdata[575:0]" +Toggle 1to0 readdata [519] "logic readdata[575:0]" +Toggle 0to1 readdata [519] "logic readdata[575:0]" +Toggle 1to0 readdata [518] "logic readdata[575:0]" +Toggle 0to1 readdata [518] "logic readdata[575:0]" +Toggle 1to0 readdata [517] "logic readdata[575:0]" +Toggle 0to1 readdata [517] "logic readdata[575:0]" +Toggle 1to0 readdata [516] "logic readdata[575:0]" +Toggle 0to1 readdata [516] "logic readdata[575:0]" +Toggle 1to0 readdata [515] "logic readdata[575:0]" +Toggle 0to1 readdata [515] "logic readdata[575:0]" +Toggle 1to0 readdata [514] "logic readdata[575:0]" +Toggle 0to1 readdata [514] "logic readdata[575:0]" +Toggle 1to0 readdata [513] "logic readdata[575:0]" +Toggle 0to1 readdata [513] "logic readdata[575:0]" +Toggle 1to0 readdata [512] "logic readdata[575:0]" +Toggle 0to1 readdata [512] "logic readdata[575:0]" +Toggle 1to0 readdata [575] "logic readdata[575:0]" +Toggle 0to1 readdata [575] "logic readdata[575:0]" +Toggle 1to0 writedata [574] "logic writedata[575:0]" +Toggle 0to1 writedata [574] "logic writedata[575:0]" +Toggle 1to0 writedata [573] "logic writedata[575:0]" +Toggle 0to1 writedata [573] "logic writedata[575:0]" +Toggle 1to0 writedata [572] "logic writedata[575:0]" +Toggle 0to1 writedata [572] "logic writedata[575:0]" +Toggle 1to0 writedata [571] "logic writedata[575:0]" +Toggle 0to1 writedata [571] "logic writedata[575:0]" +Toggle 1to0 writedata [570] "logic writedata[575:0]" +Toggle 0to1 writedata [570] "logic writedata[575:0]" +Toggle 1to0 writedata [569] "logic writedata[575:0]" +Toggle 0to1 writedata [569] "logic writedata[575:0]" +Toggle 1to0 writedata [568] "logic writedata[575:0]" +Toggle 0to1 writedata [568] "logic writedata[575:0]" +Toggle 1to0 writedata [567] "logic writedata[575:0]" +Toggle 0to1 writedata [567] "logic writedata[575:0]" +Toggle 1to0 writedata [566] "logic writedata[575:0]" +Toggle 0to1 writedata [566] "logic writedata[575:0]" +Toggle 1to0 writedata [565] "logic writedata[575:0]" +Toggle 0to1 writedata [565] "logic writedata[575:0]" +Toggle 1to0 writedata [564] "logic writedata[575:0]" +Toggle 0to1 writedata [564] "logic writedata[575:0]" +Toggle 1to0 writedata [563] "logic writedata[575:0]" +Toggle 0to1 writedata [563] "logic writedata[575:0]" +Toggle 1to0 writedata [562] "logic writedata[575:0]" +Toggle 0to1 writedata [562] "logic writedata[575:0]" +Toggle 1to0 writedata [561] "logic writedata[575:0]" +Toggle 0to1 writedata [561] "logic writedata[575:0]" +Toggle 1to0 writedata [560] "logic writedata[575:0]" +Toggle 0to1 writedata [560] "logic writedata[575:0]" +Toggle 1to0 writedata [559] "logic writedata[575:0]" +Toggle 0to1 writedata [559] "logic writedata[575:0]" +Toggle 1to0 writedata [558] "logic writedata[575:0]" +Toggle 0to1 writedata [558] "logic writedata[575:0]" +Toggle 1to0 writedata [557] "logic writedata[575:0]" +Toggle 0to1 writedata [557] "logic writedata[575:0]" +Toggle 1to0 writedata [556] "logic writedata[575:0]" +Toggle 0to1 writedata [556] "logic writedata[575:0]" +Toggle 1to0 writedata [555] "logic writedata[575:0]" +Toggle 0to1 writedata [555] "logic writedata[575:0]" +Toggle 1to0 writedata [554] "logic writedata[575:0]" +Toggle 0to1 writedata [554] "logic writedata[575:0]" +Toggle 1to0 writedata [553] "logic writedata[575:0]" +Toggle 0to1 writedata [553] "logic writedata[575:0]" +Toggle 1to0 writedata [552] "logic writedata[575:0]" +Toggle 0to1 writedata [552] "logic writedata[575:0]" +Toggle 1to0 writedata [551] "logic writedata[575:0]" +Toggle 0to1 writedata [551] "logic writedata[575:0]" +Toggle 1to0 writedata [550] "logic writedata[575:0]" +Toggle 0to1 writedata [550] "logic writedata[575:0]" +Toggle 1to0 writedata [549] "logic writedata[575:0]" +Toggle 0to1 writedata [549] "logic writedata[575:0]" +Toggle 1to0 writedata [548] "logic writedata[575:0]" +Toggle 0to1 writedata [548] "logic writedata[575:0]" +Toggle 1to0 writedata [547] "logic writedata[575:0]" +Toggle 0to1 writedata [547] "logic writedata[575:0]" +Toggle 1to0 writedata [546] "logic writedata[575:0]" +Toggle 0to1 writedata [546] "logic writedata[575:0]" +Toggle 1to0 writedata [545] "logic writedata[575:0]" +Toggle 0to1 writedata [545] "logic writedata[575:0]" +Toggle 1to0 writedata [544] "logic writedata[575:0]" +Toggle 0to1 writedata [544] "logic writedata[575:0]" +Toggle 1to0 writedata [543] "logic writedata[575:0]" +Toggle 0to1 writedata [543] "logic writedata[575:0]" +Toggle 1to0 writedata [542] "logic writedata[575:0]" +Toggle 0to1 writedata [542] "logic writedata[575:0]" +Toggle 1to0 writedata [541] "logic writedata[575:0]" +Toggle 0to1 writedata [541] "logic writedata[575:0]" +Toggle 1to0 writedata [540] "logic writedata[575:0]" +Toggle 0to1 writedata [540] "logic writedata[575:0]" +Toggle 1to0 writedata [539] "logic writedata[575:0]" +Toggle 0to1 writedata [539] "logic writedata[575:0]" +Toggle 1to0 writedata [538] "logic writedata[575:0]" +Toggle 0to1 writedata [538] "logic writedata[575:0]" +Toggle 1to0 writedata [537] "logic writedata[575:0]" +Toggle 0to1 writedata [537] "logic writedata[575:0]" +Toggle 1to0 writedata [536] "logic writedata[575:0]" +Toggle 0to1 writedata [536] "logic writedata[575:0]" +Toggle 1to0 writedata [535] "logic writedata[575:0]" +Toggle 0to1 writedata [535] "logic writedata[575:0]" +Toggle 1to0 writedata [534] "logic writedata[575:0]" +Toggle 0to1 writedata [534] "logic writedata[575:0]" +Toggle 1to0 writedata [533] "logic writedata[575:0]" +Toggle 0to1 writedata [533] "logic writedata[575:0]" +Toggle 1to0 writedata [532] "logic writedata[575:0]" +Toggle 0to1 writedata [532] "logic writedata[575:0]" +Toggle 1to0 writedata [531] "logic writedata[575:0]" +Toggle 0to1 writedata [531] "logic writedata[575:0]" +Toggle 1to0 writedata [530] "logic writedata[575:0]" +Toggle 0to1 writedata [530] "logic writedata[575:0]" +Toggle 1to0 writedata [529] "logic writedata[575:0]" +Toggle 0to1 writedata [529] "logic writedata[575:0]" +Toggle 1to0 writedata [528] "logic writedata[575:0]" +Toggle 0to1 writedata [528] "logic writedata[575:0]" +Toggle 1to0 writedata [527] "logic writedata[575:0]" +Toggle 0to1 writedata [527] "logic writedata[575:0]" +Toggle 1to0 writedata [526] "logic writedata[575:0]" +Toggle 0to1 writedata [526] "logic writedata[575:0]" +Toggle 1to0 writedata [525] "logic writedata[575:0]" +Toggle 0to1 writedata [525] "logic writedata[575:0]" +Toggle 1to0 writedata [524] "logic writedata[575:0]" +Toggle 0to1 writedata [524] "logic writedata[575:0]" +Toggle 1to0 writedata [523] "logic writedata[575:0]" +Toggle 0to1 writedata [523] "logic writedata[575:0]" +Toggle 1to0 writedata [522] "logic writedata[575:0]" +Toggle 0to1 writedata [522] "logic writedata[575:0]" +Toggle 1to0 writedata [521] "logic writedata[575:0]" +Toggle 0to1 writedata [521] "logic writedata[575:0]" +Toggle 1to0 writedata [520] "logic writedata[575:0]" +Toggle 0to1 writedata [520] "logic writedata[575:0]" +Toggle 1to0 writedata [519] "logic writedata[575:0]" +Toggle 0to1 writedata [519] "logic writedata[575:0]" +Toggle 1to0 writedata [518] "logic writedata[575:0]" +Toggle 0to1 writedata [518] "logic writedata[575:0]" +Toggle 1to0 writedata [517] "logic writedata[575:0]" +Toggle 0to1 writedata [517] "logic writedata[575:0]" +Toggle 1to0 writedata [516] "logic writedata[575:0]" +Toggle 0to1 writedata [516] "logic writedata[575:0]" +Toggle 1to0 writedata [515] "logic writedata[575:0]" +Toggle 0to1 writedata [515] "logic writedata[575:0]" +Toggle 1to0 writedata [514] "logic writedata[575:0]" +Toggle 0to1 writedata [514] "logic writedata[575:0]" +Toggle 1to0 writedata [513] "logic writedata[575:0]" +Toggle 0to1 writedata [513] "logic writedata[575:0]" +Toggle 1to0 writedata [512] "logic writedata[575:0]" +Toggle 0to1 writedata [512] "logic writedata[575:0]" +Toggle 1to0 writedata [575] "logic writedata[575:0]" +Toggle 0to1 writedata [575] "logic writedata[575:0]" +Toggle 1to0 rst_n "logic rst_n" +Toggle 0to1 rst_n "logic rst_n" +CHECKSUM: "2948434777 858782335" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_lpbk.mem_if +Toggle 1to0 address [25] "logic address[26:0]" +Toggle 0to1 address [25] "logic address[26:0]" +Toggle 1to0 address [24] "logic address[26:0]" +Toggle 0to1 address [24] "logic address[26:0]" +Toggle 1to0 address [23] "logic address[26:0]" +Toggle 0to1 address [23] "logic address[26:0]" +Toggle 1to0 address [22] "logic address[26:0]" +Toggle 0to1 address [22] "logic address[26:0]" +Toggle 1to0 address [21] "logic address[26:0]" +Toggle 0to1 address [21] "logic address[26:0]" +Toggle 1to0 address [20] "logic address[26:0]" +Toggle 0to1 address [20] "logic address[26:0]" +Toggle 1to0 address [19] "logic address[26:0]" +Toggle 0to1 address [19] "logic address[26:0]" +Toggle 1to0 address [18] "logic address[26:0]" +Toggle 0to1 address [18] "logic address[26:0]" +Toggle 1to0 address [17] "logic address[26:0]" +Toggle 0to1 address [17] "logic address[26:0]" +Toggle 1to0 address [16] "logic address[26:0]" +Toggle 0to1 address [16] "logic address[26:0]" +Toggle 1to0 address [15] "logic address[26:0]" +Toggle 0to1 address [15] "logic address[26:0]" +Toggle 1to0 address [14] "logic address[26:0]" +Toggle 0to1 address [14] "logic address[26:0]" +Toggle 1to0 address [13] "logic address[26:0]" +Toggle 0to1 address [13] "logic address[26:0]" +Toggle 1to0 address [12] "logic address[26:0]" +Toggle 0to1 address [12] "logic address[26:0]" +Toggle 1to0 address [11] "logic address[26:0]" +Toggle 0to1 address [11] "logic address[26:0]" +Toggle 1to0 address [26] "logic address[26:0]" +Toggle 0to1 address [26] "logic address[26:0]" +ANNOTATION: " Does not toggle " +Toggle byteenable "logic byteenable[71:0]" +ANNOTATION: " Does not toggle " +Toggle burstcount "logic burstcount[6:0]" +Toggle 1to0 readdatavalid "logic readdatavalid" +Toggle 0to1 readdatavalid "logic readdatavalid" +Toggle 1to0 burstcount [5] "logic burstcount[6:0]" +Toggle 0to1 burstcount [5] "logic burstcount[6:0]" +Toggle 1to0 burstcount [4] "logic burstcount[6:0]" +Toggle 0to1 burstcount [4] "logic burstcount[6:0]" +Toggle 1to0 burstcount [3] "logic burstcount[6:0]" +Toggle 0to1 burstcount [3] "logic burstcount[6:0]" +Toggle 1to0 burstcount [6] "logic burstcount[6:0]" +Toggle 0to1 burstcount [6] "logic burstcount[6:0]" +ANNOTATION: " Does not toggle " +Toggle readdata "logic readdata[575:0]" +Toggle 0to1 clk "logic clk" +Toggle 1to0 clk "logic clk" +Toggle 0to1 rst_n "logic rst_n" +Toggle 1to0 rst_n "logic rst_n" +Toggle 0to1 ecc_interrupt "logic ecc_interrupt" +Toggle 1to0 ecc_interrupt "logic ecc_interrupt" +Toggle 0to1 writeresponsevalid "logic writeresponsevalid" +Toggle 1to0 writeresponsevalid "logic writeresponsevalid" +Toggle 0to1 writedata [575] "logic writedata[575:0]" +Toggle 1to0 writedata [575] "logic writedata[575:0]" +Toggle 0to1 writedata [512] "logic writedata[575:0]" +Toggle 1to0 writedata [512] "logic writedata[575:0]" +Toggle 0to1 writedata [513] "logic writedata[575:0]" +Toggle 1to0 writedata [513] "logic writedata[575:0]" +Toggle 0to1 writedata [514] "logic writedata[575:0]" +Toggle 1to0 writedata [514] "logic writedata[575:0]" +Toggle 0to1 writedata [515] "logic writedata[575:0]" +Toggle 1to0 writedata [515] "logic writedata[575:0]" +Toggle 0to1 writedata [516] "logic writedata[575:0]" +Toggle 1to0 writedata [516] "logic writedata[575:0]" +Toggle 0to1 writedata [517] "logic writedata[575:0]" +Toggle 1to0 writedata [517] "logic writedata[575:0]" +Toggle 0to1 writedata [518] "logic writedata[575:0]" +Toggle 1to0 writedata [518] "logic writedata[575:0]" +Toggle 0to1 writedata [519] "logic writedata[575:0]" +Toggle 1to0 writedata [519] "logic writedata[575:0]" +Toggle 0to1 writedata [520] "logic writedata[575:0]" +Toggle 1to0 writedata [520] "logic writedata[575:0]" +Toggle 0to1 writedata [521] "logic writedata[575:0]" +Toggle 1to0 writedata [521] "logic writedata[575:0]" +Toggle 0to1 writedata [522] "logic writedata[575:0]" +Toggle 1to0 writedata [522] "logic writedata[575:0]" +Toggle 0to1 writedata [523] "logic writedata[575:0]" +Toggle 1to0 writedata [523] "logic writedata[575:0]" +Toggle 0to1 writedata [524] "logic writedata[575:0]" +Toggle 1to0 writedata [524] "logic writedata[575:0]" +Toggle 0to1 writedata [525] "logic writedata[575:0]" +Toggle 1to0 writedata [525] "logic writedata[575:0]" +Toggle 0to1 writedata [526] "logic writedata[575:0]" +Toggle 1to0 writedata [526] "logic writedata[575:0]" +Toggle 0to1 writedata [527] "logic writedata[575:0]" +Toggle 1to0 writedata [527] "logic writedata[575:0]" +Toggle 0to1 writedata [528] "logic writedata[575:0]" +Toggle 1to0 writedata [528] "logic writedata[575:0]" +Toggle 0to1 writedata [529] "logic writedata[575:0]" +Toggle 1to0 writedata [529] "logic writedata[575:0]" +Toggle 0to1 writedata [530] "logic writedata[575:0]" +Toggle 1to0 writedata [530] "logic writedata[575:0]" +Toggle 0to1 writedata [531] "logic writedata[575:0]" +Toggle 1to0 writedata [531] "logic writedata[575:0]" +Toggle 0to1 writedata [532] "logic writedata[575:0]" +Toggle 1to0 writedata [532] "logic writedata[575:0]" +Toggle 0to1 writedata [533] "logic writedata[575:0]" +Toggle 1to0 writedata [533] "logic writedata[575:0]" +Toggle 0to1 writedata [534] "logic writedata[575:0]" +Toggle 1to0 writedata [534] "logic writedata[575:0]" +Toggle 0to1 writedata [535] "logic writedata[575:0]" +Toggle 1to0 writedata [535] "logic writedata[575:0]" +Toggle 0to1 writedata [536] "logic writedata[575:0]" +Toggle 1to0 writedata [536] "logic writedata[575:0]" +Toggle 0to1 writedata [537] "logic writedata[575:0]" +Toggle 1to0 writedata [537] "logic writedata[575:0]" +Toggle 0to1 writedata [538] "logic writedata[575:0]" +Toggle 1to0 writedata [538] "logic writedata[575:0]" +Toggle 0to1 writedata [539] "logic writedata[575:0]" +Toggle 1to0 writedata [539] "logic writedata[575:0]" +Toggle 0to1 writedata [540] "logic writedata[575:0]" +Toggle 1to0 writedata [540] "logic writedata[575:0]" +Toggle 0to1 writedata [541] "logic writedata[575:0]" +Toggle 1to0 writedata [541] "logic writedata[575:0]" +Toggle 0to1 writedata [542] "logic writedata[575:0]" +Toggle 1to0 writedata [542] "logic writedata[575:0]" +Toggle 0to1 writedata [543] "logic writedata[575:0]" +Toggle 1to0 writedata [543] "logic writedata[575:0]" +Toggle 0to1 writedata [544] "logic writedata[575:0]" +Toggle 1to0 writedata [544] "logic writedata[575:0]" +Toggle 0to1 writedata [545] "logic writedata[575:0]" +Toggle 1to0 writedata [545] "logic writedata[575:0]" +Toggle 0to1 writedata [546] "logic writedata[575:0]" +Toggle 1to0 writedata [546] "logic writedata[575:0]" +Toggle 0to1 writedata [547] "logic writedata[575:0]" +Toggle 1to0 writedata [547] "logic writedata[575:0]" +Toggle 0to1 writedata [548] "logic writedata[575:0]" +Toggle 1to0 writedata [548] "logic writedata[575:0]" +Toggle 0to1 writedata [549] "logic writedata[575:0]" +Toggle 1to0 writedata [549] "logic writedata[575:0]" +Toggle 0to1 writedata [550] "logic writedata[575:0]" +Toggle 1to0 writedata [550] "logic writedata[575:0]" +Toggle 0to1 writedata [551] "logic writedata[575:0]" +Toggle 1to0 writedata [551] "logic writedata[575:0]" +Toggle 0to1 writedata [552] "logic writedata[575:0]" +Toggle 1to0 writedata [552] "logic writedata[575:0]" +Toggle 0to1 writedata [553] "logic writedata[575:0]" +Toggle 1to0 writedata [553] "logic writedata[575:0]" +Toggle 0to1 writedata [554] "logic writedata[575:0]" +Toggle 1to0 writedata [554] "logic writedata[575:0]" +Toggle 0to1 writedata [555] "logic writedata[575:0]" +Toggle 1to0 writedata [555] "logic writedata[575:0]" +Toggle 0to1 writedata [556] "logic writedata[575:0]" +Toggle 1to0 writedata [556] "logic writedata[575:0]" +Toggle 0to1 writedata [557] "logic writedata[575:0]" +Toggle 1to0 writedata [557] "logic writedata[575:0]" +Toggle 0to1 writedata [558] "logic writedata[575:0]" +Toggle 1to0 writedata [558] "logic writedata[575:0]" +Toggle 0to1 writedata [559] "logic writedata[575:0]" +Toggle 1to0 writedata [559] "logic writedata[575:0]" +Toggle 0to1 writedata [560] "logic writedata[575:0]" +Toggle 1to0 writedata [560] "logic writedata[575:0]" +Toggle 0to1 writedata [561] "logic writedata[575:0]" +Toggle 1to0 writedata [561] "logic writedata[575:0]" +Toggle 0to1 writedata [562] "logic writedata[575:0]" +Toggle 1to0 writedata [562] "logic writedata[575:0]" +Toggle 0to1 writedata [563] "logic writedata[575:0]" +Toggle 1to0 writedata [563] "logic writedata[575:0]" +Toggle 0to1 writedata [564] "logic writedata[575:0]" +Toggle 1to0 writedata [564] "logic writedata[575:0]" +Toggle 0to1 writedata [565] "logic writedata[575:0]" +Toggle 1to0 writedata [565] "logic writedata[575:0]" +Toggle 0to1 writedata [566] "logic writedata[575:0]" +Toggle 1to0 writedata [566] "logic writedata[575:0]" +Toggle 0to1 writedata [567] "logic writedata[575:0]" +Toggle 1to0 writedata [567] "logic writedata[575:0]" +Toggle 0to1 writedata [568] "logic writedata[575:0]" +Toggle 1to0 writedata [568] "logic writedata[575:0]" +Toggle 0to1 writedata [569] "logic writedata[575:0]" +Toggle 1to0 writedata [569] "logic writedata[575:0]" +Toggle 0to1 writedata [570] "logic writedata[575:0]" +Toggle 1to0 writedata [570] "logic writedata[575:0]" +Toggle 0to1 writedata [571] "logic writedata[575:0]" +Toggle 1to0 writedata [571] "logic writedata[575:0]" +Toggle 0to1 writedata [572] "logic writedata[575:0]" +Toggle 1to0 writedata [572] "logic writedata[575:0]" +Toggle 0to1 writedata [573] "logic writedata[575:0]" +Toggle 1to0 writedata [573] "logic writedata[575:0]" +Toggle 0to1 writedata [574] "logic writedata[575:0]" +Toggle 1to0 writedata [574] "logic writedata[575:0]" +CHECKSUM: "3520213052 291490293" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_rx_rsp_q +Block 2 "4108503805" "out0 = (raddr0[0] ? odd_out : even_out);" +Block 5 "2211809701" "even_din = even_in_q;" +CHECKSUM: "3520213052 291490293" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_tx_req_q +Block 2 "4108503805" "out0 = (raddr0[0] ? odd_out : even_out);" +Block 6 "724266113" "even_din = (((!w_odd_even[0]) & wen0) ? din0 : din1);" +CHECKSUM: "3190985420 2894799360" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_tx_req_q.even_que.fifo_ram +Toggle perr_in "logic perr_in[8:0]" +Toggle 1to0 perr_or "logic perr_or" +Toggle 0to1 perr_or "logic perr_or" +Toggle 1to0 perr "logic perr" +Toggle 0to1 perr "logic perr" +CHECKSUM: "3190985420 2894799360" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_tx_req_q.odd_que.fifo_ram +Toggle perr_in "logic perr_in[8:0]" +Toggle 1to0 perr_or "logic perr_or" +Toggle 0to1 perr_or "logic perr_or" +Toggle 1to0 perr "logic perr" +Toggle 0to1 perr "logic perr" +CHECKSUM: "3190985420 2021409564" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_rx_rsp_q.even_que.fifo_ram +Toggle perr_in "logic perr_in[8:0]" +Toggle 1to0 perr_or "logic perr_or" +Toggle 0to1 perr_or "logic perr_or" +Toggle 1to0 perr "logic perr" +Toggle 0to1 perr "logic perr" +CHECKSUM: "3190985420 2021409564" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.he_rx_rsp_q.odd_que.fifo_ram +Toggle perr_in "logic perr_in[8:0]" +Toggle 1to0 perr_or "logic perr_or" +Toggle 0to1 perr_or "logic perr_or" +Toggle 1to0 perr "logic perr" +Toggle 0to1 perr "logic perr" +CHECKSUM: "599439132 1795363957" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_lpbk.emif_req_q +ANNOTATION: " Data signals " +Toggle fifo_dout "net fifo_dout[604:0]" +ANNOTATION: " Data signals " +Toggle fifo_din "net fifo_din[604:0]" +Toggle 0to1 almost_empty "net almost_empty" +Toggle 1to0 almost_empty "net almost_empty" +Toggle 0to1 full "net full" +Toggle 1to0 full "net full" +Toggle 0to1 fifo_err "logic fifo_err" +Toggle 1to0 fifo_err "logic fifo_err" +ANNOTATION: " Not connected " +Toggle fifo_eccstatus "net fifo_eccstatus[1:0]" +CHECKSUM: "599439132 1844698467" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_lpbk.rx_q +ANNOTATION: " Data signals " +Toggle fifo_dout "net fifo_dout[513:0]" +ANNOTATION: " Data signals " +Toggle fifo_din "net fifo_din[513:0]" +Toggle 0to1 almost_empty "net almost_empty" +Toggle 1to0 almost_empty "net almost_empty" +Toggle 0to1 full "net full" +Toggle 1to0 full "net full" +Toggle 0to1 fifo_err "logic fifo_err" +Toggle 1to0 fifo_err "logic fifo_err" +ANNOTATION: " Not connected " +Toggle fifo_eccstatus "net fifo_eccstatus[1:0]" +CHECKSUM: "599439132 1418678335" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.mmio_rsp_q +Toggle 1to0 fifo_count [2] "net fifo_count[3:0]" +Toggle 0to1 fifo_count [2] "net fifo_count[3:0]" +Toggle 1to0 fifo_count [1] "net fifo_count[3:0]" +Toggle 0to1 fifo_count [1] "net fifo_count[3:0]" +Toggle 1to0 fifo_count [3] "net fifo_count[3:0]" +Toggle 0to1 fifo_count [3] "net fifo_count[3:0]" +ANNOTATION: " Data signals " +Toggle fifo_dout "net fifo_dout[511:0]" +ANNOTATION: " Data signals " +Toggle fifo_din "net fifo_din[511:0]" +Toggle 0to1 almost_empty "net almost_empty" +Toggle 1to0 almost_empty "net almost_empty" +Toggle 0to1 full "net full" +Toggle 1to0 full "net full" +Toggle 0to1 fifo_err "logic fifo_err" +Toggle 1to0 fifo_err "logic fifo_err" +ANNOTATION: " Not connected " +Toggle fifo_eccstatus "net fifo_eccstatus[1:0]" +CHECKSUM: "599439132 2723442098" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_lpbk.tx_q +ANNOTATION: " Data signals " +Toggle fifo_dout "net fifo_dout[514:0]" +ANNOTATION: " Data signals " +Toggle fifo_din "net fifo_din[514:0]" +Toggle 0to1 fifo_err "logic fifo_err" +Toggle 1to0 fifo_err "logic fifo_err" +Toggle 0to1 full "net full" +Toggle 1to0 full "net full" +Toggle 0to1 almost_empty "net almost_empty" +Toggle 1to0 almost_empty "net almost_empty" +ANNOTATION: " Not connected " +Toggle fifo_eccstatus "net fifo_eccstatus[1:0]" +Toggle 0to1 fifo_count [10] "net fifo_count[10:0]" +Toggle 1to0 fifo_count [10] "net fifo_count[10:0]" +Toggle 0to1 fifo_count [9] "net fifo_count[10:0]" +Toggle 1to0 fifo_count [9] "net fifo_count[10:0]" +CHECKSUM: "599439132 2365331093" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_rdwr.tx_q +ANNOTATION: " Data signals " +Toggle fifo_dout "net fifo_dout[38:0]" +ANNOTATION: " Data signals " +Toggle fifo_din "net fifo_din[38:0]" +Toggle 0to1 almost_empty "net almost_empty" +Toggle 1to0 almost_empty "net almost_empty" +Toggle 0to1 full "net full" +Toggle 1to0 full "net full" +Toggle 0to1 fifo_err "logic fifo_err" +Toggle 1to0 fifo_err "logic fifo_err" +ANNOTATION: " Not connected " +Toggle fifo_eccstatus "net fifo_eccstatus[1:0]" +CHECKSUM: "965016526 1952858649" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_rdwr +Block 76 "1604857731" ";" +Block 80 "2371758446" ";" +Block 84 "145859954" ";" +Block 71 "2245356259" "ErrorVector[1] <= 1;" +Block 83 "853555128" "#100" +Block 79 "3842708538" "$display(\"======================================================================================================\");" +Block 75 "676313567" "$display(\"======================================================================================================\");" +CHECKSUM: "1259019545 702362531" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.axi_rx_stage_1 +ANNOTATION: " Not valid condition " +Condition 1 "4206754987" "(((~genblk1.s_tready_pre)) && genblk1.s_tready_reg) 1 -1" (1 "01") +CHECKSUM: "1259019545 702362531" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.axi_rx_stage_2 +ANNOTATION: " Not valid condition " +Condition 1 "4206754987" "(((~genblk1.s_tready_pre)) && genblk1.s_tready_reg) 1 -1" (1 "01") +CHECKSUM: "1259019545 702362531" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.axi_tx_stage_1 +ANNOTATION: " Not valid condition " +Condition 1 "4206754987" "(((~genblk1.s_tready_pre)) && genblk1.s_tready_reg) 1 -1" (1 "01") +CHECKSUM: "599439132 3833084147" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_rdwr.tx_q +Block 5 "1895881913" "fifo_err <= 1'b1;" +Block 4 "2246164006" "fifo_err <= 1'b1;" +CHECKSUM: "599439132 3833084147" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_lpbk.emif_req_q +Block 5 "1895881913" "fifo_err <= 1'b1;" +Block 4 "2246164006" "fifo_err <= 1'b1;" +CHECKSUM: "599439132 3833084147" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_lpbk.rx_q +Block 5 "1895881913" "fifo_err <= 1'b1;" +Block 4 "2246164006" "fifo_err <= 1'b1;" +CHECKSUM: "599439132 3833084147" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_lpbk.tx_q +Block 5 "1895881913" "fifo_err <= 1'b1;" +Block 4 "2246164006" "fifo_err <= 1'b1;" +CHECKSUM: "599439132 3833084147" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.mmio_rsp_q +Block 5 "1895881913" "fifo_err <= 1'b1;" +Block 4 "2246164006" "fifo_err <= 1'b1;" +CHECKSUM: "2618233009 1440168460" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req +Block 155 "157836716" ";" +Block 154 "853555128" "#100" +ANNOTATION: "ErrorVector[1] is 0" +Block 142 "268819500" "ErrorVector[1] <= 1;" +ANNOTATION: "Errorvector[2] is 0" +Block 145 "3910752870" "ErrorVector[2] <= 1;" +ANNOTATION: "Errorvector[3] is 0" +Block 148 "2228869873" "ErrorVector[3] <= 1;" +ANNOTATION: "Errorvector[4] is 0" +Block 151 "2400460436" "ErrorVector[4] <= 1;" +ANNOTATION: "errorVector[0] is 0" +Block 139 "1901327212" "ErrorVector[0] <= 1;" +CHECKSUM: "1575787188 369815844" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_lpbk +Block 132 "1608699120" ";" +Block 136 "977391136" ";" +Block 140 "1084742192" ";" +Block 144 "1354075342" ";" +Block 149 "1604857731" ";" +Block 153 "2392870434" ";" +Block 157 "201305867" ";" +Block 161 "145859954" ";" +Block 132 "1608699120" ";" +Block 136 "977391136" ";" +Block 140 "1084742192" ";" +Block 144 "1354075342" ";" +Block 149 "1604857731" ";" +Block 153 "2392870434" ";" +Block 157 "201305867" ";" +Block 161 "145859954" ";" +Block 132 "1608699120" ";" +Block 136 "977391136" ";" +Block 140 "1084742192" ";" +Block 144 "1354075342" ";" +Block 149 "1604857731" ";" +Block 153 "2392870434" ";" +Block 157 "201305867" ";" +Block 161 "145859954" ";" +Block 132 "1608699120" ";" +Block 136 "977391136" ";" +Block 140 "1084742192" ";" +Block 144 "1354075342" ";" +Block 149 "1604857731" ";" +Block 153 "2392870434" ";" +Block 157 "201305867" ";" +Block 161 "145859954" ";" +Block 132 "1608699120" ";" +Block 136 "977391136" ";" +Block 140 "1084742192" ";" +Block 144 "1354075342" ";" +Block 149 "1604857731" ";" +Block 153 "2392870434" ";" +Block 157 "201305867" ";" +Block 161 "145859954" ";" +Block 132 "1608699120" ";" +Block 136 "977391136" ";" +Block 140 "1084742192" ";" +Block 144 "1354075342" ";" +Block 149 "1604857731" ";" +Block 153 "2392870434" ";" +Block 157 "201305867" ";" +Block 161 "145859954" ";" +Block 132 "1608699120" ";" +Block 136 "977391136" ";" +Block 140 "1084742192" ";" +Block 144 "1354075342" ";" +Block 149 "1604857731" ";" +Block 153 "2392870434" ";" +Block 157 "201305867" ";" +Block 161 "145859954" ";" +Block 132 "1608699120" ";" +Block 136 "977391136" ";" +Block 140 "1084742192" ";" +Block 144 "1354075342" ";" +Block 149 "1604857731" ";" +Block 153 "2392870434" ";" +Block 157 "201305867" ";" +Block 161 "145859954" ";" +CHECKSUM: "1575787188 369815844" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_lpbk +ANNOTATION: " Header " +Toggle ram_rad "logic ram_rad[7:0]" +CHECKSUM: "471063460 132245459" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_rdwr +Toggle 1to0 req_cnt [10:10]"logic req_cnt[26:0]" +Toggle 0to1 req_cnt [10:10]"logic req_cnt[26:0]" +Toggle 1to0 req_cnt [9:9]"logic req_cnt[26:0]" +Toggle 0to1 req_cnt [9:9]"logic req_cnt[26:0]" +CHECKSUM: "1097727372 702362531" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.axi_rx_stage_1 +Toggle genblk1.m_tdest_pre "logic genblk1.m_tdest_pre[7:0]" +Toggle s_tid "logic s_tid[7:0]" +Toggle s_tdest "logic s_tdest[7:0]" +Toggle m_tid "logic m_tid[7:0]" +Toggle genblk1.s_tid_reg "logic genblk1.s_tid_reg[7:0]" +Toggle genblk1.s_tdest_reg "logic genblk1.s_tdest_reg[7:0]" +Toggle genblk1.m_tid_reg "logic genblk1.m_tid_reg[7:0]" +Toggle genblk1.m_tid_pre "logic genblk1.m_tid_pre[7:0]" +Toggle genblk1.m_tdest_reg "logic genblk1.m_tdest_reg[7:0]" +Toggle 0to1 s_tuser [9:9]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [9:9]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [1:1]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [1:1]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [2:2]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [2:2]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [3:3]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [3:3]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [4:4]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [4:4]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [5:5]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [5:5]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [6:6]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [6:6]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [7:7]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [7:7]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [8:8]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [8:8]"logic s_tuser[9:0]" +Toggle 0to1 m_tuser [9:9]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [9:9]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [1:1]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [1:1]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [2:2]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [2:2]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [3:3]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [3:3]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [4:4]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [4:4]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [5:5]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [5:5]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [6:6]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [6:6]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [7:7]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [7:7]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [8:8]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [8:8]"logic m_tuser[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [9:9]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [9:9]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [1:1]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [1:1]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [2:2]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [2:2]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [3:3]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [3:3]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [4:4]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [4:4]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [5:5]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [5:5]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [6:6]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [6:6]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [7:7]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [7:7]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [8:8]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [8:8]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [9:9]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [9:9]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [1:1]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [1:1]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [2:2]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [2:2]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [3:3]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [3:3]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [4:4]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [4:4]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [5:5]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [5:5]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [6:6]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [6:6]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [7:7]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [7:7]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [8:8]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [8:8]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [9:9]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [9:9]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [1:1]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [1:1]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [2:2]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [2:2]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [3:3]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [3:3]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [4:4]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [4:4]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [5:5]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [5:5]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [6:6]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [6:6]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [7:7]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [7:7]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [8:8]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [8:8]"logic genblk1.m_tuser_pre[9:0]" +CHECKSUM: "1097727372 702362531" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.axi_rx_stage_2 +Toggle genblk1.m_tdest_pre "logic genblk1.m_tdest_pre[7:0]" +Toggle s_tid "logic s_tid[7:0]" +Toggle s_tdest "logic s_tdest[7:0]" +Toggle m_tid "logic m_tid[7:0]" +Toggle genblk1.s_tid_reg "logic genblk1.s_tid_reg[7:0]" +Toggle genblk1.s_tdest_reg "logic genblk1.s_tdest_reg[7:0]" +Toggle genblk1.m_tid_reg "logic genblk1.m_tid_reg[7:0]" +Toggle genblk1.m_tid_pre "logic genblk1.m_tid_pre[7:0]" +Toggle genblk1.m_tdest_reg "logic genblk1.m_tdest_reg[7:0]" +Toggle 0to1 genblk1.m_tuser_pre [9:9]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [9:9]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [1:1]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [1:1]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [2:2]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [2:2]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [3:3]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [3:3]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [4:4]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [4:4]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [5:5]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [5:5]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [6:6]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [6:6]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [7:7]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [7:7]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [8:8]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [8:8]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [9:9]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [9:9]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [1:1]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [1:1]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [2:2]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [2:2]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [3:3]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [3:3]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [4:4]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [4:4]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [5:5]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [5:5]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [6:6]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [6:6]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [7:7]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [7:7]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [8:8]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [8:8]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 s_tuser [9:9]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [9:9]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [1:1]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [1:1]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [2:2]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [2:2]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [3:3]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [3:3]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [4:4]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [4:4]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [5:5]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [5:5]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [6:6]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [6:6]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [7:7]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [7:7]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [8:8]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [8:8]"logic s_tuser[9:0]" +Toggle 0to1 m_tuser [9:9]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [9:9]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [1:1]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [1:1]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [2:2]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [2:2]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [3:3]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [3:3]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [4:4]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [4:4]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [5:5]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [5:5]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [6:6]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [6:6]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [7:7]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [7:7]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [8:8]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [8:8]"logic m_tuser[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [9:9]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [9:9]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [1:1]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [1:1]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [2:2]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [2:2]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [3:3]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [3:3]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [4:4]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [4:4]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [5:5]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [5:5]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [6:6]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [6:6]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [7:7]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [7:7]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [8:8]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [8:8]"logic genblk1.s_tuser_reg[9:0]" +CHECKSUM: "1097727372 702362531" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.axi_tx_stage_1 +Toggle s_tid "logic s_tid[7:0]" +Toggle 0to1 genblk1.m_tuser_pre [9:9]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [9:9]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [1:1]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [1:1]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [2:2]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [2:2]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [3:3]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [3:3]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [4:4]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [4:4]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [5:5]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [5:5]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [6:6]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [6:6]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [7:7]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [7:7]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [8:8]"logic genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [8:8]"logic genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [9:9]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [9:9]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [1:1]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [1:1]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [2:2]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [2:2]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [3:3]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [3:3]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [4:4]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [4:4]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [5:5]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [5:5]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [6:6]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [6:6]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [7:7]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [7:7]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [8:8]"logic genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [8:8]"logic genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [9:9]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [9:9]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [1:1]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [1:1]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [2:2]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [2:2]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [3:3]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [3:3]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [4:4]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [4:4]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [5:5]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [5:5]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [6:6]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [6:6]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [7:7]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [7:7]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [8:8]"logic genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [8:8]"logic genblk1.s_tuser_reg[9:0]" +Toggle 0to1 s_tuser [9:9]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [9:9]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [1:1]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [1:1]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [2:2]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [2:2]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [3:3]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [3:3]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [4:4]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [4:4]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [5:5]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [5:5]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [6:6]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [6:6]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [7:7]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [7:7]"logic s_tuser[9:0]" +Toggle 0to1 s_tuser [8:8]"logic s_tuser[9:0]" +Toggle 1to0 s_tuser [8:8]"logic s_tuser[9:0]" +Toggle 0to1 m_tuser [9:9]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [9:9]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [1:1]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [1:1]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [2:2]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [2:2]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [3:3]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [3:3]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [4:4]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [4:4]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [5:5]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [5:5]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [6:6]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [6:6]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [7:7]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [7:7]"logic m_tuser[9:0]" +Toggle 0to1 m_tuser [8:8]"logic m_tuser[9:0]" +Toggle 1to0 m_tuser [8:8]"logic m_tuser[9:0]" +Toggle genblk1.m_tdest_pre "logic genblk1.m_tdest_pre[7:0]" +Toggle s_tdest "logic s_tdest[7:0]" +Toggle m_tid "logic m_tid[7:0]" +Toggle genblk1.s_tid_reg "logic genblk1.s_tid_reg[7:0]" +Toggle genblk1.m_tid_reg "logic genblk1.m_tid_reg[7:0]" +Toggle genblk1.m_tid_pre "logic genblk1.m_tid_pre[7:0]" +Toggle genblk1.m_tdest_reg "logic genblk1.m_tdest_reg[7:0]" +CHECKSUM: "471063460 132245459" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_rdwr +Block 91 "157836716" ";" +Block 87 "3892685149" ";" +Block 83 "3524869349" ";" +Block 91 "157836716" ";" +Block 87 "3892685149" ";" +Block 83 "3524869349" ";" +Block 91 "157836716" ";" +Block 87 "3892685149" ";" +Block 83 "3524869349" ";" +CHECKSUM: "3704842485 2457344362" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req +ANNOTATION: "ErrorVector is 0" +Block 155 "145859954" ";" +CHECKSUM: "471063460 2567436146" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.mode_rdwr +Toggle 0to1 req_cnt [26:26]"logic req_cnt[26:0]" diff --git a/verification/coverage/interface_inside_afu_exclusions.el b/verification/coverage/interface_inside_afu_exclusions.el new file mode 100644 index 0000000..e6d7c2d --- /dev/null +++ b/verification/coverage/interface_inside_afu_exclusions.el @@ -0,0 +1,93 @@ +//================================================== +// This file contains the Excluded objects +// Generated By User: maravi3x +// Format Version: 2 +// Date: Wed Feb 16 01:32:09 2022 +// ExclMode: default +//================================================== +CHECKSUM: "869564193" +ANNOTATION: " Excluded as per designer's input.Could see that since parameter AXI4_LITE_CSR is set to 0. This interface will not be used. " +INSTANCE:tb_top.DUT.afu_top.he_lb_csr_if +CHECKSUM: "4202741256" +ANNOTATION: " Excluded as per designer's input.Port 1 and 2 are connected to afu_tx_a_port[1] and afu_tx_a_port[2] respectively which is already excluded in the top level. " +INSTANCE:tb_top.DUT.afu_top.fn2mx_tx_a_port[2] +CHECKSUM: "4202741256" +ANNOTATION: " Excluded as per designer's input.Port 1 and 2 are connected to afu_tx_a_port[1] and afu_tx_a_port[2] respectively which is already excluded in the top level. " +INSTANCE:tb_top.DUT.afu_top.fn2mx_tx_a_port[3] + +CHECKSUM: "4202741256 701653482" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_port +Toggle 0to1 clk "net clk" +Toggle 1to0 clk "net clk" +Toggle 0to1 rst_n "net rst_n" +Toggle 1to0 rst_n "net rst_n" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "4202741256 701653482" +INSTANCE: tb_top.DUT.afu_top.ho2mx_rx_port +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 clk "net clk" +Toggle 1to0 clk "net clk" +Toggle 0to1 rst_n "net rst_n" +Toggle 1to0 rst_n "net rst_n" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.ho2mx_rx_port +ANNOTATION: " Could see that clk and rst_n for this interface is floating .Excluded as per designer's input " +Assert assert_tkeep_undef_when_tvalid_high "assertion" +ANNOTATION: " Could see that clk and rst_n for this interface is floating .Excluded as per designer's input " +Assert assert_tvalid_undef_when_not_in_reset "assertion" +ANNOTATION: " Could see that clk and rst_n for this interface is floating .Excluded as per designer's input " +Assert assert_tvalid_tready_handshake "assertion" +ANNOTATION: " Could see that clk and rst_n for this interface is floating .Excluded as per designer's input " +Assert assert_tuser_undef_when_tvalid_high "assertion" +ANNOTATION: " Could see that clk and rst_n for this interface is floating .Excluded as per designer's input " +Assert assert_tready_undef_when_not_in_reset "assertion" +ANNOTATION: " Could see that clk and rst_n for this interface is floating .Excluded as per designer's input " +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_port +ANNOTATION: " Could see that clk and rst_n for this interface is floating .Excluded as per designer's input " +Assert assert_tkeep_undef_when_tvalid_high "assertion" +ANNOTATION: " Could see that clk and rst_n for this interface is floating .Excluded as per designer's input " +Assert assert_tvalid_undef_when_not_in_reset "assertion" +ANNOTATION: " Could see that clk and rst_n for this interface is floating .Excluded as per designer's input " +Assert assert_tvalid_tready_handshake "assertion" +ANNOTATION: " Could see that clk and rst_n for this interface is floating .Excluded as per designer's input " +Assert assert_tuser_undef_when_tvalid_high "assertion" +ANNOTATION: " Could see that clk and rst_n for this interface is floating .Excluded as per designer's input " +Assert assert_tready_undef_when_not_in_reset "assertion" +ANNOTATION: " Could see that clk and rst_n for this interface is floating .Excluded as per designer's input " +Assert assert_tlast_undef_when_tvalid_high "assertion" diff --git a/verification/coverage/interface_outside_afu_exclusions.el b/verification/coverage/interface_outside_afu_exclusions.el new file mode 100644 index 0000000..d9b508f --- /dev/null +++ b/verification/coverage/interface_outside_afu_exclusions.el @@ -0,0 +1,451 @@ +//================================================== +// This file contains the Excluded objects +// Generated By User: srudrarx +// Format Version: 2 +// Date: Wed May 25 03:35:55 2022 +// ExclMode: default +//================================================== +CHECKSUM: "869564193" +INSTANCE:tb_top.DUT.bpf_pmci_slv_if +CHECKSUM: "869564193" +ANNOTATION: " Excluded as per designer?s input.Interface not used " +INSTANCE:tb_top.DUT.m_afu_lite +CHECKSUM: "869564193 23825937" +INSTANCE: tb_top.DUT.bpf_fme_slv_if +Toggle bresp "logic bresp[1:0]" +Toggle rresp "logic rresp[1:0]" +CHECKSUM: "869564193 23825937" +INSTANCE: tb_top.DUT.bpf_pmci_slv_if +Toggle 0to1 araddr [0] "logic araddr[15:0]" +Toggle 1to0 araddr [0] "logic araddr[15:0]" +Toggle 0to1 araddr [1] "logic araddr[15:0]" +Toggle 1to0 araddr [1] "logic araddr[15:0]" +Toggle 0to1 araddr [4] "logic araddr[15:0]" +Toggle 1to0 araddr [4] "logic araddr[15:0]" +Toggle 0to1 araddr [5] "logic araddr[15:0]" +Toggle 1to0 araddr [5] "logic araddr[15:0]" +Toggle 0to1 araddr [7] "logic araddr[15:0]" +Toggle 1to0 araddr [7] "logic araddr[15:0]" +Toggle 0to1 araddr [8] "logic araddr[15:0]" +Toggle 1to0 araddr [8] "logic araddr[15:0]" +Toggle 0to1 araddr [9] "logic araddr[15:0]" +Toggle 1to0 araddr [9] "logic araddr[15:0]" +Toggle 0to1 araddr [12] "logic araddr[15:0]" +Toggle 1to0 araddr [12] "logic araddr[15:0]" +Toggle 0to1 araddr [13] "logic araddr[15:0]" +Toggle 1to0 araddr [13] "logic araddr[15:0]" +Toggle 0to1 araddr [14] "logic araddr[15:0]" +Toggle 1to0 araddr [14] "logic araddr[15:0]" +Toggle 0to1 araddr [15] "logic araddr[15:0]" +Toggle 1to0 araddr [15] "logic araddr[15:0]" +Toggle 0to1 awaddr [0] "logic awaddr[15:0]" +Toggle 1to0 awaddr [0] "logic awaddr[15:0]" +Toggle 0to1 awaddr [1] "logic awaddr[15:0]" +Toggle 1to0 awaddr [1] "logic awaddr[15:0]" +Toggle 0to1 awaddr [4] "logic awaddr[15:0]" +Toggle 1to0 awaddr [4] "logic awaddr[15:0]" +Toggle 0to1 awaddr [5] "logic awaddr[15:0]" +Toggle 1to0 awaddr [5] "logic awaddr[15:0]" +Toggle 0to1 awaddr [8] "logic awaddr[15:0]" +Toggle 1to0 awaddr [8] "logic awaddr[15:0]" +Toggle 0to1 awaddr [9] "logic awaddr[15:0]" +Toggle 1to0 awaddr [9] "logic awaddr[15:0]" +Toggle 0to1 awaddr [11] "logic awaddr[15:0]" +Toggle 1to0 awaddr [11] "logic awaddr[15:0]" +Toggle 0to1 awaddr [12] "logic awaddr[15:0]" +Toggle 1to0 awaddr [12] "logic awaddr[15:0]" +Toggle 0to1 awaddr [14] "logic awaddr[15:0]" +Toggle 1to0 awaddr [14] "logic awaddr[15:0]" +Toggle 0to1 awaddr [15] "logic awaddr[15:0]" +Toggle 1to0 awaddr [15] "logic awaddr[15:0]" +Toggle araddr "logic araddr[15:0]" +Toggle 0to1 rdata [63] "logic rdata[63:0]" +Toggle 1to0 rdata [63] "logic rdata[63:0]" +Toggle 0to1 rdata [8] "logic rdata[63:0]" +Toggle 1to0 rdata [8] "logic rdata[63:0]" +Toggle 0to1 rdata [14] "logic rdata[63:0]" +Toggle 1to0 rdata [14] "logic rdata[63:0]" +Toggle 0to1 rdata [17] "logic rdata[63:0]" +Toggle 1to0 rdata [17] "logic rdata[63:0]" +Toggle 0to1 rdata [20] "logic rdata[63:0]" +Toggle 1to0 rdata [20] "logic rdata[63:0]" +Toggle 0to1 rdata [22] "logic rdata[63:0]" +Toggle 1to0 rdata [22] "logic rdata[63:0]" +Toggle 0to1 rdata [24] "logic rdata[63:0]" +Toggle 1to0 rdata [24] "logic rdata[63:0]" +Toggle 0to1 rdata [29] "logic rdata[63:0]" +Toggle 1to0 rdata [29] "logic rdata[63:0]" +Toggle 0to1 rdata [32] "logic rdata[63:0]" +Toggle 1to0 rdata [32] "logic rdata[63:0]" +Toggle 0to1 rdata [34] "logic rdata[63:0]" +Toggle 1to0 rdata [34] "logic rdata[63:0]" +Toggle 0to1 rdata [35] "logic rdata[63:0]" +Toggle 1to0 rdata [35] "logic rdata[63:0]" +Toggle 0to1 rdata [36] "logic rdata[63:0]" +Toggle 1to0 rdata [36] "logic rdata[63:0]" +Toggle 0to1 rdata [37] "logic rdata[63:0]" +Toggle 1to0 rdata [37] "logic rdata[63:0]" +Toggle 0to1 rdata [38] "logic rdata[63:0]" +Toggle 1to0 rdata [38] "logic rdata[63:0]" +Toggle 0to1 rdata [39] "logic rdata[63:0]" +Toggle 1to0 rdata [39] "logic rdata[63:0]" +Toggle 0to1 rdata [40] "logic rdata[63:0]" +Toggle 1to0 rdata [40] "logic rdata[63:0]" +Toggle 0to1 rdata [41] "logic rdata[63:0]" +Toggle 1to0 rdata [41] "logic rdata[63:0]" +Toggle 0to1 rdata [42] "logic rdata[63:0]" +Toggle 1to0 rdata [42] "logic rdata[63:0]" +Toggle 0to1 rdata [43] "logic rdata[63:0]" +Toggle 1to0 rdata [43] "logic rdata[63:0]" +Toggle 0to1 rdata [44] "logic rdata[63:0]" +Toggle 1to0 rdata [44] "logic rdata[63:0]" +Toggle 0to1 rdata [45] "logic rdata[63:0]" +Toggle 1to0 rdata [45] "logic rdata[63:0]" +Toggle 0to1 rdata [46] "logic rdata[63:0]" +Toggle 1to0 rdata [46] "logic rdata[63:0]" +Toggle 0to1 rdata [47] "logic rdata[63:0]" +Toggle 1to0 rdata [47] "logic rdata[63:0]" +Toggle 0to1 rdata [48] "logic rdata[63:0]" +Toggle 1to0 rdata [48] "logic rdata[63:0]" +Toggle 0to1 rdata [49] "logic rdata[63:0]" +Toggle 1to0 rdata [49] "logic rdata[63:0]" +Toggle 0to1 rdata [50] "logic rdata[63:0]" +Toggle 1to0 rdata [50] "logic rdata[63:0]" +Toggle 0to1 rdata [51] "logic rdata[63:0]" +Toggle 1to0 rdata [51] "logic rdata[63:0]" +Toggle 0to1 rdata [52] "logic rdata[63:0]" +Toggle 1to0 rdata [52] "logic rdata[63:0]" +Toggle 0to1 rdata [53] "logic rdata[63:0]" +Toggle 1to0 rdata [53] "logic rdata[63:0]" +Toggle 0to1 rdata [54] "logic rdata[63:0]" +Toggle 1to0 rdata [54] "logic rdata[63:0]" +Toggle 0to1 rdata [55] "logic rdata[63:0]" +Toggle 1to0 rdata [55] "logic rdata[63:0]" +Toggle 0to1 rdata [56] "logic rdata[63:0]" +Toggle 1to0 rdata [56] "logic rdata[63:0]" +Toggle 0to1 rdata [57] "logic rdata[63:0]" +Toggle 1to0 rdata [57] "logic rdata[63:0]" +Toggle 0to1 rdata [58] "logic rdata[63:0]" +Toggle 1to0 rdata [58] "logic rdata[63:0]" +Toggle 0to1 rdata [59] "logic rdata[63:0]" +Toggle 1to0 rdata [59] "logic rdata[63:0]" +Toggle 0to1 rdata [62] "logic rdata[63:0]" +Toggle 1to0 rdata [62] "logic rdata[63:0]" +ANNOTATION: " Address ranges ,data ranges not possible to access, bresp/rresp excluded " +Toggle bresp "logic bresp[1:0]" +Toggle 0to1 awprot [2] "logic awprot[2:0]" +Toggle 1to0 awprot [2] "logic awprot[2:0]" +Toggle 0to1 awprot [1] "logic awprot[2:0]" +Toggle 1to0 awprot [1] "logic awprot[2:0]" +Toggle 0to1 arprot [2] "logic arprot[2:0]" +Toggle 1to0 arprot [2] "logic arprot[2:0]" +Toggle 0to1 arprot [1] "logic arprot[2:0]" +Toggle 1to0 arprot [1] "logic arprot[2:0]" +CHECKSUM: "869564193 23825937" +INSTANCE: tb_top.DUT.bpf_pcie_slv_if +Toggle 0to1 awaddr [1] "logic awaddr[15:0]" +Toggle 1to0 awaddr [1] "logic awaddr[15:0]" +Toggle 0to1 awaddr [0] "logic awaddr[15:0]" +Toggle 1to0 awaddr [0] "logic awaddr[15:0]" +Toggle 0to1 araddr [1] "logic araddr[15:0]" +Toggle 1to0 araddr [1] "logic araddr[15:0]" +Toggle 0to1 araddr [0] "logic araddr[15:0]" +Toggle 1to0 araddr [0] "logic araddr[15:0]" +Toggle rresp "logic rresp[1:0]" +CHECKSUM: "869564193 1260913042" +INSTANCE: tb_top.DUT.bpf_apf_slv_if +Toggle 0to1 awprot [2] "logic awprot[2:0]" +Toggle 1to0 awprot [2] "logic awprot[2:0]" +Toggle 0to1 awprot [0] "logic awprot[2:0]" +Toggle 1to0 awprot [0] "logic awprot[2:0]" +Toggle 0to1 araddr [19] "logic araddr[19:0]" +Toggle 1to0 araddr [19] "logic araddr[19:0]" +Toggle 0to1 araddr [0] "logic araddr[19:0]" +Toggle 1to0 araddr [0] "logic araddr[19:0]" +Toggle 0to1 araddr [1] "logic araddr[19:0]" +Toggle 1to0 araddr [1] "logic araddr[19:0]" +Toggle 0to1 araddr [2] "logic araddr[19:0]" +Toggle 1to0 araddr [2] "logic araddr[19:0]" +Toggle 0to1 araddr [3] "logic araddr[19:0]" +Toggle 1to0 araddr [3] "logic araddr[19:0]" +Toggle 0to1 araddr [4] "logic araddr[19:0]" +Toggle 1to0 araddr [4] "logic araddr[19:0]" +Toggle 0to1 araddr [5] "logic araddr[19:0]" +Toggle 1to0 araddr [5] "logic araddr[19:0]" +Toggle 0to1 araddr [6] "logic araddr[19:0]" +Toggle 1to0 araddr [6] "logic araddr[19:0]" +Toggle 0to1 araddr [7] "logic araddr[19:0]" +Toggle 1to0 araddr [7] "logic araddr[19:0]" +Toggle 0to1 araddr [8] "logic araddr[19:0]" +Toggle 1to0 araddr [8] "logic araddr[19:0]" +Toggle 0to1 araddr [9] "logic araddr[19:0]" +Toggle 1to0 araddr [9] "logic araddr[19:0]" +Toggle 0to1 araddr [10] "logic araddr[19:0]" +Toggle 1to0 araddr [10] "logic araddr[19:0]" +Toggle 0to1 araddr [11] "logic araddr[19:0]" +Toggle 1to0 araddr [11] "logic araddr[19:0]" +Toggle 0to1 araddr [12] "logic araddr[19:0]" +Toggle 1to0 araddr [12] "logic araddr[19:0]" +Toggle 0to1 araddr [14] "logic araddr[19:0]" +Toggle 1to0 araddr [14] "logic araddr[19:0]" +Toggle 0to1 araddr [15] "logic araddr[19:0]" +Toggle 1to0 araddr [15] "logic araddr[19:0]" +Toggle 0to1 araddr [16] "logic araddr[19:0]" +Toggle 1to0 araddr [16] "logic araddr[19:0]" +Toggle 0to1 araddr [17] "logic araddr[19:0]" +Toggle 1to0 araddr [17] "logic araddr[19:0]" +Toggle 0to1 awaddr [17] "logic awaddr[19:0]" +Toggle 1to0 awaddr [17] "logic awaddr[19:0]" +Toggle 0to1 awaddr [0] "logic awaddr[19:0]" +Toggle 1to0 awaddr [0] "logic awaddr[19:0]" +Toggle 0to1 awaddr [1] "logic awaddr[19:0]" +Toggle 1to0 awaddr [1] "logic awaddr[19:0]" +Toggle 0to1 awaddr [2] "logic awaddr[19:0]" +Toggle 1to0 awaddr [2] "logic awaddr[19:0]" +Toggle 0to1 awaddr [5] "logic awaddr[19:0]" +Toggle 1to0 awaddr [5] "logic awaddr[19:0]" +Toggle 0to1 awaddr [6] "logic awaddr[19:0]" +Toggle 1to0 awaddr [6] "logic awaddr[19:0]" +Toggle 0to1 awaddr [7] "logic awaddr[19:0]" +Toggle 1to0 awaddr [7] "logic awaddr[19:0]" +Toggle 0to1 awaddr [8] "logic awaddr[19:0]" +Toggle 1to0 awaddr [8] "logic awaddr[19:0]" +Toggle 0to1 awaddr [9] "logic awaddr[19:0]" +Toggle 1to0 awaddr [9] "logic awaddr[19:0]" +Toggle 0to1 awaddr [10] "logic awaddr[19:0]" +Toggle 1to0 awaddr [10] "logic awaddr[19:0]" +Toggle 0to1 awaddr [11] "logic awaddr[19:0]" +Toggle 1to0 awaddr [11] "logic awaddr[19:0]" +Toggle 0to1 awaddr [12] "logic awaddr[19:0]" +Toggle 1to0 awaddr [12] "logic awaddr[19:0]" +Toggle 0to1 awaddr [14] "logic awaddr[19:0]" +Toggle 1to0 awaddr [14] "logic awaddr[19:0]" +Toggle 0to1 awaddr [15] "logic awaddr[19:0]" +Toggle 1to0 awaddr [15] "logic awaddr[19:0]" +Toggle 0to1 awaddr [16] "logic awaddr[19:0]" +Toggle 1to0 awaddr [16] "logic awaddr[19:0]" +ANNOTATION: " Connected to bpf_fme_mst_if and bpf_pmci_lpbk_mst_if. Excluding unused address and data fields Address ranges ,data ranges not possible to access,bresp/rresp excluded. " +Toggle bresp "logic bresp[1:0]" +Toggle rresp "logic rresp[1:0]" +ANNOTATION: " Connected to bpf_fme_mst_if and bpf_pmci_lpbk_mst_if. Excluding unused address and data fields Address ranges ,data ranges not possible to access,bresp/rresp excluded. " +Toggle rdata "logic rdata[63:0]" +Toggle 0to1 arprot [2] "logic arprot[2:0]" +Toggle 1to0 arprot [2] "logic arprot[2:0]" +Toggle 0to1 arprot [0] "logic arprot[2:0]" +Toggle 1to0 arprot [0] "logic arprot[2:0]" +CHECKSUM: "869564193 1260913042" +INSTANCE: tb_top.DUT.bpf_fme_mst_if +ANNOTATION: " Connected to pfa_master in fme_top where address,writedata and write hardcoded to specific value . (read tied to 0 , readata left floating).Connected to pfa_master in fme_top where it?s hardcoded ( address,writedata,read,readata unconnected). " +Toggle arprot "logic arprot[2:0]" +ANNOTATION: " Connected to pfa_master in fme_top where address,writedata and write hardcoded to specific value . (read tied to 0 , readata left floating).Connected to pfa_master in fme_top where it?s hardcoded ( address,writedata,read,readata unconnected). " +Toggle awprot "logic awprot[2:0]" +ANNOTATION: " Connected to pfa_master in fme_top where address,writedata and write hardcoded to specific value . (read tied to 0 , readata left floating).Connected to pfa_master in fme_top where it?s hardcoded ( address,writedata,read,readata unconnected). " +Toggle rresp "logic rresp[1:0]" +Toggle 0to1 bready "logic bready" +Toggle 1to0 bready "logic bready" +Toggle 0to1 rready "logic rready" +Toggle 1to0 rready "logic rready" +Toggle 0to1 awaddr [18] "logic awaddr[19:0]" +Toggle 1to0 awaddr [18] "logic awaddr[19:0]" +Toggle 0to1 awaddr [0] "logic awaddr[19:0]" +Toggle 1to0 awaddr [0] "logic awaddr[19:0]" +Toggle 0to1 awaddr [1] "logic awaddr[19:0]" +Toggle 1to0 awaddr [1] "logic awaddr[19:0]" +Toggle 0to1 awaddr [2] "logic awaddr[19:0]" +Toggle 1to0 awaddr [2] "logic awaddr[19:0]" +Toggle 0to1 awaddr [3] "logic awaddr[19:0]" +Toggle 1to0 awaddr [3] "logic awaddr[19:0]" +Toggle 0to1 awaddr [5] "logic awaddr[19:0]" +Toggle 1to0 awaddr [5] "logic awaddr[19:0]" +Toggle 0to1 awaddr [6] "logic awaddr[19:0]" +Toggle 1to0 awaddr [6] "logic awaddr[19:0]" +Toggle 0to1 awaddr [7] "logic awaddr[19:0]" +Toggle 1to0 awaddr [7] "logic awaddr[19:0]" +Toggle 0to1 awaddr [8] "logic awaddr[19:0]" +Toggle 1to0 awaddr [8] "logic awaddr[19:0]" +Toggle 0to1 awaddr [9] "logic awaddr[19:0]" +Toggle 1to0 awaddr [9] "logic awaddr[19:0]" +Toggle 0to1 awaddr [10] "logic awaddr[19:0]" +Toggle 1to0 awaddr [10] "logic awaddr[19:0]" +Toggle 0to1 awaddr [11] "logic awaddr[19:0]" +Toggle 1to0 awaddr [11] "logic awaddr[19:0]" +Toggle 0to1 awaddr [12] "logic awaddr[19:0]" +Toggle 1to0 awaddr [12] "logic awaddr[19:0]" +Toggle 0to1 awaddr [13] "logic awaddr[19:0]" +Toggle 1to0 awaddr [13] "logic awaddr[19:0]" +Toggle 0to1 awaddr [14] "logic awaddr[19:0]" +Toggle 1to0 awaddr [14] "logic awaddr[19:0]" +Toggle 0to1 awaddr [15] "logic awaddr[19:0]" +Toggle 1to0 awaddr [15] "logic awaddr[19:0]" +Toggle 0to1 awaddr [16] "logic awaddr[19:0]" +Toggle 1to0 awaddr [16] "logic awaddr[19:0]" +Toggle 0to1 awaddr [17] "logic awaddr[19:0]" +Toggle 1to0 awaddr [17] "logic awaddr[19:0]" +Toggle 0to1 araddr [18] "logic araddr[19:0]" +Toggle 1to0 araddr [18] "logic araddr[19:0]" +Toggle 0to1 araddr [0] "logic araddr[19:0]" +Toggle 1to0 araddr [0] "logic araddr[19:0]" +Toggle 0to1 araddr [1] "logic araddr[19:0]" +Toggle 1to0 araddr [1] "logic araddr[19:0]" +Toggle 0to1 araddr [2] "logic araddr[19:0]" +Toggle 1to0 araddr [2] "logic araddr[19:0]" +Toggle 0to1 araddr [3] "logic araddr[19:0]" +Toggle 1to0 araddr [3] "logic araddr[19:0]" +Toggle 0to1 araddr [5] "logic araddr[19:0]" +Toggle 1to0 araddr [5] "logic araddr[19:0]" +Toggle 0to1 araddr [6] "logic araddr[19:0]" +Toggle 1to0 araddr [6] "logic araddr[19:0]" +Toggle 0to1 araddr [7] "logic araddr[19:0]" +Toggle 1to0 araddr [7] "logic araddr[19:0]" +Toggle 0to1 araddr [8] "logic araddr[19:0]" +Toggle 1to0 araddr [8] "logic araddr[19:0]" +Toggle 0to1 araddr [9] "logic araddr[19:0]" +Toggle 1to0 araddr [9] "logic araddr[19:0]" +Toggle 0to1 araddr [10] "logic araddr[19:0]" +Toggle 1to0 araddr [10] "logic araddr[19:0]" +Toggle 0to1 araddr [11] "logic araddr[19:0]" +Toggle 1to0 araddr [11] "logic araddr[19:0]" +Toggle 0to1 araddr [12] "logic araddr[19:0]" +Toggle 1to0 araddr [12] "logic araddr[19:0]" +Toggle 0to1 araddr [13] "logic araddr[19:0]" +Toggle 1to0 araddr [13] "logic araddr[19:0]" +Toggle 0to1 araddr [14] "logic araddr[19:0]" +Toggle 1to0 araddr [14] "logic araddr[19:0]" +Toggle 0to1 araddr [15] "logic araddr[19:0]" +Toggle 1to0 araddr [15] "logic araddr[19:0]" +Toggle 0to1 araddr [16] "logic araddr[19:0]" +Toggle 1to0 araddr [16] "logic araddr[19:0]" +Toggle 0to1 araddr [17] "logic araddr[19:0]" +Toggle 1to0 araddr [17] "logic araddr[19:0]" +Toggle 0to1 arready "logic arready" +Toggle 1to0 arready "logic arready" +Toggle 0to1 arvalid "logic arvalid" +Toggle 1to0 arvalid "logic arvalid" +ANNOTATION: " Connected to pfa_master in fme_top where address,writedata and write hardcoded to specific value . (read tied to 0 , readata left floating).Connected to pfa_master in fme_top where it?s hardcoded ( address,writedata,read,readata unconnected). " +Toggle rdata "logic rdata[63:0]" +Toggle 0to1 rvalid "logic rvalid" +Toggle 1to0 rvalid "logic rvalid" +Toggle 0to1 wdata [63] "logic wdata[63:0]" +Toggle 1to0 wdata [63] "logic wdata[63:0]" +Toggle 0to1 wdata [0] "logic wdata[63:0]" +Toggle 1to0 wdata [0] "logic wdata[63:0]" +Toggle 0to1 wdata [3] "logic wdata[63:0]" +Toggle 1to0 wdata [3] "logic wdata[63:0]" +Toggle 0to1 wdata [4] "logic wdata[63:0]" +Toggle 1to0 wdata [4] "logic wdata[63:0]" +Toggle 0to1 wdata [5] "logic wdata[63:0]" +Toggle 1to0 wdata [5] "logic wdata[63:0]" +Toggle 0to1 wdata [6] "logic wdata[63:0]" +Toggle 1to0 wdata [6] "logic wdata[63:0]" +Toggle 0to1 wdata [7] "logic wdata[63:0]" +Toggle 1to0 wdata [7] "logic wdata[63:0]" +Toggle 0to1 wdata [8] "logic wdata[63:0]" +Toggle 1to0 wdata [8] "logic wdata[63:0]" +Toggle 0to1 wdata [9] "logic wdata[63:0]" +Toggle 1to0 wdata [9] "logic wdata[63:0]" +Toggle 0to1 wdata [10] "logic wdata[63:0]" +Toggle 1to0 wdata [10] "logic wdata[63:0]" +Toggle 0to1 wdata [11] "logic wdata[63:0]" +Toggle 1to0 wdata [11] "logic wdata[63:0]" +Toggle 0to1 wdata [12] "logic wdata[63:0]" +Toggle 1to0 wdata [12] "logic wdata[63:0]" +Toggle 0to1 wdata [13] "logic wdata[63:0]" +Toggle 1to0 wdata [13] "logic wdata[63:0]" +Toggle 0to1 wdata [14] "logic wdata[63:0]" +Toggle 1to0 wdata [14] "logic wdata[63:0]" +Toggle 0to1 wdata [15] "logic wdata[63:0]" +Toggle 1to0 wdata [15] "logic wdata[63:0]" +Toggle 0to1 wdata [16] "logic wdata[63:0]" +Toggle 1to0 wdata [16] "logic wdata[63:0]" +Toggle 0to1 wdata [17] "logic wdata[63:0]" +Toggle 1to0 wdata [17] "logic wdata[63:0]" +Toggle 0to1 wdata [18] "logic wdata[63:0]" +Toggle 1to0 wdata [18] "logic wdata[63:0]" +Toggle 0to1 wdata [19] "logic wdata[63:0]" +Toggle 1to0 wdata [19] "logic wdata[63:0]" +Toggle 0to1 wdata [20] "logic wdata[63:0]" +Toggle 1to0 wdata [20] "logic wdata[63:0]" +Toggle 0to1 wdata [21] "logic wdata[63:0]" +Toggle 1to0 wdata [21] "logic wdata[63:0]" +Toggle 0to1 wdata [22] "logic wdata[63:0]" +Toggle 1to0 wdata [22] "logic wdata[63:0]" +Toggle 0to1 wdata [23] "logic wdata[63:0]" +Toggle 1to0 wdata [23] "logic wdata[63:0]" +Toggle 0to1 wdata [24] "logic wdata[63:0]" +Toggle 1to0 wdata [24] "logic wdata[63:0]" +Toggle 0to1 wdata [25] "logic wdata[63:0]" +Toggle 1to0 wdata [25] "logic wdata[63:0]" +Toggle 0to1 wdata [26] "logic wdata[63:0]" +Toggle 1to0 wdata [26] "logic wdata[63:0]" +Toggle 0to1 wdata [27] "logic wdata[63:0]" +Toggle 1to0 wdata [27] "logic wdata[63:0]" +Toggle 0to1 wdata [28] "logic wdata[63:0]" +Toggle 1to0 wdata [28] "logic wdata[63:0]" +Toggle 0to1 wdata [29] "logic wdata[63:0]" +Toggle 1to0 wdata [29] "logic wdata[63:0]" +Toggle 0to1 wdata [30] "logic wdata[63:0]" +Toggle 1to0 wdata [30] "logic wdata[63:0]" +Toggle 0to1 wdata [31] "logic wdata[63:0]" +Toggle 1to0 wdata [31] "logic wdata[63:0]" +Toggle 0to1 wdata [32] "logic wdata[63:0]" +Toggle 1to0 wdata [32] "logic wdata[63:0]" +Toggle 0to1 wdata [33] "logic wdata[63:0]" +Toggle 1to0 wdata [33] "logic wdata[63:0]" +Toggle 0to1 wdata [34] "logic wdata[63:0]" +Toggle 1to0 wdata [34] "logic wdata[63:0]" +Toggle 0to1 wdata [35] "logic wdata[63:0]" +Toggle 1to0 wdata [35] "logic wdata[63:0]" +Toggle 0to1 wdata [36] "logic wdata[63:0]" +Toggle 1to0 wdata [36] "logic wdata[63:0]" +Toggle 0to1 wdata [37] "logic wdata[63:0]" +Toggle 1to0 wdata [37] "logic wdata[63:0]" +Toggle 0to1 wdata [38] "logic wdata[63:0]" +Toggle 1to0 wdata [38] "logic wdata[63:0]" +Toggle 0to1 wdata [39] "logic wdata[63:0]" +Toggle 1to0 wdata [39] "logic wdata[63:0]" +Toggle 0to1 wdata [40] "logic wdata[63:0]" +Toggle 1to0 wdata [40] "logic wdata[63:0]" +Toggle 0to1 wdata [41] "logic wdata[63:0]" +Toggle 1to0 wdata [41] "logic wdata[63:0]" +Toggle 0to1 wdata [42] "logic wdata[63:0]" +Toggle 1to0 wdata [42] "logic wdata[63:0]" +Toggle 0to1 wdata [43] "logic wdata[63:0]" +Toggle 1to0 wdata [43] "logic wdata[63:0]" +Toggle 0to1 wdata [44] "logic wdata[63:0]" +Toggle 1to0 wdata [44] "logic wdata[63:0]" +Toggle 0to1 wdata [45] "logic wdata[63:0]" +Toggle 1to0 wdata [45] "logic wdata[63:0]" +Toggle 0to1 wdata [46] "logic wdata[63:0]" +Toggle 1to0 wdata [46] "logic wdata[63:0]" +Toggle 0to1 wdata [47] "logic wdata[63:0]" +Toggle 1to0 wdata [47] "logic wdata[63:0]" +Toggle 0to1 wdata [48] "logic wdata[63:0]" +Toggle 1to0 wdata [48] "logic wdata[63:0]" +Toggle 0to1 wdata [49] "logic wdata[63:0]" +Toggle 1to0 wdata [49] "logic wdata[63:0]" +Toggle 0to1 wdata [50] "logic wdata[63:0]" +Toggle 1to0 wdata [50] "logic wdata[63:0]" +Toggle 0to1 wdata [51] "logic wdata[63:0]" +Toggle 1to0 wdata [51] "logic wdata[63:0]" +Toggle 0to1 wdata [52] "logic wdata[63:0]" +Toggle 1to0 wdata [52] "logic wdata[63:0]" +Toggle 0to1 wdata [53] "logic wdata[63:0]" +Toggle 1to0 wdata [53] "logic wdata[63:0]" +Toggle 0to1 wdata [54] "logic wdata[63:0]" +Toggle 1to0 wdata [54] "logic wdata[63:0]" +Toggle 0to1 wdata [55] "logic wdata[63:0]" +Toggle 1to0 wdata [55] "logic wdata[63:0]" +Toggle 0to1 wdata [56] "logic wdata[63:0]" +Toggle 1to0 wdata [56] "logic wdata[63:0]" +Toggle 0to1 wdata [57] "logic wdata[63:0]" +Toggle 1to0 wdata [57] "logic wdata[63:0]" +Toggle 0to1 wdata [58] "logic wdata[63:0]" +Toggle 1to0 wdata [58] "logic wdata[63:0]" +Toggle 0to1 wdata [59] "logic wdata[63:0]" +Toggle 1to0 wdata [59] "logic wdata[63:0]" +Toggle 0to1 wdata [60] "logic wdata[63:0]" +Toggle 1to0 wdata [60] "logic wdata[63:0]" +Toggle 0to1 wdata [61] "logic wdata[63:0]" +Toggle 1to0 wdata [61] "logic wdata[63:0]" +Toggle 0to1 wdata [62] "logic wdata[63:0]" +Toggle 1to0 wdata [62] "logic wdata[63:0]" diff --git a/verification/coverage/local_commit.el b/verification/coverage/local_commit.el new file mode 100644 index 0000000..63367ea --- /dev/null +++ b/verification/coverage/local_commit.el @@ -0,0 +1,7215 @@ +//================================================== +// This file contains the Excluded objects +// Generated By User: ppawar2x +// Format Version: 2 +// Date: Fri Apr 8 05:25:19 2022 +// ExclMode: default +//================================================== +CHECKSUM: "1656915986 1606718296" +INSTANCE: tb_top.DUT.afu_top.local_commit +Condition 5 "1439598622" "(tx_is_dm ? rx_cmp_dm_hdr : rx_cmp_pu_hdr) 1 -1" (1 "0") +Condition 11 "2740418167" "(source.tready && commit_in_ready) 1 -1" (2 "10") +ANNOTATION: " treday is always 'h1 " +Condition 2 "4117776622" "(commit_in.tvalid && commit_in.tready) 1 -1" (2 "10") +Condition 12 "1762675126" "(sink.tvalid && commit_in_ready) 1 -1" (2 "10") +Condition 8 "1963954577" "(commit_in.tready || ((!rx_pending))) 1 -1" (1 "00") +CHECKSUM: "1259019545 3297052881" +INSTANCE: tb_top.DUT.afu_top.local_commit.commit_skid.r.axis_pl_stage[0].axis_reg_inst +Toggle s_tkeep "net s_tkeep[63:0]" +Toggle s_tuser "net s_tuser[9:0]" +Toggle s_tdest "net s_tdest[7:0]" +Toggle s_tid "net s_tid[7:0]" +Toggle 0to1 s_tdata [511] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [511] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [0] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [0] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [1] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [1] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [2] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [2] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [3] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [3] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [6] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [6] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [7] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [7] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [8] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [8] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [9] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [9] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [10] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [10] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [11] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [11] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [12] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [12] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [13] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [13] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [14] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [14] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [15] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [15] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [16] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [16] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [17] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [17] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [18] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [18] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [19] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [19] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [21] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [21] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [22] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [22] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [23] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [23] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [24] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [24] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [25] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [25] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [26] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [26] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [27] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [27] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [28] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [28] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [29] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [29] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [30] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [30] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [31] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [31] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [32] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [32] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [33] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [33] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [34] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [34] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [35] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [35] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [36] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [36] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [37] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [37] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [38] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [38] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [39] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [39] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [40] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [40] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [41] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [41] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [42] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [42] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [43] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [43] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [44] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [44] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [45] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [45] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [46] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [46] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [47] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [47] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [48] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [48] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [49] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [49] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [50] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [50] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [51] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [51] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [52] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [52] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [53] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [53] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [54] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [54] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [55] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [55] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [56] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [56] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [57] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [57] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [58] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [58] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [59] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [59] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [60] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [60] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [61] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [61] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [62] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [62] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [63] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [63] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [64] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [64] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [65] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [65] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [66] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [66] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [67] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [67] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [68] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [68] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [69] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [69] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [70] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [70] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [71] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [71] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [72] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [72] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [73] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [73] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [74] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [74] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [75] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [75] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [76] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [76] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [77] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [77] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [78] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [78] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [79] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [79] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [80] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [80] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [81] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [81] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [82] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [82] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [83] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [83] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [84] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [84] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [85] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [85] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [86] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [86] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [87] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [87] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [88] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [88] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [89] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [89] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [90] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [90] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [91] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [91] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [92] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [92] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [93] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [93] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [94] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [94] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [95] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [95] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [96] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [96] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [97] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [97] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [98] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [98] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [99] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [99] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [100] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [100] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [101] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [101] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [102] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [102] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [103] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [103] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [104] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [104] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [105] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [105] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [106] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [106] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [107] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [107] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [108] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [108] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [109] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [109] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [110] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [110] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [111] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [111] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [112] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [112] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [113] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [113] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [114] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [114] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [115] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [115] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [116] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [116] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [117] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [117] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [126] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [126] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [127] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [127] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [128] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [128] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [129] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [129] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [130] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [130] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [131] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [131] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [132] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [132] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [133] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [133] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [134] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [134] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [135] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [135] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [136] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [136] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [137] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [137] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [138] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [138] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [139] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [139] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [140] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [140] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [141] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [141] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [142] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [142] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [143] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [143] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [144] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [144] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [145] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [145] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [146] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [146] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [147] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [147] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [148] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [148] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [149] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [149] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [150] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [150] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [151] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [151] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [152] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [152] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [153] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [153] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [154] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [154] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [155] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [155] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [156] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [156] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [157] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [157] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [158] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [158] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [159] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [159] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [160] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [160] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [162] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [162] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [163] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [163] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [164] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [164] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [165] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [165] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [166] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [166] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [167] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [167] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [168] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [168] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [169] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [169] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [170] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [170] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [171] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [171] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [172] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [172] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [173] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [173] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [175] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [175] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [176] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [176] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [177] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [177] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [178] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [178] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [179] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [179] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [180] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [180] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [181] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [181] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [182] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [182] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [183] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [183] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [184] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [184] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [185] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [185] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [186] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [186] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [187] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [187] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [188] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [188] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [189] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [189] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [190] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [190] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [191] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [191] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [192] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [192] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [193] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [193] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [194] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [194] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [195] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [195] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [196] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [196] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [197] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [197] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [198] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [198] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [199] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [199] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [200] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [200] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [201] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [201] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [202] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [202] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [203] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [203] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [204] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [204] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [205] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [205] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [206] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [206] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [207] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [207] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [208] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [208] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [209] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [209] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [210] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [210] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [211] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [211] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [212] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [212] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [213] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [213] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [214] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [214] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [215] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [215] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [216] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [216] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [217] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [217] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [218] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [218] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [219] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [219] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [220] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [220] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [221] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [221] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [222] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [222] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [223] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [223] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [226] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [226] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [227] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [227] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [228] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [228] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [229] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [229] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [230] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [230] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [231] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [231] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [232] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [232] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [233] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [233] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [234] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [234] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [235] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [235] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [236] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [236] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [237] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [237] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [238] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [238] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [239] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [239] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [240] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [240] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [241] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [241] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [242] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [242] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [243] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [243] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [244] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [244] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [245] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [245] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [246] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [246] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [247] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [247] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [248] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [248] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [249] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [249] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [250] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [250] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [251] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [251] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [252] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [252] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [253] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [253] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [254] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [254] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [255] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [255] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [256] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [256] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [257] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [257] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [258] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [258] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [259] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [259] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [260] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [260] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [261] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [261] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [262] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [262] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [263] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [263] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [264] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [264] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [265] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [265] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [266] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [266] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [267] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [267] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [268] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [268] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [269] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [269] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [270] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [270] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [271] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [271] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [272] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [272] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [273] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [273] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [274] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [274] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [275] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [275] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [276] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [276] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [277] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [277] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [278] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [278] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [279] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [279] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [280] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [280] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [281] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [281] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [282] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [282] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [283] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [283] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [284] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [284] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [285] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [285] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [286] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [286] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [287] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [287] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [288] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [288] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [289] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [289] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [290] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [290] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [291] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [291] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [292] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [292] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [293] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [293] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [294] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [294] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [295] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [295] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [296] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [296] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [297] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [297] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [298] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [298] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [299] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [299] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [300] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [300] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [301] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [301] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [302] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [302] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [303] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [303] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [304] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [304] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [305] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [305] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [306] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [306] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [307] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [307] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [308] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [308] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [309] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [309] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [310] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [310] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [311] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [311] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [312] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [312] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [313] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [313] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [314] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [314] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [315] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [315] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [316] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [316] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [317] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [317] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [318] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [318] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [319] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [319] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [320] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [320] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [321] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [321] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [322] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [322] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [323] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [323] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [324] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [324] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [325] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [325] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [326] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [326] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [327] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [327] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [328] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [328] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [329] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [329] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [330] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [330] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [331] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [331] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [332] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [332] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [333] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [333] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [334] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [334] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [335] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [335] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [336] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [336] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [337] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [337] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [338] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [338] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [339] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [339] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [340] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [340] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [341] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [341] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [342] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [342] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [343] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [343] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [344] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [344] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [345] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [345] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [346] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [346] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [347] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [347] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [348] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [348] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [349] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [349] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [350] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [350] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [351] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [351] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [352] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [352] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [353] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [353] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [354] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [354] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [355] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [355] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [356] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [356] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [357] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [357] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [358] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [358] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [359] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [359] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [360] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [360] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [361] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [361] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [362] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [362] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [363] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [363] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [364] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [364] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [365] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [365] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [366] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [366] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [367] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [367] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [368] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [368] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [369] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [369] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [370] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [370] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [371] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [371] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [372] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [372] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [373] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [373] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [374] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [374] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [375] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [375] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [376] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [376] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [377] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [377] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [378] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [378] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [379] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [379] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [380] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [380] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [381] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [381] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [382] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [382] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [383] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [383] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [384] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [384] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [385] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [385] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [386] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [386] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [387] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [387] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [388] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [388] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [389] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [389] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [390] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [390] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [391] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [391] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [392] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [392] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [393] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [393] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [394] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [394] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [395] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [395] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [396] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [396] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [397] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [397] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [398] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [398] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [399] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [399] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [400] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [400] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [401] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [401] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [402] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [402] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [403] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [403] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [404] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [404] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [405] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [405] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [406] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [406] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [407] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [407] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [408] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [408] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [409] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [409] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [410] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [410] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [411] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [411] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [412] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [412] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [413] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [413] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [414] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [414] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [415] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [415] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [416] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [416] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [417] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [417] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [418] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [418] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [419] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [419] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [420] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [420] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [421] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [421] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [422] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [422] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [423] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [423] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [424] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [424] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [425] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [425] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [426] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [426] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [427] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [427] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [428] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [428] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [429] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [429] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [430] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [430] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [431] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [431] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [432] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [432] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [433] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [433] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [434] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [434] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [435] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [435] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [436] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [436] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [437] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [437] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [438] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [438] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [439] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [439] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [440] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [440] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [441] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [441] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [442] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [442] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [443] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [443] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [444] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [444] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [445] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [445] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [446] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [446] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [447] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [447] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [448] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [448] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [449] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [449] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [450] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [450] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [451] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [451] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [452] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [452] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [453] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [453] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [454] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [454] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [455] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [455] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [456] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [456] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [457] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [457] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [458] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [458] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [459] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [459] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [460] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [460] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [461] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [461] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [462] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [462] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [463] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [463] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [464] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [464] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [465] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [465] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [466] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [466] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [467] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [467] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [468] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [468] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [469] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [469] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [470] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [470] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [471] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [471] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [472] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [472] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [473] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [473] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [474] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [474] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [475] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [475] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [476] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [476] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [477] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [477] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [478] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [478] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [479] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [479] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [480] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [480] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [481] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [481] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [482] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [482] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [483] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [483] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [484] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [484] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [485] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [485] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [486] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [486] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [487] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [487] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [488] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [488] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [489] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [489] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [490] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [490] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [491] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [491] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [492] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [492] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [493] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [493] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [494] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [494] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [495] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [495] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [496] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [496] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [497] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [497] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [498] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [498] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [499] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [499] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [500] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [500] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [501] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [501] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [502] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [502] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [503] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [503] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [504] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [504] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [505] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [505] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [506] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [506] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [507] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [507] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [508] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [508] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [509] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [509] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [510] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [510] "net s_tdata[511:0]" +Toggle 0to1 s_tlast "net s_tlast" +Toggle 1to0 s_tlast "net s_tlast" +Toggle m_tdest "net m_tdest[7:0]" +Toggle m_tuser "net m_tuser[9:0]" +Toggle 0to1 m_tready "net m_tready" +Toggle 1to0 m_tready "net m_tready" +Toggle 0to1 m_tlast "net m_tlast" +Toggle 1to0 m_tlast "net m_tlast" +Toggle m_tkeep "net m_tkeep[63:0]" +Toggle m_tid "net m_tid[7:0]" +Toggle 0to1 m_tdata [511] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [511] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [0] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [0] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [1] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [1] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [2] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [2] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [3] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [3] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [6] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [6] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [7] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [7] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [8] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [8] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [9] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [9] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [10] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [10] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [11] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [11] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [12] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [12] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [13] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [13] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [14] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [14] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [15] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [15] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [16] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [16] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [17] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [17] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [18] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [18] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [19] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [19] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [21] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [21] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [22] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [22] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [23] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [23] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [24] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [24] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [25] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [25] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [26] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [26] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [27] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [27] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [28] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [28] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [29] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [29] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [30] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [30] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [31] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [31] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [32] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [32] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [33] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [33] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [34] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [34] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [35] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [35] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [36] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [36] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [37] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [37] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [38] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [38] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [39] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [39] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [40] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [40] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [41] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [41] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [42] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [42] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [43] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [43] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [44] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [44] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [45] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [45] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [46] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [46] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [47] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [47] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [48] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [48] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [49] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [49] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [50] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [50] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [51] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [51] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [52] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [52] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [53] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [53] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [54] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [54] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [55] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [55] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [56] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [56] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [57] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [57] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [58] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [58] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [59] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [59] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [60] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [60] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [61] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [61] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [62] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [62] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [63] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [63] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [64] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [64] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [65] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [65] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [66] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [66] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [67] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [67] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [68] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [68] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [69] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [69] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [70] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [70] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [71] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [71] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [72] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [72] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [73] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [73] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [74] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [74] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [75] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [75] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [76] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [76] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [77] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [77] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [78] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [78] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [79] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [79] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [80] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [80] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [81] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [81] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [82] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [82] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [83] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [83] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [84] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [84] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [85] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [85] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [86] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [86] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [87] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [87] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [88] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [88] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [89] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [89] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [90] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [90] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [91] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [91] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [92] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [92] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [93] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [93] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [94] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [94] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [95] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [95] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [96] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [96] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [97] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [97] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [98] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [98] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [99] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [99] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [100] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [100] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [101] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [101] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [102] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [102] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [103] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [103] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [104] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [104] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [105] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [105] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [106] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [106] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [107] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [107] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [108] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [108] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [109] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [109] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [110] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [110] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [111] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [111] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [112] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [112] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [113] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [113] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [114] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [114] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [115] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [115] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [116] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [116] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [117] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [117] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [126] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [126] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [127] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [127] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [128] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [128] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [129] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [129] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [130] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [130] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [131] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [131] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [132] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [132] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [133] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [133] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [134] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [134] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [135] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [135] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [136] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [136] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [137] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [137] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [138] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [138] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [139] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [139] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [140] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [140] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [141] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [141] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [142] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [142] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [143] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [143] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [144] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [144] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [145] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [145] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [146] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [146] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [147] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [147] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [148] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [148] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [149] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [149] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [150] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [150] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [151] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [151] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [152] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [152] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [153] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [153] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [154] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [154] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [155] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [155] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [156] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [156] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [157] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [157] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [158] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [158] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [159] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [159] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [160] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [160] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [162] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [162] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [163] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [163] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [164] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [164] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [165] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [165] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [166] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [166] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [167] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [167] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [168] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [168] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [169] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [169] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [170] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [170] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [171] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [171] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [172] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [172] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [173] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [173] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [175] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [175] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [176] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [176] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [177] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [177] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [178] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [178] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [179] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [179] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [180] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [180] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [181] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [181] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [182] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [182] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [183] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [183] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [184] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [184] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [185] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [185] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [186] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [186] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [187] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [187] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [188] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [188] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [189] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [189] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [190] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [190] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [191] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [191] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [192] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [192] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [193] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [193] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [194] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [194] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [195] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [195] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [196] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [196] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [197] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [197] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [198] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [198] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [199] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [199] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [200] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [200] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [201] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [201] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [202] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [202] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [203] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [203] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [204] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [204] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [205] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [205] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [206] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [206] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [207] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [207] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [208] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [208] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [209] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [209] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [210] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [210] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [211] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [211] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [212] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [212] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [213] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [213] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [214] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [214] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [215] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [215] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [216] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [216] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [217] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [217] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [218] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [218] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [219] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [219] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [220] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [220] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [221] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [221] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [222] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [222] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [223] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [223] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [226] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [226] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [227] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [227] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [228] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [228] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [229] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [229] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [230] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [230] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [231] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [231] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [232] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [232] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [233] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [233] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [234] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [234] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [235] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [235] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [236] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [236] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [237] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [237] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [238] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [238] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [239] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [239] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [240] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [240] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [241] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [241] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [242] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [242] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [243] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [243] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [244] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [244] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [245] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [245] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [246] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [246] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [247] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [247] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [248] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [248] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [249] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [249] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [250] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [250] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [251] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [251] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [252] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [252] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [253] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [253] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [254] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [254] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [255] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [255] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [256] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [256] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [257] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [257] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [258] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [258] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [259] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [259] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [260] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [260] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [261] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [261] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [262] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [262] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [263] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [263] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [264] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [264] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [265] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [265] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [266] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [266] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [267] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [267] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [268] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [268] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [269] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [269] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [270] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [270] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [271] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [271] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [272] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [272] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [273] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [273] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [274] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [274] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [275] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [275] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [276] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [276] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [277] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [277] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [278] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [278] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [279] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [279] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [280] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [280] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [281] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [281] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [282] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [282] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [283] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [283] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [284] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [284] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [285] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [285] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [286] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [286] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [287] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [287] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [288] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [288] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [289] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [289] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [290] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [290] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [291] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [291] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [292] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [292] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [293] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [293] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [294] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [294] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [295] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [295] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [296] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [296] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [297] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [297] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [298] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [298] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [299] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [299] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [300] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [300] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [301] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [301] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [302] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [302] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [303] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [303] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [304] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [304] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [305] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [305] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [306] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [306] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [307] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [307] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [308] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [308] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [309] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [309] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [310] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [310] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [311] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [311] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [312] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [312] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [313] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [313] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [314] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [314] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [315] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [315] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [316] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [316] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [317] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [317] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [318] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [318] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [319] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [319] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [320] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [320] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [321] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [321] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [322] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [322] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [323] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [323] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [324] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [324] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [325] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [325] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [326] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [326] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [327] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [327] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [328] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [328] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [329] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [329] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [330] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [330] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [331] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [331] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [332] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [332] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [333] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [333] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [334] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [334] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [335] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [335] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [336] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [336] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [337] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [337] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [338] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [338] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [339] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [339] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [340] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [340] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [341] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [341] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [342] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [342] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [343] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [343] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [344] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [344] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [345] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [345] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [346] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [346] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [347] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [347] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [348] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [348] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [349] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [349] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [350] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [350] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [351] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [351] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [352] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [352] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [353] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [353] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [354] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [354] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [355] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [355] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [356] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [356] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [357] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [357] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [358] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [358] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [359] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [359] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [360] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [360] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [361] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [361] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [362] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [362] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [363] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [363] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [364] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [364] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [365] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [365] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [366] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [366] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [367] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [367] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [368] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [368] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [369] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [369] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [370] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [370] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [371] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [371] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [372] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [372] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [373] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [373] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [374] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [374] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [375] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [375] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [376] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [376] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [377] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [377] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [378] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [378] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [379] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [379] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [380] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [380] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [381] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [381] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [382] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [382] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [383] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [383] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [384] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [384] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [385] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [385] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [386] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [386] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [387] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [387] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [388] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [388] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [389] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [389] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [390] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [390] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [391] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [391] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [392] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [392] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [393] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [393] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [394] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [394] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [395] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [395] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [396] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [396] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [397] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [397] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [398] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [398] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [399] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [399] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [400] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [400] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [401] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [401] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [402] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [402] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [403] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [403] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [404] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [404] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [405] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [405] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [406] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [406] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [407] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [407] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [408] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [408] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [409] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [409] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [410] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [410] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [411] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [411] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [412] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [412] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [413] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [413] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [414] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [414] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [415] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [415] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [416] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [416] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [417] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [417] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [418] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [418] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [419] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [419] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [420] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [420] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [421] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [421] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [422] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [422] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [423] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [423] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [424] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [424] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [425] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [425] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [426] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [426] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [427] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [427] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [428] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [428] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [429] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [429] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [430] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [430] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [431] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [431] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [432] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [432] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [433] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [433] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [434] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [434] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [435] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [435] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [436] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [436] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [437] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [437] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [438] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [438] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [439] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [439] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [440] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [440] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [441] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [441] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [442] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [442] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [443] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [443] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [444] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [444] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [445] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [445] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [446] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [446] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [447] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [447] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [448] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [448] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [449] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [449] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [450] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [450] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [451] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [451] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [452] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [452] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [453] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [453] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [454] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [454] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [455] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [455] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [456] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [456] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [457] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [457] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [458] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [458] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [459] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [459] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [460] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [460] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [461] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [461] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [462] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [462] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [463] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [463] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [464] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [464] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [465] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [465] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [466] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [466] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [467] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [467] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [468] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [468] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [469] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [469] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [470] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [470] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [471] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [471] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [472] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [472] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [473] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [473] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [474] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [474] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [475] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [475] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [476] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [476] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [477] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [477] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [478] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [478] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [479] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [479] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [480] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [480] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [481] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [481] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [482] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [482] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [483] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [483] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [484] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [484] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [485] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [485] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [486] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [486] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [487] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [487] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [488] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [488] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [489] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [489] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [490] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [490] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [491] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [491] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [492] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [492] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [493] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [493] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [494] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [494] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [495] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [495] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [496] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [496] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [497] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [497] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [498] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [498] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [499] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [499] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [500] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [500] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [501] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [501] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [502] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [502] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [503] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [503] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [504] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [504] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [505] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [505] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [506] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [506] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [507] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [507] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [508] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [508] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [509] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [509] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [510] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [510] "net m_tdata[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [511] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [511] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [0] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [0] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [1] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [1] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [2] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [2] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [3] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [3] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [6] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [6] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [7] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [7] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [8] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [8] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [9] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [9] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [10] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [10] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [11] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [11] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [12] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [12] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [13] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [13] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [14] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [14] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [15] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [15] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [16] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [16] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [17] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [17] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [18] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [18] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [19] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [19] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [21] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [21] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [22] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [22] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [23] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [23] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [24] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [24] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [25] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [25] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [26] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [26] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [27] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [27] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [28] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [28] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [29] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [29] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [30] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [30] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [31] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [31] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [32] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [32] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [33] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [33] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [34] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [34] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [35] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [35] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [36] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [36] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [37] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [37] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [38] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [38] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [39] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [39] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [40] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [40] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [41] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [41] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [42] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [42] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [43] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [43] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [44] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [44] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [45] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [45] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [46] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [46] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [47] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [47] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [48] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [48] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [49] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [49] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [50] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [50] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [51] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [51] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [52] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [52] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [53] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [53] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [54] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [54] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [55] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [55] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [56] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [56] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [57] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [57] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [58] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [58] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [59] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [59] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [60] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [60] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [61] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [61] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [62] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [62] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [63] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [63] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [64] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [64] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [65] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [65] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [66] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [66] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [67] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [67] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [68] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [68] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [69] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [69] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [70] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [70] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [71] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [71] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [72] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [72] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [73] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [73] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [74] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [74] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [75] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [75] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [76] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [76] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [77] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [77] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [78] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [78] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [79] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [79] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [80] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [80] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [81] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [81] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [82] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [82] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [83] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [83] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [84] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [84] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [85] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [85] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [86] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [86] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [87] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [87] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [88] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [88] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [89] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [89] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [90] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [90] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [91] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [91] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [92] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [92] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [93] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [93] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [94] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [94] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [95] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [95] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [96] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [96] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [97] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [97] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [98] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [98] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [99] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [99] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [100] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [100] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [101] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [101] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [102] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [102] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [103] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [103] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [104] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [104] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [105] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [105] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [106] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [106] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [107] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [107] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [108] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [108] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [109] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [109] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [110] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [110] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [111] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [111] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [112] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [112] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [113] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [113] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [114] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [114] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [115] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [115] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [116] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [116] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [117] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [117] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [126] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [126] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [127] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [127] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [128] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [128] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [129] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [129] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [130] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [130] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [131] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [131] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [132] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [132] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [133] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [133] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [134] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [134] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [135] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [135] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [136] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [136] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [137] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [137] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [138] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [138] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [139] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [139] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [140] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [140] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [141] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [141] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [142] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [142] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [143] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [143] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [144] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [144] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [145] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [145] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [146] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [146] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [147] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [147] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [148] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [148] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [149] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [149] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [150] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [150] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [151] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [151] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [152] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [152] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [153] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [153] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [154] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [154] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [155] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [155] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [156] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [156] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [157] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [157] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [158] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [158] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [159] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [159] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [160] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [160] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [162] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [162] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [163] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [163] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [164] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [164] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [165] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [165] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [166] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [166] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [167] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [167] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [168] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [168] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [169] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [169] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [170] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [170] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [171] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [171] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [172] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [172] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [173] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [173] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [175] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [175] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [176] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [176] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [177] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [177] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [178] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [178] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [179] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [179] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [180] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [180] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [181] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [181] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [182] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [182] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [183] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [183] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [184] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [184] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [185] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [185] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [186] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [186] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [187] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [187] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [188] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [188] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [189] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [189] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [190] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [190] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [191] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [191] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [192] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [192] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [193] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [193] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [194] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [194] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [195] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [195] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [196] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [196] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [197] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [197] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [198] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [198] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [199] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [199] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [200] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [200] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [201] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [201] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [202] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [202] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [203] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [203] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [204] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [204] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [205] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [205] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [206] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [206] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [207] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [207] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [208] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [208] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [209] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [209] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [210] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [210] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [211] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [211] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [212] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [212] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [213] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [213] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [214] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [214] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [215] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [215] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [216] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [216] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [217] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [217] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [218] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [218] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [219] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [219] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [220] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [220] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [221] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [221] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [222] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [222] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [223] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [223] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [226] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [226] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [227] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [227] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [228] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [228] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [229] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [229] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [230] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [230] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [231] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [231] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [232] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [232] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [233] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [233] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [234] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [234] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [235] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [235] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [236] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [236] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [237] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [237] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [238] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [238] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [239] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [239] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [240] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [240] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [241] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [241] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [242] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [242] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [243] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [243] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [244] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [244] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [245] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [245] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [246] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [246] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [247] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [247] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [248] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [248] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [249] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [249] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [250] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [250] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [251] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [251] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [252] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [252] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [253] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [253] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [254] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [254] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [255] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [255] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [256] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [256] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [257] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [257] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [258] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [258] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [259] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [259] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [260] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [260] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [261] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [261] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [262] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [262] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [263] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [263] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [264] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [264] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [265] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [265] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [266] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [266] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [267] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [267] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [268] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [268] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [269] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [269] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [270] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [270] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [271] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [271] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [272] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [272] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [273] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [273] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [274] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [274] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [275] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [275] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [276] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [276] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [277] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [277] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [278] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [278] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [279] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [279] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [280] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [280] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [281] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [281] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [282] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [282] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [283] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [283] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [284] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [284] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [285] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [285] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [286] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [286] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [287] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [287] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [288] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [288] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [289] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [289] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [290] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [290] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [291] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [291] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [292] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [292] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [293] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [293] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [294] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [294] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [295] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [295] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [296] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [296] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [297] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [297] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [298] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [298] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [299] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [299] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [300] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [300] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [301] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [301] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [302] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [302] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [303] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [303] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [304] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [304] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [305] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [305] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [306] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [306] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [307] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [307] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [308] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [308] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [309] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [309] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [310] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [310] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [311] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [311] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [312] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [312] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [313] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [313] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [314] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [314] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [315] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [315] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [316] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [316] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [317] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [317] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [318] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [318] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [319] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [319] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [320] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [320] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [321] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [321] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [322] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [322] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [323] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [323] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [324] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [324] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [325] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [325] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [326] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [326] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [327] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [327] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [328] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [328] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [329] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [329] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [330] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [330] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [331] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [331] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [332] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [332] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [333] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [333] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [334] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [334] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [335] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [335] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [336] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [336] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [337] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [337] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [338] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [338] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [339] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [339] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [340] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [340] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [341] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [341] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [342] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [342] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [343] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [343] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [344] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [344] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [345] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [345] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [346] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [346] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [347] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [347] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [348] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [348] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [349] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [349] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [350] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [350] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [351] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [351] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [352] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [352] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [353] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [353] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [354] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [354] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [355] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [355] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [356] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [356] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [357] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [357] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [358] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [358] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [359] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [359] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [360] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [360] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [361] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [361] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [362] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [362] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [363] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [363] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [364] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [364] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [365] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [365] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [366] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [366] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [367] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [367] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [368] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [368] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [369] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [369] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [370] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [370] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [371] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [371] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [372] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [372] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [373] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [373] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [374] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [374] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [375] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [375] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [376] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [376] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [377] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [377] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [378] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [378] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [379] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [379] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [380] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [380] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [381] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [381] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [382] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [382] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [383] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [383] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [384] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [384] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [385] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [385] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [386] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [386] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [387] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [387] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [388] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [388] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [389] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [389] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [390] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [390] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [391] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [391] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [392] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [392] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [393] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [393] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [394] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [394] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [395] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [395] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [396] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [396] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [397] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [397] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [398] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [398] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [399] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [399] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [400] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [400] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [401] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [401] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [402] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [402] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [403] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [403] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [404] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [404] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [405] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [405] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [406] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [406] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [407] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [407] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [408] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [408] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [409] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [409] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [410] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [410] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [411] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [411] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [412] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [412] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [413] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [413] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [414] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [414] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [415] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [415] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [416] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [416] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [417] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [417] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [418] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [418] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [419] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [419] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [420] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [420] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [421] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [421] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [422] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [422] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [423] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [423] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [424] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [424] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [425] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [425] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [426] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [426] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [427] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [427] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [428] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [428] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [429] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [429] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [430] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [430] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [431] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [431] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [432] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [432] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [433] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [433] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [434] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [434] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [435] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [435] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [436] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [436] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [437] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [437] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [438] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [438] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [439] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [439] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [440] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [440] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [441] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [441] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [442] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [442] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [443] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [443] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [444] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [444] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [445] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [445] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [446] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [446] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [447] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [447] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [448] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [448] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [449] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [449] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [450] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [450] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [451] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [451] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [452] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [452] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [453] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [453] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [454] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [454] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [455] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [455] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [456] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [456] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [457] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [457] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [458] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [458] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [459] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [459] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [460] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [460] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [461] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [461] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [462] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [462] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [463] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [463] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [464] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [464] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [465] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [465] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [466] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [466] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [467] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [467] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [468] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [468] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [469] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [469] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [470] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [470] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [471] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [471] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [472] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [472] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [473] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [473] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [474] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [474] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [475] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [475] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [476] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [476] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [477] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [477] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [478] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [478] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [479] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [479] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [480] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [480] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [481] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [481] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [482] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [482] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [483] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [483] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [484] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [484] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [485] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [485] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [486] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [486] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [487] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [487] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [488] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [488] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [489] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [489] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [490] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [490] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [491] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [491] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [492] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [492] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [493] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [493] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [494] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [494] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [495] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [495] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [496] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [496] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [497] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [497] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [498] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [498] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [499] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [499] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [500] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [500] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [501] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [501] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [502] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [502] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [503] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [503] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [504] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [504] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [505] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [505] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [506] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [506] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [507] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [507] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [508] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [508] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [509] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [509] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [510] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [510] "reg genblk1.s_tdata_reg[511:0]" +Toggle genblk1.m_tid_pre "reg genblk1.m_tid_pre[7:0]" +Toggle 0to1 genblk1.s_tlast_reg "reg genblk1.s_tlast_reg" +Toggle 1to0 genblk1.s_tlast_reg "reg genblk1.s_tlast_reg" +Toggle genblk1.s_tkeep_reg "reg genblk1.s_tkeep_reg[63:0]" +Toggle genblk1.m_tuser_reg "reg genblk1.m_tuser_reg[9:0]" +Toggle genblk1.m_tuser_pre "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tlast_reg "reg genblk1.m_tlast_reg" +Toggle 1to0 genblk1.m_tlast_reg "reg genblk1.m_tlast_reg" +Toggle 0to1 genblk1.m_tlast_pre "reg genblk1.m_tlast_pre" +Toggle 1to0 genblk1.m_tlast_pre "reg genblk1.m_tlast_pre" +Toggle genblk1.m_tkeep_reg "reg genblk1.m_tkeep_reg[63:0]" +Toggle genblk1.m_tkeep_pre "reg genblk1.m_tkeep_pre[63:0]" +Toggle genblk1.m_tid_reg "reg genblk1.m_tid_reg[7:0]" +ANNOTATION: " Constant value 'h1 " +Toggle genblk1.s_tuser_reg "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tready_pre "logic genblk1.s_tready_pre" +Toggle 1to0 genblk1.s_tready_pre "logic genblk1.s_tready_pre" +ANNOTATION: " value is 'hx " +Toggle genblk1.s_tid_reg "reg genblk1.s_tid_reg[7:0]" +ANNOTATION: " value is 'hx " +Toggle genblk1.s_tdest_reg "reg genblk1.s_tdest_reg[7:0]" +Toggle genblk1.m_tdata_pre "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [511] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [511] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [0] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [0] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [1] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [1] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [2] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [2] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [3] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [3] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [6] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [6] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [7] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [7] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [8] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [8] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [9] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [9] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [10] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [10] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [11] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [11] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [12] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [12] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [13] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [13] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [14] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [14] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [15] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [15] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [16] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [16] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [17] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [17] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [18] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [18] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [19] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [19] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [21] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [21] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [22] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [22] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [23] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [23] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [24] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [24] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [25] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [25] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [26] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [26] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [27] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [27] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [28] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [28] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [29] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [29] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [30] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [30] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [31] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [31] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [32] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [32] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [33] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [33] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [34] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [34] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [35] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [35] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [36] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [36] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [37] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [37] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [38] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [38] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [39] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [39] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [40] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [40] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [41] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [41] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [42] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [42] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [43] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [43] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [44] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [44] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [45] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [45] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [46] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [46] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [47] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [47] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [48] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [48] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [49] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [49] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [50] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [50] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [51] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [51] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [52] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [52] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [53] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [53] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [54] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [54] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [55] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [55] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [56] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [56] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [57] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [57] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [58] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [58] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [59] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [59] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [60] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [60] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [61] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [61] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [62] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [62] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [63] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [63] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [64] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [64] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [65] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [65] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [66] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [66] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [67] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [67] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [68] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [68] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [69] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [69] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [70] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [70] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [71] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [71] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [72] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [72] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [73] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [73] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [74] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [74] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [75] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [75] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [76] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [76] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [77] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [77] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [78] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [78] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [79] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [79] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [80] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [80] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [81] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [81] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [82] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [82] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [83] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [83] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [84] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [84] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [85] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [85] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [86] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [86] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [87] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [87] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [88] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [88] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [89] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [89] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [90] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [90] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [91] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [91] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [92] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [92] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [93] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [93] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [94] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [94] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [95] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [95] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [96] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [96] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [97] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [97] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [98] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [98] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [99] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [99] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [100] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [100] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [101] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [101] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [102] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [102] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [103] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [103] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [104] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [104] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [105] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [105] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [106] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [106] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [107] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [107] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [108] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [108] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [109] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [109] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [110] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [110] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [111] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [111] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [112] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [112] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [113] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [113] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [114] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [114] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [115] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [115] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [116] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [116] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [117] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [117] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [126] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [126] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [127] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [127] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [128] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [128] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [129] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [129] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [130] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [130] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [131] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [131] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [132] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [132] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [133] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [133] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [134] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [134] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [135] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [135] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [136] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [136] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [137] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [137] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [138] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [138] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [139] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [139] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [140] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [140] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [141] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [141] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [142] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [142] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [143] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [143] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [144] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [144] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [145] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [145] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [146] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [146] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [147] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [147] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [148] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [148] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [149] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [149] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [150] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [150] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [151] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [151] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [152] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [152] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [153] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [153] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [154] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [154] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [155] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [155] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [156] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [156] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [157] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [157] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [158] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [158] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [159] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [159] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [160] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [160] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [162] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [162] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [163] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [163] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [164] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [164] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [165] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [165] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [166] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [166] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [167] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [167] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [168] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [168] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [169] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [169] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [170] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [170] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [171] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [171] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [172] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [172] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [173] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [173] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [175] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [175] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [176] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [176] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [177] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [177] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [178] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [178] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [179] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [179] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [180] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [180] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [181] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [181] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [182] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [182] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [183] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [183] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [184] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [184] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [185] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [185] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [186] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [186] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [187] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [187] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [188] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [188] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [189] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [189] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [190] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [190] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [191] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [191] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [192] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [192] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [193] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [193] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [194] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [194] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [195] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [195] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [196] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [196] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [197] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [197] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [198] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [198] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [199] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [199] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [200] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [200] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [201] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [201] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [202] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [202] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [203] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [203] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [204] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [204] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [205] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [205] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [206] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [206] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [207] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [207] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [208] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [208] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [209] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [209] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [210] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [210] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [211] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [211] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [212] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [212] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [213] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [213] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [214] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [214] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [215] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [215] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [216] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [216] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [217] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [217] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [218] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [218] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [219] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [219] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [220] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [220] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [221] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [221] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [222] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [222] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [223] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [223] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [226] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [226] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [227] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [227] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [228] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [228] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [229] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [229] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [230] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [230] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [231] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [231] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [232] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [232] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [233] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [233] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [234] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [234] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [235] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [235] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [236] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [236] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [237] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [237] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [238] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [238] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [239] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [239] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [240] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [240] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [241] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [241] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [242] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [242] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [243] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [243] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [244] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [244] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [245] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [245] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [246] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [246] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [247] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [247] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [248] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [248] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [249] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [249] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [250] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [250] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [251] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [251] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [252] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [252] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [253] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [253] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [254] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [254] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [255] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [255] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [256] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [256] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [257] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [257] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [258] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [258] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [259] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [259] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [260] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [260] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [261] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [261] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [262] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [262] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [263] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [263] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [264] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [264] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [265] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [265] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [266] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [266] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [267] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [267] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [268] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [268] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [269] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [269] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [270] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [270] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [271] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [271] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [272] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [272] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [273] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [273] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [274] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [274] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [275] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [275] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [276] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [276] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [277] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [277] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [278] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [278] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [279] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [279] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [280] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [280] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [281] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [281] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [282] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [282] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [283] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [283] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [284] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [284] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [285] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [285] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [286] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [286] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [287] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [287] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [288] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [288] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [289] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [289] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [290] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [290] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [291] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [291] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [292] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [292] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [293] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [293] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [294] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [294] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [295] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [295] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [296] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [296] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [297] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [297] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [298] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [298] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [299] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [299] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [300] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [300] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [301] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [301] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [302] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [302] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [303] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [303] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [304] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [304] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [305] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [305] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [306] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [306] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [307] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [307] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [308] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [308] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [309] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [309] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [310] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [310] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [311] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [311] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [312] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [312] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [313] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [313] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [314] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [314] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [315] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [315] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [316] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [316] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [317] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [317] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [318] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [318] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [319] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [319] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [320] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [320] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [321] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [321] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [322] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [322] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [323] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [323] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [324] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [324] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [325] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [325] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [326] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [326] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [327] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [327] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [328] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [328] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [329] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [329] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [330] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [330] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [331] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [331] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [332] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [332] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [333] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [333] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [334] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [334] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [335] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [335] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [336] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [336] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [337] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [337] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [338] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [338] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [339] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [339] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [340] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [340] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [341] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [341] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [342] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [342] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [343] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [343] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [344] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [344] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [345] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [345] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [346] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [346] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [347] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [347] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [348] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [348] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [349] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [349] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [350] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [350] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [351] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [351] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [352] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [352] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [353] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [353] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [354] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [354] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [355] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [355] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [356] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [356] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [357] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [357] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [358] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [358] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [359] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [359] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [360] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [360] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [361] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [361] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [362] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [362] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [363] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [363] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [364] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [364] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [365] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [365] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [366] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [366] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [367] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [367] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [368] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [368] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [369] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [369] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [370] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [370] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [371] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [371] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [372] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [372] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [373] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [373] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [374] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [374] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [375] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [375] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [376] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [376] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [377] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [377] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [378] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [378] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [379] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [379] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [380] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [380] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [381] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [381] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [382] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [382] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [383] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [383] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [384] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [384] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [385] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [385] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [386] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [386] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [387] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [387] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [388] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [388] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [389] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [389] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [390] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [390] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [391] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [391] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [392] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [392] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [393] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [393] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [394] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [394] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [395] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [395] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [396] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [396] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [397] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [397] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [398] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [398] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [399] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [399] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [400] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [400] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [401] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [401] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [402] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [402] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [403] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [403] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [404] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [404] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [405] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [405] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [406] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [406] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [407] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [407] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [408] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [408] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [409] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [409] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [410] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [410] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [411] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [411] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [412] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [412] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [413] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [413] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [414] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [414] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [415] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [415] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [416] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [416] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [417] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [417] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [418] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [418] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [419] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [419] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [420] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [420] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [421] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [421] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [422] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [422] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [423] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [423] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [424] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [424] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [425] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [425] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [426] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [426] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [427] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [427] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [428] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [428] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [429] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [429] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [430] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [430] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [431] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [431] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [432] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [432] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [433] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [433] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [434] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [434] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [435] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [435] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [436] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [436] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [437] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [437] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [438] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [438] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [439] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [439] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [440] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [440] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [441] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [441] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [442] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [442] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [443] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [443] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [444] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [444] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [445] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [445] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [446] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [446] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [447] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [447] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [448] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [448] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [449] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [449] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [450] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [450] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [451] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [451] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [452] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [452] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [453] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [453] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [454] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [454] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [455] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [455] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [456] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [456] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [457] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [457] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [458] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [458] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [459] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [459] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [460] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [460] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [461] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [461] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [462] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [462] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [463] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [463] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [464] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [464] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [465] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [465] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [466] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [466] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [467] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [467] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [468] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [468] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [469] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [469] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [470] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [470] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [471] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [471] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [472] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [472] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [473] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [473] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [474] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [474] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [475] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [475] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [476] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [476] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [477] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [477] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [478] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [478] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [479] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [479] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [480] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [480] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [481] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [481] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [482] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [482] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [483] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [483] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [484] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [484] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [485] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [485] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [486] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [486] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [487] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [487] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [488] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [488] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [489] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [489] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [490] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [490] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [491] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [491] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [492] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [492] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [493] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [493] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [494] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [494] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [495] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [495] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [496] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [496] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [497] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [497] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [498] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [498] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [499] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [499] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [500] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [500] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [501] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [501] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [502] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [502] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [503] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [503] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [504] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [504] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [505] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [505] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [506] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [506] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [507] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [507] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [508] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [508] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [509] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [509] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [510] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [510] "reg genblk1.m_tdata_reg[511:0]" +ANNOTATION: " value is 'hx " +Toggle genblk1.m_tdest_pre "reg genblk1.m_tdest_pre[7:0]" +ANNOTATION: " value is 'hx " +Toggle genblk1.m_tdest_reg "reg genblk1.m_tdest_reg[7:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.local_commit.commit_in +ANNOTATION: " 64 bits keep " +Toggle tkeep "logic tkeep[63:0]" +ANNOTATION: " Constant value as 'h1 for DM mode. " +Toggle tuser_vendor "logic tuser_vendor[9:0]" +Toggle 0to1 tready "logic tready" +Toggle 1to0 tready "logic tready" +Toggle 0to1 tdata [511] "logic tdata[511:0]" +Toggle 1to0 tdata [511] "logic tdata[511:0]" +Toggle 0to1 tdata [226] "logic tdata[511:0]" +Toggle 1to0 tdata [226] "logic tdata[511:0]" +Toggle 0to1 tdata [227] "logic tdata[511:0]" +Toggle 1to0 tdata [227] "logic tdata[511:0]" +Toggle 0to1 tdata [228] "logic tdata[511:0]" +Toggle 1to0 tdata [228] "logic tdata[511:0]" +Toggle 0to1 tdata [229] "logic tdata[511:0]" +Toggle 1to0 tdata [229] "logic tdata[511:0]" +Toggle 0to1 tdata [230] "logic tdata[511:0]" +Toggle 1to0 tdata [230] "logic tdata[511:0]" +Toggle 0to1 tdata [231] "logic tdata[511:0]" +Toggle 1to0 tdata [231] "logic tdata[511:0]" +Toggle 0to1 tdata [232] "logic tdata[511:0]" +Toggle 1to0 tdata [232] "logic tdata[511:0]" +Toggle 0to1 tdata [233] "logic tdata[511:0]" +Toggle 1to0 tdata [233] "logic tdata[511:0]" +Toggle 0to1 tdata [234] "logic tdata[511:0]" +Toggle 1to0 tdata [234] "logic tdata[511:0]" +Toggle 0to1 tdata [235] "logic tdata[511:0]" +Toggle 1to0 tdata [235] "logic tdata[511:0]" +Toggle 0to1 tdata [236] "logic tdata[511:0]" +Toggle 1to0 tdata [236] "logic tdata[511:0]" +Toggle 0to1 tdata [237] "logic tdata[511:0]" +Toggle 1to0 tdata [237] "logic tdata[511:0]" +Toggle 0to1 tdata [238] "logic tdata[511:0]" +Toggle 1to0 tdata [238] "logic tdata[511:0]" +Toggle 0to1 tdata [239] "logic tdata[511:0]" +Toggle 1to0 tdata [239] "logic tdata[511:0]" +Toggle 0to1 tdata [240] "logic tdata[511:0]" +Toggle 1to0 tdata [240] "logic tdata[511:0]" +Toggle 0to1 tdata [241] "logic tdata[511:0]" +Toggle 1to0 tdata [241] "logic tdata[511:0]" +Toggle 0to1 tdata [242] "logic tdata[511:0]" +Toggle 1to0 tdata [242] "logic tdata[511:0]" +Toggle 0to1 tdata [243] "logic tdata[511:0]" +Toggle 1to0 tdata [243] "logic tdata[511:0]" +Toggle 0to1 tdata [244] "logic tdata[511:0]" +Toggle 1to0 tdata [244] "logic tdata[511:0]" +Toggle 0to1 tdata [245] "logic tdata[511:0]" +Toggle 1to0 tdata [245] "logic tdata[511:0]" +Toggle 0to1 tdata [246] "logic tdata[511:0]" +Toggle 1to0 tdata [246] "logic tdata[511:0]" +Toggle 0to1 tdata [247] "logic tdata[511:0]" +Toggle 1to0 tdata [247] "logic tdata[511:0]" +Toggle 0to1 tdata [248] "logic tdata[511:0]" +Toggle 1to0 tdata [248] "logic tdata[511:0]" +Toggle 0to1 tdata [249] "logic tdata[511:0]" +Toggle 1to0 tdata [249] "logic tdata[511:0]" +Toggle 0to1 tdata [250] "logic tdata[511:0]" +Toggle 1to0 tdata [250] "logic tdata[511:0]" +Toggle 0to1 tdata [251] "logic tdata[511:0]" +Toggle 1to0 tdata [251] "logic tdata[511:0]" +Toggle 0to1 tdata [252] "logic tdata[511:0]" +Toggle 1to0 tdata [252] "logic tdata[511:0]" +Toggle 0to1 tdata [253] "logic tdata[511:0]" +Toggle 1to0 tdata [253] "logic tdata[511:0]" +Toggle 0to1 tdata [254] "logic tdata[511:0]" +Toggle 1to0 tdata [254] "logic tdata[511:0]" +Toggle 0to1 tdata [255] "logic tdata[511:0]" +Toggle 1to0 tdata [255] "logic tdata[511:0]" +Toggle 0to1 tdata [256] "logic tdata[511:0]" +Toggle 1to0 tdata [256] "logic tdata[511:0]" +Toggle 0to1 tdata [257] "logic tdata[511:0]" +Toggle 1to0 tdata [257] "logic tdata[511:0]" +Toggle 0to1 tdata [258] "logic tdata[511:0]" +Toggle 1to0 tdata [258] "logic tdata[511:0]" +Toggle 0to1 tdata [259] "logic tdata[511:0]" +Toggle 1to0 tdata [259] "logic tdata[511:0]" +Toggle 0to1 tdata [260] "logic tdata[511:0]" +Toggle 1to0 tdata [260] "logic tdata[511:0]" +Toggle 0to1 tdata [261] "logic tdata[511:0]" +Toggle 1to0 tdata [261] "logic tdata[511:0]" +Toggle 0to1 tdata [262] "logic tdata[511:0]" +Toggle 1to0 tdata [262] "logic tdata[511:0]" +Toggle 0to1 tdata [263] "logic tdata[511:0]" +Toggle 1to0 tdata [263] "logic tdata[511:0]" +Toggle 0to1 tdata [264] "logic tdata[511:0]" +Toggle 1to0 tdata [264] "logic tdata[511:0]" +Toggle 0to1 tdata [265] "logic tdata[511:0]" +Toggle 1to0 tdata [265] "logic tdata[511:0]" +Toggle 0to1 tdata [266] "logic tdata[511:0]" +Toggle 1to0 tdata [266] "logic tdata[511:0]" +Toggle 0to1 tdata [267] "logic tdata[511:0]" +Toggle 1to0 tdata [267] "logic tdata[511:0]" +Toggle 0to1 tdata [268] "logic tdata[511:0]" +Toggle 1to0 tdata [268] "logic tdata[511:0]" +Toggle 0to1 tdata [269] "logic tdata[511:0]" +Toggle 1to0 tdata [269] "logic tdata[511:0]" +Toggle 0to1 tdata [270] "logic tdata[511:0]" +Toggle 1to0 tdata [270] "logic tdata[511:0]" +Toggle 0to1 tdata [271] "logic tdata[511:0]" +Toggle 1to0 tdata [271] "logic tdata[511:0]" +Toggle 0to1 tdata [272] "logic tdata[511:0]" +Toggle 1to0 tdata [272] "logic tdata[511:0]" +Toggle 0to1 tdata [273] "logic tdata[511:0]" +Toggle 1to0 tdata [273] "logic tdata[511:0]" +Toggle 0to1 tdata [274] "logic tdata[511:0]" +Toggle 1to0 tdata [274] "logic tdata[511:0]" +Toggle 0to1 tdata [275] "logic tdata[511:0]" +Toggle 1to0 tdata [275] "logic tdata[511:0]" +Toggle 0to1 tdata [276] "logic tdata[511:0]" +Toggle 1to0 tdata [276] "logic tdata[511:0]" +Toggle 0to1 tdata [277] "logic tdata[511:0]" +Toggle 1to0 tdata [277] "logic tdata[511:0]" +Toggle 0to1 tdata [278] "logic tdata[511:0]" +Toggle 1to0 tdata [278] "logic tdata[511:0]" +Toggle 0to1 tdata [279] "logic tdata[511:0]" +Toggle 1to0 tdata [279] "logic tdata[511:0]" +Toggle 0to1 tdata [280] "logic tdata[511:0]" +Toggle 1to0 tdata [280] "logic tdata[511:0]" +Toggle 0to1 tdata [281] "logic tdata[511:0]" +Toggle 1to0 tdata [281] "logic tdata[511:0]" +Toggle 0to1 tdata [282] "logic tdata[511:0]" +Toggle 1to0 tdata [282] "logic tdata[511:0]" +Toggle 0to1 tdata [283] "logic tdata[511:0]" +Toggle 1to0 tdata [283] "logic tdata[511:0]" +Toggle 0to1 tdata [284] "logic tdata[511:0]" +Toggle 1to0 tdata [284] "logic tdata[511:0]" +Toggle 0to1 tdata [285] "logic tdata[511:0]" +Toggle 1to0 tdata [285] "logic tdata[511:0]" +Toggle 0to1 tdata [286] "logic tdata[511:0]" +Toggle 1to0 tdata [286] "logic tdata[511:0]" +Toggle 0to1 tdata [287] "logic tdata[511:0]" +Toggle 1to0 tdata [287] "logic tdata[511:0]" +Toggle 0to1 tdata [288] "logic tdata[511:0]" +Toggle 1to0 tdata [288] "logic tdata[511:0]" +Toggle 0to1 tdata [289] "logic tdata[511:0]" +Toggle 1to0 tdata [289] "logic tdata[511:0]" +Toggle 0to1 tdata [290] "logic tdata[511:0]" +Toggle 1to0 tdata [290] "logic tdata[511:0]" +Toggle 0to1 tdata [291] "logic tdata[511:0]" +Toggle 1to0 tdata [291] "logic tdata[511:0]" +Toggle 0to1 tdata [292] "logic tdata[511:0]" +Toggle 1to0 tdata [292] "logic tdata[511:0]" +Toggle 0to1 tdata [293] "logic tdata[511:0]" +Toggle 1to0 tdata [293] "logic tdata[511:0]" +Toggle 0to1 tdata [294] "logic tdata[511:0]" +Toggle 1to0 tdata [294] "logic tdata[511:0]" +Toggle 0to1 tdata [295] "logic tdata[511:0]" +Toggle 1to0 tdata [295] "logic tdata[511:0]" +Toggle 0to1 tdata [296] "logic tdata[511:0]" +Toggle 1to0 tdata [296] "logic tdata[511:0]" +Toggle 0to1 tdata [297] "logic tdata[511:0]" +Toggle 1to0 tdata [297] "logic tdata[511:0]" +Toggle 0to1 tdata [298] "logic tdata[511:0]" +Toggle 1to0 tdata [298] "logic tdata[511:0]" +Toggle 0to1 tdata [299] "logic tdata[511:0]" +Toggle 1to0 tdata [299] "logic tdata[511:0]" +Toggle 0to1 tdata [300] "logic tdata[511:0]" +Toggle 1to0 tdata [300] "logic tdata[511:0]" +Toggle 0to1 tdata [301] "logic tdata[511:0]" +Toggle 1to0 tdata [301] "logic tdata[511:0]" +Toggle 0to1 tdata [302] "logic tdata[511:0]" +Toggle 1to0 tdata [302] "logic tdata[511:0]" +Toggle 0to1 tdata [303] "logic tdata[511:0]" +Toggle 1to0 tdata [303] "logic tdata[511:0]" +Toggle 0to1 tdata [304] "logic tdata[511:0]" +Toggle 1to0 tdata [304] "logic tdata[511:0]" +Toggle 0to1 tdata [305] "logic tdata[511:0]" +Toggle 1to0 tdata [305] "logic tdata[511:0]" +Toggle 0to1 tdata [306] "logic tdata[511:0]" +Toggle 1to0 tdata [306] "logic tdata[511:0]" +Toggle 0to1 tdata [307] "logic tdata[511:0]" +Toggle 1to0 tdata [307] "logic tdata[511:0]" +Toggle 0to1 tdata [308] "logic tdata[511:0]" +Toggle 1to0 tdata [308] "logic tdata[511:0]" +Toggle 0to1 tdata [309] "logic tdata[511:0]" +Toggle 1to0 tdata [309] "logic tdata[511:0]" +Toggle 0to1 tdata [310] "logic tdata[511:0]" +Toggle 1to0 tdata [310] "logic tdata[511:0]" +Toggle 0to1 tdata [311] "logic tdata[511:0]" +Toggle 1to0 tdata [311] "logic tdata[511:0]" +Toggle 0to1 tdata [312] "logic tdata[511:0]" +Toggle 1to0 tdata [312] "logic tdata[511:0]" +Toggle 0to1 tdata [313] "logic tdata[511:0]" +Toggle 1to0 tdata [313] "logic tdata[511:0]" +Toggle 0to1 tdata [314] "logic tdata[511:0]" +Toggle 1to0 tdata [314] "logic tdata[511:0]" +Toggle 0to1 tdata [315] "logic tdata[511:0]" +Toggle 1to0 tdata [315] "logic tdata[511:0]" +Toggle 0to1 tdata [316] "logic tdata[511:0]" +Toggle 1to0 tdata [316] "logic tdata[511:0]" +Toggle 0to1 tdata [317] "logic tdata[511:0]" +Toggle 1to0 tdata [317] "logic tdata[511:0]" +Toggle 0to1 tdata [318] "logic tdata[511:0]" +Toggle 1to0 tdata [318] "logic tdata[511:0]" +Toggle 0to1 tdata [319] "logic tdata[511:0]" +Toggle 1to0 tdata [319] "logic tdata[511:0]" +Toggle 0to1 tdata [320] "logic tdata[511:0]" +Toggle 1to0 tdata [320] "logic tdata[511:0]" +Toggle 0to1 tdata [321] "logic tdata[511:0]" +Toggle 1to0 tdata [321] "logic tdata[511:0]" +Toggle 0to1 tdata [322] "logic tdata[511:0]" +Toggle 1to0 tdata [322] "logic tdata[511:0]" +Toggle 0to1 tdata [323] "logic tdata[511:0]" +Toggle 1to0 tdata [323] "logic tdata[511:0]" +Toggle 0to1 tdata [324] "logic tdata[511:0]" +Toggle 1to0 tdata [324] "logic tdata[511:0]" +Toggle 0to1 tdata [325] "logic tdata[511:0]" +Toggle 1to0 tdata [325] "logic tdata[511:0]" +Toggle 0to1 tdata [326] "logic tdata[511:0]" +Toggle 1to0 tdata [326] "logic tdata[511:0]" +Toggle 0to1 tdata [327] "logic tdata[511:0]" +Toggle 1to0 tdata [327] "logic tdata[511:0]" +Toggle 0to1 tdata [328] "logic tdata[511:0]" +Toggle 1to0 tdata [328] "logic tdata[511:0]" +Toggle 0to1 tdata [329] "logic tdata[511:0]" +Toggle 1to0 tdata [329] "logic tdata[511:0]" +Toggle 0to1 tdata [330] "logic tdata[511:0]" +Toggle 1to0 tdata [330] "logic tdata[511:0]" +Toggle 0to1 tdata [331] "logic tdata[511:0]" +Toggle 1to0 tdata [331] "logic tdata[511:0]" +Toggle 0to1 tdata [332] "logic tdata[511:0]" +Toggle 1to0 tdata [332] "logic tdata[511:0]" +Toggle 0to1 tdata [333] "logic tdata[511:0]" +Toggle 1to0 tdata [333] "logic tdata[511:0]" +Toggle 0to1 tdata [334] "logic tdata[511:0]" +Toggle 1to0 tdata [334] "logic tdata[511:0]" +Toggle 0to1 tdata [335] "logic tdata[511:0]" +Toggle 1to0 tdata [335] "logic tdata[511:0]" +Toggle 0to1 tdata [336] "logic tdata[511:0]" +Toggle 1to0 tdata [336] "logic tdata[511:0]" +Toggle 0to1 tdata [337] "logic tdata[511:0]" +Toggle 1to0 tdata [337] "logic tdata[511:0]" +Toggle 0to1 tdata [338] "logic tdata[511:0]" +Toggle 1to0 tdata [338] "logic tdata[511:0]" +Toggle 0to1 tdata [339] "logic tdata[511:0]" +Toggle 1to0 tdata [339] "logic tdata[511:0]" +Toggle 0to1 tdata [340] "logic tdata[511:0]" +Toggle 1to0 tdata [340] "logic tdata[511:0]" +Toggle 0to1 tdata [341] "logic tdata[511:0]" +Toggle 1to0 tdata [341] "logic tdata[511:0]" +Toggle 0to1 tdata [342] "logic tdata[511:0]" +Toggle 1to0 tdata [342] "logic tdata[511:0]" +Toggle 0to1 tdata [343] "logic tdata[511:0]" +Toggle 1to0 tdata [343] "logic tdata[511:0]" +Toggle 0to1 tdata [344] "logic tdata[511:0]" +Toggle 1to0 tdata [344] "logic tdata[511:0]" +Toggle 0to1 tdata [345] "logic tdata[511:0]" +Toggle 1to0 tdata [345] "logic tdata[511:0]" +Toggle 0to1 tdata [346] "logic tdata[511:0]" +Toggle 1to0 tdata [346] "logic tdata[511:0]" +Toggle 0to1 tdata [347] "logic tdata[511:0]" +Toggle 1to0 tdata [347] "logic tdata[511:0]" +Toggle 0to1 tdata [348] "logic tdata[511:0]" +Toggle 1to0 tdata [348] "logic tdata[511:0]" +Toggle 0to1 tdata [349] "logic tdata[511:0]" +Toggle 1to0 tdata [349] "logic tdata[511:0]" +Toggle 0to1 tdata [350] "logic tdata[511:0]" +Toggle 1to0 tdata [350] "logic tdata[511:0]" +Toggle 0to1 tdata [351] "logic tdata[511:0]" +Toggle 1to0 tdata [351] "logic tdata[511:0]" +Toggle 0to1 tdata [352] "logic tdata[511:0]" +Toggle 1to0 tdata [352] "logic tdata[511:0]" +Toggle 0to1 tdata [353] "logic tdata[511:0]" +Toggle 1to0 tdata [353] "logic tdata[511:0]" +Toggle 0to1 tdata [354] "logic tdata[511:0]" +Toggle 1to0 tdata [354] "logic tdata[511:0]" +Toggle 0to1 tdata [355] "logic tdata[511:0]" +Toggle 1to0 tdata [355] "logic tdata[511:0]" +Toggle 0to1 tdata [356] "logic tdata[511:0]" +Toggle 1to0 tdata [356] "logic tdata[511:0]" +Toggle 0to1 tdata [357] "logic tdata[511:0]" +Toggle 1to0 tdata [357] "logic tdata[511:0]" +Toggle 0to1 tdata [358] "logic tdata[511:0]" +Toggle 1to0 tdata [358] "logic tdata[511:0]" +Toggle 0to1 tdata [359] "logic tdata[511:0]" +Toggle 1to0 tdata [359] "logic tdata[511:0]" +Toggle 0to1 tdata [360] "logic tdata[511:0]" +Toggle 1to0 tdata [360] "logic tdata[511:0]" +Toggle 0to1 tdata [361] "logic tdata[511:0]" +Toggle 1to0 tdata [361] "logic tdata[511:0]" +Toggle 0to1 tdata [362] "logic tdata[511:0]" +Toggle 1to0 tdata [362] "logic tdata[511:0]" +Toggle 0to1 tdata [363] "logic tdata[511:0]" +Toggle 1to0 tdata [363] "logic tdata[511:0]" +Toggle 0to1 tdata [364] "logic tdata[511:0]" +Toggle 1to0 tdata [364] "logic tdata[511:0]" +Toggle 0to1 tdata [365] "logic tdata[511:0]" +Toggle 1to0 tdata [365] "logic tdata[511:0]" +Toggle 0to1 tdata [366] "logic tdata[511:0]" +Toggle 1to0 tdata [366] "logic tdata[511:0]" +Toggle 0to1 tdata [367] "logic tdata[511:0]" +Toggle 1to0 tdata [367] "logic tdata[511:0]" +Toggle 0to1 tdata [368] "logic tdata[511:0]" +Toggle 1to0 tdata [368] "logic tdata[511:0]" +Toggle 0to1 tdata [369] "logic tdata[511:0]" +Toggle 1to0 tdata [369] "logic tdata[511:0]" +Toggle 0to1 tdata [370] "logic tdata[511:0]" +Toggle 1to0 tdata [370] "logic tdata[511:0]" +Toggle 0to1 tdata [371] "logic tdata[511:0]" +Toggle 1to0 tdata [371] "logic tdata[511:0]" +Toggle 0to1 tdata [372] "logic tdata[511:0]" +Toggle 1to0 tdata [372] "logic tdata[511:0]" +Toggle 0to1 tdata [373] "logic tdata[511:0]" +Toggle 1to0 tdata [373] "logic tdata[511:0]" +Toggle 0to1 tdata [374] "logic tdata[511:0]" +Toggle 1to0 tdata [374] "logic tdata[511:0]" +Toggle 0to1 tdata [375] "logic tdata[511:0]" +Toggle 1to0 tdata [375] "logic tdata[511:0]" +Toggle 0to1 tdata [376] "logic tdata[511:0]" +Toggle 1to0 tdata [376] "logic tdata[511:0]" +Toggle 0to1 tdata [377] "logic tdata[511:0]" +Toggle 1to0 tdata [377] "logic tdata[511:0]" +Toggle 0to1 tdata [378] "logic tdata[511:0]" +Toggle 1to0 tdata [378] "logic tdata[511:0]" +Toggle 0to1 tdata [379] "logic tdata[511:0]" +Toggle 1to0 tdata [379] "logic tdata[511:0]" +Toggle 0to1 tdata [380] "logic tdata[511:0]" +Toggle 1to0 tdata [380] "logic tdata[511:0]" +Toggle 0to1 tdata [381] "logic tdata[511:0]" +Toggle 1to0 tdata [381] "logic tdata[511:0]" +Toggle 0to1 tdata [382] "logic tdata[511:0]" +Toggle 1to0 tdata [382] "logic tdata[511:0]" +Toggle 0to1 tdata [383] "logic tdata[511:0]" +Toggle 1to0 tdata [383] "logic tdata[511:0]" +Toggle 0to1 tdata [384] "logic tdata[511:0]" +Toggle 1to0 tdata [384] "logic tdata[511:0]" +Toggle 0to1 tdata [385] "logic tdata[511:0]" +Toggle 1to0 tdata [385] "logic tdata[511:0]" +Toggle 0to1 tdata [386] "logic tdata[511:0]" +Toggle 1to0 tdata [386] "logic tdata[511:0]" +Toggle 0to1 tdata [387] "logic tdata[511:0]" +Toggle 1to0 tdata [387] "logic tdata[511:0]" +Toggle 0to1 tdata [388] "logic tdata[511:0]" +Toggle 1to0 tdata [388] "logic tdata[511:0]" +Toggle 0to1 tdata [389] "logic tdata[511:0]" +Toggle 1to0 tdata [389] "logic tdata[511:0]" +Toggle 0to1 tdata [390] "logic tdata[511:0]" +Toggle 1to0 tdata [390] "logic tdata[511:0]" +Toggle 0to1 tdata [391] "logic tdata[511:0]" +Toggle 1to0 tdata [391] "logic tdata[511:0]" +Toggle 0to1 tdata [392] "logic tdata[511:0]" +Toggle 1to0 tdata [392] "logic tdata[511:0]" +Toggle 0to1 tdata [393] "logic tdata[511:0]" +Toggle 1to0 tdata [393] "logic tdata[511:0]" +Toggle 0to1 tdata [394] "logic tdata[511:0]" +Toggle 1to0 tdata [394] "logic tdata[511:0]" +Toggle 0to1 tdata [395] "logic tdata[511:0]" +Toggle 1to0 tdata [395] "logic tdata[511:0]" +Toggle 0to1 tdata [396] "logic tdata[511:0]" +Toggle 1to0 tdata [396] "logic tdata[511:0]" +Toggle 0to1 tdata [397] "logic tdata[511:0]" +Toggle 1to0 tdata [397] "logic tdata[511:0]" +Toggle 0to1 tdata [398] "logic tdata[511:0]" +Toggle 1to0 tdata [398] "logic tdata[511:0]" +Toggle 0to1 tdata [399] "logic tdata[511:0]" +Toggle 1to0 tdata [399] "logic tdata[511:0]" +Toggle 0to1 tdata [400] "logic tdata[511:0]" +Toggle 1to0 tdata [400] "logic tdata[511:0]" +Toggle 0to1 tdata [401] "logic tdata[511:0]" +Toggle 1to0 tdata [401] "logic tdata[511:0]" +Toggle 0to1 tdata [402] "logic tdata[511:0]" +Toggle 1to0 tdata [402] "logic tdata[511:0]" +Toggle 0to1 tdata [403] "logic tdata[511:0]" +Toggle 1to0 tdata [403] "logic tdata[511:0]" +Toggle 0to1 tdata [404] "logic tdata[511:0]" +Toggle 1to0 tdata [404] "logic tdata[511:0]" +Toggle 0to1 tdata [405] "logic tdata[511:0]" +Toggle 1to0 tdata [405] "logic tdata[511:0]" +Toggle 0to1 tdata [406] "logic tdata[511:0]" +Toggle 1to0 tdata [406] "logic tdata[511:0]" +Toggle 0to1 tdata [407] "logic tdata[511:0]" +Toggle 1to0 tdata [407] "logic tdata[511:0]" +Toggle 0to1 tdata [408] "logic tdata[511:0]" +Toggle 1to0 tdata [408] "logic tdata[511:0]" +Toggle 0to1 tdata [409] "logic tdata[511:0]" +Toggle 1to0 tdata [409] "logic tdata[511:0]" +Toggle 0to1 tdata [410] "logic tdata[511:0]" +Toggle 1to0 tdata [410] "logic tdata[511:0]" +Toggle 0to1 tdata [411] "logic tdata[511:0]" +Toggle 1to0 tdata [411] "logic tdata[511:0]" +Toggle 0to1 tdata [412] "logic tdata[511:0]" +Toggle 1to0 tdata [412] "logic tdata[511:0]" +Toggle 0to1 tdata [413] "logic tdata[511:0]" +Toggle 1to0 tdata [413] "logic tdata[511:0]" +Toggle 0to1 tdata [414] "logic tdata[511:0]" +Toggle 1to0 tdata [414] "logic tdata[511:0]" +Toggle 0to1 tdata [415] "logic tdata[511:0]" +Toggle 1to0 tdata [415] "logic tdata[511:0]" +Toggle 0to1 tdata [416] "logic tdata[511:0]" +Toggle 1to0 tdata [416] "logic tdata[511:0]" +Toggle 0to1 tdata [417] "logic tdata[511:0]" +Toggle 1to0 tdata [417] "logic tdata[511:0]" +Toggle 0to1 tdata [418] "logic tdata[511:0]" +Toggle 1to0 tdata [418] "logic tdata[511:0]" +Toggle 0to1 tdata [419] "logic tdata[511:0]" +Toggle 1to0 tdata [419] "logic tdata[511:0]" +Toggle 0to1 tdata [420] "logic tdata[511:0]" +Toggle 1to0 tdata [420] "logic tdata[511:0]" +Toggle 0to1 tdata [421] "logic tdata[511:0]" +Toggle 1to0 tdata [421] "logic tdata[511:0]" +Toggle 0to1 tdata [422] "logic tdata[511:0]" +Toggle 1to0 tdata [422] "logic tdata[511:0]" +Toggle 0to1 tdata [423] "logic tdata[511:0]" +Toggle 1to0 tdata [423] "logic tdata[511:0]" +Toggle 0to1 tdata [424] "logic tdata[511:0]" +Toggle 1to0 tdata [424] "logic tdata[511:0]" +Toggle 0to1 tdata [425] "logic tdata[511:0]" +Toggle 1to0 tdata [425] "logic tdata[511:0]" +Toggle 0to1 tdata [426] "logic tdata[511:0]" +Toggle 1to0 tdata [426] "logic tdata[511:0]" +Toggle 0to1 tdata [427] "logic tdata[511:0]" +Toggle 1to0 tdata [427] "logic tdata[511:0]" +Toggle 0to1 tdata [428] "logic tdata[511:0]" +Toggle 1to0 tdata [428] "logic tdata[511:0]" +Toggle 0to1 tdata [429] "logic tdata[511:0]" +Toggle 1to0 tdata [429] "logic tdata[511:0]" +Toggle 0to1 tdata [430] "logic tdata[511:0]" +Toggle 1to0 tdata [430] "logic tdata[511:0]" +Toggle 0to1 tdata [431] "logic tdata[511:0]" +Toggle 1to0 tdata [431] "logic tdata[511:0]" +Toggle 0to1 tdata [432] "logic tdata[511:0]" +Toggle 1to0 tdata [432] "logic tdata[511:0]" +Toggle 0to1 tdata [433] "logic tdata[511:0]" +Toggle 1to0 tdata [433] "logic tdata[511:0]" +Toggle 0to1 tdata [434] "logic tdata[511:0]" +Toggle 1to0 tdata [434] "logic tdata[511:0]" +Toggle 0to1 tdata [435] "logic tdata[511:0]" +Toggle 1to0 tdata [435] "logic tdata[511:0]" +Toggle 0to1 tdata [436] "logic tdata[511:0]" +Toggle 1to0 tdata [436] "logic tdata[511:0]" +Toggle 0to1 tdata [437] "logic tdata[511:0]" +Toggle 1to0 tdata [437] "logic tdata[511:0]" +Toggle 0to1 tdata [438] "logic tdata[511:0]" +Toggle 1to0 tdata [438] "logic tdata[511:0]" +Toggle 0to1 tdata [439] "logic tdata[511:0]" +Toggle 1to0 tdata [439] "logic tdata[511:0]" +Toggle 0to1 tdata [440] "logic tdata[511:0]" +Toggle 1to0 tdata [440] "logic tdata[511:0]" +Toggle 0to1 tdata [441] "logic tdata[511:0]" +Toggle 1to0 tdata [441] "logic tdata[511:0]" +Toggle 0to1 tdata [442] "logic tdata[511:0]" +Toggle 1to0 tdata [442] "logic tdata[511:0]" +Toggle 0to1 tdata [443] "logic tdata[511:0]" +Toggle 1to0 tdata [443] "logic tdata[511:0]" +Toggle 0to1 tdata [444] "logic tdata[511:0]" +Toggle 1to0 tdata [444] "logic tdata[511:0]" +Toggle 0to1 tdata [445] "logic tdata[511:0]" +Toggle 1to0 tdata [445] "logic tdata[511:0]" +Toggle 0to1 tdata [446] "logic tdata[511:0]" +Toggle 1to0 tdata [446] "logic tdata[511:0]" +Toggle 0to1 tdata [447] "logic tdata[511:0]" +Toggle 1to0 tdata [447] "logic tdata[511:0]" +Toggle 0to1 tdata [448] "logic tdata[511:0]" +Toggle 1to0 tdata [448] "logic tdata[511:0]" +Toggle 0to1 tdata [449] "logic tdata[511:0]" +Toggle 1to0 tdata [449] "logic tdata[511:0]" +Toggle 0to1 tdata [450] "logic tdata[511:0]" +Toggle 1to0 tdata [450] "logic tdata[511:0]" +Toggle 0to1 tdata [451] "logic tdata[511:0]" +Toggle 1to0 tdata [451] "logic tdata[511:0]" +Toggle 0to1 tdata [452] "logic tdata[511:0]" +Toggle 1to0 tdata [452] "logic tdata[511:0]" +Toggle 0to1 tdata [453] "logic tdata[511:0]" +Toggle 1to0 tdata [453] "logic tdata[511:0]" +Toggle 0to1 tdata [454] "logic tdata[511:0]" +Toggle 1to0 tdata [454] "logic tdata[511:0]" +Toggle 0to1 tdata [455] "logic tdata[511:0]" +Toggle 1to0 tdata [455] "logic tdata[511:0]" +Toggle 0to1 tdata [456] "logic tdata[511:0]" +Toggle 1to0 tdata [456] "logic tdata[511:0]" +Toggle 0to1 tdata [457] "logic tdata[511:0]" +Toggle 1to0 tdata [457] "logic tdata[511:0]" +Toggle 0to1 tdata [458] "logic tdata[511:0]" +Toggle 1to0 tdata [458] "logic tdata[511:0]" +Toggle 0to1 tdata [459] "logic tdata[511:0]" +Toggle 1to0 tdata [459] "logic tdata[511:0]" +Toggle 0to1 tdata [460] "logic tdata[511:0]" +Toggle 1to0 tdata [460] "logic tdata[511:0]" +Toggle 0to1 tdata [461] "logic tdata[511:0]" +Toggle 1to0 tdata [461] "logic tdata[511:0]" +Toggle 0to1 tdata [462] "logic tdata[511:0]" +Toggle 1to0 tdata [462] "logic tdata[511:0]" +Toggle 0to1 tdata [463] "logic tdata[511:0]" +Toggle 1to0 tdata [463] "logic tdata[511:0]" +Toggle 0to1 tdata [464] "logic tdata[511:0]" +Toggle 1to0 tdata [464] "logic tdata[511:0]" +Toggle 0to1 tdata [465] "logic tdata[511:0]" +Toggle 1to0 tdata [465] "logic tdata[511:0]" +Toggle 0to1 tdata [466] "logic tdata[511:0]" +Toggle 1to0 tdata [466] "logic tdata[511:0]" +Toggle 0to1 tdata [467] "logic tdata[511:0]" +Toggle 1to0 tdata [467] "logic tdata[511:0]" +Toggle 0to1 tdata [468] "logic tdata[511:0]" +Toggle 1to0 tdata [468] "logic tdata[511:0]" +Toggle 0to1 tdata [469] "logic tdata[511:0]" +Toggle 1to0 tdata [469] "logic tdata[511:0]" +Toggle 0to1 tdata [470] "logic tdata[511:0]" +Toggle 1to0 tdata [470] "logic tdata[511:0]" +Toggle 0to1 tdata [471] "logic tdata[511:0]" +Toggle 1to0 tdata [471] "logic tdata[511:0]" +Toggle 0to1 tdata [472] "logic tdata[511:0]" +Toggle 1to0 tdata [472] "logic tdata[511:0]" +Toggle 0to1 tdata [473] "logic tdata[511:0]" +Toggle 1to0 tdata [473] "logic tdata[511:0]" +Toggle 0to1 tdata [474] "logic tdata[511:0]" +Toggle 1to0 tdata [474] "logic tdata[511:0]" +Toggle 0to1 tdata [475] "logic tdata[511:0]" +Toggle 1to0 tdata [475] "logic tdata[511:0]" +Toggle 0to1 tdata [476] "logic tdata[511:0]" +Toggle 1to0 tdata [476] "logic tdata[511:0]" +Toggle 0to1 tdata [477] "logic tdata[511:0]" +Toggle 1to0 tdata [477] "logic tdata[511:0]" +Toggle 0to1 tdata [478] "logic tdata[511:0]" +Toggle 1to0 tdata [478] "logic tdata[511:0]" +Toggle 0to1 tdata [479] "logic tdata[511:0]" +Toggle 1to0 tdata [479] "logic tdata[511:0]" +Toggle 0to1 tdata [480] "logic tdata[511:0]" +Toggle 1to0 tdata [480] "logic tdata[511:0]" +Toggle 0to1 tdata [481] "logic tdata[511:0]" +Toggle 1to0 tdata [481] "logic tdata[511:0]" +Toggle 0to1 tdata [482] "logic tdata[511:0]" +Toggle 1to0 tdata [482] "logic tdata[511:0]" +Toggle 0to1 tdata [483] "logic tdata[511:0]" +Toggle 1to0 tdata [483] "logic tdata[511:0]" +Toggle 0to1 tdata [484] "logic tdata[511:0]" +Toggle 1to0 tdata [484] "logic tdata[511:0]" +Toggle 0to1 tdata [485] "logic tdata[511:0]" +Toggle 1to0 tdata [485] "logic tdata[511:0]" +Toggle 0to1 tdata [486] "logic tdata[511:0]" +Toggle 1to0 tdata [486] "logic tdata[511:0]" +Toggle 0to1 tdata [487] "logic tdata[511:0]" +Toggle 1to0 tdata [487] "logic tdata[511:0]" +Toggle 0to1 tdata [488] "logic tdata[511:0]" +Toggle 1to0 tdata [488] "logic tdata[511:0]" +Toggle 0to1 tdata [489] "logic tdata[511:0]" +Toggle 1to0 tdata [489] "logic tdata[511:0]" +Toggle 0to1 tdata [490] "logic tdata[511:0]" +Toggle 1to0 tdata [490] "logic tdata[511:0]" +Toggle 0to1 tdata [491] "logic tdata[511:0]" +Toggle 1to0 tdata [491] "logic tdata[511:0]" +Toggle 0to1 tdata [492] "logic tdata[511:0]" +Toggle 1to0 tdata [492] "logic tdata[511:0]" +Toggle 0to1 tdata [493] "logic tdata[511:0]" +Toggle 1to0 tdata [493] "logic tdata[511:0]" +Toggle 0to1 tdata [494] "logic tdata[511:0]" +Toggle 1to0 tdata [494] "logic tdata[511:0]" +Toggle 0to1 tdata [495] "logic tdata[511:0]" +Toggle 1to0 tdata [495] "logic tdata[511:0]" +Toggle 0to1 tdata [496] "logic tdata[511:0]" +Toggle 1to0 tdata [496] "logic tdata[511:0]" +Toggle 0to1 tdata [497] "logic tdata[511:0]" +Toggle 1to0 tdata [497] "logic tdata[511:0]" +Toggle 0to1 tdata [498] "logic tdata[511:0]" +Toggle 1to0 tdata [498] "logic tdata[511:0]" +Toggle 0to1 tdata [499] "logic tdata[511:0]" +Toggle 1to0 tdata [499] "logic tdata[511:0]" +Toggle 0to1 tdata [500] "logic tdata[511:0]" +Toggle 1to0 tdata [500] "logic tdata[511:0]" +Toggle 0to1 tdata [501] "logic tdata[511:0]" +Toggle 1to0 tdata [501] "logic tdata[511:0]" +Toggle 0to1 tdata [502] "logic tdata[511:0]" +Toggle 1to0 tdata [502] "logic tdata[511:0]" +Toggle 0to1 tdata [503] "logic tdata[511:0]" +Toggle 1to0 tdata [503] "logic tdata[511:0]" +Toggle 0to1 tdata [504] "logic tdata[511:0]" +Toggle 1to0 tdata [504] "logic tdata[511:0]" +Toggle 0to1 tdata [505] "logic tdata[511:0]" +Toggle 1to0 tdata [505] "logic tdata[511:0]" +Toggle 0to1 tdata [506] "logic tdata[511:0]" +Toggle 1to0 tdata [506] "logic tdata[511:0]" +Toggle 0to1 tdata [507] "logic tdata[511:0]" +Toggle 1to0 tdata [507] "logic tdata[511:0]" +Toggle 0to1 tdata [508] "logic tdata[511:0]" +Toggle 1to0 tdata [508] "logic tdata[511:0]" +Toggle 0to1 tdata [509] "logic tdata[511:0]" +Toggle 1to0 tdata [509] "logic tdata[511:0]" +Toggle 0to1 tdata [510] "logic tdata[511:0]" +Toggle 1to0 tdata [510] "logic tdata[511:0]" +Toggle 0to1 tlast "logic tlast" +Toggle 1to0 tlast "logic tlast" +Toggle 0to1 tdata [40] "logic tdata[511:0]" +Toggle 1to0 tdata [40] "logic tdata[511:0]" +Toggle 0to1 tdata [32] "logic tdata[511:0]" +Toggle 1to0 tdata [32] "logic tdata[511:0]" +Toggle 0to1 tdata [33] "logic tdata[511:0]" +Toggle 1to0 tdata [33] "logic tdata[511:0]" +Toggle 0to1 tdata [34] "logic tdata[511:0]" +Toggle 1to0 tdata [34] "logic tdata[511:0]" +Toggle 0to1 tdata [35] "logic tdata[511:0]" +Toggle 1to0 tdata [35] "logic tdata[511:0]" +Toggle 0to1 tdata [36] "logic tdata[511:0]" +Toggle 1to0 tdata [36] "logic tdata[511:0]" +Toggle 0to1 tdata [37] "logic tdata[511:0]" +Toggle 1to0 tdata [37] "logic tdata[511:0]" +Toggle 0to1 tdata [38] "logic tdata[511:0]" +Toggle 1to0 tdata [38] "logic tdata[511:0]" +Toggle 0to1 tdata [39] "logic tdata[511:0]" +Toggle 1to0 tdata [39] "logic tdata[511:0]" +Toggle 0to1 tdata [128] "logic tdata[511:0]" +Toggle 1to0 tdata [128] "logic tdata[511:0]" +Toggle 0to1 tdata [129] "logic tdata[511:0]" +Toggle 1to0 tdata [129] "logic tdata[511:0]" +Toggle 0to1 tdata [130] "logic tdata[511:0]" +Toggle 1to0 tdata [130] "logic tdata[511:0]" +Toggle 0to1 tdata [131] "logic tdata[511:0]" +Toggle 1to0 tdata [131] "logic tdata[511:0]" +Toggle 0to1 tdata [132] "logic tdata[511:0]" +Toggle 1to0 tdata [132] "logic tdata[511:0]" +Toggle 0to1 tdata [133] "logic tdata[511:0]" +Toggle 1to0 tdata [133] "logic tdata[511:0]" +Toggle 0to1 tdata [134] "logic tdata[511:0]" +Toggle 1to0 tdata [134] "logic tdata[511:0]" +Toggle 0to1 tdata [135] "logic tdata[511:0]" +Toggle 1to0 tdata [135] "logic tdata[511:0]" +Toggle 0to1 tdata [136] "logic tdata[511:0]" +Toggle 1to0 tdata [136] "logic tdata[511:0]" +Toggle 0to1 tdata [137] "logic tdata[511:0]" +Toggle 1to0 tdata [137] "logic tdata[511:0]" +Toggle 0to1 tdata [138] "logic tdata[511:0]" +Toggle 1to0 tdata [138] "logic tdata[511:0]" +Toggle 0to1 tdata [139] "logic tdata[511:0]" +Toggle 1to0 tdata [139] "logic tdata[511:0]" +Toggle 0to1 tdata [140] "logic tdata[511:0]" +Toggle 1to0 tdata [140] "logic tdata[511:0]" +Toggle 0to1 tdata [141] "logic tdata[511:0]" +Toggle 1to0 tdata [141] "logic tdata[511:0]" +Toggle 0to1 tdata [142] "logic tdata[511:0]" +Toggle 1to0 tdata [142] "logic tdata[511:0]" +Toggle 0to1 tdata [143] "logic tdata[511:0]" +Toggle 1to0 tdata [143] "logic tdata[511:0]" +Toggle 0to1 tdata [144] "logic tdata[511:0]" +Toggle 1to0 tdata [144] "logic tdata[511:0]" +Toggle 0to1 tdata [145] "logic tdata[511:0]" +Toggle 1to0 tdata [145] "logic tdata[511:0]" +Toggle 0to1 tdata [146] "logic tdata[511:0]" +Toggle 1to0 tdata [146] "logic tdata[511:0]" +Toggle 0to1 tdata [147] "logic tdata[511:0]" +Toggle 1to0 tdata [147] "logic tdata[511:0]" +Toggle 0to1 tdata [148] "logic tdata[511:0]" +Toggle 1to0 tdata [148] "logic tdata[511:0]" +Toggle 0to1 tdata [149] "logic tdata[511:0]" +Toggle 1to0 tdata [149] "logic tdata[511:0]" +Toggle 0to1 tdata [150] "logic tdata[511:0]" +Toggle 1to0 tdata [150] "logic tdata[511:0]" +Toggle 0to1 tdata [151] "logic tdata[511:0]" +Toggle 1to0 tdata [151] "logic tdata[511:0]" +Toggle 0to1 tdata [152] "logic tdata[511:0]" +Toggle 1to0 tdata [152] "logic tdata[511:0]" +Toggle 0to1 tdata [153] "logic tdata[511:0]" +Toggle 1to0 tdata [153] "logic tdata[511:0]" +Toggle 0to1 tdata [154] "logic tdata[511:0]" +Toggle 1to0 tdata [154] "logic tdata[511:0]" +Toggle 0to1 tdata [155] "logic tdata[511:0]" +Toggle 1to0 tdata [155] "logic tdata[511:0]" +Toggle 0to1 tdata [156] "logic tdata[511:0]" +Toggle 1to0 tdata [156] "logic tdata[511:0]" +Toggle 0to1 tdata [157] "logic tdata[511:0]" +Toggle 1to0 tdata [157] "logic tdata[511:0]" +Toggle 0to1 tdata [158] "logic tdata[511:0]" +Toggle 1to0 tdata [158] "logic tdata[511:0]" +Toggle 0to1 tdata [173] "logic tdata[511:0]" +Toggle 1to0 tdata [173] "logic tdata[511:0]" +Toggle 0to1 tdata [162] "logic tdata[511:0]" +Toggle 1to0 tdata [162] "logic tdata[511:0]" +Toggle 0to1 tdata [163] "logic tdata[511:0]" +Toggle 1to0 tdata [163] "logic tdata[511:0]" +Toggle 0to1 tdata [164] "logic tdata[511:0]" +Toggle 1to0 tdata [164] "logic tdata[511:0]" +Toggle 0to1 tdata [165] "logic tdata[511:0]" +Toggle 1to0 tdata [165] "logic tdata[511:0]" +Toggle 0to1 tdata [166] "logic tdata[511:0]" +Toggle 1to0 tdata [166] "logic tdata[511:0]" +Toggle 0to1 tdata [167] "logic tdata[511:0]" +Toggle 1to0 tdata [167] "logic tdata[511:0]" +Toggle 0to1 tdata [168] "logic tdata[511:0]" +Toggle 1to0 tdata [168] "logic tdata[511:0]" +Toggle 0to1 tdata [169] "logic tdata[511:0]" +Toggle 1to0 tdata [169] "logic tdata[511:0]" +Toggle 0to1 tdata [170] "logic tdata[511:0]" +Toggle 1to0 tdata [170] "logic tdata[511:0]" +Toggle 0to1 tdata [171] "logic tdata[511:0]" +Toggle 1to0 tdata [171] "logic tdata[511:0]" +Toggle 0to1 tdata [172] "logic tdata[511:0]" +Toggle 1to0 tdata [172] "logic tdata[511:0]" +Toggle 0to1 tdata [175] "logic tdata[511:0]" +Toggle 1to0 tdata [175] "logic tdata[511:0]" +Toggle 0to1 tdata [176] "logic tdata[511:0]" +Toggle 1to0 tdata [176] "logic tdata[511:0]" +Toggle 0to1 tdata [177] "logic tdata[511:0]" +Toggle 1to0 tdata [177] "logic tdata[511:0]" +Toggle 0to1 tdata [178] "logic tdata[511:0]" +Toggle 1to0 tdata [178] "logic tdata[511:0]" +Toggle 0to1 tdata [179] "logic tdata[511:0]" +Toggle 1to0 tdata [179] "logic tdata[511:0]" +Toggle 0to1 tdata [180] "logic tdata[511:0]" +Toggle 1to0 tdata [180] "logic tdata[511:0]" +Toggle 0to1 tdata [181] "logic tdata[511:0]" +Toggle 1to0 tdata [181] "logic tdata[511:0]" +Toggle 0to1 tdata [182] "logic tdata[511:0]" +Toggle 1to0 tdata [182] "logic tdata[511:0]" +Toggle 0to1 tdata [183] "logic tdata[511:0]" +Toggle 1to0 tdata [183] "logic tdata[511:0]" +Toggle 0to1 tdata [184] "logic tdata[511:0]" +Toggle 1to0 tdata [184] "logic tdata[511:0]" +Toggle 0to1 tdata [185] "logic tdata[511:0]" +Toggle 1to0 tdata [185] "logic tdata[511:0]" +Toggle 0to1 tdata [186] "logic tdata[511:0]" +Toggle 1to0 tdata [186] "logic tdata[511:0]" +Toggle 0to1 tdata [187] "logic tdata[511:0]" +Toggle 1to0 tdata [187] "logic tdata[511:0]" +Toggle 0to1 tdata [188] "logic tdata[511:0]" +Toggle 1to0 tdata [188] "logic tdata[511:0]" +Toggle 0to1 tdata [189] "logic tdata[511:0]" +Toggle 1to0 tdata [189] "logic tdata[511:0]" +Toggle 0to1 tdata [190] "logic tdata[511:0]" +Toggle 1to0 tdata [190] "logic tdata[511:0]" +Toggle 0to1 tdata [191] "logic tdata[511:0]" +Toggle 1to0 tdata [191] "logic tdata[511:0]" +Toggle 0to1 tdata [192] "logic tdata[511:0]" +Toggle 1to0 tdata [192] "logic tdata[511:0]" +Toggle 0to1 tdata [193] "logic tdata[511:0]" +Toggle 1to0 tdata [193] "logic tdata[511:0]" +Toggle 0to1 tdata [194] "logic tdata[511:0]" +Toggle 1to0 tdata [194] "logic tdata[511:0]" +Toggle 0to1 tdata [195] "logic tdata[511:0]" +Toggle 1to0 tdata [195] "logic tdata[511:0]" +Toggle 0to1 tdata [196] "logic tdata[511:0]" +Toggle 1to0 tdata [196] "logic tdata[511:0]" +Toggle 0to1 tdata [197] "logic tdata[511:0]" +Toggle 1to0 tdata [197] "logic tdata[511:0]" +Toggle 0to1 tdata [198] "logic tdata[511:0]" +Toggle 1to0 tdata [198] "logic tdata[511:0]" +Toggle 0to1 tdata [199] "logic tdata[511:0]" +Toggle 1to0 tdata [199] "logic tdata[511:0]" +Toggle 0to1 tdata [200] "logic tdata[511:0]" +Toggle 1to0 tdata [200] "logic tdata[511:0]" +Toggle 0to1 tdata [201] "logic tdata[511:0]" +Toggle 1to0 tdata [201] "logic tdata[511:0]" +Toggle 0to1 tdata [202] "logic tdata[511:0]" +Toggle 1to0 tdata [202] "logic tdata[511:0]" +Toggle 0to1 tdata [203] "logic tdata[511:0]" +Toggle 1to0 tdata [203] "logic tdata[511:0]" +Toggle 0to1 tdata [204] "logic tdata[511:0]" +Toggle 1to0 tdata [204] "logic tdata[511:0]" +Toggle 0to1 tdata [205] "logic tdata[511:0]" +Toggle 1to0 tdata [205] "logic tdata[511:0]" +Toggle 0to1 tdata [206] "logic tdata[511:0]" +Toggle 1to0 tdata [206] "logic tdata[511:0]" +Toggle 0to1 tdata [207] "logic tdata[511:0]" +Toggle 1to0 tdata [207] "logic tdata[511:0]" +Toggle 0to1 tdata [208] "logic tdata[511:0]" +Toggle 1to0 tdata [208] "logic tdata[511:0]" +Toggle 0to1 tdata [209] "logic tdata[511:0]" +Toggle 1to0 tdata [209] "logic tdata[511:0]" +Toggle 0to1 tdata [210] "logic tdata[511:0]" +Toggle 1to0 tdata [210] "logic tdata[511:0]" +Toggle 0to1 tdata [211] "logic tdata[511:0]" +Toggle 1to0 tdata [211] "logic tdata[511:0]" +Toggle 0to1 tdata [212] "logic tdata[511:0]" +Toggle 1to0 tdata [212] "logic tdata[511:0]" +Toggle 0to1 tdata [213] "logic tdata[511:0]" +Toggle 1to0 tdata [213] "logic tdata[511:0]" +Toggle 0to1 tdata [214] "logic tdata[511:0]" +Toggle 1to0 tdata [214] "logic tdata[511:0]" +Toggle 0to1 tdata [215] "logic tdata[511:0]" +Toggle 1to0 tdata [215] "logic tdata[511:0]" +Toggle 0to1 tdata [216] "logic tdata[511:0]" +Toggle 1to0 tdata [216] "logic tdata[511:0]" +Toggle 0to1 tdata [217] "logic tdata[511:0]" +Toggle 1to0 tdata [217] "logic tdata[511:0]" +Toggle 0to1 tdata [218] "logic tdata[511:0]" +Toggle 1to0 tdata [218] "logic tdata[511:0]" +Toggle 0to1 tdata [219] "logic tdata[511:0]" +Toggle 1to0 tdata [219] "logic tdata[511:0]" +Toggle 0to1 tdata [220] "logic tdata[511:0]" +Toggle 1to0 tdata [220] "logic tdata[511:0]" +Toggle 0to1 tdata [221] "logic tdata[511:0]" +Toggle 1to0 tdata [221] "logic tdata[511:0]" +Toggle 0to1 tdata [222] "logic tdata[511:0]" +Toggle 1to0 tdata [222] "logic tdata[511:0]" +Toggle 0to1 tdata [223] "logic tdata[511:0]" +Toggle 1to0 tdata [223] "logic tdata[511:0]" +Toggle 0to1 tdata [0] "logic tdata[511:0]" +Toggle 1to0 tdata [0] "logic tdata[511:0]" +Toggle 0to1 tdata [1] "logic tdata[511:0]" +Toggle 1to0 tdata [1] "logic tdata[511:0]" +Toggle 0to1 tdata [2] "logic tdata[511:0]" +Toggle 1to0 tdata [2] "logic tdata[511:0]" +Toggle 0to1 tdata [3] "logic tdata[511:0]" +Toggle 1to0 tdata [3] "logic tdata[511:0]" +Toggle 0to1 tdata [10] "logic tdata[511:0]" +Toggle 1to0 tdata [10] "logic tdata[511:0]" +Toggle 0to1 tdata [11] "logic tdata[511:0]" +Toggle 1to0 tdata [11] "logic tdata[511:0]" +Toggle 0to1 tdata [12] "logic tdata[511:0]" +Toggle 1to0 tdata [12] "logic tdata[511:0]" +Toggle 0to1 tdata [13] "logic tdata[511:0]" +Toggle 1to0 tdata [13] "logic tdata[511:0]" +Toggle 0to1 tdata [14] "logic tdata[511:0]" +Toggle 1to0 tdata [14] "logic tdata[511:0]" +Toggle 0to1 tdata [15] "logic tdata[511:0]" +Toggle 1to0 tdata [15] "logic tdata[511:0]" +Toggle 0to1 tdata [16] "logic tdata[511:0]" +Toggle 1to0 tdata [16] "logic tdata[511:0]" +Toggle 0to1 tdata [17] "logic tdata[511:0]" +Toggle 1to0 tdata [17] "logic tdata[511:0]" +Toggle 0to1 tdata [18] "logic tdata[511:0]" +Toggle 1to0 tdata [18] "logic tdata[511:0]" +Toggle 0to1 tdata [19] "logic tdata[511:0]" +Toggle 1to0 tdata [19] "logic tdata[511:0]" +Toggle 0to1 tdata [111] "logic tdata[511:0]" +Toggle 1to0 tdata [111] "logic tdata[511:0]" +Toggle 0to1 tdata [64] "logic tdata[511:0]" +Toggle 1to0 tdata [64] "logic tdata[511:0]" +Toggle 0to1 tdata [65] "logic tdata[511:0]" +Toggle 1to0 tdata [65] "logic tdata[511:0]" +Toggle 0to1 tdata [66] "logic tdata[511:0]" +Toggle 1to0 tdata [66] "logic tdata[511:0]" +Toggle 0to1 tdata [67] "logic tdata[511:0]" +Toggle 1to0 tdata [67] "logic tdata[511:0]" +Toggle 0to1 tdata [68] "logic tdata[511:0]" +Toggle 1to0 tdata [68] "logic tdata[511:0]" +Toggle 0to1 tdata [69] "logic tdata[511:0]" +Toggle 1to0 tdata [69] "logic tdata[511:0]" +Toggle 0to1 tdata [70] "logic tdata[511:0]" +Toggle 1to0 tdata [70] "logic tdata[511:0]" +Toggle 0to1 tdata [71] "logic tdata[511:0]" +Toggle 1to0 tdata [71] "logic tdata[511:0]" +Toggle 0to1 tdata [72] "logic tdata[511:0]" +Toggle 1to0 tdata [72] "logic tdata[511:0]" +Toggle 0to1 tdata [73] "logic tdata[511:0]" +Toggle 1to0 tdata [73] "logic tdata[511:0]" +Toggle 0to1 tdata [74] "logic tdata[511:0]" +Toggle 1to0 tdata [74] "logic tdata[511:0]" +Toggle 0to1 tdata [75] "logic tdata[511:0]" +Toggle 1to0 tdata [75] "logic tdata[511:0]" +Toggle 0to1 tdata [76] "logic tdata[511:0]" +Toggle 1to0 tdata [76] "logic tdata[511:0]" +Toggle 0to1 tdata [77] "logic tdata[511:0]" +Toggle 1to0 tdata [77] "logic tdata[511:0]" +Toggle 0to1 tdata [78] "logic tdata[511:0]" +Toggle 1to0 tdata [78] "logic tdata[511:0]" +Toggle 0to1 tdata [79] "logic tdata[511:0]" +Toggle 1to0 tdata [79] "logic tdata[511:0]" +Toggle 0to1 tdata [80] "logic tdata[511:0]" +Toggle 1to0 tdata [80] "logic tdata[511:0]" +Toggle 0to1 tdata [81] "logic tdata[511:0]" +Toggle 1to0 tdata [81] "logic tdata[511:0]" +Toggle 0to1 tdata [82] "logic tdata[511:0]" +Toggle 1to0 tdata [82] "logic tdata[511:0]" +Toggle 0to1 tdata [83] "logic tdata[511:0]" +Toggle 1to0 tdata [83] "logic tdata[511:0]" +Toggle 0to1 tdata [84] "logic tdata[511:0]" +Toggle 1to0 tdata [84] "logic tdata[511:0]" +Toggle 0to1 tdata [85] "logic tdata[511:0]" +Toggle 1to0 tdata [85] "logic tdata[511:0]" +Toggle 0to1 tdata [86] "logic tdata[511:0]" +Toggle 1to0 tdata [86] "logic tdata[511:0]" +Toggle 0to1 tdata [87] "logic tdata[511:0]" +Toggle 1to0 tdata [87] "logic tdata[511:0]" +Toggle 0to1 tdata [88] "logic tdata[511:0]" +Toggle 1to0 tdata [88] "logic tdata[511:0]" +Toggle 0to1 tdata [89] "logic tdata[511:0]" +Toggle 1to0 tdata [89] "logic tdata[511:0]" +Toggle 0to1 tdata [90] "logic tdata[511:0]" +Toggle 1to0 tdata [90] "logic tdata[511:0]" +Toggle 0to1 tdata [91] "logic tdata[511:0]" +Toggle 1to0 tdata [91] "logic tdata[511:0]" +Toggle 0to1 tdata [92] "logic tdata[511:0]" +Toggle 1to0 tdata [92] "logic tdata[511:0]" +Toggle 0to1 tdata [93] "logic tdata[511:0]" +Toggle 1to0 tdata [93] "logic tdata[511:0]" +Toggle 0to1 tdata [94] "logic tdata[511:0]" +Toggle 1to0 tdata [94] "logic tdata[511:0]" +Toggle 0to1 tdata [95] "logic tdata[511:0]" +Toggle 1to0 tdata [95] "logic tdata[511:0]" +Toggle 0to1 tdata [96] "logic tdata[511:0]" +Toggle 1to0 tdata [96] "logic tdata[511:0]" +Toggle 0to1 tdata [97] "logic tdata[511:0]" +Toggle 1to0 tdata [97] "logic tdata[511:0]" +Toggle 0to1 tdata [98] "logic tdata[511:0]" +Toggle 1to0 tdata [98] "logic tdata[511:0]" +Toggle 0to1 tdata [99] "logic tdata[511:0]" +Toggle 1to0 tdata [99] "logic tdata[511:0]" +Toggle 0to1 tdata [100] "logic tdata[511:0]" +Toggle 1to0 tdata [100] "logic tdata[511:0]" +Toggle 0to1 tdata [101] "logic tdata[511:0]" +Toggle 1to0 tdata [101] "logic tdata[511:0]" +Toggle 0to1 tdata [102] "logic tdata[511:0]" +Toggle 1to0 tdata [102] "logic tdata[511:0]" +Toggle 0to1 tdata [103] "logic tdata[511:0]" +Toggle 1to0 tdata [103] "logic tdata[511:0]" +Toggle 0to1 tdata [104] "logic tdata[511:0]" +Toggle 1to0 tdata [104] "logic tdata[511:0]" +Toggle 0to1 tdata [105] "logic tdata[511:0]" +Toggle 1to0 tdata [105] "logic tdata[511:0]" +Toggle 0to1 tdata [106] "logic tdata[511:0]" +Toggle 1to0 tdata [106] "logic tdata[511:0]" +Toggle 0to1 tdata [107] "logic tdata[511:0]" +Toggle 1to0 tdata [107] "logic tdata[511:0]" +Toggle 0to1 tdata [108] "logic tdata[511:0]" +Toggle 1to0 tdata [108] "logic tdata[511:0]" +Toggle 0to1 tdata [109] "logic tdata[511:0]" +Toggle 1to0 tdata [109] "logic tdata[511:0]" +Toggle 0to1 tdata [110] "logic tdata[511:0]" +Toggle 1to0 tdata [110] "logic tdata[511:0]" +Toggle 0to1 tdata [63] "logic tdata[511:0]" +Toggle 1to0 tdata [63] "logic tdata[511:0]" +Toggle 0to1 tdata [48] "logic tdata[511:0]" +Toggle 1to0 tdata [48] "logic tdata[511:0]" +Toggle 0to1 tdata [49] "logic tdata[511:0]" +Toggle 1to0 tdata [49] "logic tdata[511:0]" +Toggle 0to1 tdata [50] "logic tdata[511:0]" +Toggle 1to0 tdata [50] "logic tdata[511:0]" +Toggle 0to1 tdata [51] "logic tdata[511:0]" +Toggle 1to0 tdata [51] "logic tdata[511:0]" +Toggle 0to1 tdata [52] "logic tdata[511:0]" +Toggle 1to0 tdata [52] "logic tdata[511:0]" +Toggle 0to1 tdata [53] "logic tdata[511:0]" +Toggle 1to0 tdata [53] "logic tdata[511:0]" +Toggle 0to1 tdata [54] "logic tdata[511:0]" +Toggle 1to0 tdata [54] "logic tdata[511:0]" +Toggle 0to1 tdata [55] "logic tdata[511:0]" +Toggle 1to0 tdata [55] "logic tdata[511:0]" +Toggle 0to1 tdata [56] "logic tdata[511:0]" +Toggle 1to0 tdata [56] "logic tdata[511:0]" +Toggle 0to1 tdata [57] "logic tdata[511:0]" +Toggle 1to0 tdata [57] "logic tdata[511:0]" +Toggle 0to1 tdata [58] "logic tdata[511:0]" +Toggle 1to0 tdata [58] "logic tdata[511:0]" +Toggle 0to1 tdata [59] "logic tdata[511:0]" +Toggle 1to0 tdata [59] "logic tdata[511:0]" +Toggle 0to1 tdata [60] "logic tdata[511:0]" +Toggle 1to0 tdata [60] "logic tdata[511:0]" +Toggle 0to1 tdata [61] "logic tdata[511:0]" +Toggle 1to0 tdata [61] "logic tdata[511:0]" +Toggle 0to1 tdata [62] "logic tdata[511:0]" +Toggle 1to0 tdata [62] "logic tdata[511:0]" +Toggle 0to1 tdata [21] "logic tdata[511:0]" +Toggle 1to0 tdata [21] "logic tdata[511:0]" +Toggle 0to1 tdata [22] "logic tdata[511:0]" +Toggle 1to0 tdata [22] "logic tdata[511:0]" +Toggle 0to1 tdata [23] "logic tdata[511:0]" +Toggle 1to0 tdata [23] "logic tdata[511:0]" +Toggle 0to1 tdata [24] "logic tdata[511:0]" +Toggle 1to0 tdata [24] "logic tdata[511:0]" +Toggle 0to1 tdata [25] "logic tdata[511:0]" +Toggle 1to0 tdata [25] "logic tdata[511:0]" +Toggle 0to1 tdata [26] "logic tdata[511:0]" +Toggle 1to0 tdata [26] "logic tdata[511:0]" +Toggle 0to1 tdata [27] "logic tdata[511:0]" +Toggle 1to0 tdata [27] "logic tdata[511:0]" +Toggle 0to1 tdata [28] "logic tdata[511:0]" +Toggle 1to0 tdata [28] "logic tdata[511:0]" +Toggle 0to1 tdata [29] "logic tdata[511:0]" +Toggle 1to0 tdata [29] "logic tdata[511:0]" +Toggle 0to1 tdata [30] "logic tdata[511:0]" +Toggle 1to0 tdata [30] "logic tdata[511:0]" +Toggle 0to1 tdata [31] "logic tdata[511:0]" +Toggle 1to0 tdata [31] "logic tdata[511:0]" +Toggle 0to1 tdata [41] "logic tdata[511:0]" +Toggle 1to0 tdata [41] "logic tdata[511:0]" +Toggle 0to1 tdata [42] "logic tdata[511:0]" +Toggle 1to0 tdata [42] "logic tdata[511:0]" +Toggle 0to1 tdata [43] "logic tdata[511:0]" +Toggle 1to0 tdata [43] "logic tdata[511:0]" +Toggle 0to1 tdata [44] "logic tdata[511:0]" +Toggle 1to0 tdata [44] "logic tdata[511:0]" +Toggle 0to1 tdata [45] "logic tdata[511:0]" +Toggle 1to0 tdata [45] "logic tdata[511:0]" +Toggle 0to1 tdata [46] "logic tdata[511:0]" +Toggle 1to0 tdata [46] "logic tdata[511:0]" +Toggle 0to1 tdata [47] "logic tdata[511:0]" +Toggle 1to0 tdata [47] "logic tdata[511:0]" +Toggle 0to1 tdata [160] "logic tdata[511:0]" +Toggle 1to0 tdata [160] "logic tdata[511:0]" +Toggle 0to1 tdata [159] "logic tdata[511:0]" +Toggle 1to0 tdata [159] "logic tdata[511:0]" +Toggle 0to1 tdata [7] "logic tdata[511:0]" +Toggle 1to0 tdata [7] "logic tdata[511:0]" +Toggle 0to1 tdata [8] "logic tdata[511:0]" +Toggle 1to0 tdata [8] "logic tdata[511:0]" +Toggle 0to1 tdata [9] "logic tdata[511:0]" +Toggle 1to0 tdata [9] "logic tdata[511:0]" +Toggle 0to1 tdata [117] "logic tdata[511:0]" +Toggle 1to0 tdata [117] "logic tdata[511:0]" +Toggle 0to1 tdata [112] "logic tdata[511:0]" +Toggle 1to0 tdata [112] "logic tdata[511:0]" +Toggle 0to1 tdata [113] "logic tdata[511:0]" +Toggle 1to0 tdata [113] "logic tdata[511:0]" +Toggle 0to1 tdata [114] "logic tdata[511:0]" +Toggle 1to0 tdata [114] "logic tdata[511:0]" +Toggle 0to1 tdata [115] "logic tdata[511:0]" +Toggle 1to0 tdata [115] "logic tdata[511:0]" +Toggle 0to1 tdata [116] "logic tdata[511:0]" +Toggle 1to0 tdata [116] "logic tdata[511:0]" +Toggle 0to1 tdata [6] "logic tdata[511:0]" +Toggle 1to0 tdata [6] "logic tdata[511:0]" +Toggle 0to1 tdata [126] "logic tdata[511:0]" +Toggle 1to0 tdata [126] "logic tdata[511:0]" +Toggle 0to1 tdata [127] "logic tdata[511:0]" +Toggle 1to0 tdata [127] "logic tdata[511:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.local_commit.commit_skid.r.axis_pl[0] +Toggle tkeep "logic tkeep[63:0]" +ANNOTATION: " Constant value as 'h1 for DM mode. " +Toggle tuser_vendor "logic tuser_vendor[9:0]" +Toggle 0to1 tdata [511] "logic tdata[511:0]" +Toggle 1to0 tdata [511] "logic tdata[511:0]" +Toggle 0to1 tdata [0] "logic tdata[511:0]" +Toggle 1to0 tdata [0] "logic tdata[511:0]" +Toggle 0to1 tdata [1] "logic tdata[511:0]" +Toggle 1to0 tdata [1] "logic tdata[511:0]" +Toggle 0to1 tdata [2] "logic tdata[511:0]" +Toggle 1to0 tdata [2] "logic tdata[511:0]" +Toggle 0to1 tdata [3] "logic tdata[511:0]" +Toggle 1to0 tdata [3] "logic tdata[511:0]" +Toggle 0to1 tdata [7] "logic tdata[511:0]" +Toggle 1to0 tdata [7] "logic tdata[511:0]" +Toggle 0to1 tdata [8] "logic tdata[511:0]" +Toggle 1to0 tdata [8] "logic tdata[511:0]" +Toggle 0to1 tdata [9] "logic tdata[511:0]" +Toggle 1to0 tdata [9] "logic tdata[511:0]" +Toggle 0to1 tdata [10] "logic tdata[511:0]" +Toggle 1to0 tdata [10] "logic tdata[511:0]" +Toggle 0to1 tdata [11] "logic tdata[511:0]" +Toggle 1to0 tdata [11] "logic tdata[511:0]" +Toggle 0to1 tdata [12] "logic tdata[511:0]" +Toggle 1to0 tdata [12] "logic tdata[511:0]" +Toggle 0to1 tdata [13] "logic tdata[511:0]" +Toggle 1to0 tdata [13] "logic tdata[511:0]" +Toggle 0to1 tdata [14] "logic tdata[511:0]" +Toggle 1to0 tdata [14] "logic tdata[511:0]" +Toggle 0to1 tdata [15] "logic tdata[511:0]" +Toggle 1to0 tdata [15] "logic tdata[511:0]" +Toggle 0to1 tdata [16] "logic tdata[511:0]" +Toggle 1to0 tdata [16] "logic tdata[511:0]" +Toggle 0to1 tdata [17] "logic tdata[511:0]" +Toggle 1to0 tdata [17] "logic tdata[511:0]" +Toggle 0to1 tdata [18] "logic tdata[511:0]" +Toggle 1to0 tdata [18] "logic tdata[511:0]" +Toggle 0to1 tdata [19] "logic tdata[511:0]" +Toggle 1to0 tdata [19] "logic tdata[511:0]" +Toggle 0to1 tdata [21] "logic tdata[511:0]" +Toggle 1to0 tdata [21] "logic tdata[511:0]" +Toggle 0to1 tdata [22] "logic tdata[511:0]" +Toggle 1to0 tdata [22] "logic tdata[511:0]" +Toggle 0to1 tdata [23] "logic tdata[511:0]" +Toggle 1to0 tdata [23] "logic tdata[511:0]" +Toggle 0to1 tdata [24] "logic tdata[511:0]" +Toggle 1to0 tdata [24] "logic tdata[511:0]" +Toggle 0to1 tdata [25] "logic tdata[511:0]" +Toggle 1to0 tdata [25] "logic tdata[511:0]" +Toggle 0to1 tdata [26] "logic tdata[511:0]" +Toggle 1to0 tdata [26] "logic tdata[511:0]" +Toggle 0to1 tdata [27] "logic tdata[511:0]" +Toggle 1to0 tdata [27] "logic tdata[511:0]" +Toggle 0to1 tdata [28] "logic tdata[511:0]" +Toggle 1to0 tdata [28] "logic tdata[511:0]" +Toggle 0to1 tdata [29] "logic tdata[511:0]" +Toggle 1to0 tdata [29] "logic tdata[511:0]" +Toggle 0to1 tdata [30] "logic tdata[511:0]" +Toggle 1to0 tdata [30] "logic tdata[511:0]" +Toggle 0to1 tdata [31] "logic tdata[511:0]" +Toggle 1to0 tdata [31] "logic tdata[511:0]" +Toggle 0to1 tdata [32] "logic tdata[511:0]" +Toggle 1to0 tdata [32] "logic tdata[511:0]" +Toggle 0to1 tdata [33] "logic tdata[511:0]" +Toggle 1to0 tdata [33] "logic tdata[511:0]" +Toggle 0to1 tdata [34] "logic tdata[511:0]" +Toggle 1to0 tdata [34] "logic tdata[511:0]" +Toggle 0to1 tdata [35] "logic tdata[511:0]" +Toggle 1to0 tdata [35] "logic tdata[511:0]" +Toggle 0to1 tdata [36] "logic tdata[511:0]" +Toggle 1to0 tdata [36] "logic tdata[511:0]" +Toggle 0to1 tdata [37] "logic tdata[511:0]" +Toggle 1to0 tdata [37] "logic tdata[511:0]" +Toggle 0to1 tdata [38] "logic tdata[511:0]" +Toggle 1to0 tdata [38] "logic tdata[511:0]" +Toggle 0to1 tdata [39] "logic tdata[511:0]" +Toggle 1to0 tdata [39] "logic tdata[511:0]" +Toggle 0to1 tdata [40] "logic tdata[511:0]" +Toggle 1to0 tdata [40] "logic tdata[511:0]" +Toggle 0to1 tdata [41] "logic tdata[511:0]" +Toggle 1to0 tdata [41] "logic tdata[511:0]" +Toggle 0to1 tdata [42] "logic tdata[511:0]" +Toggle 1to0 tdata [42] "logic tdata[511:0]" +Toggle 0to1 tdata [43] "logic tdata[511:0]" +Toggle 1to0 tdata [43] "logic tdata[511:0]" +Toggle 0to1 tdata [44] "logic tdata[511:0]" +Toggle 1to0 tdata [44] "logic tdata[511:0]" +Toggle 0to1 tdata [45] "logic tdata[511:0]" +Toggle 1to0 tdata [45] "logic tdata[511:0]" +Toggle 0to1 tdata [46] "logic tdata[511:0]" +Toggle 1to0 tdata [46] "logic tdata[511:0]" +Toggle 0to1 tdata [47] "logic tdata[511:0]" +Toggle 1to0 tdata [47] "logic tdata[511:0]" +Toggle 0to1 tdata [48] "logic tdata[511:0]" +Toggle 1to0 tdata [48] "logic tdata[511:0]" +Toggle 0to1 tdata [49] "logic tdata[511:0]" +Toggle 1to0 tdata [49] "logic tdata[511:0]" +Toggle 0to1 tdata [50] "logic tdata[511:0]" +Toggle 1to0 tdata [50] "logic tdata[511:0]" +Toggle 0to1 tdata [51] "logic tdata[511:0]" +Toggle 1to0 tdata [51] "logic tdata[511:0]" +Toggle 0to1 tdata [52] "logic tdata[511:0]" +Toggle 1to0 tdata [52] "logic tdata[511:0]" +Toggle 0to1 tdata [53] "logic tdata[511:0]" +Toggle 1to0 tdata [53] "logic tdata[511:0]" +Toggle 0to1 tdata [54] "logic tdata[511:0]" +Toggle 1to0 tdata [54] "logic tdata[511:0]" +Toggle 0to1 tdata [55] "logic tdata[511:0]" +Toggle 1to0 tdata [55] "logic tdata[511:0]" +Toggle 0to1 tdata [56] "logic tdata[511:0]" +Toggle 1to0 tdata [56] "logic tdata[511:0]" +Toggle 0to1 tdata [57] "logic tdata[511:0]" +Toggle 1to0 tdata [57] "logic tdata[511:0]" +Toggle 0to1 tdata [58] "logic tdata[511:0]" +Toggle 1to0 tdata [58] "logic tdata[511:0]" +Toggle 0to1 tdata [59] "logic tdata[511:0]" +Toggle 1to0 tdata [59] "logic tdata[511:0]" +Toggle 0to1 tdata [60] "logic tdata[511:0]" +Toggle 1to0 tdata [60] "logic tdata[511:0]" +Toggle 0to1 tdata [61] "logic tdata[511:0]" +Toggle 1to0 tdata [61] "logic tdata[511:0]" +Toggle 0to1 tdata [62] "logic tdata[511:0]" +Toggle 1to0 tdata [62] "logic tdata[511:0]" +Toggle 0to1 tdata [63] "logic tdata[511:0]" +Toggle 1to0 tdata [63] "logic tdata[511:0]" +Toggle 0to1 tdata [64] "logic tdata[511:0]" +Toggle 1to0 tdata [64] "logic tdata[511:0]" +Toggle 0to1 tdata [65] "logic tdata[511:0]" +Toggle 1to0 tdata [65] "logic tdata[511:0]" +Toggle 0to1 tdata [66] "logic tdata[511:0]" +Toggle 1to0 tdata [66] "logic tdata[511:0]" +Toggle 0to1 tdata [67] "logic tdata[511:0]" +Toggle 1to0 tdata [67] "logic tdata[511:0]" +Toggle 0to1 tdata [68] "logic tdata[511:0]" +Toggle 1to0 tdata [68] "logic tdata[511:0]" +Toggle 0to1 tdata [69] "logic tdata[511:0]" +Toggle 1to0 tdata [69] "logic tdata[511:0]" +Toggle 0to1 tdata [70] "logic tdata[511:0]" +Toggle 1to0 tdata [70] "logic tdata[511:0]" +Toggle 0to1 tdata [71] "logic tdata[511:0]" +Toggle 1to0 tdata [71] "logic tdata[511:0]" +Toggle 0to1 tdata [72] "logic tdata[511:0]" +Toggle 1to0 tdata [72] "logic tdata[511:0]" +Toggle 0to1 tdata [73] "logic tdata[511:0]" +Toggle 1to0 tdata [73] "logic tdata[511:0]" +Toggle 0to1 tdata [74] "logic tdata[511:0]" +Toggle 1to0 tdata [74] "logic tdata[511:0]" +Toggle 0to1 tdata [75] "logic tdata[511:0]" +Toggle 1to0 tdata [75] "logic tdata[511:0]" +Toggle 0to1 tdata [76] "logic tdata[511:0]" +Toggle 1to0 tdata [76] "logic tdata[511:0]" +Toggle 0to1 tdata [77] "logic tdata[511:0]" +Toggle 1to0 tdata [77] "logic tdata[511:0]" +Toggle 0to1 tdata [78] "logic tdata[511:0]" +Toggle 1to0 tdata [78] "logic tdata[511:0]" +Toggle 0to1 tdata [79] "logic tdata[511:0]" +Toggle 1to0 tdata [79] "logic tdata[511:0]" +Toggle 0to1 tdata [80] "logic tdata[511:0]" +Toggle 1to0 tdata [80] "logic tdata[511:0]" +Toggle 0to1 tdata [81] "logic tdata[511:0]" +Toggle 1to0 tdata [81] "logic tdata[511:0]" +Toggle 0to1 tdata [82] "logic tdata[511:0]" +Toggle 1to0 tdata [82] "logic tdata[511:0]" +Toggle 0to1 tdata [83] "logic tdata[511:0]" +Toggle 1to0 tdata [83] "logic tdata[511:0]" +Toggle 0to1 tdata [84] "logic tdata[511:0]" +Toggle 1to0 tdata [84] "logic tdata[511:0]" +Toggle 0to1 tdata [85] "logic tdata[511:0]" +Toggle 1to0 tdata [85] "logic tdata[511:0]" +Toggle 0to1 tdata [86] "logic tdata[511:0]" +Toggle 1to0 tdata [86] "logic tdata[511:0]" +Toggle 0to1 tdata [87] "logic tdata[511:0]" +Toggle 1to0 tdata [87] "logic tdata[511:0]" +Toggle 0to1 tdata [88] "logic tdata[511:0]" +Toggle 1to0 tdata [88] "logic tdata[511:0]" +Toggle 0to1 tdata [89] "logic tdata[511:0]" +Toggle 1to0 tdata [89] "logic tdata[511:0]" +Toggle 0to1 tdata [90] "logic tdata[511:0]" +Toggle 1to0 tdata [90] "logic tdata[511:0]" +Toggle 0to1 tdata [91] "logic tdata[511:0]" +Toggle 1to0 tdata [91] "logic tdata[511:0]" +Toggle 0to1 tdata [92] "logic tdata[511:0]" +Toggle 1to0 tdata [92] "logic tdata[511:0]" +Toggle 0to1 tdata [93] "logic tdata[511:0]" +Toggle 1to0 tdata [93] "logic tdata[511:0]" +Toggle 0to1 tdata [94] "logic tdata[511:0]" +Toggle 1to0 tdata [94] "logic tdata[511:0]" +Toggle 0to1 tdata [95] "logic tdata[511:0]" +Toggle 1to0 tdata [95] "logic tdata[511:0]" +Toggle 0to1 tdata [96] "logic tdata[511:0]" +Toggle 1to0 tdata [96] "logic tdata[511:0]" +Toggle 0to1 tdata [97] "logic tdata[511:0]" +Toggle 1to0 tdata [97] "logic tdata[511:0]" +Toggle 0to1 tdata [98] "logic tdata[511:0]" +Toggle 1to0 tdata [98] "logic tdata[511:0]" +Toggle 0to1 tdata [99] "logic tdata[511:0]" +Toggle 1to0 tdata [99] "logic tdata[511:0]" +Toggle 0to1 tdata [100] "logic tdata[511:0]" +Toggle 1to0 tdata [100] "logic tdata[511:0]" +Toggle 0to1 tdata [101] "logic tdata[511:0]" +Toggle 1to0 tdata [101] "logic tdata[511:0]" +Toggle 0to1 tdata [102] "logic tdata[511:0]" +Toggle 1to0 tdata [102] "logic tdata[511:0]" +Toggle 0to1 tdata [103] "logic tdata[511:0]" +Toggle 1to0 tdata [103] "logic tdata[511:0]" +Toggle 0to1 tdata [104] "logic tdata[511:0]" +Toggle 1to0 tdata [104] "logic tdata[511:0]" +Toggle 0to1 tdata [105] "logic tdata[511:0]" +Toggle 1to0 tdata [105] "logic tdata[511:0]" +Toggle 0to1 tdata [106] "logic tdata[511:0]" +Toggle 1to0 tdata [106] "logic tdata[511:0]" +Toggle 0to1 tdata [107] "logic tdata[511:0]" +Toggle 1to0 tdata [107] "logic tdata[511:0]" +Toggle 0to1 tdata [108] "logic tdata[511:0]" +Toggle 1to0 tdata [108] "logic tdata[511:0]" +Toggle 0to1 tdata [109] "logic tdata[511:0]" +Toggle 1to0 tdata [109] "logic tdata[511:0]" +Toggle 0to1 tdata [110] "logic tdata[511:0]" +Toggle 1to0 tdata [110] "logic tdata[511:0]" +Toggle 0to1 tdata [111] "logic tdata[511:0]" +Toggle 1to0 tdata [111] "logic tdata[511:0]" +Toggle 0to1 tdata [112] "logic tdata[511:0]" +Toggle 1to0 tdata [112] "logic tdata[511:0]" +Toggle 0to1 tdata [113] "logic tdata[511:0]" +Toggle 1to0 tdata [113] "logic tdata[511:0]" +Toggle 0to1 tdata [114] "logic tdata[511:0]" +Toggle 1to0 tdata [114] "logic tdata[511:0]" +Toggle 0to1 tdata [115] "logic tdata[511:0]" +Toggle 1to0 tdata [115] "logic tdata[511:0]" +Toggle 0to1 tdata [116] "logic tdata[511:0]" +Toggle 1to0 tdata [116] "logic tdata[511:0]" +Toggle 0to1 tdata [117] "logic tdata[511:0]" +Toggle 1to0 tdata [117] "logic tdata[511:0]" +Toggle 0to1 tdata [126] "logic tdata[511:0]" +Toggle 1to0 tdata [126] "logic tdata[511:0]" +Toggle 0to1 tdata [127] "logic tdata[511:0]" +Toggle 1to0 tdata [127] "logic tdata[511:0]" +Toggle 0to1 tdata [128] "logic tdata[511:0]" +Toggle 1to0 tdata [128] "logic tdata[511:0]" +Toggle 0to1 tdata [129] "logic tdata[511:0]" +Toggle 1to0 tdata [129] "logic tdata[511:0]" +Toggle 0to1 tdata [130] "logic tdata[511:0]" +Toggle 1to0 tdata [130] "logic tdata[511:0]" +Toggle 0to1 tdata [131] "logic tdata[511:0]" +Toggle 1to0 tdata [131] "logic tdata[511:0]" +Toggle 0to1 tdata [132] "logic tdata[511:0]" +Toggle 1to0 tdata [132] "logic tdata[511:0]" +Toggle 0to1 tdata [133] "logic tdata[511:0]" +Toggle 1to0 tdata [133] "logic tdata[511:0]" +Toggle 0to1 tdata [134] "logic tdata[511:0]" +Toggle 1to0 tdata [134] "logic tdata[511:0]" +Toggle 0to1 tdata [135] "logic tdata[511:0]" +Toggle 1to0 tdata [135] "logic tdata[511:0]" +Toggle 0to1 tdata [136] "logic tdata[511:0]" +Toggle 1to0 tdata [136] "logic tdata[511:0]" +Toggle 0to1 tdata [137] "logic tdata[511:0]" +Toggle 1to0 tdata [137] "logic tdata[511:0]" +Toggle 0to1 tdata [138] "logic tdata[511:0]" +Toggle 1to0 tdata [138] "logic tdata[511:0]" +Toggle 0to1 tdata [139] "logic tdata[511:0]" +Toggle 1to0 tdata [139] "logic tdata[511:0]" +Toggle 0to1 tdata [140] "logic tdata[511:0]" +Toggle 1to0 tdata [140] "logic tdata[511:0]" +Toggle 0to1 tdata [141] "logic tdata[511:0]" +Toggle 1to0 tdata [141] "logic tdata[511:0]" +Toggle 0to1 tdata [142] "logic tdata[511:0]" +Toggle 1to0 tdata [142] "logic tdata[511:0]" +Toggle 0to1 tdata [143] "logic tdata[511:0]" +Toggle 1to0 tdata [143] "logic tdata[511:0]" +Toggle 0to1 tdata [144] "logic tdata[511:0]" +Toggle 1to0 tdata [144] "logic tdata[511:0]" +Toggle 0to1 tdata [145] "logic tdata[511:0]" +Toggle 1to0 tdata [145] "logic tdata[511:0]" +Toggle 0to1 tdata [146] "logic tdata[511:0]" +Toggle 1to0 tdata [146] "logic tdata[511:0]" +Toggle 0to1 tdata [147] "logic tdata[511:0]" +Toggle 1to0 tdata [147] "logic tdata[511:0]" +Toggle 0to1 tdata [148] "logic tdata[511:0]" +Toggle 1to0 tdata [148] "logic tdata[511:0]" +Toggle 0to1 tdata [149] "logic tdata[511:0]" +Toggle 1to0 tdata [149] "logic tdata[511:0]" +Toggle 0to1 tdata [150] "logic tdata[511:0]" +Toggle 1to0 tdata [150] "logic tdata[511:0]" +Toggle 0to1 tdata [151] "logic tdata[511:0]" +Toggle 1to0 tdata [151] "logic tdata[511:0]" +Toggle 0to1 tdata [152] "logic tdata[511:0]" +Toggle 1to0 tdata [152] "logic tdata[511:0]" +Toggle 0to1 tdata [153] "logic tdata[511:0]" +Toggle 1to0 tdata [153] "logic tdata[511:0]" +Toggle 0to1 tdata [154] "logic tdata[511:0]" +Toggle 1to0 tdata [154] "logic tdata[511:0]" +Toggle 0to1 tdata [155] "logic tdata[511:0]" +Toggle 1to0 tdata [155] "logic tdata[511:0]" +Toggle 0to1 tdata [156] "logic tdata[511:0]" +Toggle 1to0 tdata [156] "logic tdata[511:0]" +Toggle 0to1 tdata [157] "logic tdata[511:0]" +Toggle 1to0 tdata [157] "logic tdata[511:0]" +Toggle 0to1 tdata [158] "logic tdata[511:0]" +Toggle 1to0 tdata [158] "logic tdata[511:0]" +Toggle 0to1 tdata [159] "logic tdata[511:0]" +Toggle 1to0 tdata [159] "logic tdata[511:0]" +Toggle 0to1 tdata [160] "logic tdata[511:0]" +Toggle 1to0 tdata [160] "logic tdata[511:0]" +Toggle 0to1 tdata [162] "logic tdata[511:0]" +Toggle 1to0 tdata [162] "logic tdata[511:0]" +Toggle 0to1 tdata [163] "logic tdata[511:0]" +Toggle 1to0 tdata [163] "logic tdata[511:0]" +Toggle 0to1 tdata [164] "logic tdata[511:0]" +Toggle 1to0 tdata [164] "logic tdata[511:0]" +Toggle 0to1 tdata [165] "logic tdata[511:0]" +Toggle 1to0 tdata [165] "logic tdata[511:0]" +Toggle 0to1 tdata [166] "logic tdata[511:0]" +Toggle 1to0 tdata [166] "logic tdata[511:0]" +Toggle 0to1 tdata [167] "logic tdata[511:0]" +Toggle 1to0 tdata [167] "logic tdata[511:0]" +Toggle 0to1 tdata [168] "logic tdata[511:0]" +Toggle 1to0 tdata [168] "logic tdata[511:0]" +Toggle 0to1 tdata [169] "logic tdata[511:0]" +Toggle 1to0 tdata [169] "logic tdata[511:0]" +Toggle 0to1 tdata [170] "logic tdata[511:0]" +Toggle 1to0 tdata [170] "logic tdata[511:0]" +Toggle 0to1 tdata [171] "logic tdata[511:0]" +Toggle 1to0 tdata [171] "logic tdata[511:0]" +Toggle 0to1 tdata [172] "logic tdata[511:0]" +Toggle 1to0 tdata [172] "logic tdata[511:0]" +Toggle 0to1 tdata [173] "logic tdata[511:0]" +Toggle 1to0 tdata [173] "logic tdata[511:0]" +Toggle 0to1 tdata [175] "logic tdata[511:0]" +Toggle 1to0 tdata [175] "logic tdata[511:0]" +Toggle 0to1 tdata [176] "logic tdata[511:0]" +Toggle 1to0 tdata [176] "logic tdata[511:0]" +Toggle 0to1 tdata [177] "logic tdata[511:0]" +Toggle 1to0 tdata [177] "logic tdata[511:0]" +Toggle 0to1 tdata [178] "logic tdata[511:0]" +Toggle 1to0 tdata [178] "logic tdata[511:0]" +Toggle 0to1 tdata [179] "logic tdata[511:0]" +Toggle 1to0 tdata [179] "logic tdata[511:0]" +Toggle 0to1 tdata [180] "logic tdata[511:0]" +Toggle 1to0 tdata [180] "logic tdata[511:0]" +Toggle 0to1 tdata [181] "logic tdata[511:0]" +Toggle 1to0 tdata [181] "logic tdata[511:0]" +Toggle 0to1 tdata [182] "logic tdata[511:0]" +Toggle 1to0 tdata [182] "logic tdata[511:0]" +Toggle 0to1 tdata [183] "logic tdata[511:0]" +Toggle 1to0 tdata [183] "logic tdata[511:0]" +Toggle 0to1 tdata [184] "logic tdata[511:0]" +Toggle 1to0 tdata [184] "logic tdata[511:0]" +Toggle 0to1 tdata [185] "logic tdata[511:0]" +Toggle 1to0 tdata [185] "logic tdata[511:0]" +Toggle 0to1 tdata [186] "logic tdata[511:0]" +Toggle 1to0 tdata [186] "logic tdata[511:0]" +Toggle 0to1 tdata [187] "logic tdata[511:0]" +Toggle 1to0 tdata [187] "logic tdata[511:0]" +Toggle 0to1 tdata [188] "logic tdata[511:0]" +Toggle 1to0 tdata [188] "logic tdata[511:0]" +Toggle 0to1 tdata [189] "logic tdata[511:0]" +Toggle 1to0 tdata [189] "logic tdata[511:0]" +Toggle 0to1 tdata [190] "logic tdata[511:0]" +Toggle 1to0 tdata [190] "logic tdata[511:0]" +Toggle 0to1 tdata [191] "logic tdata[511:0]" +Toggle 1to0 tdata [191] "logic tdata[511:0]" +Toggle 0to1 tdata [192] "logic tdata[511:0]" +Toggle 1to0 tdata [192] "logic tdata[511:0]" +Toggle 0to1 tdata [193] "logic tdata[511:0]" +Toggle 1to0 tdata [193] "logic tdata[511:0]" +Toggle 0to1 tdata [194] "logic tdata[511:0]" +Toggle 1to0 tdata [194] "logic tdata[511:0]" +Toggle 0to1 tdata [195] "logic tdata[511:0]" +Toggle 1to0 tdata [195] "logic tdata[511:0]" +Toggle 0to1 tdata [196] "logic tdata[511:0]" +Toggle 1to0 tdata [196] "logic tdata[511:0]" +Toggle 0to1 tdata [197] "logic tdata[511:0]" +Toggle 1to0 tdata [197] "logic tdata[511:0]" +Toggle 0to1 tdata [198] "logic tdata[511:0]" +Toggle 1to0 tdata [198] "logic tdata[511:0]" +Toggle 0to1 tdata [199] "logic tdata[511:0]" +Toggle 1to0 tdata [199] "logic tdata[511:0]" +Toggle 0to1 tdata [200] "logic tdata[511:0]" +Toggle 1to0 tdata [200] "logic tdata[511:0]" +Toggle 0to1 tdata [201] "logic tdata[511:0]" +Toggle 1to0 tdata [201] "logic tdata[511:0]" +Toggle 0to1 tdata [202] "logic tdata[511:0]" +Toggle 1to0 tdata [202] "logic tdata[511:0]" +Toggle 0to1 tdata [203] "logic tdata[511:0]" +Toggle 1to0 tdata [203] "logic tdata[511:0]" +Toggle 0to1 tdata [204] "logic tdata[511:0]" +Toggle 1to0 tdata [204] "logic tdata[511:0]" +Toggle 0to1 tdata [205] "logic tdata[511:0]" +Toggle 1to0 tdata [205] "logic tdata[511:0]" +Toggle 0to1 tdata [206] "logic tdata[511:0]" +Toggle 1to0 tdata [206] "logic tdata[511:0]" +Toggle 0to1 tdata [207] "logic tdata[511:0]" +Toggle 1to0 tdata [207] "logic tdata[511:0]" +Toggle 0to1 tdata [208] "logic tdata[511:0]" +Toggle 1to0 tdata [208] "logic tdata[511:0]" +Toggle 0to1 tdata [209] "logic tdata[511:0]" +Toggle 1to0 tdata [209] "logic tdata[511:0]" +Toggle 0to1 tdata [210] "logic tdata[511:0]" +Toggle 1to0 tdata [210] "logic tdata[511:0]" +Toggle 0to1 tdata [211] "logic tdata[511:0]" +Toggle 1to0 tdata [211] "logic tdata[511:0]" +Toggle 0to1 tdata [212] "logic tdata[511:0]" +Toggle 1to0 tdata [212] "logic tdata[511:0]" +Toggle 0to1 tdata [213] "logic tdata[511:0]" +Toggle 1to0 tdata [213] "logic tdata[511:0]" +Toggle 0to1 tdata [214] "logic tdata[511:0]" +Toggle 1to0 tdata [214] "logic tdata[511:0]" +Toggle 0to1 tdata [215] "logic tdata[511:0]" +Toggle 1to0 tdata [215] "logic tdata[511:0]" +Toggle 0to1 tdata [216] "logic tdata[511:0]" +Toggle 1to0 tdata [216] "logic tdata[511:0]" +Toggle 0to1 tdata [217] "logic tdata[511:0]" +Toggle 1to0 tdata [217] "logic tdata[511:0]" +Toggle 0to1 tdata [218] "logic tdata[511:0]" +Toggle 1to0 tdata [218] "logic tdata[511:0]" +Toggle 0to1 tdata [219] "logic tdata[511:0]" +Toggle 1to0 tdata [219] "logic tdata[511:0]" +Toggle 0to1 tdata [220] "logic tdata[511:0]" +Toggle 1to0 tdata [220] "logic tdata[511:0]" +Toggle 0to1 tdata [221] "logic tdata[511:0]" +Toggle 1to0 tdata [221] "logic tdata[511:0]" +Toggle 0to1 tdata [222] "logic tdata[511:0]" +Toggle 1to0 tdata [222] "logic tdata[511:0]" +Toggle 0to1 tdata [223] "logic tdata[511:0]" +Toggle 1to0 tdata [223] "logic tdata[511:0]" +Toggle 0to1 tdata [226] "logic tdata[511:0]" +Toggle 1to0 tdata [226] "logic tdata[511:0]" +Toggle 0to1 tdata [227] "logic tdata[511:0]" +Toggle 1to0 tdata [227] "logic tdata[511:0]" +Toggle 0to1 tdata [228] "logic tdata[511:0]" +Toggle 1to0 tdata [228] "logic tdata[511:0]" +Toggle 0to1 tdata [229] "logic tdata[511:0]" +Toggle 1to0 tdata [229] "logic tdata[511:0]" +Toggle 0to1 tdata [230] "logic tdata[511:0]" +Toggle 1to0 tdata [230] "logic tdata[511:0]" +Toggle 0to1 tdata [231] "logic tdata[511:0]" +Toggle 1to0 tdata [231] "logic tdata[511:0]" +Toggle 0to1 tdata [232] "logic tdata[511:0]" +Toggle 1to0 tdata [232] "logic tdata[511:0]" +Toggle 0to1 tdata [233] "logic tdata[511:0]" +Toggle 1to0 tdata [233] "logic tdata[511:0]" +Toggle 0to1 tdata [234] "logic tdata[511:0]" +Toggle 1to0 tdata [234] "logic tdata[511:0]" +Toggle 0to1 tdata [235] "logic tdata[511:0]" +Toggle 1to0 tdata [235] "logic tdata[511:0]" +Toggle 0to1 tdata [236] "logic tdata[511:0]" +Toggle 1to0 tdata [236] "logic tdata[511:0]" +Toggle 0to1 tdata [237] "logic tdata[511:0]" +Toggle 1to0 tdata [237] "logic tdata[511:0]" +Toggle 0to1 tdata [238] "logic tdata[511:0]" +Toggle 1to0 tdata [238] "logic tdata[511:0]" +Toggle 0to1 tdata [239] "logic tdata[511:0]" +Toggle 1to0 tdata [239] "logic tdata[511:0]" +Toggle 0to1 tdata [240] "logic tdata[511:0]" +Toggle 1to0 tdata [240] "logic tdata[511:0]" +Toggle 0to1 tdata [241] "logic tdata[511:0]" +Toggle 1to0 tdata [241] "logic tdata[511:0]" +Toggle 0to1 tdata [242] "logic tdata[511:0]" +Toggle 1to0 tdata [242] "logic tdata[511:0]" +Toggle 0to1 tdata [243] "logic tdata[511:0]" +Toggle 1to0 tdata [243] "logic tdata[511:0]" +Toggle 0to1 tdata [244] "logic tdata[511:0]" +Toggle 1to0 tdata [244] "logic tdata[511:0]" +Toggle 0to1 tdata [245] "logic tdata[511:0]" +Toggle 1to0 tdata [245] "logic tdata[511:0]" +Toggle 0to1 tdata [246] "logic tdata[511:0]" +Toggle 1to0 tdata [246] "logic tdata[511:0]" +Toggle 0to1 tdata [247] "logic tdata[511:0]" +Toggle 1to0 tdata [247] "logic tdata[511:0]" +Toggle 0to1 tdata [248] "logic tdata[511:0]" +Toggle 1to0 tdata [248] "logic tdata[511:0]" +Toggle 0to1 tdata [249] "logic tdata[511:0]" +Toggle 1to0 tdata [249] "logic tdata[511:0]" +Toggle 0to1 tdata [250] "logic tdata[511:0]" +Toggle 1to0 tdata [250] "logic tdata[511:0]" +Toggle 0to1 tdata [251] "logic tdata[511:0]" +Toggle 1to0 tdata [251] "logic tdata[511:0]" +Toggle 0to1 tdata [252] "logic tdata[511:0]" +Toggle 1to0 tdata [252] "logic tdata[511:0]" +Toggle 0to1 tdata [253] "logic tdata[511:0]" +Toggle 1to0 tdata [253] "logic tdata[511:0]" +Toggle 0to1 tdata [254] "logic tdata[511:0]" +Toggle 1to0 tdata [254] "logic tdata[511:0]" +Toggle 0to1 tdata [255] "logic tdata[511:0]" +Toggle 1to0 tdata [255] "logic tdata[511:0]" +Toggle 0to1 tdata [256] "logic tdata[511:0]" +Toggle 1to0 tdata [256] "logic tdata[511:0]" +Toggle 0to1 tdata [257] "logic tdata[511:0]" +Toggle 1to0 tdata [257] "logic tdata[511:0]" +Toggle 0to1 tdata [258] "logic tdata[511:0]" +Toggle 1to0 tdata [258] "logic tdata[511:0]" +Toggle 0to1 tdata [259] "logic tdata[511:0]" +Toggle 1to0 tdata [259] "logic tdata[511:0]" +Toggle 0to1 tdata [260] "logic tdata[511:0]" +Toggle 1to0 tdata [260] "logic tdata[511:0]" +Toggle 0to1 tdata [261] "logic tdata[511:0]" +Toggle 1to0 tdata [261] "logic tdata[511:0]" +Toggle 0to1 tdata [262] "logic tdata[511:0]" +Toggle 1to0 tdata [262] "logic tdata[511:0]" +Toggle 0to1 tdata [263] "logic tdata[511:0]" +Toggle 1to0 tdata [263] "logic tdata[511:0]" +Toggle 0to1 tdata [264] "logic tdata[511:0]" +Toggle 1to0 tdata [264] "logic tdata[511:0]" +Toggle 0to1 tdata [265] "logic tdata[511:0]" +Toggle 1to0 tdata [265] "logic tdata[511:0]" +Toggle 0to1 tdata [266] "logic tdata[511:0]" +Toggle 1to0 tdata [266] "logic tdata[511:0]" +Toggle 0to1 tdata [267] "logic tdata[511:0]" +Toggle 1to0 tdata [267] "logic tdata[511:0]" +Toggle 0to1 tdata [268] "logic tdata[511:0]" +Toggle 1to0 tdata [268] "logic tdata[511:0]" +Toggle 0to1 tdata [269] "logic tdata[511:0]" +Toggle 1to0 tdata [269] "logic tdata[511:0]" +Toggle 0to1 tdata [270] "logic tdata[511:0]" +Toggle 1to0 tdata [270] "logic tdata[511:0]" +Toggle 0to1 tdata [271] "logic tdata[511:0]" +Toggle 1to0 tdata [271] "logic tdata[511:0]" +Toggle 0to1 tdata [272] "logic tdata[511:0]" +Toggle 1to0 tdata [272] "logic tdata[511:0]" +Toggle 0to1 tdata [273] "logic tdata[511:0]" +Toggle 1to0 tdata [273] "logic tdata[511:0]" +Toggle 0to1 tdata [274] "logic tdata[511:0]" +Toggle 1to0 tdata [274] "logic tdata[511:0]" +Toggle 0to1 tdata [275] "logic tdata[511:0]" +Toggle 1to0 tdata [275] "logic tdata[511:0]" +Toggle 0to1 tdata [276] "logic tdata[511:0]" +Toggle 1to0 tdata [276] "logic tdata[511:0]" +Toggle 0to1 tdata [277] "logic tdata[511:0]" +Toggle 1to0 tdata [277] "logic tdata[511:0]" +Toggle 0to1 tdata [278] "logic tdata[511:0]" +Toggle 1to0 tdata [278] "logic tdata[511:0]" +Toggle 0to1 tdata [279] "logic tdata[511:0]" +Toggle 1to0 tdata [279] "logic tdata[511:0]" +Toggle 0to1 tdata [280] "logic tdata[511:0]" +Toggle 1to0 tdata [280] "logic tdata[511:0]" +Toggle 0to1 tdata [281] "logic tdata[511:0]" +Toggle 1to0 tdata [281] "logic tdata[511:0]" +Toggle 0to1 tdata [282] "logic tdata[511:0]" +Toggle 1to0 tdata [282] "logic tdata[511:0]" +Toggle 0to1 tdata [283] "logic tdata[511:0]" +Toggle 1to0 tdata [283] "logic tdata[511:0]" +Toggle 0to1 tdata [284] "logic tdata[511:0]" +Toggle 1to0 tdata [284] "logic tdata[511:0]" +Toggle 0to1 tdata [285] "logic tdata[511:0]" +Toggle 1to0 tdata [285] "logic tdata[511:0]" +Toggle 0to1 tdata [286] "logic tdata[511:0]" +Toggle 1to0 tdata [286] "logic tdata[511:0]" +Toggle 0to1 tdata [287] "logic tdata[511:0]" +Toggle 1to0 tdata [287] "logic tdata[511:0]" +Toggle 0to1 tdata [288] "logic tdata[511:0]" +Toggle 1to0 tdata [288] "logic tdata[511:0]" +Toggle 0to1 tdata [289] "logic tdata[511:0]" +Toggle 1to0 tdata [289] "logic tdata[511:0]" +Toggle 0to1 tdata [290] "logic tdata[511:0]" +Toggle 1to0 tdata [290] "logic tdata[511:0]" +Toggle 0to1 tdata [291] "logic tdata[511:0]" +Toggle 1to0 tdata [291] "logic tdata[511:0]" +Toggle 0to1 tdata [292] "logic tdata[511:0]" +Toggle 1to0 tdata [292] "logic tdata[511:0]" +Toggle 0to1 tdata [293] "logic tdata[511:0]" +Toggle 1to0 tdata [293] "logic tdata[511:0]" +Toggle 0to1 tdata [294] "logic tdata[511:0]" +Toggle 1to0 tdata [294] "logic tdata[511:0]" +Toggle 0to1 tdata [295] "logic tdata[511:0]" +Toggle 1to0 tdata [295] "logic tdata[511:0]" +Toggle 0to1 tdata [296] "logic tdata[511:0]" +Toggle 1to0 tdata [296] "logic tdata[511:0]" +Toggle 0to1 tdata [297] "logic tdata[511:0]" +Toggle 1to0 tdata [297] "logic tdata[511:0]" +Toggle 0to1 tdata [298] "logic tdata[511:0]" +Toggle 1to0 tdata [298] "logic tdata[511:0]" +Toggle 0to1 tdata [299] "logic tdata[511:0]" +Toggle 1to0 tdata [299] "logic tdata[511:0]" +Toggle 0to1 tdata [300] "logic tdata[511:0]" +Toggle 1to0 tdata [300] "logic tdata[511:0]" +Toggle 0to1 tdata [301] "logic tdata[511:0]" +Toggle 1to0 tdata [301] "logic tdata[511:0]" +Toggle 0to1 tdata [302] "logic tdata[511:0]" +Toggle 1to0 tdata [302] "logic tdata[511:0]" +Toggle 0to1 tdata [303] "logic tdata[511:0]" +Toggle 1to0 tdata [303] "logic tdata[511:0]" +Toggle 0to1 tdata [304] "logic tdata[511:0]" +Toggle 1to0 tdata [304] "logic tdata[511:0]" +Toggle 0to1 tdata [305] "logic tdata[511:0]" +Toggle 1to0 tdata [305] "logic tdata[511:0]" +Toggle 0to1 tdata [306] "logic tdata[511:0]" +Toggle 1to0 tdata [306] "logic tdata[511:0]" +Toggle 0to1 tdata [307] "logic tdata[511:0]" +Toggle 1to0 tdata [307] "logic tdata[511:0]" +Toggle 0to1 tdata [308] "logic tdata[511:0]" +Toggle 1to0 tdata [308] "logic tdata[511:0]" +Toggle 0to1 tdata [309] "logic tdata[511:0]" +Toggle 1to0 tdata [309] "logic tdata[511:0]" +Toggle 0to1 tdata [310] "logic tdata[511:0]" +Toggle 1to0 tdata [310] "logic tdata[511:0]" +Toggle 0to1 tdata [311] "logic tdata[511:0]" +Toggle 1to0 tdata [311] "logic tdata[511:0]" +Toggle 0to1 tdata [312] "logic tdata[511:0]" +Toggle 1to0 tdata [312] "logic tdata[511:0]" +Toggle 0to1 tdata [313] "logic tdata[511:0]" +Toggle 1to0 tdata [313] "logic tdata[511:0]" +Toggle 0to1 tdata [314] "logic tdata[511:0]" +Toggle 1to0 tdata [314] "logic tdata[511:0]" +Toggle 0to1 tdata [315] "logic tdata[511:0]" +Toggle 1to0 tdata [315] "logic tdata[511:0]" +Toggle 0to1 tdata [316] "logic tdata[511:0]" +Toggle 1to0 tdata [316] "logic tdata[511:0]" +Toggle 0to1 tdata [317] "logic tdata[511:0]" +Toggle 1to0 tdata [317] "logic tdata[511:0]" +Toggle 0to1 tdata [318] "logic tdata[511:0]" +Toggle 1to0 tdata [318] "logic tdata[511:0]" +Toggle 0to1 tdata [319] "logic tdata[511:0]" +Toggle 1to0 tdata [319] "logic tdata[511:0]" +Toggle 0to1 tdata [320] "logic tdata[511:0]" +Toggle 1to0 tdata [320] "logic tdata[511:0]" +Toggle 0to1 tdata [321] "logic tdata[511:0]" +Toggle 1to0 tdata [321] "logic tdata[511:0]" +Toggle 0to1 tdata [322] "logic tdata[511:0]" +Toggle 1to0 tdata [322] "logic tdata[511:0]" +Toggle 0to1 tdata [323] "logic tdata[511:0]" +Toggle 1to0 tdata [323] "logic tdata[511:0]" +Toggle 0to1 tdata [324] "logic tdata[511:0]" +Toggle 1to0 tdata [324] "logic tdata[511:0]" +Toggle 0to1 tdata [325] "logic tdata[511:0]" +Toggle 1to0 tdata [325] "logic tdata[511:0]" +Toggle 0to1 tdata [326] "logic tdata[511:0]" +Toggle 1to0 tdata [326] "logic tdata[511:0]" +Toggle 0to1 tdata [327] "logic tdata[511:0]" +Toggle 1to0 tdata [327] "logic tdata[511:0]" +Toggle 0to1 tdata [328] "logic tdata[511:0]" +Toggle 1to0 tdata [328] "logic tdata[511:0]" +Toggle 0to1 tdata [329] "logic tdata[511:0]" +Toggle 1to0 tdata [329] "logic tdata[511:0]" +Toggle 0to1 tdata [330] "logic tdata[511:0]" +Toggle 1to0 tdata [330] "logic tdata[511:0]" +Toggle 0to1 tdata [331] "logic tdata[511:0]" +Toggle 1to0 tdata [331] "logic tdata[511:0]" +Toggle 0to1 tdata [332] "logic tdata[511:0]" +Toggle 1to0 tdata [332] "logic tdata[511:0]" +Toggle 0to1 tdata [333] "logic tdata[511:0]" +Toggle 1to0 tdata [333] "logic tdata[511:0]" +Toggle 0to1 tdata [334] "logic tdata[511:0]" +Toggle 1to0 tdata [334] "logic tdata[511:0]" +Toggle 0to1 tdata [335] "logic tdata[511:0]" +Toggle 1to0 tdata [335] "logic tdata[511:0]" +Toggle 0to1 tdata [336] "logic tdata[511:0]" +Toggle 1to0 tdata [336] "logic tdata[511:0]" +Toggle 0to1 tdata [337] "logic tdata[511:0]" +Toggle 1to0 tdata [337] "logic tdata[511:0]" +Toggle 0to1 tdata [338] "logic tdata[511:0]" +Toggle 1to0 tdata [338] "logic tdata[511:0]" +Toggle 0to1 tdata [339] "logic tdata[511:0]" +Toggle 1to0 tdata [339] "logic tdata[511:0]" +Toggle 0to1 tdata [340] "logic tdata[511:0]" +Toggle 1to0 tdata [340] "logic tdata[511:0]" +Toggle 0to1 tdata [341] "logic tdata[511:0]" +Toggle 1to0 tdata [341] "logic tdata[511:0]" +Toggle 0to1 tdata [342] "logic tdata[511:0]" +Toggle 1to0 tdata [342] "logic tdata[511:0]" +Toggle 0to1 tdata [343] "logic tdata[511:0]" +Toggle 1to0 tdata [343] "logic tdata[511:0]" +Toggle 0to1 tdata [344] "logic tdata[511:0]" +Toggle 1to0 tdata [344] "logic tdata[511:0]" +Toggle 0to1 tdata [345] "logic tdata[511:0]" +Toggle 1to0 tdata [345] "logic tdata[511:0]" +Toggle 0to1 tdata [346] "logic tdata[511:0]" +Toggle 1to0 tdata [346] "logic tdata[511:0]" +Toggle 0to1 tdata [347] "logic tdata[511:0]" +Toggle 1to0 tdata [347] "logic tdata[511:0]" +Toggle 0to1 tdata [348] "logic tdata[511:0]" +Toggle 1to0 tdata [348] "logic tdata[511:0]" +Toggle 0to1 tdata [349] "logic tdata[511:0]" +Toggle 1to0 tdata [349] "logic tdata[511:0]" +Toggle 0to1 tdata [350] "logic tdata[511:0]" +Toggle 1to0 tdata [350] "logic tdata[511:0]" +Toggle 0to1 tdata [351] "logic tdata[511:0]" +Toggle 1to0 tdata [351] "logic tdata[511:0]" +Toggle 0to1 tdata [352] "logic tdata[511:0]" +Toggle 1to0 tdata [352] "logic tdata[511:0]" +Toggle 0to1 tdata [353] "logic tdata[511:0]" +Toggle 1to0 tdata [353] "logic tdata[511:0]" +Toggle 0to1 tdata [354] "logic tdata[511:0]" +Toggle 1to0 tdata [354] "logic tdata[511:0]" +Toggle 0to1 tdata [355] "logic tdata[511:0]" +Toggle 1to0 tdata [355] "logic tdata[511:0]" +Toggle 0to1 tdata [356] "logic tdata[511:0]" +Toggle 1to0 tdata [356] "logic tdata[511:0]" +Toggle 0to1 tdata [357] "logic tdata[511:0]" +Toggle 1to0 tdata [357] "logic tdata[511:0]" +Toggle 0to1 tdata [358] "logic tdata[511:0]" +Toggle 1to0 tdata [358] "logic tdata[511:0]" +Toggle 0to1 tdata [359] "logic tdata[511:0]" +Toggle 1to0 tdata [359] "logic tdata[511:0]" +Toggle 0to1 tdata [360] "logic tdata[511:0]" +Toggle 1to0 tdata [360] "logic tdata[511:0]" +Toggle 0to1 tdata [361] "logic tdata[511:0]" +Toggle 1to0 tdata [361] "logic tdata[511:0]" +Toggle 0to1 tdata [362] "logic tdata[511:0]" +Toggle 1to0 tdata [362] "logic tdata[511:0]" +Toggle 0to1 tdata [363] "logic tdata[511:0]" +Toggle 1to0 tdata [363] "logic tdata[511:0]" +Toggle 0to1 tdata [364] "logic tdata[511:0]" +Toggle 1to0 tdata [364] "logic tdata[511:0]" +Toggle 0to1 tdata [365] "logic tdata[511:0]" +Toggle 1to0 tdata [365] "logic tdata[511:0]" +Toggle 0to1 tdata [366] "logic tdata[511:0]" +Toggle 1to0 tdata [366] "logic tdata[511:0]" +Toggle 0to1 tdata [367] "logic tdata[511:0]" +Toggle 1to0 tdata [367] "logic tdata[511:0]" +Toggle 0to1 tdata [368] "logic tdata[511:0]" +Toggle 1to0 tdata [368] "logic tdata[511:0]" +Toggle 0to1 tdata [369] "logic tdata[511:0]" +Toggle 1to0 tdata [369] "logic tdata[511:0]" +Toggle 0to1 tdata [370] "logic tdata[511:0]" +Toggle 1to0 tdata [370] "logic tdata[511:0]" +Toggle 0to1 tdata [371] "logic tdata[511:0]" +Toggle 1to0 tdata [371] "logic tdata[511:0]" +Toggle 0to1 tdata [372] "logic tdata[511:0]" +Toggle 1to0 tdata [372] "logic tdata[511:0]" +Toggle 0to1 tdata [373] "logic tdata[511:0]" +Toggle 1to0 tdata [373] "logic tdata[511:0]" +Toggle 0to1 tdata [374] "logic tdata[511:0]" +Toggle 1to0 tdata [374] "logic tdata[511:0]" +Toggle 0to1 tdata [375] "logic tdata[511:0]" +Toggle 1to0 tdata [375] "logic tdata[511:0]" +Toggle 0to1 tdata [376] "logic tdata[511:0]" +Toggle 1to0 tdata [376] "logic tdata[511:0]" +Toggle 0to1 tdata [377] "logic tdata[511:0]" +Toggle 1to0 tdata [377] "logic tdata[511:0]" +Toggle 0to1 tdata [378] "logic tdata[511:0]" +Toggle 1to0 tdata [378] "logic tdata[511:0]" +Toggle 0to1 tdata [379] "logic tdata[511:0]" +Toggle 1to0 tdata [379] "logic tdata[511:0]" +Toggle 0to1 tdata [380] "logic tdata[511:0]" +Toggle 1to0 tdata [380] "logic tdata[511:0]" +Toggle 0to1 tdata [381] "logic tdata[511:0]" +Toggle 1to0 tdata [381] "logic tdata[511:0]" +Toggle 0to1 tdata [382] "logic tdata[511:0]" +Toggle 1to0 tdata [382] "logic tdata[511:0]" +Toggle 0to1 tdata [383] "logic tdata[511:0]" +Toggle 1to0 tdata [383] "logic tdata[511:0]" +Toggle 0to1 tdata [384] "logic tdata[511:0]" +Toggle 1to0 tdata [384] "logic tdata[511:0]" +Toggle 0to1 tdata [385] "logic tdata[511:0]" +Toggle 1to0 tdata [385] "logic tdata[511:0]" +Toggle 0to1 tdata [386] "logic tdata[511:0]" +Toggle 1to0 tdata [386] "logic tdata[511:0]" +Toggle 0to1 tdata [387] "logic tdata[511:0]" +Toggle 1to0 tdata [387] "logic tdata[511:0]" +Toggle 0to1 tdata [388] "logic tdata[511:0]" +Toggle 1to0 tdata [388] "logic tdata[511:0]" +Toggle 0to1 tdata [389] "logic tdata[511:0]" +Toggle 1to0 tdata [389] "logic tdata[511:0]" +Toggle 0to1 tdata [390] "logic tdata[511:0]" +Toggle 1to0 tdata [390] "logic tdata[511:0]" +Toggle 0to1 tdata [391] "logic tdata[511:0]" +Toggle 1to0 tdata [391] "logic tdata[511:0]" +Toggle 0to1 tdata [392] "logic tdata[511:0]" +Toggle 1to0 tdata [392] "logic tdata[511:0]" +Toggle 0to1 tdata [393] "logic tdata[511:0]" +Toggle 1to0 tdata [393] "logic tdata[511:0]" +Toggle 0to1 tdata [394] "logic tdata[511:0]" +Toggle 1to0 tdata [394] "logic tdata[511:0]" +Toggle 0to1 tdata [395] "logic tdata[511:0]" +Toggle 1to0 tdata [395] "logic tdata[511:0]" +Toggle 0to1 tdata [396] "logic tdata[511:0]" +Toggle 1to0 tdata [396] "logic tdata[511:0]" +Toggle 0to1 tdata [397] "logic tdata[511:0]" +Toggle 1to0 tdata [397] "logic tdata[511:0]" +Toggle 0to1 tdata [398] "logic tdata[511:0]" +Toggle 1to0 tdata [398] "logic tdata[511:0]" +Toggle 0to1 tdata [399] "logic tdata[511:0]" +Toggle 1to0 tdata [399] "logic tdata[511:0]" +Toggle 0to1 tdata [400] "logic tdata[511:0]" +Toggle 1to0 tdata [400] "logic tdata[511:0]" +Toggle 0to1 tdata [401] "logic tdata[511:0]" +Toggle 1to0 tdata [401] "logic tdata[511:0]" +Toggle 0to1 tdata [402] "logic tdata[511:0]" +Toggle 1to0 tdata [402] "logic tdata[511:0]" +Toggle 0to1 tdata [403] "logic tdata[511:0]" +Toggle 1to0 tdata [403] "logic tdata[511:0]" +Toggle 0to1 tdata [404] "logic tdata[511:0]" +Toggle 1to0 tdata [404] "logic tdata[511:0]" +Toggle 0to1 tdata [405] "logic tdata[511:0]" +Toggle 1to0 tdata [405] "logic tdata[511:0]" +Toggle 0to1 tdata [406] "logic tdata[511:0]" +Toggle 1to0 tdata [406] "logic tdata[511:0]" +Toggle 0to1 tdata [407] "logic tdata[511:0]" +Toggle 1to0 tdata [407] "logic tdata[511:0]" +Toggle 0to1 tdata [408] "logic tdata[511:0]" +Toggle 1to0 tdata [408] "logic tdata[511:0]" +Toggle 0to1 tdata [409] "logic tdata[511:0]" +Toggle 1to0 tdata [409] "logic tdata[511:0]" +Toggle 0to1 tdata [410] "logic tdata[511:0]" +Toggle 1to0 tdata [410] "logic tdata[511:0]" +Toggle 0to1 tdata [411] "logic tdata[511:0]" +Toggle 1to0 tdata [411] "logic tdata[511:0]" +Toggle 0to1 tdata [412] "logic tdata[511:0]" +Toggle 1to0 tdata [412] "logic tdata[511:0]" +Toggle 0to1 tdata [413] "logic tdata[511:0]" +Toggle 1to0 tdata [413] "logic tdata[511:0]" +Toggle 0to1 tdata [414] "logic tdata[511:0]" +Toggle 1to0 tdata [414] "logic tdata[511:0]" +Toggle 0to1 tdata [415] "logic tdata[511:0]" +Toggle 1to0 tdata [415] "logic tdata[511:0]" +Toggle 0to1 tdata [416] "logic tdata[511:0]" +Toggle 1to0 tdata [416] "logic tdata[511:0]" +Toggle 0to1 tdata [417] "logic tdata[511:0]" +Toggle 1to0 tdata [417] "logic tdata[511:0]" +Toggle 0to1 tdata [418] "logic tdata[511:0]" +Toggle 1to0 tdata [418] "logic tdata[511:0]" +Toggle 0to1 tdata [419] "logic tdata[511:0]" +Toggle 1to0 tdata [419] "logic tdata[511:0]" +Toggle 0to1 tdata [420] "logic tdata[511:0]" +Toggle 1to0 tdata [420] "logic tdata[511:0]" +Toggle 0to1 tdata [421] "logic tdata[511:0]" +Toggle 1to0 tdata [421] "logic tdata[511:0]" +Toggle 0to1 tdata [422] "logic tdata[511:0]" +Toggle 1to0 tdata [422] "logic tdata[511:0]" +Toggle 0to1 tdata [423] "logic tdata[511:0]" +Toggle 1to0 tdata [423] "logic tdata[511:0]" +Toggle 0to1 tdata [424] "logic tdata[511:0]" +Toggle 1to0 tdata [424] "logic tdata[511:0]" +Toggle 0to1 tdata [425] "logic tdata[511:0]" +Toggle 1to0 tdata [425] "logic tdata[511:0]" +Toggle 0to1 tdata [426] "logic tdata[511:0]" +Toggle 1to0 tdata [426] "logic tdata[511:0]" +Toggle 0to1 tdata [427] "logic tdata[511:0]" +Toggle 1to0 tdata [427] "logic tdata[511:0]" +Toggle 0to1 tdata [428] "logic tdata[511:0]" +Toggle 1to0 tdata [428] "logic tdata[511:0]" +Toggle 0to1 tdata [429] "logic tdata[511:0]" +Toggle 1to0 tdata [429] "logic tdata[511:0]" +Toggle 0to1 tdata [430] "logic tdata[511:0]" +Toggle 1to0 tdata [430] "logic tdata[511:0]" +Toggle 0to1 tdata [431] "logic tdata[511:0]" +Toggle 1to0 tdata [431] "logic tdata[511:0]" +Toggle 0to1 tdata [432] "logic tdata[511:0]" +Toggle 1to0 tdata [432] "logic tdata[511:0]" +Toggle 0to1 tdata [433] "logic tdata[511:0]" +Toggle 1to0 tdata [433] "logic tdata[511:0]" +Toggle 0to1 tdata [434] "logic tdata[511:0]" +Toggle 1to0 tdata [434] "logic tdata[511:0]" +Toggle 0to1 tdata [435] "logic tdata[511:0]" +Toggle 1to0 tdata [435] "logic tdata[511:0]" +Toggle 0to1 tdata [436] "logic tdata[511:0]" +Toggle 1to0 tdata [436] "logic tdata[511:0]" +Toggle 0to1 tdata [437] "logic tdata[511:0]" +Toggle 1to0 tdata [437] "logic tdata[511:0]" +Toggle 0to1 tdata [438] "logic tdata[511:0]" +Toggle 1to0 tdata [438] "logic tdata[511:0]" +Toggle 0to1 tdata [439] "logic tdata[511:0]" +Toggle 1to0 tdata [439] "logic tdata[511:0]" +Toggle 0to1 tdata [440] "logic tdata[511:0]" +Toggle 1to0 tdata [440] "logic tdata[511:0]" +Toggle 0to1 tdata [441] "logic tdata[511:0]" +Toggle 1to0 tdata [441] "logic tdata[511:0]" +Toggle 0to1 tdata [442] "logic tdata[511:0]" +Toggle 1to0 tdata [442] "logic tdata[511:0]" +Toggle 0to1 tdata [443] "logic tdata[511:0]" +Toggle 1to0 tdata [443] "logic tdata[511:0]" +Toggle 0to1 tdata [444] "logic tdata[511:0]" +Toggle 1to0 tdata [444] "logic tdata[511:0]" +Toggle 0to1 tdata [445] "logic tdata[511:0]" +Toggle 1to0 tdata [445] "logic tdata[511:0]" +Toggle 0to1 tdata [446] "logic tdata[511:0]" +Toggle 1to0 tdata [446] "logic tdata[511:0]" +Toggle 0to1 tdata [447] "logic tdata[511:0]" +Toggle 1to0 tdata [447] "logic tdata[511:0]" +Toggle 0to1 tdata [448] "logic tdata[511:0]" +Toggle 1to0 tdata [448] "logic tdata[511:0]" +Toggle 0to1 tdata [449] "logic tdata[511:0]" +Toggle 1to0 tdata [449] "logic tdata[511:0]" +Toggle 0to1 tdata [450] "logic tdata[511:0]" +Toggle 1to0 tdata [450] "logic tdata[511:0]" +Toggle 0to1 tdata [451] "logic tdata[511:0]" +Toggle 1to0 tdata [451] "logic tdata[511:0]" +Toggle 0to1 tdata [452] "logic tdata[511:0]" +Toggle 1to0 tdata [452] "logic tdata[511:0]" +Toggle 0to1 tdata [453] "logic tdata[511:0]" +Toggle 1to0 tdata [453] "logic tdata[511:0]" +Toggle 0to1 tdata [454] "logic tdata[511:0]" +Toggle 1to0 tdata [454] "logic tdata[511:0]" +Toggle 0to1 tdata [455] "logic tdata[511:0]" +Toggle 1to0 tdata [455] "logic tdata[511:0]" +Toggle 0to1 tdata [456] "logic tdata[511:0]" +Toggle 1to0 tdata [456] "logic tdata[511:0]" +Toggle 0to1 tdata [457] "logic tdata[511:0]" +Toggle 1to0 tdata [457] "logic tdata[511:0]" +Toggle 0to1 tdata [458] "logic tdata[511:0]" +Toggle 1to0 tdata [458] "logic tdata[511:0]" +Toggle 0to1 tdata [459] "logic tdata[511:0]" +Toggle 1to0 tdata [459] "logic tdata[511:0]" +Toggle 0to1 tdata [460] "logic tdata[511:0]" +Toggle 1to0 tdata [460] "logic tdata[511:0]" +Toggle 0to1 tdata [461] "logic tdata[511:0]" +Toggle 1to0 tdata [461] "logic tdata[511:0]" +Toggle 0to1 tdata [462] "logic tdata[511:0]" +Toggle 1to0 tdata [462] "logic tdata[511:0]" +Toggle 0to1 tdata [463] "logic tdata[511:0]" +Toggle 1to0 tdata [463] "logic tdata[511:0]" +Toggle 0to1 tdata [464] "logic tdata[511:0]" +Toggle 1to0 tdata [464] "logic tdata[511:0]" +Toggle 0to1 tdata [465] "logic tdata[511:0]" +Toggle 1to0 tdata [465] "logic tdata[511:0]" +Toggle 0to1 tdata [466] "logic tdata[511:0]" +Toggle 1to0 tdata [466] "logic tdata[511:0]" +Toggle 0to1 tdata [467] "logic tdata[511:0]" +Toggle 1to0 tdata [467] "logic tdata[511:0]" +Toggle 0to1 tdata [468] "logic tdata[511:0]" +Toggle 1to0 tdata [468] "logic tdata[511:0]" +Toggle 0to1 tdata [469] "logic tdata[511:0]" +Toggle 1to0 tdata [469] "logic tdata[511:0]" +Toggle 0to1 tdata [470] "logic tdata[511:0]" +Toggle 1to0 tdata [470] "logic tdata[511:0]" +Toggle 0to1 tdata [471] "logic tdata[511:0]" +Toggle 1to0 tdata [471] "logic tdata[511:0]" +Toggle 0to1 tdata [472] "logic tdata[511:0]" +Toggle 1to0 tdata [472] "logic tdata[511:0]" +Toggle 0to1 tdata [473] "logic tdata[511:0]" +Toggle 1to0 tdata [473] "logic tdata[511:0]" +Toggle 0to1 tdata [474] "logic tdata[511:0]" +Toggle 1to0 tdata [474] "logic tdata[511:0]" +Toggle 0to1 tdata [475] "logic tdata[511:0]" +Toggle 1to0 tdata [475] "logic tdata[511:0]" +Toggle 0to1 tdata [476] "logic tdata[511:0]" +Toggle 1to0 tdata [476] "logic tdata[511:0]" +Toggle 0to1 tdata [477] "logic tdata[511:0]" +Toggle 1to0 tdata [477] "logic tdata[511:0]" +Toggle 0to1 tdata [478] "logic tdata[511:0]" +Toggle 1to0 tdata [478] "logic tdata[511:0]" +Toggle 0to1 tdata [479] "logic tdata[511:0]" +Toggle 1to0 tdata [479] "logic tdata[511:0]" +Toggle 0to1 tdata [480] "logic tdata[511:0]" +Toggle 1to0 tdata [480] "logic tdata[511:0]" +Toggle 0to1 tdata [481] "logic tdata[511:0]" +Toggle 1to0 tdata [481] "logic tdata[511:0]" +Toggle 0to1 tdata [482] "logic tdata[511:0]" +Toggle 1to0 tdata [482] "logic tdata[511:0]" +Toggle 0to1 tdata [483] "logic tdata[511:0]" +Toggle 1to0 tdata [483] "logic tdata[511:0]" +Toggle 0to1 tdata [484] "logic tdata[511:0]" +Toggle 1to0 tdata [484] "logic tdata[511:0]" +Toggle 0to1 tdata [485] "logic tdata[511:0]" +Toggle 1to0 tdata [485] "logic tdata[511:0]" +Toggle 0to1 tdata [486] "logic tdata[511:0]" +Toggle 1to0 tdata [486] "logic tdata[511:0]" +Toggle 0to1 tdata [487] "logic tdata[511:0]" +Toggle 1to0 tdata [487] "logic tdata[511:0]" +Toggle 0to1 tdata [488] "logic tdata[511:0]" +Toggle 1to0 tdata [488] "logic tdata[511:0]" +Toggle 0to1 tdata [489] "logic tdata[511:0]" +Toggle 1to0 tdata [489] "logic tdata[511:0]" +Toggle 0to1 tdata [490] "logic tdata[511:0]" +Toggle 1to0 tdata [490] "logic tdata[511:0]" +Toggle 0to1 tdata [491] "logic tdata[511:0]" +Toggle 1to0 tdata [491] "logic tdata[511:0]" +Toggle 0to1 tdata [492] "logic tdata[511:0]" +Toggle 1to0 tdata [492] "logic tdata[511:0]" +Toggle 0to1 tdata [493] "logic tdata[511:0]" +Toggle 1to0 tdata [493] "logic tdata[511:0]" +Toggle 0to1 tdata [494] "logic tdata[511:0]" +Toggle 1to0 tdata [494] "logic tdata[511:0]" +Toggle 0to1 tdata [495] "logic tdata[511:0]" +Toggle 1to0 tdata [495] "logic tdata[511:0]" +Toggle 0to1 tdata [496] "logic tdata[511:0]" +Toggle 1to0 tdata [496] "logic tdata[511:0]" +Toggle 0to1 tdata [497] "logic tdata[511:0]" +Toggle 1to0 tdata [497] "logic tdata[511:0]" +Toggle 0to1 tdata [498] "logic tdata[511:0]" +Toggle 1to0 tdata [498] "logic tdata[511:0]" +Toggle 0to1 tdata [499] "logic tdata[511:0]" +Toggle 1to0 tdata [499] "logic tdata[511:0]" +Toggle 0to1 tdata [500] "logic tdata[511:0]" +Toggle 1to0 tdata [500] "logic tdata[511:0]" +Toggle 0to1 tdata [501] "logic tdata[511:0]" +Toggle 1to0 tdata [501] "logic tdata[511:0]" +Toggle 0to1 tdata [502] "logic tdata[511:0]" +Toggle 1to0 tdata [502] "logic tdata[511:0]" +Toggle 0to1 tdata [503] "logic tdata[511:0]" +Toggle 1to0 tdata [503] "logic tdata[511:0]" +Toggle 0to1 tdata [504] "logic tdata[511:0]" +Toggle 1to0 tdata [504] "logic tdata[511:0]" +Toggle 0to1 tdata [505] "logic tdata[511:0]" +Toggle 1to0 tdata [505] "logic tdata[511:0]" +Toggle 0to1 tdata [506] "logic tdata[511:0]" +Toggle 1to0 tdata [506] "logic tdata[511:0]" +Toggle 0to1 tdata [507] "logic tdata[511:0]" +Toggle 1to0 tdata [507] "logic tdata[511:0]" +Toggle 0to1 tdata [508] "logic tdata[511:0]" +Toggle 1to0 tdata [508] "logic tdata[511:0]" +Toggle 0to1 tdata [509] "logic tdata[511:0]" +Toggle 1to0 tdata [509] "logic tdata[511:0]" +Toggle 0to1 tdata [510] "logic tdata[511:0]" +Toggle 1to0 tdata [510] "logic tdata[511:0]" +Toggle 0to1 tdata [6] "logic tdata[511:0]" +Toggle 0to1 tlast "logic tlast" +Toggle 1to0 tlast "logic tlast" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.local_commit.commit_skid.r.axis_pl[1] +Toggle tkeep "logic tkeep[63:0]" +Toggle 0to1 tlast "logic tlast" +Toggle 1to0 tlast "logic tlast" +Toggle 0to1 tready "logic tready" +Toggle 1to0 tready "logic tready" +Toggle tuser_vendor "logic tuser_vendor[9:0]" +Toggle 0to1 tdata [511] "logic tdata[511:0]" +Toggle 1to0 tdata [511] "logic tdata[511:0]" +Toggle 0to1 tdata [0] "logic tdata[511:0]" +Toggle 1to0 tdata [0] "logic tdata[511:0]" +Toggle 0to1 tdata [1] "logic tdata[511:0]" +Toggle 1to0 tdata [1] "logic tdata[511:0]" +Toggle 0to1 tdata [2] "logic tdata[511:0]" +Toggle 1to0 tdata [2] "logic tdata[511:0]" +Toggle 0to1 tdata [3] "logic tdata[511:0]" +Toggle 1to0 tdata [3] "logic tdata[511:0]" +Toggle 0to1 tdata [7] "logic tdata[511:0]" +Toggle 1to0 tdata [7] "logic tdata[511:0]" +Toggle 0to1 tdata [8] "logic tdata[511:0]" +Toggle 1to0 tdata [8] "logic tdata[511:0]" +Toggle 0to1 tdata [9] "logic tdata[511:0]" +Toggle 1to0 tdata [9] "logic tdata[511:0]" +Toggle 0to1 tdata [10] "logic tdata[511:0]" +Toggle 1to0 tdata [10] "logic tdata[511:0]" +Toggle 0to1 tdata [11] "logic tdata[511:0]" +Toggle 1to0 tdata [11] "logic tdata[511:0]" +Toggle 0to1 tdata [12] "logic tdata[511:0]" +Toggle 1to0 tdata [12] "logic tdata[511:0]" +Toggle 0to1 tdata [13] "logic tdata[511:0]" +Toggle 1to0 tdata [13] "logic tdata[511:0]" +Toggle 0to1 tdata [14] "logic tdata[511:0]" +Toggle 1to0 tdata [14] "logic tdata[511:0]" +Toggle 0to1 tdata [15] "logic tdata[511:0]" +Toggle 1to0 tdata [15] "logic tdata[511:0]" +Toggle 0to1 tdata [16] "logic tdata[511:0]" +Toggle 1to0 tdata [16] "logic tdata[511:0]" +Toggle 0to1 tdata [17] "logic tdata[511:0]" +Toggle 1to0 tdata [17] "logic tdata[511:0]" +Toggle 0to1 tdata [18] "logic tdata[511:0]" +Toggle 1to0 tdata [18] "logic tdata[511:0]" +Toggle 0to1 tdata [19] "logic tdata[511:0]" +Toggle 1to0 tdata [19] "logic tdata[511:0]" +Toggle 0to1 tdata [21] "logic tdata[511:0]" +Toggle 1to0 tdata [21] "logic tdata[511:0]" +Toggle 0to1 tdata [22] "logic tdata[511:0]" +Toggle 1to0 tdata [22] "logic tdata[511:0]" +Toggle 0to1 tdata [23] "logic tdata[511:0]" +Toggle 1to0 tdata [23] "logic tdata[511:0]" +Toggle 0to1 tdata [24] "logic tdata[511:0]" +Toggle 1to0 tdata [24] "logic tdata[511:0]" +Toggle 0to1 tdata [25] "logic tdata[511:0]" +Toggle 1to0 tdata [25] "logic tdata[511:0]" +Toggle 0to1 tdata [26] "logic tdata[511:0]" +Toggle 1to0 tdata [26] "logic tdata[511:0]" +Toggle 0to1 tdata [27] "logic tdata[511:0]" +Toggle 1to0 tdata [27] "logic tdata[511:0]" +Toggle 0to1 tdata [28] "logic tdata[511:0]" +Toggle 1to0 tdata [28] "logic tdata[511:0]" +Toggle 0to1 tdata [29] "logic tdata[511:0]" +Toggle 1to0 tdata [29] "logic tdata[511:0]" +Toggle 0to1 tdata [30] "logic tdata[511:0]" +Toggle 1to0 tdata [30] "logic tdata[511:0]" +Toggle 0to1 tdata [31] "logic tdata[511:0]" +Toggle 1to0 tdata [31] "logic tdata[511:0]" +Toggle 0to1 tdata [32] "logic tdata[511:0]" +Toggle 1to0 tdata [32] "logic tdata[511:0]" +Toggle 0to1 tdata [33] "logic tdata[511:0]" +Toggle 1to0 tdata [33] "logic tdata[511:0]" +Toggle 0to1 tdata [34] "logic tdata[511:0]" +Toggle 1to0 tdata [34] "logic tdata[511:0]" +Toggle 0to1 tdata [35] "logic tdata[511:0]" +Toggle 1to0 tdata [35] "logic tdata[511:0]" +Toggle 0to1 tdata [36] "logic tdata[511:0]" +Toggle 1to0 tdata [36] "logic tdata[511:0]" +Toggle 0to1 tdata [37] "logic tdata[511:0]" +Toggle 1to0 tdata [37] "logic tdata[511:0]" +Toggle 0to1 tdata [38] "logic tdata[511:0]" +Toggle 1to0 tdata [38] "logic tdata[511:0]" +Toggle 0to1 tdata [39] "logic tdata[511:0]" +Toggle 1to0 tdata [39] "logic tdata[511:0]" +Toggle 0to1 tdata [40] "logic tdata[511:0]" +Toggle 1to0 tdata [40] "logic tdata[511:0]" +Toggle 0to1 tdata [41] "logic tdata[511:0]" +Toggle 1to0 tdata [41] "logic tdata[511:0]" +Toggle 0to1 tdata [42] "logic tdata[511:0]" +Toggle 1to0 tdata [42] "logic tdata[511:0]" +Toggle 0to1 tdata [43] "logic tdata[511:0]" +Toggle 1to0 tdata [43] "logic tdata[511:0]" +Toggle 0to1 tdata [44] "logic tdata[511:0]" +Toggle 1to0 tdata [44] "logic tdata[511:0]" +Toggle 0to1 tdata [45] "logic tdata[511:0]" +Toggle 1to0 tdata [45] "logic tdata[511:0]" +Toggle 0to1 tdata [46] "logic tdata[511:0]" +Toggle 1to0 tdata [46] "logic tdata[511:0]" +Toggle 0to1 tdata [47] "logic tdata[511:0]" +Toggle 1to0 tdata [47] "logic tdata[511:0]" +Toggle 0to1 tdata [48] "logic tdata[511:0]" +Toggle 1to0 tdata [48] "logic tdata[511:0]" +Toggle 0to1 tdata [49] "logic tdata[511:0]" +Toggle 1to0 tdata [49] "logic tdata[511:0]" +Toggle 0to1 tdata [50] "logic tdata[511:0]" +Toggle 1to0 tdata [50] "logic tdata[511:0]" +Toggle 0to1 tdata [51] "logic tdata[511:0]" +Toggle 1to0 tdata [51] "logic tdata[511:0]" +Toggle 0to1 tdata [52] "logic tdata[511:0]" +Toggle 1to0 tdata [52] "logic tdata[511:0]" +Toggle 0to1 tdata [53] "logic tdata[511:0]" +Toggle 1to0 tdata [53] "logic tdata[511:0]" +Toggle 0to1 tdata [54] "logic tdata[511:0]" +Toggle 1to0 tdata [54] "logic tdata[511:0]" +Toggle 0to1 tdata [55] "logic tdata[511:0]" +Toggle 1to0 tdata [55] "logic tdata[511:0]" +Toggle 0to1 tdata [56] "logic tdata[511:0]" +Toggle 1to0 tdata [56] "logic tdata[511:0]" +Toggle 0to1 tdata [57] "logic tdata[511:0]" +Toggle 1to0 tdata [57] "logic tdata[511:0]" +Toggle 0to1 tdata [58] "logic tdata[511:0]" +Toggle 1to0 tdata [58] "logic tdata[511:0]" +Toggle 0to1 tdata [59] "logic tdata[511:0]" +Toggle 1to0 tdata [59] "logic tdata[511:0]" +Toggle 0to1 tdata [60] "logic tdata[511:0]" +Toggle 1to0 tdata [60] "logic tdata[511:0]" +Toggle 0to1 tdata [61] "logic tdata[511:0]" +Toggle 1to0 tdata [61] "logic tdata[511:0]" +Toggle 0to1 tdata [62] "logic tdata[511:0]" +Toggle 1to0 tdata [62] "logic tdata[511:0]" +Toggle 0to1 tdata [63] "logic tdata[511:0]" +Toggle 1to0 tdata [63] "logic tdata[511:0]" +Toggle 0to1 tdata [64] "logic tdata[511:0]" +Toggle 1to0 tdata [64] "logic tdata[511:0]" +Toggle 0to1 tdata [65] "logic tdata[511:0]" +Toggle 1to0 tdata [65] "logic tdata[511:0]" +Toggle 0to1 tdata [66] "logic tdata[511:0]" +Toggle 1to0 tdata [66] "logic tdata[511:0]" +Toggle 0to1 tdata [67] "logic tdata[511:0]" +Toggle 1to0 tdata [67] "logic tdata[511:0]" +Toggle 0to1 tdata [68] "logic tdata[511:0]" +Toggle 1to0 tdata [68] "logic tdata[511:0]" +Toggle 0to1 tdata [69] "logic tdata[511:0]" +Toggle 1to0 tdata [69] "logic tdata[511:0]" +Toggle 0to1 tdata [70] "logic tdata[511:0]" +Toggle 1to0 tdata [70] "logic tdata[511:0]" +Toggle 0to1 tdata [71] "logic tdata[511:0]" +Toggle 1to0 tdata [71] "logic tdata[511:0]" +Toggle 0to1 tdata [72] "logic tdata[511:0]" +Toggle 1to0 tdata [72] "logic tdata[511:0]" +Toggle 0to1 tdata [73] "logic tdata[511:0]" +Toggle 1to0 tdata [73] "logic tdata[511:0]" +Toggle 0to1 tdata [74] "logic tdata[511:0]" +Toggle 1to0 tdata [74] "logic tdata[511:0]" +Toggle 0to1 tdata [75] "logic tdata[511:0]" +Toggle 1to0 tdata [75] "logic tdata[511:0]" +Toggle 0to1 tdata [76] "logic tdata[511:0]" +Toggle 1to0 tdata [76] "logic tdata[511:0]" +Toggle 0to1 tdata [77] "logic tdata[511:0]" +Toggle 1to0 tdata [77] "logic tdata[511:0]" +Toggle 0to1 tdata [78] "logic tdata[511:0]" +Toggle 1to0 tdata [78] "logic tdata[511:0]" +Toggle 0to1 tdata [79] "logic tdata[511:0]" +Toggle 1to0 tdata [79] "logic tdata[511:0]" +Toggle 0to1 tdata [80] "logic tdata[511:0]" +Toggle 1to0 tdata [80] "logic tdata[511:0]" +Toggle 0to1 tdata [81] "logic tdata[511:0]" +Toggle 1to0 tdata [81] "logic tdata[511:0]" +Toggle 0to1 tdata [82] "logic tdata[511:0]" +Toggle 1to0 tdata [82] "logic tdata[511:0]" +Toggle 0to1 tdata [83] "logic tdata[511:0]" +Toggle 1to0 tdata [83] "logic tdata[511:0]" +Toggle 0to1 tdata [84] "logic tdata[511:0]" +Toggle 1to0 tdata [84] "logic tdata[511:0]" +Toggle 0to1 tdata [85] "logic tdata[511:0]" +Toggle 1to0 tdata [85] "logic tdata[511:0]" +Toggle 0to1 tdata [86] "logic tdata[511:0]" +Toggle 1to0 tdata [86] "logic tdata[511:0]" +Toggle 0to1 tdata [87] "logic tdata[511:0]" +Toggle 1to0 tdata [87] "logic tdata[511:0]" +Toggle 0to1 tdata [88] "logic tdata[511:0]" +Toggle 1to0 tdata [88] "logic tdata[511:0]" +Toggle 0to1 tdata [89] "logic tdata[511:0]" +Toggle 1to0 tdata [89] "logic tdata[511:0]" +Toggle 0to1 tdata [90] "logic tdata[511:0]" +Toggle 1to0 tdata [90] "logic tdata[511:0]" +Toggle 0to1 tdata [91] "logic tdata[511:0]" +Toggle 1to0 tdata [91] "logic tdata[511:0]" +Toggle 0to1 tdata [92] "logic tdata[511:0]" +Toggle 1to0 tdata [92] "logic tdata[511:0]" +Toggle 0to1 tdata [93] "logic tdata[511:0]" +Toggle 1to0 tdata [93] "logic tdata[511:0]" +Toggle 0to1 tdata [94] "logic tdata[511:0]" +Toggle 1to0 tdata [94] "logic tdata[511:0]" +Toggle 0to1 tdata [95] "logic tdata[511:0]" +Toggle 1to0 tdata [95] "logic tdata[511:0]" +Toggle 0to1 tdata [96] "logic tdata[511:0]" +Toggle 1to0 tdata [96] "logic tdata[511:0]" +Toggle 0to1 tdata [97] "logic tdata[511:0]" +Toggle 1to0 tdata [97] "logic tdata[511:0]" +Toggle 0to1 tdata [98] "logic tdata[511:0]" +Toggle 1to0 tdata [98] "logic tdata[511:0]" +Toggle 0to1 tdata [99] "logic tdata[511:0]" +Toggle 1to0 tdata [99] "logic tdata[511:0]" +Toggle 0to1 tdata [100] "logic tdata[511:0]" +Toggle 1to0 tdata [100] "logic tdata[511:0]" +Toggle 0to1 tdata [101] "logic tdata[511:0]" +Toggle 1to0 tdata [101] "logic tdata[511:0]" +Toggle 0to1 tdata [102] "logic tdata[511:0]" +Toggle 1to0 tdata [102] "logic tdata[511:0]" +Toggle 0to1 tdata [103] "logic tdata[511:0]" +Toggle 1to0 tdata [103] "logic tdata[511:0]" +Toggle 0to1 tdata [104] "logic tdata[511:0]" +Toggle 1to0 tdata [104] "logic tdata[511:0]" +Toggle 0to1 tdata [105] "logic tdata[511:0]" +Toggle 1to0 tdata [105] "logic tdata[511:0]" +Toggle 0to1 tdata [106] "logic tdata[511:0]" +Toggle 1to0 tdata [106] "logic tdata[511:0]" +Toggle 0to1 tdata [107] "logic tdata[511:0]" +Toggle 1to0 tdata [107] "logic tdata[511:0]" +Toggle 0to1 tdata [108] "logic tdata[511:0]" +Toggle 1to0 tdata [108] "logic tdata[511:0]" +Toggle 0to1 tdata [109] "logic tdata[511:0]" +Toggle 1to0 tdata [109] "logic tdata[511:0]" +Toggle 0to1 tdata [110] "logic tdata[511:0]" +Toggle 1to0 tdata [110] "logic tdata[511:0]" +Toggle 0to1 tdata [111] "logic tdata[511:0]" +Toggle 1to0 tdata [111] "logic tdata[511:0]" +Toggle 0to1 tdata [112] "logic tdata[511:0]" +Toggle 1to0 tdata [112] "logic tdata[511:0]" +Toggle 0to1 tdata [113] "logic tdata[511:0]" +Toggle 1to0 tdata [113] "logic tdata[511:0]" +Toggle 0to1 tdata [114] "logic tdata[511:0]" +Toggle 1to0 tdata [114] "logic tdata[511:0]" +Toggle 0to1 tdata [115] "logic tdata[511:0]" +Toggle 1to0 tdata [115] "logic tdata[511:0]" +Toggle 0to1 tdata [116] "logic tdata[511:0]" +Toggle 1to0 tdata [116] "logic tdata[511:0]" +Toggle 0to1 tdata [117] "logic tdata[511:0]" +Toggle 1to0 tdata [117] "logic tdata[511:0]" +Toggle 0to1 tdata [126] "logic tdata[511:0]" +Toggle 1to0 tdata [126] "logic tdata[511:0]" +Toggle 0to1 tdata [127] "logic tdata[511:0]" +Toggle 1to0 tdata [127] "logic tdata[511:0]" +Toggle 0to1 tdata [128] "logic tdata[511:0]" +Toggle 1to0 tdata [128] "logic tdata[511:0]" +Toggle 0to1 tdata [129] "logic tdata[511:0]" +Toggle 1to0 tdata [129] "logic tdata[511:0]" +Toggle 0to1 tdata [130] "logic tdata[511:0]" +Toggle 1to0 tdata [130] "logic tdata[511:0]" +Toggle 0to1 tdata [131] "logic tdata[511:0]" +Toggle 1to0 tdata [131] "logic tdata[511:0]" +Toggle 0to1 tdata [132] "logic tdata[511:0]" +Toggle 1to0 tdata [132] "logic tdata[511:0]" +Toggle 0to1 tdata [133] "logic tdata[511:0]" +Toggle 1to0 tdata [133] "logic tdata[511:0]" +Toggle 0to1 tdata [134] "logic tdata[511:0]" +Toggle 1to0 tdata [134] "logic tdata[511:0]" +Toggle 0to1 tdata [135] "logic tdata[511:0]" +Toggle 1to0 tdata [135] "logic tdata[511:0]" +Toggle 0to1 tdata [136] "logic tdata[511:0]" +Toggle 1to0 tdata [136] "logic tdata[511:0]" +Toggle 0to1 tdata [137] "logic tdata[511:0]" +Toggle 1to0 tdata [137] "logic tdata[511:0]" +Toggle 0to1 tdata [138] "logic tdata[511:0]" +Toggle 1to0 tdata [138] "logic tdata[511:0]" +Toggle 0to1 tdata [139] "logic tdata[511:0]" +Toggle 1to0 tdata [139] "logic tdata[511:0]" +Toggle 0to1 tdata [140] "logic tdata[511:0]" +Toggle 1to0 tdata [140] "logic tdata[511:0]" +Toggle 0to1 tdata [141] "logic tdata[511:0]" +Toggle 1to0 tdata [141] "logic tdata[511:0]" +Toggle 0to1 tdata [142] "logic tdata[511:0]" +Toggle 1to0 tdata [142] "logic tdata[511:0]" +Toggle 0to1 tdata [143] "logic tdata[511:0]" +Toggle 1to0 tdata [143] "logic tdata[511:0]" +Toggle 0to1 tdata [144] "logic tdata[511:0]" +Toggle 1to0 tdata [144] "logic tdata[511:0]" +Toggle 0to1 tdata [145] "logic tdata[511:0]" +Toggle 1to0 tdata [145] "logic tdata[511:0]" +Toggle 0to1 tdata [146] "logic tdata[511:0]" +Toggle 1to0 tdata [146] "logic tdata[511:0]" +Toggle 0to1 tdata [147] "logic tdata[511:0]" +Toggle 1to0 tdata [147] "logic tdata[511:0]" +Toggle 0to1 tdata [148] "logic tdata[511:0]" +Toggle 1to0 tdata [148] "logic tdata[511:0]" +Toggle 0to1 tdata [149] "logic tdata[511:0]" +Toggle 1to0 tdata [149] "logic tdata[511:0]" +Toggle 0to1 tdata [150] "logic tdata[511:0]" +Toggle 1to0 tdata [150] "logic tdata[511:0]" +Toggle 0to1 tdata [151] "logic tdata[511:0]" +Toggle 1to0 tdata [151] "logic tdata[511:0]" +Toggle 0to1 tdata [152] "logic tdata[511:0]" +Toggle 1to0 tdata [152] "logic tdata[511:0]" +Toggle 0to1 tdata [153] "logic tdata[511:0]" +Toggle 1to0 tdata [153] "logic tdata[511:0]" +Toggle 0to1 tdata [154] "logic tdata[511:0]" +Toggle 1to0 tdata [154] "logic tdata[511:0]" +Toggle 0to1 tdata [155] "logic tdata[511:0]" +Toggle 1to0 tdata [155] "logic tdata[511:0]" +Toggle 0to1 tdata [156] "logic tdata[511:0]" +Toggle 1to0 tdata [156] "logic tdata[511:0]" +Toggle 0to1 tdata [157] "logic tdata[511:0]" +Toggle 1to0 tdata [157] "logic tdata[511:0]" +Toggle 0to1 tdata [158] "logic tdata[511:0]" +Toggle 1to0 tdata [158] "logic tdata[511:0]" +Toggle 0to1 tdata [159] "logic tdata[511:0]" +Toggle 1to0 tdata [159] "logic tdata[511:0]" +Toggle 0to1 tdata [160] "logic tdata[511:0]" +Toggle 1to0 tdata [160] "logic tdata[511:0]" +Toggle 0to1 tdata [162] "logic tdata[511:0]" +Toggle 1to0 tdata [162] "logic tdata[511:0]" +Toggle 0to1 tdata [163] "logic tdata[511:0]" +Toggle 1to0 tdata [163] "logic tdata[511:0]" +Toggle 0to1 tdata [164] "logic tdata[511:0]" +Toggle 1to0 tdata [164] "logic tdata[511:0]" +Toggle 0to1 tdata [165] "logic tdata[511:0]" +Toggle 1to0 tdata [165] "logic tdata[511:0]" +Toggle 0to1 tdata [166] "logic tdata[511:0]" +Toggle 1to0 tdata [166] "logic tdata[511:0]" +Toggle 0to1 tdata [167] "logic tdata[511:0]" +Toggle 1to0 tdata [167] "logic tdata[511:0]" +Toggle 0to1 tdata [168] "logic tdata[511:0]" +Toggle 1to0 tdata [168] "logic tdata[511:0]" +Toggle 0to1 tdata [169] "logic tdata[511:0]" +Toggle 1to0 tdata [169] "logic tdata[511:0]" +Toggle 0to1 tdata [170] "logic tdata[511:0]" +Toggle 1to0 tdata [170] "logic tdata[511:0]" +Toggle 0to1 tdata [171] "logic tdata[511:0]" +Toggle 1to0 tdata [171] "logic tdata[511:0]" +Toggle 0to1 tdata [172] "logic tdata[511:0]" +Toggle 1to0 tdata [172] "logic tdata[511:0]" +Toggle 0to1 tdata [173] "logic tdata[511:0]" +Toggle 1to0 tdata [173] "logic tdata[511:0]" +Toggle 0to1 tdata [175] "logic tdata[511:0]" +Toggle 1to0 tdata [175] "logic tdata[511:0]" +Toggle 0to1 tdata [176] "logic tdata[511:0]" +Toggle 1to0 tdata [176] "logic tdata[511:0]" +Toggle 0to1 tdata [177] "logic tdata[511:0]" +Toggle 1to0 tdata [177] "logic tdata[511:0]" +Toggle 0to1 tdata [178] "logic tdata[511:0]" +Toggle 1to0 tdata [178] "logic tdata[511:0]" +Toggle 0to1 tdata [179] "logic tdata[511:0]" +Toggle 1to0 tdata [179] "logic tdata[511:0]" +Toggle 0to1 tdata [180] "logic tdata[511:0]" +Toggle 1to0 tdata [180] "logic tdata[511:0]" +Toggle 0to1 tdata [181] "logic tdata[511:0]" +Toggle 1to0 tdata [181] "logic tdata[511:0]" +Toggle 0to1 tdata [182] "logic tdata[511:0]" +Toggle 1to0 tdata [182] "logic tdata[511:0]" +Toggle 0to1 tdata [183] "logic tdata[511:0]" +Toggle 1to0 tdata [183] "logic tdata[511:0]" +Toggle 0to1 tdata [184] "logic tdata[511:0]" +Toggle 1to0 tdata [184] "logic tdata[511:0]" +Toggle 0to1 tdata [185] "logic tdata[511:0]" +Toggle 1to0 tdata [185] "logic tdata[511:0]" +Toggle 0to1 tdata [186] "logic tdata[511:0]" +Toggle 1to0 tdata [186] "logic tdata[511:0]" +Toggle 0to1 tdata [187] "logic tdata[511:0]" +Toggle 1to0 tdata [187] "logic tdata[511:0]" +Toggle 0to1 tdata [188] "logic tdata[511:0]" +Toggle 1to0 tdata [188] "logic tdata[511:0]" +Toggle 0to1 tdata [189] "logic tdata[511:0]" +Toggle 1to0 tdata [189] "logic tdata[511:0]" +Toggle 0to1 tdata [190] "logic tdata[511:0]" +Toggle 1to0 tdata [190] "logic tdata[511:0]" +Toggle 0to1 tdata [191] "logic tdata[511:0]" +Toggle 1to0 tdata [191] "logic tdata[511:0]" +Toggle 0to1 tdata [192] "logic tdata[511:0]" +Toggle 1to0 tdata [192] "logic tdata[511:0]" +Toggle 0to1 tdata [193] "logic tdata[511:0]" +Toggle 1to0 tdata [193] "logic tdata[511:0]" +Toggle 0to1 tdata [194] "logic tdata[511:0]" +Toggle 1to0 tdata [194] "logic tdata[511:0]" +Toggle 0to1 tdata [195] "logic tdata[511:0]" +Toggle 1to0 tdata [195] "logic tdata[511:0]" +Toggle 0to1 tdata [196] "logic tdata[511:0]" +Toggle 1to0 tdata [196] "logic tdata[511:0]" +Toggle 0to1 tdata [197] "logic tdata[511:0]" +Toggle 1to0 tdata [197] "logic tdata[511:0]" +Toggle 0to1 tdata [198] "logic tdata[511:0]" +Toggle 1to0 tdata [198] "logic tdata[511:0]" +Toggle 0to1 tdata [199] "logic tdata[511:0]" +Toggle 1to0 tdata [199] "logic tdata[511:0]" +Toggle 0to1 tdata [200] "logic tdata[511:0]" +Toggle 1to0 tdata [200] "logic tdata[511:0]" +Toggle 0to1 tdata [201] "logic tdata[511:0]" +Toggle 1to0 tdata [201] "logic tdata[511:0]" +Toggle 0to1 tdata [202] "logic tdata[511:0]" +Toggle 1to0 tdata [202] "logic tdata[511:0]" +Toggle 0to1 tdata [203] "logic tdata[511:0]" +Toggle 1to0 tdata [203] "logic tdata[511:0]" +Toggle 0to1 tdata [204] "logic tdata[511:0]" +Toggle 1to0 tdata [204] "logic tdata[511:0]" +Toggle 0to1 tdata [205] "logic tdata[511:0]" +Toggle 1to0 tdata [205] "logic tdata[511:0]" +Toggle 0to1 tdata [206] "logic tdata[511:0]" +Toggle 1to0 tdata [206] "logic tdata[511:0]" +Toggle 0to1 tdata [207] "logic tdata[511:0]" +Toggle 1to0 tdata [207] "logic tdata[511:0]" +Toggle 0to1 tdata [208] "logic tdata[511:0]" +Toggle 1to0 tdata [208] "logic tdata[511:0]" +Toggle 0to1 tdata [209] "logic tdata[511:0]" +Toggle 1to0 tdata [209] "logic tdata[511:0]" +Toggle 0to1 tdata [210] "logic tdata[511:0]" +Toggle 1to0 tdata [210] "logic tdata[511:0]" +Toggle 0to1 tdata [211] "logic tdata[511:0]" +Toggle 1to0 tdata [211] "logic tdata[511:0]" +Toggle 0to1 tdata [212] "logic tdata[511:0]" +Toggle 1to0 tdata [212] "logic tdata[511:0]" +Toggle 0to1 tdata [213] "logic tdata[511:0]" +Toggle 1to0 tdata [213] "logic tdata[511:0]" +Toggle 0to1 tdata [214] "logic tdata[511:0]" +Toggle 1to0 tdata [214] "logic tdata[511:0]" +Toggle 0to1 tdata [215] "logic tdata[511:0]" +Toggle 1to0 tdata [215] "logic tdata[511:0]" +Toggle 0to1 tdata [216] "logic tdata[511:0]" +Toggle 1to0 tdata [216] "logic tdata[511:0]" +Toggle 0to1 tdata [217] "logic tdata[511:0]" +Toggle 1to0 tdata [217] "logic tdata[511:0]" +Toggle 0to1 tdata [218] "logic tdata[511:0]" +Toggle 1to0 tdata [218] "logic tdata[511:0]" +Toggle 0to1 tdata [219] "logic tdata[511:0]" +Toggle 1to0 tdata [219] "logic tdata[511:0]" +Toggle 0to1 tdata [220] "logic tdata[511:0]" +Toggle 1to0 tdata [220] "logic tdata[511:0]" +Toggle 0to1 tdata [221] "logic tdata[511:0]" +Toggle 1to0 tdata [221] "logic tdata[511:0]" +Toggle 0to1 tdata [222] "logic tdata[511:0]" +Toggle 1to0 tdata [222] "logic tdata[511:0]" +Toggle 0to1 tdata [223] "logic tdata[511:0]" +Toggle 1to0 tdata [223] "logic tdata[511:0]" +Toggle 0to1 tdata [226] "logic tdata[511:0]" +Toggle 1to0 tdata [226] "logic tdata[511:0]" +Toggle 0to1 tdata [227] "logic tdata[511:0]" +Toggle 1to0 tdata [227] "logic tdata[511:0]" +Toggle 0to1 tdata [228] "logic tdata[511:0]" +Toggle 1to0 tdata [228] "logic tdata[511:0]" +Toggle 0to1 tdata [229] "logic tdata[511:0]" +Toggle 1to0 tdata [229] "logic tdata[511:0]" +Toggle 0to1 tdata [230] "logic tdata[511:0]" +Toggle 1to0 tdata [230] "logic tdata[511:0]" +Toggle 0to1 tdata [231] "logic tdata[511:0]" +Toggle 1to0 tdata [231] "logic tdata[511:0]" +Toggle 0to1 tdata [232] "logic tdata[511:0]" +Toggle 1to0 tdata [232] "logic tdata[511:0]" +Toggle 0to1 tdata [233] "logic tdata[511:0]" +Toggle 1to0 tdata [233] "logic tdata[511:0]" +Toggle 0to1 tdata [234] "logic tdata[511:0]" +Toggle 1to0 tdata [234] "logic tdata[511:0]" +Toggle 0to1 tdata [235] "logic tdata[511:0]" +Toggle 1to0 tdata [235] "logic tdata[511:0]" +Toggle 0to1 tdata [236] "logic tdata[511:0]" +Toggle 1to0 tdata [236] "logic tdata[511:0]" +Toggle 0to1 tdata [237] "logic tdata[511:0]" +Toggle 1to0 tdata [237] "logic tdata[511:0]" +Toggle 0to1 tdata [238] "logic tdata[511:0]" +Toggle 1to0 tdata [238] "logic tdata[511:0]" +Toggle 0to1 tdata [239] "logic tdata[511:0]" +Toggle 1to0 tdata [239] "logic tdata[511:0]" +Toggle 0to1 tdata [240] "logic tdata[511:0]" +Toggle 1to0 tdata [240] "logic tdata[511:0]" +Toggle 0to1 tdata [241] "logic tdata[511:0]" +Toggle 1to0 tdata [241] "logic tdata[511:0]" +Toggle 0to1 tdata [242] "logic tdata[511:0]" +Toggle 1to0 tdata [242] "logic tdata[511:0]" +Toggle 0to1 tdata [243] "logic tdata[511:0]" +Toggle 1to0 tdata [243] "logic tdata[511:0]" +Toggle 0to1 tdata [244] "logic tdata[511:0]" +Toggle 1to0 tdata [244] "logic tdata[511:0]" +Toggle 0to1 tdata [245] "logic tdata[511:0]" +Toggle 1to0 tdata [245] "logic tdata[511:0]" +Toggle 0to1 tdata [246] "logic tdata[511:0]" +Toggle 1to0 tdata [246] "logic tdata[511:0]" +Toggle 0to1 tdata [247] "logic tdata[511:0]" +Toggle 1to0 tdata [247] "logic tdata[511:0]" +Toggle 0to1 tdata [248] "logic tdata[511:0]" +Toggle 1to0 tdata [248] "logic tdata[511:0]" +Toggle 0to1 tdata [249] "logic tdata[511:0]" +Toggle 1to0 tdata [249] "logic tdata[511:0]" +Toggle 0to1 tdata [250] "logic tdata[511:0]" +Toggle 1to0 tdata [250] "logic tdata[511:0]" +Toggle 0to1 tdata [251] "logic tdata[511:0]" +Toggle 1to0 tdata [251] "logic tdata[511:0]" +Toggle 0to1 tdata [252] "logic tdata[511:0]" +Toggle 1to0 tdata [252] "logic tdata[511:0]" +Toggle 0to1 tdata [253] "logic tdata[511:0]" +Toggle 1to0 tdata [253] "logic tdata[511:0]" +Toggle 0to1 tdata [254] "logic tdata[511:0]" +Toggle 1to0 tdata [254] "logic tdata[511:0]" +Toggle 0to1 tdata [255] "logic tdata[511:0]" +Toggle 1to0 tdata [255] "logic tdata[511:0]" +Toggle 0to1 tdata [256] "logic tdata[511:0]" +Toggle 1to0 tdata [256] "logic tdata[511:0]" +Toggle 0to1 tdata [257] "logic tdata[511:0]" +Toggle 1to0 tdata [257] "logic tdata[511:0]" +Toggle 0to1 tdata [258] "logic tdata[511:0]" +Toggle 1to0 tdata [258] "logic tdata[511:0]" +Toggle 0to1 tdata [259] "logic tdata[511:0]" +Toggle 1to0 tdata [259] "logic tdata[511:0]" +Toggle 0to1 tdata [260] "logic tdata[511:0]" +Toggle 1to0 tdata [260] "logic tdata[511:0]" +Toggle 0to1 tdata [261] "logic tdata[511:0]" +Toggle 1to0 tdata [261] "logic tdata[511:0]" +Toggle 0to1 tdata [262] "logic tdata[511:0]" +Toggle 1to0 tdata [262] "logic tdata[511:0]" +Toggle 0to1 tdata [263] "logic tdata[511:0]" +Toggle 1to0 tdata [263] "logic tdata[511:0]" +Toggle 0to1 tdata [264] "logic tdata[511:0]" +Toggle 1to0 tdata [264] "logic tdata[511:0]" +Toggle 0to1 tdata [265] "logic tdata[511:0]" +Toggle 1to0 tdata [265] "logic tdata[511:0]" +Toggle 0to1 tdata [266] "logic tdata[511:0]" +Toggle 1to0 tdata [266] "logic tdata[511:0]" +Toggle 0to1 tdata [267] "logic tdata[511:0]" +Toggle 1to0 tdata [267] "logic tdata[511:0]" +Toggle 0to1 tdata [268] "logic tdata[511:0]" +Toggle 1to0 tdata [268] "logic tdata[511:0]" +Toggle 0to1 tdata [269] "logic tdata[511:0]" +Toggle 1to0 tdata [269] "logic tdata[511:0]" +Toggle 0to1 tdata [270] "logic tdata[511:0]" +Toggle 1to0 tdata [270] "logic tdata[511:0]" +Toggle 0to1 tdata [271] "logic tdata[511:0]" +Toggle 1to0 tdata [271] "logic tdata[511:0]" +Toggle 0to1 tdata [272] "logic tdata[511:0]" +Toggle 1to0 tdata [272] "logic tdata[511:0]" +Toggle 0to1 tdata [273] "logic tdata[511:0]" +Toggle 1to0 tdata [273] "logic tdata[511:0]" +Toggle 0to1 tdata [274] "logic tdata[511:0]" +Toggle 1to0 tdata [274] "logic tdata[511:0]" +Toggle 0to1 tdata [275] "logic tdata[511:0]" +Toggle 1to0 tdata [275] "logic tdata[511:0]" +Toggle 0to1 tdata [276] "logic tdata[511:0]" +Toggle 1to0 tdata [276] "logic tdata[511:0]" +Toggle 0to1 tdata [277] "logic tdata[511:0]" +Toggle 1to0 tdata [277] "logic tdata[511:0]" +Toggle 0to1 tdata [278] "logic tdata[511:0]" +Toggle 1to0 tdata [278] "logic tdata[511:0]" +Toggle 0to1 tdata [279] "logic tdata[511:0]" +Toggle 1to0 tdata [279] "logic tdata[511:0]" +Toggle 0to1 tdata [280] "logic tdata[511:0]" +Toggle 1to0 tdata [280] "logic tdata[511:0]" +Toggle 0to1 tdata [281] "logic tdata[511:0]" +Toggle 1to0 tdata [281] "logic tdata[511:0]" +Toggle 0to1 tdata [282] "logic tdata[511:0]" +Toggle 1to0 tdata [282] "logic tdata[511:0]" +Toggle 0to1 tdata [283] "logic tdata[511:0]" +Toggle 1to0 tdata [283] "logic tdata[511:0]" +Toggle 0to1 tdata [284] "logic tdata[511:0]" +Toggle 1to0 tdata [284] "logic tdata[511:0]" +Toggle 0to1 tdata [285] "logic tdata[511:0]" +Toggle 1to0 tdata [285] "logic tdata[511:0]" +Toggle 0to1 tdata [286] "logic tdata[511:0]" +Toggle 1to0 tdata [286] "logic tdata[511:0]" +Toggle 0to1 tdata [287] "logic tdata[511:0]" +Toggle 1to0 tdata [287] "logic tdata[511:0]" +Toggle 0to1 tdata [288] "logic tdata[511:0]" +Toggle 1to0 tdata [288] "logic tdata[511:0]" +Toggle 0to1 tdata [289] "logic tdata[511:0]" +Toggle 1to0 tdata [289] "logic tdata[511:0]" +Toggle 0to1 tdata [290] "logic tdata[511:0]" +Toggle 1to0 tdata [290] "logic tdata[511:0]" +Toggle 0to1 tdata [291] "logic tdata[511:0]" +Toggle 1to0 tdata [291] "logic tdata[511:0]" +Toggle 0to1 tdata [292] "logic tdata[511:0]" +Toggle 1to0 tdata [292] "logic tdata[511:0]" +Toggle 0to1 tdata [293] "logic tdata[511:0]" +Toggle 1to0 tdata [293] "logic tdata[511:0]" +Toggle 0to1 tdata [294] "logic tdata[511:0]" +Toggle 1to0 tdata [294] "logic tdata[511:0]" +Toggle 0to1 tdata [295] "logic tdata[511:0]" +Toggle 1to0 tdata [295] "logic tdata[511:0]" +Toggle 0to1 tdata [296] "logic tdata[511:0]" +Toggle 1to0 tdata [296] "logic tdata[511:0]" +Toggle 0to1 tdata [297] "logic tdata[511:0]" +Toggle 1to0 tdata [297] "logic tdata[511:0]" +Toggle 0to1 tdata [298] "logic tdata[511:0]" +Toggle 1to0 tdata [298] "logic tdata[511:0]" +Toggle 0to1 tdata [299] "logic tdata[511:0]" +Toggle 1to0 tdata [299] "logic tdata[511:0]" +Toggle 0to1 tdata [300] "logic tdata[511:0]" +Toggle 1to0 tdata [300] "logic tdata[511:0]" +Toggle 0to1 tdata [301] "logic tdata[511:0]" +Toggle 1to0 tdata [301] "logic tdata[511:0]" +Toggle 0to1 tdata [302] "logic tdata[511:0]" +Toggle 1to0 tdata [302] "logic tdata[511:0]" +Toggle 0to1 tdata [303] "logic tdata[511:0]" +Toggle 1to0 tdata [303] "logic tdata[511:0]" +Toggle 0to1 tdata [304] "logic tdata[511:0]" +Toggle 1to0 tdata [304] "logic tdata[511:0]" +Toggle 0to1 tdata [305] "logic tdata[511:0]" +Toggle 1to0 tdata [305] "logic tdata[511:0]" +Toggle 0to1 tdata [306] "logic tdata[511:0]" +Toggle 1to0 tdata [306] "logic tdata[511:0]" +Toggle 0to1 tdata [307] "logic tdata[511:0]" +Toggle 1to0 tdata [307] "logic tdata[511:0]" +Toggle 0to1 tdata [308] "logic tdata[511:0]" +Toggle 1to0 tdata [308] "logic tdata[511:0]" +Toggle 0to1 tdata [309] "logic tdata[511:0]" +Toggle 1to0 tdata [309] "logic tdata[511:0]" +Toggle 0to1 tdata [310] "logic tdata[511:0]" +Toggle 1to0 tdata [310] "logic tdata[511:0]" +Toggle 0to1 tdata [311] "logic tdata[511:0]" +Toggle 1to0 tdata [311] "logic tdata[511:0]" +Toggle 0to1 tdata [312] "logic tdata[511:0]" +Toggle 1to0 tdata [312] "logic tdata[511:0]" +Toggle 0to1 tdata [313] "logic tdata[511:0]" +Toggle 1to0 tdata [313] "logic tdata[511:0]" +Toggle 0to1 tdata [314] "logic tdata[511:0]" +Toggle 1to0 tdata [314] "logic tdata[511:0]" +Toggle 0to1 tdata [315] "logic tdata[511:0]" +Toggle 1to0 tdata [315] "logic tdata[511:0]" +Toggle 0to1 tdata [316] "logic tdata[511:0]" +Toggle 1to0 tdata [316] "logic tdata[511:0]" +Toggle 0to1 tdata [317] "logic tdata[511:0]" +Toggle 1to0 tdata [317] "logic tdata[511:0]" +Toggle 0to1 tdata [318] "logic tdata[511:0]" +Toggle 1to0 tdata [318] "logic tdata[511:0]" +Toggle 0to1 tdata [319] "logic tdata[511:0]" +Toggle 1to0 tdata [319] "logic tdata[511:0]" +Toggle 0to1 tdata [320] "logic tdata[511:0]" +Toggle 1to0 tdata [320] "logic tdata[511:0]" +Toggle 0to1 tdata [321] "logic tdata[511:0]" +Toggle 1to0 tdata [321] "logic tdata[511:0]" +Toggle 0to1 tdata [322] "logic tdata[511:0]" +Toggle 1to0 tdata [322] "logic tdata[511:0]" +Toggle 0to1 tdata [323] "logic tdata[511:0]" +Toggle 1to0 tdata [323] "logic tdata[511:0]" +Toggle 0to1 tdata [324] "logic tdata[511:0]" +Toggle 1to0 tdata [324] "logic tdata[511:0]" +Toggle 0to1 tdata [325] "logic tdata[511:0]" +Toggle 1to0 tdata [325] "logic tdata[511:0]" +Toggle 0to1 tdata [326] "logic tdata[511:0]" +Toggle 1to0 tdata [326] "logic tdata[511:0]" +Toggle 0to1 tdata [327] "logic tdata[511:0]" +Toggle 1to0 tdata [327] "logic tdata[511:0]" +Toggle 0to1 tdata [328] "logic tdata[511:0]" +Toggle 1to0 tdata [328] "logic tdata[511:0]" +Toggle 0to1 tdata [329] "logic tdata[511:0]" +Toggle 1to0 tdata [329] "logic tdata[511:0]" +Toggle 0to1 tdata [330] "logic tdata[511:0]" +Toggle 1to0 tdata [330] "logic tdata[511:0]" +Toggle 0to1 tdata [331] "logic tdata[511:0]" +Toggle 1to0 tdata [331] "logic tdata[511:0]" +Toggle 0to1 tdata [332] "logic tdata[511:0]" +Toggle 1to0 tdata [332] "logic tdata[511:0]" +Toggle 0to1 tdata [333] "logic tdata[511:0]" +Toggle 1to0 tdata [333] "logic tdata[511:0]" +Toggle 0to1 tdata [334] "logic tdata[511:0]" +Toggle 1to0 tdata [334] "logic tdata[511:0]" +Toggle 0to1 tdata [335] "logic tdata[511:0]" +Toggle 1to0 tdata [335] "logic tdata[511:0]" +Toggle 0to1 tdata [336] "logic tdata[511:0]" +Toggle 1to0 tdata [336] "logic tdata[511:0]" +Toggle 0to1 tdata [337] "logic tdata[511:0]" +Toggle 1to0 tdata [337] "logic tdata[511:0]" +Toggle 0to1 tdata [338] "logic tdata[511:0]" +Toggle 1to0 tdata [338] "logic tdata[511:0]" +Toggle 0to1 tdata [339] "logic tdata[511:0]" +Toggle 1to0 tdata [339] "logic tdata[511:0]" +Toggle 0to1 tdata [340] "logic tdata[511:0]" +Toggle 1to0 tdata [340] "logic tdata[511:0]" +Toggle 0to1 tdata [341] "logic tdata[511:0]" +Toggle 1to0 tdata [341] "logic tdata[511:0]" +Toggle 0to1 tdata [342] "logic tdata[511:0]" +Toggle 1to0 tdata [342] "logic tdata[511:0]" +Toggle 0to1 tdata [343] "logic tdata[511:0]" +Toggle 1to0 tdata [343] "logic tdata[511:0]" +Toggle 0to1 tdata [344] "logic tdata[511:0]" +Toggle 1to0 tdata [344] "logic tdata[511:0]" +Toggle 0to1 tdata [345] "logic tdata[511:0]" +Toggle 1to0 tdata [345] "logic tdata[511:0]" +Toggle 0to1 tdata [346] "logic tdata[511:0]" +Toggle 1to0 tdata [346] "logic tdata[511:0]" +Toggle 0to1 tdata [347] "logic tdata[511:0]" +Toggle 1to0 tdata [347] "logic tdata[511:0]" +Toggle 0to1 tdata [348] "logic tdata[511:0]" +Toggle 1to0 tdata [348] "logic tdata[511:0]" +Toggle 0to1 tdata [349] "logic tdata[511:0]" +Toggle 1to0 tdata [349] "logic tdata[511:0]" +Toggle 0to1 tdata [350] "logic tdata[511:0]" +Toggle 1to0 tdata [350] "logic tdata[511:0]" +Toggle 0to1 tdata [351] "logic tdata[511:0]" +Toggle 1to0 tdata [351] "logic tdata[511:0]" +Toggle 0to1 tdata [352] "logic tdata[511:0]" +Toggle 1to0 tdata [352] "logic tdata[511:0]" +Toggle 0to1 tdata [353] "logic tdata[511:0]" +Toggle 1to0 tdata [353] "logic tdata[511:0]" +Toggle 0to1 tdata [354] "logic tdata[511:0]" +Toggle 1to0 tdata [354] "logic tdata[511:0]" +Toggle 0to1 tdata [355] "logic tdata[511:0]" +Toggle 1to0 tdata [355] "logic tdata[511:0]" +Toggle 0to1 tdata [356] "logic tdata[511:0]" +Toggle 1to0 tdata [356] "logic tdata[511:0]" +Toggle 0to1 tdata [357] "logic tdata[511:0]" +Toggle 1to0 tdata [357] "logic tdata[511:0]" +Toggle 0to1 tdata [358] "logic tdata[511:0]" +Toggle 1to0 tdata [358] "logic tdata[511:0]" +Toggle 0to1 tdata [359] "logic tdata[511:0]" +Toggle 1to0 tdata [359] "logic tdata[511:0]" +Toggle 0to1 tdata [360] "logic tdata[511:0]" +Toggle 1to0 tdata [360] "logic tdata[511:0]" +Toggle 0to1 tdata [361] "logic tdata[511:0]" +Toggle 1to0 tdata [361] "logic tdata[511:0]" +Toggle 0to1 tdata [362] "logic tdata[511:0]" +Toggle 1to0 tdata [362] "logic tdata[511:0]" +Toggle 0to1 tdata [363] "logic tdata[511:0]" +Toggle 1to0 tdata [363] "logic tdata[511:0]" +Toggle 0to1 tdata [364] "logic tdata[511:0]" +Toggle 1to0 tdata [364] "logic tdata[511:0]" +Toggle 0to1 tdata [365] "logic tdata[511:0]" +Toggle 1to0 tdata [365] "logic tdata[511:0]" +Toggle 0to1 tdata [366] "logic tdata[511:0]" +Toggle 1to0 tdata [366] "logic tdata[511:0]" +Toggle 0to1 tdata [367] "logic tdata[511:0]" +Toggle 1to0 tdata [367] "logic tdata[511:0]" +Toggle 0to1 tdata [368] "logic tdata[511:0]" +Toggle 1to0 tdata [368] "logic tdata[511:0]" +Toggle 0to1 tdata [369] "logic tdata[511:0]" +Toggle 1to0 tdata [369] "logic tdata[511:0]" +Toggle 0to1 tdata [370] "logic tdata[511:0]" +Toggle 1to0 tdata [370] "logic tdata[511:0]" +Toggle 0to1 tdata [371] "logic tdata[511:0]" +Toggle 1to0 tdata [371] "logic tdata[511:0]" +Toggle 0to1 tdata [372] "logic tdata[511:0]" +Toggle 1to0 tdata [372] "logic tdata[511:0]" +Toggle 0to1 tdata [373] "logic tdata[511:0]" +Toggle 1to0 tdata [373] "logic tdata[511:0]" +Toggle 0to1 tdata [374] "logic tdata[511:0]" +Toggle 1to0 tdata [374] "logic tdata[511:0]" +Toggle 0to1 tdata [375] "logic tdata[511:0]" +Toggle 1to0 tdata [375] "logic tdata[511:0]" +Toggle 0to1 tdata [376] "logic tdata[511:0]" +Toggle 1to0 tdata [376] "logic tdata[511:0]" +Toggle 0to1 tdata [377] "logic tdata[511:0]" +Toggle 1to0 tdata [377] "logic tdata[511:0]" +Toggle 0to1 tdata [378] "logic tdata[511:0]" +Toggle 1to0 tdata [378] "logic tdata[511:0]" +Toggle 0to1 tdata [379] "logic tdata[511:0]" +Toggle 1to0 tdata [379] "logic tdata[511:0]" +Toggle 0to1 tdata [380] "logic tdata[511:0]" +Toggle 1to0 tdata [380] "logic tdata[511:0]" +Toggle 0to1 tdata [381] "logic tdata[511:0]" +Toggle 1to0 tdata [381] "logic tdata[511:0]" +Toggle 0to1 tdata [382] "logic tdata[511:0]" +Toggle 1to0 tdata [382] "logic tdata[511:0]" +Toggle 0to1 tdata [383] "logic tdata[511:0]" +Toggle 1to0 tdata [383] "logic tdata[511:0]" +Toggle 0to1 tdata [384] "logic tdata[511:0]" +Toggle 1to0 tdata [384] "logic tdata[511:0]" +Toggle 0to1 tdata [385] "logic tdata[511:0]" +Toggle 1to0 tdata [385] "logic tdata[511:0]" +Toggle 0to1 tdata [386] "logic tdata[511:0]" +Toggle 1to0 tdata [386] "logic tdata[511:0]" +Toggle 0to1 tdata [387] "logic tdata[511:0]" +Toggle 1to0 tdata [387] "logic tdata[511:0]" +Toggle 0to1 tdata [388] "logic tdata[511:0]" +Toggle 1to0 tdata [388] "logic tdata[511:0]" +Toggle 0to1 tdata [389] "logic tdata[511:0]" +Toggle 1to0 tdata [389] "logic tdata[511:0]" +Toggle 0to1 tdata [390] "logic tdata[511:0]" +Toggle 1to0 tdata [390] "logic tdata[511:0]" +Toggle 0to1 tdata [391] "logic tdata[511:0]" +Toggle 1to0 tdata [391] "logic tdata[511:0]" +Toggle 0to1 tdata [392] "logic tdata[511:0]" +Toggle 1to0 tdata [392] "logic tdata[511:0]" +Toggle 0to1 tdata [393] "logic tdata[511:0]" +Toggle 1to0 tdata [393] "logic tdata[511:0]" +Toggle 0to1 tdata [394] "logic tdata[511:0]" +Toggle 1to0 tdata [394] "logic tdata[511:0]" +Toggle 0to1 tdata [395] "logic tdata[511:0]" +Toggle 1to0 tdata [395] "logic tdata[511:0]" +Toggle 0to1 tdata [396] "logic tdata[511:0]" +Toggle 1to0 tdata [396] "logic tdata[511:0]" +Toggle 0to1 tdata [397] "logic tdata[511:0]" +Toggle 1to0 tdata [397] "logic tdata[511:0]" +Toggle 0to1 tdata [398] "logic tdata[511:0]" +Toggle 1to0 tdata [398] "logic tdata[511:0]" +Toggle 0to1 tdata [399] "logic tdata[511:0]" +Toggle 1to0 tdata [399] "logic tdata[511:0]" +Toggle 0to1 tdata [400] "logic tdata[511:0]" +Toggle 1to0 tdata [400] "logic tdata[511:0]" +Toggle 0to1 tdata [401] "logic tdata[511:0]" +Toggle 1to0 tdata [401] "logic tdata[511:0]" +Toggle 0to1 tdata [402] "logic tdata[511:0]" +Toggle 1to0 tdata [402] "logic tdata[511:0]" +Toggle 0to1 tdata [403] "logic tdata[511:0]" +Toggle 1to0 tdata [403] "logic tdata[511:0]" +Toggle 0to1 tdata [404] "logic tdata[511:0]" +Toggle 1to0 tdata [404] "logic tdata[511:0]" +Toggle 0to1 tdata [405] "logic tdata[511:0]" +Toggle 1to0 tdata [405] "logic tdata[511:0]" +Toggle 0to1 tdata [406] "logic tdata[511:0]" +Toggle 1to0 tdata [406] "logic tdata[511:0]" +Toggle 0to1 tdata [407] "logic tdata[511:0]" +Toggle 1to0 tdata [407] "logic tdata[511:0]" +Toggle 0to1 tdata [408] "logic tdata[511:0]" +Toggle 1to0 tdata [408] "logic tdata[511:0]" +Toggle 0to1 tdata [409] "logic tdata[511:0]" +Toggle 1to0 tdata [409] "logic tdata[511:0]" +Toggle 0to1 tdata [410] "logic tdata[511:0]" +Toggle 1to0 tdata [410] "logic tdata[511:0]" +Toggle 0to1 tdata [411] "logic tdata[511:0]" +Toggle 1to0 tdata [411] "logic tdata[511:0]" +Toggle 0to1 tdata [412] "logic tdata[511:0]" +Toggle 1to0 tdata [412] "logic tdata[511:0]" +Toggle 0to1 tdata [413] "logic tdata[511:0]" +Toggle 1to0 tdata [413] "logic tdata[511:0]" +Toggle 0to1 tdata [414] "logic tdata[511:0]" +Toggle 1to0 tdata [414] "logic tdata[511:0]" +Toggle 0to1 tdata [415] "logic tdata[511:0]" +Toggle 1to0 tdata [415] "logic tdata[511:0]" +Toggle 0to1 tdata [416] "logic tdata[511:0]" +Toggle 1to0 tdata [416] "logic tdata[511:0]" +Toggle 0to1 tdata [417] "logic tdata[511:0]" +Toggle 1to0 tdata [417] "logic tdata[511:0]" +Toggle 0to1 tdata [418] "logic tdata[511:0]" +Toggle 1to0 tdata [418] "logic tdata[511:0]" +Toggle 0to1 tdata [419] "logic tdata[511:0]" +Toggle 1to0 tdata [419] "logic tdata[511:0]" +Toggle 0to1 tdata [420] "logic tdata[511:0]" +Toggle 1to0 tdata [420] "logic tdata[511:0]" +Toggle 0to1 tdata [421] "logic tdata[511:0]" +Toggle 1to0 tdata [421] "logic tdata[511:0]" +Toggle 0to1 tdata [422] "logic tdata[511:0]" +Toggle 1to0 tdata [422] "logic tdata[511:0]" +Toggle 0to1 tdata [423] "logic tdata[511:0]" +Toggle 1to0 tdata [423] "logic tdata[511:0]" +Toggle 0to1 tdata [424] "logic tdata[511:0]" +Toggle 1to0 tdata [424] "logic tdata[511:0]" +Toggle 0to1 tdata [425] "logic tdata[511:0]" +Toggle 1to0 tdata [425] "logic tdata[511:0]" +Toggle 0to1 tdata [426] "logic tdata[511:0]" +Toggle 1to0 tdata [426] "logic tdata[511:0]" +Toggle 0to1 tdata [427] "logic tdata[511:0]" +Toggle 1to0 tdata [427] "logic tdata[511:0]" +Toggle 0to1 tdata [428] "logic tdata[511:0]" +Toggle 1to0 tdata [428] "logic tdata[511:0]" +Toggle 0to1 tdata [429] "logic tdata[511:0]" +Toggle 1to0 tdata [429] "logic tdata[511:0]" +Toggle 0to1 tdata [430] "logic tdata[511:0]" +Toggle 1to0 tdata [430] "logic tdata[511:0]" +Toggle 0to1 tdata [431] "logic tdata[511:0]" +Toggle 1to0 tdata [431] "logic tdata[511:0]" +Toggle 0to1 tdata [432] "logic tdata[511:0]" +Toggle 1to0 tdata [432] "logic tdata[511:0]" +Toggle 0to1 tdata [433] "logic tdata[511:0]" +Toggle 1to0 tdata [433] "logic tdata[511:0]" +Toggle 0to1 tdata [434] "logic tdata[511:0]" +Toggle 1to0 tdata [434] "logic tdata[511:0]" +Toggle 0to1 tdata [435] "logic tdata[511:0]" +Toggle 1to0 tdata [435] "logic tdata[511:0]" +Toggle 0to1 tdata [436] "logic tdata[511:0]" +Toggle 1to0 tdata [436] "logic tdata[511:0]" +Toggle 0to1 tdata [437] "logic tdata[511:0]" +Toggle 1to0 tdata [437] "logic tdata[511:0]" +Toggle 0to1 tdata [438] "logic tdata[511:0]" +Toggle 1to0 tdata [438] "logic tdata[511:0]" +Toggle 0to1 tdata [439] "logic tdata[511:0]" +Toggle 1to0 tdata [439] "logic tdata[511:0]" +Toggle 0to1 tdata [440] "logic tdata[511:0]" +Toggle 1to0 tdata [440] "logic tdata[511:0]" +Toggle 0to1 tdata [441] "logic tdata[511:0]" +Toggle 1to0 tdata [441] "logic tdata[511:0]" +Toggle 0to1 tdata [442] "logic tdata[511:0]" +Toggle 1to0 tdata [442] "logic tdata[511:0]" +Toggle 0to1 tdata [443] "logic tdata[511:0]" +Toggle 1to0 tdata [443] "logic tdata[511:0]" +Toggle 0to1 tdata [444] "logic tdata[511:0]" +Toggle 1to0 tdata [444] "logic tdata[511:0]" +Toggle 0to1 tdata [445] "logic tdata[511:0]" +Toggle 1to0 tdata [445] "logic tdata[511:0]" +Toggle 0to1 tdata [446] "logic tdata[511:0]" +Toggle 1to0 tdata [446] "logic tdata[511:0]" +Toggle 0to1 tdata [447] "logic tdata[511:0]" +Toggle 1to0 tdata [447] "logic tdata[511:0]" +Toggle 0to1 tdata [448] "logic tdata[511:0]" +Toggle 1to0 tdata [448] "logic tdata[511:0]" +Toggle 0to1 tdata [449] "logic tdata[511:0]" +Toggle 1to0 tdata [449] "logic tdata[511:0]" +Toggle 0to1 tdata [450] "logic tdata[511:0]" +Toggle 1to0 tdata [450] "logic tdata[511:0]" +Toggle 0to1 tdata [451] "logic tdata[511:0]" +Toggle 1to0 tdata [451] "logic tdata[511:0]" +Toggle 0to1 tdata [452] "logic tdata[511:0]" +Toggle 1to0 tdata [452] "logic tdata[511:0]" +Toggle 0to1 tdata [453] "logic tdata[511:0]" +Toggle 1to0 tdata [453] "logic tdata[511:0]" +Toggle 0to1 tdata [454] "logic tdata[511:0]" +Toggle 1to0 tdata [454] "logic tdata[511:0]" +Toggle 0to1 tdata [455] "logic tdata[511:0]" +Toggle 1to0 tdata [455] "logic tdata[511:0]" +Toggle 0to1 tdata [456] "logic tdata[511:0]" +Toggle 1to0 tdata [456] "logic tdata[511:0]" +Toggle 0to1 tdata [457] "logic tdata[511:0]" +Toggle 1to0 tdata [457] "logic tdata[511:0]" +Toggle 0to1 tdata [458] "logic tdata[511:0]" +Toggle 1to0 tdata [458] "logic tdata[511:0]" +Toggle 0to1 tdata [459] "logic tdata[511:0]" +Toggle 1to0 tdata [459] "logic tdata[511:0]" +Toggle 0to1 tdata [460] "logic tdata[511:0]" +Toggle 1to0 tdata [460] "logic tdata[511:0]" +Toggle 0to1 tdata [461] "logic tdata[511:0]" +Toggle 1to0 tdata [461] "logic tdata[511:0]" +Toggle 0to1 tdata [462] "logic tdata[511:0]" +Toggle 1to0 tdata [462] "logic tdata[511:0]" +Toggle 0to1 tdata [463] "logic tdata[511:0]" +Toggle 1to0 tdata [463] "logic tdata[511:0]" +Toggle 0to1 tdata [464] "logic tdata[511:0]" +Toggle 1to0 tdata [464] "logic tdata[511:0]" +Toggle 0to1 tdata [465] "logic tdata[511:0]" +Toggle 1to0 tdata [465] "logic tdata[511:0]" +Toggle 0to1 tdata [466] "logic tdata[511:0]" +Toggle 1to0 tdata [466] "logic tdata[511:0]" +Toggle 0to1 tdata [467] "logic tdata[511:0]" +Toggle 1to0 tdata [467] "logic tdata[511:0]" +Toggle 0to1 tdata [468] "logic tdata[511:0]" +Toggle 1to0 tdata [468] "logic tdata[511:0]" +Toggle 0to1 tdata [469] "logic tdata[511:0]" +Toggle 1to0 tdata [469] "logic tdata[511:0]" +Toggle 0to1 tdata [470] "logic tdata[511:0]" +Toggle 1to0 tdata [470] "logic tdata[511:0]" +Toggle 0to1 tdata [471] "logic tdata[511:0]" +Toggle 1to0 tdata [471] "logic tdata[511:0]" +Toggle 0to1 tdata [472] "logic tdata[511:0]" +Toggle 1to0 tdata [472] "logic tdata[511:0]" +Toggle 0to1 tdata [473] "logic tdata[511:0]" +Toggle 1to0 tdata [473] "logic tdata[511:0]" +Toggle 0to1 tdata [474] "logic tdata[511:0]" +Toggle 1to0 tdata [474] "logic tdata[511:0]" +Toggle 0to1 tdata [475] "logic tdata[511:0]" +Toggle 1to0 tdata [475] "logic tdata[511:0]" +Toggle 0to1 tdata [476] "logic tdata[511:0]" +Toggle 1to0 tdata [476] "logic tdata[511:0]" +Toggle 0to1 tdata [477] "logic tdata[511:0]" +Toggle 1to0 tdata [477] "logic tdata[511:0]" +Toggle 0to1 tdata [478] "logic tdata[511:0]" +Toggle 1to0 tdata [478] "logic tdata[511:0]" +Toggle 0to1 tdata [479] "logic tdata[511:0]" +Toggle 1to0 tdata [479] "logic tdata[511:0]" +Toggle 0to1 tdata [480] "logic tdata[511:0]" +Toggle 1to0 tdata [480] "logic tdata[511:0]" +Toggle 0to1 tdata [481] "logic tdata[511:0]" +Toggle 1to0 tdata [481] "logic tdata[511:0]" +Toggle 0to1 tdata [482] "logic tdata[511:0]" +Toggle 1to0 tdata [482] "logic tdata[511:0]" +Toggle 0to1 tdata [483] "logic tdata[511:0]" +Toggle 1to0 tdata [483] "logic tdata[511:0]" +Toggle 0to1 tdata [484] "logic tdata[511:0]" +Toggle 1to0 tdata [484] "logic tdata[511:0]" +Toggle 0to1 tdata [485] "logic tdata[511:0]" +Toggle 1to0 tdata [485] "logic tdata[511:0]" +Toggle 0to1 tdata [486] "logic tdata[511:0]" +Toggle 1to0 tdata [486] "logic tdata[511:0]" +Toggle 0to1 tdata [487] "logic tdata[511:0]" +Toggle 1to0 tdata [487] "logic tdata[511:0]" +Toggle 0to1 tdata [488] "logic tdata[511:0]" +Toggle 1to0 tdata [488] "logic tdata[511:0]" +Toggle 0to1 tdata [489] "logic tdata[511:0]" +Toggle 1to0 tdata [489] "logic tdata[511:0]" +Toggle 0to1 tdata [490] "logic tdata[511:0]" +Toggle 1to0 tdata [490] "logic tdata[511:0]" +Toggle 0to1 tdata [491] "logic tdata[511:0]" +Toggle 1to0 tdata [491] "logic tdata[511:0]" +Toggle 0to1 tdata [492] "logic tdata[511:0]" +Toggle 1to0 tdata [492] "logic tdata[511:0]" +Toggle 0to1 tdata [493] "logic tdata[511:0]" +Toggle 1to0 tdata [493] "logic tdata[511:0]" +Toggle 0to1 tdata [494] "logic tdata[511:0]" +Toggle 1to0 tdata [494] "logic tdata[511:0]" +Toggle 0to1 tdata [495] "logic tdata[511:0]" +Toggle 1to0 tdata [495] "logic tdata[511:0]" +Toggle 0to1 tdata [496] "logic tdata[511:0]" +Toggle 1to0 tdata [496] "logic tdata[511:0]" +Toggle 0to1 tdata [497] "logic tdata[511:0]" +Toggle 1to0 tdata [497] "logic tdata[511:0]" +Toggle 0to1 tdata [498] "logic tdata[511:0]" +Toggle 1to0 tdata [498] "logic tdata[511:0]" +Toggle 0to1 tdata [499] "logic tdata[511:0]" +Toggle 1to0 tdata [499] "logic tdata[511:0]" +Toggle 0to1 tdata [500] "logic tdata[511:0]" +Toggle 1to0 tdata [500] "logic tdata[511:0]" +Toggle 0to1 tdata [501] "logic tdata[511:0]" +Toggle 1to0 tdata [501] "logic tdata[511:0]" +Toggle 0to1 tdata [502] "logic tdata[511:0]" +Toggle 1to0 tdata [502] "logic tdata[511:0]" +Toggle 0to1 tdata [503] "logic tdata[511:0]" +Toggle 1to0 tdata [503] "logic tdata[511:0]" +Toggle 0to1 tdata [504] "logic tdata[511:0]" +Toggle 1to0 tdata [504] "logic tdata[511:0]" +Toggle 0to1 tdata [505] "logic tdata[511:0]" +Toggle 1to0 tdata [505] "logic tdata[511:0]" +Toggle 0to1 tdata [506] "logic tdata[511:0]" +Toggle 1to0 tdata [506] "logic tdata[511:0]" +Toggle 0to1 tdata [507] "logic tdata[511:0]" +Toggle 1to0 tdata [507] "logic tdata[511:0]" +Toggle 0to1 tdata [508] "logic tdata[511:0]" +Toggle 1to0 tdata [508] "logic tdata[511:0]" +Toggle 0to1 tdata [509] "logic tdata[511:0]" +Toggle 1to0 tdata [509] "logic tdata[511:0]" +Toggle 0to1 tdata [510] "logic tdata[511:0]" +Toggle 1to0 tdata [510] "logic tdata[511:0]" +Toggle 0to1 tdata [6] "logic tdata[511:0]" +CHECKSUM: "1656915986 3885313134" +INSTANCE: tb_top.DUT.afu_top.local_commit +ANNOTATION: " value is 'h0 " +Toggle rx_cmp_dm_intr.pref "logic rx_cmp_dm_intr.pref[23:0]" +Toggle 1to0 rx_cmp_dm_intr.pref_present "logic rx_cmp_dm_intr.pref_present" +Toggle 0to1 rx_cmp_dm_intr.pref_present "logic rx_cmp_dm_intr.pref_present" +ANNOTATION: " value is 'h0 " +Toggle rx_cmp_dm_intr.pref_type "logic rx_cmp_dm_intr.pref_type[4:0]" +ANNOTATION: " value is 'h0 " +Toggle rx_cmp_dm_intr.metadata_h "logic rx_cmp_dm_intr.metadata_h[31:0]" +ANNOTATION: " value is 'h0 " +Toggle rx_cmp_dm_intr.low_addr_l "logic rx_cmp_dm_intr.low_addr_l[7:0]" +ANNOTATION: " value is 'h0 " +Toggle rx_cmp_dm_intr.low_addr_h "logic rx_cmp_dm_intr.low_addr_h[15:0]" +ANNOTATION: " value is 'h0 " +Toggle rx_cmp_dm_intr.length_m "logic rx_cmp_dm_intr.length_m[9:0]" +Toggle rx_cmp_dm_intr.cpl_status "logic rx_cmp_dm_intr.cpl_status[2:0]" +ANNOTATION: " value is 'h0 " +Toggle rx_cmp_pu_hdr.comp_id "logic rx_cmp_pu_hdr.comp_id[15:0]" +ANNOTATION: " value will be constant " +Toggle rx_cmp_pu_hdr.fmt_type "logic rx_cmp_pu_hdr.fmt_type[7:0]" +ANNOTATION: " value is 'h0 " +Toggle rx_cmp_pu_hdr.low_addr "logic rx_cmp_pu_hdr.low_addr[6:0]" +ANNOTATION: " value is 'h0 " +Toggle rx_cmp_pu_hdr.cpl_status "logic rx_cmp_pu_hdr.cpl_status[2:0]" +Toggle 1to0 rx_cmp_pu_hdr.byte_count [0] "logic rx_cmp_pu_hdr.byte_count[11:0]" +Toggle 0to1 rx_cmp_pu_hdr.byte_count [0] "logic rx_cmp_pu_hdr.byte_count[11:0]" +Toggle 1to0 rx_cmp_pu_hdr.byte_count [1] "logic rx_cmp_pu_hdr.byte_count[11:0]" +Toggle 0to1 rx_cmp_pu_hdr.byte_count [1] "logic rx_cmp_pu_hdr.byte_count[11:0]" +Toggle 1to0 rx_cmp_pu_hdr.bcm "logic rx_cmp_pu_hdr.bcm" +Toggle 0to1 rx_cmp_pu_hdr.bcm "logic rx_cmp_pu_hdr.bcm" +Toggle 1to0 rx_cmp_pu_hdr.pref_present "logic rx_cmp_pu_hdr.pref_present" +Toggle 0to1 rx_cmp_pu_hdr.pref_present "logic rx_cmp_pu_hdr.pref_present" +ANNOTATION: " Always value will be 'h0 " +Toggle rx_cmp_pu_hdr.pref "logic rx_cmp_pu_hdr.pref[23:0]" +Toggle 1to0 rx_cmp_pu_hdr.mm_mode "logic rx_cmp_pu_hdr.mm_mode" +Toggle 0to1 rx_cmp_pu_hdr.mm_mode "logic rx_cmp_pu_hdr.mm_mode" +ANNOTATION: " Always value will be 'h0 " +Toggle rx_cmp_pu_hdr.pref_type "logic rx_cmp_pu_hdr.pref_type[4:0]" +Toggle rx_cmp_pu_hdr.slot_num "logic rx_cmp_pu_hdr.slot_num[4:0]" +Toggle rx_cmp_dm_intr.slot_num "logic rx_cmp_dm_intr.slot_num[4:0]" +Toggle rx_cmp_dm_hdr.slot_num "logic rx_cmp_dm_hdr.slot_num[4:0]" +Toggle 1to0 commit_in_ready "net commit_in_ready" +Toggle 0to1 commit_in_ready "net commit_in_ready" +ANNOTATION: " value will be constant " +Toggle rx_cmp_pu_hdr.attr.AT "logic rx_cmp_pu_hdr.attr.AT[1:0]" +Toggle 1to0 rx_cmp_pu_hdr.attr.EP "logic rx_cmp_pu_hdr.attr.EP" +Toggle 0to1 rx_cmp_pu_hdr.attr.EP "logic rx_cmp_pu_hdr.attr.EP" +Toggle 1to0 rx_cmp_pu_hdr.attr.LN "logic rx_cmp_pu_hdr.attr.LN" +Toggle 0to1 rx_cmp_pu_hdr.attr.LN "logic rx_cmp_pu_hdr.attr.LN" +Toggle 1to0 rx_cmp_pu_hdr.attr.TD "logic rx_cmp_pu_hdr.attr.TD" +Toggle 0to1 rx_cmp_pu_hdr.attr.TD "logic rx_cmp_pu_hdr.attr.TD" +Toggle 1to0 rx_cmp_pu_hdr.attr.TH "logic rx_cmp_pu_hdr.attr.TH" +Toggle 0to1 rx_cmp_pu_hdr.attr.TH "logic rx_cmp_pu_hdr.attr.TH" +ANNOTATION: " value will be constant " +Toggle rx_cmp_pu_hdr.TC "logic rx_cmp_pu_hdr.TC[2:0]" +Toggle rx_cmp_dm_intr.rsvd7 "logic rx_cmp_dm_intr.rsvd7[15:0]" +Toggle rx_cmp_dm_intr.rsvd8 "logic rx_cmp_dm_intr.rsvd8[12:0]" +Toggle 1to0 rx_cmp_dm_intr.rsvd9 "logic rx_cmp_dm_intr.rsvd9" +Toggle 0to1 rx_cmp_dm_intr.rsvd9 "logic rx_cmp_dm_intr.rsvd9" +Toggle 1to0 rx_cmp_dm_intr.rsvd10 "logic rx_cmp_dm_intr.rsvd10" +Toggle 0to1 rx_cmp_dm_intr.rsvd10 "logic rx_cmp_dm_intr.rsvd10" +Toggle rx_cmp_dm_intr.rsvd6 "logic rx_cmp_dm_intr.rsvd6[7:0]" +ANNOTATION: " value is 'h0 " +Toggle rx_cmp_dm_intr.fmt_type "logic rx_cmp_dm_intr.fmt_type[7:0]" +ANNOTATION: " value is 'h0 " +Toggle rx_cmp_dm_intr.length_h "logic rx_cmp_dm_intr.length_h[1:0]" +ANNOTATION: " value is 'h0 " +Toggle rx_cmp_dm_intr.length_l "logic rx_cmp_dm_intr.length_l[1:0]" +Toggle 1to0 rx_cmp_dm_intr.mm_mode "logic rx_cmp_dm_intr.mm_mode" +Toggle 0to1 rx_cmp_dm_intr.mm_mode "logic rx_cmp_dm_intr.mm_mode" +Toggle rx_cmp_dm_intr.rsvd1 "logic rx_cmp_dm_intr.rsvd1[6:0]" +Toggle rx_cmp_dm_intr.rsvd2 "logic rx_cmp_dm_intr.rsvd2[3:0]" +Toggle rx_cmp_dm_intr.rsvd3 "logic rx_cmp_dm_intr.rsvd3[1:0]" +Toggle 1to0 rx_cmp_dm_intr.rsvd4 "logic rx_cmp_dm_intr.rsvd4" +Toggle 0to1 rx_cmp_dm_intr.rsvd4 "logic rx_cmp_dm_intr.rsvd4" +Toggle rx_cmp_dm_intr.rsvd5 "logic rx_cmp_dm_intr.rsvd5[15:0]" +Toggle 1to0 rx_cmp_dm_intr.FC "logic rx_cmp_dm_intr.FC" +Toggle 0to1 rx_cmp_dm_intr.FC "logic rx_cmp_dm_intr.FC" +ANNOTATION: " value will be constant " +Toggle rx_cmp_dm_intr.TC "logic rx_cmp_dm_intr.TC[2:0]" +ANNOTATION: " value will be constant " +Toggle rx_cmp_dm_intr.attr.AT "logic rx_cmp_dm_intr.attr.AT[1:0]" +Toggle 1to0 rx_cmp_dm_intr.attr.EP "logic rx_cmp_dm_intr.attr.EP" +Toggle 0to1 rx_cmp_dm_intr.attr.EP "logic rx_cmp_dm_intr.attr.EP" +Toggle 1to0 rx_cmp_dm_intr.attr.LN "logic rx_cmp_dm_intr.attr.LN" +Toggle 0to1 rx_cmp_dm_intr.attr.LN "logic rx_cmp_dm_intr.attr.LN" +Toggle 1to0 rx_cmp_dm_intr.attr.TD "logic rx_cmp_dm_intr.attr.TD" +Toggle 0to1 rx_cmp_dm_intr.attr.TD "logic rx_cmp_dm_intr.attr.TD" +Toggle 1to0 rx_cmp_dm_intr.attr.TH "logic rx_cmp_dm_intr.attr.TH" +Toggle 0to1 rx_cmp_dm_intr.attr.TH "logic rx_cmp_dm_intr.attr.TH" +Toggle 1to0 rx_cmp_pu_hdr.attr.rsvd1 "logic rx_cmp_pu_hdr.attr.rsvd1" +Toggle 0to1 rx_cmp_pu_hdr.attr.rsvd1 "logic rx_cmp_pu_hdr.attr.rsvd1" +ANNOTATION: " Rsvdz field " +Toggle rx_cmp_pu_hdr.attr.rsvd2 "logic rx_cmp_pu_hdr.attr.rsvd2[1:0]" +ANNOTATION: " Rsvdz field " +Toggle rx_cmp_dm_hdr.rsvd8 "logic rx_cmp_dm_hdr.rsvd8[12:0]" +Toggle 1to0 rx_cmp_dm_hdr.rsvd9 "logic rx_cmp_dm_hdr.rsvd9" +Toggle 0to1 rx_cmp_dm_hdr.rsvd9 "logic rx_cmp_dm_hdr.rsvd9" +Toggle 1to0 rx_cmp_dm_hdr.rsvd10 "logic rx_cmp_dm_hdr.rsvd10" +Toggle 0to1 rx_cmp_dm_hdr.rsvd10 "logic rx_cmp_dm_hdr.rsvd10" +Toggle 1to0 rx_cmp_dm_intr.attr.rsvd1 "logic rx_cmp_dm_intr.attr.rsvd1" +Toggle 0to1 rx_cmp_dm_intr.attr.rsvd1 "logic rx_cmp_dm_intr.attr.rsvd1" +ANNOTATION: " Rsvdz field " +Toggle rx_cmp_dm_intr.attr.rsvd2 "logic rx_cmp_dm_intr.attr.rsvd2[1:0]" +ANNOTATION: " Rsvdz field " +Toggle rx_cmp_pu_hdr.rsvd1 "logic rx_cmp_pu_hdr.rsvd1[6:0]" +ANNOTATION: " Rsvdz field " +Toggle rx_cmp_pu_hdr.rsvd2 "logic rx_cmp_pu_hdr.rsvd2[3:0]" +ANNOTATION: " Rsvdz field " +Toggle rx_cmp_pu_hdr.rsvd3 "logic rx_cmp_pu_hdr.rsvd3[1:0]" +ANNOTATION: " Rsvdz field " +Toggle rx_cmp_pu_hdr.rsvd4 "logic rx_cmp_pu_hdr.rsvd4[31:0]" +Toggle 1to0 rx_cmp_pu_hdr.rsvd5 "logic rx_cmp_pu_hdr.rsvd5" +Toggle 0to1 rx_cmp_pu_hdr.rsvd5 "logic rx_cmp_pu_hdr.rsvd5" +Toggle 1to0 rx_cmp_dm_hdr.mm_mode "logic rx_cmp_dm_hdr.mm_mode" +Toggle 0to1 rx_cmp_dm_hdr.mm_mode "logic rx_cmp_dm_hdr.mm_mode" +ANNOTATION: " Rsvdz field " +Toggle rx_cmp_dm_hdr.pref "logic rx_cmp_dm_hdr.pref[23:0]" +Toggle 1to0 rx_cmp_dm_hdr.pref_present "logic rx_cmp_dm_hdr.pref_present" +Toggle 0to1 rx_cmp_dm_hdr.pref_present "logic rx_cmp_dm_hdr.pref_present" +ANNOTATION: " Rsvdz field " +Toggle rx_cmp_dm_hdr.pref_type "logic rx_cmp_dm_hdr.pref_type[4:0]" +ANNOTATION: " Rsvdz field " +Toggle rx_cmp_dm_hdr.rsvd1 "logic rx_cmp_dm_hdr.rsvd1[6:0]" +ANNOTATION: " Rsvdz field " +Toggle rx_cmp_dm_hdr.rsvd2 "logic rx_cmp_dm_hdr.rsvd2[3:0]" +ANNOTATION: " Rsvdz field " +Toggle rx_cmp_dm_hdr.rsvd3 "logic rx_cmp_dm_hdr.rsvd3[1:0]" +Toggle 1to0 rx_cmp_dm_hdr.rsvd4 "logic rx_cmp_dm_hdr.rsvd4" +Toggle 0to1 rx_cmp_dm_hdr.rsvd4 "logic rx_cmp_dm_hdr.rsvd4" +ANNOTATION: " Rsvdz field " +Toggle rx_cmp_dm_hdr.rsvd5 "logic rx_cmp_dm_hdr.rsvd5[15:0]" +ANNOTATION: " Rsvdz field " +Toggle rx_cmp_dm_hdr.rsvd6 "logic rx_cmp_dm_hdr.rsvd6[7:0]" +ANNOTATION: " Rsvdz field " +Toggle rx_cmp_dm_hdr.rsvd7 "logic rx_cmp_dm_hdr.rsvd7[15:0]" +ANNOTATION: " value will be constant " +Toggle rx_cmp_dm_hdr.TC "logic rx_cmp_dm_hdr.TC[2:0]" +ANNOTATION: " value will be constant " +Toggle rx_cmp_dm_hdr.attr.AT "logic rx_cmp_dm_hdr.attr.AT[1:0]" +Toggle 1to0 rx_cmp_dm_hdr.attr.EP "logic rx_cmp_dm_hdr.attr.EP" +Toggle 0to1 rx_cmp_dm_hdr.attr.EP "logic rx_cmp_dm_hdr.attr.EP" +Toggle 1to0 rx_cmp_dm_hdr.attr.LN "logic rx_cmp_dm_hdr.attr.LN" +Toggle 0to1 rx_cmp_dm_hdr.attr.LN "logic rx_cmp_dm_hdr.attr.LN" +Toggle 1to0 rx_cmp_dm_hdr.attr.TD "logic rx_cmp_dm_hdr.attr.TD" +Toggle 0to1 rx_cmp_dm_hdr.attr.TD "logic rx_cmp_dm_hdr.attr.TD" +Toggle 1to0 rx_cmp_dm_hdr.attr.TH "logic rx_cmp_dm_hdr.attr.TH" +Toggle 0to1 rx_cmp_dm_hdr.attr.TH "logic rx_cmp_dm_hdr.attr.TH" +Toggle 1to0 rx_cmp_dm_hdr.attr.rsvd1 "logic rx_cmp_dm_hdr.attr.rsvd1" +Toggle 0to1 rx_cmp_dm_hdr.attr.rsvd1 "logic rx_cmp_dm_hdr.attr.rsvd1" +ANNOTATION: " value will be constant " +Toggle rx_cmp_dm_hdr.attr.rsvd2 "logic rx_cmp_dm_hdr.attr.rsvd2[1:0]" +ANNOTATION: " value will be constant " +Toggle rx_cmp_dm_hdr.cpl_status "logic rx_cmp_dm_hdr.cpl_status[2:0]" +ANNOTATION: " value will be constant " +Toggle rx_cmp_dm_hdr.fmt_type "logic rx_cmp_dm_hdr.fmt_type[7:0]" +Toggle 1to0 rx_cmp_dm_hdr.FC "logic rx_cmp_dm_hdr.FC" +Toggle 0to1 rx_cmp_dm_hdr.FC "logic rx_cmp_dm_hdr.FC" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.local_commit.commit_in +Assert assert_tvalid_tready_handshake "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.local_commit.commit_skid.r.axis_pl[0] +Assert assert_tvalid_tready_handshake "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.local_commit.commit_skid.r.axis_pl[1] +Assert assert_tvalid_tready_handshake "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.local_commit.commit_in +Assert assert_tvalid_tready_handshake "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.local_commit.commit_skid.r.axis_pl[0] +Assert assert_tvalid_tready_handshake "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.local_commit.commit_skid.r.axis_pl[1] +Assert assert_tvalid_tready_handshake "assertion" diff --git a/verification/coverage/msix_exclusions.el b/verification/coverage/msix_exclusions.el new file mode 100644 index 0000000..829844b --- /dev/null +++ b/verification/coverage/msix_exclusions.el @@ -0,0 +1,2588 @@ +//================================================== +// This file contains the Excluded objects +// Generated By User: srudrarx +// Format Version: 2 +// Date: Thu May 12 00:02:25 2022 +// ExclMode: default +//================================================== +CHECKSUM: "3630569307" +INSTANCE:tb_top.DUT.pcie_wrapper.msix_top.msix_wrapper_inst.msix_fme_bridge_inst.msix_scfifo.scfifo_inst.dev +CHECKSUM: "3630569307" +INSTANCE:tb_top.DUT.pcie_wrapper.msix_top.msix_user_irq_inst.user_scfifo.scfifo_inst.dev +CHECKSUM: "2100166288" +INSTANCE:tb_top.DUT.pcie_wrapper.msix_top.msix_wrapper_inst.msix_fme_bridge_inst.msix_scfifo.scfifo_inst +CHECKSUM: "2100166288" +INSTANCE:tb_top.DUT.pcie_wrapper.msix_top.msix_user_irq_inst.user_scfifo.scfifo_inst +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.pcie_wrapper.msix_top.sync.resync_chains[0].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.pcie_wrapper.msix_top.sync.resync_chains[1].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.pcie_wrapper.msix_top.sync.resync_chains[2].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.pcie_wrapper.msix_top.sync.resync_chains[3].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.pcie_wrapper.msix_top.sync.resync_chains[4].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.pcie_wrapper.msix_top.sync.resync_chains[5].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.pcie_wrapper.msix_top.sync.resync_chains[6].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.pcie_wrapper.msix_top.sync.resync_chains[7].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.pcie_wrapper.msix_top.sync.resync_chains[8].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.pcie_wrapper.msix_top.sync.resync_chains[9].genblk1.synchronizer +CHECKSUM: "2725671737" +INSTANCE:tb_top.DUT.pcie_wrapper.msix_top.sync +CHECKSUM: "3852207126 1064450560" +INSTANCE: tb_top.DUT.pcie_wrapper.msix_top.msix_wrapper_inst.msix_fme_bridge_inst +Toggle 0to1 wfull "net wfull" +Toggle 1to0 wfull "net wfull" +CHECKSUM: "3782056757 2625294833" +INSTANCE: tb_top.DUT.pcie_wrapper.msix_top +Toggle 1to0 pcie_p2c_sideband.flr_rcvd_pf_num [0] "logic pcie_p2c_sideband.flr_rcvd_pf_num[0:0]" +Toggle 0to1 pcie_p2c_sideband.flr_rcvd_pf_num [0] "logic pcie_p2c_sideband.flr_rcvd_pf_num[0:0]" +Toggle 1to0 i_pcie_p2c_sideband.flr_rcvd_pf_num [0] "logic i_pcie_p2c_sideband.flr_rcvd_pf_num[0:0]" +Toggle 0to1 i_pcie_p2c_sideband.flr_rcvd_pf_num [0] "logic i_pcie_p2c_sideband.flr_rcvd_pf_num[0:0]" +Toggle addr_64b "logic addr_64b[16:0]" +Toggle o_pcie_c2p_sideband.flr_completed_pf "logic o_pcie_c2p_sideband.flr_completed_pf[1:0]" +Toggle 0to1 port_irq_in "logic port_irq_in" +Toggle 1to0 port_irq_in "logic port_irq_in" +Toggle 0to1 pf_user_irq "logic pf_user_irq" +Toggle 1to0 pf_user_irq "logic pf_user_irq" +Toggle 0to1 pf_irq_rsp.tvalid "logic pf_irq_rsp.tvalid" +Toggle 1to0 pf_irq_rsp.tvalid "logic pf_irq_rsp.tvalid" +Toggle pf_irq_rsp.tdata.rid "logic pf_irq_rsp.tdata.rid[15:0]" +Toggle pf_irq_rsp.tdata.irq_id "logic pf_irq_rsp.tdata.irq_id[7:0]" +Toggle 0to1 pcie_p2c_sideband.pcie_linkup "logic pcie_p2c_sideband.pcie_linkup" +Toggle 1to0 pcie_p2c_sideband.pcie_linkup "logic pcie_p2c_sideband.pcie_linkup" +Toggle pcie_p2c_sideband.pcie_chk_rx_err_code "logic pcie_p2c_sideband.pcie_chk_rx_err_code[31:0]" +Toggle pcie_p2c_sideband.flr_rcvd_vf_num "logic pcie_p2c_sideband.flr_rcvd_vf_num[1:0]" +Toggle 0to1 pcie_p2c_sideband.flr_rcvd_vf "logic pcie_p2c_sideband.flr_rcvd_vf" +Toggle 1to0 pcie_p2c_sideband.flr_rcvd_vf "logic pcie_p2c_sideband.flr_rcvd_vf" +Toggle pcie_p2c_sideband.flr_active_pf "logic pcie_p2c_sideband.flr_active_pf[1:0]" +Toggle 0to1 pcie_p2c_sideband.cfg_ctl.vf0_msix_mask "logic pcie_p2c_sideband.cfg_ctl.vf0_msix_mask" +Toggle 1to0 pcie_p2c_sideband.cfg_ctl.vf0_msix_mask "logic pcie_p2c_sideband.cfg_ctl.vf0_msix_mask" +Toggle 0to1 pcie_p2c_sideband.cfg_ctl.msix_pf_mask_en "logic pcie_p2c_sideband.cfg_ctl.msix_pf_mask_en" +Toggle 1to0 pcie_p2c_sideband.cfg_ctl.msix_pf_mask_en "logic pcie_p2c_sideband.cfg_ctl.msix_pf_mask_en" +Toggle 0to1 pcie_p2c_sideband.cfg_ctl.msix_enable "logic pcie_p2c_sideband.cfg_ctl.msix_enable" +Toggle 1to0 pcie_p2c_sideband.cfg_ctl.msix_enable "logic pcie_p2c_sideband.cfg_ctl.msix_enable" +Toggle pcie_p2c_sideband.cfg_ctl.max_read_req_size "logic pcie_p2c_sideband.cfg_ctl.max_read_req_size[2:0]" +Toggle pcie_p2c_sideband.cfg_ctl.max_payload_size "logic pcie_p2c_sideband.cfg_ctl.max_payload_size[2:0]" +Toggle 0to1 pcie_p2c_sideband.cfg_ctl.extended_tag_enable "logic pcie_p2c_sideband.cfg_ctl.extended_tag_enable" +Toggle 1to0 pcie_p2c_sideband.cfg_ctl.extended_tag_enable "logic pcie_p2c_sideband.cfg_ctl.extended_tag_enable" +Toggle o_pcie_c2p_sideband.flr_completed_vf_num "logic o_pcie_c2p_sideband.flr_completed_vf_num[1:0]" +Toggle 0to1 o_pcie_c2p_sideband.flr_completed_vf "logic o_pcie_c2p_sideband.flr_completed_vf" +Toggle 1to0 o_pcie_c2p_sideband.flr_completed_vf "logic o_pcie_c2p_sideband.flr_completed_vf" +Toggle o_pcie_c2p_sideband.flr_completed_pf_num "logic o_pcie_c2p_sideband.flr_completed_pf_num[0:0]" +Toggle 0to1 i_pcie_p2c_sideband.cfg_ctl.extended_tag_enable "logic i_pcie_p2c_sideband.cfg_ctl.extended_tag_enable" +Toggle 1to0 i_pcie_p2c_sideband.cfg_ctl.extended_tag_enable "logic i_pcie_p2c_sideband.cfg_ctl.extended_tag_enable" +Toggle i_pcie_p2c_sideband.pcie_chk_rx_err_code "logic i_pcie_p2c_sideband.pcie_chk_rx_err_code[31:0]" +Toggle i_pcie_p2c_sideband.flr_rcvd_vf_num "logic i_pcie_p2c_sideband.flr_rcvd_vf_num[1:0]" +Toggle 0to1 i_pcie_p2c_sideband.flr_rcvd_vf "logic i_pcie_p2c_sideband.flr_rcvd_vf" +Toggle 1to0 i_pcie_p2c_sideband.flr_rcvd_vf "logic i_pcie_p2c_sideband.flr_rcvd_vf" +Toggle i_pcie_p2c_sideband.flr_active_pf "logic i_pcie_p2c_sideband.flr_active_pf[1:0]" +Toggle 0to1 i_pcie_p2c_sideband.cfg_ctl.vf0_msix_mask "logic i_pcie_p2c_sideband.cfg_ctl.vf0_msix_mask" +Toggle 1to0 i_pcie_p2c_sideband.cfg_ctl.vf0_msix_mask "logic i_pcie_p2c_sideband.cfg_ctl.vf0_msix_mask" +Toggle 0to1 i_pcie_p2c_sideband.cfg_ctl.msix_pf_mask_en "logic i_pcie_p2c_sideband.cfg_ctl.msix_pf_mask_en" +Toggle 1to0 i_pcie_p2c_sideband.cfg_ctl.msix_pf_mask_en "logic i_pcie_p2c_sideband.cfg_ctl.msix_pf_mask_en" +Toggle 0to1 i_pcie_p2c_sideband.cfg_ctl.msix_enable "logic i_pcie_p2c_sideband.cfg_ctl.msix_enable" +Toggle 1to0 i_pcie_p2c_sideband.cfg_ctl.msix_enable "logic i_pcie_p2c_sideband.cfg_ctl.msix_enable" +Toggle i_pcie_p2c_sideband.cfg_ctl.max_read_req_size "logic i_pcie_p2c_sideband.cfg_ctl.max_read_req_size[2:0]" +Toggle i_pcie_p2c_sideband.cfg_ctl.max_payload_size "logic i_pcie_p2c_sideband.cfg_ctl.max_payload_size[2:0]" +Toggle 0to1 cr2out_msix_vpba [63] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [63] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [4] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [4] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [5] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [5] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [6] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [6] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [7] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [7] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [8] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [8] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [9] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [9] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [10] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [10] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [11] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [11] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [12] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [12] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [13] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [13] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [14] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [14] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [15] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [15] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [16] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [16] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [17] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [17] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [18] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [18] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [19] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [19] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [20] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [20] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [21] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [21] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [22] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [22] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [23] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [23] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [24] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [24] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [25] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [25] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [26] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [26] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [27] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [27] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [28] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [28] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [29] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [29] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [30] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [30] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [31] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [31] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [32] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [32] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [33] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [33] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [34] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [34] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [35] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [35] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [36] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [36] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [37] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [37] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [38] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [38] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [39] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [39] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [40] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [40] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [41] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [41] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [42] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [42] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [43] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [43] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [44] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [44] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [45] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [45] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [46] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [46] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [47] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [47] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [48] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [48] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [49] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [49] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [50] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [50] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [51] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [51] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [52] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [52] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [53] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [53] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [54] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [54] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [55] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [55] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [56] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [56] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [57] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [57] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [58] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [58] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [59] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [59] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [60] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [60] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [61] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [61] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [62] "logic cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [62] "logic cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_pba [63] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [63] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [0] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [0] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [1] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [1] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [2] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [2] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [3] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [3] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [4] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [4] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [5] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [5] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [7] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [7] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [8] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [8] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [9] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [9] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [10] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [10] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [11] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [11] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [12] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [12] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [13] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [13] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [14] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [14] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [15] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [15] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [16] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [16] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [17] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [17] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [18] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [18] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [19] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [19] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [20] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [20] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [21] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [21] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [22] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [22] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [23] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [23] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [24] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [24] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [25] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [25] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [26] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [26] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [27] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [27] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [28] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [28] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [29] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [29] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [30] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [30] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [31] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [31] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [32] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [32] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [33] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [33] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [34] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [34] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [35] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [35] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [36] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [36] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [37] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [37] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [38] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [38] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [39] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [39] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [40] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [40] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [41] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [41] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [42] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [42] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [43] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [43] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [44] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [44] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [45] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [45] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [46] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [46] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [47] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [47] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [48] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [48] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [49] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [49] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [50] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [50] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [51] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [51] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [52] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [52] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [53] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [53] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [54] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [54] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [55] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [55] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [56] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [56] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [57] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [57] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [58] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [58] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [59] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [59] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [60] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [60] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [61] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [61] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [62] "logic cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [62] "logic cr2out_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [5] "logic inp2cr_msix_pba[6:0]" +Toggle 1to0 inp2cr_msix_pba [5] "logic inp2cr_msix_pba[6:0]" +Toggle 0to1 inp2cr_msix_pba [0] "logic inp2cr_msix_pba[6:0]" +Toggle 1to0 inp2cr_msix_pba [0] "logic inp2cr_msix_pba[6:0]" +Toggle 0to1 inp2cr_msix_pba [1] "logic inp2cr_msix_pba[6:0]" +Toggle 1to0 inp2cr_msix_pba [1] "logic inp2cr_msix_pba[6:0]" +Toggle 0to1 inp2cr_msix_pba [2] "logic inp2cr_msix_pba[6:0]" +Toggle 1to0 inp2cr_msix_pba [2] "logic inp2cr_msix_pba[6:0]" +Toggle 0to1 inp2cr_msix_pba [3] "logic inp2cr_msix_pba[6:0]" +Toggle 1to0 inp2cr_msix_pba [3] "logic inp2cr_msix_pba[6:0]" +Toggle 0to1 inp2cr_msix_pba [4] "logic inp2cr_msix_pba[6:0]" +Toggle 1to0 inp2cr_msix_pba [4] "logic inp2cr_msix_pba[6:0]" +Toggle 0to1 o_msix_addr [63] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [63] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [32] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [32] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [33] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [33] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [34] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [34] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [35] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [35] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [36] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [36] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [37] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [37] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [38] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [38] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [39] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [39] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [40] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [40] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [41] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [41] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [42] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [42] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [43] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [43] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [44] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [44] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [45] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [45] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [46] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [46] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [47] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [47] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [48] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [48] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [49] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [49] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [50] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [50] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [51] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [51] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [52] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [52] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [53] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [53] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [54] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [54] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [55] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [55] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [56] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [56] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [57] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [57] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [58] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [58] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [59] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [59] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [60] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [60] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [61] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [61] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [62] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [62] "logic o_msix_addr[63:0]" +Toggle a2c_msix_en_pf "logic a2c_msix_en_pf[1:0]" +Toggle a2c_msix_fn_mask_pf "logic a2c_msix_fn_mask_pf[1:0]" +Toggle 0to1 cr2out_msix_vaddr3 [63] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [63] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [31] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [31] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [32] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [32] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [33] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [33] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [34] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [34] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [35] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [35] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [36] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [36] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [37] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [37] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [38] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [38] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [39] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [39] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [40] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [40] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [41] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [41] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [42] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [42] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [43] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [43] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [44] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [44] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [45] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [45] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [46] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [46] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [47] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [47] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [48] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [48] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [49] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [49] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [50] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [50] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [51] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [51] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [52] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [52] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [53] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [53] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [54] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [54] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [55] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [55] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [56] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [56] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [57] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [57] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [58] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [58] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [59] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [59] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [60] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [60] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [61] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [61] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [62] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [62] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [63] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [63] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [33] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [33] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [34] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [34] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [35] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [35] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [36] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [36] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [37] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [37] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [38] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [38] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [39] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [39] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [40] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [40] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [41] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [41] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [42] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [42] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [43] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [43] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [44] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [44] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [45] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [45] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [46] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [46] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [47] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [47] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [48] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [48] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [49] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [49] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [50] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [50] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [51] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [51] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [52] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [52] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [53] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [53] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [54] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [54] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [55] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [55] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [56] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [56] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [57] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [57] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [58] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [58] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [59] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [59] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [60] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [60] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [61] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [61] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [62] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [62] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [63] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [63] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [32] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [32] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [33] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [33] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [34] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [34] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [35] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [35] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [36] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [36] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [37] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [37] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [38] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [38] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [39] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [39] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [40] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [40] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [41] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [41] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [42] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [42] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [43] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [43] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [44] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [44] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [45] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [45] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [46] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [46] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [47] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [47] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [48] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [48] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [49] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [49] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [50] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [50] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [51] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [51] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [52] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [52] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [53] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [53] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [54] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [54] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [55] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [55] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [56] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [56] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [57] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [57] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [58] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [58] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [59] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [59] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [60] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [60] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [61] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [61] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [62] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [62] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [63] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [63] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [33] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [33] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [34] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [34] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [35] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [35] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [36] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [36] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [37] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [37] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [38] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [38] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [39] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [39] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [40] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [40] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [41] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [41] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [42] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [42] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [43] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [43] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [44] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [44] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [45] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [45] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [46] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [46] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [47] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [47] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [48] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [48] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [49] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [49] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [50] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [50] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [51] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [51] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [52] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [52] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [53] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [53] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [54] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [54] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [55] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [55] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [56] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [56] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [57] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [57] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [58] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [58] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [59] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [59] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [60] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [60] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [61] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [61] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [62] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [62] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [63] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [63] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [32] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [32] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [33] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [33] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [34] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [34] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [35] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [35] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [36] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [36] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [37] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [37] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [38] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [38] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [39] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [39] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [40] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [40] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [41] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [41] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [42] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [42] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [43] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [43] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [44] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [44] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [45] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [45] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [46] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [46] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [47] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [47] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [48] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [48] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [49] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [49] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [50] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [50] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [51] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [51] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [52] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [52] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [53] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [53] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [54] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [54] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [55] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [55] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [56] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [56] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [57] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [57] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [58] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [58] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [59] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [59] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [60] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [60] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [61] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [61] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [62] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [62] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [63] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [63] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [32] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [32] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [33] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [33] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [34] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [34] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [35] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [35] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [36] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [36] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [37] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [37] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [38] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [38] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [39] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [39] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [40] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [40] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [41] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [41] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [42] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [42] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [43] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [43] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [44] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [44] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [45] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [45] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [46] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [46] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [47] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [47] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [48] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [48] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [49] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [49] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [50] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [50] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [51] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [51] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [52] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [52] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [53] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [53] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [54] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [54] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [55] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [55] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [56] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [56] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [57] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [57] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [58] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [58] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [59] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [59] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [60] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [60] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [61] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [61] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [62] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [62] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 user_irq_valid "logic user_irq_valid" +Toggle 1to0 user_irq_valid "logic user_irq_valid" +Toggle vf_irq_rsp.tdata.rid "logic vf_irq_rsp.tdata.rid[15:0]" +Toggle 0to1 inp2cr_msix_vpba [6] "logic inp2cr_msix_vpba[6:0]" +Toggle 1to0 inp2cr_msix_vpba [6] "logic inp2cr_msix_vpba[6:0]" +Toggle 0to1 inp2cr_msix_vpba [4] "logic inp2cr_msix_vpba[6:0]" +Toggle 1to0 inp2cr_msix_vpba [4] "logic inp2cr_msix_vpba[6:0]" +Toggle 0to1 inp2cr_msix_vpba [5] "logic inp2cr_msix_vpba[6:0]" +Toggle 1to0 inp2cr_msix_vpba [5] "logic inp2cr_msix_vpba[6:0]" +Toggle 0to1 pf_mask_vector [5] "logic pf_mask_vector[6:0]" +Toggle 1to0 pf_mask_vector [5] "logic pf_mask_vector[6:0]" +Toggle 0to1 pf_mask_vector [0] "logic pf_mask_vector[6:0]" +Toggle 1to0 pf_mask_vector [0] "logic pf_mask_vector[6:0]" +Toggle 0to1 pf_mask_vector [1] "logic pf_mask_vector[6:0]" +Toggle 1to0 pf_mask_vector [1] "logic pf_mask_vector[6:0]" +Toggle 0to1 pf_mask_vector [2] "logic pf_mask_vector[6:0]" +Toggle 1to0 pf_mask_vector [2] "logic pf_mask_vector[6:0]" +Toggle 0to1 pf_mask_vector [3] "logic pf_mask_vector[6:0]" +Toggle 1to0 pf_mask_vector [3] "logic pf_mask_vector[6:0]" +Toggle 0to1 pf_mask_vector [4] "logic pf_mask_vector[6:0]" +Toggle 1to0 pf_mask_vector [4] "logic pf_mask_vector[6:0]" +Toggle 0to1 vf_irq_rsp.tdata.irq_id [7] "logic vf_irq_rsp.tdata.irq_id[7:0]" +Toggle 1to0 vf_irq_rsp.tdata.irq_id [7] "logic vf_irq_rsp.tdata.irq_id[7:0]" +Toggle 0to1 vf_irq_rsp.tdata.irq_id [4] "logic vf_irq_rsp.tdata.irq_id[7:0]" +Toggle 1to0 vf_irq_rsp.tdata.irq_id [4] "logic vf_irq_rsp.tdata.irq_id[7:0]" +Toggle 0to1 vf_irq_rsp.tdata.irq_id [5] "logic vf_irq_rsp.tdata.irq_id[7:0]" +Toggle 1to0 vf_irq_rsp.tdata.irq_id [5] "logic vf_irq_rsp.tdata.irq_id[7:0]" +Toggle 0to1 vf_irq_rsp.tdata.irq_id [6] "logic vf_irq_rsp.tdata.irq_id[7:0]" +Toggle 1to0 vf_irq_rsp.tdata.irq_id [6] "logic vf_irq_rsp.tdata.irq_id[7:0]" +Toggle 0to1 i_pcie_p2c_sideband.pcie_linkup "logic i_pcie_p2c_sideband.pcie_linkup" +Toggle 1to0 i_pcie_p2c_sideband.pcie_linkup "logic i_pcie_p2c_sideband.pcie_linkup" +Toggle 0to1 afu_softreset "logic afu_softreset" +Toggle 1to0 afu_softreset "logic afu_softreset" +Toggle 0to1 cr2out_port_error_clear "logic cr2out_port_error_clear" +Toggle 1to0 cr2out_port_error_clear "logic cr2out_port_error_clear" +Toggle 0to1 i_intr_id [3] "logic i_intr_id[3:0]" +Toggle 1to0 i_intr_id [3] "logic i_intr_id[3:0]" +Toggle 0to1 i_intr_id [0] "logic i_intr_id[3:0]" +Toggle 1to0 i_intr_id [0] "logic i_intr_id[3:0]" +Toggle 0to1 msix_mask "logic msix_mask" +Toggle 1to0 msix_mask "logic msix_mask" +Toggle 0to1 o_msix_addr [3] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [3] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [7] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [7] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [4] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [5] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [0] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [0] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [1] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [1] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [2] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [2] "logic o_msix_addr[63:0]" +Toggle 0to1 vf_irq_rsp.tdata.irq_id [3] "logic vf_irq_rsp.tdata.irq_id[7:0]" +Toggle 1to0 vf_irq_rsp.tdata.irq_id [3] "logic vf_irq_rsp.tdata.irq_id[7:0]" +Toggle 0to1 vf_irq_rsp.tdata.irq_id [2] "logic vf_irq_rsp.tdata.irq_id[7:0]" +Toggle 1to0 vf_irq_rsp.tdata.irq_id [2] "logic vf_irq_rsp.tdata.irq_id[7:0]" +Toggle 0to1 vf_mask_vector [4] "logic vf_mask_vector[4:0]" +Toggle 1to0 vf_mask_vector [4] "logic vf_mask_vector[4:0]" +Toggle 0to1 vf_msix_mask "logic vf_msix_mask" +Toggle 1to0 vf_msix_mask "logic vf_msix_mask" +Toggle 0to1 o_msix_addr [5] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [4] "logic o_msix_addr[63:0]" +Toggle 0to1 o_msix_addr [6] "logic o_msix_addr[63:0]" +Toggle 1to0 o_msix_addr [6] "logic o_msix_addr[63:0]" +CHECKSUM: "3119255466 1959348882" +INSTANCE: tb_top.DUT.pcie_wrapper.msix_top.fme_msix_table +Toggle 0to1 o_intr_id [3] "logic o_intr_id[3:0]" +Toggle 1to0 o_intr_id [3] "logic o_intr_id[3:0]" +Toggle 0to1 o_intr_id [0] "logic o_intr_id[3:0]" +Toggle 1to0 o_intr_id [0] "logic o_intr_id[3:0]" +Toggle 0to1 cr2out_msix_vaddr3 [63] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [63] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [31] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [31] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [32] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [32] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [33] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [33] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [34] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [34] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [35] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [35] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [36] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [36] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [37] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [37] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [38] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [38] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [39] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [39] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [40] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [40] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [41] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [41] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [42] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [42] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [43] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [43] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [44] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [44] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [45] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [45] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [46] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [46] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [47] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [47] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [48] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [48] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [49] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [49] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [50] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [50] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [51] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [51] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [52] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [52] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [53] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [53] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [54] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [54] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [55] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [55] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [56] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [56] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [57] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [57] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [58] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [58] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [59] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [59] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [60] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [60] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [61] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [61] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vaddr3 [62] "logic cr2out_msix_vaddr3[63:0]" +Toggle 1to0 cr2out_msix_vaddr3 [62] "logic cr2out_msix_vaddr3[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [63] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [63] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [33] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [33] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [34] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [34] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [35] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [35] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [36] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [36] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [37] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [37] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [38] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [38] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [39] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [39] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [40] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [40] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [41] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [41] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [42] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [42] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [43] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [43] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [44] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [44] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [45] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [45] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [46] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [46] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [47] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [47] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [48] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [48] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [49] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [49] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [50] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [50] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [51] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [51] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [52] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [52] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [53] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [53] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [54] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [54] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [55] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [55] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [56] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [56] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [57] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [57] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [58] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [58] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [59] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [59] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [60] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [60] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [61] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [61] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat0 [62] "logic cr2out_msix_vctldat0[63:0]" +Toggle 1to0 cr2out_msix_vctldat0 [62] "logic cr2out_msix_vctldat0[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [63] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [63] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [33] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [33] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [34] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [34] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [35] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [35] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [36] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [36] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [37] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [37] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [38] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [38] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [39] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [39] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [40] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [40] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [41] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [41] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [42] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [42] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [43] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [43] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [44] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [44] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [45] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [45] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [46] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [46] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [47] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [47] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [48] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [48] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [49] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [49] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [50] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [50] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [51] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [51] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [52] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [52] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [53] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [53] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [54] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [54] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [55] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [55] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [56] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [56] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [57] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [57] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [58] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [58] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [59] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [59] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [60] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [60] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [61] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [61] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vctldat2 [62] "logic cr2out_msix_vctldat2[63:0]" +Toggle 1to0 cr2out_msix_vctldat2 [62] "logic cr2out_msix_vctldat2[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [63] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [63] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [32] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [32] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [33] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [33] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [34] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [34] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [35] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [35] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [36] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [36] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [37] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [37] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [38] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [38] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [39] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [39] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [40] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [40] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [41] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [41] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [42] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [42] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [43] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [43] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [44] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [44] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [45] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [45] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [46] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [46] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [47] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [47] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [48] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [48] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [49] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [49] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [50] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [50] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [51] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [51] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [52] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [52] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [53] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [53] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [54] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [54] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [55] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [55] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [56] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [56] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [57] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [57] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [58] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [58] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [59] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [59] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [60] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [60] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [61] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [61] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vaddr0 [62] "logic cr2out_msix_vaddr0[63:0]" +Toggle 1to0 cr2out_msix_vaddr0 [62] "logic cr2out_msix_vaddr0[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [63] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [63] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [33] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [33] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [34] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [34] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [35] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [35] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [36] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [36] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [37] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [37] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [38] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [38] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [39] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [39] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [40] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [40] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [41] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [41] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [42] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [42] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [43] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [43] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [44] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [44] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [45] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [45] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [46] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [46] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [47] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [47] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [48] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [48] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [49] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [49] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [50] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [50] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [51] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [51] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [52] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [52] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [53] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [53] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [54] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [54] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [55] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [55] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [56] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [56] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [57] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [57] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [58] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [58] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [59] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [59] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [60] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [60] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [61] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [61] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vctldat1 [62] "logic cr2out_msix_vctldat1[63:0]" +Toggle 1to0 cr2out_msix_vctldat1 [62] "logic cr2out_msix_vctldat1[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [63] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [63] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [32] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [32] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [33] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [33] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [34] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [34] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [35] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [35] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [36] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [36] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [37] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [37] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [38] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [38] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [39] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [39] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [40] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [40] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [41] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [41] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [42] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [42] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [43] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [43] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [44] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [44] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [45] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [45] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [46] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [46] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [47] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [47] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [48] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [48] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [49] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [49] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [50] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [50] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [51] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [51] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [52] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [52] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [53] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [53] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [54] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [54] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [55] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [55] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [56] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [56] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [57] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [57] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [58] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [58] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [59] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [59] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [60] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [60] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [61] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [61] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr2 [62] "logic cr2out_msix_vaddr2[63:0]" +Toggle 1to0 cr2out_msix_vaddr2 [62] "logic cr2out_msix_vaddr2[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [63] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [63] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [32] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [32] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [33] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [33] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [34] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [34] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [35] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [35] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [36] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [36] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [37] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [37] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [38] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [38] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [39] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [39] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [40] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [40] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [41] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [41] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [42] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [42] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [43] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [43] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [44] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [44] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [45] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [45] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [46] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [46] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [47] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [47] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [48] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [48] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [49] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [49] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [50] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [50] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [51] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [51] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [52] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [52] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [53] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [53] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [54] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [54] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [55] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [55] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [56] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [56] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [57] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [57] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [58] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [58] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [59] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [59] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [60] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [60] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [61] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [61] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vaddr1 [62] "logic cr2out_msix_vaddr1[63:0]" +Toggle 1to0 cr2out_msix_vaddr1 [62] "logic cr2out_msix_vaddr1[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [63] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [63] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [33] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [33] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [34] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [34] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [35] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [35] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [36] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [36] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [37] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [37] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [38] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [38] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [39] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [39] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [40] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [40] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [41] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [41] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [42] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [42] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [43] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [43] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [44] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [44] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [45] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [45] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [46] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [46] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [47] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [47] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [48] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [48] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [49] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [49] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [50] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [50] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [51] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [51] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [52] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [52] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [53] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [53] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [54] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [54] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [55] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [55] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [56] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [56] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [57] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [57] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [58] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [58] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [59] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [59] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [60] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [60] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [61] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [61] "logic cr2out_msix_vctldat3[63:0]" +Toggle 0to1 cr2out_msix_vctldat3 [62] "logic cr2out_msix_vctldat3[63:0]" +Toggle 1to0 cr2out_msix_vctldat3 [62] "logic cr2out_msix_vctldat3[63:0]" +CHECKSUM: "124270709 1832595925" +INSTANCE: tb_top.DUT.pcie_wrapper.msix_top.msix_user_irq_inst.user_scfifo +Toggle 1to0 w_ready "logic w_ready" +Toggle 0to1 w_ready "logic w_ready" +Toggle 0to1 almost_full "logic almost_full" +Toggle 1to0 almost_full "logic almost_full" +Toggle 0to1 w_full "logic w_full" +Toggle 1to0 w_full "logic w_full" +Toggle 0to1 sclr "logic sclr" +Toggle 1to0 sclr "logic sclr" +CHECKSUM: "124270709 3982754594" +INSTANCE: tb_top.DUT.pcie_wrapper.msix_top.msix_wrapper_inst.msix_fme_bridge_inst.msix_scfifo +Toggle 0to1 almost_full "logic almost_full" +Toggle 1to0 almost_full "logic almost_full" +Toggle 0to1 w_full "logic w_full" +Toggle 1to0 w_full "logic w_full" +Toggle 0to1 sclr "logic sclr" +Toggle 1to0 sclr "logic sclr" +CHECKSUM: "3782056757 3756458786" +INSTANCE: tb_top.DUT.pcie_wrapper.msix_top +ANNOTATION: " user interrupts are supported for vf_user_irq and not pf_user_irq " +Branch 3 "1844070375" "(((((o_intr_id == 3'b0) || (o_intr_id == 3'b1)) || (o_intr_id == 3'h2)) || (o_intr_id == 3'h3)) && o_intr_valid)" (0) "(((((o_intr_id == 3'b0) || (o_intr_id == 3'b1)) || (o_intr_id == 3'h2)) || (o_intr_id == 3'h3)) && o_intr_valid) 1" +Branch 14 "1501460013" "(~rst_n)" (3) "(~rst_n) 0,0,-" +Branch 14 "1501460013" "(~rst_n)" (1) "(~rst_n) 0,1,1" +Branch 15 "3184281831" "(~rst_n)" (3) "(~rst_n) 0,0,-" +CHECKSUM: "127665118 2299330444" +INSTANCE: tb_top.DUT.pcie_wrapper.msix_top.msix_wrapper_inst.msix_pba +ANNOTATION: " only 6th bit of PBA is used so rest all branches are invalid " +Branch 0 "2872854103" "pf_monitor_wire" (1) "pf_monitor_wire 7'bzz1zzzz " +ANNOTATION: " only 6th bit of PBA is used so rest all branches are invalid " +Branch 0 "2872854103" "pf_monitor_wire" (5) "pf_monitor_wire 7'bzzzzzz1 " +ANNOTATION: " only 6th bit of PBA is used so rest all branches are invalid " +Branch 0 "2872854103" "pf_monitor_wire" (4) "pf_monitor_wire 7'bzzzzz1z " +ANNOTATION: " only 6th bit of PBA is used so rest all branches are invalid " +Branch 0 "2872854103" "pf_monitor_wire" (3) "pf_monitor_wire 7'bzzzz1zz " +ANNOTATION: " only 6th bit of PBA is used so rest all branches are invalid " +Branch 0 "2872854103" "pf_monitor_wire" (2) "pf_monitor_wire 7'bzzz1zzz " +Branch 3 "2242792596" "(~rst_n)" (2) "(~rst_n) 0,7'bzz1zzzz " +Branch 3 "2242792596" "(~rst_n)" (6) "(~rst_n) 0,7'bzzzzzz1 " +Branch 3 "2242792596" "(~rst_n)" (5) "(~rst_n) 0,7'bzzzzz1z " +Branch 3 "2242792596" "(~rst_n)" (4) "(~rst_n) 0,7'bzzzz1zz " +Branch 3 "2242792596" "(~rst_n)" (3) "(~rst_n) 0,7'bzzz1zzz " +ANNOTATION: " only 0 -3 one hot combination is used for user interrupt " +Branch 4 "1522282852" "vf_monitor_wire" (0) "vf_monitor_wire 5'b1zzzz " +Branch 7 "3319784913" "(~rst_n)" (1) "(~rst_n) 0,5'b1zzzz " +Branch 7 "3319784913" "(~rst_n)" (6) "(~rst_n) 0,default" +Branch 7 "3319784913" "(~rst_n)" (4) "(~rst_n) 0,5'bzzz1z " +Branch 7 "3319784913" "(~rst_n)" (2) "(~rst_n) 0,5'bz1zzz " +Branch 7 "3319784913" "(~rst_n)" (3) "(~rst_n) 0,5'bzz1zz " +Branch 7 "3319784913" "(~rst_n)" (5) "(~rst_n) 0,5'bzzzz1 " +CHECKSUM: "4037266764 2877412560" +INSTANCE: tb_top.DUT.pcie_wrapper.msix_top.msix_user_irq_inst +Branch 3 "4139418820" "(~rst_n)" (5) "(~rst_n) 0,1,MISSING_DEFAULT" +CHECKSUM: "3119255466 1484545624" +INSTANCE: tb_top.DUT.pcie_wrapper.msix_top.fme_msix_table +ANNOTATION: " Only INTR1 is supported " +Branch 0 "1363051132" "(!rst_n)" (2) "(!rst_n) 0,3'b1 " +ANNOTATION: " Only INTR1 is supported " +Branch 0 "1363051132" "(!rst_n)" (5) "(!rst_n) 0,3'd4 " +ANNOTATION: " Only INTR1 is supported " +Branch 0 "1363051132" "(!rst_n)" (4) "(!rst_n) 0,3'd3 " +ANNOTATION: " Only INTR1 is supported " +Branch 0 "1363051132" "(!rst_n)" (3) "(!rst_n) 0,3'd2 " +CHECKSUM: "3782056757 3000253941" +INSTANCE: tb_top.DUT.pcie_wrapper.msix_top +Condition 18 "972554527" "((((o_intr_id == 3'b0) || (o_intr_id == 3'b1) || (o_intr_id == 3'h2) || (o_intr_id == 3'h3)) && o_intr_valid) ? 'b1 : 'b0) 1 -1" (2 "1") +Condition 6 "3334564034" "(((!pf_irq_rsp.tvalid)) || o_msix_rsp.tready) 1 -1" +Condition 28 "3918591929" "(o_msix_rsp.tvalid && o_msix_rsp.tready) 1 -1" (2 "10") +CHECKSUM: "4037266764 4133335424" +INSTANCE: tb_top.DUT.pcie_wrapper.msix_top.msix_user_irq_inst +Condition 1 "1172040511" "(msix_ack || ((|mask_bit))) 1 -1" (3 "10") +Condition 1 "1172040511" "(msix_ack || ((|mask_bit))) 1 -1" (1 "00") +CHECKSUM: "3119255466 2727592952" +INSTANCE: tb_top.DUT.pcie_wrapper.msix_top.fme_msix_table +ANNOTATION: " Only INTR1 is supported " +Condition 1 "1056197046" "(i_intr_valid && (i_intr_id != 3'h6)) 1 -1" (3 "11") +CHECKSUM: "4037266764 2093578176" +INSTANCE: tb_top.DUT.pcie_wrapper.msix_top.msix_user_irq_inst +Toggle 1to0 w_ready "logic w_ready" +Toggle 0to1 w_ready "logic w_ready" +Toggle 1to0 fifo_full "logic fifo_full" +Toggle 0to1 fifo_full "logic fifo_full" +Toggle 1to0 i_msix_mask "net i_msix_mask" +Toggle 0to1 i_msix_mask "net i_msix_mask" +Toggle 0to1 o_afu_msix_req_tready "net o_afu_msix_req_tready" +Toggle 1to0 o_afu_msix_req_tready "net o_afu_msix_req_tready" +Toggle 0to1 fifo_out [3] "logic fifo_out[3:0]" +Toggle 1to0 fifo_out [3] "logic fifo_out[3:0]" +Toggle 0to1 fifo_out [2] "logic fifo_out[3:0]" +Toggle 1to0 fifo_out [2] "logic fifo_out[3:0]" +Toggle mask_bit "logic mask_bit[3:0]" +CHECKSUM: "127665118 1449645766" +INSTANCE: tb_top.DUT.pcie_wrapper.msix_top.msix_wrapper_inst.msix_pba +Toggle 1to0 vf_priority_wire [4] "logic vf_priority_wire[4:0]" +Toggle 0to1 vf_priority_wire [4] "logic vf_priority_wire[4:0]" +Toggle 1to0 vf_monitor_wire [4] "logic vf_monitor_wire[4:0]" +Toggle 0to1 vf_monitor_wire [4] "logic vf_monitor_wire[4:0]" +Toggle 1to0 pf_irq_edge_vector [4] "logic pf_irq_edge_vector[6:0]" +Toggle 0to1 pf_irq_edge_vector [4] "logic pf_irq_edge_vector[6:0]" +Toggle 1to0 pf_irq_edge_vector [3] "logic pf_irq_edge_vector[6:0]" +Toggle 0to1 pf_irq_edge_vector [3] "logic pf_irq_edge_vector[6:0]" +Toggle 1to0 pf_irq_edge_vector [2] "logic pf_irq_edge_vector[6:0]" +Toggle 0to1 pf_irq_edge_vector [2] "logic pf_irq_edge_vector[6:0]" +Toggle 1to0 pf_irq_edge_vector [1] "logic pf_irq_edge_vector[6:0]" +Toggle 0to1 pf_irq_edge_vector [1] "logic pf_irq_edge_vector[6:0]" +Toggle 1to0 pf_irq_edge_vector [0] "logic pf_irq_edge_vector[6:0]" +Toggle 0to1 pf_irq_edge_vector [0] "logic pf_irq_edge_vector[6:0]" +Toggle 1to0 pf_irq_edge_vector [5] "logic pf_irq_edge_vector[6:0]" +Toggle 0to1 pf_irq_edge_vector [5] "logic pf_irq_edge_vector[6:0]" +Toggle 1to0 pf_irq_sync1 [4] "logic pf_irq_sync1[6:0]" +Toggle 0to1 pf_irq_sync1 [4] "logic pf_irq_sync1[6:0]" +Toggle 1to0 pf_irq_sync1 [3] "logic pf_irq_sync1[6:0]" +Toggle 0to1 pf_irq_sync1 [3] "logic pf_irq_sync1[6:0]" +Toggle 1to0 pf_irq_sync1 [2] "logic pf_irq_sync1[6:0]" +Toggle 0to1 pf_irq_sync1 [2] "logic pf_irq_sync1[6:0]" +Toggle 1to0 pf_irq_sync1 [1] "logic pf_irq_sync1[6:0]" +Toggle 0to1 pf_irq_sync1 [1] "logic pf_irq_sync1[6:0]" +Toggle 1to0 pf_irq_sync1 [0] "logic pf_irq_sync1[6:0]" +Toggle 0to1 pf_irq_sync1 [0] "logic pf_irq_sync1[6:0]" +Toggle 1to0 pf_irq_sync1 [5] "logic pf_irq_sync1[6:0]" +Toggle 0to1 pf_irq_sync1 [5] "logic pf_irq_sync1[6:0]" +Toggle 1to0 pf_irq_vector [4] "net pf_irq_vector[6:0]" +Toggle 0to1 pf_irq_vector [4] "net pf_irq_vector[6:0]" +Toggle 1to0 pf_irq_vector [3] "net pf_irq_vector[6:0]" +Toggle 0to1 pf_irq_vector [3] "net pf_irq_vector[6:0]" +Toggle 1to0 pf_irq_vector [2] "net pf_irq_vector[6:0]" +Toggle 0to1 pf_irq_vector [2] "net pf_irq_vector[6:0]" +Toggle 1to0 pf_irq_vector [1] "net pf_irq_vector[6:0]" +Toggle 0to1 pf_irq_vector [1] "net pf_irq_vector[6:0]" +Toggle 1to0 pf_irq_vector [0] "net pf_irq_vector[6:0]" +Toggle 0to1 pf_irq_vector [0] "net pf_irq_vector[6:0]" +Toggle 1to0 pf_irq_vector [5] "net pf_irq_vector[6:0]" +Toggle 0to1 pf_irq_vector [5] "net pf_irq_vector[6:0]" +Toggle 1to0 pf_mask_vector [4] "net pf_mask_vector[6:0]" +Toggle 0to1 pf_mask_vector [4] "net pf_mask_vector[6:0]" +Toggle 1to0 pf_mask_vector [3] "net pf_mask_vector[6:0]" +Toggle 0to1 pf_mask_vector [3] "net pf_mask_vector[6:0]" +Toggle 1to0 pf_mask_vector [2] "net pf_mask_vector[6:0]" +Toggle 0to1 pf_mask_vector [2] "net pf_mask_vector[6:0]" +Toggle 1to0 pf_mask_vector [1] "net pf_mask_vector[6:0]" +Toggle 0to1 pf_mask_vector [1] "net pf_mask_vector[6:0]" +Toggle 1to0 pf_mask_vector [0] "net pf_mask_vector[6:0]" +Toggle 0to1 pf_mask_vector [0] "net pf_mask_vector[6:0]" +Toggle 1to0 pf_mask_vector [5] "net pf_mask_vector[6:0]" +Toggle 0to1 pf_mask_vector [5] "net pf_mask_vector[6:0]" +Toggle 1to0 pf_monitor_wire [4] "logic pf_monitor_wire[6:0]" +Toggle 0to1 pf_monitor_wire [4] "logic pf_monitor_wire[6:0]" +Toggle 1to0 pf_monitor_wire [3] "logic pf_monitor_wire[6:0]" +Toggle 0to1 pf_monitor_wire [3] "logic pf_monitor_wire[6:0]" +Toggle 1to0 pf_monitor_wire [2] "logic pf_monitor_wire[6:0]" +Toggle 0to1 pf_monitor_wire [2] "logic pf_monitor_wire[6:0]" +Toggle 1to0 pf_monitor_wire [1] "logic pf_monitor_wire[6:0]" +Toggle 0to1 pf_monitor_wire [1] "logic pf_monitor_wire[6:0]" +Toggle 1to0 pf_monitor_wire [0] "logic pf_monitor_wire[6:0]" +Toggle 0to1 pf_monitor_wire [0] "logic pf_monitor_wire[6:0]" +Toggle 1to0 pf_monitor_wire [5] "logic pf_monitor_wire[6:0]" +Toggle 0to1 pf_monitor_wire [5] "logic pf_monitor_wire[6:0]" +Toggle 1to0 pf_priority_wire [4] "logic pf_priority_wire[6:0]" +Toggle 0to1 pf_priority_wire [4] "logic pf_priority_wire[6:0]" +Toggle 1to0 pf_priority_wire [3] "logic pf_priority_wire[6:0]" +Toggle 0to1 pf_priority_wire [3] "logic pf_priority_wire[6:0]" +Toggle 1to0 pf_priority_wire [2] "logic pf_priority_wire[6:0]" +Toggle 0to1 pf_priority_wire [2] "logic pf_priority_wire[6:0]" +Toggle 1to0 pf_priority_wire [1] "logic pf_priority_wire[6:0]" +Toggle 0to1 pf_priority_wire [1] "logic pf_priority_wire[6:0]" +Toggle 1to0 pf_priority_wire [0] "logic pf_priority_wire[6:0]" +Toggle 0to1 pf_priority_wire [0] "logic pf_priority_wire[6:0]" +Toggle 1to0 pf_priority_wire [5] "logic pf_priority_wire[6:0]" +Toggle 0to1 pf_priority_wire [5] "logic pf_priority_wire[6:0]" +Toggle 1to0 rst_n "net rst_n" +Toggle 1to0 vf_irq_edge_vector [4] "logic vf_irq_edge_vector[4:0]" +Toggle 0to1 vf_irq_edge_vector [4] "logic vf_irq_edge_vector[4:0]" +Toggle 1to0 vf_irq_monitor [4] "logic vf_irq_monitor[4:0]" +Toggle 0to1 vf_irq_monitor [4] "logic vf_irq_monitor[4:0]" +Toggle 1to0 vf_irq_sync1 [4] "logic vf_irq_sync1[4:0]" +Toggle 0to1 vf_irq_sync1 [4] "logic vf_irq_sync1[4:0]" +Toggle 1to0 vf_irq_vector [4] "net vf_irq_vector[4:0]" +Toggle 0to1 vf_irq_vector [4] "net vf_irq_vector[4:0]" +Toggle 1to0 vf_mask_vector [1] "net vf_mask_vector[4:0]" +Toggle 0to1 vf_mask_vector [1] "net vf_mask_vector[4:0]" +Toggle 1to0 vf_mask_vector [0] "net vf_mask_vector[4:0]" +Toggle 0to1 vf_mask_vector [0] "net vf_mask_vector[4:0]" +Toggle 1to0 vf_mask_vector [4] "net vf_mask_vector[4:0]" +Toggle 0to1 vf_mask_vector [4] "net vf_mask_vector[4:0]" +Toggle 1to0 pf_irq_monitor [4] "logic pf_irq_monitor[6:0]" +Toggle 0to1 pf_irq_monitor [4] "logic pf_irq_monitor[6:0]" +Toggle 1to0 pf_irq_monitor [3] "logic pf_irq_monitor[6:0]" +Toggle 0to1 pf_irq_monitor [3] "logic pf_irq_monitor[6:0]" +Toggle 1to0 pf_irq_monitor [2] "logic pf_irq_monitor[6:0]" +Toggle 0to1 pf_irq_monitor [2] "logic pf_irq_monitor[6:0]" +Toggle 1to0 pf_irq_monitor [1] "logic pf_irq_monitor[6:0]" +Toggle 0to1 pf_irq_monitor [1] "logic pf_irq_monitor[6:0]" +Toggle 1to0 pf_irq_monitor [0] "logic pf_irq_monitor[6:0]" +Toggle 0to1 pf_irq_monitor [0] "logic pf_irq_monitor[6:0]" +Toggle 1to0 pf_irq_monitor [5] "logic pf_irq_monitor[6:0]" +Toggle 0to1 pf_irq_monitor [5] "logic pf_irq_monitor[6:0]" +Toggle 1to0 inp2cr_msix_vpba [62] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [62] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [61] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [61] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [60] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [60] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [59] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [59] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [58] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [58] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [57] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [57] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [56] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [56] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [55] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [55] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [54] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [54] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [53] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [53] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [52] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [52] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [51] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [51] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [50] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [50] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [49] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [49] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [48] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [48] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [47] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [47] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [46] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [46] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [45] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [45] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [44] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [44] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [43] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [43] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [42] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [42] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [41] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [41] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [40] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [40] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [39] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [39] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [38] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [38] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [37] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [37] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [36] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [36] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [35] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [35] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [34] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [34] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [33] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [33] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [32] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [32] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [31] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [31] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [30] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [30] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [29] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [29] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [28] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [28] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [27] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [27] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [26] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [26] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [25] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [25] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [24] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [24] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [23] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [23] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [22] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [22] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [21] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [21] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [20] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [20] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [19] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [19] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [18] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [18] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [17] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [17] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [16] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [16] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [15] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [15] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [14] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [14] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [13] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [13] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [12] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [12] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [11] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [11] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [10] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [10] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [9] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [9] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [8] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [8] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [7] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [7] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [6] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [6] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [5] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [5] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [4] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [4] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [63] "logic inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [63] "logic inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_pba [4] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [4] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [3] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [3] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [2] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [2] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [1] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [1] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [0] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [0] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [5] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [5] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [62] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [62] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [61] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [61] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [60] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [60] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [59] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [59] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [58] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [58] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [57] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [57] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [56] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [56] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [55] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [55] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [54] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [54] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [53] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [53] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [52] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [52] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [51] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [51] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [50] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [50] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [49] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [49] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [48] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [48] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [47] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [47] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [46] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [46] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [45] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [45] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [44] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [44] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [43] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [43] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [42] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [42] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [41] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [41] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [40] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [40] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [39] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [39] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [38] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [38] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [37] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [37] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [36] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [36] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [35] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [35] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [34] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [34] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [33] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [33] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [32] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [32] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [31] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [31] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [30] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [30] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [29] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [29] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [28] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [28] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [27] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [27] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [26] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [26] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [25] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [25] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [24] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [24] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [23] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [23] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [22] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [22] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [21] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [21] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [20] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [20] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [19] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [19] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [18] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [18] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [17] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [17] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [16] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [16] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [15] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [15] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [14] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [14] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [13] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [13] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [12] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [12] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [11] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [11] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [10] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [10] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [9] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [9] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [8] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [8] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [7] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [7] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [63] "logic inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [63] "logic inp2cr_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_vpba [62] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [62] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [61] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [61] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [60] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [60] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [59] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [59] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [58] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [58] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [57] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [57] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [56] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [56] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [55] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [55] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [54] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [54] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [53] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [53] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [52] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [52] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [51] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [51] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [50] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [50] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [49] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [49] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [48] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [48] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [47] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [47] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [46] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [46] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [45] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [45] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [44] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [44] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [43] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [43] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [42] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [42] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [41] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [41] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [40] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [40] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [39] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [39] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [38] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [38] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [37] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [37] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [36] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [36] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [35] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [35] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [34] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [34] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [33] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [33] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [32] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [32] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [31] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [31] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [30] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [30] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [29] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [29] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [28] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [28] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [27] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [27] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [26] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [26] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [25] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [25] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [24] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [24] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [23] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [23] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [22] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [22] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [21] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [21] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [20] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [20] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [19] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [19] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [18] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [18] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [17] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [17] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [16] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [16] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [15] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [15] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [14] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [14] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [13] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [13] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [12] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [12] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [11] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [11] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [10] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [10] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [9] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [9] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [8] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [8] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [7] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [7] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [6] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [6] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [5] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [5] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [4] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [4] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [63] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [63] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_pba [4] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [4] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [3] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [3] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [2] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [2] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [1] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [1] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [0] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [0] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [5] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [5] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [62] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [62] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [61] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [61] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [60] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [60] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [59] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [59] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [58] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [58] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [57] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [57] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [56] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [56] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [55] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [55] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [54] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [54] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [53] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [53] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [52] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [52] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [51] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [51] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [50] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [50] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [49] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [49] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [48] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [48] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [47] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [47] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [46] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [46] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [45] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [45] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [44] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [44] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [43] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [43] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [42] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [42] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [41] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [41] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [40] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [40] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [39] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [39] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [38] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [38] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [37] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [37] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [36] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [36] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [35] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [35] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [34] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [34] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [33] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [33] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [32] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [32] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [31] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [31] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [30] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [30] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [29] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [29] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [28] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [28] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [27] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [27] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [26] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [26] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [25] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [25] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [24] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [24] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [23] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [23] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [22] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [22] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [21] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [21] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [20] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [20] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [19] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [19] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [18] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [18] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [17] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [17] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [16] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [16] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [15] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [15] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [14] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [14] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [13] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [13] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [12] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [12] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [11] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [11] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [10] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [10] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [9] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [9] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [8] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [8] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [7] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [7] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [63] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [63] "net cr2out_msix_pba[63:0]" +Toggle pba_sclr "net pba_sclr[6:0]" +Toggle 0to1 pf_msix_mask "net pf_msix_mask" +Toggle 1to0 pf_msix_mask "net pf_msix_mask" +Toggle 0to1 vf_msix_mask "net vf_msix_mask" +Toggle 1to0 vf_msix_mask "net vf_msix_mask" +CHECKSUM: "851333347 1208170496" +INSTANCE: tb_top.DUT.pcie_wrapper.msix_top.msix_wrapper_inst +Toggle 0to1 cr2out_msix_pba [63] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [63] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [0] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [0] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [1] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [1] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [2] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [2] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [3] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [3] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [4] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [4] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [5] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [5] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [7] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [7] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [8] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [8] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [9] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [9] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [10] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [10] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [11] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [11] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [12] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [12] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [13] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [13] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [14] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [14] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [15] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [15] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [16] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [16] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [17] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [17] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [18] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [18] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [19] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [19] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [20] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [20] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [21] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [21] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [22] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [22] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [23] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [23] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [24] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [24] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [25] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [25] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [26] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [26] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [27] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [27] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [28] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [28] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [29] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [29] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [30] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [30] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [31] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [31] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [32] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [32] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [33] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [33] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [34] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [34] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [35] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [35] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [36] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [36] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [37] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [37] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [38] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [38] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [39] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [39] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [40] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [40] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [41] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [41] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [42] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [42] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [43] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [43] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [44] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [44] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [45] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [45] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [46] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [46] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [47] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [47] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [48] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [48] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [49] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [49] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [50] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [50] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [51] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [51] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [52] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [52] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [53] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [53] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [54] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [54] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [55] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [55] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [56] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [56] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [57] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [57] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [58] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [58] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [59] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [59] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [60] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [60] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [61] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [61] "net cr2out_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_pba [62] "net cr2out_msix_pba[63:0]" +Toggle 1to0 cr2out_msix_pba [62] "net cr2out_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [63] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [63] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [0] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [0] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [1] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [1] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [2] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [2] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [3] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [3] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [4] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [4] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [5] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [5] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [7] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [7] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [8] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [8] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [9] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [9] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [10] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [10] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [11] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [11] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [12] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [12] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [13] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [13] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [14] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [14] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [15] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [15] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [16] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [16] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [17] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [17] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [18] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [18] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [19] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [19] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [20] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [20] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [21] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [21] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [22] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [22] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [23] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [23] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [24] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [24] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [25] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [25] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [26] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [26] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [27] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [27] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [28] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [28] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [29] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [29] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [30] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [30] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [31] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [31] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [32] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [32] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [33] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [33] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [34] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [34] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [35] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [35] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [36] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [36] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [37] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [37] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [38] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [38] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [39] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [39] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [40] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [40] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [41] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [41] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [42] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [42] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [43] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [43] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [44] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [44] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [45] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [45] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [46] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [46] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [47] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [47] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [48] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [48] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [49] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [49] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [50] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [50] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [51] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [51] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [52] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [52] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [53] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [53] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [54] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [54] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [55] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [55] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [56] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [56] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [57] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [57] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [58] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [58] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [59] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [59] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [60] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [60] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [61] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [61] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 inp2cr_msix_pba [62] "net inp2cr_msix_pba[63:0]" +Toggle 1to0 inp2cr_msix_pba [62] "net inp2cr_msix_pba[63:0]" +Toggle 0to1 cr2out_msix_vpba [63] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [63] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [4] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [4] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [5] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [5] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [6] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [6] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [7] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [7] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [8] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [8] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [9] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [9] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [10] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [10] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [11] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [11] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [12] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [12] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [13] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [13] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [14] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [14] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [15] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [15] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [16] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [16] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [17] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [17] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [18] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [18] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [19] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [19] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [20] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [20] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [21] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [21] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [22] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [22] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [23] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [23] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [24] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [24] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [25] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [25] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [26] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [26] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [27] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [27] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [28] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [28] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [29] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [29] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [30] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [30] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [31] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [31] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [32] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [32] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [33] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [33] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [34] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [34] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [35] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [35] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [36] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [36] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [37] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [37] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [38] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [38] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [39] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [39] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [40] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [40] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [41] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [41] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [42] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [42] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [43] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [43] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [44] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [44] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [45] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [45] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [46] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [46] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [47] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [47] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [48] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [48] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [49] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [49] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [50] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [50] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [51] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [51] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [52] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [52] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [53] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [53] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [54] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [54] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [55] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [55] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [56] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [56] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [57] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [57] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [58] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [58] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [59] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [59] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [60] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [60] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [61] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [61] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 cr2out_msix_vpba [62] "net cr2out_msix_vpba[63:0]" +Toggle 1to0 cr2out_msix_vpba [62] "net cr2out_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [63] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [63] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [4] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [4] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [5] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [5] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [6] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [6] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [7] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [7] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [8] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [8] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [9] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [9] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [10] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [10] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [11] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [11] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [12] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [12] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [13] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [13] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [14] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [14] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [15] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [15] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [16] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [16] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [17] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [17] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [18] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [18] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [19] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [19] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [20] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [20] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [21] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [21] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [22] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [22] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [23] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [23] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [24] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [24] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [25] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [25] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [26] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [26] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [27] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [27] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [28] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [28] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [29] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [29] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [30] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [30] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [31] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [31] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [32] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [32] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [33] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [33] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [34] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [34] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [35] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [35] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [36] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [36] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [37] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [37] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [38] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [38] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [39] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [39] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [40] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [40] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [41] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [41] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [42] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [42] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [43] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [43] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [44] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [44] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [45] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [45] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [46] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [46] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [47] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [47] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [48] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [48] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [49] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [49] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [50] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [50] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [51] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [51] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [52] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [52] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [53] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [53] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [54] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [54] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [55] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [55] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [56] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [56] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [57] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [57] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [58] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [58] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [59] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [59] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [60] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [60] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [61] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [61] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 inp2cr_msix_vpba [62] "net inp2cr_msix_vpba[63:0]" +Toggle 1to0 inp2cr_msix_vpba [62] "net inp2cr_msix_vpba[63:0]" +Toggle 0to1 pf_irq_vector [5] "logic pf_irq_vector[6:0]" +Toggle 1to0 pf_irq_vector [5] "logic pf_irq_vector[6:0]" +Toggle 0to1 pf_irq_vector [0] "logic pf_irq_vector[6:0]" +Toggle 1to0 pf_irq_vector [0] "logic pf_irq_vector[6:0]" +Toggle 0to1 pf_irq_vector [1] "logic pf_irq_vector[6:0]" +Toggle 1to0 pf_irq_vector [1] "logic pf_irq_vector[6:0]" +Toggle 0to1 pf_irq_vector [2] "logic pf_irq_vector[6:0]" +Toggle 1to0 pf_irq_vector [2] "logic pf_irq_vector[6:0]" +Toggle 0to1 pf_irq_vector [3] "logic pf_irq_vector[6:0]" +Toggle 1to0 pf_irq_vector [3] "logic pf_irq_vector[6:0]" +Toggle 0to1 pf_irq_vector [4] "logic pf_irq_vector[6:0]" +Toggle 1to0 pf_irq_vector [4] "logic pf_irq_vector[6:0]" +Toggle 0to1 vf_irq_vector [4] "logic vf_irq_vector[4:0]" +Toggle 1to0 vf_irq_vector [4] "logic vf_irq_vector[4:0]" +Toggle 0to1 port_irq_edge "logic port_irq_edge" +Toggle 1to0 port_irq_edge "logic port_irq_edge" +Toggle port_irq_sync "logic port_irq_sync[1:0]" +Toggle port_irq_pulse "logic port_irq_pulse[1:0]" +Toggle 0to1 port_irq_out "logic port_irq_out" +Toggle 1to0 port_irq_out "logic port_irq_out" +Toggle 0to1 port_irq_in "net port_irq_in" +Toggle 1to0 port_irq_in "net port_irq_in" +Toggle pba_sclr "net pba_sclr[6:0]" +Toggle a2c_msix_en_pf "net a2c_msix_en_pf[1:0]" +Toggle a2c_msix_fn_mask_pf "net a2c_msix_fn_mask_pf[1:0]" diff --git a/verification/coverage/mx2ho_ab_mux.el b/verification/coverage/mx2ho_ab_mux.el new file mode 100644 index 0000000..addf8fe --- /dev/null +++ b/verification/coverage/mx2ho_ab_mux.el @@ -0,0 +1,578 @@ +//================================================== +// This file contains the Excluded objects +// Generated By User: srudrarx +// Format Version: 2 +// Date: Wed May 25 03:44:50 2022 +// ExclMode: default +//================================================== +CHECKSUM: "1944445801" +INSTANCE:tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[1].skid +CHECKSUM: "1259019545" +INSTANCE:tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[1].skid.r.axis_pl_stage[0].axis_reg_inst +CHECKSUM: "1259019545" +INSTANCE:tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[1].skid.r.axis_pl_stage[1].axis_reg_inst +CHECKSUM: "2765972262 3063981320" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux +Toggle 1to0 hold_1hot [1] "logic hold_1hot[1:0]" +Toggle 0to1 hold_1hot [1] "logic hold_1hot[1:0]" +Toggle in_tdata [1][511:0] "logic [1:0][511:0]in_tdata" +Toggle in_tkeep [1][63:0] "logic [1:0][63:0]in_tkeep" +Toggle 1to0 in_tlast [1] "logic in_tlast[1:0]" +Toggle 0to1 in_tlast [1] "logic in_tlast[1:0]" +Toggle 1to0 in_tready [1] "logic in_tready[1:0]" +Toggle 0to1 in_tready [1] "logic in_tready[1:0]" +Toggle in_tuser_vendor [0][9:1] "logic [1:0][9:0]in_tuser_vendor" +Toggle in_tuser_vendor [1][9:0] "logic [1:0][9:0]in_tuser_vendor" +Toggle 1to0 in_tvalid [1] "logic in_tvalid[1:0]" +Toggle 0to1 in_tvalid [1] "logic in_tvalid[1:0]" +Toggle 1to0 sel_1hot [1] "logic sel_1hot[1:0]" +Toggle 0to1 sel_1hot [1] "logic sel_1hot[1:0]" +Toggle 1to0 bid_tvalid [1] "logic bid_tvalid[1:0]" +Toggle 0to1 bid_tvalid [1] "logic bid_tvalid[1:0]" +CHECKSUM: "3777034231 861830707" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.arb +Toggle 1to0 in_valid [1] "logic in_valid[1:0]" +Toggle 0to1 in_valid [1] "logic in_valid[1:0]" +Toggle 1to0 out_select [0] "logic out_select[0:0]" +Toggle 0to1 out_select [0] "logic out_select[0:0]" +Toggle 1to0 out_select_1hot [1] "logic out_select_1hot[1:0]" +Toggle 0to1 out_select_1hot [1] "logic out_select_1hot[1:0]" +Toggle 1to0 hold_priority [1] "logic hold_priority[1:0]" +Toggle 0to1 hold_priority [1] "logic hold_priority[1:0]" +CHECKSUM: "50492599 3281435365" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.arb.gen_4way_arbiter.inst_fair_arbiter_4way +Toggle 1to0 hold_priority [1] "logic hold_priority[1:0]" +Toggle 0to1 hold_priority [1] "logic hold_priority[1:0]" +Toggle 1to0 in_valid [1] "logic in_valid[1:0]" +Toggle 0to1 in_valid [1] "logic in_valid[1:0]" +Toggle 1to0 out_select [0] "logic out_select[0:0]" +Toggle 0to1 out_select [0] "logic out_select[0:0]" +Toggle 1to0 out_select_1hot [1] "logic out_select_1hot[1:0]" +Toggle 0to1 out_select_1hot [1] "logic out_select_1hot[1:0]" +Toggle 1to0 fixed_width_in_valid [2] "reg fixed_width_in_valid[3:0]" +Toggle 0to1 fixed_width_in_valid [2] "reg fixed_width_in_valid[3:0]" +Toggle 1to0 fixed_width_in_valid [1] "reg fixed_width_in_valid[3:0]" +Toggle 0to1 fixed_width_in_valid [1] "reg fixed_width_in_valid[3:0]" +Toggle 1to0 fixed_width_in_valid [3] "reg fixed_width_in_valid[3:0]" +Toggle 0to1 fixed_width_in_valid [3] "reg fixed_width_in_valid[3:0]" +CHECKSUM: "1944445801 2367304296" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[1].skid +Toggle 1to0 rst_n "logic rst_n" +Toggle 0to1 rst_n "logic rst_n" +Toggle 1to0 clk "logic clk" +Toggle 0to1 clk "logic clk" +CHECKSUM: "1259019545 3297052881" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[0].skid.r.axis_pl_stage[0].axis_reg_inst +Toggle genblk1.m_tdest_reg "reg genblk1.m_tdest_reg[7:0]" +Toggle genblk1.m_tid_pre "reg genblk1.m_tid_pre[7:0]" +Toggle genblk1.m_tid_reg "reg genblk1.m_tid_reg[7:0]" +Toggle 1to0 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle genblk1.s_tdest_reg "reg genblk1.s_tdest_reg[7:0]" +Toggle genblk1.s_tid_reg "reg genblk1.s_tid_reg[7:0]" +Toggle 1to0 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle m_tdest "net m_tdest[7:0]" +Toggle m_tid "net m_tid[7:0]" +Toggle 1to0 m_tuser [8] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [8] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [7] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [7] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [6] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [6] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [5] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [5] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [4] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [4] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [3] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [3] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [2] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [2] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [1] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [1] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [9] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [9] "net m_tuser[9:0]" +Toggle s_tdest "net s_tdest[7:0]" +Toggle s_tid "net s_tid[7:0]" +Toggle 1to0 s_tuser [8] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [8] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [7] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [7] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [6] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [6] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [5] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [5] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [4] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [4] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [3] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [3] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [2] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [2] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [1] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [1] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [9] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [9] "net s_tuser[9:0]" +Toggle genblk1.m_tdest_pre "reg genblk1.m_tdest_pre[7:0]" +CHECKSUM: "1259019545 3297052881" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[0].skid.r.axis_pl_stage[1].axis_reg_inst +Toggle genblk1.m_tdest_reg "reg genblk1.m_tdest_reg[7:0]" +Toggle genblk1.m_tid_pre "reg genblk1.m_tid_pre[7:0]" +Toggle genblk1.m_tid_reg "reg genblk1.m_tid_reg[7:0]" +Toggle 1to0 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle genblk1.s_tdest_reg "reg genblk1.s_tdest_reg[7:0]" +Toggle genblk1.s_tid_reg "reg genblk1.s_tid_reg[7:0]" +Toggle 1to0 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle m_tdest "net m_tdest[7:0]" +Toggle m_tid "net m_tid[7:0]" +Toggle 1to0 m_tuser [8] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [8] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [7] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [7] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [6] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [6] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [5] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [5] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [4] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [4] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [3] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [3] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [2] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [2] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [1] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [1] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [9] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [9] "net m_tuser[9:0]" +Toggle s_tdest "net s_tdest[7:0]" +Toggle s_tid "net s_tid[7:0]" +Toggle 1to0 s_tuser [8] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [8] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [7] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [7] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [6] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [6] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [5] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [5] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [4] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [4] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [3] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [3] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [2] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [2] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [1] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [1] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [9] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [9] "net s_tuser[9:0]" +Toggle genblk1.m_tdest_pre "reg genblk1.m_tdest_pre[7:0]" +CHECKSUM: "1259019545 3297052881" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[1].skid.r.axis_pl_stage[0].axis_reg_inst +Toggle 1to0 s_tready "net s_tready" +Toggle 0to1 s_tready "net s_tready" +Toggle 1to0 s_tlast "net s_tlast" +Toggle 0to1 s_tlast "net s_tlast" +Toggle s_tdata "net s_tdata[511:0]" +Toggle m_tuser "net m_tuser[9:0]" +Toggle s_tid "net s_tid[7:0]" +Toggle s_tdest "net s_tdest[7:0]" +Toggle s_tkeep "net s_tkeep[63:0]" +Toggle 1to0 rst_n "net rst_n" +Toggle 0to1 rst_n "net rst_n" +Toggle 1to0 m_tvalid "net m_tvalid" +Toggle 0to1 m_tvalid "net m_tvalid" +Toggle 1to0 m_tready "net m_tready" +Toggle 0to1 m_tready "net m_tready" +Toggle 1to0 m_tlast "net m_tlast" +Toggle 0to1 m_tlast "net m_tlast" +Toggle m_tkeep "net m_tkeep[63:0]" +Toggle m_tdest "net m_tdest[7:0]" +Toggle m_tdata "net m_tdata[511:0]" +Toggle 1to0 genblk1.s_tvalid_reg "reg genblk1.s_tvalid_reg" +Toggle 0to1 genblk1.s_tvalid_reg "reg genblk1.s_tvalid_reg" +Toggle m_tid "net m_tid[7:0]" +Toggle 1to0 genblk1.use_reg "reg genblk1.use_reg" +Toggle 0to1 genblk1.use_reg "reg genblk1.use_reg" +Toggle genblk1.s_tuser_reg "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tready_reg "reg genblk1.s_tready_reg" +Toggle 0to1 genblk1.s_tready_reg "reg genblk1.s_tready_reg" +Toggle 1to0 genblk1.s_tready_reg_dup "reg genblk1.s_tready_reg_dup" +Toggle 0to1 genblk1.s_tready_reg_dup "reg genblk1.s_tready_reg_dup" +Toggle 1to0 genblk1.s_tready_pre "logic genblk1.s_tready_pre" +Toggle 0to1 genblk1.s_tready_pre "logic genblk1.s_tready_pre" +Toggle 1to0 genblk1.s_tlast_reg "reg genblk1.s_tlast_reg" +Toggle 0to1 genblk1.s_tlast_reg "reg genblk1.s_tlast_reg" +Toggle genblk1.s_tid_reg "reg genblk1.s_tid_reg[7:0]" +Toggle genblk1.s_tkeep_reg "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 s_tvalid "net s_tvalid" +Toggle 0to1 s_tvalid "net s_tvalid" +Toggle s_tuser "net s_tuser[9:0]" +Toggle genblk1.s_tdata_reg "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tvalid_pre "reg genblk1.m_tvalid_pre" +Toggle 0to1 genblk1.m_tvalid_pre "reg genblk1.m_tvalid_pre" +Toggle 1to0 genblk1.m_tvalid_reg "reg genblk1.m_tvalid_reg" +Toggle 0to1 genblk1.m_tvalid_reg "reg genblk1.m_tvalid_reg" +Toggle genblk1.m_tuser_reg "reg genblk1.m_tuser_reg[9:0]" +Toggle genblk1.m_tkeep_reg "reg genblk1.m_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tlast_pre "reg genblk1.m_tlast_pre" +Toggle 0to1 genblk1.m_tlast_pre "reg genblk1.m_tlast_pre" +Toggle 1to0 genblk1.m_tlast_reg "reg genblk1.m_tlast_reg" +Toggle 0to1 genblk1.m_tlast_reg "reg genblk1.m_tlast_reg" +Toggle genblk1.m_tuser_pre "reg genblk1.m_tuser_pre[9:0]" +Toggle genblk1.m_tkeep_pre "reg genblk1.m_tkeep_pre[63:0]" +Toggle genblk1.m_tid_reg "reg genblk1.m_tid_reg[7:0]" +Toggle genblk1.m_tid_pre "reg genblk1.m_tid_pre[7:0]" +Toggle genblk1.m_tdest_reg "reg genblk1.m_tdest_reg[7:0]" +Toggle genblk1.m_tdest_pre "reg genblk1.m_tdest_pre[7:0]" +Toggle genblk1.m_tdata_reg "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 clk "net clk" +Toggle 0to1 clk "net clk" +Toggle genblk1.m_tdata_pre "reg genblk1.m_tdata_pre[511:0]" +Toggle genblk1.s_tdest_reg "reg genblk1.s_tdest_reg[7:0]" +CHECKSUM: "1259019545 3297052881" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[1].skid.r.axis_pl_stage[1].axis_reg_inst +Toggle 1to0 m_tvalid "net m_tvalid" +Toggle 0to1 m_tvalid "net m_tvalid" +Toggle m_tdest "net m_tdest[7:0]" +Toggle m_tdata "net m_tdata[511:0]" +Toggle m_tuser "net m_tuser[9:0]" +Toggle 1to0 m_tlast "net m_tlast" +Toggle 0to1 m_tlast "net m_tlast" +Toggle m_tid "net m_tid[7:0]" +Toggle 1to0 m_tready "net m_tready" +Toggle 0to1 m_tready "net m_tready" +Toggle m_tkeep "net m_tkeep[63:0]" +Toggle 1to0 genblk1.use_reg "reg genblk1.use_reg" +Toggle 0to1 genblk1.use_reg "reg genblk1.use_reg" +Toggle 1to0 s_tvalid "net s_tvalid" +Toggle 0to1 s_tvalid "net s_tvalid" +Toggle 1to0 s_tready "net s_tready" +Toggle 0to1 s_tready "net s_tready" +Toggle s_tuser "net s_tuser[9:0]" +Toggle s_tkeep "net s_tkeep[63:0]" +Toggle s_tdest "net s_tdest[7:0]" +Toggle s_tdata "net s_tdata[511:0]" +Toggle s_tid "net s_tid[7:0]" +Toggle 1to0 s_tlast "net s_tlast" +Toggle 0to1 s_tlast "net s_tlast" +Toggle 1to0 genblk1.s_tvalid_reg "reg genblk1.s_tvalid_reg" +Toggle 0to1 genblk1.s_tvalid_reg "reg genblk1.s_tvalid_reg" +Toggle 1to0 genblk1.s_tready_reg_dup "reg genblk1.s_tready_reg_dup" +Toggle 0to1 genblk1.s_tready_reg_dup "reg genblk1.s_tready_reg_dup" +Toggle 1to0 genblk1.s_tlast_reg "reg genblk1.s_tlast_reg" +Toggle 0to1 genblk1.s_tlast_reg "reg genblk1.s_tlast_reg" +Toggle genblk1.s_tkeep_reg "reg genblk1.s_tkeep_reg[63:0]" +Toggle 1to0 genblk1.m_tvalid_reg "reg genblk1.m_tvalid_reg" +Toggle 0to1 genblk1.m_tvalid_reg "reg genblk1.m_tvalid_reg" +Toggle 1to0 genblk1.s_tready_reg "reg genblk1.s_tready_reg" +Toggle 0to1 genblk1.s_tready_reg "reg genblk1.s_tready_reg" +Toggle genblk1.s_tuser_reg "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tready_pre "logic genblk1.s_tready_pre" +Toggle 0to1 genblk1.s_tready_pre "logic genblk1.s_tready_pre" +Toggle genblk1.s_tid_reg "reg genblk1.s_tid_reg[7:0]" +Toggle genblk1.s_tdest_reg "reg genblk1.s_tdest_reg[7:0]" +Toggle genblk1.s_tdata_reg "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tvalid_pre "reg genblk1.m_tvalid_pre" +Toggle 0to1 genblk1.m_tvalid_pre "reg genblk1.m_tvalid_pre" +Toggle genblk1.m_tuser_pre "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tlast_reg "reg genblk1.m_tlast_reg" +Toggle 0to1 genblk1.m_tlast_reg "reg genblk1.m_tlast_reg" +Toggle 1to0 genblk1.m_tlast_pre "reg genblk1.m_tlast_pre" +Toggle 0to1 genblk1.m_tlast_pre "reg genblk1.m_tlast_pre" +Toggle genblk1.m_tkeep_reg "reg genblk1.m_tkeep_reg[63:0]" +Toggle genblk1.m_tid_reg "reg genblk1.m_tid_reg[7:0]" +Toggle genblk1.m_tuser_reg "reg genblk1.m_tuser_reg[9:0]" +Toggle genblk1.m_tkeep_pre "reg genblk1.m_tkeep_pre[63:0]" +Toggle genblk1.m_tid_pre "reg genblk1.m_tid_pre[7:0]" +Toggle genblk1.m_tdest_reg "reg genblk1.m_tdest_reg[7:0]" +Toggle genblk1.m_tdata_pre "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 clk "net clk" +Toggle 0to1 clk "net clk" +Toggle genblk1.m_tdest_pre "reg genblk1.m_tdest_pre[7:0]" +Toggle genblk1.m_tdata_reg "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 rst_n "net rst_n" +Toggle 0to1 rst_n "net rst_n" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.sink_in[1] +Toggle tuser_vendor "logic tuser_vendor[9:0]" +Toggle 1to0 tready "logic tready" +Toggle 0to1 tready "logic tready" +Toggle 1to0 tlast "logic tlast" +Toggle 0to1 tlast "logic tlast" +Toggle tkeep "logic tkeep[63:0]" +Toggle 1to0 rst_n "net rst_n" +Toggle 0to1 rst_n "net rst_n" +Toggle tdata "logic tdata[511:0]" +Toggle 1to0 clk "net clk" +Toggle 0to1 clk "net clk" +Toggle 1to0 tvalid "logic tvalid" +Toggle 0to1 tvalid "logic tvalid" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.sink_in[0] +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[0].skid.r.axis_pl[0] +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[0].skid.r.axis_pl[1] +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[0].skid.r.axis_pl[2] +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[1].skid.r.axis_pl[0] +Toggle 1to0 rst_n "net rst_n" +Toggle 0to1 rst_n "net rst_n" +Toggle tdata "logic tdata[511:0]" +Toggle tkeep "logic tkeep[63:0]" +Toggle 1to0 tlast "logic tlast" +Toggle 0to1 tlast "logic tlast" +Toggle tuser_vendor "logic tuser_vendor[9:0]" +Toggle 1to0 tvalid "logic tvalid" +Toggle 0to1 tvalid "logic tvalid" +Toggle 1to0 tready "logic tready" +Toggle 0to1 tready "logic tready" +Toggle 1to0 clk "net clk" +Toggle 0to1 clk "net clk" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[1].skid.r.axis_pl[1] +Toggle 1to0 rst_n "net rst_n" +Toggle 0to1 rst_n "net rst_n" +Toggle tdata "logic tdata[511:0]" +Toggle tkeep "logic tkeep[63:0]" +Toggle 1to0 tlast "logic tlast" +Toggle 0to1 tlast "logic tlast" +Toggle tuser_vendor "logic tuser_vendor[9:0]" +Toggle 1to0 tvalid "logic tvalid" +Toggle 0to1 tvalid "logic tvalid" +Toggle 1to0 tready "logic tready" +Toggle 0to1 tready "logic tready" +Toggle 1to0 clk "net clk" +Toggle 0to1 clk "net clk" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[1].skid.r.axis_pl[2] +Toggle 1to0 rst_n "net rst_n" +Toggle 0to1 rst_n "net rst_n" +Toggle 1to0 tvalid "logic tvalid" +Toggle 0to1 tvalid "logic tvalid" +Toggle tuser_vendor "logic tuser_vendor[9:0]" +Toggle 1to0 tready "logic tready" +Toggle 0to1 tready "logic tready" +Toggle tkeep "logic tkeep[63:0]" +Toggle 1to0 tlast "logic tlast" +Toggle 0to1 tlast "logic tlast" +Toggle tdata "logic tdata[511:0]" +Toggle 1to0 clk "net clk" +Toggle 0to1 clk "net clk" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[1].skid.r.axis_pl[0] +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[1].skid.r.axis_pl[1] +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[1].skid.r.axis_pl[2] +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.sink_in[0] +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.sink_in[1] +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" diff --git a/verification/coverage/mx2ho_ho2mx_port_remap.el b/verification/coverage/mx2ho_ho2mx_port_remap.el new file mode 100644 index 0000000..ace530b --- /dev/null +++ b/verification/coverage/mx2ho_ho2mx_port_remap.el @@ -0,0 +1,212 @@ +//================================================== +// This file contains the Excluded objects +// Generated By User: srudrarx +// Format Version: 2 +// Date: Tue May 24 21:38:43 2022 +// ExclMode: default +//================================================== +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.mx2ho_tx_ab[1] +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_remap +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.ho2mx_rx_remap +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.ho2mx_rx_port +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_port +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.arb2ho_tx_port +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab[1] +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab[0] +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.ho2mx_rx_port +Assert assert_tdata_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.ho2mx_rx_remap +Assert assert_tdata_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab[0] +Assert assert_tdata_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab[1] +Assert assert_tdata_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_port +Assert assert_tdata_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_remap +Assert assert_tdata_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.arb2ho_tx_port +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" diff --git a/verification/coverage/port_gasket_exclusions.el b/verification/coverage/port_gasket_exclusions.el new file mode 100644 index 0000000..d96ab12 --- /dev/null +++ b/verification/coverage/port_gasket_exclusions.el @@ -0,0 +1,29161 @@ +//================================================== +// This file contains the Excluded objects +// Generated By User: ppawar2x +// Format Version: 2 +// Date: Tue May 24 03:01:22 2022 +// ExclMode: default +//================================================== +CHECKSUM: "3647691149" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl +CHECKSUM: "1419561142" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.MEM_CH[0].avmm_bridge_inst +CHECKSUM: "1419561142" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.MEM_CH[1].avmm_bridge_inst +CHECKSUM: "1258926683" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i +CHECKSUM: "1498774643" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.host_if +CHECKSUM: "439186474" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.dprio_clk_mux +CHECKSUM: "439186474" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.csr_clk_mux +CHECKSUM: "2340561204" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.avalon_st_adapter_001.data_format_adapter_0 +CHECKSUM: "3630569307" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.req_q.genblk1.scfifo_component.dev +CHECKSUM: "3630569307" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.req_mdata_q.genblk1.scfifo_component.dev +CHECKSUM: "3630569307" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.RSP_Q[0].rsp_q.genblk1.scfifo_component.dev +CHECKSUM: "3630569307" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.RSP_Q[1].rsp_q.genblk1.scfifo_component.dev +CHECKSUM: "3630569307" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW.dev +CHECKSUM: "3630569307" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW.LOWLATENCY.dev +CHECKSUM: "3630569307" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW.dcfifo_async.ASYNC.dev +CHECKSUM: "3244719577" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xtestmux.x13.xclklossdet1 +CHECKSUM: "3998669287" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xref.xref_dig_hs +CHECKSUM: "2722001989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.jop_blaster_avmm_s_burst_adapter.altera_merlin_burst_adapter_13_1.burst_adapter.the_min.ab_sub +CHECKSUM: "2722001989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.jop_blaster_avmm_s_burst_adapter.altera_merlin_burst_adapter_13_1.burst_adapter.the_min.ac_sub +CHECKSUM: "2722001989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.jop_blaster_avmm_s_burst_adapter.altera_merlin_burst_adapter_13_1.burst_adapter.the_min.bc_sub +CHECKSUM: "2722001989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.jop_blaster_avmm_s_burst_adapter.altera_merlin_burst_adapter_13_1.burst_adapter.the_min.da_sub +CHECKSUM: "2722001989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.jop_blaster_avmm_s_burst_adapter.altera_merlin_burst_adapter_13_1.burst_adapter.the_min.db_sub +CHECKSUM: "2722001989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.jop_blaster_avmm_s_burst_adapter.altera_merlin_burst_adapter_13_1.burst_adapter.the_min.dc_sub +CHECKSUM: "65474030" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.rsp_demux +CHECKSUM: "551369117" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.PR_IP.s10_pr_0.config_stream_endpoint_inst.pr_mailbox_if +CHECKSUM: "734304423" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xfb +CHECKSUM: "3931651105" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xextclk0.xpm_dllout +CHECKSUM: "3931651105" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xextclk1.xpm_dllout +CHECKSUM: "3931651105" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdllout +CHECKSUM: "1143951268" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xatb_iopll +CHECKSUM: "486783923" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_mem.the_altsyncram.altera_syncram_inst +CHECKSUM: "486783923" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_mem.the_altsyncram.altera_syncram_inst +CHECKSUM: "486783923" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll_reconfig.iopll_reconfig_0.altsyncram_inst.altera_syncram_inst +CHECKSUM: "2429148318" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.avalon_st_adapter_001 +CHECKSUM: "589964682" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.resync.csr_to_qph_sync +CHECKSUM: "589964682" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.resync.qph_to_csr_sync +CHECKSUM: "2100166288" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.req_q.genblk1.scfifo_component +CHECKSUM: "2100166288" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.req_mdata_q.genblk1.scfifo_component +CHECKSUM: "2100166288" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.RSP_Q[0].rsp_q.genblk1.scfifo_component +CHECKSUM: "2100166288" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.RSP_Q[1].rsp_q.genblk1.scfifo_component +CHECKSUM: "3437887257" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xfpll_ctrl.xfpll_selfrst.selfrst3_sync.genblk1.genblk1.genblk1.genblk1.bit_sync_i[0].bit_sync2_reset_type_l_inst +CHECKSUM: "3437887257" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.status_reg_nregs.stat_reg_nbits[0].cfg_dprio_status_sync_regs.write_en_ack_sync_1.genblk1.genblk1.genblk1.genblk1.bit_sync_i[0].bit_sync2_reset_type_l_inst +CHECKSUM: "3437887257" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.status_reg_nregs.stat_reg_nbits[1].cfg_dprio_status_sync_regs.write_en_ack_sync_1.genblk1.genblk1.genblk1.genblk1.bit_sync_i[0].bit_sync2_reset_type_l_inst +CHECKSUM: "3437887257" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.status_reg_nregs.stat_reg_nbits[2].cfg_dprio_status_sync_regs.write_en_ack_sync_1.genblk1.genblk1.genblk1.genblk1.bit_sync_i[0].bit_sync2_reset_type_l_inst +CHECKSUM: "3437887257" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xshadow.shadow_status_nregs[0].cfg_dprio_shadow_status_regs.write_en_sync_1.genblk1.genblk1.genblk1.genblk1.bit_sync_i[0].bit_sync2_reset_type_l_inst +CHECKSUM: "3437887257" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xshadow.shadow_status_nregs[1].cfg_dprio_shadow_status_regs.write_en_sync_1.genblk1.genblk1.genblk1.genblk1.bit_sync_i[0].bit_sync2_reset_type_l_inst +CHECKSUM: "3437887257" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xshadow.shadow_status_nregs[2].cfg_dprio_shadow_status_regs.write_en_sync_1.genblk1.genblk1.genblk1.genblk1.bit_sync_i[0].bit_sync2_reset_type_l_inst +CHECKSUM: "3437887257" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.tstbus_int_sync_bit.genblk1.genblk1.genblk1.genblk1.bit_sync_i[0].bit_sync2_reset_type_l_inst +CHECKSUM: "2166155012" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.h2t_mem_s1_agent_rsp_fifo +CHECKSUM: "2166155012" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.t2h_mem_s1_agent_rsp_fifo +CHECKSUM: "2166155012" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.st_dbg_ip_ip_avmm_s_agent_rsp_fifo +CHECKSUM: "211558359" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xref +CHECKSUM: "3166389434" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[0].avmm_cdc_inst.avmm_cdc.cmd_fifo +CHECKSUM: "3166389434" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[1].avmm_cdc_inst.avmm_cdc.cmd_fifo +CHECKSUM: "4072958007" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.avmm_bridge_m0_translator +CHECKSUM: "4072958007" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_1.st_dbg_ip_h2t_mem_translator +CHECKSUM: "4072958007" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_2.st_dbg_ip_t2h_mem_translator +CHECKSUM: "4140002751" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.status_reg_nregs +CHECKSUM: "401826046" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.cb_bfm_inst +CHECKSUM: "3222090888" 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+INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[0].avmm_cdc_inst +CHECKSUM: "283274567" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[1].avmm_cdc_inst +CHECKSUM: "901514427" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.host_if.host_if.genblk3.aw_channel_pipeline +CHECKSUM: "901514427" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.host_if.host_if.genblk6.w_channel_pipeline +CHECKSUM: "901514427" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.host_if.host_if.genblk9.b_channel_pipeline +CHECKSUM: "901514427" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.host_if.host_if.genblk12.ar_channel_pipeline +CHECKSUM: "901514427" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.host_if.host_if.genblk15.r_channel_pipeline +CHECKSUM: "901514427" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_rdy_to_cr.pipe_inst +CHECKSUM: "1161111439" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll_reconfig.iopll_reconfig_0.altera_iopll_reconfig_fsm_inst +CHECKSUM: "2144707150" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[0].avmm_cdc_inst.avmm_cdc.cmd_fifo.my_altera_avalon_dc_fifo_cmd_fifo.write_crosser.sync[0].u +CHECKSUM: "2144707150" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[0].avmm_cdc_inst.avmm_cdc.cmd_fifo.my_altera_avalon_dc_fifo_cmd_fifo.write_crosser.sync[1].u +CHECKSUM: "2144707150" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[0].avmm_cdc_inst.avmm_cdc.cmd_fifo.my_altera_avalon_dc_fifo_cmd_fifo.write_crosser.sync[2].u +CHECKSUM: "2144707150" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[0].avmm_cdc_inst.avmm_cdc.cmd_fifo.my_altera_avalon_dc_fifo_cmd_fifo.write_crosser.sync[3].u +CHECKSUM: "2144707150" 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Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[0].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[1].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[2].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[3].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[4].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[5].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[6].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[7].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[8].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[9].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[10].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[11].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[12].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[13].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[14].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[15].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[16].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[17].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[18].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[19].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[20].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[21].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[22].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[23].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[24].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[25].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[26].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[27].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[28].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[29].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[30].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[31].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[32].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[33].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[34].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[35].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[36].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[37].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[38].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[39].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[40].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[41].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[42].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[43].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[44].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[45].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[46].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[47].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[48].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[49].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[50].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[51].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[52].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[53].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[54].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[55].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[56].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[57].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[58].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[59].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[60].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[61].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[62].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync.resync_chains[63].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.resync.csr_to_qph_sync.ena_strb.sr.resync_chains[0].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.resync.csr_to_qph_sync.ack_strb.sr.resync_chains[0].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.resync.qph_to_csr_sync.ena_strb.sr.resync_chains[0].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.resync.qph_to_csr_sync.ack_strb.sr.resync_chains[0].genblk1.synchronizer_nocut +CHECKSUM: "2144707150" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_locked_resync.resync_chains[0].genblk1.synchronizer_nocut +CHECKSUM: "1827042670" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.resync +CHECKSUM: "1705231235" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xvco_iopll.xvco +CHECKSUM: "1160761177" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.sld_hub_controller +CHECKSUM: "2528311387" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component +CHECKSUM: "3578343879" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.crosser +CHECKSUM: "3578343879" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.crosser_001 +CHECKSUM: "3578343879" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.crosser_002 +CHECKSUM: "3578343879" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.crosser_003 +CHECKSUM: "2867341587" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.reset_in +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[50].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[50].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[50].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[50].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[50].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[50].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[50].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[51].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[51].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[51].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[51].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[51].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[51].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[51].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[51].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[52].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[52].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[52].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[52].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[52].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[52].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[52].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[52].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[0].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[0].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[0].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[0].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[0].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[0].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[0].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[0].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[1].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[1].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[1].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[1].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[1].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[1].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[1].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[1].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[2].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[2].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[2].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[2].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[2].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[2].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[2].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[2].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[3].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[3].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[3].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[3].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[3].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[3].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[3].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[3].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[4].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[4].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[4].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[4].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[4].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[4].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[4].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[4].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[5].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[5].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[5].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[5].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[5].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[5].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[5].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[5].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[6].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[6].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[6].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[6].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[6].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[6].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[6].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[6].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[7].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[7].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[7].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[7].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[7].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[7].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[7].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[7].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[8].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[8].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[8].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[8].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[8].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[8].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[8].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[8].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[9].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[9].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[9].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[9].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[9].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[9].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[9].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[9].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[10].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[10].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[10].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[10].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[10].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[10].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[10].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[10].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[11].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[11].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[11].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[11].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[11].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[11].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[11].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[11].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[12].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[12].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[12].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[12].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[12].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[12].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[12].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[12].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[13].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[13].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[13].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[13].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[13].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[13].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[13].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[13].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[14].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[14].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[14].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[14].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[14].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[14].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[14].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[14].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[15].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[15].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[15].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[15].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[15].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[15].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[15].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[15].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[16].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[16].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[16].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[16].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[16].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[16].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[16].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[16].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[17].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[17].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[17].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[17].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[17].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[17].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[17].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[17].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[18].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[18].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[18].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[18].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[18].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[18].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[18].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[18].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[19].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[19].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[19].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[19].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[19].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[19].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[19].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[19].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[20].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[20].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[20].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[20].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[20].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[20].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[20].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[20].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[21].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[21].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[21].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[21].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[21].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[21].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[21].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[21].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[22].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[22].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[22].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[22].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[22].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[22].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[22].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[22].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[23].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[23].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[23].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[23].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[23].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[23].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[23].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[23].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[24].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[24].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[24].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[24].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[24].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[24].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[24].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[24].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[25].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[25].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[25].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[25].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[25].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[25].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[25].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[25].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[26].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[26].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[26].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[26].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[26].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[26].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[26].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[26].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[27].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[27].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[27].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[27].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[27].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[27].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[27].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[27].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[28].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[28].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[28].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[28].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[28].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[28].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[28].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[28].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[29].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[29].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[29].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[29].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[29].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[29].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[29].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[29].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[30].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[30].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[30].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[30].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[30].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[30].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[30].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[30].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[31].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[31].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[31].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[31].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[31].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[31].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[31].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[31].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[32].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[32].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[32].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[32].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[32].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[32].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[32].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[32].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[33].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[33].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[33].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[33].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[33].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[33].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[33].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[33].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[34].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[34].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[34].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[34].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[34].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[34].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[34].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[34].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[35].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[35].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[35].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[35].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[35].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[35].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[35].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[35].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[36].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[36].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[36].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[36].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[36].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[36].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[36].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[36].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[37].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[37].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[37].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[37].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[37].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[37].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[37].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[37].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[38].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[38].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[38].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[38].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[38].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[38].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[38].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[38].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[39].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[39].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[39].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[39].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[39].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[39].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[39].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[39].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[40].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[40].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[40].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[40].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[40].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[40].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[40].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[40].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[41].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[41].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[41].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[41].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[41].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[41].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[41].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[41].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[42].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[42].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[42].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[42].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[42].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[42].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[42].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[42].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[43].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[43].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[43].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[43].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[43].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[43].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[43].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[43].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[44].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[44].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[44].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[44].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[44].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[44].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[44].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[44].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[45].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[45].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[45].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[45].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[45].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[45].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[45].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[45].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[46].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[46].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[46].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[46].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[46].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[46].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[46].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[46].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[47].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[47].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[47].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[47].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[47].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[47].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[47].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[47].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[48].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[48].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[48].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[48].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[48].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[48].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[48].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[48].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[49].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[49].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[49].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[49].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[49].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[49].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[49].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[49].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[50].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[53].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[53].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[53].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[53].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[53].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[53].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[53].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[53].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[54].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[54].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[54].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[54].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[54].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[54].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[54].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[54].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[55].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[55].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[55].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[55].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[55].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[55].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[55].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[55].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[56].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[56].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[56].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[56].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[56].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[56].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[56].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[56].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[57].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[57].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[57].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[57].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[57].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[57].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[57].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[57].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[58].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[58].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[58].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[58].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[58].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[58].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[58].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[58].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[59].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[59].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[59].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[59].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[59].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[59].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[59].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[59].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[60].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[60].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[60].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[60].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[60].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[60].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[60].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[60].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[61].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[61].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[61].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[61].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[61].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[61].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[61].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[61].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[62].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[62].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[62].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[62].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[62].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[62].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[62].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[62].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[63].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[63].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[63].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[63].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[63].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[63].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[63].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[63].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[64].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[64].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[64].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[64].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[64].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[64].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[64].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[64].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[65].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[65].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[65].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[65].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[65].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[65].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[65].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[65].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[66].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[66].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[66].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[66].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[66].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[66].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[66].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[66].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[67].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[67].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[67].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[67].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[67].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[67].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[67].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[67].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[68].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[68].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[68].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[68].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[68].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[68].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[68].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[68].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[69].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[69].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[69].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[69].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[69].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[69].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[69].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[69].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[70].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[70].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[70].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[70].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[70].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[70].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[70].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[70].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[71].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[71].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[71].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[71].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[71].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[71].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[71].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[71].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[72].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[72].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[72].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[72].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[72].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[72].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[72].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[72].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[73].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[73].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[73].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[73].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[73].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[73].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[73].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[73].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[74].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[74].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[74].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[74].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[74].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[74].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[74].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[74].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit.dprio_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[1].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[1].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[1].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[1].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[1].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[1].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[1].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[1].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[2].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[2].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[2].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[2].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[2].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[2].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[2].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_ns_reg +CHECKSUM: "1859928551" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[2].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_ns_reg +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_wr_dma.des_ptr_fifo.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_wr_dma.des_ptr_fifo.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[0].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[0].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[0].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[0].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[1].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[1].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[1].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[1].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[2].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[2].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[2].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[2].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[3].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[3].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[3].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[3].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_rdy_to_cr.hld_data_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_rdy_to_cr.hld_data_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.hld_fifo_32.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst +CHECKSUM: "2406711859" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.hld_fifo_32.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst +CHECKSUM: "4265999236" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_freq +CHECKSUM: "4209750252" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_rdy_to_cr.reset_controller_0 +CHECKSUM: "869564193" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.m_remote_stp_csr_if +CHECKSUM: "869564193" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_csr_if +CHECKSUM: "4179443622" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.PR_IP +CHECKSUM: "1862097811" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_cr_to_rdy.reset_controller_0 +CHECKSUM: "3120118257" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xclkin_sw +CHECKSUM: "3620977630" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xbuf_ls0 +CHECKSUM: "3620977630" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xbuf_ls1 +CHECKSUM: "3620977630" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xbuf_ls2_0 +CHECKSUM: "3620977630" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xbuf_ls2_1 +CHECKSUM: "3620977630" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xbuf_ls2_2 +CHECKSUM: "3620977630" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xbuf_ls2_3 +CHECKSUM: "3620977630" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xbuf_ls2_4 +CHECKSUM: "3620977630" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xbuf_ls2_5 +CHECKSUM: "3620977630" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.x253 +CHECKSUM: "3620977630" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xbuf_ls3 +CHECKSUM: "3620977630" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xbuf_ls4 +CHECKSUM: "3620977630" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xbuf_ls5 +CHECKSUM: "3620977630" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xbuf_ls6 +CHECKSUM: "3620977630" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xbuf_ls7 +CHECKSUM: "1521101020" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only +CHECKSUM: "3735296934" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_rdy_to_cr +CHECKSUM: "3025675407" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.genblk3[0].pr_frz_hssi_ss_port +CHECKSUM: "1363256016" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst +CHECKSUM: "939390165" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.cmd_demux +CHECKSUM: "1565427362" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xclkin_sw.xclkin_mux +CHECKSUM: "3654927921" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.cmd_mux +CHECKSUM: "4250681599" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_rd_dma +CHECKSUM: "1605679508" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xncnt_iopll.xiopll_cnt +CHECKSUM: "1605679508" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xmcnt_iopll.xpm_ncnt_iopll +CHECKSUM: "1605679508" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll0.xpm_ncnt_iopll +CHECKSUM: "1605679508" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll1.xpm_ncnt_iopll +CHECKSUM: "1605679508" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll2.xpm_ncnt_iopll +CHECKSUM: "1605679508" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll3.xpm_ncnt_iopll +CHECKSUM: "1605679508" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll4.xpm_ncnt_iopll +CHECKSUM: "1605679508" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll5.xpm_ncnt_iopll +CHECKSUM: "1605679508" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll6.xpm_ncnt_iopll +CHECKSUM: "1605679508" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll7.xpm_ncnt_iopll +CHECKSUM: "1605679508" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll8.xpm_ncnt_iopll +CHECKSUM: "3391153812" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.st_dbg_ip_ip_avmm_s_rsp_width_adapter +CHECKSUM: "3640142029" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW.dcfifo_async.ASYNC.WR_FE +CHECKSUM: "3640142029" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW.dcfifo_async.ASYNC.RD_FE +CHECKSUM: "1134816394" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.jop_blaster_avmm_s_burst_adapter +CHECKSUM: "723648173" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[0].avmm_cdc_inst.avmm_cdc +CHECKSUM: "723648173" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[1].avmm_cdc_inst.avmm_cdc +CHECKSUM: "2498459360" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll_reconfig +CHECKSUM: "368946036" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xlockf +CHECKSUM: "312248075" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.host_if_m0_translator +CHECKSUM: "1304541354" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xtestmux.x13 +CHECKSUM: "4004773024" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.router_003 +CHECKSUM: "83094581" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.rsp_mux +CHECKSUM: "83094581" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.rsp_mux_001 +CHECKSUM: "2184725858" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xcoutbuf0 +CHECKSUM: "2184725858" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xcoutbuf1 +CHECKSUM: "2184725858" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xcoutbuf2 +CHECKSUM: "2184725858" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xcoutbuf3 +CHECKSUM: "3465876274" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xfpll_ctrl.xfpll_selfrst +CHECKSUM: "191805629" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0 +CHECKSUM: "1594086126" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.h2t_mem_s1_agent +CHECKSUM: "1594086126" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.t2h_mem_s1_agent +CHECKSUM: "1594086126" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.st_dbg_ip_ip_avmm_s_agent +CHECKSUM: "849780446" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.router +CHECKSUM: "1364397637" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.addr_match_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_real_stall_out.stall_out_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.real_almost_empty.almost_empty_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.addr_match_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_real_stall_out.stall_out_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.real_almost_empty.almost_empty_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.addr_match_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_real_stall_out.stall_out_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_real_stall_out.stall_out_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.real_almost_empty.almost_empty_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_wr_dma.des_ptr_fifo.genblk1.hs.acl_high_speed_fifo_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_wr_dma.des_ptr_fifo.genblk1.hs.acl_high_speed_fifo_inst.addr_match_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_wr_dma.des_ptr_fifo.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_wr_dma.des_ptr_fifo.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_wr_dma.des_ptr_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_real_stall_out.stall_out_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.addr_match_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_real_stall_out.stall_out_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.real_almost_full.almost_full_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.addr_match_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[2].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_real_stall_out.stall_out_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[2].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.real_almost_full.almost_full_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.addr_match_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.acl_reset_handler_inst +CHECKSUM: "679067000" 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+INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[0].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_real_stall_out.stall_out_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[0].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[0].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.addr_match_inst.acl_reset_handler_inst +CHECKSUM: "679067000" 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+INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[1].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[1].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_real_stall_out.stall_out_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[1].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.acl_reset_handler_inst +CHECKSUM: "679067000" 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+INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_real_stall_out.stall_out_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.addr_match_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_real_stall_out.stall_out_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_rdy_to_cr.hld_data_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_rdy_to_cr.hld_data_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.addr_match_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_rdy_to_cr.hld_data_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_rdy_to_cr.hld_data_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_rdy_to_cr.hld_data_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.real_almost_full.almost_full_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.hld_fifo_32.genblk1.hs.acl_high_speed_fifo_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.hld_fifo_32.genblk1.hs.acl_high_speed_fifo_inst.addr_match_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.hld_fifo_32.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.hld_fifo_32.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.acl_reset_handler_inst +CHECKSUM: "679067000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.hld_fifo_32.genblk1.hs.acl_high_speed_fifo_inst.gen_real_stall_out.stall_out_inst.acl_reset_handler_inst +CHECKSUM: "1878414050" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.reset_controller_0.my_altera_reset_controller.genblk1.alt_rst_sync_uq1 +CHECKSUM: "1878414050" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.reset_controller_0.my_altera_reset_controller.genblk1.alt_rst_req_sync_uq1 +CHECKSUM: "1878414050" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_rdy_to_cr.reset_controller_0.my_altera_reset_controller.genblk1.alt_rst_sync_uq1 +CHECKSUM: "1878414050" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_rdy_to_cr.reset_controller_0.my_altera_reset_controller.genblk1.alt_rst_req_sync_uq1 +CHECKSUM: "1878414050" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.reset_controller_0.my_altera_reset_controller.genblk1.alt_rst_sync_uq1 +CHECKSUM: "1878414050" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.reset_controller_0.my_altera_reset_controller.genblk1.alt_rst_req_sync_uq1 +CHECKSUM: "1878414050" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_mca.reset_controller_0.my_altera_reset_controller.genblk1.alt_rst_sync_uq1 +CHECKSUM: "1878414050" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_mca.reset_controller_0.my_altera_reset_controller.genblk1.alt_rst_req_sync_uq1 +CHECKSUM: "1878414050" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_cr_to_rdy.reset_controller_0.my_altera_reset_controller.genblk1.alt_rst_sync_uq1 +CHECKSUM: "1878414050" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_cr_to_rdy.reset_controller_0.my_altera_reset_controller.genblk1.alt_rst_req_sync_uq1 +CHECKSUM: "1878414050" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.rst_controller.genblk1.alt_rst_sync_uq1 +CHECKSUM: "1878414050" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.rst_controller.genblk1.alt_rst_req_sync_uq1 +CHECKSUM: "1878414050" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.rst_controller_001.genblk1.alt_rst_sync_uq1 +CHECKSUM: "1878414050" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.rst_controller_001.genblk1.alt_rst_req_sync_uq1 +CHECKSUM: "1878414050" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.rst_controller.genblk1.alt_rst_sync_uq1 +CHECKSUM: "1878414050" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.rst_controller.genblk1.alt_rst_req_sync_uq1 +CHECKSUM: "1878414050" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.rst_controller_001.genblk1.alt_rst_sync_uq1 +CHECKSUM: "1878414050" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.rst_controller_001.genblk1.alt_rst_req_sync_uq1 +CHECKSUM: "1878414050" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.rst_controller_002.genblk1.alt_rst_sync_uq1 +CHECKSUM: "1878414050" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.rst_controller_002.genblk1.alt_rst_req_sync_uq1 +CHECKSUM: "2906461845" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xref.xref_dig +CHECKSUM: "3374363839" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xshadow +CHECKSUM: "931667779" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.jop_blaster_avmm_s_burst_adapter.altera_merlin_burst_adapter_13_1.burst_adapter.the_burstwrap_increment +CHECKSUM: "466901962" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src +CHECKSUM: "1622589509" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.PR_IP.s10_pr_0 +CHECKSUM: "2076690712" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xvreg_0p9v0.xvreg +CHECKSUM: "2076690712" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xvreg_0p9v1.xvreg +CHECKSUM: "2678432399" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits +CHECKSUM: "2678432399" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[1].csr_reg_nbits +CHECKSUM: "2678432399" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[2].csr_reg_nbits +CHECKSUM: "2958998375" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.jop_blaster_avmm_s_burst_adapter.altera_merlin_burst_adapter_13_1.burst_adapter.the_min.ab_sub.subtract +CHECKSUM: "2958998375" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.jop_blaster_avmm_s_burst_adapter.altera_merlin_burst_adapter_13_1.burst_adapter.the_min.ac_sub.subtract +CHECKSUM: "2958998375" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.jop_blaster_avmm_s_burst_adapter.altera_merlin_burst_adapter_13_1.burst_adapter.the_min.bc_sub.subtract +CHECKSUM: "2958998375" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.jop_blaster_avmm_s_burst_adapter.altera_merlin_burst_adapter_13_1.burst_adapter.the_min.da_sub.subtract +CHECKSUM: "2958998375" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.jop_blaster_avmm_s_burst_adapter.altera_merlin_burst_adapter_13_1.burst_adapter.the_min.db_sub.subtract +CHECKSUM: "2958998375" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.jop_blaster_avmm_s_burst_adapter.altera_merlin_burst_adapter_13_1.burst_adapter.the_min.dc_sub.subtract +CHECKSUM: "1694564288" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.router_001 +CHECKSUM: "1694564288" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.router_002 +CHECKSUM: "3212033890" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.cfg_dprio_readdata_mux +CHECKSUM: "2719578593" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xvco_iopll +CHECKSUM: "4187586737" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.intel_st_dbg_if_csr +CHECKSUM: "2983509537" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xfpll_ctrl +CHECKSUM: "2647209962" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.x221 +CHECKSUM: "3626981367" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.st_dbg_ip_ip_avmm_s_cmd_width_adapter +CHECKSUM: "2204843170" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW.LOWLATENCY.eva +CHECKSUM: "748540438" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xfb.xfb_dig +CHECKSUM: "401468160" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xfb.xfb_dig_hs +CHECKSUM: "2164693073" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.avmm_bridge_m0_limiter +CHECKSUM: "3211086611" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.emif[0].pr_frz_afu_avmm_if +CHECKSUM: "3211086611" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.emif[1].pr_frz_afu_avmm_if +CHECKSUM: "177151901" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.PR_IP.s10_pr_0.s10_pr_ctrl_inst +CHECKSUM: "2051236245" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll_reconfig.iopll_reconfig_0.shift_0 +CHECKSUM: "2051236245" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll_reconfig.iopll_reconfig_0.shift_1 +CHECKSUM: "2051236245" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll_reconfig.iopll_reconfig_0.shift_2 +CHECKSUM: "2051236245" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll_reconfig.iopll_reconfig_0.shift_3 +CHECKSUM: "2345283701" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.jop_blaster_avmm_s_translator +CHECKSUM: "1632530803" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock +CHECKSUM: "2709875921" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.h2t_mem_s1_agent.uncompressor +CHECKSUM: "2709875921" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.t2h_mem_s1_agent.uncompressor +CHECKSUM: "2709875921" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.st_dbg_ip_ip_avmm_s_agent.uncompressor +CHECKSUM: "2709875921" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.st_dbg_ip_ip_avmm_s_rsp_width_adapter.genblk7.uncompressor +CHECKSUM: "2709875921" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.jop_blaster_avmm_s_agent.uncompressor +CHECKSUM: "373108365" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.jop_blaster_avmm_s_agent +CHECKSUM: "2981306564" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.pipelined_compare_gt_4 +CHECKSUM: "2981306564" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.pipelined_compare_eq_5 +CHECKSUM: "2981306564" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.pipelined_compare_eq_4 +CHECKSUM: "2981306564" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.pipelined_compare_eq_3 +CHECKSUM: "2981306564" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.pipelined_compare_eq_2 +CHECKSUM: "2981306564" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.pipelined_compare_eq_1 +CHECKSUM: "2981306564" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.pipelined_compare_eq_4 +CHECKSUM: "2981306564" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.pipelined_compare_gt4 +CHECKSUM: "2981306564" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.pipelined_compare_gt0 +CHECKSUM: "2981306564" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.pipelined_compare_eq_nonzero +CHECKSUM: "2981306564" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.pipelined_compare_eq_one +CHECKSUM: "2435155933" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW.dcfifo_async.ASYNC +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_wr_dma.des_ptr_fifo +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[0].src_fifo +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[0].snk_fifo +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[1].src_fifo +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[1].snk_fifo +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[2].src_fifo +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[2].snk_fifo +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[3].src_fifo +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[3].snk_fifo +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[0].hld_fifo_inst +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[1].hld_fifo_inst +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[2].hld_fifo_inst +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_rdy_to_cr.hld_data_fifo_inst +CHECKSUM: "2084140992" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.hld_fifo_32 +CHECKSUM: "985156884" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll_reconfig.iopll_reconfig_0 +CHECKSUM: "490828870" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[0].avmm_cdc_inst.avmm_cdc.rsp_fifo +CHECKSUM: "490828870" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[1].avmm_cdc_inst.avmm_cdc.rsp_fifo +CHECKSUM: "2104367544" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.PR_IP.s10_pr_0.s10_pr_stream_inst +CHECKSUM: "2545521084" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs +CHECKSUM: "3730150716" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.router_002 +CHECKSUM: "1581380245" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xncnt_iopll +CHECKSUM: "2078068937" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW.LOWLATENCY +CHECKSUM: "2776742179" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xpfd +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[1].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[1].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[1].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[1].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[1].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[1].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[1].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[1].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[2].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[2].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[2].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[2].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[2].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[2].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[2].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit +CHECKSUM: "850054989" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs.csr_reg_nregs[2].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit +CHECKSUM: "11117611" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_mem.the_altsyncram.altera_syncram_inst.mem +CHECKSUM: "11117611" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_mem.the_altsyncram.altera_syncram_inst.mem +CHECKSUM: "11117611" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll_reconfig.iopll_reconfig_0.altsyncram_inst.altera_syncram_inst.mem +CHECKSUM: "3387394568" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.cmd_demux +CHECKSUM: "3387394568" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.cmd_demux_001 +CHECKSUM: "3429637898" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.clock_in +CHECKSUM: "2951701883" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_2 +CHECKSUM: "1041264627" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_mca +CHECKSUM: "1129721953" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.ioplldig_dprio_arbiter_inst +CHECKSUM: "1435185811" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xibias_blk_iopll.xibias_refc +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.genblk3.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.genblk3.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.genblk3.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.genblk3.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.genblk3.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.genblk3.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_wr_dma.des_ptr_fifo.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_wr_dma.des_ptr_fifo.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[0].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[0].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[0].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.genblk2.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[0].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[1].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[1].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[1].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[1].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[2].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[2].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[2].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[2].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[3].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[3].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[3].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[3].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.genblk2.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.genblk2.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.genblk2.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.genblk2.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.genblk2.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_rdy_to_cr.hld_data_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.genblk3.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_rdy_to_cr.hld_data_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.genblk3.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.hld_fifo_32.genblk1.hs.acl_high_speed_fifo_inst.wraddr_lfsr.m20k_wraddr_inst.genblk4.lfsr_inst +CHECKSUM: "1984188521" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.hld_fifo_32.genblk1.hs.acl_high_speed_fifo_inst.rdaddr_lfsr.m20k_rdaddr_inst.genblk4.lfsr_inst +CHECKSUM: "3102614577" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h +CHECKSUM: "1485393196" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.sld_hub_controller.core.the_resp_fsm +CHECKSUM: "2777854568" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xfpll_ctrl.xfpll_selfrst.selfrst3_sync +CHECKSUM: "2777854568" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.status_reg_nregs.stat_reg_nbits[0].cfg_dprio_status_sync_regs.write_en_ack_sync_1 +CHECKSUM: "2777854568" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.status_reg_nregs.stat_reg_nbits[1].cfg_dprio_status_sync_regs.write_en_ack_sync_1 +CHECKSUM: "2777854568" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.status_reg_nregs.stat_reg_nbits[2].cfg_dprio_status_sync_regs.write_en_ack_sync_1 +CHECKSUM: "2777854568" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xshadow.shadow_status_nregs[0].cfg_dprio_shadow_status_regs.write_en_sync_1 +CHECKSUM: "2777854568" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xshadow.shadow_status_nregs[1].cfg_dprio_shadow_status_regs.write_en_sync_1 +CHECKSUM: "2777854568" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xshadow.shadow_status_nregs[2].cfg_dprio_shadow_status_regs.write_en_sync_1 +CHECKSUM: "2777854568" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.tstbus_int_sync_bit +CHECKSUM: "2766928488" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[53].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[53].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[53].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[53].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[53].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[53].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[53].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[54].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[54].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[54].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[54].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[54].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[54].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[54].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[54].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[55].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[55].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[55].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[55].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[55].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[55].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[55].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[0].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[0].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[0].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[0].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[0].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[0].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[0].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[0].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[1].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[1].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[1].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[1].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[1].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[1].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[1].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[1].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[2].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[2].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[2].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[2].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[2].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[2].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[2].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[2].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[3].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[3].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[3].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[3].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[3].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[3].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[3].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[3].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[4].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[4].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[4].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[4].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[4].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[4].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[4].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[4].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[5].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[5].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[5].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[5].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[5].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[5].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[5].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[5].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[6].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[6].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[6].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[6].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[6].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[6].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[6].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[6].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[7].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[7].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[7].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[7].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[7].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[7].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[7].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[7].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[8].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[8].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[8].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[8].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[8].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[8].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[8].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[8].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[9].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[9].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[9].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[9].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[9].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[9].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[9].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[9].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[10].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[10].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[10].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[10].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[10].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[10].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[10].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[10].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[11].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[11].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[11].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[11].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[11].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[11].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[11].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[11].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[12].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[12].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[12].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[12].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[12].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[12].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[12].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[12].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[13].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[13].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[13].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[13].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[13].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[13].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[13].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[13].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[14].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[14].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[14].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[14].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[14].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[14].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[14].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[14].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[15].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[15].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[15].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[15].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[15].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[15].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[15].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[15].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[16].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[16].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[16].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[16].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[16].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[16].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[16].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[16].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[17].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[17].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[17].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[17].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[17].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[17].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[17].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[17].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[18].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[18].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[18].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[18].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[18].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[18].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[18].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[18].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[19].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[19].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[19].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[19].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[19].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[19].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[19].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[19].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[20].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[20].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[20].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[20].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[20].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[20].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[20].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[20].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[21].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[21].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[21].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[21].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[21].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[21].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[21].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[21].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[22].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[22].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[22].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[22].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[22].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[22].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[22].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[22].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[23].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[23].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[23].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[23].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[23].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[23].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[23].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[23].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[24].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[24].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[24].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[24].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[24].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[24].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[24].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[24].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[25].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[25].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[25].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[25].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[25].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[25].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[25].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[25].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[26].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[26].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[26].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[26].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[26].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[26].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[26].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[26].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[27].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[27].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[27].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[27].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[27].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[27].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[27].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[27].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[28].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[28].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[28].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[28].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[28].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[28].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[28].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[28].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[29].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[29].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[29].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[29].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[29].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[29].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[29].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[29].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[30].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[30].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[30].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[30].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[30].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[30].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[30].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[30].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[31].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[31].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[31].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[31].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[31].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[31].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[31].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[31].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[32].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[32].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[32].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[32].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[32].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[32].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[32].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[32].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[33].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[33].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[33].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[33].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[33].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[33].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[33].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[33].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[34].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[34].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[34].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[34].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[34].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[34].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[34].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[34].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[35].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[35].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[35].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[35].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[35].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[35].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[35].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[35].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[36].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[36].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[36].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[36].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[36].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[36].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[36].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[36].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[37].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[37].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[37].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[37].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[37].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[37].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[37].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[37].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[38].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[38].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[38].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[38].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[38].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[38].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[38].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[38].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[39].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[39].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[39].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[39].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[39].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[39].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[39].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[39].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[40].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[40].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[40].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[40].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[40].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[40].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[40].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[40].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[41].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[41].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[41].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[41].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[41].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[41].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[41].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[41].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[42].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[42].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[42].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[42].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[42].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[42].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[42].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[42].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[43].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[43].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[43].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[43].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[43].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[43].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[43].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[43].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[44].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[44].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[44].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[44].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[44].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[44].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[44].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[44].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[45].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[45].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[45].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[45].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[45].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[45].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[45].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[45].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[46].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[46].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[46].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[46].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[46].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[46].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[46].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[46].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[47].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[47].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[47].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[47].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[47].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[47].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[47].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[47].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[48].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[48].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[48].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[48].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[48].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[48].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[48].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[48].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[49].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[49].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[49].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[49].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[49].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[49].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[49].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[49].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[50].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[50].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[50].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[50].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[50].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[50].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[50].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[50].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[51].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[51].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[51].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[51].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[51].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[51].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[51].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[51].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[52].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[52].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[52].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[52].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[52].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[52].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[52].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[52].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[53].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[55].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[56].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[56].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[56].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[56].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[56].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[56].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[56].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[56].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[57].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[57].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[57].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[57].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[57].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[57].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[57].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[57].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[58].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[58].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[58].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[58].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[58].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[58].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[58].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[58].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[59].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[59].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[59].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[59].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[59].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[59].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[59].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[59].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[60].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[60].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[60].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[60].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[60].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[60].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[60].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[60].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[61].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[61].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[61].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[61].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[61].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[61].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[61].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[61].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[62].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[62].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[62].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[62].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[62].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[62].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[62].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[62].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[63].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[63].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[63].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[63].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[63].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[63].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[63].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[63].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[64].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[64].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[64].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[64].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[64].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[64].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[64].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[64].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[65].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[65].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[65].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[65].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[65].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[65].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[65].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[65].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[66].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[66].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[66].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[66].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[66].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[66].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[66].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[66].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[67].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[67].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[67].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[67].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[67].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[67].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[67].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[67].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[68].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[68].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[68].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[68].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[68].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[68].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[68].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[68].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[69].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[69].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[69].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[69].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[69].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[69].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[69].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[69].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[70].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[70].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[70].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[70].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[70].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[70].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[70].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[70].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[71].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[71].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[71].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[71].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[71].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[71].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[71].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[71].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[72].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[72].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[72].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[72].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[72].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[72].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[72].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[72].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[73].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[73].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[73].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[73].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[73].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[73].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[73].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[73].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[74].ctrl_reg_nbits.ctrl_reg_bit[0].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[74].ctrl_reg_nbits.ctrl_reg_bit[1].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[74].ctrl_reg_nbits.ctrl_reg_bit[2].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[74].ctrl_reg_nbits.ctrl_reg_bit[3].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[74].ctrl_reg_nbits.ctrl_reg_bit[4].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[74].ctrl_reg_nbits.ctrl_reg_bit[5].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[74].ctrl_reg_nbits.ctrl_reg_bit[6].ctrl_reg_bit +CHECKSUM: "2680538708" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[74].ctrl_reg_nbits.ctrl_reg_bit[7].ctrl_reg_bit +CHECKSUM: "4052506047" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pg_csr_inst.fme_id_rom +CHECKSUM: "2430403158" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.crosser.clock_xer +CHECKSUM: "2430403158" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.crosser_001.clock_xer +CHECKSUM: "2430403158" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.crosser_002.clock_xer +CHECKSUM: "2430403158" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.crosser_003.clock_xer +CHECKSUM: "625632385" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_rcfg_fsm +CHECKSUM: "3412084000" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0 +CHECKSUM: "2648583793" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0 +CHECKSUM: "268032114" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xmcnt_iopll.xpm_phmux_iopll +CHECKSUM: "268032114" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll0.xpm_phmux_iopll +CHECKSUM: "268032114" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll1.xpm_phmux_iopll +CHECKSUM: "268032114" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll2.xpm_phmux_iopll +CHECKSUM: "268032114" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll3.xpm_phmux_iopll +CHECKSUM: "268032114" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll4.xpm_phmux_iopll +CHECKSUM: "268032114" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll5.xpm_phmux_iopll +CHECKSUM: "268032114" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll6.xpm_phmux_iopll +CHECKSUM: "268032114" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll7.xpm_phmux_iopll +CHECKSUM: "268032114" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll8.xpm_phmux_iopll +CHECKSUM: "2676968162" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xlockdet +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.genblk3[0].hssi_pr_freeze_rst_n.resync_chains[0].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.genblk3[0].hssi_pr_freeze_resync_inst.resync_chains[0].genblk1.synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.crosser.clock_xer.in_to_out_synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.crosser.clock_xer.out_to_in_synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.crosser_001.clock_xer.in_to_out_synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.crosser_001.clock_xer.out_to_in_synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.crosser_002.clock_xer.in_to_out_synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.crosser_002.clock_xer.out_to_in_synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.crosser_003.clock_xer.in_to_out_synchronizer +CHECKSUM: "809561450" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.crosser_003.clock_xer.out_to_in_synchronizer +CHECKSUM: "809561450" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll_reconfig.iopll_reconfig_0.altera_std_synchronizer_inst +CHECKSUM: "809561450" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll_reconfig.iopll_reconfig_0.altera_std_synchronizer_inst_2 +CHECKSUM: "3489340793" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.router_003.the_default_decode +CHECKSUM: "2276763156" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.router.the_default_decode +CHECKSUM: "2276763156" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.router_001.the_default_decode +CHECKSUM: "1515437579" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.reset_controller_0 +CHECKSUM: "1288042903" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst +CHECKSUM: "2274420169" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.genblk3[0].pr_frz_hssi_ss_port.pr_frz_mx2fn_hssi_port +CHECKSUM: "1237406075" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo +CHECKSUM: "4268832638" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xvco_cal +CHECKSUM: "1013531185" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_endianness +CHECKSUM: "552739243" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_endianness +CHECKSUM: "1047009842" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_1 +CHECKSUM: "2564205526" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.sld_hub_controller.core.tdo_enable_fifo +CHECKSUM: "266563707" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip +CHECKSUM: "630983284" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.MEM_CH[0].avmm_bridge_inst.avmm_pipeline_bridge +CHECKSUM: "630983284" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.MEM_CH[1].avmm_bridge_inst.avmm_pipeline_bridge +CHECKSUM: "1312041587" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.jop_blaster_avmm_s_agent_rsp_fifo +CHECKSUM: "1312041587" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.jop_blaster_avmm_s_agent_rdata_fifo +CHECKSUM: "3785487976" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll +CHECKSUM: "2058486622" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xfine_dly_n.xfdly +CHECKSUM: "2058486622" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xmcnt_iopll.xpm_fine_dly +CHECKSUM: "2058486622" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll0.xpm_fine_dly +CHECKSUM: "2058486622" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll1.xpm_fine_dly +CHECKSUM: "2058486622" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll2.xpm_fine_dly +CHECKSUM: "2058486622" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll3.xpm_fine_dly +CHECKSUM: "2058486622" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll4.xpm_fine_dly +CHECKSUM: "2058486622" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll5.xpm_fine_dly +CHECKSUM: "2058486622" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll6.xpm_fine_dly +CHECKSUM: "2058486622" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll7.xpm_fine_dly +CHECKSUM: "2058486622" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll8.xpm_fine_dly +CHECKSUM: "2058486622" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xfine_dly_0.xfdly +CHECKSUM: "2058486622" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xfine_dly_1.xfdly +CHECKSUM: "2058486622" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xfine_dly_2.xfdly +CHECKSUM: "2058486622" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xfine_dly_3.xfdly +CHECKSUM: "1311232317" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll +CHECKSUM: "4166040586" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pg_csr_inst.fme_id_rom.rom_1port_0 +CHECKSUM: "2725671737" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.emif[0].ddr4_pr_freeze_sync +CHECKSUM: "2725671737" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.emif[1].ddr4_pr_freeze_sync +CHECKSUM: "2725671737" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.genblk3[0].hssi_pr_freeze_rst_n +CHECKSUM: "2725671737" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.genblk3[0].hssi_pr_freeze_resync_inst +CHECKSUM: "2725671737" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.remotestp_status_sync +CHECKSUM: "2725671737" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.resync.csr_to_qph_sync.ena_strb.sr +CHECKSUM: "2725671737" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.resync.csr_to_qph_sync.ack_strb.sr +CHECKSUM: "2725671737" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.resync.qph_to_csr_sync.ena_strb.sr +CHECKSUM: "2725671737" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.resync.qph_to_csr_sync.ack_strb.sr +CHECKSUM: "2725671737" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_locked_resync +CHECKSUM: "3625705236" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_mem +CHECKSUM: "1593343932" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.router +CHECKSUM: "1593343932" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.router_001 +CHECKSUM: "3849196286" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.cmd_mux +CHECKSUM: "3849196286" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.cmd_mux_001 +CHECKSUM: "3849196286" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.cmd_mux_002 +CHECKSUM: "1871588399" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_mem +CHECKSUM: "231095476" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.sld_hub_controller.core +CHECKSUM: "3680525604" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xfpll_ctrl.xfpll_selfrst.pllrefclk_lock_clkgate +CHECKSUM: "3224954320" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_mem.the_altsyncram +CHECKSUM: "3224954320" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_mem.the_altsyncram +CHECKSUM: "3224954320" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll_reconfig.iopll_reconfig_0.altsyncram_inst +CHECKSUM: "3937263212" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.rsp_mux.arb +CHECKSUM: "3937263212" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.cmd_mux.arb +CHECKSUM: "2643833594" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.avmm_bridge_m0_agent +CHECKSUM: "179687198" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xtestmux +CHECKSUM: "1940521540" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.sys_clk +CHECKSUM: "2899763949" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdynamic +CHECKSUM: "2236060187" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.avalon_st_adapter.channel_adapter_0 +CHECKSUM: "465197913" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xmcnt_iopll +CHECKSUM: "465197913" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll0 +CHECKSUM: "465197913" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll1 +CHECKSUM: "465197913" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll2 +CHECKSUM: "465197913" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll3 +CHECKSUM: "465197913" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll4 +CHECKSUM: "465197913" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll5 +CHECKSUM: "465197913" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll6 +CHECKSUM: "465197913" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll7 +CHECKSUM: "465197913" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xccnt_iopll8 +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[0].avmm_cdc_inst.avmm_cdc.cmd_fifo.my_altera_avalon_dc_fifo_cmd_fifo.altera_syncram_component +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[0].avmm_cdc_inst.avmm_cdc.rsp_fifo.my_altera_avalon_dc_fifo_rsp_fifo.altera_syncram_component +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[1].avmm_cdc_inst.avmm_cdc.cmd_fifo.my_altera_avalon_dc_fifo_cmd_fifo.altera_syncram_component +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[1].avmm_cdc_inst.avmm_cdc.rsp_fifo.my_altera_avalon_dc_fifo_rsp_fifo.altera_syncram_component +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pg_csr_inst.fme_id_rom.rom_1port_0.altera_syncram_component +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_wr_dma.des_ptr_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[0].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[0].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[1].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[1].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[2].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[2].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[3].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[3].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_rdy_to_cr.hld_data_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst +CHECKSUM: "3572029108" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.hld_fifo_32.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst +CHECKSUM: "3867284221" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xclkin_sw.xclkin_mux.xmux0 +CHECKSUM: "3867284221" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xclkin_sw.xclkin_mux.xmux1 +CHECKSUM: "1057049437" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.mbn0 +CHECKSUM: "3319682098" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.avmm_bridge +CHECKSUM: "114691403" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.host_if_m0_agent.genblk3.align_address_to_size +CHECKSUM: "114691403" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.jop_blaster_avmm_s_burst_adapter.altera_merlin_burst_adapter_13_1.burst_adapter.align_address_to_size +CHECKSUM: "3721733451" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll +CHECKSUM: "2401798681" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.hssi_afu_fc[0] +CHECKSUM: "2401798681" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.genblk3[0].pr_frz_hssi_ss_port.hssi_frz2port_fc +CHECKSUM: "417648577" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.rsp_mux +CHECKSUM: "1016217597" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xtestmux.x13.xclklossdet0 +CHECKSUM: "1944445801" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_fn2mx_b_port +CHECKSUM: "1944445801" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_mx2fn_b_port +CHECKSUM: "1944445801" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_fn2mx_b_port +CHECKSUM: "1944445801" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_mx2fn_b_port +CHECKSUM: "1948657568" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.sld_hub_controller.core.tdo_enable_fifo.el0 +CHECKSUM: "1948657568" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.sld_hub_controller.core.tdo_enable_fifo.el1 +CHECKSUM: "3548810037" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xvreg_0p9v0 +CHECKSUM: "3548810037" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xvreg_0p9v1 +CHECKSUM: "3673976300" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xio_clkgatelatch_cellsync0 +CHECKSUM: "3673976300" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.ioplldig_dprio_arbiter_inst.xio_clkgatelatch_cellsync +CHECKSUM: "2998850266" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.PR_IP.s10_pr_0.config_stream_endpoint_inst +CHECKSUM: "3499209036" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.host_if_m0_agent +CHECKSUM: "3258744020" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.dps_pulse_gen_fourteennm_iopll_inst +CHECKSUM: "2966939740" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_cr_to_rdy +CHECKSUM: "3995845929" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xchgpmplf_iopll +CHECKSUM: "1287884272" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.router_001.the_default_decode +CHECKSUM: "1287884272" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.router_002.the_default_decode +CHECKSUM: "482997955" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.jop_blaster_avmm_s_burst_adapter.altera_merlin_burst_adapter_13_1.burst_adapter +CHECKSUM: "4135327237" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst +CHECKSUM: "4135327237" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst +CHECKSUM: "4135327237" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst +CHECKSUM: "4135327237" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_wr_dma.des_ptr_fifo.genblk1.hs.acl_high_speed_fifo_inst +CHECKSUM: "4135327237" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst +CHECKSUM: "4135327237" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst +CHECKSUM: "4135327237" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst +CHECKSUM: "4135327237" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[0].src_fifo.genblk1.hs.acl_high_speed_fifo_inst +CHECKSUM: "4135327237" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[0].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst +CHECKSUM: "4135327237" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[1].src_fifo.genblk1.hs.acl_high_speed_fifo_inst +CHECKSUM: "4135327237" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[1].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst +CHECKSUM: "4135327237" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[2].src_fifo.genblk1.hs.acl_high_speed_fifo_inst +CHECKSUM: "4135327237" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[2].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst +CHECKSUM: "4135327237" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[3].src_fifo.genblk1.hs.acl_high_speed_fifo_inst +CHECKSUM: "4135327237" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[3].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst +CHECKSUM: "4135327237" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst +CHECKSUM: "4135327237" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst +CHECKSUM: "4135327237" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst +CHECKSUM: "4135327237" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_rdy_to_cr.hld_data_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst +CHECKSUM: "4135327237" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.hld_fifo_32.genblk1.hs.acl_high_speed_fifo_inst +CHECKSUM: "2483535075" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xfpll_ctrl.xfpll_ctrl_cnt +CHECKSUM: "2468343982" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_wr_dma +CHECKSUM: "517801317" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.router.the_default_decode +CHECKSUM: "2999484643" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core +CHECKSUM: "4173487581" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0 +CHECKSUM: "3339211258" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.rsp_mux.arb.adder +CHECKSUM: "3339211258" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.cmd_mux.arb.adder +CHECKSUM: "2921017544" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xpllcoutbuf8 +CHECKSUM: "2921017544" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xpllcoutbuf7 +CHECKSUM: "2921017544" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xpllcoutbuf6 +CHECKSUM: "2921017544" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xpllcoutbuf5 +CHECKSUM: "2921017544" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xpllcoutbuf4 +CHECKSUM: "2921017544" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xpllcoutbuf3 +CHECKSUM: "2921017544" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xpllcoutbuf2 +CHECKSUM: "2921017544" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xpllcoutbuf1 +CHECKSUM: "2921017544" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xpllcoutbuf0 +CHECKSUM: "766516227" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xiotest0_clkmux_cellsyn2 +CHECKSUM: "766516227" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xiotest1_clkmux_cellsyn2 +CHECKSUM: "766516227" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xiotest2_clkmux_cellsyn2 +CHECKSUM: "766516227" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xio_clkmux_cellsyn2 +CHECKSUM: "766516227" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.ioplldig_dprio_arbiter_inst.xio_clkmux_cellsyn00 +CHECKSUM: "766516227" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.ioplldig_dprio_arbiter_inst.xio_clkmux_cellsyn0 +CHECKSUM: "766516227" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.ioplldig_dprio_arbiter_inst.xio_clkmux_cellsyn1 +CHECKSUM: "766516227" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.ioplldig_dprio_arbiter_inst.xio_clkmux_cellsyn2 +CHECKSUM: "766516227" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.ioplldig_dprio_arbiter_inst.xio_clkmux_cellsyn3 +CHECKSUM: "766516227" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.ioplldig_dprio_arbiter_inst.xio_clkmux_cellsyn4 +CHECKSUM: "766516227" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.ioplldig_dprio_arbiter_inst.xio_clkmux_cellsyn5 +CHECKSUM: "3468691583" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk +CHECKSUM: "732497648" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.st_dbg_ip_ip_avmm_s_burst_adapter +CHECKSUM: "3531400438" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n +CHECKSUM: "948708616" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.status_reg_nregs.stat_reg_nbits[0].cfg_dprio_status_reg_nbits +CHECKSUM: "948708616" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.status_reg_nregs.stat_reg_nbits[1].cfg_dprio_status_reg_nbits +CHECKSUM: "948708616" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.status_reg_nregs.stat_reg_nbits[2].cfg_dprio_status_reg_nbits +CHECKSUM: "3516772677" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[0].avmm_cdc_inst.avmm_cdc.cmd_fifo.my_altera_avalon_dc_fifo_cmd_fifo.write_crosser +CHECKSUM: "3516772677" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[0].avmm_cdc_inst.avmm_cdc.cmd_fifo.my_altera_avalon_dc_fifo_cmd_fifo.read_crosser +CHECKSUM: "3516772677" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[0].avmm_cdc_inst.avmm_cdc.rsp_fifo.my_altera_avalon_dc_fifo_rsp_fifo.write_crosser +CHECKSUM: "3516772677" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[0].avmm_cdc_inst.avmm_cdc.rsp_fifo.my_altera_avalon_dc_fifo_rsp_fifo.read_crosser +CHECKSUM: "3516772677" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[1].avmm_cdc_inst.avmm_cdc.cmd_fifo.my_altera_avalon_dc_fifo_cmd_fifo.write_crosser +CHECKSUM: "3516772677" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[1].avmm_cdc_inst.avmm_cdc.cmd_fifo.my_altera_avalon_dc_fifo_cmd_fifo.read_crosser +CHECKSUM: "3516772677" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[1].avmm_cdc_inst.avmm_cdc.rsp_fifo.my_altera_avalon_dc_fifo_rsp_fifo.write_crosser +CHECKSUM: "3516772677" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[1].avmm_cdc_inst.avmm_cdc.rsp_fifo.my_altera_avalon_dc_fifo_rsp_fifo.read_crosser +CHECKSUM: "1110541301" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.sld_hub_controller.core.the_csr_slave +CHECKSUM: "2998783951" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.rsp_demux +CHECKSUM: "2998783951" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.rsp_demux_001 +CHECKSUM: "2998783951" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.rsp_demux_002 +CHECKSUM: "2402049597" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.s_remote_stp_csr_if +CHECKSUM: "1259019545" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_fn2mx_b_port.r.axis_pl_stage[0].axis_reg_inst +CHECKSUM: "1259019545" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_mx2fn_b_port.r.axis_pl_stage[0].axis_reg_inst +CHECKSUM: "1259019545" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_fn2mx_b_port.r.axis_pl_stage[0].axis_reg_inst +CHECKSUM: "1259019545" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_mx2fn_b_port.r.axis_pl_stage[0].axis_reg_inst +CHECKSUM: "1259019545" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.genblk3[0].pr_frz_hssi_ss_port.pr_frz_mx2fn_hssi_port.axis_pl_stage[0].axis_reg_inst +CHECKSUM: "3602032500" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.ioplldig_dprio_uc_read_inst +CHECKSUM: "3720418767" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.avalon_st_adapter_001.channel_adapter_0 +CHECKSUM: "1737242610" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xextclk0 +CHECKSUM: "1737242610" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xextclk1 +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[0].avmm_cdc_inst.avmm_cdc.cmd_fifo.my_altera_avalon_dc_fifo_cmd_fifo.altera_syncram_component.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[0].avmm_cdc_inst.avmm_cdc.rsp_fifo.my_altera_avalon_dc_fifo_rsp_fifo.altera_syncram_component.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[1].avmm_cdc_inst.avmm_cdc.cmd_fifo.my_altera_avalon_dc_fifo_cmd_fifo.altera_syncram_component.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[1].avmm_cdc_inst.avmm_cdc.rsp_fifo.my_altera_avalon_dc_fifo_rsp_fifo.altera_syncram_component.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pg_csr_inst.fme_id_rom.rom_1port_0.altera_syncram_component.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_wr_dma.des_ptr_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[0].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[0].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[1].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[1].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[2].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[2].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[3].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[3].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_rdy_to_cr.hld_data_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst.mem +CHECKSUM: "1856983264" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.hld_fifo_32.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped.genblk2.genblk1.genblk1.genblk1.genblk1.altera_syncram_inst.mem +CHECKSUM: "1664533546" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.router_002.the_default_decode +CHECKSUM: "480407761" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.single_csr_chain.csr_reg_nregs +CHECKSUM: "2105066374" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.genblk3[0].pr_frz_hssi_ss_port.hssi_frz2port_ss_st_tx +CHECKSUM: "2105066374" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.genblk3[0].pr_frz_hssi_ss_port.pr_frz_mx2fn_hssi_port.axis_pl[0] +CHECKSUM: "2105066374" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.genblk3[0].pr_frz_hssi_ss_port.pr_frz_mx2fn_hssi_port.axis_pl[1] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_fn2mx_b_port.r.axis_pl[0] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.axi_tx_b_if_t0[0] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.axi_tx_b_if_t0[1] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.axi_tx_b_if_t1[0] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.axi_tx_b_if_t1[1] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_b_if_t0[0] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_b_if_t0[1] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_b_if_t1[0] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_b_if_t1[1] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_fn2mx_b_port.r.axis_pl[1] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_mx2fn_b_port.r.axis_pl[0] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_mx2fn_b_port.r.axis_pl[1] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_fn2mx_b_port.r.axis_pl[0] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_fn2mx_b_port.r.axis_pl[1] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_mx2fn_b_port.r.axis_pl[0] +CHECKSUM: "2277721912" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_mx2fn_b_port.r.axis_pl[1] +CHECKSUM: "3592500593" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.PR_IP.s10_pr_0.config_stream_endpoint_inst.inst +CHECKSUM: "2326896669" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_mca.reset_controller_0 +CHECKSUM: "4182766142" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.reset_controller_0 +CHECKSUM: "3480793069" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xclkin_sw.xpm_pll_so +CHECKSUM: "1198972895" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.avalon_st_adapter +CHECKSUM: "1391475479" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.mm_interconnect_0.jop_blaster_avmm_s_burst_adapter.altera_merlin_burst_adapter_13_1.burst_adapter.the_min +CHECKSUM: "224520764" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[51].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[52].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[53].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[0].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[1].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[2].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[3].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[4].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[5].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[6].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[7].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[8].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[9].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[10].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[11].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[12].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[13].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[14].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[15].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[16].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[17].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[18].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[19].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[20].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[21].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[22].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[23].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[24].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[25].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[26].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[27].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[28].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[29].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[62].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[30].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[31].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[32].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[33].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[34].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[35].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[36].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[37].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[38].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[39].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[40].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[41].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[42].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[43].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[44].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[45].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[46].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[47].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[48].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[49].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[50].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[54].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[55].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[56].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[57].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[58].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[59].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[60].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[61].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[63].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[64].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[65].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[66].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[67].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[68].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[69].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[70].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[71].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[72].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[73].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_select[74].ctrl_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.status_select[0].status_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.status_select[1].status_select_i +CHECKSUM: "2693343167" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.status_select[2].status_select_i +CHECKSUM: "4080229002" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.addr_match_inst +CHECKSUM: "4080229002" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_real_stall_out.stall_out_inst +CHECKSUM: "4080229002" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.real_almost_empty.almost_empty_inst +CHECKSUM: "4080229002" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.addr_match_inst +CHECKSUM: "4080229002" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_real_stall_out.stall_out_inst +CHECKSUM: "4080229002" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.real_almost_empty.almost_empty_inst +CHECKSUM: "4080229002" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.addr_match_inst +CHECKSUM: "4080229002" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_real_stall_out.stall_out_inst +CHECKSUM: "4080229002" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_src.hld_fifo.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.real_almost_empty.almost_empty_inst +CHECKSUM: "4080229002" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_wr_dma.des_ptr_fifo.genblk1.hs.acl_high_speed_fifo_inst.addr_match_inst +CHECKSUM: "4080229002" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_wr_dma.des_ptr_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_real_stall_out.stall_out_inst +CHECKSUM: "4080229002" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.addr_match_inst +CHECKSUM: "4080229002" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk.hld_fifo.genblk1.gen_slices[0].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_real_stall_out.stall_out_inst +CHECKSUM: "4080229002" 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"4080229002" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[1].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_real_stall_out.stall_out_inst +CHECKSUM: "4080229002" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[1].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.addr_match_inst +CHECKSUM: "4080229002" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[1].snk_fifo.genblk1.hs.acl_high_speed_fifo_inst.gen_real_stall_out.stall_out_inst +CHECKSUM: "4080229002" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.DESCRIPTOR_FIFOS[2].src_fifo.genblk1.hs.acl_high_speed_fifo_inst.addr_match_inst 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+INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[1].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped +CHECKSUM: "2393816311" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.Uacl_sc_fifo_data.genblk1.gen_slices[2].hld_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped +CHECKSUM: "2393816311" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_rdy_to_cr.hld_data_fifo_inst.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped +CHECKSUM: "2393816311" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.hld_fifo_32.genblk1.hs.acl_high_speed_fifo_inst.gen_ram.altera_syncram_wrapped +CHECKSUM: "4280551540" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster +CHECKSUM: "393161843" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.st_dbg_ip_ip_avmm_s_burst_adapter.altera_merlin_burst_adapter_uncompressed_only.burst_adapter +CHECKSUM: "4030212358" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.status_reg_nregs.stat_reg_nbits[0].cfg_dprio_status_sync_regs +CHECKSUM: "4030212358" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.status_reg_nregs.stat_reg_nbits[1].cfg_dprio_status_sync_regs +CHECKSUM: "4030212358" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.status_reg_nregs.stat_reg_nbits[2].cfg_dprio_status_sync_regs +CHECKSUM: "3233919499" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_w2n.reset_controller_0.my_altera_reset_controller +CHECKSUM: "3233919499" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.h2t_rdy_to_cr.reset_controller_0.my_altera_reset_controller +CHECKSUM: "3233919499" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_n2w.reset_controller_0.my_altera_reset_controller +CHECKSUM: "3233919499" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_mca.reset_controller_0.my_altera_reset_controller +CHECKSUM: "3233919499" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.t2h_cr_to_rdy.reset_controller_0.my_altera_reset_controller +CHECKSUM: "3233919499" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.rst_controller +CHECKSUM: "3233919499" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.rst_controller_001 +CHECKSUM: "3233919499" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.rst_controller +CHECKSUM: "3233919499" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.rst_controller_001 +CHECKSUM: "3233919499" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.rst_controller_002 +CHECKSUM: "2892752744" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW.LOWLATENCY.DP_WS_DGRP +CHECKSUM: "2892752744" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW.LOWLATENCY.DP_RS_DGWP +CHECKSUM: "2892752744" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW.LOWLATENCY.DP_RDUSEDW +CHECKSUM: "2892752744" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW.LOWLATENCY.DP_WRUSEDW +CHECKSUM: "2892752744" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW.dcfifo_async.ASYNC.DP_RDPTR_D +CHECKSUM: "2892752744" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW.dcfifo_async.ASYNC.DP_WRPTR_D +CHECKSUM: "2892752744" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW.dcfifo_async.ASYNC.DP_WS_NBRP +CHECKSUM: "2892752744" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW.dcfifo_async.ASYNC.DP_RS_NBWP +CHECKSUM: "2892752744" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW.dcfifo_async.ASYNC.DP_WS_DBRP +CHECKSUM: "2892752744" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW.dcfifo_async.ASYNC.DP_RS_DBWP +CHECKSUM: "2892752744" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW.dcfifo_async.ASYNC.DP_WRUSEDW +CHECKSUM: "2892752744" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW.dcfifo_async.ASYNC.DP_RDUSEDW +CHECKSUM: "2892752744" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW.dcfifo_async.ASYNC.DP_WR_DBUW +CHECKSUM: "2892752744" +ANNOTATION: " PR FLOw is not performed at top level. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_ctrl.inst_pr_async_fifo.dcfifo_component.DCFIFO_MW.dcfifo_async.ASYNC.DP_RD_DBUW +CHECKSUM: "3139278599" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.h2t_mem_s1_translator +CHECKSUM: "3139278599" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.t2h_mem_s1_translator +CHECKSUM: "3139278599" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_0.st_dbg_ip_ip_avmm_s_translator +CHECKSUM: "3139278599" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_1.h2t_mem_s2_translator +CHECKSUM: "3139278599" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.mm_interconnect_2.t2h_mem_s2_translator +CHECKSUM: "2841503598" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xshadow.shadow_status_nregs[0].cfg_dprio_shadow_status_regs +CHECKSUM: "2841503598" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xshadow.shadow_status_nregs[1].cfg_dprio_shadow_status_regs +CHECKSUM: "2841503598" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xshadow.shadow_status_nregs[2].cfg_dprio_shadow_status_regs +CHECKSUM: "3827536215" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[0].avmm_cdc_inst.avmm_cdc.cmd_fifo.my_altera_avalon_dc_fifo_cmd_fifo +CHECKSUM: "3827536215" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[0].avmm_cdc_inst.avmm_cdc.rsp_fifo.my_altera_avalon_dc_fifo_rsp_fifo +CHECKSUM: "3827536215" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[1].avmm_cdc_inst.avmm_cdc.cmd_fifo.my_altera_avalon_dc_fifo_cmd_fifo +CHECKSUM: "3827536215" +INSTANCE:tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.CH[1].avmm_cdc_inst.avmm_cdc.rsp_fifo.my_altera_avalon_dc_fifo_rsp_fifo +CHECKSUM: "3911171965" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.avalon_st_adapter.data_format_adapter_0 +CHECKSUM: "2416356986" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.jop_blaster.jop_blaster.st_dbg_ip.dma_wrapper_h2t_t2h.intel_st_dbg_if_snk +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[54].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[55].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[56].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[0].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[1].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[2].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[3].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[4].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[5].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[6].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[7].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[8].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[9].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[10].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[11].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[12].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[13].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[14].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[15].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[16].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[17].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[18].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[19].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[20].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[21].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[22].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[23].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[24].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[25].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[26].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[27].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[28].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[29].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[30].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[31].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[32].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[65].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[33].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[34].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[35].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[36].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[37].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[38].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[39].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[40].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[41].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[42].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[43].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[44].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[45].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[46].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[47].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[48].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[49].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[50].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[51].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[52].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[53].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[57].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[58].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[59].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[60].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[61].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[62].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[63].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[64].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[66].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[67].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[68].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[69].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[70].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[71].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[72].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[73].ctrl_reg_nbits +CHECKSUM: "1212776321" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xdprio_dps_iopll.xdprio.ctrl_stat_reg_chnl.ctrl_reg_nregs.ctrl_reg_nbits[74].ctrl_reg_nbits +CHECKSUM: "2105996586" +INSTANCE:tb_top.DUT.afu_top.port_gasket.remote_stp_top_inst.remote_debug_jtag_only.host_if.host_if +CHECKSUM: "2675160066" +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk.qph_user_clk_iopll.iopll_0.stratix10_altera_iopll_i.s10_iopll.fourteennm_pll.genblk1.inst.i0.xiopll_core.xibias_blk_iopll +CHECKSUM: "3634243260" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.resync.csr_to_qph_sync.ena_strb +CHECKSUM: "3634243260" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.resync.csr_to_qph_sync.ack_strb +CHECKSUM: "3634243260" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.resync.qph_to_csr_sync.ena_strb +CHECKSUM: "3634243260" +ANNOTATION: " Sim coverage is not be needed as Remote STP feature is mainly being validated in HW. " +INSTANCE:tb_top.DUT.afu_top.port_gasket.user_clock.resync.qph_to_csr_sync.ack_strb +CHECKSUM: "2100166288 3999080949" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.req_q.genblk1.scfifo_component +Toggle eccstatus "net eccstatus[1:0]" +CHECKSUM: "2100166288 623959126" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.RSP_Q[0].rsp_q.genblk1.scfifo_component +Toggle eccstatus "net eccstatus[1:0]" +CHECKSUM: "2100166288 623959126" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.RSP_Q[1].rsp_q.genblk1.scfifo_component +Toggle eccstatus "net eccstatus[1:0]" +CHECKSUM: "509893243 2671631820" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_ctrl +Fsm pr_control_state "929146028" +Fsm pr_reset_state "338956497" +CHECKSUM: "599439132 1849783068" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.req_q +ANNOTATION: " Quartus fifo- need not be generated " +Branch 0 "233563799" "(!Resetb)" (2) "(!Resetb) 0,((fifo_wen & (!fifo_ren)) & full) " +ANNOTATION: " Quartus fifo- need not be generated " +Branch 0 "233563799" "(!Resetb)" (1) "(!Resetb) 0,(fifo_ren & (fifo_count == 4'b0)) " +CHECKSUM: "599439132 1559097988" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.req_mdata_q +ANNOTATION: " Quartus fifo- need not be generated " +Branch 0 "3058795487" "(!Resetb)" (2) "(!Resetb) 0,((fifo_wen & (!fifo_ren)) & full) " +ANNOTATION: " Quartus fifo- need not be generated " +Branch 0 "3058795487" "(!Resetb)" (1) "(!Resetb) 0,(fifo_ren & (fifo_count == 7'b0)) " +CHECKSUM: "599439132 1299608076" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.RSP_Q[0].rsp_q +ANNOTATION: " Quartus fifo- need not be generated " +Branch 0 "595110794" "(!Resetb)" (2) "(!Resetb) 0,((fifo_wen & (!fifo_ren)) & full) " +ANNOTATION: " Quartus fifo- need not be generated " +Branch 0 "595110794" "(!Resetb)" (1) "(!Resetb) 0,(fifo_ren & (fifo_count == 6'b0)) " +CHECKSUM: "599439132 1299608076" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.RSP_Q[1].rsp_q +ANNOTATION: " Quartus fifo- need not be generated " +Branch 0 "595110794" "(!Resetb)" (2) "(!Resetb) 0,((fifo_wen & (!fifo_ren)) & full) " +ANNOTATION: " Quartus fifo- need not be generated " +Branch 0 "595110794" "(!Resetb)" (1) "(!Resetb) 0,(fifo_ren & (fifo_count == 6'b0)) " +CHECKSUM: "1621989688 963234123" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst +Toggle 0to1 o_he_readdata_T0 [575] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [575] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [512] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [512] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [513] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [513] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [514] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [514] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [515] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [515] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [516] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [516] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [517] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [517] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [518] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [518] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [519] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [519] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [520] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [520] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [521] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [521] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [522] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [522] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [523] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [523] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [524] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [524] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [525] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [525] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [526] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [526] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [527] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [527] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [528] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [528] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [529] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [529] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [530] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [530] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [531] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [531] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [532] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [532] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [533] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [533] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [534] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [534] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [535] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [535] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [536] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [536] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [537] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [537] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [538] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [538] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [539] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [539] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [540] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [540] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [541] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [541] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [542] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [542] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [543] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [543] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [544] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [544] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [545] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [545] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [546] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [546] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [547] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [547] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [548] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [548] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [549] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [549] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [550] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [550] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [551] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [551] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [552] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [552] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [553] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [553] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [554] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [554] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [555] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [555] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [556] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [556] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [557] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [557] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [558] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [558] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [559] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [559] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [560] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [560] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [561] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [561] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [562] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [562] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [563] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [563] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [564] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [564] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [565] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [565] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [566] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [566] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [567] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [567] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [568] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [568] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [569] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [569] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [570] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [570] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [571] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [571] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [572] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [572] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [573] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [573] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T0 [574] "logic o_he_readdata_T0[575:0]" +Toggle 1to0 o_he_readdata_T0 [574] "logic o_he_readdata_T0[575:0]" +Toggle 0to1 o_he_readdata_T1 [575] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [575] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [512] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [512] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [513] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [513] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [514] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [514] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [515] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [515] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [516] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [516] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [517] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [517] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [518] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [518] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [519] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [519] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [520] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [520] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [521] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [521] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [522] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [522] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [523] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [523] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [524] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [524] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [525] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [525] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [526] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [526] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [527] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [527] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [528] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [528] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [529] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [529] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [530] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [530] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [531] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [531] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [532] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [532] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [533] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [533] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [534] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [534] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [535] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [535] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [536] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [536] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [537] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [537] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [538] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [538] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [539] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [539] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [540] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [540] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [541] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [541] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [542] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [542] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [543] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [543] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [544] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [544] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [545] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [545] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [546] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [546] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [547] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [547] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [548] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [548] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [549] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [549] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [550] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [550] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [551] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [551] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [552] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [552] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [553] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [553] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [554] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [554] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [555] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [555] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [556] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [556] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [557] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [557] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [558] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [558] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [559] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [559] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [560] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [560] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [561] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [561] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [562] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [562] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [563] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [563] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [564] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [564] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [565] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [565] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [566] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [566] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [567] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [567] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [568] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [568] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [569] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [569] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [570] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [570] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [571] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [571] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [572] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [572] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [573] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [573] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 o_he_readdata_T1 [574] "logic o_he_readdata_T1[575:0]" +Toggle 1to0 o_he_readdata_T1 [574] "logic o_he_readdata_T1[575:0]" +Toggle 0to1 rdburstcount [6] "logic rdburstcount[6:0]" +Toggle 1to0 rdburstcount [6] "logic rdburstcount[6:0]" +Toggle 0to1 rdburstcount [3] "logic rdburstcount[6:0]" +Toggle 1to0 rdburstcount [3] "logic rdburstcount[6:0]" +Toggle 0to1 rdburstcount [4] "logic rdburstcount[6:0]" +Toggle 1to0 rdburstcount [4] "logic rdburstcount[6:0]" +Toggle 0to1 rdburstcount [5] "logic rdburstcount[6:0]" +Toggle 1to0 rdburstcount [5] "logic rdburstcount[6:0]" +ANNOTATION: " Not used " +Toggle req_ecc "logic req_ecc[1:0]" +Toggle 0to1 req_err "logic req_err" +Toggle 1to0 req_err "logic req_err" +Toggle 0to1 req_full_q "logic req_full_q" +Toggle 1to0 req_full_q "logic req_full_q" +Toggle req_trk_din_p "logic req_trk_din_p[7:0]" +Toggle 0to1 req_wen_p "logic req_wen_p" +Toggle 1to0 req_wen_p "logic req_wen_p" +Toggle 0to1 req_trk_wen_p "logic req_trk_wen_p" +Toggle 1to0 req_trk_wen_p "logic req_trk_wen_p" +Toggle 0to1 req_trk_full_q "logic req_trk_full_q" +Toggle 1to0 req_trk_full_q "logic req_trk_full_q" +Toggle 0to1 req_trk_full "logic req_trk_full" +Toggle 1to0 req_trk_full "logic req_trk_full" +Toggle 0to1 req_trk_err "logic req_trk_err" +Toggle 1to0 req_trk_err "logic req_trk_err" +Toggle req_trk_ecc "logic req_trk_ecc[1:0]" +Toggle rsp_err "logic rsp_err[1:0]" +Toggle req_din_p "logic req_din_p[683:0]" +Toggle s0_readdatavalid "logic s0_readdatavalid[1:0]" +Toggle 0to1 req_dout_burstcount [6] "logic req_dout_burstcount[6:0]" +Toggle 1to0 req_dout_burstcount [6] "logic req_dout_burstcount[6:0]" +Toggle 0to1 req_dout_burstcount [3] "logic req_dout_burstcount[6:0]" +Toggle 1to0 req_dout_burstcount [3] "logic req_dout_burstcount[6:0]" +Toggle 0to1 req_dout_burstcount [4] "logic req_dout_burstcount[6:0]" +Toggle 1to0 req_dout_burstcount [4] "logic req_dout_burstcount[6:0]" +Toggle 0to1 req_dout_burstcount [5] "logic req_dout_burstcount[6:0]" +Toggle 1to0 req_dout_burstcount [5] "logic req_dout_burstcount[6:0]" +Toggle 0to1 req_dout_be [71] "logic req_dout_be[71:0]" +Toggle 1to0 req_dout_be [71] "logic req_dout_be[71:0]" +Toggle 0to1 req_dout_be [64] "logic req_dout_be[71:0]" +Toggle 1to0 req_dout_be [64] "logic req_dout_be[71:0]" +Toggle 0to1 req_dout_be [65] "logic req_dout_be[71:0]" +Toggle 1to0 req_dout_be [65] "logic req_dout_be[71:0]" +Toggle 0to1 req_dout_be [66] "logic req_dout_be[71:0]" +Toggle 1to0 req_dout_be [66] "logic req_dout_be[71:0]" +Toggle 0to1 req_dout_be [67] "logic req_dout_be[71:0]" +Toggle 1to0 req_dout_be [67] "logic req_dout_be[71:0]" +Toggle 0to1 req_dout_be [68] "logic req_dout_be[71:0]" +Toggle 1to0 req_dout_be [68] "logic req_dout_be[71:0]" +Toggle 0to1 req_dout_be [69] "logic req_dout_be[71:0]" +Toggle 1to0 req_dout_be [69] "logic req_dout_be[71:0]" +Toggle 0to1 req_dout_be [70] "logic req_dout_be[71:0]" +Toggle 1to0 req_dout_be [70] "logic req_dout_be[71:0]" +Toggle 0to1 req_dout_addr [26] "logic req_dout_addr[26:0]" +Toggle 1to0 req_dout_addr [26] "logic req_dout_addr[26:0]" +Toggle 0to1 req_dout_addr [11] "logic req_dout_addr[26:0]" +Toggle 1to0 req_dout_addr [11] "logic req_dout_addr[26:0]" +Toggle 0to1 req_dout_addr [12] "logic req_dout_addr[26:0]" +Toggle 1to0 req_dout_addr [12] "logic req_dout_addr[26:0]" +Toggle 0to1 req_dout_addr [13] "logic req_dout_addr[26:0]" +Toggle 1to0 req_dout_addr [13] "logic req_dout_addr[26:0]" +Toggle 0to1 req_dout_addr [14] "logic req_dout_addr[26:0]" +Toggle 1to0 req_dout_addr [14] "logic req_dout_addr[26:0]" +Toggle 0to1 req_dout_addr [15] "logic req_dout_addr[26:0]" +Toggle 1to0 req_dout_addr [15] "logic req_dout_addr[26:0]" +Toggle 0to1 req_dout_addr [16] "logic req_dout_addr[26:0]" +Toggle 1to0 req_dout_addr [16] "logic req_dout_addr[26:0]" +Toggle 0to1 req_dout_addr [17] "logic req_dout_addr[26:0]" +Toggle 1to0 req_dout_addr [17] "logic req_dout_addr[26:0]" +Toggle 0to1 req_dout_addr [18] "logic req_dout_addr[26:0]" +Toggle 1to0 req_dout_addr [18] "logic req_dout_addr[26:0]" +Toggle 0to1 req_dout_addr [19] "logic req_dout_addr[26:0]" +Toggle 1to0 req_dout_addr [19] "logic req_dout_addr[26:0]" +Toggle 0to1 req_dout_addr [20] "logic req_dout_addr[26:0]" +Toggle 1to0 req_dout_addr [20] "logic req_dout_addr[26:0]" +Toggle 0to1 req_dout_addr [21] "logic req_dout_addr[26:0]" +Toggle 1to0 req_dout_addr [21] "logic req_dout_addr[26:0]" +Toggle 0to1 req_dout_addr [22] "logic req_dout_addr[26:0]" +Toggle 1to0 req_dout_addr [22] "logic req_dout_addr[26:0]" +Toggle 0to1 req_dout_addr [23] "logic req_dout_addr[26:0]" +Toggle 1to0 req_dout_addr [23] "logic req_dout_addr[26:0]" +Toggle 0to1 req_dout_addr [24] "logic req_dout_addr[26:0]" +Toggle 1to0 req_dout_addr [24] "logic req_dout_addr[26:0]" +Toggle 0to1 req_dout_addr [25] "logic req_dout_addr[26:0]" +Toggle 1to0 req_dout_addr [25] "logic req_dout_addr[26:0]" +Toggle 0to1 req_dout_writedata [575] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [575] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [512] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [512] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [513] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [513] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [514] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [514] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [515] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [515] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [516] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [516] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [517] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [517] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [518] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [518] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [519] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [519] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [520] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [520] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [521] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [521] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [522] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [522] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [523] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [523] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [524] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [524] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [525] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [525] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [526] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [526] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [527] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [527] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [528] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [528] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [529] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [529] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [530] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [530] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [531] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [531] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [532] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [532] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [533] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [533] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [534] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [534] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [535] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [535] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [536] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [536] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [537] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [537] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [538] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [538] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [539] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [539] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [540] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [540] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [541] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [541] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [542] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [542] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [543] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [543] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [544] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [544] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [545] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [545] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [546] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [546] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [547] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [547] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [548] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [548] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [549] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [549] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [550] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [550] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [551] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [551] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [552] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [552] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [553] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [553] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [554] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [554] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [555] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [555] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [556] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [556] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [557] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [557] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [558] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [558] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [559] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [559] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [560] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [560] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [561] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [561] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [562] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [562] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [563] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [563] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [564] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [564] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [565] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [565] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [566] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [566] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [567] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [567] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [568] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [568] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [569] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [569] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [570] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [570] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [571] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [571] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [572] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [572] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [573] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [573] "logic req_dout_writedata[575:0]" +Toggle 0to1 req_dout_writedata [574] "logic req_dout_writedata[575:0]" +Toggle 1to0 req_dout_writedata [574] "logic req_dout_writedata[575:0]" +CHECKSUM: "2245513748 1941661985" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pg_csr_inst +Fsm rom_state "1565177879" +Fsm WriteState "27616187" +Transition ST_BWAIT->ST_WADDR "2->0" +Fsm WriteState "27616187" +Transition ST_WADDR->ST_WDATA "0->1" +Fsm WriteState "27616187" +State ST_WDATA "1" +CHECKSUM: "2063190404 2009976046" +INSTANCE: tb_top.DUT.afu_top.port_gasket.port_reset_fsm_inst +Toggle i_pcie_p2c_sideband.flr_active_pf "logic i_pcie_p2c_sideband.flr_active_pf[1:0]" +Toggle i_pcie_p2c_sideband.flr_rcvd_pf_num "logic i_pcie_p2c_sideband.flr_rcvd_pf_num[0:0]" +Toggle o_pcie_c2p_sideband.flr_completed_pf "logic o_pcie_c2p_sideband.flr_completed_pf[1:0]" +Toggle o_pcie_c2p_sideband.flr_completed_pf_num "logic o_pcie_c2p_sideband.flr_completed_pf_num[0:0]" +Toggle 0to1 rst_n_2x "logic rst_n_2x" +Toggle 1to0 rst_n_2x "logic rst_n_2x" +Toggle i_pcie_p2c_sideband.flr_rcvd_vf_num "logic i_pcie_p2c_sideband.flr_rcvd_vf_num[1:0]" +Toggle 0to1 i_pcie_p2c_sideband.flr_rcvd_vf "logic i_pcie_p2c_sideband.flr_rcvd_vf" +Toggle 1to0 i_pcie_p2c_sideband.flr_rcvd_vf "logic i_pcie_p2c_sideband.flr_rcvd_vf" +Toggle o_pcie_c2p_sideband.flr_completed_vf_num "logic o_pcie_c2p_sideband.flr_completed_vf_num[1:0]" +Toggle 0to1 o_pcie_c2p_sideband.flr_completed_vf "logic o_pcie_c2p_sideband.flr_completed_vf" +Toggle 1to0 o_pcie_c2p_sideband.flr_completed_vf "logic o_pcie_c2p_sideband.flr_completed_vf" +Toggle 0to1 o_port_ctrl [63] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [63] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [5] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [5] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [6] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [6] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [7] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [7] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [8] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [8] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [9] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [9] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [10] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [10] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [11] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [11] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [12] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [12] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [13] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [13] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [14] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [14] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [15] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [15] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [16] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [16] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [17] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [17] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [18] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [18] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [19] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [19] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [20] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [20] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [21] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [21] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [22] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [22] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [23] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [23] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [24] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [24] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [25] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [25] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [26] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [26] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [27] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [27] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [28] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [28] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [29] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [29] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [30] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [30] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [31] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [31] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [32] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [32] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [33] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [33] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [34] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [34] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [35] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [35] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [36] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [36] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [37] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [37] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [38] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [38] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [39] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [39] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [40] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [40] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [41] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [41] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [42] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [42] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [43] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [43] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [44] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [44] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [45] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [45] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [46] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [46] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [47] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [47] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [48] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [48] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [49] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [49] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [50] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [50] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [51] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [51] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [52] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [52] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [53] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [53] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [54] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [54] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [55] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [55] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [56] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [56] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [57] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [57] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [58] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [58] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [59] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [59] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [60] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [60] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [61] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [61] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [62] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [62] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [1] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [1] "logic o_port_ctrl[63:0]" +Toggle 0to1 i_afu_access_ctrl "logic i_afu_access_ctrl" +Toggle 1to0 i_afu_access_ctrl "logic i_afu_access_ctrl" +Toggle 0to1 o_vf_flr_access_err "logic o_vf_flr_access_err" +Toggle 1to0 o_vf_flr_access_err "logic o_vf_flr_access_err" +Toggle 0to1 vf_flr_access_error_d "reg vf_flr_access_error_d" +Toggle 1to0 vf_flr_access_error_d "reg vf_flr_access_error_d" +Toggle 0to1 vf_flr_access_error "reg vf_flr_access_error" +Toggle 1to0 vf_flr_access_error "reg vf_flr_access_error" +Toggle 0to1 i_pcie_p2c_sideband.cfg_ctl.extended_tag_enable "logic i_pcie_p2c_sideband.cfg_ctl.extended_tag_enable" +Toggle 1to0 i_pcie_p2c_sideband.cfg_ctl.extended_tag_enable "logic i_pcie_p2c_sideband.cfg_ctl.extended_tag_enable" +Toggle 0to1 i_pcie_p2c_sideband.cfg_ctl.vf0_msix_mask "logic i_pcie_p2c_sideband.cfg_ctl.vf0_msix_mask" +Toggle 1to0 i_pcie_p2c_sideband.cfg_ctl.vf0_msix_mask "logic i_pcie_p2c_sideband.cfg_ctl.vf0_msix_mask" +Toggle 0to1 i_pcie_p2c_sideband.cfg_ctl.msix_pf_mask_en "logic i_pcie_p2c_sideband.cfg_ctl.msix_pf_mask_en" +Toggle 1to0 i_pcie_p2c_sideband.cfg_ctl.msix_pf_mask_en "logic i_pcie_p2c_sideband.cfg_ctl.msix_pf_mask_en" +Toggle 0to1 i_pcie_p2c_sideband.cfg_ctl.msix_enable "logic i_pcie_p2c_sideband.cfg_ctl.msix_enable" +Toggle 1to0 i_pcie_p2c_sideband.cfg_ctl.msix_enable "logic i_pcie_p2c_sideband.cfg_ctl.msix_enable" +ANNOTATION: " Unused code hence excluded " +Toggle i_pcie_p2c_sideband.cfg_ctl.max_read_req_size "logic i_pcie_p2c_sideband.cfg_ctl.max_read_req_size[2:0]" +ANNOTATION: " Unused code hence excluded " +Toggle i_pcie_p2c_sideband.cfg_ctl.max_payload_size "logic i_pcie_p2c_sideband.cfg_ctl.max_payload_size[2:0]" +Toggle 0to1 i_pcie_p2c_sideband.pcie_linkup "logic i_pcie_p2c_sideband.pcie_linkup" +Toggle 1to0 i_pcie_p2c_sideband.pcie_linkup "logic i_pcie_p2c_sideband.pcie_linkup" +Toggle i_pcie_p2c_sideband.pcie_chk_rx_err_code "logic i_pcie_p2c_sideband.pcie_chk_rx_err_code[31:0]" +Toggle 0to1 i_read_flush_done "logic i_read_flush_done" +Toggle 1to0 i_read_flush_done "logic i_read_flush_done" +Toggle 0to1 i_sel_mmio_rsp "logic i_sel_mmio_rsp" +Toggle 1to0 i_sel_mmio_rsp "logic i_sel_mmio_rsp" +Toggle 0to1 i_port_ctrl [63] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [63] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [5] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [5] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [6] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [6] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [7] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [7] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [8] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [8] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [9] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [9] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [10] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [10] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [11] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [11] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [12] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [12] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [13] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [13] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [14] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [14] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [15] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [15] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [16] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [16] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [17] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [17] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [18] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [18] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [19] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [19] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [20] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [20] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [21] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [21] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [22] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [22] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [23] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [23] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [24] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [24] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [25] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [25] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [26] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [26] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [27] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [27] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [28] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [28] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [29] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [29] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [30] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [30] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [31] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [31] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [32] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [32] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [33] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [33] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [34] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [34] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [35] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [35] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [36] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [36] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [37] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [37] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [38] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [38] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [39] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [39] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [40] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [40] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [41] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [41] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [42] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [42] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [43] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [43] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [44] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [44] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [45] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [45] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [46] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [46] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [47] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [47] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [48] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [48] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [49] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [49] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [50] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [50] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [51] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [51] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [52] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [52] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [53] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [53] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [54] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [54] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [55] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [55] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [56] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [56] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [57] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [57] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [58] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [58] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [59] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [59] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [60] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [60] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [61] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [61] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [62] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [62] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [1] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [1] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [2] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [2] "logic i_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [2] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [2] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [0] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [0] "logic o_port_ctrl[63:0]" +Toggle 0to1 i_pr_reset "logic i_pr_reset" +Toggle 1to0 i_pr_reset "logic i_pr_reset" +CHECKSUM: "2221342403 3727968704" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot +Toggle pr_freeze_hssi "logic pr_freeze_hssi[0:0]" +Toggle 0to1 pr_freeze "net pr_freeze" +Toggle 1to0 pr_freeze "net pr_freeze" +Toggle 0to1 pr_freeze_fnmx_q1 "logic pr_freeze_fnmx_q1" +Toggle 1to0 pr_freeze_fnmx_q1 "logic pr_freeze_fnmx_q1" +Toggle 0to1 pr_freeze_fnmx_q0 "logic pr_freeze_fnmx_q0" +Toggle 1to0 pr_freeze_fnmx_q0 "logic pr_freeze_fnmx_q0" +Toggle 0to1 pr2sr_tdo "logic pr2sr_tdo" +Toggle 1to0 pr2sr_tdo "logic pr2sr_tdo" +Toggle 0to1 sr2pr_tckena "logic sr2pr_tckena" +Toggle 1to0 sr2pr_tckena "logic sr2pr_tckena" +Toggle 0to1 sr2pr_tms "logic sr2pr_tms" +Toggle 1to0 sr2pr_tms "logic sr2pr_tms" +Toggle 0to1 sr2pr_tdi "logic sr2pr_tdi" +Toggle 1to0 sr2pr_tdi "logic sr2pr_tdi" +CHECKSUM: "3211086611 1212592008" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.MREG[0].reg_avmm_if +Toggle 1to0 i_m0_pck_Tx [680] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [680] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [679] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [679] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [678] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [678] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [677] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [677] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [676] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [676] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [675] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [675] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [674] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [674] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [673] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [673] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [672] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [672] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [671] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [671] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [670] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [670] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [669] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [669] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [668] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [668] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [667] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [667] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [666] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [666] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [665] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [665] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [78] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [78] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [77] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [77] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [76] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [76] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [75] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [75] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [74] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [74] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [73] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [73] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [72] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [72] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [71] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [71] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [6] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [6] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [5] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [5] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [4] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [4] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [3] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [3] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [2] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [2] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [1] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [1] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [654] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [654] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [653] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [653] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [652] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [652] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [651] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [651] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [650] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [650] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [649] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [649] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [648] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [648] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [647] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [647] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [646] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [646] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [645] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [645] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [644] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [644] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [643] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [643] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [642] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [642] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [641] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [641] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [640] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [640] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [639] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [639] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [638] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [638] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [637] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [637] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [636] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [636] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [635] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [635] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [634] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [634] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [633] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [633] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [632] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [632] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [631] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [631] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [630] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [630] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [629] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [629] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [628] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [628] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [627] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [627] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [626] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [626] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [625] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [625] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [624] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [624] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [623] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [623] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [622] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [622] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [621] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [621] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [620] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [620] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [619] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [619] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [618] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [618] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [617] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [617] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [616] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [616] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [615] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [615] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [614] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [614] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [613] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [613] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [612] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [612] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [611] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [611] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [610] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [610] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [609] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [609] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [608] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [608] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [607] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [607] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [606] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [606] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [605] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [605] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [604] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [604] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [603] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [603] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [602] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [602] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [601] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [601] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [600] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [600] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [599] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [599] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [598] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [598] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [597] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [597] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [596] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [596] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [595] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [595] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [594] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [594] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [593] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [593] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [592] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [592] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [591] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [591] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [681] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [681] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [680] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [680] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [679] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [679] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [678] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [678] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [677] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [677] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [676] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [676] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [675] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [675] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [674] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [674] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [673] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [673] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [672] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [672] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [671] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [671] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [670] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [670] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [669] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [669] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [668] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [668] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [667] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [667] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [666] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [666] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [665] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [665] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [654] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [654] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [653] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [653] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [652] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [652] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [651] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [651] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [650] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [650] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [649] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [649] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [648] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [648] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [647] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [647] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [646] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [646] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [645] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [645] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [644] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [644] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [643] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [643] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [642] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [642] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [641] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [641] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [640] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [640] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [639] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [639] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [638] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [638] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [637] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [637] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [636] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [636] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [635] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [635] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [634] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [634] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [633] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [633] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [632] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [632] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [631] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [631] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [630] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [630] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [629] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [629] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [628] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [628] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [627] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [627] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [626] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [626] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [625] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [625] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [624] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [624] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [623] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [623] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [622] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [622] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [621] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [621] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [620] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [620] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [619] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [619] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [618] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [618] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [617] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [617] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [616] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [616] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [615] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [615] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [614] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [614] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [613] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [613] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [612] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [612] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [611] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [611] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [610] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [610] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [609] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [609] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [608] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [608] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [607] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [607] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [606] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [606] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [605] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [605] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [604] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [604] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [603] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [603] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [602] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [602] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [601] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [601] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [600] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [600] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [599] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [599] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [598] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [598] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [597] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [597] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [596] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [596] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [595] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [595] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [594] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [594] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [593] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [593] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [592] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [592] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [591] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [591] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [78] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [78] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [77] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [77] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [76] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [76] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [75] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [75] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [74] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [74] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [73] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [73] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [72] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [72] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [71] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [71] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [6] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [6] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [5] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [5] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [4] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [4] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [3] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [3] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [2] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [2] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [1] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [1] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [681] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [681] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [653] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [653] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [652] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [652] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [651] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [651] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [650] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [650] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [649] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [649] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [648] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [648] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [647] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [647] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [646] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [646] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [645] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [645] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [644] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [644] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [643] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [643] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [642] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [642] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [641] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [641] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [640] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [640] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [639] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [639] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [638] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [638] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [637] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [637] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [636] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [636] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [635] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [635] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [634] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [634] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [633] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [633] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [632] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [632] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [631] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [631] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [630] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [630] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [629] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [629] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [628] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [628] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [627] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [627] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [626] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [626] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [625] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [625] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [624] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [624] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [623] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [623] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [622] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [622] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [621] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [621] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [620] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [620] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [619] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [619] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [618] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [618] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [617] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [617] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [616] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [616] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [615] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [615] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [614] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [614] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [613] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [613] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [612] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [612] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [611] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [611] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [610] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [610] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [609] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [609] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [608] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [608] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [607] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [607] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [606] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [606] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [605] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [605] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [604] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [604] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [603] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [603] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [602] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [602] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [601] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [601] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [600] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [600] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [599] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [599] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [598] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [598] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [597] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [597] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [596] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [596] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [595] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [595] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [594] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [594] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [593] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [593] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [592] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [592] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [591] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [591] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [654] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [654] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [680] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [680] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [679] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [679] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [678] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [678] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [677] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [677] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [676] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [676] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [675] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [675] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [674] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [674] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [673] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [673] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [672] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [672] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [671] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [671] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [670] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [670] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [669] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [669] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [668] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [668] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [667] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [667] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [666] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [666] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [665] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [665] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [78] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [78] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [77] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [77] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [76] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [76] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [75] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [75] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [74] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [74] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [73] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [73] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [72] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [72] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [71] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [71] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [6] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [6] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [5] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [5] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [4] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [4] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [3] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [3] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [2] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [2] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [1] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [1] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [681] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [681] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx [680] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [680] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [679] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [679] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [678] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [678] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [677] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [677] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [676] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [676] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [675] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [675] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [674] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [674] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [673] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [673] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [672] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [672] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [671] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [671] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [670] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [670] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [669] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [669] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [668] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [668] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [667] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [667] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [666] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [666] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [665] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [665] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [654] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [654] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [653] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [653] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [652] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [652] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [651] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [651] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [650] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [650] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [649] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [649] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [648] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [648] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [647] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [647] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [646] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [646] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [645] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [645] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [644] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [644] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [643] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [643] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [642] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [642] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [641] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [641] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [640] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [640] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [639] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [639] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [638] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [638] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [637] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [637] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [636] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [636] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [635] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [635] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [634] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [634] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [633] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [633] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [632] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [632] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [631] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [631] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [630] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [630] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [629] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [629] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [628] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [628] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [627] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [627] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [626] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [626] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [625] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [625] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [624] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [624] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [623] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [623] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [622] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [622] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [621] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [621] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [620] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [620] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [619] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [619] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [618] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [618] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [617] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [617] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [616] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [616] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [615] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [615] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [614] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [614] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [613] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [613] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [612] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [612] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [611] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [611] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [610] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [610] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [609] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [609] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [608] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [608] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [607] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [607] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [606] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [606] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [605] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [605] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [604] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [604] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [603] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [603] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [602] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [602] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [601] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [601] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [600] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [600] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [599] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [599] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [598] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [598] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [597] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [597] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [596] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [596] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [595] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [595] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [594] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [594] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [593] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [593] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [592] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [592] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [591] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [591] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [78] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [78] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [77] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [77] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [76] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [76] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [75] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [75] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [74] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [74] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [73] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [73] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [72] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [72] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [71] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [71] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [6] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [6] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [5] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [5] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [4] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [4] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [3] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [3] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [2] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [2] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [1] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [1] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [681] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [681] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_m0_pck_Rx [576] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [576] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [513] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [513] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [514] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [514] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [515] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [515] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [516] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [516] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [517] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [517] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [518] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [518] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [519] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [519] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [520] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [520] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [521] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [521] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [522] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [522] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [523] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [523] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [524] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [524] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [525] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [525] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [526] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [526] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [527] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [527] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [528] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [528] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [529] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [529] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [530] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [530] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [531] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [531] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [532] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [532] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [533] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [533] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [534] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [534] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [535] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [535] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [536] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [536] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [537] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [537] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [538] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [538] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [539] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [539] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [540] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [540] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [541] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [541] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [542] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [542] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [543] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [543] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [544] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [544] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [545] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [545] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [546] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [546] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [547] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [547] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [548] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [548] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [549] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [549] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [550] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [550] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [551] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [551] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [552] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [552] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [553] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [553] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [554] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [554] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [555] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [555] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [556] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [556] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [557] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [557] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [558] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [558] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [559] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [559] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [560] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [560] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [561] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [561] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [562] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [562] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [563] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [563] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [564] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [564] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [565] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [565] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [566] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [566] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [567] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [567] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [568] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [568] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [569] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [569] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [570] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [570] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [571] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [571] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [572] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [572] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [573] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [573] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [574] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [574] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [575] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [575] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [576] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [576] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [513] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [513] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [514] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [514] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [515] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [515] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [516] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [516] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [517] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [517] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [518] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [518] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [519] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [519] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [520] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [520] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [521] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [521] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [522] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [522] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [523] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [523] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [524] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [524] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [525] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [525] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [526] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [526] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [527] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [527] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [528] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [528] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [529] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [529] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [530] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [530] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [531] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [531] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [532] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [532] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [533] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [533] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [534] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [534] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [535] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [535] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [536] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [536] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [537] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [537] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [538] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [538] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [539] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [539] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [540] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [540] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [541] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [541] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [542] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [542] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [543] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [543] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [544] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [544] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [545] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [545] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [546] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [546] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [547] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [547] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [548] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [548] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [549] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [549] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [550] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [550] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [551] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [551] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [552] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [552] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [553] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [553] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [554] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [554] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [555] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [555] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [556] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [556] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [557] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [557] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [558] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [558] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [559] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [559] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [560] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [560] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [561] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [561] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [562] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [562] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [563] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [563] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [564] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [564] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [565] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [565] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [566] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [566] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [567] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [567] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [568] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [568] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [569] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [569] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [570] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [570] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [571] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [571] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [572] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [572] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [573] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [573] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [574] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [574] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [575] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [575] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx [576] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [576] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [513] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [513] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [514] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [514] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [515] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [515] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [516] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [516] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [517] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [517] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [518] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [518] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [519] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [519] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [520] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [520] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [521] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [521] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [522] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [522] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [523] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [523] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [524] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [524] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [525] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [525] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [526] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [526] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [527] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [527] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [528] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [528] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [529] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [529] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [530] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [530] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [531] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [531] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [532] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [532] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [533] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [533] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [534] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [534] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [535] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [535] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [536] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [536] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [537] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [537] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [538] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [538] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [539] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [539] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [540] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [540] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [541] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [541] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [542] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [542] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [543] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [543] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [544] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [544] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [545] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [545] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [546] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [546] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [547] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [547] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [548] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [548] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [549] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [549] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [550] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [550] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [551] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [551] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [552] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [552] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [553] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [553] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [554] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [554] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [555] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [555] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [556] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [556] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [557] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [557] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [558] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [558] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [559] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [559] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [560] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [560] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [561] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [561] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [562] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [562] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [563] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [563] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [564] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [564] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [565] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [565] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [566] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [566] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [567] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [567] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [568] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [568] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [569] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [569] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [570] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [570] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [571] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [571] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [572] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [572] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [573] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [573] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [574] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [574] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [575] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [575] "logic i_s0_pck_Rx[576:0]" +CHECKSUM: "3211086611 1212592008" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.MREG[1].reg_avmm_if +Toggle 1to0 o_s0_pck_Tx_q [680] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [680] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [679] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [679] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [678] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [678] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [677] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [677] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [676] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [676] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [675] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [675] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [674] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [674] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [673] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [673] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [672] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [672] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [671] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [671] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [670] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [670] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [669] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [669] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [668] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [668] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [667] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [667] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [666] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [666] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [665] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [665] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [654] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [654] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [653] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [653] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [652] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [652] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [651] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [651] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [650] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [650] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [649] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [649] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [648] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [648] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [647] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [647] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [646] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [646] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [645] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [645] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [644] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [644] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [643] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [643] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [642] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [642] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [641] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [641] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [640] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [640] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [639] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [639] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [638] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [638] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [637] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [637] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [636] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [636] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [635] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [635] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [634] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [634] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [633] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [633] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [632] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [632] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [631] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [631] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [630] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [630] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [629] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [629] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [628] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [628] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [627] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [627] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [626] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [626] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [625] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [625] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [624] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [624] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [623] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [623] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [622] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [622] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [621] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [621] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [620] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [620] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [619] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [619] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [618] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [618] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [617] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [617] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [616] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [616] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [615] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [615] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [614] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [614] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [613] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [613] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [612] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [612] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [611] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [611] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [610] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [610] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [609] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [609] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [608] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [608] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [607] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [607] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [606] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [606] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [605] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [605] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [604] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [604] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [603] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [603] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [602] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [602] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [601] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [601] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [600] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [600] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [599] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [599] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [598] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [598] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [597] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [597] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [596] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [596] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [595] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [595] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [594] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [594] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [593] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [593] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [592] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [592] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [591] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [591] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [78] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [78] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [77] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [77] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [76] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [76] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [75] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [75] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [74] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [74] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [73] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [73] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [72] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [72] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [71] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [71] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [6] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [6] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [5] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [5] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [4] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [4] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [3] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [3] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx_q [681] "logic o_s0_pck_Tx_q[683:0]" +Toggle 0to1 o_s0_pck_Tx_q [681] "logic o_s0_pck_Tx_q[683:0]" +Toggle 1to0 o_s0_pck_Tx [680] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [680] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [679] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [679] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [678] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [678] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [677] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [677] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [676] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [676] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [675] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [675] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [674] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [674] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [673] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [673] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [672] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [672] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [671] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [671] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [670] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [670] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [669] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [669] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [668] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [668] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [667] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [667] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [666] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [666] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [665] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [665] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [654] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [654] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [653] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [653] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [652] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [652] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [651] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [651] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [650] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [650] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [649] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [649] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [648] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [648] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [647] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [647] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [646] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [646] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [645] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [645] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [644] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [644] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [643] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [643] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [642] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [642] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [641] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [641] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [640] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [640] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [639] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [639] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [638] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [638] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [637] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [637] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [636] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [636] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [635] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [635] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [634] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [634] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [633] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [633] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [632] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [632] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [631] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [631] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [630] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [630] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [629] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [629] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [628] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [628] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [627] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [627] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [626] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [626] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [625] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [625] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [624] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [624] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [623] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [623] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [622] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [622] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [621] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [621] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [620] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [620] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [619] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [619] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [618] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [618] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [617] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [617] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [616] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [616] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [615] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [615] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [614] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [614] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [613] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [613] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [612] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [612] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [611] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [611] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [610] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [610] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [609] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [609] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [608] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [608] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [607] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [607] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [606] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [606] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [605] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [605] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [604] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [604] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [603] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [603] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [602] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [602] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [601] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [601] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [600] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [600] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [599] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [599] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [598] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [598] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [597] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [597] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [596] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [596] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [595] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [595] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [594] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [594] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [593] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [593] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [592] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [592] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [591] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [591] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [78] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [78] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [77] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [77] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [76] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [76] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [75] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [75] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [74] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [74] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [73] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [73] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [72] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [72] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [71] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [71] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [6] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [6] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [5] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [5] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [4] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [4] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [3] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [3] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 o_s0_pck_Tx [681] "logic o_s0_pck_Tx[683:0]" +Toggle 0to1 o_s0_pck_Tx [681] "logic o_s0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [680] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [680] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [679] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [679] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [678] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [678] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [677] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [677] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [676] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [676] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [675] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [675] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [674] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [674] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [673] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [673] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [672] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [672] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [671] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [671] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [670] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [670] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [669] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [669] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [668] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [668] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [667] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [667] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [666] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [666] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [665] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [665] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [654] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [654] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [653] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [653] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [652] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [652] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [651] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [651] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [650] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [650] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [649] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [649] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [648] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [648] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [647] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [647] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [646] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [646] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [645] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [645] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [644] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [644] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [643] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [643] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [642] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [642] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [641] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [641] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [640] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [640] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [639] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [639] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [638] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [638] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [637] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [637] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [636] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [636] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [635] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [635] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [634] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [634] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [633] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [633] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [632] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [632] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [631] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [631] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [630] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [630] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [629] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [629] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [628] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [628] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [627] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [627] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [626] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [626] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [625] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [625] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [624] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [624] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [623] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [623] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [622] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [622] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [621] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [621] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [620] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [620] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [619] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [619] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [618] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [618] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [617] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [617] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [616] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [616] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [615] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [615] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [614] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [614] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [613] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [613] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [612] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [612] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [611] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [611] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [610] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [610] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [609] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [609] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [608] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [608] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [607] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [607] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [606] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [606] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [605] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [605] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [604] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [604] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [603] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [603] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [602] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [602] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [601] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [601] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [600] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [600] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [599] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [599] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [598] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [598] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [597] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [597] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [596] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [596] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [595] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [595] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [594] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [594] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [593] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [593] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [592] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [592] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [591] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [591] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [78] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [78] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [77] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [77] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [76] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [76] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [75] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [75] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [74] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [74] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [73] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [73] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [72] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [72] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [71] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [71] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [6] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [6] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [5] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [5] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [4] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [4] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [3] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [3] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx_q [681] "logic i_m0_pck_Tx_q[683:0]" +Toggle 0to1 i_m0_pck_Tx_q [681] "logic i_m0_pck_Tx_q[683:0]" +Toggle 1to0 i_m0_pck_Tx [680] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [680] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [679] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [679] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [678] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [678] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [677] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [677] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [676] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [676] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [675] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [675] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [674] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [674] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [673] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [673] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [672] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [672] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [671] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [671] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [670] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [670] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [669] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [669] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [668] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [668] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [667] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [667] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [666] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [666] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [665] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [665] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [654] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [654] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [653] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [653] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [652] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [652] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [651] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [651] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [650] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [650] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [649] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [649] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [648] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [648] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [647] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [647] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [646] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [646] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [645] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [645] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [644] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [644] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [643] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [643] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [642] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [642] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [641] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [641] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [640] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [640] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [639] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [639] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [638] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [638] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [637] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [637] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [636] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [636] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [635] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [635] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [634] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [634] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [633] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [633] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [632] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [632] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [631] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [631] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [630] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [630] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [629] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [629] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [628] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [628] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [627] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [627] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [626] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [626] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [625] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [625] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [624] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [624] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [623] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [623] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [622] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [622] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [621] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [621] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [620] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [620] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [619] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [619] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [618] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [618] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [617] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [617] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [616] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [616] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [615] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [615] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [614] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [614] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [613] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [613] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [612] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [612] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [611] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [611] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [610] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [610] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [609] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [609] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [608] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [608] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [607] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [607] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [606] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [606] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [605] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [605] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [604] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [604] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [603] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [603] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [602] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [602] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [601] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [601] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [600] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [600] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [599] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [599] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [598] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [598] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [597] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [597] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [596] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [596] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [595] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [595] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [594] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [594] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [593] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [593] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [592] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [592] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [591] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [591] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [78] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [78] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [77] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [77] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [76] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [76] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [75] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [75] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [74] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [74] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [73] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [73] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [72] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [72] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [71] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [71] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [6] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [6] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [5] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [5] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [4] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [4] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [3] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [3] "logic i_m0_pck_Tx[683:0]" +Toggle 1to0 i_m0_pck_Tx [681] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 i_m0_pck_Tx [681] "logic i_m0_pck_Tx[683:0]" +Toggle 0to1 o_m0_pck_Rx [576] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [576] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [513] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [513] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [514] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [514] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [515] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [515] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [516] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [516] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [517] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [517] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [518] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [518] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [519] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [519] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [520] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [520] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [521] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [521] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [522] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [522] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [523] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [523] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [524] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [524] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [525] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [525] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [526] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [526] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [527] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [527] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [528] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [528] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [529] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [529] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [530] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [530] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [531] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [531] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [532] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [532] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [533] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [533] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [534] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [534] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [535] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [535] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [536] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [536] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [537] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [537] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [538] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [538] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [539] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [539] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [540] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [540] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [541] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [541] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [542] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [542] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [543] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [543] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [544] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [544] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [545] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [545] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [546] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [546] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [547] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [547] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [548] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [548] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [549] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [549] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [550] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [550] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [551] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [551] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [552] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [552] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [553] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [553] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [554] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [554] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [555] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [555] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [556] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [556] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [557] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [557] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [558] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [558] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [559] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [559] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [560] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [560] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [561] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [561] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [562] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [562] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [563] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [563] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [564] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [564] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [565] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [565] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [566] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [566] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [567] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [567] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [568] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [568] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [569] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [569] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [570] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [570] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [571] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [571] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [572] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [572] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [573] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [573] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [574] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [574] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 o_m0_pck_Rx [575] "logic o_m0_pck_Rx[576:0]" +Toggle 1to0 o_m0_pck_Rx [575] "logic o_m0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [576] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [576] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [513] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [513] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [514] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [514] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [515] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [515] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [516] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [516] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [517] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [517] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [518] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [518] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [519] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [519] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [520] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [520] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [521] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [521] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [522] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [522] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [523] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [523] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [524] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [524] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [525] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [525] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [526] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [526] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [527] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [527] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [528] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [528] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [529] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [529] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [530] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [530] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [531] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [531] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [532] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [532] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [533] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [533] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [534] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [534] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [535] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [535] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [536] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [536] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [537] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [537] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [538] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [538] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [539] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [539] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [540] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [540] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [541] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [541] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [542] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [542] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [543] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [543] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [544] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [544] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [545] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [545] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [546] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [546] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [547] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [547] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [548] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [548] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [549] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [549] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [550] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [550] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [551] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [551] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [552] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [552] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [553] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [553] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [554] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [554] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [555] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [555] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [556] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [556] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [557] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [557] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [558] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [558] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [559] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [559] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [560] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [560] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [561] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [561] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [562] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [562] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [563] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [563] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [564] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [564] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [565] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [565] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [566] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [566] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [567] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [567] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [568] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [568] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [569] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [569] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [570] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [570] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [571] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [571] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [572] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [572] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [573] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [573] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [574] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [574] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx_q [575] "logic i_s0_pck_Rx_q[576:0]" +Toggle 1to0 i_s0_pck_Rx_q [575] "logic i_s0_pck_Rx_q[576:0]" +Toggle 0to1 i_s0_pck_Rx [576] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [576] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [513] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [513] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [514] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [514] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [515] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [515] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [516] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [516] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [517] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [517] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [518] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [518] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [519] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [519] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [520] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [520] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [521] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [521] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [522] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [522] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [523] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [523] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [524] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [524] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [525] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [525] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [526] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [526] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [527] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [527] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [528] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [528] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [529] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [529] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [530] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [530] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [531] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [531] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [532] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [532] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [533] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [533] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [534] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [534] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [535] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [535] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [536] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [536] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [537] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [537] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [538] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [538] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [539] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [539] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [540] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [540] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [541] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [541] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [542] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [542] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [543] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [543] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [544] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [544] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [545] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [545] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [546] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [546] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [547] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [547] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [548] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [548] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [549] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [549] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [550] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [550] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [551] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [551] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [552] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [552] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [553] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [553] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [554] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [554] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [555] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [555] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [556] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [556] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [557] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [557] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [558] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [558] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [559] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [559] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [560] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [560] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [561] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [561] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [562] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [562] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [563] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [563] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [564] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [564] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [565] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [565] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [566] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [566] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [567] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [567] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [568] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [568] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [569] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [569] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [570] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [570] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [571] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [571] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [572] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [572] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [573] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [573] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [574] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [574] "logic i_s0_pck_Rx[576:0]" +Toggle 0to1 i_s0_pck_Rx [575] "logic i_s0_pck_Rx[576:0]" +Toggle 1to0 i_s0_pck_Rx [575] "logic i_s0_pck_Rx[576:0]" +CHECKSUM: "2245513748 3796798641" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pg_csr_inst +Block 24 "3430927095" "if (aw_ready_valid)" +Block 25 "3415493964" "WriteNextState = ST_WDATA;" +Block 27 "719276282" "if (w_ready_valid)" +Block 28 "327817328" "WriteNextState = ST_BWAIT;" +Block 37 "973118593" "axi_s_if.wready = 1'b1;" +Block 39 "2539332069" "csr_write = '{default:0, (*adjust*)default:0};" +Block 42 "1412762927" "csr_write = '{default:0, (*adjust*)default:0};" +Block 65 "3615548423" "axi_s_if.rdata = m_remotestp_if.rdata;" +Block 70 "674365679" "axi_s_if.rvalid = m_remotestp_if.rvalid;" +CHECKSUM: "2063190404 327973041" +INSTANCE: tb_top.DUT.afu_top.port_gasket.port_reset_fsm_inst +Fsm fsm_reset "327973041" +Transition RESET_CLEAR->RESET_HOLD "8->1" +Fsm fsm_reset "327973041" +Transition RESET_DEACT->RESET_HOLD "4->1" +CHECKSUM: "2063190404 1018801019" +INSTANCE: tb_top.DUT.afu_top.port_gasket.port_reset_fsm_inst +Branch 1 "147214253" "1'b1" (7) "1'b1 fsm_reset[RESET_SET_BIT] ,-,-,-,0" +Branch 1 "147214253" "1'b1" (8) "1'b1 MISSING_DEFAULT,-,-,-,-" +Branch 3 "4279864501" "((~rst_n_2x) | o_pcie_c2p_sideband.flr_completed_vf)" (1) "((~rst_n_2x) | o_pcie_c2p_sideband.flr_completed_vf) 0,1" +Branch 4 "3622414033" "(~rst_n_2x)" (2) "(~rst_n_2x) 0,0,1" +CHECKSUM: "2245513748 218315394" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pg_csr_inst +Branch 12 "4225463740" "ReadState" (4) "ReadState MISSING_DEFAULT,-,-" +Branch 14 "1535680582" "ReadState" (3) "ReadState MISSING_DEFAULT,-" +Branch 8 "1761624787" "WriteState" (8) "WriteState MISSING_DEFAULT,-,-,-,-" +Branch 8 "1761624787" "WriteState" (4) "WriteState ST_WDATA ,-,-,0,-" +Branch 9 "2972621228" "WriteState" (1) "WriteState ST_WDATA ,-,-" +Branch 9 "2972621228" "WriteState" (6) "WriteState MISSING_DEFAULT,-,-" +Branch 13 "768932900" "remotestp_araddr_hit" (0) "remotestp_araddr_hit 1" +Branch 14 "1535680582" "ReadState" (1) "ReadState ST_RDATA ,1" +Branch 4 "3223164278" "remotestp_awaddr_hit" (0) "remotestp_awaddr_hit 1" +Branch 5 "3223164278" "remotestp_awaddr_hit" (0) "remotestp_awaddr_hit 1" +Branch 6 "1391670162" "remotestp_araddr_hit" (0) "remotestp_araddr_hit 1" +Branch 9 "2972621228" "WriteState" (2) "WriteState ST_BWAIT ,1,-" +Branch 9 "2972621228" "WriteState" (4) "WriteState ST_BRESP ,-,1" +Branch 8 "1761624787" "WriteState" (1) "WriteState ST_WADDR ,0,1,-,-" +Branch 8 "1761624787" "WriteState" (3) "WriteState ST_WDATA ,-,-,1,-" +Branch 0 "3772450998" "(!axi_s_if.wvalid)" (2) "(!axi_s_if.wvalid) 0,0,1,1,-" +Branch 0 "3772450998" "(!axi_s_if.wvalid)" (3) "(!axi_s_if.wvalid) 0,0,1,0,-" +CHECKSUM: "509893243 4041695300" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_ctrl +Branch 1 "122278713" "1'b1" (1) "1'b1 pr_control_state[PR_CTL_PREV_PR_CLR_BIT] " +Branch 1 "122278713" "1'b1" (5) "1'b1 pr_control_state[PR_CTL_PR_IN_PROGRESS_BIT] " +Branch 1 "122278713" "1'b1" (4) "1'b1 pr_control_state[PR_CTL_INITIATE_PR_BIT] " +Branch 1 "122278713" "1'b1" (3) "1'b1 pr_control_state[PR_CTL_AFU_FREEZE_BIT] " +Branch 1 "122278713" "1'b1" (2) "1'b1 pr_control_state[PR_CTL_PORT_RESET_BIT] " +Branch 8 "1195373846" "1'b1" (2) "1'b1 pr_control_state[PR_CTL_PREV_PR_CLR_BIT] ,-,1,-,-,-,-,-,-,-" +Branch 8 "1195373846" "1'b1" (11) "1'b1 pr_control_state[PR_CTL_PR_IN_PROGRESS_BIT] ,-,-,-,-,-,0,-,-,-" +Branch 8 "1195373846" "1'b1" (10) "1'b1 pr_control_state[PR_CTL_PR_IN_PROGRESS_BIT] ,-,-,-,-,-,1,-,-,-" +Branch 8 "1195373846" "1'b1" (9) "1'b1 pr_control_state[PR_CTL_INITIATE_PR_BIT] ,-,-,-,-,0,-,-,-,-" +Branch 8 "1195373846" "1'b1" (8) "1'b1 pr_control_state[PR_CTL_INITIATE_PR_BIT] ,-,-,-,-,1,-,-,-,-" +Branch 8 "1195373846" "1'b1" (7) "1'b1 pr_control_state[PR_CTL_AFU_FREEZE_BIT] ,-,-,-,0,-,-,-,-,-" +Branch 8 "1195373846" "1'b1" (6) "1'b1 pr_control_state[PR_CTL_AFU_FREEZE_BIT] ,-,-,-,1,-,-,-,-,-" +Branch 8 "1195373846" "1'b1" (5) "1'b1 pr_control_state[PR_CTL_PORT_RESET_BIT] ,-,-,0,-,-,-,-,-,-" +Branch 8 "1195373846" "1'b1" (4) "1'b1 pr_control_state[PR_CTL_PORT_RESET_BIT] ,-,-,1,-,-,-,-,-,-" +Branch 8 "1195373846" "1'b1" (3) "1'b1 pr_control_state[PR_CTL_PREV_PR_CLR_BIT] ,-,0,-,-,-,-,-,-,-" +Branch 9 "2548807968" "pr_control_state[PR_CTL_PR_IN_PROGRESS_BIT]" (0) "pr_control_state[PR_CTL_PR_IN_PROGRESS_BIT] 1" +Branch 10 "2779413214" "(!rst_n_1x)" (3) "(!rst_n_1x) 0,0,pr_control_state[PR_CTL_PREV_PR_CLR_BIT] " +Branch 10 "2779413214" "(!rst_n_1x)" (7) "(!rst_n_1x) 0,0,pr_control_state[PR_CTL_PR_IN_PROGRESS_BIT] " +Branch 10 "2779413214" "(!rst_n_1x)" (6) "(!rst_n_1x) 0,0,pr_control_state[PR_CTL_INITIATE_PR_BIT] " +Branch 10 "2779413214" "(!rst_n_1x)" (5) "(!rst_n_1x) 0,0,pr_control_state[PR_CTL_AFU_FREEZE_BIT] " +Branch 10 "2779413214" "(!rst_n_1x)" (4) "(!rst_n_1x) 0,0,pr_control_state[PR_CTL_PORT_RESET_BIT] " +Branch 11 "916418589" "pr_ip_status" (1) "pr_ip_status pr_pkg::CONFIGURATION_SYSTEM_IS_BUSY " +Branch 11 "916418589" "pr_ip_status" (4) "pr_ip_status pr_pkg::PR_ERROR_IS_TRIGGERED " +Branch 11 "916418589" "pr_ip_status" (3) "pr_ip_status pr_pkg::PR_OPERATION_SUCCESSFUL " +Branch 11 "916418589" "pr_ip_status" (2) "pr_ip_status pr_pkg::PR_OPERATION_IN_PROGRESS " +Branch 12 "3221848194" "(~pr_ip_reset_n)" (1) "(~pr_ip_reset_n) 0,1" +ANNOTATION: " PR FLOW taken taken care at unit level hence excluded " +Branch 13 "305424438" "(~pr_ip_reset_n)" (1) "(~pr_ip_reset_n) 0,1,1" +Branch 13 "305424438" "(~pr_ip_reset_n)" (2) "(~pr_ip_reset_n) 0,1,0" +Branch 5 "1780479690" "1'b1" (4) "1'b1 pr_reset_state[PR_RST_ACK_BIT] ,-,-,1" +ANNOTATION: " PR FLOw is not performed at top level. " +Branch 8 "1195373846" "1'b1" (12) "1'b1 pr_control_state[PR_CTL_REQ_COMPLETE_BIT] ,-,-,-,-,-,-,1,-,-" +ANNOTATION: " PR FLOw is not performed at top level. " +Branch 8 "1195373846" "1'b1" (17) "1'b1 pr_control_state[PR_CTL_REINIT_SERVICE_BIT] ,-,-,-,-,-,-,-,-,0" +ANNOTATION: " PR FLOw is not performed at top level. " +Branch 8 "1195373846" "1'b1" (16) "1'b1 pr_control_state[PR_CTL_REINIT_SERVICE_BIT] ,-,-,-,-,-,-,-,-,1" +ANNOTATION: " PR FLOw is not performed at top level. " +Branch 8 "1195373846" "1'b1" (15) "1'b1 pr_control_state[PR_CTL_PORT_OO_RESET_BIT] ,-,-,-,-,-,-,-,0,-" +ANNOTATION: " PR FLOw is not performed at top level. " +Branch 8 "1195373846" "1'b1" (14) "1'b1 pr_control_state[PR_CTL_PORT_OO_RESET_BIT] ,-,-,-,-,-,-,-,1,-" +ANNOTATION: " PR FLOw is not performed at top level. " +Branch 8 "1195373846" "1'b1" (13) "1'b1 pr_control_state[PR_CTL_REQ_COMPLETE_BIT] ,-,-,-,-,-,-,0,-,-" +Branch 10 "2779413214" "(!rst_n_1x)" (8) "(!rst_n_1x) 0,0,pr_control_state[PR_CTL_REQ_COMPLETE_BIT] " +Branch 10 "2779413214" "(!rst_n_1x)" (10) "(!rst_n_1x) 0,0,pr_control_state[PR_CTL_REINIT_SERVICE_BIT] " +Branch 10 "2779413214" "(!rst_n_1x)" (9) "(!rst_n_1x) 0,0,pr_control_state[PR_CTL_PORT_OO_RESET_BIT] " +Branch 10 "2779413214" "(!rst_n_1x)" (1) "(!rst_n_1x) 0,1,-" +Branch 1 "122278713" "1'b1" (6) "1'b1 pr_control_state[PR_CTL_REQ_COMPLETE_BIT] " +Branch 1 "122278713" "1'b1" (8) "1'b1 pr_control_state[PR_CTL_REINIT_SERVICE_BIT] " +Branch 1 "122278713" "1'b1" (7) "1'b1 pr_control_state[PR_CTL_PORT_OO_RESET_BIT] " +Branch 5 "1780479690" "1'b1" (0) "1'b1 pr_reset_state[PR_RST_IDLE_BIT] ,1,-,-" +Branch 5 "1780479690" "1'b1" (3) "1'b1 pr_reset_state[PR_RST_REQ_BIT] ,-,0,-" +Branch 5 "1780479690" "1'b1" (2) "1'b1 pr_reset_state[PR_RST_REQ_BIT] ,-,1,-" +Branch 5 "1780479690" "1'b1" (5) "1'b1 pr_reset_state[PR_RST_ACK_BIT] ,-,-,0" +Branch 7 "64705102" "(!rst_n_1x)" (1) "(!rst_n_1x) 0,1" +CHECKSUM: "2063190404 1706557912" +INSTANCE: tb_top.DUT.afu_top.port_gasket.port_reset_fsm_inst +ANNOTATION: " Tied to 'h1 in design " +Condition 1 "3636465555" "(i_read_flush_done && port_deact) 1 -1" (1 "01") +CHECKSUM: "2245513748 1961550632" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pg_csr_inst +Condition 14 "3316197504" "(aw_ready_valid && w_ready_valid) 1 -1" (1 "01") +Condition 14 "3316197504" "(aw_ready_valid && w_ready_valid) 1 -1" (2 "10") +Condition 4 "3134688409" "(((!waddr_reg[2])) ? LOWER32 : UPPER32) 1 -1" +Condition 8 "272111311" "(remotestp_araddr_hit ? axi_s_if.arvalid : 1'b0) 1 -1" +Condition 7 "26262652" "(remotestp_awaddr_hit ? axi_s_if.wvalid : 1'b0) 1 -1" +Condition 6 "3292508500" "(remotestp_awaddr_hit ? axi_s_if.awvalid : 1'b0) 1 -1" +CHECKSUM: "2310210991 1345492558" +INSTANCE: tb_top.DUT.afu_top.port_gasket +Toggle 1to0 rst2csr_port_ctrl [0] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [0] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 i_pr2sr_tdo "logic i_pr2sr_tdo" +Toggle 0to1 i_pr2sr_tdo "logic i_pr2sr_tdo" +Toggle 1to0 pcie_p2c_sideband.pcie_linkup "logic pcie_p2c_sideband.pcie_linkup" +Toggle 0to1 pcie_p2c_sideband.pcie_linkup "logic pcie_p2c_sideband.pcie_linkup" +ANNOTATION: " Unused code hence excluded " +Toggle pcie_p2c_sideband.pcie_chk_rx_err_code "logic pcie_p2c_sideband.pcie_chk_rx_err_code[31:0]" +Toggle 1to0 pcie_p2c_sideband.cfg_ctl.extended_tag_enable "logic pcie_p2c_sideband.cfg_ctl.extended_tag_enable" +Toggle 0to1 pcie_p2c_sideband.cfg_ctl.extended_tag_enable "logic pcie_p2c_sideband.cfg_ctl.extended_tag_enable" +ANNOTATION: " Unused code hence excluded " +Toggle pcie_p2c_sideband.cfg_ctl.max_payload_size "logic pcie_p2c_sideband.cfg_ctl.max_payload_size[2:0]" +ANNOTATION: " Unused code hence excluded " +Toggle pcie_p2c_sideband.cfg_ctl.max_read_req_size "logic pcie_p2c_sideband.cfg_ctl.max_read_req_size[2:0]" +Toggle 1to0 pcie_p2c_sideband.cfg_ctl.msix_enable "logic pcie_p2c_sideband.cfg_ctl.msix_enable" +Toggle 0to1 pcie_p2c_sideband.cfg_ctl.msix_enable "logic pcie_p2c_sideband.cfg_ctl.msix_enable" +Toggle 1to0 pcie_p2c_sideband.cfg_ctl.msix_pf_mask_en "logic pcie_p2c_sideband.cfg_ctl.msix_pf_mask_en" +Toggle 0to1 pcie_p2c_sideband.cfg_ctl.msix_pf_mask_en "logic pcie_p2c_sideband.cfg_ctl.msix_pf_mask_en" +Toggle 1to0 pcie_p2c_sideband.cfg_ctl.vf0_msix_mask "logic pcie_p2c_sideband.cfg_ctl.vf0_msix_mask" +Toggle 0to1 pcie_p2c_sideband.cfg_ctl.vf0_msix_mask "logic pcie_p2c_sideband.cfg_ctl.vf0_msix_mask" +Toggle 1to0 o_pr_parity_error "logic o_pr_parity_error" +Toggle 0to1 o_pr_parity_error "logic o_pr_parity_error" +Toggle 1to0 i_read_flush_done "logic i_read_flush_done" +Toggle 0to1 i_read_flush_done "logic i_read_flush_done" +ANNOTATION: " Unused code hence excluded " +Toggle pcie_p2c_sideband.flr_active_pf "logic pcie_p2c_sideband.flr_active_pf[1:0]" +Toggle 1to0 pr_reset "logic pr_reset" +Toggle 0to1 pr_reset "logic pr_reset" +Toggle 1to0 pr_freeze "logic pr_freeze" +Toggle 0to1 pr_freeze "logic pr_freeze" +Toggle 1to0 csr2rst_port_ctrl [2] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [2] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [1] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [1] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [62] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [62] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [61] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [61] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [60] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [60] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [59] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [59] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [58] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [58] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [57] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [57] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [56] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [56] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [55] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [55] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [54] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [54] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [53] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [53] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [52] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [52] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [51] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [51] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [50] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [50] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [49] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [49] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [48] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [48] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [47] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [47] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [46] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [46] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [45] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [45] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [44] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [44] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [43] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [43] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [42] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [42] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [41] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [41] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [40] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [40] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [39] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [39] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [38] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [38] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [37] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [37] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [36] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [36] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [35] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [35] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [34] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [34] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [33] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [33] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [32] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [32] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [31] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [31] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [30] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [30] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [29] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [29] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [28] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [28] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [27] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [27] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [26] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [26] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [25] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [25] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [24] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [24] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [23] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [23] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [22] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [22] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [21] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [21] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [20] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [20] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [19] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [19] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [18] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [18] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [17] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [17] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [16] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [16] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [15] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [15] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [14] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [14] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [13] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [13] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [12] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [12] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [11] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [11] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [10] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [10] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [9] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [9] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [8] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [8] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [7] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [7] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [6] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [6] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [5] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [5] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 csr2rst_port_ctrl [63] "logic csr2rst_port_ctrl[63:0]" +Toggle 0to1 csr2rst_port_ctrl [63] "logic csr2rst_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [2] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [2] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [1] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [1] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [62] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [62] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [61] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [61] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [60] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [60] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [59] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [59] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [58] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [58] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [57] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [57] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [56] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [56] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [55] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [55] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [54] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [54] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [53] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [53] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [52] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [52] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [51] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [51] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [50] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [50] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [49] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [49] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [48] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [48] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [47] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [47] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [46] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [46] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [45] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [45] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [44] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [44] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [43] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [43] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [42] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [42] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [41] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [41] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [40] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [40] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [39] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [39] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [38] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [38] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [37] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [37] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [36] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [36] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [35] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [35] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [34] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [34] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [33] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [33] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [32] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [32] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [31] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [31] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [30] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [30] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [29] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [29] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [28] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [28] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [27] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [27] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [26] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [26] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [25] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [25] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [24] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [24] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [23] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [23] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [22] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [22] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [21] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [21] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [20] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [20] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [19] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [19] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [18] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [18] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [17] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [17] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [16] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [16] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [15] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [15] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [14] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [14] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [13] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [13] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [12] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [12] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [11] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [11] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [10] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [10] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [9] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [9] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [8] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [8] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [7] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [7] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [6] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [6] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [5] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [5] "logic rst2csr_port_ctrl[63:0]" +Toggle 1to0 rst2csr_port_ctrl [63] "logic rst2csr_port_ctrl[63:0]" +Toggle 0to1 rst2csr_port_ctrl [63] "logic rst2csr_port_ctrl[63:0]" +ANNOTATION: " Unused code hence excluded " +Toggle pcie_p2c_sideband.flr_rcvd_pf_num "logic pcie_p2c_sideband.flr_rcvd_pf_num[0:0]" +Toggle 1to0 pcie_p2c_sideband.flr_rcvd_vf "logic pcie_p2c_sideband.flr_rcvd_vf" +Toggle 0to1 pcie_p2c_sideband.flr_rcvd_vf "logic pcie_p2c_sideband.flr_rcvd_vf" +ANNOTATION: " Unused code hence excluded " +Toggle pcie_p2c_sideband.flr_rcvd_vf_num "logic pcie_p2c_sideband.flr_rcvd_vf_num[1:0]" +ANNOTATION: " Ro and reserved fields " +Toggle user_clk_freq_sts_1 "logic user_clk_freq_sts_1[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [1] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [1] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [2] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [2] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [3] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [3] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [4] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [4] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [5] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [5] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [6] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [6] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [7] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [7] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [32] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [32] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [33] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [33] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [34] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [34] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [35] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [35] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [36] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [36] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [37] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [37] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [38] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [38] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [39] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [39] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [40] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [40] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [41] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [41] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [44] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [44] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [48] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [48] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [49] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [49] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [52] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [52] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [56] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [56] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [57] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [57] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [60] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [60] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [0] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [0] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 uclk_div2 "logic uclk_div2" +Toggle 0to1 uclk_div2 "logic uclk_div2" +Toggle 0to1 user_clk_freq_sts_0 [63] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [63] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [8] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [8] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [9] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [9] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [10] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [10] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [11] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [11] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [12] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [12] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [13] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [13] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [14] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [14] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [15] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [15] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [16] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [16] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [17] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [17] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [18] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [18] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [19] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [19] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [20] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [20] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [21] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [21] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [22] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [22] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [23] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [23] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [24] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [24] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [25] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [25] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [26] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [26] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [27] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [27] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [28] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [28] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [29] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [29] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [30] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [30] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [31] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [31] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [42] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [42] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [43] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [43] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [45] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [45] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [46] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [46] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [47] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [47] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [50] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [50] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [51] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [51] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [53] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [53] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [54] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [54] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [55] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [55] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [58] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [58] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [59] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [59] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [61] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [61] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [62] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [62] "logic user_clk_freq_sts_0[63:0]" +ANNOTATION: " Remotestp feature simcov not neeeded,taken care at HW testing hence excluded " +Toggle remotestp_status_2x "logic remotestp_status_2x[63:0]" +ANNOTATION: " Remotestp feature simcov not neeeded,taken care at HW testing hence excluded " +Toggle remotestp_status_100 "logic remotestp_status_100[63:0]" +Toggle 0to1 o_sr2pr_tckena "logic o_sr2pr_tckena" +Toggle 1to0 o_sr2pr_tckena "logic o_sr2pr_tckena" +Toggle 0to1 o_sr2pr_tms "logic o_sr2pr_tms" +Toggle 1to0 o_sr2pr_tms "logic o_sr2pr_tms" +Toggle 0to1 o_sr2pr_tdi "logic o_sr2pr_tdi" +Toggle 1to0 o_sr2pr_tdi "logic o_sr2pr_tdi" +CHECKSUM: "2221342403 313161863" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot +Branch 0 "3382341477" "pr_freeze_fnmx_q1" (0) "pr_freeze_fnmx_q1 1" +Branch 1 "3382341477" "pr_freeze_fnmx_q1" (0) "pr_freeze_fnmx_q1 1" +Branch 2 "3382341477" "pr_freeze_fnmx_q1" (0) "pr_freeze_fnmx_q1 1" +Branch 3 "3382341477" "pr_freeze_fnmx_q1" (0) "pr_freeze_fnmx_q1 1" +Branch 4 "803207236" "pr_freeze_fnmx_q1" (0) "pr_freeze_fnmx_q1 1" +Branch 5 "803207236" "pr_freeze_fnmx_q1" (0) "pr_freeze_fnmx_q1 1" +Branch 6 "803207236" "pr_freeze_fnmx_q1" (0) "pr_freeze_fnmx_q1 1" +Branch 7 "803207236" "pr_freeze_fnmx_q1" (0) "pr_freeze_fnmx_q1 1" +Branch 8 "1178541779" "pr_freeze_emif[0]" (0) "pr_freeze_emif[0] 1" +Branch 9 "3786001500" "pr_freeze_emif[1]" (0) "pr_freeze_emif[1] 1" +CHECKSUM: "3468691583 788362483" +INSTANCE: tb_top.DUT.afu_top.port_gasket.user_clock.qph_user_clk +Toggle 1to0 user_clk_freq_sts_0 [62] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [62] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [61] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [61] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [59] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [59] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [58] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [58] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [55] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [55] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [54] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [54] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [53] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [53] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [51] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [51] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [50] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [50] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [47] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [47] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [46] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [46] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [45] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [45] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [43] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [43] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [42] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [42] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [63] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [63] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [62] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [62] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [61] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [61] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [60] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [60] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [59] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [59] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [58] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [58] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [57] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [57] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [56] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [56] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [55] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [55] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [54] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [54] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [53] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [53] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [52] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [52] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [51] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [51] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [50] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [50] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [49] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [49] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [48] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [48] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [47] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [47] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [46] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [46] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [45] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [45] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [44] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [44] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [43] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [43] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [42] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [42] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [41] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [41] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [40] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [40] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [39] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [39] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [38] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [38] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [37] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [37] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [36] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [36] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [35] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [35] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [34] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [34] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [33] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [33] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [31] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [31] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [30] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [30] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [29] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [29] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [28] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [28] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [27] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [27] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [26] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [26] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [25] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [25] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [24] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [24] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [23] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [23] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [22] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [22] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [21] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [21] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [20] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [20] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [19] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [19] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [18] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [18] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [17] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [17] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [16] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [16] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [15] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [15] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [14] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [14] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [13] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [13] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [12] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [12] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [11] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [11] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [10] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [10] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [9] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [9] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [8] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [8] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [7] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [7] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [6] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [6] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [5] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [5] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [4] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [4] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [3] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [3] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [2] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [2] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [1] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [1] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_1 [63] "net user_clk_freq_cmd_1[63:0]" +Toggle 0to1 user_clk_freq_cmd_1 [63] "net user_clk_freq_cmd_1[63:0]" +Toggle 1to0 user_clk_freq_cmd_0 [62] "net user_clk_freq_cmd_0[63:0]" +Toggle 0to1 user_clk_freq_cmd_0 [62] "net user_clk_freq_cmd_0[63:0]" +Toggle 1to0 user_clk_freq_cmd_0 [61] "net user_clk_freq_cmd_0[63:0]" +Toggle 0to1 user_clk_freq_cmd_0 [61] "net user_clk_freq_cmd_0[63:0]" +Toggle 1to0 user_clk_freq_cmd_0 [60] "net user_clk_freq_cmd_0[63:0]" +Toggle 0to1 user_clk_freq_cmd_0 [60] "net user_clk_freq_cmd_0[63:0]" +Toggle 1to0 user_clk_freq_cmd_0 [59] "net user_clk_freq_cmd_0[63:0]" +Toggle 0to1 user_clk_freq_cmd_0 [59] "net user_clk_freq_cmd_0[63:0]" +Toggle 1to0 user_clk_freq_cmd_0 [58] "net user_clk_freq_cmd_0[63:0]" +Toggle 0to1 user_clk_freq_cmd_0 [58] "net user_clk_freq_cmd_0[63:0]" +Toggle 1to0 user_clk_freq_cmd_0 [55] "net user_clk_freq_cmd_0[63:0]" +Toggle 0to1 user_clk_freq_cmd_0 [55] "net user_clk_freq_cmd_0[63:0]" +Toggle 1to0 user_clk_freq_cmd_0 [54] "net user_clk_freq_cmd_0[63:0]" +Toggle 0to1 user_clk_freq_cmd_0 [54] "net user_clk_freq_cmd_0[63:0]" +Toggle 1to0 user_clk_freq_cmd_0 [53] "net user_clk_freq_cmd_0[63:0]" +Toggle 0to1 user_clk_freq_cmd_0 [53] "net user_clk_freq_cmd_0[63:0]" +Toggle 1to0 user_clk_freq_cmd_0 [51] "net user_clk_freq_cmd_0[63:0]" +Toggle 0to1 user_clk_freq_cmd_0 [51] "net user_clk_freq_cmd_0[63:0]" +Toggle 1to0 user_clk_freq_cmd_0 [50] "net user_clk_freq_cmd_0[63:0]" +Toggle 0to1 user_clk_freq_cmd_0 [50] "net user_clk_freq_cmd_0[63:0]" +Toggle 1to0 user_clk_freq_cmd_0 [47] "net user_clk_freq_cmd_0[63:0]" +Toggle 0to1 user_clk_freq_cmd_0 [47] "net user_clk_freq_cmd_0[63:0]" +Toggle 1to0 user_clk_freq_cmd_0 [46] "net user_clk_freq_cmd_0[63:0]" +Toggle 0to1 user_clk_freq_cmd_0 [46] "net user_clk_freq_cmd_0[63:0]" +Toggle 1to0 user_clk_freq_cmd_0 [45] "net user_clk_freq_cmd_0[63:0]" +Toggle 0to1 user_clk_freq_cmd_0 [45] "net user_clk_freq_cmd_0[63:0]" +Toggle 1to0 user_clk_freq_cmd_0 [43] "net user_clk_freq_cmd_0[63:0]" +Toggle 0to1 user_clk_freq_cmd_0 [43] "net user_clk_freq_cmd_0[63:0]" +Toggle 1to0 user_clk_freq_cmd_0 [42] "net user_clk_freq_cmd_0[63:0]" +Toggle 0to1 user_clk_freq_cmd_0 [42] "net user_clk_freq_cmd_0[63:0]" +Toggle 1to0 user_clk_freq_cmd_0 [63] "net user_clk_freq_cmd_0[63:0]" +Toggle 0to1 user_clk_freq_cmd_0 [63] "net user_clk_freq_cmd_0[63:0]" +CHECKSUM: "3021715206 3213032206" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he2mem_if +Toggle 1to0 byteenable [70] "logic byteenable[71:0]" +Toggle 0to1 byteenable [70] "logic byteenable[71:0]" +Toggle 1to0 byteenable [69] "logic byteenable[71:0]" +Toggle 0to1 byteenable [69] "logic byteenable[71:0]" +Toggle 1to0 byteenable [68] "logic byteenable[71:0]" +Toggle 0to1 byteenable [68] "logic byteenable[71:0]" +Toggle 1to0 byteenable [67] "logic byteenable[71:0]" +Toggle 0to1 byteenable [67] "logic byteenable[71:0]" +Toggle 1to0 byteenable [66] "logic byteenable[71:0]" +Toggle 0to1 byteenable [66] "logic byteenable[71:0]" +Toggle 1to0 byteenable [65] "logic byteenable[71:0]" +Toggle 0to1 byteenable [65] "logic byteenable[71:0]" +Toggle 1to0 byteenable [64] "logic byteenable[71:0]" +Toggle 0to1 byteenable [64] "logic byteenable[71:0]" +Toggle 1to0 byteenable [63] "logic byteenable[71:0]" +Toggle 0to1 byteenable [63] "logic byteenable[71:0]" +Toggle 1to0 byteenable [62] "logic byteenable[71:0]" +Toggle 0to1 byteenable [62] "logic byteenable[71:0]" +Toggle 1to0 byteenable [61] "logic byteenable[71:0]" +Toggle 0to1 byteenable [61] "logic byteenable[71:0]" +Toggle 1to0 byteenable [60] "logic byteenable[71:0]" +Toggle 0to1 byteenable [60] "logic byteenable[71:0]" +Toggle 1to0 byteenable [59] "logic byteenable[71:0]" +Toggle 0to1 byteenable [59] "logic byteenable[71:0]" +Toggle 1to0 byteenable [58] "logic byteenable[71:0]" +Toggle 0to1 byteenable [58] "logic byteenable[71:0]" +Toggle 1to0 byteenable [57] "logic byteenable[71:0]" +Toggle 0to1 byteenable [57] "logic byteenable[71:0]" +Toggle 1to0 byteenable [56] "logic byteenable[71:0]" +Toggle 0to1 byteenable [56] "logic byteenable[71:0]" +Toggle 1to0 byteenable [55] "logic byteenable[71:0]" +Toggle 0to1 byteenable [55] "logic byteenable[71:0]" +Toggle 1to0 byteenable [54] "logic byteenable[71:0]" +Toggle 0to1 byteenable [54] "logic byteenable[71:0]" +Toggle 1to0 byteenable [53] "logic byteenable[71:0]" +Toggle 0to1 byteenable [53] "logic byteenable[71:0]" +Toggle 1to0 byteenable [52] "logic byteenable[71:0]" +Toggle 0to1 byteenable [52] "logic byteenable[71:0]" +Toggle 1to0 byteenable [51] "logic byteenable[71:0]" +Toggle 0to1 byteenable [51] "logic byteenable[71:0]" +Toggle 1to0 byteenable [50] "logic byteenable[71:0]" +Toggle 0to1 byteenable [50] "logic byteenable[71:0]" +Toggle 1to0 byteenable [49] "logic byteenable[71:0]" +Toggle 0to1 byteenable [49] "logic byteenable[71:0]" +Toggle 1to0 byteenable [48] "logic byteenable[71:0]" +Toggle 0to1 byteenable [48] "logic byteenable[71:0]" +Toggle 1to0 byteenable [47] "logic byteenable[71:0]" +Toggle 0to1 byteenable [47] "logic byteenable[71:0]" +Toggle 1to0 byteenable [46] "logic byteenable[71:0]" +Toggle 0to1 byteenable [46] "logic byteenable[71:0]" +Toggle 1to0 byteenable [45] "logic byteenable[71:0]" +Toggle 0to1 byteenable [45] "logic byteenable[71:0]" +Toggle 1to0 byteenable [44] "logic byteenable[71:0]" +Toggle 0to1 byteenable [44] "logic byteenable[71:0]" +Toggle 1to0 byteenable [43] "logic byteenable[71:0]" +Toggle 0to1 byteenable [43] "logic byteenable[71:0]" +Toggle 1to0 byteenable [42] "logic byteenable[71:0]" +Toggle 0to1 byteenable [42] "logic byteenable[71:0]" +Toggle 1to0 byteenable [41] "logic byteenable[71:0]" +Toggle 0to1 byteenable [41] "logic byteenable[71:0]" +Toggle 1to0 byteenable [40] "logic byteenable[71:0]" +Toggle 0to1 byteenable [40] "logic byteenable[71:0]" +Toggle 1to0 byteenable [39] "logic byteenable[71:0]" +Toggle 0to1 byteenable [39] "logic byteenable[71:0]" +Toggle 1to0 byteenable [38] "logic byteenable[71:0]" +Toggle 0to1 byteenable [38] "logic byteenable[71:0]" +Toggle 1to0 byteenable [37] "logic byteenable[71:0]" +Toggle 0to1 byteenable [37] "logic byteenable[71:0]" +Toggle 1to0 byteenable [36] "logic byteenable[71:0]" +Toggle 0to1 byteenable [36] "logic byteenable[71:0]" +Toggle 1to0 byteenable [35] "logic byteenable[71:0]" +Toggle 0to1 byteenable [35] "logic byteenable[71:0]" +Toggle 1to0 byteenable [34] "logic byteenable[71:0]" +Toggle 0to1 byteenable [34] "logic byteenable[71:0]" +Toggle 1to0 byteenable [33] "logic byteenable[71:0]" +Toggle 0to1 byteenable [33] "logic byteenable[71:0]" +Toggle 1to0 byteenable [32] "logic byteenable[71:0]" +Toggle 0to1 byteenable [32] "logic byteenable[71:0]" +Toggle 1to0 byteenable [31] "logic byteenable[71:0]" +Toggle 0to1 byteenable [31] "logic byteenable[71:0]" +Toggle 1to0 byteenable [30] "logic byteenable[71:0]" +Toggle 0to1 byteenable [30] "logic byteenable[71:0]" +Toggle 1to0 byteenable [29] "logic byteenable[71:0]" +Toggle 0to1 byteenable [29] "logic byteenable[71:0]" +Toggle 1to0 byteenable [28] "logic byteenable[71:0]" +Toggle 0to1 byteenable [28] "logic byteenable[71:0]" +Toggle 1to0 byteenable [27] "logic byteenable[71:0]" +Toggle 0to1 byteenable [27] "logic byteenable[71:0]" +Toggle 1to0 byteenable [26] "logic byteenable[71:0]" +Toggle 0to1 byteenable [26] "logic byteenable[71:0]" +Toggle 1to0 byteenable [25] "logic byteenable[71:0]" +Toggle 0to1 byteenable [25] "logic byteenable[71:0]" +Toggle 1to0 byteenable [24] "logic byteenable[71:0]" +Toggle 0to1 byteenable [24] "logic byteenable[71:0]" +Toggle 1to0 byteenable [23] "logic byteenable[71:0]" +Toggle 0to1 byteenable [23] "logic byteenable[71:0]" +Toggle 1to0 byteenable [22] "logic byteenable[71:0]" +Toggle 0to1 byteenable [22] "logic byteenable[71:0]" +Toggle 1to0 byteenable [21] "logic byteenable[71:0]" +Toggle 0to1 byteenable [21] "logic byteenable[71:0]" +Toggle 1to0 byteenable [20] "logic byteenable[71:0]" +Toggle 0to1 byteenable [20] "logic byteenable[71:0]" +Toggle 1to0 byteenable [19] "logic byteenable[71:0]" +Toggle 0to1 byteenable [19] "logic byteenable[71:0]" +Toggle 1to0 byteenable [18] "logic byteenable[71:0]" +Toggle 0to1 byteenable [18] "logic byteenable[71:0]" +Toggle 1to0 byteenable [17] "logic byteenable[71:0]" +Toggle 0to1 byteenable [17] "logic byteenable[71:0]" +Toggle 1to0 byteenable [16] "logic byteenable[71:0]" +Toggle 0to1 byteenable [16] "logic byteenable[71:0]" +Toggle 1to0 byteenable [15] "logic byteenable[71:0]" +Toggle 0to1 byteenable [15] "logic byteenable[71:0]" +Toggle 1to0 byteenable [14] "logic byteenable[71:0]" +Toggle 0to1 byteenable [14] "logic byteenable[71:0]" +Toggle 1to0 byteenable [13] "logic byteenable[71:0]" +Toggle 0to1 byteenable [13] "logic byteenable[71:0]" +Toggle 1to0 byteenable [12] "logic byteenable[71:0]" +Toggle 0to1 byteenable [12] "logic byteenable[71:0]" +Toggle 1to0 byteenable [11] "logic byteenable[71:0]" +Toggle 0to1 byteenable [11] "logic byteenable[71:0]" +Toggle 1to0 byteenable [10] "logic byteenable[71:0]" +Toggle 0to1 byteenable [10] "logic byteenable[71:0]" +Toggle 1to0 byteenable [9] "logic byteenable[71:0]" +Toggle 0to1 byteenable [9] "logic byteenable[71:0]" +Toggle 1to0 byteenable [8] "logic byteenable[71:0]" +Toggle 0to1 byteenable [8] "logic byteenable[71:0]" +Toggle 1to0 byteenable [7] "logic byteenable[71:0]" +Toggle 0to1 byteenable [7] "logic byteenable[71:0]" +Toggle 1to0 byteenable [6] "logic byteenable[71:0]" +Toggle 0to1 byteenable [6] "logic byteenable[71:0]" +Toggle 1to0 byteenable [5] "logic byteenable[71:0]" +Toggle 0to1 byteenable [5] "logic byteenable[71:0]" +Toggle 1to0 byteenable [4] "logic byteenable[71:0]" +Toggle 0to1 byteenable [4] "logic byteenable[71:0]" +Toggle 1to0 byteenable [3] "logic byteenable[71:0]" +Toggle 0to1 byteenable [3] "logic byteenable[71:0]" +Toggle 1to0 byteenable [2] "logic byteenable[71:0]" +Toggle 0to1 byteenable [2] "logic byteenable[71:0]" +Toggle 1to0 byteenable [1] "logic byteenable[71:0]" +Toggle 0to1 byteenable [1] "logic byteenable[71:0]" +Toggle 1to0 byteenable [0] "logic byteenable[71:0]" +Toggle 0to1 byteenable [0] "logic byteenable[71:0]" +Toggle 1to0 byteenable [71] "logic byteenable[71:0]" +Toggle 0to1 byteenable [71] "logic byteenable[71:0]" +Toggle 0to1 ecc_interrupt "logic ecc_interrupt" +Toggle 1to0 ecc_interrupt "logic ecc_interrupt" +Toggle 0to1 readdata [575] "logic readdata[575:0]" +Toggle 1to0 readdata [575] "logic readdata[575:0]" +Toggle 0to1 readdata [512] "logic readdata[575:0]" +Toggle 1to0 readdata [512] "logic readdata[575:0]" +Toggle 0to1 readdata [513] "logic readdata[575:0]" +Toggle 1to0 readdata [513] "logic readdata[575:0]" +Toggle 0to1 readdata [514] "logic readdata[575:0]" +Toggle 1to0 readdata [514] "logic readdata[575:0]" +Toggle 0to1 readdata [515] "logic readdata[575:0]" +Toggle 1to0 readdata [515] "logic readdata[575:0]" +Toggle 0to1 readdata [516] "logic readdata[575:0]" +Toggle 1to0 readdata [516] "logic readdata[575:0]" +Toggle 0to1 readdata [517] "logic readdata[575:0]" +Toggle 1to0 readdata [517] "logic readdata[575:0]" +Toggle 0to1 readdata [518] "logic readdata[575:0]" +Toggle 1to0 readdata [518] "logic readdata[575:0]" +Toggle 0to1 readdata [519] "logic readdata[575:0]" +Toggle 1to0 readdata [519] "logic readdata[575:0]" +Toggle 0to1 readdata [520] "logic readdata[575:0]" +Toggle 1to0 readdata [520] "logic readdata[575:0]" +Toggle 0to1 readdata [521] "logic readdata[575:0]" +Toggle 1to0 readdata [521] "logic readdata[575:0]" +Toggle 0to1 readdata [522] "logic readdata[575:0]" +Toggle 1to0 readdata [522] "logic readdata[575:0]" +Toggle 0to1 readdata [523] "logic readdata[575:0]" +Toggle 1to0 readdata [523] "logic readdata[575:0]" +Toggle 0to1 readdata [524] "logic readdata[575:0]" +Toggle 1to0 readdata [524] "logic readdata[575:0]" +Toggle 0to1 readdata [525] "logic readdata[575:0]" +Toggle 1to0 readdata [525] "logic readdata[575:0]" +Toggle 0to1 readdata [526] "logic readdata[575:0]" +Toggle 1to0 readdata [526] "logic readdata[575:0]" +Toggle 0to1 readdata [527] "logic readdata[575:0]" +Toggle 1to0 readdata [527] "logic readdata[575:0]" +Toggle 0to1 readdata [528] "logic readdata[575:0]" +Toggle 1to0 readdata [528] "logic readdata[575:0]" +Toggle 0to1 readdata [529] "logic readdata[575:0]" +Toggle 1to0 readdata [529] "logic readdata[575:0]" +Toggle 0to1 readdata [530] "logic readdata[575:0]" +Toggle 1to0 readdata [530] "logic readdata[575:0]" +Toggle 0to1 readdata [531] "logic readdata[575:0]" +Toggle 1to0 readdata [531] "logic readdata[575:0]" +Toggle 0to1 readdata [532] "logic readdata[575:0]" +Toggle 1to0 readdata [532] "logic readdata[575:0]" +Toggle 0to1 readdata [533] "logic readdata[575:0]" +Toggle 1to0 readdata [533] "logic readdata[575:0]" +Toggle 0to1 readdata [534] "logic readdata[575:0]" +Toggle 1to0 readdata [534] "logic readdata[575:0]" +Toggle 0to1 readdata [535] "logic readdata[575:0]" +Toggle 1to0 readdata [535] "logic readdata[575:0]" +Toggle 0to1 readdata [536] "logic readdata[575:0]" +Toggle 1to0 readdata [536] "logic readdata[575:0]" +Toggle 0to1 readdata [537] "logic readdata[575:0]" +Toggle 1to0 readdata [537] "logic readdata[575:0]" +Toggle 0to1 readdata [538] "logic readdata[575:0]" +Toggle 1to0 readdata [538] "logic readdata[575:0]" +Toggle 0to1 readdata [539] "logic readdata[575:0]" +Toggle 1to0 readdata [539] "logic readdata[575:0]" +Toggle 0to1 readdata [540] "logic readdata[575:0]" +Toggle 1to0 readdata [540] "logic readdata[575:0]" +Toggle 0to1 readdata [541] "logic readdata[575:0]" +Toggle 1to0 readdata [541] "logic readdata[575:0]" +Toggle 0to1 readdata [542] "logic readdata[575:0]" +Toggle 1to0 readdata [542] "logic readdata[575:0]" +Toggle 0to1 readdata [543] "logic readdata[575:0]" +Toggle 1to0 readdata [543] "logic readdata[575:0]" +Toggle 0to1 readdata [544] "logic readdata[575:0]" +Toggle 1to0 readdata [544] "logic readdata[575:0]" +Toggle 0to1 readdata [545] "logic readdata[575:0]" +Toggle 1to0 readdata [545] "logic readdata[575:0]" +Toggle 0to1 readdata [546] "logic readdata[575:0]" +Toggle 1to0 readdata [546] "logic readdata[575:0]" +Toggle 0to1 readdata [547] "logic readdata[575:0]" +Toggle 1to0 readdata [547] "logic readdata[575:0]" +Toggle 0to1 readdata [548] "logic readdata[575:0]" +Toggle 1to0 readdata [548] "logic readdata[575:0]" +Toggle 0to1 readdata [549] "logic readdata[575:0]" +Toggle 1to0 readdata [549] "logic readdata[575:0]" +Toggle 0to1 readdata [550] "logic readdata[575:0]" +Toggle 1to0 readdata [550] "logic readdata[575:0]" +Toggle 0to1 readdata [551] "logic readdata[575:0]" +Toggle 1to0 readdata [551] "logic readdata[575:0]" +Toggle 0to1 readdata [552] "logic readdata[575:0]" +Toggle 1to0 readdata [552] "logic readdata[575:0]" +Toggle 0to1 readdata [553] "logic readdata[575:0]" +Toggle 1to0 readdata [553] "logic readdata[575:0]" +Toggle 0to1 readdata [554] "logic readdata[575:0]" +Toggle 1to0 readdata [554] "logic readdata[575:0]" +Toggle 0to1 readdata [555] "logic readdata[575:0]" +Toggle 1to0 readdata [555] "logic readdata[575:0]" +Toggle 0to1 readdata [556] "logic readdata[575:0]" +Toggle 1to0 readdata [556] "logic readdata[575:0]" +Toggle 0to1 readdata [557] "logic readdata[575:0]" +Toggle 1to0 readdata [557] "logic readdata[575:0]" +Toggle 0to1 readdata [558] "logic readdata[575:0]" +Toggle 1to0 readdata [558] "logic readdata[575:0]" +Toggle 0to1 readdata [559] "logic readdata[575:0]" +Toggle 1to0 readdata [559] "logic readdata[575:0]" +Toggle 0to1 readdata [560] "logic readdata[575:0]" +Toggle 1to0 readdata [560] "logic readdata[575:0]" +Toggle 0to1 readdata [561] "logic readdata[575:0]" +Toggle 1to0 readdata [561] "logic readdata[575:0]" +Toggle 0to1 readdata [562] "logic readdata[575:0]" +Toggle 1to0 readdata [562] "logic readdata[575:0]" +Toggle 0to1 readdata [563] "logic readdata[575:0]" +Toggle 1to0 readdata [563] "logic readdata[575:0]" +Toggle 0to1 readdata [564] "logic readdata[575:0]" +Toggle 1to0 readdata [564] "logic readdata[575:0]" +Toggle 0to1 readdata [565] "logic readdata[575:0]" +Toggle 1to0 readdata [565] "logic readdata[575:0]" +Toggle 0to1 readdata [566] "logic readdata[575:0]" +Toggle 1to0 readdata [566] "logic readdata[575:0]" +Toggle 0to1 readdata [567] "logic readdata[575:0]" +Toggle 1to0 readdata [567] "logic readdata[575:0]" +Toggle 0to1 readdata [568] "logic readdata[575:0]" +Toggle 1to0 readdata [568] "logic readdata[575:0]" +Toggle 0to1 readdata [569] "logic readdata[575:0]" +Toggle 1to0 readdata [569] "logic readdata[575:0]" +Toggle 0to1 readdata [570] "logic readdata[575:0]" +Toggle 1to0 readdata [570] "logic readdata[575:0]" +Toggle 0to1 readdata [571] "logic readdata[575:0]" +Toggle 1to0 readdata [571] "logic readdata[575:0]" +Toggle 0to1 readdata [572] "logic readdata[575:0]" +Toggle 1to0 readdata [572] "logic readdata[575:0]" +Toggle 0to1 readdata [573] "logic readdata[575:0]" +Toggle 1to0 readdata [573] "logic readdata[575:0]" +Toggle 0to1 readdata [574] "logic readdata[575:0]" +Toggle 1to0 readdata [574] "logic readdata[575:0]" +Toggle 0to1 writedata [575] "logic writedata[575:0]" +Toggle 1to0 writedata [575] "logic writedata[575:0]" +Toggle 0to1 writedata [512] "logic writedata[575:0]" +Toggle 1to0 writedata [512] "logic writedata[575:0]" +Toggle 0to1 writedata [513] "logic writedata[575:0]" +Toggle 1to0 writedata [513] "logic writedata[575:0]" +Toggle 0to1 writedata [514] "logic writedata[575:0]" +Toggle 1to0 writedata [514] "logic writedata[575:0]" +Toggle 0to1 writedata [515] "logic writedata[575:0]" +Toggle 1to0 writedata [515] "logic writedata[575:0]" +Toggle 0to1 writedata [516] "logic writedata[575:0]" +Toggle 1to0 writedata [516] "logic writedata[575:0]" +Toggle 0to1 writedata [517] "logic writedata[575:0]" +Toggle 1to0 writedata [517] "logic writedata[575:0]" +Toggle 0to1 writedata [518] "logic writedata[575:0]" +Toggle 1to0 writedata [518] "logic writedata[575:0]" +Toggle 0to1 writedata [519] "logic writedata[575:0]" +Toggle 1to0 writedata [519] "logic writedata[575:0]" +Toggle 0to1 writedata [520] "logic writedata[575:0]" +Toggle 1to0 writedata [520] "logic writedata[575:0]" +Toggle 0to1 writedata [521] "logic writedata[575:0]" +Toggle 1to0 writedata [521] "logic writedata[575:0]" +Toggle 0to1 writedata [522] "logic writedata[575:0]" +Toggle 1to0 writedata [522] "logic writedata[575:0]" +Toggle 0to1 writedata [523] "logic writedata[575:0]" +Toggle 1to0 writedata [523] "logic writedata[575:0]" +Toggle 0to1 writedata [524] "logic writedata[575:0]" +Toggle 1to0 writedata [524] "logic writedata[575:0]" +Toggle 0to1 writedata [525] "logic writedata[575:0]" +Toggle 1to0 writedata [525] "logic writedata[575:0]" +Toggle 0to1 writedata [526] "logic writedata[575:0]" +Toggle 1to0 writedata [526] "logic writedata[575:0]" +Toggle 0to1 writedata [527] "logic writedata[575:0]" +Toggle 1to0 writedata [527] "logic writedata[575:0]" +Toggle 0to1 writedata [528] "logic writedata[575:0]" +Toggle 1to0 writedata [528] "logic writedata[575:0]" +Toggle 0to1 writedata [529] "logic writedata[575:0]" +Toggle 1to0 writedata [529] "logic writedata[575:0]" +Toggle 0to1 writedata [530] "logic writedata[575:0]" +Toggle 1to0 writedata [530] "logic writedata[575:0]" +Toggle 0to1 writedata [531] "logic writedata[575:0]" +Toggle 1to0 writedata [531] "logic writedata[575:0]" +Toggle 0to1 writedata [532] "logic writedata[575:0]" +Toggle 1to0 writedata [532] "logic writedata[575:0]" +Toggle 0to1 writedata [533] "logic writedata[575:0]" +Toggle 1to0 writedata [533] "logic writedata[575:0]" +Toggle 0to1 writedata [534] "logic writedata[575:0]" +Toggle 1to0 writedata [534] "logic writedata[575:0]" +Toggle 0to1 writedata [535] "logic writedata[575:0]" +Toggle 1to0 writedata [535] "logic writedata[575:0]" +Toggle 0to1 writedata [536] "logic writedata[575:0]" +Toggle 1to0 writedata [536] "logic writedata[575:0]" +Toggle 0to1 writedata [537] "logic writedata[575:0]" +Toggle 1to0 writedata [537] "logic writedata[575:0]" +Toggle 0to1 writedata [538] "logic writedata[575:0]" +Toggle 1to0 writedata [538] "logic writedata[575:0]" +Toggle 0to1 writedata [539] "logic writedata[575:0]" +Toggle 1to0 writedata [539] "logic writedata[575:0]" +Toggle 0to1 writedata [540] "logic writedata[575:0]" +Toggle 1to0 writedata [540] "logic writedata[575:0]" +Toggle 0to1 writedata [541] "logic writedata[575:0]" +Toggle 1to0 writedata [541] "logic writedata[575:0]" +Toggle 0to1 writedata [542] "logic writedata[575:0]" +Toggle 1to0 writedata [542] "logic writedata[575:0]" +Toggle 0to1 writedata [543] "logic writedata[575:0]" +Toggle 1to0 writedata [543] "logic writedata[575:0]" +Toggle 0to1 writedata [544] "logic writedata[575:0]" +Toggle 1to0 writedata [544] "logic writedata[575:0]" +Toggle 0to1 writedata [545] "logic writedata[575:0]" +Toggle 1to0 writedata [545] "logic writedata[575:0]" +Toggle 0to1 writedata [546] "logic writedata[575:0]" +Toggle 1to0 writedata [546] "logic writedata[575:0]" +Toggle 0to1 writedata [547] "logic writedata[575:0]" +Toggle 1to0 writedata [547] "logic writedata[575:0]" +Toggle 0to1 writedata [548] "logic writedata[575:0]" +Toggle 1to0 writedata [548] "logic writedata[575:0]" +Toggle 0to1 writedata [549] "logic writedata[575:0]" +Toggle 1to0 writedata [549] "logic writedata[575:0]" +Toggle 0to1 writedata [550] "logic writedata[575:0]" +Toggle 1to0 writedata [550] "logic writedata[575:0]" +Toggle 0to1 writedata [551] "logic writedata[575:0]" +Toggle 1to0 writedata [551] "logic writedata[575:0]" +Toggle 0to1 writedata [552] "logic writedata[575:0]" +Toggle 1to0 writedata [552] "logic writedata[575:0]" +Toggle 0to1 writedata [553] "logic writedata[575:0]" +Toggle 1to0 writedata [553] "logic writedata[575:0]" +Toggle 0to1 writedata [554] "logic writedata[575:0]" +Toggle 1to0 writedata [554] "logic writedata[575:0]" +Toggle 0to1 writedata [555] "logic writedata[575:0]" +Toggle 1to0 writedata [555] "logic writedata[575:0]" +Toggle 0to1 writedata [556] "logic writedata[575:0]" +Toggle 1to0 writedata [556] "logic writedata[575:0]" +Toggle 0to1 writedata [557] "logic writedata[575:0]" +Toggle 1to0 writedata [557] "logic writedata[575:0]" +Toggle 0to1 writedata [558] "logic writedata[575:0]" +Toggle 1to0 writedata [558] "logic writedata[575:0]" +Toggle 0to1 writedata [559] "logic writedata[575:0]" +Toggle 1to0 writedata [559] "logic writedata[575:0]" +Toggle 0to1 writedata [560] "logic writedata[575:0]" +Toggle 1to0 writedata [560] "logic writedata[575:0]" +Toggle 0to1 writedata [561] "logic writedata[575:0]" +Toggle 1to0 writedata [561] "logic writedata[575:0]" +Toggle 0to1 writedata [562] "logic writedata[575:0]" +Toggle 1to0 writedata [562] "logic writedata[575:0]" +Toggle 0to1 writedata [563] "logic writedata[575:0]" +Toggle 1to0 writedata [563] "logic writedata[575:0]" +Toggle 0to1 writedata [564] "logic writedata[575:0]" +Toggle 1to0 writedata [564] "logic writedata[575:0]" +Toggle 0to1 writedata [565] "logic writedata[575:0]" +Toggle 1to0 writedata [565] "logic writedata[575:0]" +Toggle 0to1 writedata [566] "logic writedata[575:0]" +Toggle 1to0 writedata [566] "logic writedata[575:0]" +Toggle 0to1 writedata [567] "logic writedata[575:0]" +Toggle 1to0 writedata [567] "logic writedata[575:0]" +Toggle 0to1 writedata [568] "logic writedata[575:0]" +Toggle 1to0 writedata [568] "logic writedata[575:0]" +Toggle 0to1 writedata [569] "logic writedata[575:0]" +Toggle 1to0 writedata [569] "logic writedata[575:0]" +Toggle 0to1 writedata [570] "logic writedata[575:0]" +Toggle 1to0 writedata [570] "logic writedata[575:0]" +Toggle 0to1 writedata [571] "logic writedata[575:0]" +Toggle 1to0 writedata [571] "logic writedata[575:0]" +Toggle 0to1 writedata [572] "logic writedata[575:0]" +Toggle 1to0 writedata [572] "logic writedata[575:0]" +Toggle 0to1 writedata [573] "logic writedata[575:0]" +Toggle 1to0 writedata [573] "logic writedata[575:0]" +Toggle 0to1 writedata [574] "logic writedata[575:0]" +Toggle 1to0 writedata [574] "logic writedata[575:0]" +Toggle 0to1 burstcount [6] "logic burstcount[6:0]" +Toggle 1to0 burstcount [6] "logic burstcount[6:0]" +Toggle 0to1 burstcount [3] "logic burstcount[6:0]" +Toggle 1to0 burstcount [3] "logic burstcount[6:0]" +Toggle 0to1 burstcount [4] "logic burstcount[6:0]" +Toggle 1to0 burstcount [4] "logic burstcount[6:0]" +Toggle 0to1 burstcount [5] "logic burstcount[6:0]" +Toggle 1to0 burstcount [5] "logic burstcount[6:0]" +Toggle 0to1 address [26] "logic address[26:0]" +Toggle 1to0 address [26] "logic address[26:0]" +Toggle 0to1 address [11] "logic address[26:0]" +Toggle 1to0 address [11] "logic address[26:0]" +Toggle 0to1 address [12] "logic address[26:0]" +Toggle 1to0 address [12] "logic address[26:0]" +Toggle 0to1 address [13] "logic address[26:0]" +Toggle 1to0 address [13] "logic address[26:0]" +Toggle 0to1 address [14] "logic address[26:0]" +Toggle 1to0 address [14] "logic address[26:0]" +Toggle 0to1 address [15] "logic address[26:0]" +Toggle 1to0 address [15] "logic address[26:0]" +Toggle 0to1 address [16] "logic address[26:0]" +Toggle 1to0 address [16] "logic address[26:0]" +Toggle 0to1 address [17] "logic address[26:0]" +Toggle 1to0 address [17] "logic address[26:0]" +Toggle 0to1 address [18] "logic address[26:0]" +Toggle 1to0 address [18] "logic address[26:0]" +Toggle 0to1 address [19] "logic address[26:0]" +Toggle 1to0 address [19] "logic address[26:0]" +Toggle 0to1 address [20] "logic address[26:0]" +Toggle 1to0 address [20] "logic address[26:0]" +Toggle 0to1 address [21] "logic address[26:0]" +Toggle 1to0 address [21] "logic address[26:0]" +Toggle 0to1 address [22] "logic address[26:0]" +Toggle 1to0 address [22] "logic address[26:0]" +Toggle 0to1 address [23] "logic address[26:0]" +Toggle 1to0 address [23] "logic address[26:0]" +Toggle 0to1 address [24] "logic address[26:0]" +Toggle 1to0 address [24] "logic address[26:0]" +Toggle 0to1 address [25] "logic address[26:0]" +Toggle 1to0 address [25] "logic address[26:0]" +CHECKSUM: "3021715206 3213032206" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.mem_reg_if[1] +Toggle 1to0 burstcount [1] "logic burstcount[6:0]" +Toggle 1to0 burstcount [0] "logic burstcount[6:0]" +Toggle 1to0 burstcount [2] "logic burstcount[6:0]" +Toggle 1to0 byteenable [62] "logic byteenable[71:0]" +Toggle 1to0 byteenable [61] "logic byteenable[71:0]" +Toggle 1to0 byteenable [60] "logic byteenable[71:0]" +Toggle 1to0 byteenable [59] "logic byteenable[71:0]" +Toggle 1to0 byteenable [58] "logic byteenable[71:0]" +Toggle 1to0 byteenable [57] "logic byteenable[71:0]" +Toggle 1to0 byteenable [56] "logic byteenable[71:0]" +Toggle 1to0 byteenable [55] "logic byteenable[71:0]" +Toggle 1to0 byteenable [54] "logic byteenable[71:0]" +Toggle 1to0 byteenable [53] "logic byteenable[71:0]" +Toggle 1to0 byteenable [52] "logic byteenable[71:0]" +Toggle 1to0 byteenable [51] "logic byteenable[71:0]" +Toggle 1to0 byteenable [50] "logic byteenable[71:0]" +Toggle 1to0 byteenable [49] "logic byteenable[71:0]" +Toggle 1to0 byteenable [48] "logic byteenable[71:0]" +Toggle 1to0 byteenable [47] "logic byteenable[71:0]" +Toggle 1to0 byteenable [46] "logic byteenable[71:0]" +Toggle 1to0 byteenable [45] "logic byteenable[71:0]" +Toggle 1to0 byteenable [44] "logic byteenable[71:0]" +Toggle 1to0 byteenable [43] "logic byteenable[71:0]" +Toggle 1to0 byteenable [42] "logic byteenable[71:0]" +Toggle 1to0 byteenable [41] "logic byteenable[71:0]" +Toggle 1to0 byteenable [40] "logic byteenable[71:0]" +Toggle 1to0 byteenable [39] "logic byteenable[71:0]" +Toggle 1to0 byteenable [38] "logic byteenable[71:0]" +Toggle 1to0 byteenable [37] "logic byteenable[71:0]" +Toggle 1to0 byteenable [36] "logic byteenable[71:0]" +Toggle 1to0 byteenable [35] "logic byteenable[71:0]" +Toggle 1to0 byteenable [34] "logic byteenable[71:0]" +Toggle 1to0 byteenable [33] "logic byteenable[71:0]" +Toggle 1to0 byteenable [32] "logic byteenable[71:0]" +Toggle 1to0 byteenable [31] "logic byteenable[71:0]" +Toggle 1to0 byteenable [30] "logic byteenable[71:0]" +Toggle 1to0 byteenable [29] "logic byteenable[71:0]" +Toggle 1to0 byteenable [28] "logic byteenable[71:0]" +Toggle 1to0 byteenable [27] "logic byteenable[71:0]" +Toggle 1to0 byteenable [26] "logic byteenable[71:0]" +Toggle 1to0 byteenable [25] "logic byteenable[71:0]" +Toggle 1to0 byteenable [24] "logic byteenable[71:0]" +Toggle 1to0 byteenable [23] "logic byteenable[71:0]" +Toggle 1to0 byteenable [22] "logic byteenable[71:0]" +Toggle 1to0 byteenable [21] "logic byteenable[71:0]" +Toggle 1to0 byteenable [20] "logic byteenable[71:0]" +Toggle 1to0 byteenable [19] "logic byteenable[71:0]" +Toggle 1to0 byteenable [18] "logic byteenable[71:0]" +Toggle 1to0 byteenable [17] "logic byteenable[71:0]" +Toggle 1to0 byteenable [16] "logic byteenable[71:0]" +Toggle 1to0 byteenable [15] "logic byteenable[71:0]" +Toggle 1to0 byteenable [14] "logic byteenable[71:0]" +Toggle 1to0 byteenable [13] "logic byteenable[71:0]" +Toggle 1to0 byteenable [12] "logic byteenable[71:0]" +Toggle 1to0 byteenable [11] "logic byteenable[71:0]" +Toggle 1to0 byteenable [10] "logic byteenable[71:0]" +Toggle 1to0 byteenable [9] "logic byteenable[71:0]" +Toggle 1to0 byteenable [8] "logic byteenable[71:0]" +Toggle 1to0 byteenable [7] "logic byteenable[71:0]" +Toggle 1to0 byteenable [6] "logic byteenable[71:0]" +Toggle 1to0 byteenable [5] "logic byteenable[71:0]" +Toggle 1to0 byteenable [4] "logic byteenable[71:0]" +Toggle 1to0 byteenable [3] "logic byteenable[71:0]" +Toggle 1to0 byteenable [2] "logic byteenable[71:0]" +Toggle 1to0 byteenable [1] "logic byteenable[71:0]" +Toggle 1to0 byteenable [0] "logic byteenable[71:0]" +Toggle 1to0 byteenable [63] "logic byteenable[71:0]" +Toggle 0to1 ecc_interrupt "logic ecc_interrupt" +Toggle 1to0 ecc_interrupt "logic ecc_interrupt" +Toggle 0to1 writedata [575] "logic writedata[575:0]" +Toggle 1to0 writedata [575] "logic writedata[575:0]" +Toggle 0to1 writedata [512] "logic writedata[575:0]" +Toggle 1to0 writedata [512] "logic writedata[575:0]" +Toggle 0to1 writedata [513] "logic writedata[575:0]" +Toggle 1to0 writedata [513] "logic writedata[575:0]" +Toggle 0to1 writedata [514] "logic writedata[575:0]" +Toggle 1to0 writedata [514] "logic writedata[575:0]" +Toggle 0to1 writedata [515] "logic writedata[575:0]" +Toggle 1to0 writedata [515] "logic writedata[575:0]" +Toggle 0to1 writedata [516] "logic writedata[575:0]" +Toggle 1to0 writedata [516] "logic writedata[575:0]" +Toggle 0to1 writedata [517] "logic writedata[575:0]" +Toggle 1to0 writedata [517] "logic writedata[575:0]" +Toggle 0to1 writedata [518] "logic writedata[575:0]" +Toggle 1to0 writedata [518] "logic writedata[575:0]" +Toggle 0to1 writedata [519] "logic writedata[575:0]" +Toggle 1to0 writedata [519] "logic writedata[575:0]" +Toggle 0to1 writedata [520] "logic writedata[575:0]" +Toggle 1to0 writedata [520] "logic writedata[575:0]" +Toggle 0to1 writedata [521] "logic writedata[575:0]" +Toggle 1to0 writedata [521] "logic writedata[575:0]" +Toggle 0to1 writedata [522] "logic writedata[575:0]" +Toggle 1to0 writedata [522] "logic writedata[575:0]" +Toggle 0to1 writedata [523] "logic writedata[575:0]" +Toggle 1to0 writedata [523] "logic writedata[575:0]" +Toggle 0to1 writedata [524] "logic writedata[575:0]" +Toggle 1to0 writedata [524] "logic writedata[575:0]" +Toggle 0to1 writedata [525] "logic writedata[575:0]" +Toggle 1to0 writedata [525] "logic writedata[575:0]" +Toggle 0to1 writedata [526] "logic writedata[575:0]" +Toggle 1to0 writedata [526] "logic writedata[575:0]" +Toggle 0to1 writedata [527] "logic writedata[575:0]" +Toggle 1to0 writedata [527] "logic writedata[575:0]" +Toggle 0to1 writedata [528] "logic writedata[575:0]" +Toggle 1to0 writedata [528] "logic writedata[575:0]" +Toggle 0to1 writedata [529] "logic writedata[575:0]" +Toggle 1to0 writedata [529] "logic writedata[575:0]" +Toggle 0to1 writedata [530] "logic writedata[575:0]" +Toggle 1to0 writedata [530] "logic writedata[575:0]" +Toggle 0to1 writedata [531] "logic writedata[575:0]" +Toggle 1to0 writedata [531] "logic writedata[575:0]" +Toggle 0to1 writedata [532] "logic writedata[575:0]" +Toggle 1to0 writedata [532] "logic writedata[575:0]" +Toggle 0to1 writedata [533] "logic writedata[575:0]" +Toggle 1to0 writedata [533] "logic writedata[575:0]" +Toggle 0to1 writedata [534] "logic writedata[575:0]" +Toggle 1to0 writedata [534] "logic writedata[575:0]" +Toggle 0to1 writedata [535] "logic writedata[575:0]" +Toggle 1to0 writedata [535] "logic writedata[575:0]" +Toggle 0to1 writedata [536] "logic writedata[575:0]" +Toggle 1to0 writedata [536] "logic writedata[575:0]" +Toggle 0to1 writedata [537] "logic writedata[575:0]" +Toggle 1to0 writedata [537] "logic writedata[575:0]" +Toggle 0to1 writedata [538] "logic writedata[575:0]" +Toggle 1to0 writedata [538] "logic writedata[575:0]" +Toggle 0to1 writedata [539] "logic writedata[575:0]" +Toggle 1to0 writedata [539] "logic writedata[575:0]" +Toggle 0to1 writedata [540] "logic writedata[575:0]" +Toggle 1to0 writedata [540] "logic writedata[575:0]" +Toggle 0to1 writedata [541] "logic writedata[575:0]" +Toggle 1to0 writedata [541] "logic writedata[575:0]" +Toggle 0to1 writedata [542] "logic writedata[575:0]" +Toggle 1to0 writedata [542] "logic writedata[575:0]" +Toggle 0to1 writedata [543] "logic writedata[575:0]" +Toggle 1to0 writedata [543] "logic writedata[575:0]" +Toggle 0to1 writedata [544] "logic writedata[575:0]" +Toggle 1to0 writedata [544] "logic writedata[575:0]" +Toggle 0to1 writedata [545] "logic writedata[575:0]" +Toggle 1to0 writedata [545] "logic writedata[575:0]" +Toggle 0to1 writedata [546] "logic writedata[575:0]" +Toggle 1to0 writedata [546] "logic writedata[575:0]" +Toggle 0to1 writedata [547] "logic writedata[575:0]" +Toggle 1to0 writedata [547] "logic writedata[575:0]" +Toggle 0to1 writedata [548] "logic writedata[575:0]" +Toggle 1to0 writedata [548] "logic writedata[575:0]" +Toggle 0to1 writedata [549] "logic writedata[575:0]" +Toggle 1to0 writedata [549] "logic writedata[575:0]" +Toggle 0to1 writedata [550] "logic writedata[575:0]" +Toggle 1to0 writedata [550] "logic writedata[575:0]" +Toggle 0to1 writedata [551] "logic writedata[575:0]" +Toggle 1to0 writedata [551] "logic writedata[575:0]" +Toggle 0to1 writedata [552] "logic writedata[575:0]" +Toggle 1to0 writedata [552] "logic writedata[575:0]" +Toggle 0to1 writedata [553] "logic writedata[575:0]" +Toggle 1to0 writedata [553] "logic writedata[575:0]" +Toggle 0to1 writedata [554] "logic writedata[575:0]" +Toggle 1to0 writedata [554] "logic writedata[575:0]" +Toggle 0to1 writedata [555] "logic writedata[575:0]" +Toggle 1to0 writedata [555] "logic writedata[575:0]" +Toggle 0to1 writedata [556] "logic writedata[575:0]" +Toggle 1to0 writedata [556] "logic writedata[575:0]" +Toggle 0to1 writedata [557] "logic writedata[575:0]" +Toggle 1to0 writedata [557] "logic writedata[575:0]" +Toggle 0to1 writedata [558] "logic writedata[575:0]" +Toggle 1to0 writedata [558] "logic writedata[575:0]" +Toggle 0to1 writedata [559] "logic writedata[575:0]" +Toggle 1to0 writedata [559] "logic writedata[575:0]" +Toggle 0to1 writedata [560] "logic writedata[575:0]" +Toggle 1to0 writedata [560] "logic writedata[575:0]" +Toggle 0to1 writedata [561] "logic writedata[575:0]" +Toggle 1to0 writedata [561] "logic writedata[575:0]" +Toggle 0to1 writedata [562] "logic writedata[575:0]" +Toggle 1to0 writedata [562] "logic writedata[575:0]" +Toggle 0to1 writedata [563] "logic writedata[575:0]" +Toggle 1to0 writedata [563] "logic writedata[575:0]" +Toggle 0to1 writedata [564] "logic writedata[575:0]" +Toggle 1to0 writedata [564] "logic writedata[575:0]" +Toggle 0to1 writedata [565] "logic writedata[575:0]" +Toggle 1to0 writedata [565] "logic writedata[575:0]" +Toggle 0to1 writedata [566] "logic writedata[575:0]" +Toggle 1to0 writedata [566] "logic writedata[575:0]" +Toggle 0to1 writedata [567] "logic writedata[575:0]" +Toggle 1to0 writedata [567] "logic writedata[575:0]" +Toggle 0to1 writedata [568] "logic writedata[575:0]" +Toggle 1to0 writedata [568] "logic writedata[575:0]" +Toggle 0to1 writedata [569] "logic writedata[575:0]" +Toggle 1to0 writedata [569] "logic writedata[575:0]" +Toggle 0to1 writedata [570] "logic writedata[575:0]" +Toggle 1to0 writedata [570] "logic writedata[575:0]" +Toggle 0to1 writedata [571] "logic writedata[575:0]" +Toggle 1to0 writedata [571] "logic writedata[575:0]" +Toggle 0to1 writedata [572] "logic writedata[575:0]" +Toggle 1to0 writedata [572] "logic writedata[575:0]" +Toggle 0to1 writedata [573] "logic writedata[575:0]" +Toggle 1to0 writedata [573] "logic writedata[575:0]" +Toggle 0to1 writedata [574] "logic writedata[575:0]" +Toggle 1to0 writedata [574] "logic writedata[575:0]" +Toggle 0to1 readdata [575] "logic readdata[575:0]" +Toggle 1to0 readdata [575] "logic readdata[575:0]" +Toggle 0to1 readdata [512] "logic readdata[575:0]" +Toggle 1to0 readdata [512] "logic readdata[575:0]" +Toggle 0to1 readdata [513] "logic readdata[575:0]" +Toggle 1to0 readdata [513] "logic readdata[575:0]" +Toggle 0to1 readdata [514] "logic readdata[575:0]" +Toggle 1to0 readdata [514] "logic readdata[575:0]" +Toggle 0to1 readdata [515] "logic readdata[575:0]" +Toggle 1to0 readdata [515] "logic readdata[575:0]" +Toggle 0to1 readdata [516] "logic readdata[575:0]" +Toggle 1to0 readdata [516] "logic readdata[575:0]" +Toggle 0to1 readdata [517] "logic readdata[575:0]" +Toggle 1to0 readdata [517] "logic readdata[575:0]" +Toggle 0to1 readdata [518] "logic readdata[575:0]" +Toggle 1to0 readdata [518] "logic readdata[575:0]" +Toggle 0to1 readdata [519] "logic readdata[575:0]" +Toggle 1to0 readdata [519] "logic readdata[575:0]" +Toggle 0to1 readdata [520] "logic readdata[575:0]" +Toggle 1to0 readdata [520] "logic readdata[575:0]" +Toggle 0to1 readdata [521] "logic readdata[575:0]" +Toggle 1to0 readdata [521] "logic readdata[575:0]" +Toggle 0to1 readdata [522] "logic readdata[575:0]" +Toggle 1to0 readdata [522] "logic readdata[575:0]" +Toggle 0to1 readdata [523] "logic readdata[575:0]" +Toggle 1to0 readdata [523] "logic readdata[575:0]" +Toggle 0to1 readdata [524] "logic readdata[575:0]" +Toggle 1to0 readdata [524] "logic readdata[575:0]" +Toggle 0to1 readdata [525] "logic readdata[575:0]" +Toggle 1to0 readdata [525] "logic readdata[575:0]" +Toggle 0to1 readdata [526] "logic readdata[575:0]" +Toggle 1to0 readdata [526] "logic readdata[575:0]" +Toggle 0to1 readdata [527] "logic readdata[575:0]" +Toggle 1to0 readdata [527] "logic readdata[575:0]" +Toggle 0to1 readdata [528] "logic readdata[575:0]" +Toggle 1to0 readdata [528] "logic readdata[575:0]" +Toggle 0to1 readdata [529] "logic readdata[575:0]" +Toggle 1to0 readdata [529] "logic readdata[575:0]" +Toggle 0to1 readdata [530] "logic readdata[575:0]" +Toggle 1to0 readdata [530] "logic readdata[575:0]" +Toggle 0to1 readdata [531] "logic readdata[575:0]" +Toggle 1to0 readdata [531] "logic readdata[575:0]" +Toggle 0to1 readdata [532] "logic readdata[575:0]" +Toggle 1to0 readdata [532] "logic readdata[575:0]" +Toggle 0to1 readdata [533] "logic readdata[575:0]" +Toggle 1to0 readdata [533] "logic readdata[575:0]" +Toggle 0to1 readdata [534] "logic readdata[575:0]" +Toggle 1to0 readdata [534] "logic readdata[575:0]" +Toggle 0to1 readdata [535] "logic readdata[575:0]" +Toggle 1to0 readdata [535] "logic readdata[575:0]" +Toggle 0to1 readdata [536] "logic readdata[575:0]" +Toggle 1to0 readdata [536] "logic readdata[575:0]" +Toggle 0to1 readdata [537] "logic readdata[575:0]" +Toggle 1to0 readdata [537] "logic readdata[575:0]" +Toggle 0to1 readdata [538] "logic readdata[575:0]" +Toggle 1to0 readdata [538] "logic readdata[575:0]" +Toggle 0to1 readdata [539] "logic readdata[575:0]" +Toggle 1to0 readdata [539] "logic readdata[575:0]" +Toggle 0to1 readdata [540] "logic readdata[575:0]" +Toggle 1to0 readdata [540] "logic readdata[575:0]" +Toggle 0to1 readdata [541] "logic readdata[575:0]" +Toggle 1to0 readdata [541] "logic readdata[575:0]" +Toggle 0to1 readdata [542] "logic readdata[575:0]" +Toggle 1to0 readdata [542] "logic readdata[575:0]" +Toggle 0to1 readdata [543] "logic readdata[575:0]" +Toggle 1to0 readdata [543] "logic readdata[575:0]" +Toggle 0to1 readdata [544] "logic readdata[575:0]" +Toggle 1to0 readdata [544] "logic readdata[575:0]" +Toggle 0to1 readdata [545] "logic readdata[575:0]" +Toggle 1to0 readdata [545] "logic readdata[575:0]" +Toggle 0to1 readdata [546] "logic readdata[575:0]" +Toggle 1to0 readdata [546] "logic readdata[575:0]" +Toggle 0to1 readdata [547] "logic readdata[575:0]" +Toggle 1to0 readdata [547] "logic readdata[575:0]" +Toggle 0to1 readdata [548] "logic readdata[575:0]" +Toggle 1to0 readdata [548] "logic readdata[575:0]" +Toggle 0to1 readdata [549] "logic readdata[575:0]" +Toggle 1to0 readdata [549] "logic readdata[575:0]" +Toggle 0to1 readdata [550] "logic readdata[575:0]" +Toggle 1to0 readdata [550] "logic readdata[575:0]" +Toggle 0to1 readdata [551] "logic readdata[575:0]" +Toggle 1to0 readdata [551] "logic readdata[575:0]" +Toggle 0to1 readdata [552] "logic readdata[575:0]" +Toggle 1to0 readdata [552] "logic readdata[575:0]" +Toggle 0to1 readdata [553] "logic readdata[575:0]" +Toggle 1to0 readdata [553] "logic readdata[575:0]" +Toggle 0to1 readdata [554] "logic readdata[575:0]" +Toggle 1to0 readdata [554] "logic readdata[575:0]" +Toggle 0to1 readdata [555] "logic readdata[575:0]" +Toggle 1to0 readdata [555] "logic readdata[575:0]" +Toggle 0to1 readdata [556] "logic readdata[575:0]" +Toggle 1to0 readdata [556] "logic readdata[575:0]" +Toggle 0to1 readdata [557] "logic readdata[575:0]" +Toggle 1to0 readdata [557] "logic readdata[575:0]" +Toggle 0to1 readdata [558] "logic readdata[575:0]" +Toggle 1to0 readdata [558] "logic readdata[575:0]" +Toggle 0to1 readdata [559] "logic readdata[575:0]" +Toggle 1to0 readdata [559] "logic readdata[575:0]" +Toggle 0to1 readdata [560] "logic readdata[575:0]" +Toggle 1to0 readdata [560] "logic readdata[575:0]" +Toggle 0to1 readdata [561] "logic readdata[575:0]" +Toggle 1to0 readdata [561] "logic readdata[575:0]" +Toggle 0to1 readdata [562] "logic readdata[575:0]" +Toggle 1to0 readdata [562] "logic readdata[575:0]" +Toggle 0to1 readdata [563] "logic readdata[575:0]" +Toggle 1to0 readdata [563] "logic readdata[575:0]" +Toggle 0to1 readdata [564] "logic readdata[575:0]" +Toggle 1to0 readdata [564] "logic readdata[575:0]" +Toggle 0to1 readdata [565] "logic readdata[575:0]" +Toggle 1to0 readdata [565] "logic readdata[575:0]" +Toggle 0to1 readdata [566] "logic readdata[575:0]" +Toggle 1to0 readdata [566] "logic readdata[575:0]" +Toggle 0to1 readdata [567] "logic readdata[575:0]" +Toggle 1to0 readdata [567] "logic readdata[575:0]" +Toggle 0to1 readdata [568] "logic readdata[575:0]" +Toggle 1to0 readdata [568] "logic readdata[575:0]" +Toggle 0to1 readdata [569] "logic readdata[575:0]" +Toggle 1to0 readdata [569] "logic readdata[575:0]" +Toggle 0to1 readdata [570] "logic readdata[575:0]" +Toggle 1to0 readdata [570] "logic readdata[575:0]" +Toggle 0to1 readdata [571] "logic readdata[575:0]" +Toggle 1to0 readdata [571] "logic readdata[575:0]" +Toggle 0to1 readdata [572] "logic readdata[575:0]" +Toggle 1to0 readdata [572] "logic readdata[575:0]" +Toggle 0to1 readdata [573] "logic readdata[575:0]" +Toggle 1to0 readdata [573] "logic readdata[575:0]" +Toggle 0to1 readdata [574] "logic readdata[575:0]" +Toggle 1to0 readdata [574] "logic readdata[575:0]" +Toggle 0to1 byteenable [71] "logic byteenable[71:0]" +Toggle 1to0 byteenable [71] "logic byteenable[71:0]" +Toggle 0to1 byteenable [64] "logic byteenable[71:0]" +Toggle 1to0 byteenable [64] "logic byteenable[71:0]" +Toggle 0to1 byteenable [65] "logic byteenable[71:0]" +Toggle 1to0 byteenable [65] "logic byteenable[71:0]" +Toggle 0to1 byteenable [66] "logic byteenable[71:0]" +Toggle 1to0 byteenable [66] "logic byteenable[71:0]" +Toggle 0to1 byteenable [67] "logic byteenable[71:0]" +Toggle 1to0 byteenable [67] "logic byteenable[71:0]" +Toggle 0to1 byteenable [68] "logic byteenable[71:0]" +Toggle 1to0 byteenable [68] "logic byteenable[71:0]" +Toggle 0to1 byteenable [69] "logic byteenable[71:0]" +Toggle 1to0 byteenable [69] "logic byteenable[71:0]" +Toggle 0to1 byteenable [70] "logic byteenable[71:0]" +Toggle 1to0 byteenable [70] "logic byteenable[71:0]" +Toggle 0to1 address [26] "logic address[26:0]" +Toggle 1to0 address [26] "logic address[26:0]" +Toggle 0to1 address [10] "logic address[26:0]" +Toggle 1to0 address [10] "logic address[26:0]" +Toggle 0to1 address [11] "logic address[26:0]" +Toggle 1to0 address [11] "logic address[26:0]" +Toggle 0to1 address [12] "logic address[26:0]" +Toggle 1to0 address [12] "logic address[26:0]" +Toggle 0to1 address [13] "logic address[26:0]" +Toggle 1to0 address [13] "logic address[26:0]" +Toggle 0to1 address [14] "logic address[26:0]" +Toggle 1to0 address [14] "logic address[26:0]" +Toggle 0to1 address [15] "logic address[26:0]" +Toggle 1to0 address [15] "logic address[26:0]" +Toggle 0to1 address [16] "logic address[26:0]" +Toggle 1to0 address [16] "logic address[26:0]" +Toggle 0to1 address [17] "logic address[26:0]" +Toggle 1to0 address [17] "logic address[26:0]" +Toggle 0to1 address [18] "logic address[26:0]" +Toggle 1to0 address [18] "logic address[26:0]" +Toggle 0to1 address [19] "logic address[26:0]" +Toggle 1to0 address [19] "logic address[26:0]" +Toggle 0to1 address [20] "logic address[26:0]" +Toggle 1to0 address [20] "logic address[26:0]" +Toggle 0to1 address [21] "logic address[26:0]" +Toggle 1to0 address [21] "logic address[26:0]" +Toggle 0to1 address [22] "logic address[26:0]" +Toggle 1to0 address [22] "logic address[26:0]" +Toggle 0to1 address [23] "logic address[26:0]" +Toggle 1to0 address [23] "logic address[26:0]" +Toggle 0to1 address [24] "logic address[26:0]" +Toggle 1to0 address [24] "logic address[26:0]" +Toggle 0to1 address [25] "logic address[26:0]" +Toggle 1to0 address [25] "logic address[26:0]" +Toggle 0to1 burstcount [6] "logic burstcount[6:0]" +Toggle 1to0 burstcount [6] "logic burstcount[6:0]" +Toggle 0to1 burstcount [3] "logic burstcount[6:0]" +Toggle 1to0 burstcount [3] "logic burstcount[6:0]" +Toggle 0to1 burstcount [4] "logic burstcount[6:0]" +Toggle 1to0 burstcount [4] "logic burstcount[6:0]" +Toggle 0to1 burstcount [5] "logic burstcount[6:0]" +Toggle 1to0 burstcount [5] "logic burstcount[6:0]" +CHECKSUM: "3021715206 3213032206" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.mem_reg_if[0] +Toggle 1to0 burstcount [0] "logic burstcount[6:0]" +Toggle 1to0 byteenable [62] "logic byteenable[71:0]" +Toggle 1to0 byteenable [61] "logic byteenable[71:0]" +Toggle 1to0 byteenable [60] "logic byteenable[71:0]" +Toggle 1to0 byteenable [59] "logic byteenable[71:0]" +Toggle 1to0 byteenable [58] "logic byteenable[71:0]" +Toggle 1to0 byteenable [57] "logic byteenable[71:0]" +Toggle 1to0 byteenable [56] "logic byteenable[71:0]" +Toggle 1to0 byteenable [55] "logic byteenable[71:0]" +Toggle 1to0 byteenable [54] "logic byteenable[71:0]" +Toggle 1to0 byteenable [53] "logic byteenable[71:0]" +Toggle 1to0 byteenable [52] "logic byteenable[71:0]" +Toggle 1to0 byteenable [51] "logic byteenable[71:0]" +Toggle 1to0 byteenable [50] "logic byteenable[71:0]" +Toggle 1to0 byteenable [49] "logic byteenable[71:0]" +Toggle 1to0 byteenable [48] "logic byteenable[71:0]" +Toggle 1to0 byteenable [47] "logic byteenable[71:0]" +Toggle 1to0 byteenable [46] "logic byteenable[71:0]" +Toggle 1to0 byteenable [45] "logic byteenable[71:0]" +Toggle 1to0 byteenable [44] "logic byteenable[71:0]" +Toggle 1to0 byteenable [43] "logic byteenable[71:0]" +Toggle 1to0 byteenable [42] "logic byteenable[71:0]" +Toggle 1to0 byteenable [41] "logic byteenable[71:0]" +Toggle 1to0 byteenable [40] "logic byteenable[71:0]" +Toggle 1to0 byteenable [39] "logic byteenable[71:0]" +Toggle 1to0 byteenable [38] "logic byteenable[71:0]" +Toggle 1to0 byteenable [37] "logic byteenable[71:0]" +Toggle 1to0 byteenable [36] "logic byteenable[71:0]" +Toggle 1to0 byteenable [35] "logic byteenable[71:0]" +Toggle 1to0 byteenable [34] "logic byteenable[71:0]" +Toggle 1to0 byteenable [33] "logic byteenable[71:0]" +Toggle 1to0 byteenable [32] "logic byteenable[71:0]" +Toggle 1to0 byteenable [31] "logic byteenable[71:0]" +Toggle 1to0 byteenable [30] "logic byteenable[71:0]" +Toggle 1to0 byteenable [29] "logic byteenable[71:0]" +Toggle 1to0 byteenable [28] "logic byteenable[71:0]" +Toggle 1to0 byteenable [27] "logic byteenable[71:0]" +Toggle 1to0 byteenable [26] "logic byteenable[71:0]" +Toggle 1to0 byteenable [25] "logic byteenable[71:0]" +Toggle 1to0 byteenable [24] "logic byteenable[71:0]" +Toggle 1to0 byteenable [23] "logic byteenable[71:0]" +Toggle 1to0 byteenable [22] "logic byteenable[71:0]" +Toggle 1to0 byteenable [21] "logic byteenable[71:0]" +Toggle 1to0 byteenable [20] "logic byteenable[71:0]" +Toggle 1to0 byteenable [19] "logic byteenable[71:0]" +Toggle 1to0 byteenable [18] "logic byteenable[71:0]" +Toggle 1to0 byteenable [17] "logic byteenable[71:0]" +Toggle 1to0 byteenable [16] "logic byteenable[71:0]" +Toggle 1to0 byteenable [15] "logic byteenable[71:0]" +Toggle 1to0 byteenable [14] "logic byteenable[71:0]" +Toggle 1to0 byteenable [13] "logic byteenable[71:0]" +Toggle 1to0 byteenable [12] "logic byteenable[71:0]" +Toggle 1to0 byteenable [11] "logic byteenable[71:0]" +Toggle 1to0 byteenable [10] "logic byteenable[71:0]" +Toggle 1to0 byteenable [9] "logic byteenable[71:0]" +Toggle 1to0 byteenable [8] "logic byteenable[71:0]" +Toggle 1to0 byteenable [7] "logic byteenable[71:0]" +Toggle 1to0 byteenable [6] "logic byteenable[71:0]" +Toggle 1to0 byteenable [5] "logic byteenable[71:0]" +Toggle 1to0 byteenable [4] "logic byteenable[71:0]" +Toggle 1to0 byteenable [3] "logic byteenable[71:0]" +Toggle 1to0 byteenable [2] "logic byteenable[71:0]" +Toggle 1to0 byteenable [1] "logic byteenable[71:0]" +Toggle 1to0 byteenable [0] "logic byteenable[71:0]" +Toggle 1to0 byteenable [63] "logic byteenable[71:0]" +Toggle 0to1 writedata [575] "logic writedata[575:0]" +Toggle 1to0 writedata [575] "logic writedata[575:0]" +Toggle 0to1 writedata [512] "logic writedata[575:0]" +Toggle 1to0 writedata [512] "logic writedata[575:0]" +Toggle 0to1 writedata [513] "logic writedata[575:0]" +Toggle 1to0 writedata [513] "logic writedata[575:0]" +Toggle 0to1 writedata [514] "logic writedata[575:0]" +Toggle 1to0 writedata [514] "logic writedata[575:0]" +Toggle 0to1 writedata [515] "logic writedata[575:0]" +Toggle 1to0 writedata [515] "logic writedata[575:0]" +Toggle 0to1 writedata [516] "logic writedata[575:0]" +Toggle 1to0 writedata [516] "logic writedata[575:0]" +Toggle 0to1 writedata [517] "logic writedata[575:0]" +Toggle 1to0 writedata [517] "logic writedata[575:0]" +Toggle 0to1 writedata [518] "logic writedata[575:0]" +Toggle 1to0 writedata [518] "logic writedata[575:0]" +Toggle 0to1 writedata [519] "logic writedata[575:0]" +Toggle 1to0 writedata [519] "logic writedata[575:0]" +Toggle 0to1 writedata [520] "logic writedata[575:0]" +Toggle 1to0 writedata [520] "logic writedata[575:0]" +Toggle 0to1 writedata [521] "logic writedata[575:0]" +Toggle 1to0 writedata [521] "logic writedata[575:0]" +Toggle 0to1 writedata [522] "logic writedata[575:0]" +Toggle 1to0 writedata [522] "logic writedata[575:0]" +Toggle 0to1 writedata [523] "logic writedata[575:0]" +Toggle 1to0 writedata [523] "logic writedata[575:0]" +Toggle 0to1 writedata [524] "logic writedata[575:0]" +Toggle 1to0 writedata [524] "logic writedata[575:0]" +Toggle 0to1 writedata [525] "logic writedata[575:0]" +Toggle 1to0 writedata [525] "logic writedata[575:0]" +Toggle 0to1 writedata [526] "logic writedata[575:0]" +Toggle 1to0 writedata [526] "logic writedata[575:0]" +Toggle 0to1 writedata [527] "logic writedata[575:0]" +Toggle 1to0 writedata [527] "logic writedata[575:0]" +Toggle 0to1 writedata [528] "logic writedata[575:0]" +Toggle 1to0 writedata [528] "logic writedata[575:0]" +Toggle 0to1 writedata [529] "logic writedata[575:0]" +Toggle 1to0 writedata [529] "logic writedata[575:0]" +Toggle 0to1 writedata [530] "logic writedata[575:0]" +Toggle 1to0 writedata [530] "logic writedata[575:0]" +Toggle 0to1 writedata [531] "logic writedata[575:0]" +Toggle 1to0 writedata [531] "logic writedata[575:0]" +Toggle 0to1 writedata [532] "logic writedata[575:0]" +Toggle 1to0 writedata [532] "logic writedata[575:0]" +Toggle 0to1 writedata [533] "logic writedata[575:0]" +Toggle 1to0 writedata [533] "logic writedata[575:0]" +Toggle 0to1 writedata [534] "logic writedata[575:0]" +Toggle 1to0 writedata [534] "logic writedata[575:0]" +Toggle 0to1 writedata [535] "logic writedata[575:0]" +Toggle 1to0 writedata [535] "logic writedata[575:0]" +Toggle 0to1 writedata [536] "logic writedata[575:0]" +Toggle 1to0 writedata [536] "logic writedata[575:0]" +Toggle 0to1 writedata [537] "logic writedata[575:0]" +Toggle 1to0 writedata [537] "logic writedata[575:0]" +Toggle 0to1 writedata [538] "logic writedata[575:0]" +Toggle 1to0 writedata [538] "logic writedata[575:0]" +Toggle 0to1 writedata [539] "logic writedata[575:0]" +Toggle 1to0 writedata [539] "logic writedata[575:0]" +Toggle 0to1 writedata [540] "logic writedata[575:0]" +Toggle 1to0 writedata [540] "logic writedata[575:0]" +Toggle 0to1 writedata [541] "logic writedata[575:0]" +Toggle 1to0 writedata [541] "logic writedata[575:0]" +Toggle 0to1 writedata [542] "logic writedata[575:0]" +Toggle 1to0 writedata [542] "logic writedata[575:0]" +Toggle 0to1 writedata [543] "logic writedata[575:0]" +Toggle 1to0 writedata [543] "logic writedata[575:0]" +Toggle 0to1 writedata [544] "logic writedata[575:0]" +Toggle 1to0 writedata [544] "logic writedata[575:0]" +Toggle 0to1 writedata [545] "logic writedata[575:0]" +Toggle 1to0 writedata [545] "logic writedata[575:0]" +Toggle 0to1 writedata [546] "logic writedata[575:0]" +Toggle 1to0 writedata [546] "logic writedata[575:0]" +Toggle 0to1 writedata [547] "logic writedata[575:0]" +Toggle 1to0 writedata [547] "logic writedata[575:0]" +Toggle 0to1 writedata [548] "logic writedata[575:0]" +Toggle 1to0 writedata [548] "logic writedata[575:0]" +Toggle 0to1 writedata [549] "logic writedata[575:0]" +Toggle 1to0 writedata [549] "logic writedata[575:0]" +Toggle 0to1 writedata [550] "logic writedata[575:0]" +Toggle 1to0 writedata [550] "logic writedata[575:0]" +Toggle 0to1 writedata [551] "logic writedata[575:0]" +Toggle 1to0 writedata [551] "logic writedata[575:0]" +Toggle 0to1 writedata [552] "logic writedata[575:0]" +Toggle 1to0 writedata [552] "logic writedata[575:0]" +Toggle 0to1 writedata [553] "logic writedata[575:0]" +Toggle 1to0 writedata [553] "logic writedata[575:0]" +Toggle 0to1 writedata [554] "logic writedata[575:0]" +Toggle 1to0 writedata [554] "logic writedata[575:0]" +Toggle 0to1 writedata [555] "logic writedata[575:0]" +Toggle 1to0 writedata [555] "logic writedata[575:0]" +Toggle 0to1 writedata [556] "logic writedata[575:0]" +Toggle 1to0 writedata [556] "logic writedata[575:0]" +Toggle 0to1 writedata [557] "logic writedata[575:0]" +Toggle 1to0 writedata [557] "logic writedata[575:0]" +Toggle 0to1 writedata [558] "logic writedata[575:0]" +Toggle 1to0 writedata [558] "logic writedata[575:0]" +Toggle 0to1 writedata [559] "logic writedata[575:0]" +Toggle 1to0 writedata [559] "logic writedata[575:0]" +Toggle 0to1 writedata [560] "logic writedata[575:0]" +Toggle 1to0 writedata [560] "logic writedata[575:0]" +Toggle 0to1 writedata [561] "logic writedata[575:0]" +Toggle 1to0 writedata [561] "logic writedata[575:0]" +Toggle 0to1 writedata [562] "logic writedata[575:0]" +Toggle 1to0 writedata [562] "logic writedata[575:0]" +Toggle 0to1 writedata [563] "logic writedata[575:0]" +Toggle 1to0 writedata [563] "logic writedata[575:0]" +Toggle 0to1 writedata [564] "logic writedata[575:0]" +Toggle 1to0 writedata [564] "logic writedata[575:0]" +Toggle 0to1 writedata [565] "logic writedata[575:0]" +Toggle 1to0 writedata [565] "logic writedata[575:0]" +Toggle 0to1 writedata [566] "logic writedata[575:0]" +Toggle 1to0 writedata [566] "logic writedata[575:0]" +Toggle 0to1 writedata [567] "logic writedata[575:0]" +Toggle 1to0 writedata [567] "logic writedata[575:0]" +Toggle 0to1 writedata [568] "logic writedata[575:0]" +Toggle 1to0 writedata [568] "logic writedata[575:0]" +Toggle 0to1 writedata [569] "logic writedata[575:0]" +Toggle 1to0 writedata [569] "logic writedata[575:0]" +Toggle 0to1 writedata [570] "logic writedata[575:0]" +Toggle 1to0 writedata [570] "logic writedata[575:0]" +Toggle 0to1 writedata [571] "logic writedata[575:0]" +Toggle 1to0 writedata [571] "logic writedata[575:0]" +Toggle 0to1 writedata [572] "logic writedata[575:0]" +Toggle 1to0 writedata [572] "logic writedata[575:0]" +Toggle 0to1 writedata [573] "logic writedata[575:0]" +Toggle 1to0 writedata [573] "logic writedata[575:0]" +Toggle 0to1 writedata [574] "logic writedata[575:0]" +Toggle 1to0 writedata [574] "logic writedata[575:0]" +Toggle 0to1 readdata [575] "logic readdata[575:0]" +Toggle 1to0 readdata [575] "logic readdata[575:0]" +Toggle 0to1 readdata [512] "logic readdata[575:0]" +Toggle 1to0 readdata [512] "logic readdata[575:0]" +Toggle 0to1 readdata [513] "logic readdata[575:0]" +Toggle 1to0 readdata [513] "logic readdata[575:0]" +Toggle 0to1 readdata [514] "logic readdata[575:0]" +Toggle 1to0 readdata [514] "logic readdata[575:0]" +Toggle 0to1 readdata [515] "logic readdata[575:0]" +Toggle 1to0 readdata [515] "logic readdata[575:0]" +Toggle 0to1 readdata [516] "logic readdata[575:0]" +Toggle 1to0 readdata [516] "logic readdata[575:0]" +Toggle 0to1 readdata [517] "logic readdata[575:0]" +Toggle 1to0 readdata [517] "logic readdata[575:0]" +Toggle 0to1 readdata [518] "logic readdata[575:0]" +Toggle 1to0 readdata [518] "logic readdata[575:0]" +Toggle 0to1 readdata [519] "logic readdata[575:0]" +Toggle 1to0 readdata [519] "logic readdata[575:0]" +Toggle 0to1 readdata [520] "logic readdata[575:0]" +Toggle 1to0 readdata [520] "logic readdata[575:0]" +Toggle 0to1 readdata [521] "logic readdata[575:0]" +Toggle 1to0 readdata [521] "logic readdata[575:0]" +Toggle 0to1 readdata [522] "logic readdata[575:0]" +Toggle 1to0 readdata [522] "logic readdata[575:0]" +Toggle 0to1 readdata [523] "logic readdata[575:0]" +Toggle 1to0 readdata [523] "logic readdata[575:0]" +Toggle 0to1 readdata [524] "logic readdata[575:0]" +Toggle 1to0 readdata [524] "logic readdata[575:0]" +Toggle 0to1 readdata [525] "logic readdata[575:0]" +Toggle 1to0 readdata [525] "logic readdata[575:0]" +Toggle 0to1 readdata [526] "logic readdata[575:0]" +Toggle 1to0 readdata [526] "logic readdata[575:0]" +Toggle 0to1 readdata [527] "logic readdata[575:0]" +Toggle 1to0 readdata [527] "logic readdata[575:0]" +Toggle 0to1 readdata [528] "logic readdata[575:0]" +Toggle 1to0 readdata [528] "logic readdata[575:0]" +Toggle 0to1 readdata [529] "logic readdata[575:0]" +Toggle 1to0 readdata [529] "logic readdata[575:0]" +Toggle 0to1 readdata [530] "logic readdata[575:0]" +Toggle 1to0 readdata [530] "logic readdata[575:0]" +Toggle 0to1 readdata [531] "logic readdata[575:0]" +Toggle 1to0 readdata [531] "logic readdata[575:0]" +Toggle 0to1 readdata [532] "logic readdata[575:0]" +Toggle 1to0 readdata [532] "logic readdata[575:0]" +Toggle 0to1 readdata [533] "logic readdata[575:0]" +Toggle 1to0 readdata [533] "logic readdata[575:0]" +Toggle 0to1 readdata [534] "logic readdata[575:0]" +Toggle 1to0 readdata [534] "logic readdata[575:0]" +Toggle 0to1 readdata [535] "logic readdata[575:0]" +Toggle 1to0 readdata [535] "logic readdata[575:0]" +Toggle 0to1 readdata [536] "logic readdata[575:0]" +Toggle 1to0 readdata [536] "logic readdata[575:0]" +Toggle 0to1 readdata [537] "logic readdata[575:0]" +Toggle 1to0 readdata [537] "logic readdata[575:0]" +Toggle 0to1 readdata [538] "logic readdata[575:0]" +Toggle 1to0 readdata [538] "logic readdata[575:0]" +Toggle 0to1 readdata [539] "logic readdata[575:0]" +Toggle 1to0 readdata [539] "logic readdata[575:0]" +Toggle 0to1 readdata [540] "logic readdata[575:0]" +Toggle 1to0 readdata [540] "logic readdata[575:0]" +Toggle 0to1 readdata [541] "logic readdata[575:0]" +Toggle 1to0 readdata [541] "logic readdata[575:0]" +Toggle 0to1 readdata [542] "logic readdata[575:0]" +Toggle 1to0 readdata [542] "logic readdata[575:0]" +Toggle 0to1 readdata [543] "logic readdata[575:0]" +Toggle 1to0 readdata [543] "logic readdata[575:0]" +Toggle 0to1 readdata [544] "logic readdata[575:0]" +Toggle 1to0 readdata [544] "logic readdata[575:0]" +Toggle 0to1 readdata [545] "logic readdata[575:0]" +Toggle 1to0 readdata [545] "logic readdata[575:0]" +Toggle 0to1 readdata [546] "logic readdata[575:0]" +Toggle 1to0 readdata [546] "logic readdata[575:0]" +Toggle 0to1 readdata [547] "logic readdata[575:0]" +Toggle 1to0 readdata [547] "logic readdata[575:0]" +Toggle 0to1 readdata [548] "logic readdata[575:0]" +Toggle 1to0 readdata [548] "logic readdata[575:0]" +Toggle 0to1 readdata [549] "logic readdata[575:0]" +Toggle 1to0 readdata [549] "logic readdata[575:0]" +Toggle 0to1 readdata [550] "logic readdata[575:0]" +Toggle 1to0 readdata [550] "logic readdata[575:0]" +Toggle 0to1 readdata [551] "logic readdata[575:0]" +Toggle 1to0 readdata [551] "logic readdata[575:0]" +Toggle 0to1 readdata [552] "logic readdata[575:0]" +Toggle 1to0 readdata [552] "logic readdata[575:0]" +Toggle 0to1 readdata [553] "logic readdata[575:0]" +Toggle 1to0 readdata [553] "logic readdata[575:0]" +Toggle 0to1 readdata [554] "logic readdata[575:0]" +Toggle 1to0 readdata [554] "logic readdata[575:0]" +Toggle 0to1 readdata [555] "logic readdata[575:0]" +Toggle 1to0 readdata [555] "logic readdata[575:0]" +Toggle 0to1 readdata [556] "logic readdata[575:0]" +Toggle 1to0 readdata [556] "logic readdata[575:0]" +Toggle 0to1 readdata [557] "logic readdata[575:0]" +Toggle 1to0 readdata [557] "logic readdata[575:0]" +Toggle 0to1 readdata [558] "logic readdata[575:0]" +Toggle 1to0 readdata [558] "logic readdata[575:0]" +Toggle 0to1 readdata [559] "logic readdata[575:0]" +Toggle 1to0 readdata [559] "logic readdata[575:0]" +Toggle 0to1 readdata [560] "logic readdata[575:0]" +Toggle 1to0 readdata [560] "logic readdata[575:0]" +Toggle 0to1 readdata [561] "logic readdata[575:0]" +Toggle 1to0 readdata [561] "logic readdata[575:0]" +Toggle 0to1 readdata [562] "logic readdata[575:0]" +Toggle 1to0 readdata [562] "logic readdata[575:0]" +Toggle 0to1 readdata [563] "logic readdata[575:0]" +Toggle 1to0 readdata [563] "logic readdata[575:0]" +Toggle 0to1 readdata [564] "logic readdata[575:0]" +Toggle 1to0 readdata [564] "logic readdata[575:0]" +Toggle 0to1 readdata [565] "logic readdata[575:0]" +Toggle 1to0 readdata [565] "logic readdata[575:0]" +Toggle 0to1 readdata [566] "logic readdata[575:0]" +Toggle 1to0 readdata [566] "logic readdata[575:0]" +Toggle 0to1 readdata [567] "logic readdata[575:0]" +Toggle 1to0 readdata [567] "logic readdata[575:0]" +Toggle 0to1 readdata [568] "logic readdata[575:0]" +Toggle 1to0 readdata [568] "logic readdata[575:0]" +Toggle 0to1 readdata [569] "logic readdata[575:0]" +Toggle 1to0 readdata [569] "logic readdata[575:0]" +Toggle 0to1 readdata [570] "logic readdata[575:0]" +Toggle 1to0 readdata [570] "logic readdata[575:0]" +Toggle 0to1 readdata [571] "logic readdata[575:0]" +Toggle 1to0 readdata [571] "logic readdata[575:0]" +Toggle 0to1 readdata [572] "logic readdata[575:0]" +Toggle 1to0 readdata [572] "logic readdata[575:0]" +Toggle 0to1 readdata [573] "logic readdata[575:0]" +Toggle 1to0 readdata [573] "logic readdata[575:0]" +Toggle 0to1 readdata [574] "logic readdata[575:0]" +Toggle 1to0 readdata [574] "logic readdata[575:0]" +Toggle 0to1 ecc_interrupt "logic ecc_interrupt" +Toggle 1to0 ecc_interrupt "logic ecc_interrupt" +Toggle 0to1 burstcount [6] "logic burstcount[6:0]" +Toggle 1to0 burstcount [6] "logic burstcount[6:0]" +Toggle 0to1 burstcount [1] "logic burstcount[6:0]" +Toggle 1to0 burstcount [1] "logic burstcount[6:0]" +Toggle 0to1 burstcount [2] "logic burstcount[6:0]" +Toggle 1to0 burstcount [2] "logic burstcount[6:0]" +Toggle 0to1 burstcount [3] "logic burstcount[6:0]" +Toggle 1to0 burstcount [3] "logic burstcount[6:0]" +Toggle 0to1 burstcount [4] "logic burstcount[6:0]" +Toggle 1to0 burstcount [4] "logic burstcount[6:0]" +Toggle 0to1 burstcount [5] "logic burstcount[6:0]" +Toggle 1to0 burstcount [5] "logic burstcount[6:0]" +Toggle 0to1 address [26] "logic address[26:0]" +Toggle 1to0 address [26] "logic address[26:0]" +Toggle 0to1 address [10] "logic address[26:0]" +Toggle 1to0 address [10] "logic address[26:0]" +Toggle 0to1 address [11] "logic address[26:0]" +Toggle 1to0 address [11] "logic address[26:0]" +Toggle 0to1 address [12] "logic address[26:0]" +Toggle 1to0 address [12] "logic address[26:0]" +Toggle 0to1 address [13] "logic address[26:0]" +Toggle 1to0 address [13] "logic address[26:0]" +Toggle 0to1 address [14] "logic address[26:0]" +Toggle 1to0 address [14] "logic address[26:0]" +Toggle 0to1 address [15] "logic address[26:0]" +Toggle 1to0 address [15] "logic address[26:0]" +Toggle 0to1 address [16] "logic address[26:0]" +Toggle 1to0 address [16] "logic address[26:0]" +Toggle 0to1 address [17] "logic address[26:0]" +Toggle 1to0 address [17] "logic address[26:0]" +Toggle 0to1 address [18] "logic address[26:0]" +Toggle 1to0 address [18] "logic address[26:0]" +Toggle 0to1 address [19] "logic address[26:0]" +Toggle 1to0 address [19] "logic address[26:0]" +Toggle 0to1 address [20] "logic address[26:0]" +Toggle 1to0 address [20] "logic address[26:0]" +Toggle 0to1 address [21] "logic address[26:0]" +Toggle 1to0 address [21] "logic address[26:0]" +Toggle 0to1 address [22] "logic address[26:0]" +Toggle 1to0 address [22] "logic address[26:0]" +Toggle 0to1 address [23] "logic address[26:0]" +Toggle 1to0 address [23] "logic address[26:0]" +Toggle 0to1 address [24] "logic address[26:0]" +Toggle 1to0 address [24] "logic address[26:0]" +Toggle 0to1 address [25] "logic address[26:0]" +Toggle 1to0 address [25] "logic address[26:0]" +Toggle 0to1 byteenable [71] "logic byteenable[71:0]" +Toggle 1to0 byteenable [71] "logic byteenable[71:0]" +Toggle 0to1 byteenable [64] "logic byteenable[71:0]" +Toggle 1to0 byteenable [64] "logic byteenable[71:0]" +Toggle 0to1 byteenable [65] "logic byteenable[71:0]" +Toggle 1to0 byteenable [65] "logic byteenable[71:0]" +Toggle 0to1 byteenable [66] "logic byteenable[71:0]" +Toggle 1to0 byteenable [66] "logic byteenable[71:0]" +Toggle 0to1 byteenable [67] "logic byteenable[71:0]" +Toggle 1to0 byteenable [67] "logic byteenable[71:0]" +Toggle 0to1 byteenable [68] "logic byteenable[71:0]" +Toggle 1to0 byteenable [68] "logic byteenable[71:0]" +Toggle 0to1 byteenable [69] "logic byteenable[71:0]" +Toggle 1to0 byteenable [69] "logic byteenable[71:0]" +Toggle 0to1 byteenable [70] "logic byteenable[71:0]" +Toggle 1to0 byteenable [70] "logic byteenable[71:0]" +CHECKSUM: "3021715206 3213032206" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.mem_if[1] +Toggle 1to0 burstcount [1] "logic burstcount[6:0]" +Toggle 1to0 burstcount [2] "logic burstcount[6:0]" +Toggle 1to0 byteenable [62] "logic byteenable[71:0]" +Toggle 1to0 byteenable [61] "logic byteenable[71:0]" +Toggle 1to0 byteenable [60] "logic byteenable[71:0]" +Toggle 1to0 byteenable [59] "logic byteenable[71:0]" +Toggle 1to0 byteenable [58] "logic byteenable[71:0]" +Toggle 1to0 byteenable [57] "logic byteenable[71:0]" +Toggle 1to0 byteenable [56] "logic byteenable[71:0]" +Toggle 1to0 byteenable [55] "logic byteenable[71:0]" +Toggle 1to0 byteenable [54] "logic byteenable[71:0]" +Toggle 1to0 byteenable [53] "logic byteenable[71:0]" +Toggle 1to0 byteenable [52] "logic byteenable[71:0]" +Toggle 1to0 byteenable [51] "logic byteenable[71:0]" +Toggle 1to0 byteenable [50] "logic byteenable[71:0]" +Toggle 1to0 byteenable [49] "logic byteenable[71:0]" +Toggle 1to0 byteenable [48] "logic byteenable[71:0]" +Toggle 1to0 byteenable [47] "logic byteenable[71:0]" +Toggle 1to0 byteenable [46] "logic byteenable[71:0]" +Toggle 1to0 byteenable [45] "logic byteenable[71:0]" +Toggle 1to0 byteenable [44] "logic byteenable[71:0]" +Toggle 1to0 byteenable [43] "logic byteenable[71:0]" +Toggle 1to0 byteenable [42] "logic byteenable[71:0]" +Toggle 1to0 byteenable [41] "logic byteenable[71:0]" +Toggle 1to0 byteenable [40] "logic byteenable[71:0]" +Toggle 1to0 byteenable [39] "logic byteenable[71:0]" +Toggle 1to0 byteenable [38] "logic byteenable[71:0]" +Toggle 1to0 byteenable [37] "logic byteenable[71:0]" +Toggle 1to0 byteenable [36] "logic byteenable[71:0]" +Toggle 1to0 byteenable [35] "logic byteenable[71:0]" +Toggle 1to0 byteenable [34] "logic byteenable[71:0]" +Toggle 1to0 byteenable [33] "logic byteenable[71:0]" +Toggle 1to0 byteenable [32] "logic byteenable[71:0]" +Toggle 1to0 byteenable [31] "logic byteenable[71:0]" +Toggle 1to0 byteenable [30] "logic byteenable[71:0]" +Toggle 1to0 byteenable [29] "logic byteenable[71:0]" +Toggle 1to0 byteenable [28] "logic byteenable[71:0]" +Toggle 1to0 byteenable [27] "logic byteenable[71:0]" +Toggle 1to0 byteenable [26] "logic byteenable[71:0]" +Toggle 1to0 byteenable [25] "logic byteenable[71:0]" +Toggle 1to0 byteenable [24] "logic byteenable[71:0]" +Toggle 1to0 byteenable [23] "logic byteenable[71:0]" +Toggle 1to0 byteenable [22] "logic byteenable[71:0]" +Toggle 1to0 byteenable [21] "logic byteenable[71:0]" +Toggle 1to0 byteenable [20] "logic byteenable[71:0]" +Toggle 1to0 byteenable [19] "logic byteenable[71:0]" +Toggle 1to0 byteenable [18] "logic byteenable[71:0]" +Toggle 1to0 byteenable [17] "logic byteenable[71:0]" +Toggle 1to0 byteenable [16] "logic byteenable[71:0]" +Toggle 1to0 byteenable [15] "logic byteenable[71:0]" +Toggle 1to0 byteenable [14] "logic byteenable[71:0]" +Toggle 1to0 byteenable [13] "logic byteenable[71:0]" +Toggle 1to0 byteenable [12] "logic byteenable[71:0]" +Toggle 1to0 byteenable [11] "logic byteenable[71:0]" +Toggle 1to0 byteenable [10] "logic byteenable[71:0]" +Toggle 1to0 byteenable [9] "logic byteenable[71:0]" +Toggle 1to0 byteenable [8] "logic byteenable[71:0]" +Toggle 1to0 byteenable [7] "logic byteenable[71:0]" +Toggle 1to0 byteenable [6] "logic byteenable[71:0]" +Toggle 1to0 byteenable [5] "logic byteenable[71:0]" +Toggle 1to0 byteenable [4] "logic byteenable[71:0]" +Toggle 1to0 byteenable [3] "logic byteenable[71:0]" +Toggle 1to0 byteenable [2] "logic byteenable[71:0]" +Toggle 1to0 byteenable [1] "logic byteenable[71:0]" +Toggle 1to0 byteenable [0] "logic byteenable[71:0]" +Toggle 1to0 byteenable [63] "logic byteenable[71:0]" +Toggle 0to1 writedata [575] "logic writedata[575:0]" +Toggle 1to0 writedata [575] "logic writedata[575:0]" +Toggle 0to1 writedata [512] "logic writedata[575:0]" +Toggle 1to0 writedata [512] "logic writedata[575:0]" +Toggle 0to1 writedata [513] "logic writedata[575:0]" +Toggle 1to0 writedata [513] "logic writedata[575:0]" +Toggle 0to1 writedata [514] "logic writedata[575:0]" +Toggle 1to0 writedata [514] "logic writedata[575:0]" +Toggle 0to1 writedata [515] "logic writedata[575:0]" +Toggle 1to0 writedata [515] "logic writedata[575:0]" +Toggle 0to1 writedata [516] "logic writedata[575:0]" +Toggle 1to0 writedata [516] "logic writedata[575:0]" +Toggle 0to1 writedata [517] "logic writedata[575:0]" +Toggle 1to0 writedata [517] "logic writedata[575:0]" +Toggle 0to1 writedata [518] "logic writedata[575:0]" +Toggle 1to0 writedata [518] "logic writedata[575:0]" +Toggle 0to1 writedata [519] "logic writedata[575:0]" +Toggle 1to0 writedata [519] "logic writedata[575:0]" +Toggle 0to1 writedata [520] "logic writedata[575:0]" +Toggle 1to0 writedata [520] "logic writedata[575:0]" +Toggle 0to1 writedata [521] "logic writedata[575:0]" +Toggle 1to0 writedata [521] "logic writedata[575:0]" +Toggle 0to1 writedata [522] "logic writedata[575:0]" +Toggle 1to0 writedata [522] "logic writedata[575:0]" +Toggle 0to1 writedata [523] "logic writedata[575:0]" +Toggle 1to0 writedata [523] "logic writedata[575:0]" +Toggle 0to1 writedata [524] "logic writedata[575:0]" +Toggle 1to0 writedata [524] "logic writedata[575:0]" +Toggle 0to1 writedata [525] "logic writedata[575:0]" +Toggle 1to0 writedata [525] "logic writedata[575:0]" +Toggle 0to1 writedata [526] "logic writedata[575:0]" +Toggle 1to0 writedata [526] "logic writedata[575:0]" +Toggle 0to1 writedata [527] "logic writedata[575:0]" +Toggle 1to0 writedata [527] "logic writedata[575:0]" +Toggle 0to1 writedata [528] "logic writedata[575:0]" +Toggle 1to0 writedata [528] "logic writedata[575:0]" +Toggle 0to1 writedata [529] "logic writedata[575:0]" +Toggle 1to0 writedata [529] "logic writedata[575:0]" +Toggle 0to1 writedata [530] "logic writedata[575:0]" +Toggle 1to0 writedata [530] "logic writedata[575:0]" +Toggle 0to1 writedata [531] "logic writedata[575:0]" +Toggle 1to0 writedata [531] "logic writedata[575:0]" +Toggle 0to1 writedata [532] "logic writedata[575:0]" +Toggle 1to0 writedata [532] "logic writedata[575:0]" +Toggle 0to1 writedata [533] "logic writedata[575:0]" +Toggle 1to0 writedata [533] "logic writedata[575:0]" +Toggle 0to1 writedata [534] "logic writedata[575:0]" +Toggle 1to0 writedata [534] "logic writedata[575:0]" +Toggle 0to1 writedata [535] "logic writedata[575:0]" +Toggle 1to0 writedata [535] "logic writedata[575:0]" +Toggle 0to1 writedata [536] "logic writedata[575:0]" +Toggle 1to0 writedata [536] "logic writedata[575:0]" +Toggle 0to1 writedata [537] "logic writedata[575:0]" +Toggle 1to0 writedata [537] "logic writedata[575:0]" +Toggle 0to1 writedata [538] "logic writedata[575:0]" +Toggle 1to0 writedata [538] "logic writedata[575:0]" +Toggle 0to1 writedata [539] "logic writedata[575:0]" +Toggle 1to0 writedata [539] "logic writedata[575:0]" +Toggle 0to1 writedata [540] "logic writedata[575:0]" +Toggle 1to0 writedata [540] "logic writedata[575:0]" +Toggle 0to1 writedata [541] "logic writedata[575:0]" +Toggle 1to0 writedata [541] "logic writedata[575:0]" +Toggle 0to1 writedata [542] "logic writedata[575:0]" +Toggle 1to0 writedata [542] "logic writedata[575:0]" +Toggle 0to1 writedata [543] "logic writedata[575:0]" +Toggle 1to0 writedata [543] "logic writedata[575:0]" +Toggle 0to1 writedata [544] "logic writedata[575:0]" +Toggle 1to0 writedata [544] "logic writedata[575:0]" +Toggle 0to1 writedata [545] "logic writedata[575:0]" +Toggle 1to0 writedata [545] "logic writedata[575:0]" +Toggle 0to1 writedata [546] "logic writedata[575:0]" +Toggle 1to0 writedata [546] "logic writedata[575:0]" +Toggle 0to1 writedata [547] "logic writedata[575:0]" +Toggle 1to0 writedata [547] "logic writedata[575:0]" +Toggle 0to1 writedata [548] "logic writedata[575:0]" +Toggle 1to0 writedata [548] "logic writedata[575:0]" +Toggle 0to1 writedata [549] "logic writedata[575:0]" +Toggle 1to0 writedata [549] "logic writedata[575:0]" +Toggle 0to1 writedata [550] "logic writedata[575:0]" +Toggle 1to0 writedata [550] "logic writedata[575:0]" +Toggle 0to1 writedata [551] "logic writedata[575:0]" +Toggle 1to0 writedata [551] "logic writedata[575:0]" +Toggle 0to1 writedata [552] "logic writedata[575:0]" +Toggle 1to0 writedata [552] "logic writedata[575:0]" +Toggle 0to1 writedata [553] "logic writedata[575:0]" +Toggle 1to0 writedata [553] "logic writedata[575:0]" +Toggle 0to1 writedata [554] "logic writedata[575:0]" +Toggle 1to0 writedata [554] "logic writedata[575:0]" +Toggle 0to1 writedata [555] "logic writedata[575:0]" +Toggle 1to0 writedata [555] "logic writedata[575:0]" +Toggle 0to1 writedata [556] "logic writedata[575:0]" +Toggle 1to0 writedata [556] "logic writedata[575:0]" +Toggle 0to1 writedata [557] "logic writedata[575:0]" +Toggle 1to0 writedata [557] "logic writedata[575:0]" +Toggle 0to1 writedata [558] "logic writedata[575:0]" +Toggle 1to0 writedata [558] "logic writedata[575:0]" +Toggle 0to1 writedata [559] "logic writedata[575:0]" +Toggle 1to0 writedata [559] "logic writedata[575:0]" +Toggle 0to1 writedata [560] "logic writedata[575:0]" +Toggle 1to0 writedata [560] "logic writedata[575:0]" +Toggle 0to1 writedata [561] "logic writedata[575:0]" +Toggle 1to0 writedata [561] "logic writedata[575:0]" +Toggle 0to1 writedata [562] "logic writedata[575:0]" +Toggle 1to0 writedata [562] "logic writedata[575:0]" +Toggle 0to1 writedata [563] "logic writedata[575:0]" +Toggle 1to0 writedata [563] "logic writedata[575:0]" +Toggle 0to1 writedata [564] "logic writedata[575:0]" +Toggle 1to0 writedata [564] "logic writedata[575:0]" +Toggle 0to1 writedata [565] "logic writedata[575:0]" +Toggle 1to0 writedata [565] "logic writedata[575:0]" +Toggle 0to1 writedata [566] "logic writedata[575:0]" +Toggle 1to0 writedata [566] "logic writedata[575:0]" +Toggle 0to1 writedata [567] "logic writedata[575:0]" +Toggle 1to0 writedata [567] "logic writedata[575:0]" +Toggle 0to1 writedata [568] "logic writedata[575:0]" +Toggle 1to0 writedata [568] "logic writedata[575:0]" +Toggle 0to1 writedata [569] "logic writedata[575:0]" +Toggle 1to0 writedata [569] "logic writedata[575:0]" +Toggle 0to1 writedata [570] "logic writedata[575:0]" +Toggle 1to0 writedata [570] "logic writedata[575:0]" +Toggle 0to1 writedata [571] "logic writedata[575:0]" +Toggle 1to0 writedata [571] "logic writedata[575:0]" +Toggle 0to1 writedata [572] "logic writedata[575:0]" +Toggle 1to0 writedata [572] "logic writedata[575:0]" +Toggle 0to1 writedata [573] "logic writedata[575:0]" +Toggle 1to0 writedata [573] "logic writedata[575:0]" +Toggle 0to1 writedata [574] "logic writedata[575:0]" +Toggle 1to0 writedata [574] "logic writedata[575:0]" +Toggle 0to1 ecc_interrupt "logic ecc_interrupt" +Toggle 1to0 ecc_interrupt "logic ecc_interrupt" +Toggle 0to1 readdata [575] "logic readdata[575:0]" +Toggle 1to0 readdata [575] "logic readdata[575:0]" +Toggle 0to1 readdata [512] "logic readdata[575:0]" +Toggle 1to0 readdata [512] "logic readdata[575:0]" +Toggle 0to1 readdata [513] "logic readdata[575:0]" +Toggle 1to0 readdata [513] "logic readdata[575:0]" +Toggle 0to1 readdata [514] "logic readdata[575:0]" +Toggle 1to0 readdata [514] "logic readdata[575:0]" +Toggle 0to1 readdata [515] "logic readdata[575:0]" +Toggle 1to0 readdata [515] "logic readdata[575:0]" +Toggle 0to1 readdata [516] "logic readdata[575:0]" +Toggle 1to0 readdata [516] "logic readdata[575:0]" +Toggle 0to1 readdata [517] "logic readdata[575:0]" +Toggle 1to0 readdata [517] "logic readdata[575:0]" +Toggle 0to1 readdata [518] "logic readdata[575:0]" +Toggle 1to0 readdata [518] "logic readdata[575:0]" +Toggle 0to1 readdata [519] "logic readdata[575:0]" +Toggle 1to0 readdata [519] "logic readdata[575:0]" +Toggle 0to1 readdata [520] "logic readdata[575:0]" +Toggle 1to0 readdata [520] "logic readdata[575:0]" +Toggle 0to1 readdata [521] "logic readdata[575:0]" +Toggle 1to0 readdata [521] "logic readdata[575:0]" +Toggle 0to1 readdata [522] "logic readdata[575:0]" +Toggle 1to0 readdata [522] "logic readdata[575:0]" +Toggle 0to1 readdata [523] "logic readdata[575:0]" +Toggle 1to0 readdata [523] "logic readdata[575:0]" +Toggle 0to1 readdata [524] "logic readdata[575:0]" +Toggle 1to0 readdata [524] "logic readdata[575:0]" +Toggle 0to1 readdata [525] "logic readdata[575:0]" +Toggle 1to0 readdata [525] "logic readdata[575:0]" +Toggle 0to1 readdata [526] "logic readdata[575:0]" +Toggle 1to0 readdata [526] "logic readdata[575:0]" +Toggle 0to1 readdata [527] "logic readdata[575:0]" +Toggle 1to0 readdata [527] "logic readdata[575:0]" +Toggle 0to1 readdata [528] "logic readdata[575:0]" +Toggle 1to0 readdata [528] "logic readdata[575:0]" +Toggle 0to1 readdata [529] "logic readdata[575:0]" +Toggle 1to0 readdata [529] "logic readdata[575:0]" +Toggle 0to1 readdata [530] "logic readdata[575:0]" +Toggle 1to0 readdata [530] "logic readdata[575:0]" +Toggle 0to1 readdata [531] "logic readdata[575:0]" +Toggle 1to0 readdata [531] "logic readdata[575:0]" +Toggle 0to1 readdata [532] "logic readdata[575:0]" +Toggle 1to0 readdata [532] "logic readdata[575:0]" +Toggle 0to1 readdata [533] "logic readdata[575:0]" +Toggle 1to0 readdata [533] "logic readdata[575:0]" +Toggle 0to1 readdata [534] "logic readdata[575:0]" +Toggle 1to0 readdata [534] "logic readdata[575:0]" +Toggle 0to1 readdata [535] "logic readdata[575:0]" +Toggle 1to0 readdata [535] "logic readdata[575:0]" +Toggle 0to1 readdata [536] "logic readdata[575:0]" +Toggle 1to0 readdata [536] "logic readdata[575:0]" +Toggle 0to1 readdata [537] "logic readdata[575:0]" +Toggle 1to0 readdata [537] "logic readdata[575:0]" +Toggle 0to1 readdata [538] "logic readdata[575:0]" +Toggle 1to0 readdata [538] "logic readdata[575:0]" +Toggle 0to1 readdata [539] "logic readdata[575:0]" +Toggle 1to0 readdata [539] "logic readdata[575:0]" +Toggle 0to1 readdata [540] "logic readdata[575:0]" +Toggle 1to0 readdata [540] "logic readdata[575:0]" +Toggle 0to1 readdata [541] "logic readdata[575:0]" +Toggle 1to0 readdata [541] "logic readdata[575:0]" +Toggle 0to1 readdata [542] "logic readdata[575:0]" +Toggle 1to0 readdata [542] "logic readdata[575:0]" +Toggle 0to1 readdata [543] "logic readdata[575:0]" +Toggle 1to0 readdata [543] "logic readdata[575:0]" +Toggle 0to1 readdata [544] "logic readdata[575:0]" +Toggle 1to0 readdata [544] "logic readdata[575:0]" +Toggle 0to1 readdata [545] "logic readdata[575:0]" +Toggle 1to0 readdata [545] "logic readdata[575:0]" +Toggle 0to1 readdata [546] "logic readdata[575:0]" +Toggle 1to0 readdata [546] "logic readdata[575:0]" +Toggle 0to1 readdata [547] "logic readdata[575:0]" +Toggle 1to0 readdata [547] "logic readdata[575:0]" +Toggle 0to1 readdata [548] "logic readdata[575:0]" +Toggle 1to0 readdata [548] "logic readdata[575:0]" +Toggle 0to1 readdata [549] "logic readdata[575:0]" +Toggle 1to0 readdata [549] "logic readdata[575:0]" +Toggle 0to1 readdata [550] "logic readdata[575:0]" +Toggle 1to0 readdata [550] "logic readdata[575:0]" +Toggle 0to1 readdata [551] "logic readdata[575:0]" +Toggle 1to0 readdata [551] "logic readdata[575:0]" +Toggle 0to1 readdata [552] "logic readdata[575:0]" +Toggle 1to0 readdata [552] "logic readdata[575:0]" +Toggle 0to1 readdata [553] "logic readdata[575:0]" +Toggle 1to0 readdata [553] "logic readdata[575:0]" +Toggle 0to1 readdata [554] "logic readdata[575:0]" +Toggle 1to0 readdata [554] "logic readdata[575:0]" +Toggle 0to1 readdata [555] "logic readdata[575:0]" +Toggle 1to0 readdata [555] "logic readdata[575:0]" +Toggle 0to1 readdata [556] "logic readdata[575:0]" +Toggle 1to0 readdata [556] "logic readdata[575:0]" +Toggle 0to1 readdata [557] "logic readdata[575:0]" +Toggle 1to0 readdata [557] "logic readdata[575:0]" +Toggle 0to1 readdata [558] "logic readdata[575:0]" +Toggle 1to0 readdata [558] "logic readdata[575:0]" +Toggle 0to1 readdata [559] "logic readdata[575:0]" +Toggle 1to0 readdata [559] "logic readdata[575:0]" +Toggle 0to1 readdata [560] "logic readdata[575:0]" +Toggle 1to0 readdata [560] "logic readdata[575:0]" +Toggle 0to1 readdata [561] "logic readdata[575:0]" +Toggle 1to0 readdata [561] "logic readdata[575:0]" +Toggle 0to1 readdata [562] "logic readdata[575:0]" +Toggle 1to0 readdata [562] "logic readdata[575:0]" +Toggle 0to1 readdata [563] "logic readdata[575:0]" +Toggle 1to0 readdata [563] "logic readdata[575:0]" +Toggle 0to1 readdata [564] "logic readdata[575:0]" +Toggle 1to0 readdata [564] "logic readdata[575:0]" +Toggle 0to1 readdata [565] "logic readdata[575:0]" +Toggle 1to0 readdata [565] "logic readdata[575:0]" +Toggle 0to1 readdata [566] "logic readdata[575:0]" +Toggle 1to0 readdata [566] "logic readdata[575:0]" +Toggle 0to1 readdata [567] "logic readdata[575:0]" +Toggle 1to0 readdata [567] "logic readdata[575:0]" +Toggle 0to1 readdata [568] "logic readdata[575:0]" +Toggle 1to0 readdata [568] "logic readdata[575:0]" +Toggle 0to1 readdata [569] "logic readdata[575:0]" +Toggle 1to0 readdata [569] "logic readdata[575:0]" +Toggle 0to1 readdata [570] "logic readdata[575:0]" +Toggle 1to0 readdata [570] "logic readdata[575:0]" +Toggle 0to1 readdata [571] "logic readdata[575:0]" +Toggle 1to0 readdata [571] "logic readdata[575:0]" +Toggle 0to1 readdata [572] "logic readdata[575:0]" +Toggle 1to0 readdata [572] "logic readdata[575:0]" +Toggle 0to1 readdata [573] "logic readdata[575:0]" +Toggle 1to0 readdata [573] "logic readdata[575:0]" +Toggle 0to1 readdata [574] "logic readdata[575:0]" +Toggle 1to0 readdata [574] "logic readdata[575:0]" +Toggle 0to1 burstcount [6] "logic burstcount[6:0]" +Toggle 1to0 burstcount [6] "logic burstcount[6:0]" +Toggle 0to1 burstcount [3] "logic burstcount[6:0]" +Toggle 1to0 burstcount [3] "logic burstcount[6:0]" +Toggle 0to1 burstcount [4] "logic burstcount[6:0]" +Toggle 1to0 burstcount [4] "logic burstcount[6:0]" +Toggle 0to1 burstcount [5] "logic burstcount[6:0]" +Toggle 1to0 burstcount [5] "logic burstcount[6:0]" +Toggle 0to1 address [26] "logic address[26:0]" +Toggle 1to0 address [26] "logic address[26:0]" +Toggle 0to1 address [10] "logic address[26:0]" +Toggle 1to0 address [10] "logic address[26:0]" +Toggle 0to1 address [11] "logic address[26:0]" +Toggle 1to0 address [11] "logic address[26:0]" +Toggle 0to1 address [12] "logic address[26:0]" +Toggle 1to0 address [12] "logic address[26:0]" +Toggle 0to1 address [13] "logic address[26:0]" +Toggle 1to0 address [13] "logic address[26:0]" +Toggle 0to1 address [14] "logic address[26:0]" +Toggle 1to0 address [14] "logic address[26:0]" +Toggle 0to1 address [15] "logic address[26:0]" +Toggle 1to0 address [15] "logic address[26:0]" +Toggle 0to1 address [16] "logic address[26:0]" +Toggle 1to0 address [16] "logic address[26:0]" +Toggle 0to1 address [17] "logic address[26:0]" +Toggle 1to0 address [17] "logic address[26:0]" +Toggle 0to1 address [18] "logic address[26:0]" +Toggle 1to0 address [18] "logic address[26:0]" +Toggle 0to1 address [19] "logic address[26:0]" +Toggle 1to0 address [19] "logic address[26:0]" +Toggle 0to1 address [20] "logic address[26:0]" +Toggle 1to0 address [20] "logic address[26:0]" +Toggle 0to1 address [21] "logic address[26:0]" +Toggle 1to0 address [21] "logic address[26:0]" +Toggle 0to1 address [22] "logic address[26:0]" +Toggle 1to0 address [22] "logic address[26:0]" +Toggle 0to1 address [23] "logic address[26:0]" +Toggle 1to0 address [23] "logic address[26:0]" +Toggle 0to1 address [24] "logic address[26:0]" +Toggle 1to0 address [24] "logic address[26:0]" +Toggle 0to1 address [25] "logic address[26:0]" +Toggle 1to0 address [25] "logic address[26:0]" +Toggle 0to1 byteenable [71] "logic byteenable[71:0]" +Toggle 1to0 byteenable [71] "logic byteenable[71:0]" +Toggle 0to1 byteenable [64] "logic byteenable[71:0]" +Toggle 1to0 byteenable [64] "logic byteenable[71:0]" +Toggle 0to1 byteenable [65] "logic byteenable[71:0]" +Toggle 1to0 byteenable [65] "logic byteenable[71:0]" +Toggle 0to1 byteenable [66] "logic byteenable[71:0]" +Toggle 1to0 byteenable [66] "logic byteenable[71:0]" +Toggle 0to1 byteenable [67] "logic byteenable[71:0]" +Toggle 1to0 byteenable [67] "logic byteenable[71:0]" +Toggle 0to1 byteenable [68] "logic byteenable[71:0]" +Toggle 1to0 byteenable [68] "logic byteenable[71:0]" +Toggle 0to1 byteenable [69] "logic byteenable[71:0]" +Toggle 1to0 byteenable [69] "logic byteenable[71:0]" +Toggle 0to1 byteenable [70] "logic byteenable[71:0]" +Toggle 1to0 byteenable [70] "logic byteenable[71:0]" +CHECKSUM: "3021715206 3213032206" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.mem_if[0] +Toggle 1to0 byteenable [62] "logic byteenable[71:0]" +Toggle 1to0 byteenable [61] "logic byteenable[71:0]" +Toggle 1to0 byteenable [60] "logic byteenable[71:0]" +Toggle 1to0 byteenable [59] "logic byteenable[71:0]" +Toggle 1to0 byteenable [58] "logic byteenable[71:0]" +Toggle 1to0 byteenable [57] "logic byteenable[71:0]" +Toggle 1to0 byteenable [56] "logic byteenable[71:0]" +Toggle 1to0 byteenable [55] "logic byteenable[71:0]" +Toggle 1to0 byteenable [54] "logic byteenable[71:0]" +Toggle 1to0 byteenable [53] "logic byteenable[71:0]" +Toggle 1to0 byteenable [52] "logic byteenable[71:0]" +Toggle 1to0 byteenable [51] "logic byteenable[71:0]" +Toggle 1to0 byteenable [50] "logic byteenable[71:0]" +Toggle 1to0 byteenable [49] "logic byteenable[71:0]" +Toggle 1to0 byteenable [48] "logic byteenable[71:0]" +Toggle 1to0 byteenable [47] "logic byteenable[71:0]" +Toggle 1to0 byteenable [46] "logic byteenable[71:0]" +Toggle 1to0 byteenable [45] "logic byteenable[71:0]" +Toggle 1to0 byteenable [44] "logic byteenable[71:0]" +Toggle 1to0 byteenable [43] "logic byteenable[71:0]" +Toggle 1to0 byteenable [42] "logic byteenable[71:0]" +Toggle 1to0 byteenable [41] "logic byteenable[71:0]" +Toggle 1to0 byteenable [40] "logic byteenable[71:0]" +Toggle 1to0 byteenable [39] "logic byteenable[71:0]" +Toggle 1to0 byteenable [38] "logic byteenable[71:0]" +Toggle 1to0 byteenable [37] "logic byteenable[71:0]" +Toggle 1to0 byteenable [36] "logic byteenable[71:0]" +Toggle 1to0 byteenable [35] "logic byteenable[71:0]" +Toggle 1to0 byteenable [34] "logic byteenable[71:0]" +Toggle 1to0 byteenable [33] "logic byteenable[71:0]" +Toggle 1to0 byteenable [32] "logic byteenable[71:0]" +Toggle 1to0 byteenable [31] "logic byteenable[71:0]" +Toggle 1to0 byteenable [30] "logic byteenable[71:0]" +Toggle 1to0 byteenable [29] "logic byteenable[71:0]" +Toggle 1to0 byteenable [28] "logic byteenable[71:0]" +Toggle 1to0 byteenable [27] "logic byteenable[71:0]" +Toggle 1to0 byteenable [26] "logic byteenable[71:0]" +Toggle 1to0 byteenable [25] "logic byteenable[71:0]" +Toggle 1to0 byteenable [24] "logic byteenable[71:0]" +Toggle 1to0 byteenable [23] "logic byteenable[71:0]" +Toggle 1to0 byteenable [22] "logic byteenable[71:0]" +Toggle 1to0 byteenable [21] "logic byteenable[71:0]" +Toggle 1to0 byteenable [20] "logic byteenable[71:0]" +Toggle 1to0 byteenable [19] "logic byteenable[71:0]" +Toggle 1to0 byteenable [18] "logic byteenable[71:0]" +Toggle 1to0 byteenable [17] "logic byteenable[71:0]" +Toggle 1to0 byteenable [16] "logic byteenable[71:0]" +Toggle 1to0 byteenable [15] "logic byteenable[71:0]" +Toggle 1to0 byteenable [14] "logic byteenable[71:0]" +Toggle 1to0 byteenable [13] "logic byteenable[71:0]" +Toggle 1to0 byteenable [12] "logic byteenable[71:0]" +Toggle 1to0 byteenable [11] "logic byteenable[71:0]" +Toggle 1to0 byteenable [10] "logic byteenable[71:0]" +Toggle 1to0 byteenable [9] "logic byteenable[71:0]" +Toggle 1to0 byteenable [8] "logic byteenable[71:0]" +Toggle 1to0 byteenable [7] "logic byteenable[71:0]" +Toggle 1to0 byteenable [6] "logic byteenable[71:0]" +Toggle 1to0 byteenable [5] "logic byteenable[71:0]" +Toggle 1to0 byteenable [4] "logic byteenable[71:0]" +Toggle 1to0 byteenable [3] "logic byteenable[71:0]" +Toggle 1to0 byteenable [2] "logic byteenable[71:0]" +Toggle 1to0 byteenable [1] "logic byteenable[71:0]" +Toggle 1to0 byteenable [0] "logic byteenable[71:0]" +Toggle 1to0 byteenable [63] "logic byteenable[71:0]" +Toggle 1to0 burstcount [1] "logic burstcount[6:0]" +Toggle 1to0 burstcount [2] "logic burstcount[6:0]" +Toggle 0to1 ecc_interrupt "logic ecc_interrupt" +Toggle 1to0 ecc_interrupt "logic ecc_interrupt" +Toggle 0to1 writedata [575] "logic writedata[575:0]" +Toggle 1to0 writedata [575] "logic writedata[575:0]" +Toggle 0to1 writedata [512] "logic writedata[575:0]" +Toggle 1to0 writedata [512] "logic writedata[575:0]" +Toggle 0to1 writedata [513] "logic writedata[575:0]" +Toggle 1to0 writedata [513] "logic writedata[575:0]" +Toggle 0to1 writedata [514] "logic writedata[575:0]" +Toggle 1to0 writedata [514] "logic writedata[575:0]" +Toggle 0to1 writedata [515] "logic writedata[575:0]" +Toggle 1to0 writedata [515] "logic writedata[575:0]" +Toggle 0to1 writedata [516] "logic writedata[575:0]" +Toggle 1to0 writedata [516] "logic writedata[575:0]" +Toggle 0to1 writedata [517] "logic writedata[575:0]" +Toggle 1to0 writedata [517] "logic writedata[575:0]" +Toggle 0to1 writedata [518] "logic writedata[575:0]" +Toggle 1to0 writedata [518] "logic writedata[575:0]" +Toggle 0to1 writedata [519] "logic writedata[575:0]" +Toggle 1to0 writedata [519] "logic writedata[575:0]" +Toggle 0to1 writedata [520] "logic writedata[575:0]" +Toggle 1to0 writedata [520] "logic writedata[575:0]" +Toggle 0to1 writedata [521] "logic writedata[575:0]" +Toggle 1to0 writedata [521] "logic writedata[575:0]" +Toggle 0to1 writedata [522] "logic writedata[575:0]" +Toggle 1to0 writedata [522] "logic writedata[575:0]" +Toggle 0to1 writedata [523] "logic writedata[575:0]" +Toggle 1to0 writedata [523] "logic writedata[575:0]" +Toggle 0to1 writedata [524] "logic writedata[575:0]" +Toggle 1to0 writedata [524] "logic writedata[575:0]" +Toggle 0to1 writedata [525] "logic writedata[575:0]" +Toggle 1to0 writedata [525] "logic writedata[575:0]" +Toggle 0to1 writedata [526] "logic writedata[575:0]" +Toggle 1to0 writedata [526] "logic writedata[575:0]" +Toggle 0to1 writedata [527] "logic writedata[575:0]" +Toggle 1to0 writedata [527] "logic writedata[575:0]" +Toggle 0to1 writedata [528] "logic writedata[575:0]" +Toggle 1to0 writedata [528] "logic writedata[575:0]" +Toggle 0to1 writedata [529] "logic writedata[575:0]" +Toggle 1to0 writedata [529] "logic writedata[575:0]" +Toggle 0to1 writedata [530] "logic writedata[575:0]" +Toggle 1to0 writedata [530] "logic writedata[575:0]" +Toggle 0to1 writedata [531] "logic writedata[575:0]" +Toggle 1to0 writedata [531] "logic writedata[575:0]" +Toggle 0to1 writedata [532] "logic writedata[575:0]" +Toggle 1to0 writedata [532] "logic writedata[575:0]" +Toggle 0to1 writedata [533] "logic writedata[575:0]" +Toggle 1to0 writedata [533] "logic writedata[575:0]" +Toggle 0to1 writedata [534] "logic writedata[575:0]" +Toggle 1to0 writedata [534] "logic writedata[575:0]" +Toggle 0to1 writedata [535] "logic writedata[575:0]" +Toggle 1to0 writedata [535] "logic writedata[575:0]" +Toggle 0to1 writedata [536] "logic writedata[575:0]" +Toggle 1to0 writedata [536] "logic writedata[575:0]" +Toggle 0to1 writedata [537] "logic writedata[575:0]" +Toggle 1to0 writedata [537] "logic writedata[575:0]" +Toggle 0to1 writedata [538] "logic writedata[575:0]" +Toggle 1to0 writedata [538] "logic writedata[575:0]" +Toggle 0to1 writedata [539] "logic writedata[575:0]" +Toggle 1to0 writedata [539] "logic writedata[575:0]" +Toggle 0to1 writedata [540] "logic writedata[575:0]" +Toggle 1to0 writedata [540] "logic writedata[575:0]" +Toggle 0to1 writedata [541] "logic writedata[575:0]" +Toggle 1to0 writedata [541] "logic writedata[575:0]" +Toggle 0to1 writedata [542] "logic writedata[575:0]" +Toggle 1to0 writedata [542] "logic writedata[575:0]" +Toggle 0to1 writedata [543] "logic writedata[575:0]" +Toggle 1to0 writedata [543] "logic writedata[575:0]" +Toggle 0to1 writedata [544] "logic writedata[575:0]" +Toggle 1to0 writedata [544] "logic writedata[575:0]" +Toggle 0to1 writedata [545] "logic writedata[575:0]" +Toggle 1to0 writedata [545] "logic writedata[575:0]" +Toggle 0to1 writedata [546] "logic writedata[575:0]" +Toggle 1to0 writedata [546] "logic writedata[575:0]" +Toggle 0to1 writedata [547] "logic writedata[575:0]" +Toggle 1to0 writedata [547] "logic writedata[575:0]" +Toggle 0to1 writedata [548] "logic writedata[575:0]" +Toggle 1to0 writedata [548] "logic writedata[575:0]" +Toggle 0to1 writedata [549] "logic writedata[575:0]" +Toggle 1to0 writedata [549] "logic writedata[575:0]" +Toggle 0to1 writedata [550] "logic writedata[575:0]" +Toggle 1to0 writedata [550] "logic writedata[575:0]" +Toggle 0to1 writedata [551] "logic writedata[575:0]" +Toggle 1to0 writedata [551] "logic writedata[575:0]" +Toggle 0to1 writedata [552] "logic writedata[575:0]" +Toggle 1to0 writedata [552] "logic writedata[575:0]" +Toggle 0to1 writedata [553] "logic writedata[575:0]" +Toggle 1to0 writedata [553] "logic writedata[575:0]" +Toggle 0to1 writedata [554] "logic writedata[575:0]" +Toggle 1to0 writedata [554] "logic writedata[575:0]" +Toggle 0to1 writedata [555] "logic writedata[575:0]" +Toggle 1to0 writedata [555] "logic writedata[575:0]" +Toggle 0to1 writedata [556] "logic writedata[575:0]" +Toggle 1to0 writedata [556] "logic writedata[575:0]" +Toggle 0to1 writedata [557] "logic writedata[575:0]" +Toggle 1to0 writedata [557] "logic writedata[575:0]" +Toggle 0to1 writedata [558] "logic writedata[575:0]" +Toggle 1to0 writedata [558] "logic writedata[575:0]" +Toggle 0to1 writedata [559] "logic writedata[575:0]" +Toggle 1to0 writedata [559] "logic writedata[575:0]" +Toggle 0to1 writedata [560] "logic writedata[575:0]" +Toggle 1to0 writedata [560] "logic writedata[575:0]" +Toggle 0to1 writedata [561] "logic writedata[575:0]" +Toggle 1to0 writedata [561] "logic writedata[575:0]" +Toggle 0to1 writedata [562] "logic writedata[575:0]" +Toggle 1to0 writedata [562] "logic writedata[575:0]" +Toggle 0to1 writedata [563] "logic writedata[575:0]" +Toggle 1to0 writedata [563] "logic writedata[575:0]" +Toggle 0to1 writedata [564] "logic writedata[575:0]" +Toggle 1to0 writedata [564] "logic writedata[575:0]" +Toggle 0to1 writedata [565] "logic writedata[575:0]" +Toggle 1to0 writedata [565] "logic writedata[575:0]" +Toggle 0to1 writedata [566] "logic writedata[575:0]" +Toggle 1to0 writedata [566] "logic writedata[575:0]" +Toggle 0to1 writedata [567] "logic writedata[575:0]" +Toggle 1to0 writedata [567] "logic writedata[575:0]" +Toggle 0to1 writedata [568] "logic writedata[575:0]" +Toggle 1to0 writedata [568] "logic writedata[575:0]" +Toggle 0to1 writedata [569] "logic writedata[575:0]" +Toggle 1to0 writedata [569] "logic writedata[575:0]" +Toggle 0to1 writedata [570] "logic writedata[575:0]" +Toggle 1to0 writedata [570] "logic writedata[575:0]" +Toggle 0to1 writedata [571] "logic writedata[575:0]" +Toggle 1to0 writedata [571] "logic writedata[575:0]" +Toggle 0to1 writedata [572] "logic writedata[575:0]" +Toggle 1to0 writedata [572] "logic writedata[575:0]" +Toggle 0to1 writedata [573] "logic writedata[575:0]" +Toggle 1to0 writedata [573] "logic writedata[575:0]" +Toggle 0to1 writedata [574] "logic writedata[575:0]" +Toggle 1to0 writedata [574] "logic writedata[575:0]" +Toggle 0to1 readdata [575] "logic readdata[575:0]" +Toggle 1to0 readdata [575] "logic readdata[575:0]" +Toggle 0to1 readdata [512] "logic readdata[575:0]" +Toggle 1to0 readdata [512] "logic readdata[575:0]" +Toggle 0to1 readdata [513] "logic readdata[575:0]" +Toggle 1to0 readdata [513] "logic readdata[575:0]" +Toggle 0to1 readdata [514] "logic readdata[575:0]" +Toggle 1to0 readdata [514] "logic readdata[575:0]" +Toggle 0to1 readdata [515] "logic readdata[575:0]" +Toggle 1to0 readdata [515] "logic readdata[575:0]" +Toggle 0to1 readdata [516] "logic readdata[575:0]" +Toggle 1to0 readdata [516] "logic readdata[575:0]" +Toggle 0to1 readdata [517] "logic readdata[575:0]" +Toggle 1to0 readdata [517] "logic readdata[575:0]" +Toggle 0to1 readdata [518] "logic readdata[575:0]" +Toggle 1to0 readdata [518] "logic readdata[575:0]" +Toggle 0to1 readdata [519] "logic readdata[575:0]" +Toggle 1to0 readdata [519] "logic readdata[575:0]" +Toggle 0to1 readdata [520] "logic readdata[575:0]" +Toggle 1to0 readdata [520] "logic readdata[575:0]" +Toggle 0to1 readdata [521] "logic readdata[575:0]" +Toggle 1to0 readdata [521] "logic readdata[575:0]" +Toggle 0to1 readdata [522] "logic readdata[575:0]" +Toggle 1to0 readdata [522] "logic readdata[575:0]" +Toggle 0to1 readdata [523] "logic readdata[575:0]" +Toggle 1to0 readdata [523] "logic readdata[575:0]" +Toggle 0to1 readdata [524] "logic readdata[575:0]" +Toggle 1to0 readdata [524] "logic readdata[575:0]" +Toggle 0to1 readdata [525] "logic readdata[575:0]" +Toggle 1to0 readdata [525] "logic readdata[575:0]" +Toggle 0to1 readdata [526] "logic readdata[575:0]" +Toggle 1to0 readdata [526] "logic readdata[575:0]" +Toggle 0to1 readdata [527] "logic readdata[575:0]" +Toggle 1to0 readdata [527] "logic readdata[575:0]" +Toggle 0to1 readdata [528] "logic readdata[575:0]" +Toggle 1to0 readdata [528] "logic readdata[575:0]" +Toggle 0to1 readdata [529] "logic readdata[575:0]" +Toggle 1to0 readdata [529] "logic readdata[575:0]" +Toggle 0to1 readdata [530] "logic readdata[575:0]" +Toggle 1to0 readdata [530] "logic readdata[575:0]" +Toggle 0to1 readdata [531] "logic readdata[575:0]" +Toggle 1to0 readdata [531] "logic readdata[575:0]" +Toggle 0to1 readdata [532] "logic readdata[575:0]" +Toggle 1to0 readdata [532] "logic readdata[575:0]" +Toggle 0to1 readdata [533] "logic readdata[575:0]" +Toggle 1to0 readdata [533] "logic readdata[575:0]" +Toggle 0to1 readdata [534] "logic readdata[575:0]" +Toggle 1to0 readdata [534] "logic readdata[575:0]" +Toggle 0to1 readdata [535] "logic readdata[575:0]" +Toggle 1to0 readdata [535] "logic readdata[575:0]" +Toggle 0to1 readdata [536] "logic readdata[575:0]" +Toggle 1to0 readdata [536] "logic readdata[575:0]" +Toggle 0to1 readdata [537] "logic readdata[575:0]" +Toggle 1to0 readdata [537] "logic readdata[575:0]" +Toggle 0to1 readdata [538] "logic readdata[575:0]" +Toggle 1to0 readdata [538] "logic readdata[575:0]" +Toggle 0to1 readdata [539] "logic readdata[575:0]" +Toggle 1to0 readdata [539] "logic readdata[575:0]" +Toggle 0to1 readdata [540] "logic readdata[575:0]" +Toggle 1to0 readdata [540] "logic readdata[575:0]" +Toggle 0to1 readdata [541] "logic readdata[575:0]" +Toggle 1to0 readdata [541] "logic readdata[575:0]" +Toggle 0to1 readdata [542] "logic readdata[575:0]" +Toggle 1to0 readdata [542] "logic readdata[575:0]" +Toggle 0to1 readdata [543] "logic readdata[575:0]" +Toggle 1to0 readdata [543] "logic readdata[575:0]" +Toggle 0to1 readdata [544] "logic readdata[575:0]" +Toggle 1to0 readdata [544] "logic readdata[575:0]" +Toggle 0to1 readdata [545] "logic readdata[575:0]" +Toggle 1to0 readdata [545] "logic readdata[575:0]" +Toggle 0to1 readdata [546] "logic readdata[575:0]" +Toggle 1to0 readdata [546] "logic readdata[575:0]" +Toggle 0to1 readdata [547] "logic readdata[575:0]" +Toggle 1to0 readdata [547] "logic readdata[575:0]" +Toggle 0to1 readdata [548] "logic readdata[575:0]" +Toggle 1to0 readdata [548] "logic readdata[575:0]" +Toggle 0to1 readdata [549] "logic readdata[575:0]" +Toggle 1to0 readdata [549] "logic readdata[575:0]" +Toggle 0to1 readdata [550] "logic readdata[575:0]" +Toggle 1to0 readdata [550] "logic readdata[575:0]" +Toggle 0to1 readdata [551] "logic readdata[575:0]" +Toggle 1to0 readdata [551] "logic readdata[575:0]" +Toggle 0to1 readdata [552] "logic readdata[575:0]" +Toggle 1to0 readdata [552] "logic readdata[575:0]" +Toggle 0to1 readdata [553] "logic readdata[575:0]" +Toggle 1to0 readdata [553] "logic readdata[575:0]" +Toggle 0to1 readdata [554] "logic readdata[575:0]" +Toggle 1to0 readdata [554] "logic readdata[575:0]" +Toggle 0to1 readdata [555] "logic readdata[575:0]" +Toggle 1to0 readdata [555] "logic readdata[575:0]" +Toggle 0to1 readdata [556] "logic readdata[575:0]" +Toggle 1to0 readdata [556] "logic readdata[575:0]" +Toggle 0to1 readdata [557] "logic readdata[575:0]" +Toggle 1to0 readdata [557] "logic readdata[575:0]" +Toggle 0to1 readdata [558] "logic readdata[575:0]" +Toggle 1to0 readdata [558] "logic readdata[575:0]" +Toggle 0to1 readdata [559] "logic readdata[575:0]" +Toggle 1to0 readdata [559] "logic readdata[575:0]" +Toggle 0to1 readdata [560] "logic readdata[575:0]" +Toggle 1to0 readdata [560] "logic readdata[575:0]" +Toggle 0to1 readdata [561] "logic readdata[575:0]" +Toggle 1to0 readdata [561] "logic readdata[575:0]" +Toggle 0to1 readdata [562] "logic readdata[575:0]" +Toggle 1to0 readdata [562] "logic readdata[575:0]" +Toggle 0to1 readdata [563] "logic readdata[575:0]" +Toggle 1to0 readdata [563] "logic readdata[575:0]" +Toggle 0to1 readdata [564] "logic readdata[575:0]" +Toggle 1to0 readdata [564] "logic readdata[575:0]" +Toggle 0to1 readdata [565] "logic readdata[575:0]" +Toggle 1to0 readdata [565] "logic readdata[575:0]" +Toggle 0to1 readdata [566] "logic readdata[575:0]" +Toggle 1to0 readdata [566] "logic readdata[575:0]" +Toggle 0to1 readdata [567] "logic readdata[575:0]" +Toggle 1to0 readdata [567] "logic readdata[575:0]" +Toggle 0to1 readdata [568] "logic readdata[575:0]" +Toggle 1to0 readdata [568] "logic readdata[575:0]" +Toggle 0to1 readdata [569] "logic readdata[575:0]" +Toggle 1to0 readdata [569] "logic readdata[575:0]" +Toggle 0to1 readdata [570] "logic readdata[575:0]" +Toggle 1to0 readdata [570] "logic readdata[575:0]" +Toggle 0to1 readdata [571] "logic readdata[575:0]" +Toggle 1to0 readdata [571] "logic readdata[575:0]" +Toggle 0to1 readdata [572] "logic readdata[575:0]" +Toggle 1to0 readdata [572] "logic readdata[575:0]" +Toggle 0to1 readdata [573] "logic readdata[575:0]" +Toggle 1to0 readdata [573] "logic readdata[575:0]" +Toggle 0to1 readdata [574] "logic readdata[575:0]" +Toggle 1to0 readdata [574] "logic readdata[575:0]" +Toggle 0to1 burstcount [6] "logic burstcount[6:0]" +Toggle 1to0 burstcount [6] "logic burstcount[6:0]" +Toggle 0to1 burstcount [3] "logic burstcount[6:0]" +Toggle 1to0 burstcount [3] "logic burstcount[6:0]" +Toggle 0to1 burstcount [4] "logic burstcount[6:0]" +Toggle 1to0 burstcount [4] "logic burstcount[6:0]" +Toggle 0to1 burstcount [5] "logic burstcount[6:0]" +Toggle 1to0 burstcount [5] "logic burstcount[6:0]" +Toggle 0to1 address [26] "logic address[26:0]" +Toggle 1to0 address [26] "logic address[26:0]" +Toggle 0to1 address [10] "logic address[26:0]" +Toggle 1to0 address [10] "logic address[26:0]" +Toggle 0to1 address [11] "logic address[26:0]" +Toggle 1to0 address [11] "logic address[26:0]" +Toggle 0to1 address [12] "logic address[26:0]" +Toggle 1to0 address [12] "logic address[26:0]" +Toggle 0to1 address [13] "logic address[26:0]" +Toggle 1to0 address [13] "logic address[26:0]" +Toggle 0to1 address [14] "logic address[26:0]" +Toggle 1to0 address [14] "logic address[26:0]" +Toggle 0to1 address [15] "logic address[26:0]" +Toggle 1to0 address [15] "logic address[26:0]" +Toggle 0to1 address [16] "logic address[26:0]" +Toggle 1to0 address [16] "logic address[26:0]" +Toggle 0to1 address [17] "logic address[26:0]" +Toggle 1to0 address [17] "logic address[26:0]" +Toggle 0to1 address [18] "logic address[26:0]" +Toggle 1to0 address [18] "logic address[26:0]" +Toggle 0to1 address [19] "logic address[26:0]" +Toggle 1to0 address [19] "logic address[26:0]" +Toggle 0to1 address [20] "logic address[26:0]" +Toggle 1to0 address [20] "logic address[26:0]" +Toggle 0to1 address [21] "logic address[26:0]" +Toggle 1to0 address [21] "logic address[26:0]" +Toggle 0to1 address [22] "logic address[26:0]" +Toggle 1to0 address [22] "logic address[26:0]" +Toggle 0to1 address [23] "logic address[26:0]" +Toggle 1to0 address [23] "logic address[26:0]" +Toggle 0to1 address [24] "logic address[26:0]" +Toggle 1to0 address [24] "logic address[26:0]" +Toggle 0to1 address [25] "logic address[26:0]" +Toggle 1to0 address [25] "logic address[26:0]" +Toggle 0to1 byteenable [71] "logic byteenable[71:0]" +Toggle 1to0 byteenable [71] "logic byteenable[71:0]" +Toggle 0to1 byteenable [64] "logic byteenable[71:0]" +Toggle 1to0 byteenable [64] "logic byteenable[71:0]" +Toggle 0to1 byteenable [65] "logic byteenable[71:0]" +Toggle 1to0 byteenable [65] "logic byteenable[71:0]" +Toggle 0to1 byteenable [66] "logic byteenable[71:0]" +Toggle 1to0 byteenable [66] "logic byteenable[71:0]" +Toggle 0to1 byteenable [67] "logic byteenable[71:0]" +Toggle 1to0 byteenable [67] "logic byteenable[71:0]" +Toggle 0to1 byteenable [68] "logic byteenable[71:0]" +Toggle 1to0 byteenable [68] "logic byteenable[71:0]" +Toggle 0to1 byteenable [69] "logic byteenable[71:0]" +Toggle 1to0 byteenable [69] "logic byteenable[71:0]" +Toggle 0to1 byteenable [70] "logic byteenable[71:0]" +Toggle 1to0 byteenable [70] "logic byteenable[71:0]" +CHECKSUM: "3021715206 3213032206" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main_emif[1] +Toggle 1to0 burstcount [1] "logic burstcount[6:0]" +Toggle 1to0 burstcount [0] "logic burstcount[6:0]" +Toggle 1to0 burstcount [2] "logic burstcount[6:0]" +Toggle 1to0 byteenable [62] "logic byteenable[71:0]" +Toggle 1to0 byteenable [61] "logic byteenable[71:0]" +Toggle 1to0 byteenable [60] "logic byteenable[71:0]" +Toggle 1to0 byteenable [59] "logic byteenable[71:0]" +Toggle 1to0 byteenable [58] "logic byteenable[71:0]" +Toggle 1to0 byteenable [57] "logic byteenable[71:0]" +Toggle 1to0 byteenable [56] "logic byteenable[71:0]" +Toggle 1to0 byteenable [55] "logic byteenable[71:0]" +Toggle 1to0 byteenable [54] "logic byteenable[71:0]" +Toggle 1to0 byteenable [53] "logic byteenable[71:0]" +Toggle 1to0 byteenable [52] "logic byteenable[71:0]" +Toggle 1to0 byteenable [51] "logic byteenable[71:0]" +Toggle 1to0 byteenable [50] "logic byteenable[71:0]" +Toggle 1to0 byteenable [49] "logic byteenable[71:0]" +Toggle 1to0 byteenable [48] "logic byteenable[71:0]" +Toggle 1to0 byteenable [47] "logic byteenable[71:0]" +Toggle 1to0 byteenable [46] "logic byteenable[71:0]" +Toggle 1to0 byteenable [45] "logic byteenable[71:0]" +Toggle 1to0 byteenable [44] "logic byteenable[71:0]" +Toggle 1to0 byteenable [43] "logic byteenable[71:0]" +Toggle 1to0 byteenable [42] "logic byteenable[71:0]" +Toggle 1to0 byteenable [41] "logic byteenable[71:0]" +Toggle 1to0 byteenable [40] "logic byteenable[71:0]" +Toggle 1to0 byteenable [39] "logic byteenable[71:0]" +Toggle 1to0 byteenable [38] "logic byteenable[71:0]" +Toggle 1to0 byteenable [37] "logic byteenable[71:0]" +Toggle 1to0 byteenable [36] "logic byteenable[71:0]" +Toggle 1to0 byteenable [35] "logic byteenable[71:0]" +Toggle 1to0 byteenable [34] "logic byteenable[71:0]" +Toggle 1to0 byteenable [33] "logic byteenable[71:0]" +Toggle 1to0 byteenable [32] "logic byteenable[71:0]" +Toggle 1to0 byteenable [31] "logic byteenable[71:0]" +Toggle 1to0 byteenable [30] "logic byteenable[71:0]" +Toggle 1to0 byteenable [29] "logic byteenable[71:0]" +Toggle 1to0 byteenable [28] "logic byteenable[71:0]" +Toggle 1to0 byteenable [27] "logic byteenable[71:0]" +Toggle 1to0 byteenable [26] "logic byteenable[71:0]" +Toggle 1to0 byteenable [25] "logic byteenable[71:0]" +Toggle 1to0 byteenable [24] "logic byteenable[71:0]" +Toggle 1to0 byteenable [23] "logic byteenable[71:0]" +Toggle 1to0 byteenable [22] "logic byteenable[71:0]" +Toggle 1to0 byteenable [21] "logic byteenable[71:0]" +Toggle 1to0 byteenable [20] "logic byteenable[71:0]" +Toggle 1to0 byteenable [19] "logic byteenable[71:0]" +Toggle 1to0 byteenable [18] "logic byteenable[71:0]" +Toggle 1to0 byteenable [17] "logic byteenable[71:0]" +Toggle 1to0 byteenable [16] "logic byteenable[71:0]" +Toggle 1to0 byteenable [15] "logic byteenable[71:0]" +Toggle 1to0 byteenable [14] "logic byteenable[71:0]" +Toggle 1to0 byteenable [13] "logic byteenable[71:0]" +Toggle 1to0 byteenable [12] "logic byteenable[71:0]" +Toggle 1to0 byteenable [11] "logic byteenable[71:0]" +Toggle 1to0 byteenable [10] "logic byteenable[71:0]" +Toggle 1to0 byteenable [9] "logic byteenable[71:0]" +Toggle 1to0 byteenable [8] "logic byteenable[71:0]" +Toggle 1to0 byteenable [7] "logic byteenable[71:0]" +Toggle 1to0 byteenable [6] "logic byteenable[71:0]" +Toggle 1to0 byteenable [5] "logic byteenable[71:0]" +Toggle 1to0 byteenable [4] "logic byteenable[71:0]" +Toggle 1to0 byteenable [3] "logic byteenable[71:0]" +Toggle 1to0 byteenable [2] "logic byteenable[71:0]" +Toggle 1to0 byteenable [1] "logic byteenable[71:0]" +Toggle 1to0 byteenable [0] "logic byteenable[71:0]" +Toggle 1to0 byteenable [63] "logic byteenable[71:0]" +Toggle 0to1 ecc_interrupt "logic ecc_interrupt" +Toggle 1to0 ecc_interrupt "logic ecc_interrupt" +Toggle 0to1 writedata [575] "logic writedata[575:0]" +Toggle 1to0 writedata [575] "logic writedata[575:0]" +Toggle 0to1 writedata [512] "logic writedata[575:0]" +Toggle 1to0 writedata [512] "logic writedata[575:0]" +Toggle 0to1 writedata [513] "logic writedata[575:0]" +Toggle 1to0 writedata [513] "logic writedata[575:0]" +Toggle 0to1 writedata [514] "logic writedata[575:0]" +Toggle 1to0 writedata [514] "logic writedata[575:0]" +Toggle 0to1 writedata [515] "logic writedata[575:0]" +Toggle 1to0 writedata [515] "logic writedata[575:0]" +Toggle 0to1 writedata [516] "logic writedata[575:0]" +Toggle 1to0 writedata [516] "logic writedata[575:0]" +Toggle 0to1 writedata [517] "logic writedata[575:0]" +Toggle 1to0 writedata [517] "logic writedata[575:0]" +Toggle 0to1 writedata [518] "logic writedata[575:0]" +Toggle 1to0 writedata [518] "logic writedata[575:0]" +Toggle 0to1 writedata [519] "logic writedata[575:0]" +Toggle 1to0 writedata [519] "logic writedata[575:0]" +Toggle 0to1 writedata [520] "logic writedata[575:0]" +Toggle 1to0 writedata [520] "logic writedata[575:0]" +Toggle 0to1 writedata [521] "logic writedata[575:0]" +Toggle 1to0 writedata [521] "logic writedata[575:0]" +Toggle 0to1 writedata [522] "logic writedata[575:0]" +Toggle 1to0 writedata [522] "logic writedata[575:0]" +Toggle 0to1 writedata [523] "logic writedata[575:0]" +Toggle 1to0 writedata [523] "logic writedata[575:0]" +Toggle 0to1 writedata [524] "logic writedata[575:0]" +Toggle 1to0 writedata [524] "logic writedata[575:0]" +Toggle 0to1 writedata [525] "logic writedata[575:0]" +Toggle 1to0 writedata [525] "logic writedata[575:0]" +Toggle 0to1 writedata [526] "logic writedata[575:0]" +Toggle 1to0 writedata [526] "logic writedata[575:0]" +Toggle 0to1 writedata [527] "logic writedata[575:0]" +Toggle 1to0 writedata [527] "logic writedata[575:0]" +Toggle 0to1 writedata [528] "logic writedata[575:0]" +Toggle 1to0 writedata [528] "logic writedata[575:0]" +Toggle 0to1 writedata [529] "logic writedata[575:0]" +Toggle 1to0 writedata [529] "logic writedata[575:0]" +Toggle 0to1 writedata [530] "logic writedata[575:0]" +Toggle 1to0 writedata [530] "logic writedata[575:0]" +Toggle 0to1 writedata [531] "logic writedata[575:0]" +Toggle 1to0 writedata [531] "logic writedata[575:0]" +Toggle 0to1 writedata [532] "logic writedata[575:0]" +Toggle 1to0 writedata [532] "logic writedata[575:0]" +Toggle 0to1 writedata [533] "logic writedata[575:0]" +Toggle 1to0 writedata [533] "logic writedata[575:0]" +Toggle 0to1 writedata [534] "logic writedata[575:0]" +Toggle 1to0 writedata [534] "logic writedata[575:0]" +Toggle 0to1 writedata [535] "logic writedata[575:0]" +Toggle 1to0 writedata [535] "logic writedata[575:0]" +Toggle 0to1 writedata [536] "logic writedata[575:0]" +Toggle 1to0 writedata [536] "logic writedata[575:0]" +Toggle 0to1 writedata [537] "logic writedata[575:0]" +Toggle 1to0 writedata [537] "logic writedata[575:0]" +Toggle 0to1 writedata [538] "logic writedata[575:0]" +Toggle 1to0 writedata [538] "logic writedata[575:0]" +Toggle 0to1 writedata [539] "logic writedata[575:0]" +Toggle 1to0 writedata [539] "logic writedata[575:0]" +Toggle 0to1 writedata [540] "logic writedata[575:0]" +Toggle 1to0 writedata [540] "logic writedata[575:0]" +Toggle 0to1 writedata [541] "logic writedata[575:0]" +Toggle 1to0 writedata [541] "logic writedata[575:0]" +Toggle 0to1 writedata [542] "logic writedata[575:0]" +Toggle 1to0 writedata [542] "logic writedata[575:0]" +Toggle 0to1 writedata [543] "logic writedata[575:0]" +Toggle 1to0 writedata [543] "logic writedata[575:0]" +Toggle 0to1 writedata [544] "logic writedata[575:0]" +Toggle 1to0 writedata [544] "logic writedata[575:0]" +Toggle 0to1 writedata [545] "logic writedata[575:0]" +Toggle 1to0 writedata [545] "logic writedata[575:0]" +Toggle 0to1 writedata [546] "logic writedata[575:0]" +Toggle 1to0 writedata [546] "logic writedata[575:0]" +Toggle 0to1 writedata [547] "logic writedata[575:0]" +Toggle 1to0 writedata [547] "logic writedata[575:0]" +Toggle 0to1 writedata [548] "logic writedata[575:0]" +Toggle 1to0 writedata [548] "logic writedata[575:0]" +Toggle 0to1 writedata [549] "logic writedata[575:0]" +Toggle 1to0 writedata [549] "logic writedata[575:0]" +Toggle 0to1 writedata [550] "logic writedata[575:0]" +Toggle 1to0 writedata [550] "logic writedata[575:0]" +Toggle 0to1 writedata [551] "logic writedata[575:0]" +Toggle 1to0 writedata [551] "logic writedata[575:0]" +Toggle 0to1 writedata [552] "logic writedata[575:0]" +Toggle 1to0 writedata [552] "logic writedata[575:0]" +Toggle 0to1 writedata [553] "logic writedata[575:0]" +Toggle 1to0 writedata [553] "logic writedata[575:0]" +Toggle 0to1 writedata [554] "logic writedata[575:0]" +Toggle 1to0 writedata [554] "logic writedata[575:0]" +Toggle 0to1 writedata [555] "logic writedata[575:0]" +Toggle 1to0 writedata [555] "logic writedata[575:0]" +Toggle 0to1 writedata [556] "logic writedata[575:0]" +Toggle 1to0 writedata [556] "logic writedata[575:0]" +Toggle 0to1 writedata [557] "logic writedata[575:0]" +Toggle 1to0 writedata [557] "logic writedata[575:0]" +Toggle 0to1 writedata [558] "logic writedata[575:0]" +Toggle 1to0 writedata [558] "logic writedata[575:0]" +Toggle 0to1 writedata [559] "logic writedata[575:0]" +Toggle 1to0 writedata [559] "logic writedata[575:0]" +Toggle 0to1 writedata [560] "logic writedata[575:0]" +Toggle 1to0 writedata [560] "logic writedata[575:0]" +Toggle 0to1 writedata [561] "logic writedata[575:0]" +Toggle 1to0 writedata [561] "logic writedata[575:0]" +Toggle 0to1 writedata [562] "logic writedata[575:0]" +Toggle 1to0 writedata [562] "logic writedata[575:0]" +Toggle 0to1 writedata [563] "logic writedata[575:0]" +Toggle 1to0 writedata [563] "logic writedata[575:0]" +Toggle 0to1 writedata [564] "logic writedata[575:0]" +Toggle 1to0 writedata [564] "logic writedata[575:0]" +Toggle 0to1 writedata [565] "logic writedata[575:0]" +Toggle 1to0 writedata [565] "logic writedata[575:0]" +Toggle 0to1 writedata [566] "logic writedata[575:0]" +Toggle 1to0 writedata [566] "logic writedata[575:0]" +Toggle 0to1 writedata [567] "logic writedata[575:0]" +Toggle 1to0 writedata [567] "logic writedata[575:0]" +Toggle 0to1 writedata [568] "logic writedata[575:0]" +Toggle 1to0 writedata [568] "logic writedata[575:0]" +Toggle 0to1 writedata [569] "logic writedata[575:0]" +Toggle 1to0 writedata [569] "logic writedata[575:0]" +Toggle 0to1 writedata [570] "logic writedata[575:0]" +Toggle 1to0 writedata [570] "logic writedata[575:0]" +Toggle 0to1 writedata [571] "logic writedata[575:0]" +Toggle 1to0 writedata [571] "logic writedata[575:0]" +Toggle 0to1 writedata [572] "logic writedata[575:0]" +Toggle 1to0 writedata [572] "logic writedata[575:0]" +Toggle 0to1 writedata [573] "logic writedata[575:0]" +Toggle 1to0 writedata [573] "logic writedata[575:0]" +Toggle 0to1 writedata [574] "logic writedata[575:0]" +Toggle 1to0 writedata [574] "logic writedata[575:0]" +Toggle 0to1 readdata [575] "logic readdata[575:0]" +Toggle 1to0 readdata [575] "logic readdata[575:0]" +Toggle 0to1 readdata [512] "logic readdata[575:0]" +Toggle 1to0 readdata [512] "logic readdata[575:0]" +Toggle 0to1 readdata [513] "logic readdata[575:0]" +Toggle 1to0 readdata [513] "logic readdata[575:0]" +Toggle 0to1 readdata [514] "logic readdata[575:0]" +Toggle 1to0 readdata [514] "logic readdata[575:0]" +Toggle 0to1 readdata [515] "logic readdata[575:0]" +Toggle 1to0 readdata [515] "logic readdata[575:0]" +Toggle 0to1 readdata [516] "logic readdata[575:0]" +Toggle 1to0 readdata [516] "logic readdata[575:0]" +Toggle 0to1 readdata [517] "logic readdata[575:0]" +Toggle 1to0 readdata [517] "logic readdata[575:0]" +Toggle 0to1 readdata [518] "logic readdata[575:0]" +Toggle 1to0 readdata [518] "logic readdata[575:0]" +Toggle 0to1 readdata [519] "logic readdata[575:0]" +Toggle 1to0 readdata [519] "logic readdata[575:0]" +Toggle 0to1 readdata [520] "logic readdata[575:0]" +Toggle 1to0 readdata [520] "logic readdata[575:0]" +Toggle 0to1 readdata [521] "logic readdata[575:0]" +Toggle 1to0 readdata [521] "logic readdata[575:0]" +Toggle 0to1 readdata [522] "logic readdata[575:0]" +Toggle 1to0 readdata [522] "logic readdata[575:0]" +Toggle 0to1 readdata [523] "logic readdata[575:0]" +Toggle 1to0 readdata [523] "logic readdata[575:0]" +Toggle 0to1 readdata [524] "logic readdata[575:0]" +Toggle 1to0 readdata [524] "logic readdata[575:0]" +Toggle 0to1 readdata [525] "logic readdata[575:0]" +Toggle 1to0 readdata [525] "logic readdata[575:0]" +Toggle 0to1 readdata [526] "logic readdata[575:0]" +Toggle 1to0 readdata [526] "logic readdata[575:0]" +Toggle 0to1 readdata [527] "logic readdata[575:0]" +Toggle 1to0 readdata [527] "logic readdata[575:0]" +Toggle 0to1 readdata [528] "logic readdata[575:0]" +Toggle 1to0 readdata [528] "logic readdata[575:0]" +Toggle 0to1 readdata [529] "logic readdata[575:0]" +Toggle 1to0 readdata [529] "logic readdata[575:0]" +Toggle 0to1 readdata [530] "logic readdata[575:0]" +Toggle 1to0 readdata [530] "logic readdata[575:0]" +Toggle 0to1 readdata [531] "logic readdata[575:0]" +Toggle 1to0 readdata [531] "logic readdata[575:0]" +Toggle 0to1 readdata [532] "logic readdata[575:0]" +Toggle 1to0 readdata [532] "logic readdata[575:0]" +Toggle 0to1 readdata [533] "logic readdata[575:0]" +Toggle 1to0 readdata [533] "logic readdata[575:0]" +Toggle 0to1 readdata [534] "logic readdata[575:0]" +Toggle 1to0 readdata [534] "logic readdata[575:0]" +Toggle 0to1 readdata [535] "logic readdata[575:0]" +Toggle 1to0 readdata [535] "logic readdata[575:0]" +Toggle 0to1 readdata [536] "logic readdata[575:0]" +Toggle 1to0 readdata [536] "logic readdata[575:0]" +Toggle 0to1 readdata [537] "logic readdata[575:0]" +Toggle 1to0 readdata [537] "logic readdata[575:0]" +Toggle 0to1 readdata [538] "logic readdata[575:0]" +Toggle 1to0 readdata [538] "logic readdata[575:0]" +Toggle 0to1 readdata [539] "logic readdata[575:0]" +Toggle 1to0 readdata [539] "logic readdata[575:0]" +Toggle 0to1 readdata [540] "logic readdata[575:0]" +Toggle 1to0 readdata [540] "logic readdata[575:0]" +Toggle 0to1 readdata [541] "logic readdata[575:0]" +Toggle 1to0 readdata [541] "logic readdata[575:0]" +Toggle 0to1 readdata [542] "logic readdata[575:0]" +Toggle 1to0 readdata [542] "logic readdata[575:0]" +Toggle 0to1 readdata [543] "logic readdata[575:0]" +Toggle 1to0 readdata [543] "logic readdata[575:0]" +Toggle 0to1 readdata [544] "logic readdata[575:0]" +Toggle 1to0 readdata [544] "logic readdata[575:0]" +Toggle 0to1 readdata [545] "logic readdata[575:0]" +Toggle 1to0 readdata [545] "logic readdata[575:0]" +Toggle 0to1 readdata [546] "logic readdata[575:0]" +Toggle 1to0 readdata [546] "logic readdata[575:0]" +Toggle 0to1 readdata [547] "logic readdata[575:0]" +Toggle 1to0 readdata [547] "logic readdata[575:0]" +Toggle 0to1 readdata [548] "logic readdata[575:0]" +Toggle 1to0 readdata [548] "logic readdata[575:0]" +Toggle 0to1 readdata [549] "logic readdata[575:0]" +Toggle 1to0 readdata [549] "logic readdata[575:0]" +Toggle 0to1 readdata [550] "logic readdata[575:0]" +Toggle 1to0 readdata [550] "logic readdata[575:0]" +Toggle 0to1 readdata [551] "logic readdata[575:0]" +Toggle 1to0 readdata [551] "logic readdata[575:0]" +Toggle 0to1 readdata [552] "logic readdata[575:0]" +Toggle 1to0 readdata [552] "logic readdata[575:0]" +Toggle 0to1 readdata [553] "logic readdata[575:0]" +Toggle 1to0 readdata [553] "logic readdata[575:0]" +Toggle 0to1 readdata [554] "logic readdata[575:0]" +Toggle 1to0 readdata [554] "logic readdata[575:0]" +Toggle 0to1 readdata [555] "logic readdata[575:0]" +Toggle 1to0 readdata [555] "logic readdata[575:0]" +Toggle 0to1 readdata [556] "logic readdata[575:0]" +Toggle 1to0 readdata [556] "logic readdata[575:0]" +Toggle 0to1 readdata [557] "logic readdata[575:0]" +Toggle 1to0 readdata [557] "logic readdata[575:0]" +Toggle 0to1 readdata [558] "logic readdata[575:0]" +Toggle 1to0 readdata [558] "logic readdata[575:0]" +Toggle 0to1 readdata [559] "logic readdata[575:0]" +Toggle 1to0 readdata [559] "logic readdata[575:0]" +Toggle 0to1 readdata [560] "logic readdata[575:0]" +Toggle 1to0 readdata [560] "logic readdata[575:0]" +Toggle 0to1 readdata [561] "logic readdata[575:0]" +Toggle 1to0 readdata [561] "logic readdata[575:0]" +Toggle 0to1 readdata [562] "logic readdata[575:0]" +Toggle 1to0 readdata [562] "logic readdata[575:0]" +Toggle 0to1 readdata [563] "logic readdata[575:0]" +Toggle 1to0 readdata [563] "logic readdata[575:0]" +Toggle 0to1 readdata [564] "logic readdata[575:0]" +Toggle 1to0 readdata [564] "logic readdata[575:0]" +Toggle 0to1 readdata [565] "logic readdata[575:0]" +Toggle 1to0 readdata [565] "logic readdata[575:0]" +Toggle 0to1 readdata [566] "logic readdata[575:0]" +Toggle 1to0 readdata [566] "logic readdata[575:0]" +Toggle 0to1 readdata [567] "logic readdata[575:0]" +Toggle 1to0 readdata [567] "logic readdata[575:0]" +Toggle 0to1 readdata [568] "logic readdata[575:0]" +Toggle 1to0 readdata [568] "logic readdata[575:0]" +Toggle 0to1 readdata [569] "logic readdata[575:0]" +Toggle 1to0 readdata [569] "logic readdata[575:0]" +Toggle 0to1 readdata [570] "logic readdata[575:0]" +Toggle 1to0 readdata [570] "logic readdata[575:0]" +Toggle 0to1 readdata [571] "logic readdata[575:0]" +Toggle 1to0 readdata [571] "logic readdata[575:0]" +Toggle 0to1 readdata [572] "logic readdata[575:0]" +Toggle 1to0 readdata [572] "logic readdata[575:0]" +Toggle 0to1 readdata [573] "logic readdata[575:0]" +Toggle 1to0 readdata [573] "logic readdata[575:0]" +Toggle 0to1 readdata [574] "logic readdata[575:0]" +Toggle 1to0 readdata [574] "logic readdata[575:0]" +Toggle 0to1 burstcount [6] "logic burstcount[6:0]" +Toggle 1to0 burstcount [6] "logic burstcount[6:0]" +Toggle 0to1 burstcount [3] "logic burstcount[6:0]" +Toggle 1to0 burstcount [3] "logic burstcount[6:0]" +Toggle 0to1 burstcount [4] "logic burstcount[6:0]" +Toggle 1to0 burstcount [4] "logic burstcount[6:0]" +Toggle 0to1 burstcount [5] "logic burstcount[6:0]" +Toggle 1to0 burstcount [5] "logic burstcount[6:0]" +Toggle 0to1 address [26] "logic address[26:0]" +Toggle 1to0 address [26] "logic address[26:0]" +Toggle 0to1 address [10] "logic address[26:0]" +Toggle 1to0 address [10] "logic address[26:0]" +Toggle 0to1 address [11] "logic address[26:0]" +Toggle 1to0 address [11] "logic address[26:0]" +Toggle 0to1 address [12] "logic address[26:0]" +Toggle 1to0 address [12] "logic address[26:0]" +Toggle 0to1 address [13] "logic address[26:0]" +Toggle 1to0 address [13] "logic address[26:0]" +Toggle 0to1 address [14] "logic address[26:0]" +Toggle 1to0 address [14] "logic address[26:0]" +Toggle 0to1 address [15] "logic address[26:0]" +Toggle 1to0 address [15] "logic address[26:0]" +Toggle 0to1 address [16] "logic address[26:0]" +Toggle 1to0 address [16] "logic address[26:0]" +Toggle 0to1 address [17] "logic address[26:0]" +Toggle 1to0 address [17] "logic address[26:0]" +Toggle 0to1 address [18] "logic address[26:0]" +Toggle 1to0 address [18] "logic address[26:0]" +Toggle 0to1 address [19] "logic address[26:0]" +Toggle 1to0 address [19] "logic address[26:0]" +Toggle 0to1 address [20] "logic address[26:0]" +Toggle 1to0 address [20] "logic address[26:0]" +Toggle 0to1 address [21] "logic address[26:0]" +Toggle 1to0 address [21] "logic address[26:0]" +Toggle 0to1 address [22] "logic address[26:0]" +Toggle 1to0 address [22] "logic address[26:0]" +Toggle 0to1 address [23] "logic address[26:0]" +Toggle 1to0 address [23] "logic address[26:0]" +Toggle 0to1 address [24] "logic address[26:0]" +Toggle 1to0 address [24] "logic address[26:0]" +Toggle 0to1 address [25] "logic address[26:0]" +Toggle 1to0 address [25] "logic address[26:0]" +Toggle 0to1 byteenable [71] "logic byteenable[71:0]" +Toggle 1to0 byteenable [71] "logic byteenable[71:0]" +Toggle 0to1 byteenable [64] "logic byteenable[71:0]" +Toggle 1to0 byteenable [64] "logic byteenable[71:0]" +Toggle 0to1 byteenable [65] "logic byteenable[71:0]" +Toggle 1to0 byteenable [65] "logic byteenable[71:0]" +Toggle 0to1 byteenable [66] "logic byteenable[71:0]" +Toggle 1to0 byteenable [66] "logic byteenable[71:0]" +Toggle 0to1 byteenable [67] "logic byteenable[71:0]" +Toggle 1to0 byteenable [67] "logic byteenable[71:0]" +Toggle 0to1 byteenable [68] "logic byteenable[71:0]" +Toggle 1to0 byteenable [68] "logic byteenable[71:0]" +Toggle 0to1 byteenable [69] "logic byteenable[71:0]" +Toggle 1to0 byteenable [69] "logic byteenable[71:0]" +Toggle 0to1 byteenable [70] "logic byteenable[71:0]" +Toggle 1to0 byteenable [70] "logic byteenable[71:0]" +CHECKSUM: "3021715206 3213032206" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main_emif[0] +Toggle 1to0 burstcount [0] "logic burstcount[6:0]" +Toggle 1to0 byteenable [62] "logic byteenable[71:0]" +Toggle 1to0 byteenable [61] "logic byteenable[71:0]" +Toggle 1to0 byteenable [60] "logic byteenable[71:0]" +Toggle 1to0 byteenable [59] "logic byteenable[71:0]" +Toggle 1to0 byteenable [58] "logic byteenable[71:0]" +Toggle 1to0 byteenable [57] "logic byteenable[71:0]" +Toggle 1to0 byteenable [56] "logic byteenable[71:0]" +Toggle 1to0 byteenable [55] "logic byteenable[71:0]" +Toggle 1to0 byteenable [54] "logic byteenable[71:0]" +Toggle 1to0 byteenable [53] "logic byteenable[71:0]" +Toggle 1to0 byteenable [52] "logic byteenable[71:0]" +Toggle 1to0 byteenable [51] "logic byteenable[71:0]" +Toggle 1to0 byteenable [50] "logic byteenable[71:0]" +Toggle 1to0 byteenable [49] "logic byteenable[71:0]" +Toggle 1to0 byteenable [48] "logic byteenable[71:0]" +Toggle 1to0 byteenable [47] "logic byteenable[71:0]" +Toggle 1to0 byteenable [46] "logic byteenable[71:0]" +Toggle 1to0 byteenable [45] "logic byteenable[71:0]" +Toggle 1to0 byteenable [44] "logic byteenable[71:0]" +Toggle 1to0 byteenable [43] "logic byteenable[71:0]" +Toggle 1to0 byteenable [42] "logic byteenable[71:0]" +Toggle 1to0 byteenable [41] "logic byteenable[71:0]" +Toggle 1to0 byteenable [40] "logic byteenable[71:0]" +Toggle 1to0 byteenable [39] "logic byteenable[71:0]" +Toggle 1to0 byteenable [38] "logic byteenable[71:0]" +Toggle 1to0 byteenable [37] "logic byteenable[71:0]" +Toggle 1to0 byteenable [36] "logic byteenable[71:0]" +Toggle 1to0 byteenable [35] "logic byteenable[71:0]" +Toggle 1to0 byteenable [34] "logic byteenable[71:0]" +Toggle 1to0 byteenable [33] "logic byteenable[71:0]" +Toggle 1to0 byteenable [32] "logic byteenable[71:0]" +Toggle 1to0 byteenable [31] "logic byteenable[71:0]" +Toggle 1to0 byteenable [30] "logic byteenable[71:0]" +Toggle 1to0 byteenable [29] "logic byteenable[71:0]" +Toggle 1to0 byteenable [28] "logic byteenable[71:0]" +Toggle 1to0 byteenable [27] "logic byteenable[71:0]" +Toggle 1to0 byteenable [26] "logic byteenable[71:0]" +Toggle 1to0 byteenable [25] "logic byteenable[71:0]" +Toggle 1to0 byteenable [24] "logic byteenable[71:0]" +Toggle 1to0 byteenable [23] "logic byteenable[71:0]" +Toggle 1to0 byteenable [22] "logic byteenable[71:0]" +Toggle 1to0 byteenable [21] "logic byteenable[71:0]" +Toggle 1to0 byteenable [20] "logic byteenable[71:0]" +Toggle 1to0 byteenable [19] "logic byteenable[71:0]" +Toggle 1to0 byteenable [18] "logic byteenable[71:0]" +Toggle 1to0 byteenable [17] "logic byteenable[71:0]" +Toggle 1to0 byteenable [16] "logic byteenable[71:0]" +Toggle 1to0 byteenable [15] "logic byteenable[71:0]" +Toggle 1to0 byteenable [14] "logic byteenable[71:0]" +Toggle 1to0 byteenable [13] "logic byteenable[71:0]" +Toggle 1to0 byteenable [12] "logic byteenable[71:0]" +Toggle 1to0 byteenable [11] "logic byteenable[71:0]" +Toggle 1to0 byteenable [10] "logic byteenable[71:0]" +Toggle 1to0 byteenable [9] "logic byteenable[71:0]" +Toggle 1to0 byteenable [8] "logic byteenable[71:0]" +Toggle 1to0 byteenable [7] "logic byteenable[71:0]" +Toggle 1to0 byteenable [6] "logic byteenable[71:0]" +Toggle 1to0 byteenable [5] "logic byteenable[71:0]" +Toggle 1to0 byteenable [4] "logic byteenable[71:0]" +Toggle 1to0 byteenable [3] "logic byteenable[71:0]" +Toggle 1to0 byteenable [2] "logic byteenable[71:0]" +Toggle 1to0 byteenable [1] "logic byteenable[71:0]" +Toggle 1to0 byteenable [0] "logic byteenable[71:0]" +Toggle 1to0 byteenable [63] "logic byteenable[71:0]" +Toggle 0to1 ecc_interrupt "logic ecc_interrupt" +Toggle 1to0 ecc_interrupt "logic ecc_interrupt" +Toggle 0to1 readdata [575] "logic readdata[575:0]" +Toggle 1to0 readdata [575] "logic readdata[575:0]" +Toggle 0to1 readdata [512] "logic readdata[575:0]" +Toggle 1to0 readdata [512] "logic readdata[575:0]" +Toggle 0to1 readdata [513] "logic readdata[575:0]" +Toggle 1to0 readdata [513] "logic readdata[575:0]" +Toggle 0to1 readdata [514] "logic readdata[575:0]" +Toggle 1to0 readdata [514] "logic readdata[575:0]" +Toggle 0to1 readdata [515] "logic readdata[575:0]" +Toggle 1to0 readdata [515] "logic readdata[575:0]" +Toggle 0to1 readdata [516] "logic readdata[575:0]" +Toggle 1to0 readdata [516] "logic readdata[575:0]" +Toggle 0to1 readdata [517] "logic readdata[575:0]" +Toggle 1to0 readdata [517] "logic readdata[575:0]" +Toggle 0to1 readdata [518] "logic readdata[575:0]" +Toggle 1to0 readdata [518] "logic readdata[575:0]" +Toggle 0to1 readdata [519] "logic readdata[575:0]" +Toggle 1to0 readdata [519] "logic readdata[575:0]" +Toggle 0to1 readdata [520] "logic readdata[575:0]" +Toggle 1to0 readdata [520] "logic readdata[575:0]" +Toggle 0to1 readdata [521] "logic readdata[575:0]" +Toggle 1to0 readdata [521] "logic readdata[575:0]" +Toggle 0to1 readdata [522] "logic readdata[575:0]" +Toggle 1to0 readdata [522] "logic readdata[575:0]" +Toggle 0to1 readdata [523] "logic readdata[575:0]" +Toggle 1to0 readdata [523] "logic readdata[575:0]" +Toggle 0to1 readdata [524] "logic readdata[575:0]" +Toggle 1to0 readdata [524] "logic readdata[575:0]" +Toggle 0to1 readdata [525] "logic readdata[575:0]" +Toggle 1to0 readdata [525] "logic readdata[575:0]" +Toggle 0to1 readdata [526] "logic readdata[575:0]" +Toggle 1to0 readdata [526] "logic readdata[575:0]" +Toggle 0to1 readdata [527] "logic readdata[575:0]" +Toggle 1to0 readdata [527] "logic readdata[575:0]" +Toggle 0to1 readdata [528] "logic readdata[575:0]" +Toggle 1to0 readdata [528] "logic readdata[575:0]" +Toggle 0to1 readdata [529] "logic readdata[575:0]" +Toggle 1to0 readdata [529] "logic readdata[575:0]" +Toggle 0to1 readdata [530] "logic readdata[575:0]" +Toggle 1to0 readdata [530] "logic readdata[575:0]" +Toggle 0to1 readdata [531] "logic readdata[575:0]" +Toggle 1to0 readdata [531] "logic readdata[575:0]" +Toggle 0to1 readdata [532] "logic readdata[575:0]" +Toggle 1to0 readdata [532] "logic readdata[575:0]" +Toggle 0to1 readdata [533] "logic readdata[575:0]" +Toggle 1to0 readdata [533] "logic readdata[575:0]" +Toggle 0to1 readdata [534] "logic readdata[575:0]" +Toggle 1to0 readdata [534] "logic readdata[575:0]" +Toggle 0to1 readdata [535] "logic readdata[575:0]" +Toggle 1to0 readdata [535] "logic readdata[575:0]" +Toggle 0to1 readdata [536] "logic readdata[575:0]" +Toggle 1to0 readdata [536] "logic readdata[575:0]" +Toggle 0to1 readdata [537] "logic readdata[575:0]" +Toggle 1to0 readdata [537] "logic readdata[575:0]" +Toggle 0to1 readdata [538] "logic readdata[575:0]" +Toggle 1to0 readdata [538] "logic readdata[575:0]" +Toggle 0to1 readdata [539] "logic readdata[575:0]" +Toggle 1to0 readdata [539] "logic readdata[575:0]" +Toggle 0to1 readdata [540] "logic readdata[575:0]" +Toggle 1to0 readdata [540] "logic readdata[575:0]" +Toggle 0to1 readdata [541] "logic readdata[575:0]" +Toggle 1to0 readdata [541] "logic readdata[575:0]" +Toggle 0to1 readdata [542] "logic readdata[575:0]" +Toggle 1to0 readdata [542] "logic readdata[575:0]" +Toggle 0to1 readdata [543] "logic readdata[575:0]" +Toggle 1to0 readdata [543] "logic readdata[575:0]" +Toggle 0to1 readdata [544] "logic readdata[575:0]" +Toggle 1to0 readdata [544] "logic readdata[575:0]" +Toggle 0to1 readdata [545] "logic readdata[575:0]" +Toggle 1to0 readdata [545] "logic readdata[575:0]" +Toggle 0to1 readdata [546] "logic readdata[575:0]" +Toggle 1to0 readdata [546] "logic readdata[575:0]" +Toggle 0to1 readdata [547] "logic readdata[575:0]" +Toggle 1to0 readdata [547] "logic readdata[575:0]" +Toggle 0to1 readdata [548] "logic readdata[575:0]" +Toggle 1to0 readdata [548] "logic readdata[575:0]" +Toggle 0to1 readdata [549] "logic readdata[575:0]" +Toggle 1to0 readdata [549] "logic readdata[575:0]" +Toggle 0to1 readdata [550] "logic readdata[575:0]" +Toggle 1to0 readdata [550] "logic readdata[575:0]" +Toggle 0to1 readdata [551] "logic readdata[575:0]" +Toggle 1to0 readdata [551] "logic readdata[575:0]" +Toggle 0to1 readdata [552] "logic readdata[575:0]" +Toggle 1to0 readdata [552] "logic readdata[575:0]" +Toggle 0to1 readdata [553] "logic readdata[575:0]" +Toggle 1to0 readdata [553] "logic readdata[575:0]" +Toggle 0to1 readdata [554] "logic readdata[575:0]" +Toggle 1to0 readdata [554] "logic readdata[575:0]" +Toggle 0to1 readdata [555] "logic readdata[575:0]" +Toggle 1to0 readdata [555] "logic readdata[575:0]" +Toggle 0to1 readdata [556] "logic readdata[575:0]" +Toggle 1to0 readdata [556] "logic readdata[575:0]" +Toggle 0to1 readdata [557] "logic readdata[575:0]" +Toggle 1to0 readdata [557] "logic readdata[575:0]" +Toggle 0to1 readdata [558] "logic readdata[575:0]" +Toggle 1to0 readdata [558] "logic readdata[575:0]" +Toggle 0to1 readdata [559] "logic readdata[575:0]" +Toggle 1to0 readdata [559] "logic readdata[575:0]" +Toggle 0to1 readdata [560] "logic readdata[575:0]" +Toggle 1to0 readdata [560] "logic readdata[575:0]" +Toggle 0to1 readdata [561] "logic readdata[575:0]" +Toggle 1to0 readdata [561] "logic readdata[575:0]" +Toggle 0to1 readdata [562] "logic readdata[575:0]" +Toggle 1to0 readdata [562] "logic readdata[575:0]" +Toggle 0to1 readdata [563] "logic readdata[575:0]" +Toggle 1to0 readdata [563] "logic readdata[575:0]" +Toggle 0to1 readdata [564] "logic readdata[575:0]" +Toggle 1to0 readdata [564] "logic readdata[575:0]" +Toggle 0to1 readdata [565] "logic readdata[575:0]" +Toggle 1to0 readdata [565] "logic readdata[575:0]" +Toggle 0to1 readdata [566] "logic readdata[575:0]" +Toggle 1to0 readdata [566] "logic readdata[575:0]" +Toggle 0to1 readdata [567] "logic readdata[575:0]" +Toggle 1to0 readdata [567] "logic readdata[575:0]" +Toggle 0to1 readdata [568] "logic readdata[575:0]" +Toggle 1to0 readdata [568] "logic readdata[575:0]" +Toggle 0to1 readdata [569] "logic readdata[575:0]" +Toggle 1to0 readdata [569] "logic readdata[575:0]" +Toggle 0to1 readdata [570] "logic readdata[575:0]" +Toggle 1to0 readdata [570] "logic readdata[575:0]" +Toggle 0to1 readdata [571] "logic readdata[575:0]" +Toggle 1to0 readdata [571] "logic readdata[575:0]" +Toggle 0to1 readdata [572] "logic readdata[575:0]" +Toggle 1to0 readdata [572] "logic readdata[575:0]" +Toggle 0to1 readdata [573] "logic readdata[575:0]" +Toggle 1to0 readdata [573] "logic readdata[575:0]" +Toggle 0to1 readdata [574] "logic readdata[575:0]" +Toggle 1to0 readdata [574] "logic readdata[575:0]" +Toggle 0to1 writedata [575] "logic writedata[575:0]" +Toggle 1to0 writedata [575] "logic writedata[575:0]" +Toggle 0to1 writedata [512] "logic writedata[575:0]" +Toggle 1to0 writedata [512] "logic writedata[575:0]" +Toggle 0to1 writedata [513] "logic writedata[575:0]" +Toggle 1to0 writedata [513] "logic writedata[575:0]" +Toggle 0to1 writedata [514] "logic writedata[575:0]" +Toggle 1to0 writedata [514] "logic writedata[575:0]" +Toggle 0to1 writedata [515] "logic writedata[575:0]" +Toggle 1to0 writedata [515] "logic writedata[575:0]" +Toggle 0to1 writedata [516] "logic writedata[575:0]" +Toggle 1to0 writedata [516] "logic writedata[575:0]" +Toggle 0to1 writedata [517] "logic writedata[575:0]" +Toggle 1to0 writedata [517] "logic writedata[575:0]" +Toggle 0to1 writedata [518] "logic writedata[575:0]" +Toggle 1to0 writedata [518] "logic writedata[575:0]" +Toggle 0to1 writedata [519] "logic writedata[575:0]" +Toggle 1to0 writedata [519] "logic writedata[575:0]" +Toggle 0to1 writedata [520] "logic writedata[575:0]" +Toggle 1to0 writedata [520] "logic writedata[575:0]" +Toggle 0to1 writedata [521] "logic writedata[575:0]" +Toggle 1to0 writedata [521] "logic writedata[575:0]" +Toggle 0to1 writedata [522] "logic writedata[575:0]" +Toggle 1to0 writedata [522] "logic writedata[575:0]" +Toggle 0to1 writedata [523] "logic writedata[575:0]" +Toggle 1to0 writedata [523] "logic writedata[575:0]" +Toggle 0to1 writedata [524] "logic writedata[575:0]" +Toggle 1to0 writedata [524] "logic writedata[575:0]" +Toggle 0to1 writedata [525] "logic writedata[575:0]" +Toggle 1to0 writedata [525] "logic writedata[575:0]" +Toggle 0to1 writedata [526] "logic writedata[575:0]" +Toggle 1to0 writedata [526] "logic writedata[575:0]" +Toggle 0to1 writedata [527] "logic writedata[575:0]" +Toggle 1to0 writedata [527] "logic writedata[575:0]" +Toggle 0to1 writedata [528] "logic writedata[575:0]" +Toggle 1to0 writedata [528] "logic writedata[575:0]" +Toggle 0to1 writedata [529] "logic writedata[575:0]" +Toggle 1to0 writedata [529] "logic writedata[575:0]" +Toggle 0to1 writedata [530] "logic writedata[575:0]" +Toggle 1to0 writedata [530] "logic writedata[575:0]" +Toggle 0to1 writedata [531] "logic writedata[575:0]" +Toggle 1to0 writedata [531] "logic writedata[575:0]" +Toggle 0to1 writedata [532] "logic writedata[575:0]" +Toggle 1to0 writedata [532] "logic writedata[575:0]" +Toggle 0to1 writedata [533] "logic writedata[575:0]" +Toggle 1to0 writedata [533] "logic writedata[575:0]" +Toggle 0to1 writedata [534] "logic writedata[575:0]" +Toggle 1to0 writedata [534] "logic writedata[575:0]" +Toggle 0to1 writedata [535] "logic writedata[575:0]" +Toggle 1to0 writedata [535] "logic writedata[575:0]" +Toggle 0to1 writedata [536] "logic writedata[575:0]" +Toggle 1to0 writedata [536] "logic writedata[575:0]" +Toggle 0to1 writedata [537] "logic writedata[575:0]" +Toggle 1to0 writedata [537] "logic writedata[575:0]" +Toggle 0to1 writedata [538] "logic writedata[575:0]" +Toggle 1to0 writedata [538] "logic writedata[575:0]" +Toggle 0to1 writedata [539] "logic writedata[575:0]" +Toggle 1to0 writedata [539] "logic writedata[575:0]" +Toggle 0to1 writedata [540] "logic writedata[575:0]" +Toggle 1to0 writedata [540] "logic writedata[575:0]" +Toggle 0to1 writedata [541] "logic writedata[575:0]" +Toggle 1to0 writedata [541] "logic writedata[575:0]" +Toggle 0to1 writedata [542] "logic writedata[575:0]" +Toggle 1to0 writedata [542] "logic writedata[575:0]" +Toggle 0to1 writedata [543] "logic writedata[575:0]" +Toggle 1to0 writedata [543] "logic writedata[575:0]" +Toggle 0to1 writedata [544] "logic writedata[575:0]" +Toggle 1to0 writedata [544] "logic writedata[575:0]" +Toggle 0to1 writedata [545] "logic writedata[575:0]" +Toggle 1to0 writedata [545] "logic writedata[575:0]" +Toggle 0to1 writedata [546] "logic writedata[575:0]" +Toggle 1to0 writedata [546] "logic writedata[575:0]" +Toggle 0to1 writedata [547] "logic writedata[575:0]" +Toggle 1to0 writedata [547] "logic writedata[575:0]" +Toggle 0to1 writedata [548] "logic writedata[575:0]" +Toggle 1to0 writedata [548] "logic writedata[575:0]" +Toggle 0to1 writedata [549] "logic writedata[575:0]" +Toggle 1to0 writedata [549] "logic writedata[575:0]" +Toggle 0to1 writedata [550] "logic writedata[575:0]" +Toggle 1to0 writedata [550] "logic writedata[575:0]" +Toggle 0to1 writedata [551] "logic writedata[575:0]" +Toggle 1to0 writedata [551] "logic writedata[575:0]" +Toggle 0to1 writedata [552] "logic writedata[575:0]" +Toggle 1to0 writedata [552] "logic writedata[575:0]" +Toggle 0to1 writedata [553] "logic writedata[575:0]" +Toggle 1to0 writedata [553] "logic writedata[575:0]" +Toggle 0to1 writedata [554] "logic writedata[575:0]" +Toggle 1to0 writedata [554] "logic writedata[575:0]" +Toggle 0to1 writedata [555] "logic writedata[575:0]" +Toggle 1to0 writedata [555] "logic writedata[575:0]" +Toggle 0to1 writedata [556] "logic writedata[575:0]" +Toggle 1to0 writedata [556] "logic writedata[575:0]" +Toggle 0to1 writedata [557] "logic writedata[575:0]" +Toggle 1to0 writedata [557] "logic writedata[575:0]" +Toggle 0to1 writedata [558] "logic writedata[575:0]" +Toggle 1to0 writedata [558] "logic writedata[575:0]" +Toggle 0to1 writedata [559] "logic writedata[575:0]" +Toggle 1to0 writedata [559] "logic writedata[575:0]" +Toggle 0to1 writedata [560] "logic writedata[575:0]" +Toggle 1to0 writedata [560] "logic writedata[575:0]" +Toggle 0to1 writedata [561] "logic writedata[575:0]" +Toggle 1to0 writedata [561] "logic writedata[575:0]" +Toggle 0to1 writedata [562] "logic writedata[575:0]" +Toggle 1to0 writedata [562] "logic writedata[575:0]" +Toggle 0to1 writedata [563] "logic writedata[575:0]" +Toggle 1to0 writedata [563] "logic writedata[575:0]" +Toggle 0to1 writedata [564] "logic writedata[575:0]" +Toggle 1to0 writedata [564] "logic writedata[575:0]" +Toggle 0to1 writedata [565] "logic writedata[575:0]" +Toggle 1to0 writedata [565] "logic writedata[575:0]" +Toggle 0to1 writedata [566] "logic writedata[575:0]" +Toggle 1to0 writedata [566] "logic writedata[575:0]" +Toggle 0to1 writedata [567] "logic writedata[575:0]" +Toggle 1to0 writedata [567] "logic writedata[575:0]" +Toggle 0to1 writedata [568] "logic writedata[575:0]" +Toggle 1to0 writedata [568] "logic writedata[575:0]" +Toggle 0to1 writedata [569] "logic writedata[575:0]" +Toggle 1to0 writedata [569] "logic writedata[575:0]" +Toggle 0to1 writedata [570] "logic writedata[575:0]" +Toggle 1to0 writedata [570] "logic writedata[575:0]" +Toggle 0to1 writedata [571] "logic writedata[575:0]" +Toggle 1to0 writedata [571] "logic writedata[575:0]" +Toggle 0to1 writedata [572] "logic writedata[575:0]" +Toggle 1to0 writedata [572] "logic writedata[575:0]" +Toggle 0to1 writedata [573] "logic writedata[575:0]" +Toggle 1to0 writedata [573] "logic writedata[575:0]" +Toggle 0to1 writedata [574] "logic writedata[575:0]" +Toggle 1to0 writedata [574] "logic writedata[575:0]" +Toggle 0to1 burstcount [6] "logic burstcount[6:0]" +Toggle 1to0 burstcount [6] "logic burstcount[6:0]" +Toggle 0to1 burstcount [1] "logic burstcount[6:0]" +Toggle 1to0 burstcount [1] "logic burstcount[6:0]" +Toggle 0to1 burstcount [2] "logic burstcount[6:0]" +Toggle 1to0 burstcount [2] "logic burstcount[6:0]" +Toggle 0to1 burstcount [3] "logic burstcount[6:0]" +Toggle 1to0 burstcount [3] "logic burstcount[6:0]" +Toggle 0to1 burstcount [4] "logic burstcount[6:0]" +Toggle 1to0 burstcount [4] "logic burstcount[6:0]" +Toggle 0to1 burstcount [5] "logic burstcount[6:0]" +Toggle 1to0 burstcount [5] "logic burstcount[6:0]" +Toggle 0to1 address [26] "logic address[26:0]" +Toggle 1to0 address [26] "logic address[26:0]" +Toggle 0to1 address [10] "logic address[26:0]" +Toggle 1to0 address [10] "logic address[26:0]" +Toggle 0to1 address [11] "logic address[26:0]" +Toggle 1to0 address [11] "logic address[26:0]" +Toggle 0to1 address [12] "logic address[26:0]" +Toggle 1to0 address [12] "logic address[26:0]" +Toggle 0to1 address [13] "logic address[26:0]" +Toggle 1to0 address [13] "logic address[26:0]" +Toggle 0to1 address [14] "logic address[26:0]" +Toggle 1to0 address [14] "logic address[26:0]" +Toggle 0to1 address [15] "logic address[26:0]" +Toggle 1to0 address [15] "logic address[26:0]" +Toggle 0to1 address [16] "logic address[26:0]" +Toggle 1to0 address [16] "logic address[26:0]" +Toggle 0to1 address [17] "logic address[26:0]" +Toggle 1to0 address [17] "logic address[26:0]" +Toggle 0to1 address [18] "logic address[26:0]" +Toggle 1to0 address [18] "logic address[26:0]" +Toggle 0to1 address [19] "logic address[26:0]" +Toggle 1to0 address [19] "logic address[26:0]" +Toggle 0to1 address [20] "logic address[26:0]" +Toggle 1to0 address [20] "logic address[26:0]" +Toggle 0to1 address [21] "logic address[26:0]" +Toggle 1to0 address [21] "logic address[26:0]" +Toggle 0to1 address [22] "logic address[26:0]" +Toggle 1to0 address [22] "logic address[26:0]" +Toggle 0to1 address [23] "logic address[26:0]" +Toggle 1to0 address [23] "logic address[26:0]" +Toggle 0to1 address [24] "logic address[26:0]" +Toggle 1to0 address [24] "logic address[26:0]" +Toggle 0to1 address [25] "logic address[26:0]" +Toggle 1to0 address [25] "logic address[26:0]" +Toggle 0to1 byteenable [71] "logic byteenable[71:0]" +Toggle 1to0 byteenable [71] "logic byteenable[71:0]" +Toggle 0to1 byteenable [64] "logic byteenable[71:0]" +Toggle 1to0 byteenable [64] "logic byteenable[71:0]" +Toggle 0to1 byteenable [65] "logic byteenable[71:0]" +Toggle 1to0 byteenable [65] "logic byteenable[71:0]" +Toggle 0to1 byteenable [66] "logic byteenable[71:0]" +Toggle 1to0 byteenable [66] "logic byteenable[71:0]" +Toggle 0to1 byteenable [67] "logic byteenable[71:0]" +Toggle 1to0 byteenable [67] "logic byteenable[71:0]" +Toggle 0to1 byteenable [68] "logic byteenable[71:0]" +Toggle 1to0 byteenable [68] "logic byteenable[71:0]" +Toggle 0to1 byteenable [69] "logic byteenable[71:0]" +Toggle 1to0 byteenable [69] "logic byteenable[71:0]" +Toggle 0to1 byteenable [70] "logic byteenable[71:0]" +Toggle 1to0 byteenable [70] "logic byteenable[71:0]" +CHECKSUM: "1259019545 3297052881" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_mx2fn_a_port.r.axis_pl_stage[0].axis_reg_inst +Toggle genblk1.s_tdest_reg "reg genblk1.s_tdest_reg[7:0]" +Toggle genblk1.s_tid_reg "reg genblk1.s_tid_reg[7:0]" +Toggle m_tdest "net m_tdest[7:0]" +Toggle m_tid "net m_tid[7:0]" +Toggle s_tdest "net s_tdest[7:0]" +Toggle s_tid "net s_tid[7:0]" +Toggle 0to1 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle genblk1.m_tid_reg "reg genblk1.m_tid_reg[7:0]" +Toggle genblk1.m_tdest_pre "reg genblk1.m_tdest_pre[7:0]" +Toggle genblk1.m_tdest_reg "reg genblk1.m_tdest_reg[7:0]" +Toggle genblk1.m_tid_pre "reg genblk1.m_tid_pre[7:0]" +Toggle 0to1 s_tuser [9] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [9] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [1] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [1] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [2] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [2] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [3] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [3] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [4] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [4] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [5] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [5] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [6] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [6] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [7] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [7] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [8] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [8] "net s_tuser[9:0]" +Toggle 0to1 m_tuser [9] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [9] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [1] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [1] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [2] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [2] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [3] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [3] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [4] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [4] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [5] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [5] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [6] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [6] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [7] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [7] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [8] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [8] "net m_tuser[9:0]" +CHECKSUM: "1259019545 3297052881" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_fn2mx_a_port.r.axis_pl_stage[0].axis_reg_inst +Toggle m_tdest "net m_tdest[7:0]" +Toggle s_tid "net s_tid[7:0]" +Toggle s_tdest "net s_tdest[7:0]" +Toggle m_tid "net m_tid[7:0]" +Toggle genblk1.s_tdest_reg "reg genblk1.s_tdest_reg[7:0]" +Toggle genblk1.s_tid_reg "reg genblk1.s_tid_reg[7:0]" +Toggle 0to1 m_tuser [9] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [9] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [1] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [1] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [2] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [2] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [3] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [3] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [4] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [4] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [5] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [5] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [6] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [6] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [7] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [7] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [8] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [8] "net m_tuser[9:0]" +Toggle 0to1 s_tkeep [31] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [31] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [0] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [0] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [1] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [1] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [2] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [2] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [3] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [3] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [4] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [4] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [5] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [5] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [6] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [6] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [7] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [7] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [8] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [8] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [9] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [9] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [10] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [10] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [11] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [11] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [12] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [12] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [13] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [13] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [14] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [14] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [15] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [15] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [16] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [16] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [17] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [17] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [18] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [18] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [19] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [19] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [20] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [20] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [21] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [21] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [22] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [22] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [23] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [23] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [24] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [24] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [25] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [25] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [26] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [26] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [27] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [27] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [28] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [28] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [29] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [29] "net s_tkeep[63:0]" +Toggle 0to1 s_tkeep [30] "net s_tkeep[63:0]" +Toggle 1to0 s_tkeep [30] "net s_tkeep[63:0]" +Toggle genblk1.m_tdest_pre "reg genblk1.m_tdest_pre[7:0]" +Toggle genblk1.m_tid_reg "reg genblk1.m_tid_reg[7:0]" +Toggle genblk1.m_tid_pre "reg genblk1.m_tid_pre[7:0]" +Toggle genblk1.m_tdest_reg "reg genblk1.m_tdest_reg[7:0]" +Toggle 0to1 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 s_tuser [9] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [9] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [1] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [1] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [2] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [2] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [3] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [3] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [4] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [4] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [5] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [5] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [6] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [6] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [7] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [7] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [8] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [8] "net s_tuser[9:0]" +CHECKSUM: "1259019545 3297052881" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_fn2mx_b_port.r.axis_pl_stage[0].axis_reg_inst +Toggle 0to1 s_tvalid "net s_tvalid" +Toggle 1to0 s_tvalid "net s_tvalid" +Toggle genblk1.m_tdata_pre "reg genblk1.m_tdata_pre[511:0]" +Toggle genblk1.m_tdata_reg "reg genblk1.m_tdata_reg[511:0]" +Toggle genblk1.m_tdest_pre "reg genblk1.m_tdest_pre[7:0]" +Toggle genblk1.m_tdest_reg "reg genblk1.m_tdest_reg[7:0]" +Toggle genblk1.m_tid_pre "reg genblk1.m_tid_pre[7:0]" +Toggle genblk1.m_tid_reg "reg genblk1.m_tid_reg[7:0]" +Toggle genblk1.m_tkeep_pre "reg genblk1.m_tkeep_pre[63:0]" +Toggle genblk1.m_tkeep_reg "reg genblk1.m_tkeep_reg[63:0]" +Toggle 0to1 genblk1.m_tlast_pre "reg genblk1.m_tlast_pre" +Toggle 1to0 genblk1.m_tlast_pre "reg genblk1.m_tlast_pre" +Toggle 0to1 genblk1.m_tlast_reg "reg genblk1.m_tlast_reg" +Toggle 1to0 genblk1.m_tlast_reg "reg genblk1.m_tlast_reg" +Toggle genblk1.m_tuser_pre "reg genblk1.m_tuser_pre[9:0]" +Toggle genblk1.m_tuser_reg "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tvalid_pre "reg genblk1.m_tvalid_pre" +Toggle 1to0 genblk1.m_tvalid_pre "reg genblk1.m_tvalid_pre" +Toggle 0to1 genblk1.m_tvalid_reg "reg genblk1.m_tvalid_reg" +Toggle 1to0 genblk1.m_tvalid_reg "reg genblk1.m_tvalid_reg" +Toggle genblk1.s_tdata_reg "reg genblk1.s_tdata_reg[511:0]" +Toggle genblk1.s_tdest_reg "reg genblk1.s_tdest_reg[7:0]" +Toggle genblk1.s_tid_reg "reg genblk1.s_tid_reg[7:0]" +Toggle genblk1.s_tkeep_reg "reg genblk1.s_tkeep_reg[63:0]" +Toggle 0to1 genblk1.s_tlast_reg "reg genblk1.s_tlast_reg" +Toggle 1to0 genblk1.s_tlast_reg "reg genblk1.s_tlast_reg" +Toggle 0to1 genblk1.s_tready_pre "logic genblk1.s_tready_pre" +Toggle 1to0 genblk1.s_tready_pre "logic genblk1.s_tready_pre" +Toggle genblk1.s_tuser_reg "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tvalid_reg "reg genblk1.s_tvalid_reg" +Toggle 1to0 genblk1.s_tvalid_reg "reg genblk1.s_tvalid_reg" +Toggle 0to1 genblk1.use_reg "reg genblk1.use_reg" +Toggle 1to0 genblk1.use_reg "reg genblk1.use_reg" +Toggle m_tdata "net m_tdata[511:0]" +Toggle m_tdest "net m_tdest[7:0]" +Toggle m_tid "net m_tid[7:0]" +Toggle m_tkeep "net m_tkeep[63:0]" +Toggle 0to1 m_tlast "net m_tlast" +Toggle 1to0 m_tlast "net m_tlast" +Toggle 0to1 m_tready "net m_tready" +Toggle 1to0 m_tready "net m_tready" +Toggle m_tuser "net m_tuser[9:0]" +Toggle 0to1 m_tvalid "net m_tvalid" +Toggle 1to0 m_tvalid "net m_tvalid" +Toggle s_tdata "net s_tdata[511:0]" +Toggle s_tdest "net s_tdest[7:0]" +Toggle s_tid "net s_tid[7:0]" +Toggle s_tkeep "net s_tkeep[63:0]" +Toggle 0to1 s_tlast "net s_tlast" +Toggle 1to0 s_tlast "net s_tlast" +Toggle s_tuser "net s_tuser[9:0]" +CHECKSUM: "1259019545 3297052881" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_fn2mx_a_port.r.axis_pl_stage[0].axis_reg_inst +Toggle m_tdest "net m_tdest[7:0]" +Toggle s_tuser "net s_tuser[9:0]" +Toggle s_tid "net s_tid[7:0]" +Toggle s_tdest "net s_tdest[7:0]" +Toggle m_tuser "net m_tuser[9:0]" +Toggle m_tid "net m_tid[7:0]" +Toggle genblk1.s_tuser_reg "reg genblk1.s_tuser_reg[9:0]" +Toggle genblk1.m_tuser_pre "reg genblk1.m_tuser_pre[9:0]" +Toggle genblk1.m_tuser_reg "reg genblk1.m_tuser_reg[9:0]" +Toggle genblk1.m_tdest_pre "reg genblk1.m_tdest_pre[7:0]" +Toggle genblk1.m_tid_reg "reg genblk1.m_tid_reg[7:0]" +Toggle genblk1.m_tid_pre "reg genblk1.m_tid_pre[7:0]" +Toggle genblk1.m_tdest_reg "reg genblk1.m_tdest_reg[7:0]" +Toggle genblk1.s_tdest_reg "reg genblk1.s_tdest_reg[7:0]" +Toggle genblk1.s_tid_reg "reg genblk1.s_tid_reg[7:0]" +Toggle 0to1 s_tdata [511] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [511] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [0] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [0] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [2] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [2] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [3] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [3] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [4] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [4] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [5] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [5] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [6] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [6] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [7] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [7] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [8] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [8] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [9] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [9] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [10] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [10] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [11] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [11] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [12] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [12] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [13] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [13] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [14] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [14] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [15] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [15] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [16] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [16] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [17] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [17] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [18] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [18] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [19] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [19] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [20] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [20] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [21] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [21] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [22] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [22] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [23] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [23] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [24] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [24] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [26] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [26] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [28] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [28] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [29] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [29] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [31] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [31] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [32] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [32] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [33] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [33] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [34] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [34] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [35] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [35] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [52] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [52] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [54] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [54] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [55] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [55] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [56] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [56] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [57] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [57] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [58] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [58] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [59] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [59] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [60] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [60] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [61] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [61] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [62] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [62] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [63] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [63] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [64] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [64] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [65] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [65] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [66] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [66] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [71] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [71] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [77] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [77] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [78] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [78] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [79] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [79] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [81] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [81] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [82] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [82] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [83] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [83] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [84] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [84] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [85] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [85] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [86] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [86] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [87] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [87] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [88] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [88] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [89] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [89] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [90] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [90] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [91] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [91] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [92] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [92] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [93] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [93] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [94] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [94] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [95] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [95] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [96] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [96] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [97] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [97] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [98] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [98] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [99] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [99] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [100] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [100] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [101] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [101] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [102] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [102] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [103] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [103] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [104] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [104] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [105] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [105] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [106] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [106] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [107] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [107] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [108] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [108] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [109] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [109] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [110] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [110] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [111] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [111] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [112] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [112] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [113] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [113] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [114] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [114] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [115] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [115] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [116] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [116] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [117] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [117] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [118] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [118] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [119] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [119] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [120] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [120] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [121] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [121] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [122] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [122] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [123] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [123] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [124] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [124] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [125] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [125] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [126] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [126] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [127] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [127] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [128] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [128] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [129] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [129] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [130] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [130] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [131] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [131] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [132] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [132] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [133] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [133] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [134] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [134] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [135] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [135] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [136] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [136] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [137] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [137] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [138] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [138] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [139] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [139] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [140] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [140] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [141] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [141] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [142] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [142] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [143] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [143] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [144] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [144] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [145] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [145] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [146] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [146] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [147] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [147] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [148] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [148] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [149] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [149] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [150] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [150] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [151] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [151] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [152] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [152] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [153] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [153] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [154] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [154] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [155] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [155] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [156] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [156] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [157] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [157] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [158] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [158] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [159] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [159] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [160] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [160] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [161] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [161] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [162] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [162] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [163] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [163] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [165] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [165] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [166] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [166] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [167] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [167] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [168] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [168] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [169] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [169] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [170] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [170] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [171] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [171] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [172] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [172] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [173] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [173] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [175] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [175] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [176] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [176] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [177] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [177] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [178] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [178] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [179] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [179] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [180] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [180] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [181] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [181] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [182] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [182] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [183] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [183] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [184] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [184] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [185] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [185] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [186] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [186] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [187] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [187] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [188] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [188] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [189] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [189] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [190] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [190] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [191] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [191] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [192] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [192] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [193] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [193] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [194] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [194] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [195] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [195] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [196] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [196] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [197] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [197] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [198] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [198] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [199] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [199] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [200] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [200] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [201] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [201] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [202] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [202] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [203] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [203] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [204] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [204] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [205] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [205] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [206] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [206] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [207] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [207] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [208] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [208] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [209] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [209] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [210] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [210] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [211] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [211] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [212] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [212] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [213] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [213] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [214] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [214] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [215] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [215] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [216] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [216] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [217] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [217] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [218] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [218] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [219] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [219] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [220] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [220] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [221] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [221] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [222] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [222] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [223] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [223] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [224] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [224] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [225] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [225] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [226] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [226] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [227] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [227] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [228] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [228] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [229] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [229] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [230] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [230] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [231] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [231] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [232] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [232] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [233] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [233] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [234] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [234] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [235] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [235] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [236] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [236] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [237] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [237] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [238] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [238] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [239] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [239] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [240] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [240] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [241] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [241] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [242] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [242] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [243] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [243] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [244] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [244] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [245] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [245] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [246] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [246] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [247] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [247] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [248] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [248] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [249] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [249] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [250] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [250] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [251] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [251] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [252] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [252] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [253] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [253] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [254] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [254] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [255] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [255] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [320] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [320] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [321] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [321] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [322] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [322] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [323] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [323] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [324] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [324] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [325] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [325] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [326] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [326] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [327] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [327] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [328] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [328] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [329] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [329] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [330] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [330] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [331] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [331] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [332] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [332] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [333] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [333] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [334] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [334] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [335] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [335] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [336] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [336] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [337] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [337] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [338] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [338] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [339] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [339] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [340] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [340] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [341] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [341] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [342] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [342] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [343] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [343] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [344] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [344] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [345] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [345] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [346] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [346] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [347] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [347] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [348] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [348] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [349] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [349] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [350] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [350] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [351] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [351] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [352] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [352] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [353] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [353] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [354] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [354] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [355] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [355] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [356] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [356] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [357] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [357] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [358] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [358] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [359] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [359] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [360] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [360] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [361] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [361] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [362] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [362] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [363] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [363] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [364] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [364] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [365] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [365] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [366] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [366] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [367] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [367] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [368] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [368] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [369] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [369] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [370] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [370] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [371] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [371] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [372] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [372] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [373] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [373] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [374] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [374] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [375] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [375] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [376] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [376] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [377] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [377] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [378] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [378] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [379] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [379] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [380] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [380] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [381] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [381] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [382] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [382] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [383] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [383] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [384] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [384] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [385] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [385] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [386] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [386] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [387] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [387] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [388] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [388] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [389] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [389] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [390] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [390] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [391] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [391] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [392] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [392] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [393] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [393] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [394] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [394] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [395] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [395] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [396] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [396] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [397] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [397] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [398] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [398] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [399] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [399] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [400] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [400] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [401] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [401] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [402] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [402] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [403] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [403] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [404] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [404] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [405] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [405] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [406] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [406] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [407] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [407] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [408] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [408] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [409] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [409] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [410] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [410] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [411] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [411] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [412] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [412] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [413] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [413] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [414] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [414] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [415] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [415] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [416] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [416] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [417] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [417] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [418] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [418] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [419] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [419] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [420] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [420] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [421] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [421] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [422] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [422] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [423] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [423] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [424] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [424] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [425] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [425] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [426] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [426] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [427] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [427] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [428] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [428] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [429] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [429] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [430] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [430] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [431] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [431] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [432] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [432] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [433] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [433] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [434] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [434] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [435] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [435] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [436] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [436] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [437] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [437] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [438] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [438] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [439] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [439] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [440] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [440] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [441] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [441] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [442] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [442] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [443] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [443] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [444] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [444] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [445] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [445] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [446] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [446] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [447] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [447] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [448] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [448] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [449] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [449] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [450] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [450] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [451] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [451] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [452] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [452] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [453] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [453] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [454] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [454] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [455] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [455] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [456] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [456] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [457] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [457] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [458] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [458] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [459] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [459] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [460] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [460] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [461] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [461] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [462] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [462] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [463] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [463] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [464] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [464] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [465] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [465] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [466] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [466] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [467] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [467] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [468] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [468] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [469] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [469] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [470] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [470] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [471] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [471] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [472] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [472] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [473] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [473] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [474] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [474] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [475] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [475] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [476] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [476] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [477] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [477] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [478] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [478] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [479] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [479] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [480] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [480] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [481] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [481] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [482] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [482] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [483] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [483] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [484] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [484] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [485] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [485] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [486] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [486] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [487] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [487] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [488] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [488] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [489] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [489] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [490] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [490] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [491] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [491] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [492] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [492] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [493] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [493] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [494] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [494] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [495] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [495] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [496] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [496] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [497] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [497] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [498] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [498] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [499] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [499] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [500] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [500] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [501] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [501] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [502] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [502] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [503] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [503] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [504] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [504] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [505] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [505] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [506] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [506] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [507] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [507] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [508] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [508] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [509] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [509] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [510] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [510] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [174] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [164] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [80] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [53] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [1] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [25] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [27] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [36] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [37] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [38] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [39] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [40] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [41] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [42] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [43] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [44] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [45] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [46] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [47] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [48] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [49] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [50] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [51] "net s_tdata[511:0]" +Toggle 1to0 s_tdata [30] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [50] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [36] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [37] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [38] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [39] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [40] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [41] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [42] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [43] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [44] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [45] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [46] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [47] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [48] "net s_tdata[511:0]" +Toggle 0to1 s_tdata [49] "net s_tdata[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [511] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [511] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [320] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [320] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [321] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [321] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [322] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [322] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [323] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [323] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [324] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [324] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [325] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [325] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [326] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [326] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [327] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [327] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [328] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [328] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [329] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [329] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [330] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [330] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [331] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [331] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [332] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [332] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [333] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [333] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [334] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [334] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [335] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [335] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [336] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [336] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [337] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [337] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [338] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [338] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [339] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [339] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [340] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [340] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [341] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [341] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [342] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [342] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [343] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [343] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [344] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [344] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [345] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [345] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [346] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [346] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [347] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [347] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [348] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [348] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [349] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [349] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [350] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [350] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [351] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [351] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [352] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [352] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [353] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [353] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [354] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [354] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [355] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [355] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [356] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [356] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [357] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [357] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [358] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [358] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [359] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [359] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [360] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [360] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [361] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [361] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [362] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [362] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [363] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [363] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [364] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [364] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [365] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [365] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [366] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [366] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [367] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [367] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [368] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [368] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [369] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [369] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [370] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [370] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [371] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [371] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [372] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [372] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [373] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [373] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [374] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [374] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [375] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [375] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [376] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [376] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [377] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [377] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [378] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [378] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [379] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [379] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [380] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [380] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [381] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [381] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [382] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [382] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [383] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [383] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [384] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [384] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [385] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [385] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [386] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [386] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [387] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [387] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [388] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [388] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [389] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [389] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [390] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [390] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [391] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [391] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [392] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [392] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [393] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [393] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [394] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [394] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [395] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [395] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [396] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [396] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [397] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [397] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [398] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [398] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [399] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [399] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [400] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [400] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [401] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [401] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [402] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [402] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [403] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [403] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [404] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [404] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [405] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [405] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [406] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [406] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [407] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [407] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [408] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [408] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [409] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [409] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [410] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [410] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [411] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [411] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [412] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [412] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [413] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [413] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [414] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [414] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [415] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [415] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [416] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [416] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [417] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [417] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [418] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [418] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [419] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [419] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [420] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [420] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [421] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [421] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [422] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [422] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [423] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [423] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [424] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [424] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [425] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [425] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [426] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [426] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [427] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [427] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [428] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [428] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [429] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [429] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [430] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [430] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [431] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [431] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [432] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [432] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [433] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [433] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [434] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [434] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [435] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [435] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [436] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [436] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [437] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [437] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [438] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [438] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [439] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [439] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [440] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [440] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [441] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [441] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [442] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [442] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [443] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [443] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [444] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [444] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [445] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [445] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [446] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [446] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [447] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [447] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [448] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [448] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [449] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [449] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [450] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [450] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [451] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [451] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [452] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [452] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [453] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [453] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [454] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [454] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [455] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [455] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [456] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [456] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [457] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [457] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [458] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [458] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [459] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [459] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [460] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [460] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [461] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [461] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [462] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [462] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [463] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [463] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [464] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [464] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [465] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [465] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [466] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [466] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [467] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [467] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [468] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [468] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [469] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [469] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [470] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [470] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [471] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [471] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [472] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [472] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [473] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [473] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [474] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [474] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [475] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [475] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [476] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [476] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [477] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [477] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [478] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [478] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [479] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [479] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [480] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [480] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [481] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [481] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [482] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [482] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [483] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [483] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [484] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [484] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [485] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [485] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [486] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [486] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [487] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [487] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [488] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [488] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [489] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [489] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [490] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [490] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [491] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [491] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [492] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [492] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [493] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [493] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [494] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [494] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [495] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [495] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [496] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [496] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [497] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [497] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [498] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [498] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [499] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [499] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [500] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [500] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [501] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [501] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [502] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [502] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [503] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [503] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [504] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [504] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [505] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [505] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [506] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [506] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [507] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [507] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [508] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [508] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [509] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [509] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [510] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [510] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [255] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [255] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [0] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [0] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [2] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [2] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [3] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [3] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [4] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [4] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [5] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [5] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [6] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [6] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [7] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [7] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [8] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [8] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [9] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [9] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [10] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [10] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [11] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [11] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [12] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [12] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [13] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [13] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [14] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [14] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [15] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [15] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [16] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [16] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [17] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [17] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [18] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [18] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [19] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [19] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [20] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [20] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [21] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [21] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [22] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [22] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [23] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [23] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [24] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [24] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [26] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [26] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [28] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [28] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [29] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [29] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [31] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [31] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [32] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [32] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [33] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [33] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [34] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [34] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [36] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [36] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [37] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [37] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [38] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [38] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [39] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [39] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [40] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [40] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [41] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [41] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [42] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [42] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [43] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [43] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [44] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [44] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [45] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [45] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [46] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [46] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [47] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [47] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [48] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [48] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [49] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [49] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [50] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [50] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [52] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [52] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [54] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [54] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [55] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [55] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [56] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [56] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [57] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [57] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [58] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [58] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [59] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [59] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [60] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [60] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [61] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [61] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [62] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [62] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [63] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [63] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [64] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [64] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [65] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [65] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [66] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [66] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [71] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [71] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [77] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [77] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [78] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [78] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [79] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [79] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [81] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [81] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [82] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [82] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [83] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [83] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [84] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [84] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [85] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [85] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [86] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [86] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [87] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [87] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [88] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [88] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [89] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [89] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [90] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [90] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [91] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [91] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [92] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [92] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [93] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [93] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [94] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [94] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [95] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [95] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [96] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [96] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [97] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [97] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [98] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [98] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [99] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [99] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [100] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [100] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [101] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [101] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [102] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [102] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [103] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [103] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [104] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [104] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [105] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [105] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [106] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [106] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [107] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [107] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [108] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [108] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [109] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [109] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [110] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [110] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [111] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [111] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [112] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [112] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [113] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [113] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [114] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [114] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [115] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [115] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [116] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [116] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [117] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [117] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [118] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [118] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [119] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [119] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [120] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [120] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [121] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [121] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [122] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [122] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [123] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [123] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [124] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [124] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [125] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [125] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [126] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [126] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [127] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [127] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [128] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [128] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [129] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [129] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [130] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [130] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [131] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [131] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [132] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [132] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [133] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [133] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [134] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [134] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [135] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [135] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [136] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [136] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [137] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [137] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [138] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [138] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [139] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [139] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [140] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [140] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [141] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [141] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [142] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [142] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [143] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [143] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [144] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [144] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [145] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [145] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [146] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [146] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [147] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [147] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [148] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [148] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [149] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [149] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [150] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [150] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [151] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [151] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [152] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [152] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [153] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [153] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [154] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [154] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [155] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [155] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [156] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [156] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [157] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [157] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [158] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [158] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [159] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [159] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [160] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [160] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [161] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [161] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [162] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [162] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [163] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [163] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [165] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [165] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [166] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [166] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [167] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [167] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [168] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [168] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [169] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [169] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [170] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [170] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [171] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [171] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [172] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [172] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [173] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [173] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [175] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [175] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [176] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [176] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [177] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [177] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [178] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [178] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [179] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [179] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [180] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [180] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [181] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [181] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [182] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [182] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [183] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [183] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [184] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [184] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [185] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [185] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [186] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [186] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [187] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [187] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [188] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [188] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [189] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [189] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [190] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [190] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [191] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [191] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [192] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [192] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [193] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [193] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [194] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [194] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [195] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [195] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [196] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [196] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [197] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [197] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [198] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [198] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [199] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [199] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [200] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [200] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [201] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [201] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [202] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [202] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [203] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [203] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [204] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [204] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [205] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [205] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [206] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [206] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [207] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [207] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [208] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [208] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [209] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [209] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [210] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [210] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [211] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [211] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [212] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [212] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [213] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [213] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [214] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [214] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [215] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [215] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [216] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [216] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [217] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [217] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [218] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [218] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [219] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [219] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [220] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [220] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [221] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [221] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [222] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [222] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [223] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [223] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [224] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [224] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [225] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [225] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [226] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [226] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [227] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [227] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [228] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [228] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [229] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [229] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [230] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [230] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [231] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [231] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [232] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [232] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [233] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [233] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [234] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [234] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [235] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [235] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [236] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [236] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [237] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [237] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [238] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [238] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [239] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [239] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [240] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [240] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [241] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [241] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [242] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [242] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [243] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [243] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [244] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [244] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [245] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [245] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [246] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [246] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [247] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [247] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [248] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [248] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [249] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [249] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [250] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [250] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [251] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [251] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [252] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [252] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [253] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [253] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.m_tdata_pre [254] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [254] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [70] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [67] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [68] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [69] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [174] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [1] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [25] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [27] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [30] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [35] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [51] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [53] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [80] "reg genblk1.m_tdata_pre[511:0]" +Toggle 1to0 genblk1.m_tdata_pre [164] "reg genblk1.m_tdata_pre[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [511] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [511] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [320] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [320] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [321] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [321] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [322] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [322] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [323] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [323] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [324] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [324] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [325] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [325] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [326] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [326] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [327] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [327] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [328] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [328] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [329] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [329] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [330] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [330] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [331] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [331] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [332] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [332] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [333] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [333] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [334] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [334] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [335] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [335] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [336] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [336] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [337] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [337] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [338] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [338] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [339] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [339] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [340] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [340] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [341] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [341] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [342] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [342] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [343] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [343] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [344] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [344] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [345] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [345] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [346] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [346] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [347] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [347] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [348] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [348] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [349] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [349] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [350] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [350] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [351] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [351] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [352] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [352] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [353] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [353] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [354] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [354] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [355] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [355] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [356] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [356] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [357] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [357] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [358] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [358] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [359] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [359] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [360] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [360] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [361] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [361] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [362] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [362] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [363] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [363] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [364] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [364] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [365] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [365] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [366] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [366] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [367] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [367] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [368] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [368] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [369] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [369] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [370] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [370] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [371] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [371] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [372] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [372] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [373] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [373] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [374] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [374] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [375] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [375] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [376] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [376] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [377] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [377] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [378] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [378] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [379] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [379] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [380] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [380] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [381] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [381] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [382] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [382] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [383] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [383] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [384] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [384] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [385] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [385] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [386] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [386] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [387] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [387] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [388] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [388] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [389] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [389] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [390] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [390] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [391] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [391] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [392] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [392] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [393] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [393] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [394] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [394] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [395] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [395] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [396] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [396] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [397] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [397] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [398] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [398] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [399] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [399] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [400] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [400] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [401] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [401] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [402] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [402] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [403] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [403] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [404] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [404] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [405] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [405] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [406] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [406] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [407] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [407] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [408] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [408] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [409] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [409] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [410] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [410] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [411] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [411] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [412] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [412] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [413] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [413] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [414] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [414] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [415] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [415] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [416] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [416] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [417] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [417] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [418] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [418] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [419] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [419] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [420] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [420] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [421] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [421] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [422] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [422] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [423] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [423] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [424] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [424] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [425] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [425] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [426] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [426] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [427] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [427] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [428] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [428] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [429] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [429] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [430] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [430] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [431] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [431] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [432] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [432] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [433] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [433] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [434] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [434] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [435] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [435] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [436] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [436] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [437] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [437] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [438] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [438] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [439] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [439] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [440] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [440] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [441] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [441] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [442] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [442] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [443] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [443] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [444] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [444] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [445] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [445] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [446] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [446] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [447] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [447] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [448] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [448] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [449] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [449] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [450] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [450] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [451] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [451] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [452] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [452] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [453] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [453] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [454] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [454] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [455] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [455] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [456] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [456] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [457] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [457] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [458] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [458] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [459] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [459] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [460] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [460] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [461] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [461] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [462] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [462] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [463] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [463] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [464] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [464] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [465] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [465] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [466] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [466] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [467] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [467] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [468] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [468] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [469] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [469] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [470] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [470] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [471] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [471] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [472] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [472] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [473] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [473] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [474] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [474] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [475] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [475] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [476] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [476] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [477] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [477] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [478] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [478] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [479] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [479] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [480] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [480] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [481] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [481] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [482] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [482] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [483] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [483] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [484] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [484] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [485] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [485] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [486] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [486] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [487] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [487] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [488] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [488] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [489] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [489] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [490] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [490] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [491] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [491] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [492] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [492] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [493] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [493] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [494] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [494] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [495] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [495] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [496] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [496] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [497] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [497] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [498] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [498] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [499] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [499] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [500] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [500] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [501] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [501] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [502] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [502] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [503] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [503] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [504] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [504] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [505] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [505] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [506] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [506] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [507] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [507] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [508] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [508] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [509] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [509] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [510] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [510] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [255] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [255] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [0] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [0] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [2] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [2] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [3] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [3] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [4] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [4] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [5] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [5] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [6] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [6] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [7] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [7] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [8] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [8] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [9] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [9] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [10] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [10] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [11] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [11] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [12] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [12] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [13] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [13] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [14] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [14] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [15] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [15] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [16] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [16] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [17] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [17] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [18] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [18] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [19] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [19] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [20] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [20] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [21] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [21] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [22] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [22] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [23] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [23] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [24] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [24] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [26] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [26] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [28] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [28] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [29] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [29] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [31] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [31] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [32] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [32] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [33] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [33] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [34] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [34] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [36] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [36] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [37] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [37] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [38] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [38] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [39] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [39] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [40] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [40] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [41] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [41] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [42] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [42] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [43] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [43] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [44] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [44] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [45] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [45] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [46] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [46] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [47] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [47] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [48] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [48] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [49] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [49] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [50] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [50] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [52] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [52] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [54] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [54] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [55] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [55] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [56] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [56] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [57] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [57] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [58] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [58] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [59] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [59] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [60] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [60] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [61] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [61] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [62] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [62] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [63] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [63] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [64] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [64] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [65] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [65] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [66] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [66] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [71] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [71] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [77] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [77] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [78] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [78] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [79] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [79] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [81] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [81] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [82] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [82] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [83] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [83] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [84] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [84] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [85] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [85] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [86] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [86] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [87] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [87] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [88] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [88] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [89] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [89] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [90] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [90] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [91] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [91] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [92] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [92] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [93] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [93] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [94] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [94] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [95] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [95] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [96] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [96] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [97] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [97] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [98] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [98] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [99] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [99] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [100] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [100] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [101] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [101] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [102] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [102] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [103] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [103] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [104] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [104] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [105] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [105] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [106] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [106] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [107] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [107] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [108] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [108] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [109] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [109] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [110] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [110] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [111] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [111] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [112] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [112] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [113] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [113] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [114] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [114] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [115] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [115] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [116] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [116] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [117] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [117] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [118] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [118] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [119] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [119] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [120] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [120] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [121] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [121] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [122] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [122] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [123] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [123] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [124] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [124] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [125] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [125] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [126] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [126] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [127] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [127] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [128] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [128] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [129] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [129] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [130] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [130] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [131] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [131] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [132] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [132] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [133] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [133] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [134] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [134] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [135] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [135] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [136] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [136] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [137] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [137] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [138] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [138] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [139] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [139] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [140] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [140] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [141] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [141] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [142] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [142] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [143] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [143] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [144] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [144] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [145] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [145] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [146] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [146] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [147] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [147] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [148] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [148] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [149] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [149] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [150] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [150] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [151] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [151] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [152] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [152] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [153] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [153] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [154] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [154] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [155] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [155] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [156] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [156] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [157] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [157] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [158] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [158] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [159] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [159] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [160] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [160] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [161] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [161] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [162] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [162] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [163] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [163] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [165] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [165] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [166] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [166] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [167] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [167] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [168] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [168] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [169] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [169] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [170] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [170] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [171] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [171] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [172] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [172] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [173] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [173] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [175] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [175] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [176] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [176] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [177] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [177] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [178] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [178] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [179] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [179] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [180] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [180] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [181] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [181] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [182] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [182] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [183] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [183] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [184] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [184] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [185] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [185] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [186] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [186] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [187] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [187] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [188] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [188] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [189] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [189] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [190] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [190] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [191] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [191] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [192] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [192] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [193] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [193] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [194] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [194] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [195] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [195] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [196] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [196] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [197] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [197] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [198] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [198] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [199] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [199] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [200] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [200] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [201] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [201] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [202] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [202] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [203] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [203] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [204] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [204] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [205] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [205] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [206] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [206] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [207] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [207] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [208] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [208] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [209] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [209] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [210] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [210] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [211] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [211] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [212] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [212] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [213] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [213] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [214] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [214] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [215] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [215] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [216] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [216] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [217] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [217] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [218] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [218] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [219] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [219] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [220] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [220] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [221] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [221] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [222] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [222] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [223] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [223] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [224] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [224] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [225] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [225] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [226] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [226] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [227] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [227] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [228] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [228] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [229] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [229] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [230] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [230] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [231] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [231] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [232] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [232] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [233] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [233] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [234] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [234] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [235] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [235] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [236] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [236] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [237] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [237] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [238] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [238] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [239] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [239] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [240] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [240] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [241] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [241] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [242] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [242] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [243] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [243] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [244] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [244] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [245] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [245] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [246] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [246] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [247] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [247] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [248] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [248] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [249] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [249] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [250] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [250] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [251] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [251] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [252] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [252] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [253] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [253] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 genblk1.s_tdata_reg [254] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [254] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [174] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [1] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [25] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [27] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [30] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [35] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [51] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [53] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [164] "reg genblk1.s_tdata_reg[511:0]" +Toggle 1to0 genblk1.s_tdata_reg [80] "reg genblk1.s_tdata_reg[511:0]" +Toggle 0to1 m_tdata [511] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [511] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [320] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [320] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [321] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [321] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [322] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [322] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [323] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [323] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [324] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [324] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [325] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [325] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [326] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [326] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [327] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [327] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [328] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [328] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [329] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [329] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [330] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [330] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [331] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [331] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [332] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [332] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [333] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [333] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [334] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [334] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [335] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [335] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [336] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [336] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [337] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [337] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [338] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [338] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [339] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [339] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [340] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [340] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [341] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [341] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [342] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [342] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [343] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [343] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [344] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [344] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [345] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [345] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [346] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [346] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [347] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [347] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [348] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [348] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [349] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [349] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [350] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [350] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [351] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [351] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [352] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [352] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [353] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [353] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [354] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [354] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [355] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [355] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [356] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [356] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [357] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [357] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [358] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [358] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [359] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [359] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [360] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [360] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [361] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [361] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [362] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [362] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [363] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [363] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [364] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [364] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [365] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [365] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [366] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [366] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [367] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [367] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [368] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [368] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [369] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [369] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [370] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [370] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [371] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [371] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [372] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [372] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [373] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [373] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [374] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [374] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [375] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [375] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [376] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [376] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [377] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [377] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [378] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [378] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [379] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [379] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [380] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [380] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [381] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [381] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [382] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [382] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [383] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [383] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [384] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [384] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [385] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [385] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [386] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [386] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [387] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [387] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [388] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [388] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [389] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [389] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [390] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [390] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [391] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [391] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [392] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [392] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [393] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [393] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [394] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [394] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [395] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [395] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [396] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [396] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [397] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [397] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [398] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [398] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [399] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [399] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [400] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [400] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [401] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [401] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [402] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [402] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [403] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [403] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [404] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [404] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [405] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [405] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [406] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [406] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [407] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [407] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [408] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [408] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [409] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [409] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [410] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [410] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [411] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [411] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [412] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [412] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [413] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [413] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [414] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [414] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [415] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [415] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [416] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [416] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [417] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [417] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [418] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [418] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [419] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [419] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [420] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [420] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [421] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [421] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [422] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [422] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [423] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [423] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [424] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [424] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [425] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [425] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [426] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [426] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [427] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [427] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [428] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [428] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [429] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [429] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [430] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [430] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [431] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [431] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [432] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [432] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [433] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [433] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [434] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [434] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [435] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [435] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [436] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [436] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [437] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [437] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [438] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [438] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [439] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [439] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [440] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [440] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [441] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [441] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [442] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [442] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [443] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [443] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [444] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [444] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [445] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [445] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [446] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [446] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [447] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [447] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [448] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [448] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [449] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [449] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [450] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [450] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [451] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [451] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [452] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [452] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [453] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [453] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [454] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [454] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [455] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [455] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [456] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [456] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [457] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [457] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [458] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [458] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [459] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [459] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [460] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [460] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [461] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [461] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [462] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [462] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [463] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [463] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [464] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [464] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [465] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [465] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [466] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [466] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [467] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [467] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [468] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [468] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [469] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [469] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [470] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [470] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [471] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [471] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [472] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [472] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [473] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [473] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [474] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [474] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [475] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [475] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [476] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [476] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [477] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [477] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [478] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [478] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [479] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [479] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [480] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [480] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [481] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [481] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [482] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [482] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [483] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [483] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [484] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [484] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [485] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [485] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [486] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [486] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [487] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [487] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [488] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [488] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [489] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [489] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [490] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [490] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [491] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [491] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [492] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [492] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [493] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [493] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [494] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [494] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [495] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [495] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [496] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [496] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [497] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [497] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [498] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [498] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [499] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [499] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [500] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [500] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [501] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [501] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [502] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [502] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [503] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [503] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [504] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [504] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [505] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [505] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [506] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [506] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [507] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [507] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [508] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [508] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [509] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [509] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [510] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [510] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [255] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [255] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [0] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [0] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [2] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [2] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [3] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [3] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [4] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [4] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [5] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [5] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [6] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [6] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [7] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [7] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [8] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [8] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [9] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [9] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [10] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [10] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [11] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [11] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [12] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [12] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [13] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [13] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [14] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [14] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [15] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [15] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [16] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [16] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [17] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [17] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [18] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [18] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [19] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [19] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [20] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [20] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [21] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [21] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [22] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [22] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [23] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [23] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [24] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [24] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [26] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [26] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [28] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [28] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [29] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [29] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [31] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [31] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [32] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [32] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [33] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [33] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [34] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [34] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [36] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [36] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [37] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [37] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [38] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [38] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [39] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [39] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [40] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [40] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [41] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [41] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [42] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [42] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [43] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [43] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [44] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [44] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [45] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [45] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [46] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [46] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [47] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [47] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [48] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [48] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [49] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [49] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [50] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [50] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [52] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [52] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [54] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [54] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [55] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [55] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [56] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [56] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [57] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [57] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [58] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [58] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [59] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [59] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [60] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [60] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [61] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [61] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [62] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [62] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [63] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [63] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [64] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [64] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [65] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [65] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [66] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [66] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [71] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [71] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [77] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [77] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [78] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [78] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [79] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [79] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [81] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [81] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [82] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [82] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [83] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [83] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [84] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [84] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [85] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [85] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [86] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [86] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [87] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [87] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [88] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [88] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [89] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [89] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [90] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [90] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [91] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [91] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [92] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [92] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [93] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [93] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [94] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [94] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [95] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [95] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [96] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [96] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [97] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [97] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [98] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [98] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [99] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [99] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [100] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [100] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [101] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [101] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [102] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [102] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [103] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [103] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [104] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [104] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [105] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [105] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [106] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [106] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [107] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [107] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [108] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [108] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [109] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [109] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [110] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [110] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [111] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [111] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [112] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [112] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [113] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [113] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [114] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [114] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [115] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [115] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [116] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [116] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [117] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [117] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [118] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [118] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [119] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [119] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [120] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [120] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [121] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [121] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [122] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [122] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [123] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [123] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [124] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [124] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [125] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [125] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [126] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [126] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [127] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [127] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [128] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [128] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [129] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [129] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [130] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [130] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [131] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [131] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [132] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [132] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [133] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [133] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [134] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [134] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [135] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [135] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [136] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [136] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [137] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [137] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [138] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [138] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [139] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [139] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [140] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [140] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [141] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [141] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [142] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [142] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [143] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [143] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [144] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [144] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [145] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [145] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [146] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [146] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [147] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [147] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [148] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [148] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [149] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [149] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [150] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [150] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [151] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [151] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [152] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [152] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [153] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [153] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [154] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [154] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [155] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [155] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [156] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [156] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [157] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [157] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [158] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [158] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [159] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [159] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [160] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [160] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [161] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [161] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [162] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [162] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [163] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [163] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [165] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [165] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [166] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [166] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [167] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [167] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [168] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [168] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [169] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [169] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [170] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [170] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [171] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [171] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [172] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [172] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [173] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [173] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [175] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [175] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [176] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [176] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [177] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [177] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [178] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [178] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [179] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [179] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [180] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [180] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [181] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [181] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [182] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [182] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [183] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [183] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [184] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [184] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [185] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [185] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [186] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [186] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [187] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [187] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [188] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [188] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [189] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [189] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [190] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [190] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [191] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [191] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [192] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [192] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [193] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [193] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [194] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [194] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [195] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [195] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [196] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [196] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [197] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [197] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [198] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [198] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [199] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [199] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [200] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [200] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [201] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [201] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [202] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [202] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [203] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [203] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [204] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [204] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [205] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [205] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [206] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [206] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [207] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [207] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [208] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [208] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [209] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [209] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [210] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [210] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [211] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [211] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [212] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [212] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [213] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [213] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [214] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [214] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [215] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [215] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [216] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [216] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [217] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [217] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [218] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [218] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [219] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [219] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [220] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [220] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [221] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [221] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [222] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [222] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [223] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [223] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [224] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [224] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [225] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [225] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [226] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [226] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [227] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [227] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [228] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [228] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [229] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [229] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [230] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [230] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [231] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [231] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [232] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [232] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [233] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [233] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [234] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [234] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [235] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [235] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [236] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [236] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [237] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [237] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [238] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [238] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [239] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [239] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [240] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [240] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [241] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [241] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [242] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [242] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [243] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [243] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [244] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [244] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [245] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [245] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [246] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [246] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [247] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [247] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [248] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [248] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [249] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [249] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [250] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [250] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [251] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [251] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [252] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [252] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [253] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [253] "net m_tdata[511:0]" +Toggle 0to1 m_tdata [254] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [254] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [174] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [1] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [25] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [27] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [30] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [35] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [51] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [53] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [80] "net m_tdata[511:0]" +Toggle 1to0 m_tdata [164] "net m_tdata[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [511] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [511] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [320] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [320] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [321] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [321] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [322] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [322] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [323] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [323] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [324] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [324] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [325] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [325] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [326] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [326] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [327] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [327] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [328] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [328] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [329] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [329] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [330] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [330] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [331] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [331] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [332] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [332] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [333] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [333] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [334] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [334] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [335] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [335] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [336] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [336] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [337] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [337] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [338] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [338] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [339] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [339] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [340] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [340] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [341] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [341] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [342] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [342] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [343] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [343] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [344] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [344] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [345] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [345] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [346] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [346] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [347] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [347] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [348] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [348] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [349] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [349] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [350] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [350] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [351] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [351] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [352] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [352] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [353] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [353] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [354] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [354] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [355] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [355] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [356] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [356] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [357] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [357] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [358] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [358] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [359] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [359] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [360] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [360] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [361] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [361] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [362] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [362] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [363] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [363] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [364] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [364] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [365] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [365] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [366] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [366] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [367] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [367] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [368] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [368] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [369] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [369] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [370] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [370] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [371] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [371] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [372] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [372] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [373] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [373] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [374] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [374] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [375] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [375] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [376] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [376] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [377] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [377] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [378] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [378] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [379] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [379] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [380] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [380] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [381] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [381] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [382] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [382] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [383] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [383] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [384] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [384] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [385] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [385] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [386] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [386] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [387] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [387] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [388] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [388] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [389] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [389] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [390] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [390] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [391] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [391] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [392] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [392] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [393] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [393] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [394] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [394] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [395] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [395] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [396] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [396] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [397] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [397] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [398] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [398] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [399] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [399] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [400] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [400] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [401] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [401] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [402] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [402] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [403] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [403] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [404] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [404] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [405] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [405] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [406] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [406] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [407] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [407] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [408] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [408] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [409] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [409] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [410] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [410] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [411] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [411] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [412] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [412] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [413] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [413] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [414] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [414] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [415] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [415] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [416] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [416] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [417] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [417] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [418] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [418] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [419] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [419] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [420] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [420] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [421] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [421] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [422] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [422] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [423] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [423] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [424] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [424] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [425] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [425] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [426] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [426] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [427] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [427] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [428] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [428] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [429] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [429] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [430] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [430] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [431] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [431] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [432] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [432] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [433] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [433] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [434] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [434] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [435] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [435] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [436] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [436] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [437] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [437] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [438] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [438] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [439] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [439] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [440] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [440] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [441] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [441] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [442] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [442] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [443] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [443] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [444] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [444] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [445] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [445] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [446] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [446] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [447] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [447] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [448] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [448] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [449] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [449] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [450] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [450] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [451] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [451] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [452] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [452] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [453] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [453] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [454] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [454] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [455] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [455] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [456] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [456] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [457] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [457] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [458] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [458] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [459] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [459] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [460] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [460] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [461] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [461] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [462] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [462] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [463] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [463] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [464] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [464] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [465] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [465] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [466] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [466] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [467] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [467] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [468] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [468] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [469] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [469] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [470] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [470] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [471] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [471] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [472] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [472] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [473] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [473] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [474] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [474] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [475] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [475] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [476] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [476] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [477] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [477] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [478] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [478] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [479] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [479] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [480] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [480] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [481] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [481] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [482] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [482] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [483] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [483] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [484] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [484] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [485] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [485] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [486] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [486] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [487] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [487] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [488] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [488] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [489] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [489] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [490] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [490] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [491] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [491] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [492] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [492] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [493] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [493] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [494] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [494] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [495] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [495] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [496] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [496] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [497] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [497] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [498] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [498] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [499] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [499] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [500] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [500] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [501] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [501] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [502] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [502] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [503] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [503] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [504] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [504] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [505] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [505] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [506] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [506] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [507] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [507] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [508] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [508] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [509] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [509] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [510] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [510] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [255] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [255] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [0] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [0] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [2] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [2] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [3] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [3] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [4] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [4] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [5] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [5] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [6] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [6] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [7] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [7] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [8] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [8] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [9] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [9] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [10] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [10] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [11] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [11] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [12] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [12] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [13] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [13] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [14] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [14] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [15] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [15] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [16] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [16] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [17] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [17] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [18] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [18] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [19] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [19] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [20] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [20] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [21] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [21] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [22] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [22] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [23] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [23] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [24] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [24] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [26] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [26] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [28] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [28] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [29] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [29] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [31] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [31] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [32] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [32] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [33] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [33] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [34] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [34] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [36] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [36] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [37] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [37] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [38] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [38] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [39] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [39] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [40] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [40] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [41] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [41] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [42] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [42] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [43] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [43] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [44] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [44] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [45] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [45] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [46] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [46] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [47] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [47] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [48] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [48] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [49] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [49] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [50] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [50] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [52] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [52] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [54] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [54] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [55] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [55] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [56] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [56] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [57] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [57] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [58] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [58] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [59] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [59] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [60] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [60] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [61] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [61] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [62] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [62] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [63] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [63] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [64] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [64] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [65] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [65] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [66] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [66] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [71] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [71] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [77] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [77] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [78] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [78] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [79] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [79] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [81] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [81] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [82] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [82] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [83] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [83] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [84] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [84] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [85] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [85] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [86] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [86] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [87] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [87] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [88] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [88] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [89] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [89] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [90] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [90] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [91] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [91] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [92] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [92] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [93] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [93] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [94] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [94] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [95] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [95] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [96] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [96] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [97] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [97] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [98] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [98] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [99] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [99] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [100] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [100] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [101] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [101] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [102] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [102] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [103] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [103] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [104] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [104] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [105] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [105] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [106] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [106] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [107] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [107] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [108] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [108] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [109] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [109] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [110] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [110] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [111] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [111] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [112] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [112] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [113] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [113] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [114] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [114] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [115] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [115] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [116] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [116] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [117] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [117] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [118] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [118] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [119] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [119] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [120] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [120] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [121] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [121] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [122] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [122] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [123] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [123] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [124] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [124] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [125] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [125] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [126] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [126] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [127] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [127] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [128] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [128] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [129] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [129] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [130] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [130] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [131] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [131] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [132] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [132] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [133] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [133] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [134] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [134] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [135] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [135] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [136] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [136] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [137] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [137] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [138] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [138] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [139] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [139] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [140] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [140] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [141] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [141] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [142] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [142] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [143] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [143] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [144] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [144] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [145] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [145] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [146] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [146] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [147] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [147] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [148] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [148] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [149] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [149] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [150] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [150] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [151] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [151] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [152] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [152] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [153] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [153] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [154] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [154] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [155] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [155] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [156] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [156] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [157] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [157] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [158] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [158] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [159] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [159] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [160] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [160] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [161] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [161] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [162] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [162] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [163] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [163] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [165] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [165] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [166] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [166] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [167] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [167] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [168] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [168] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [169] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [169] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [170] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [170] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [171] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [171] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [172] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [172] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [173] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [173] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [175] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [175] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [176] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [176] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [177] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [177] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [178] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [178] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [179] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [179] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [180] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [180] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [181] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [181] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [182] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [182] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [183] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [183] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [184] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [184] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [185] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [185] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [186] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [186] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [187] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [187] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [188] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [188] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [189] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [189] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [190] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [190] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [191] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [191] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [192] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [192] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [193] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [193] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [194] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [194] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [195] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [195] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [196] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [196] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [197] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [197] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [198] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [198] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [199] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [199] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [200] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [200] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [201] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [201] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [202] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [202] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [203] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [203] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [204] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [204] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [205] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [205] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [206] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [206] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [207] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [207] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [208] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [208] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [209] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [209] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [210] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [210] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [211] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [211] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [212] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [212] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [213] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [213] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [214] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [214] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [215] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [215] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [216] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [216] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [217] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [217] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [218] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [218] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [219] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [219] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [220] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [220] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [221] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [221] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [222] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [222] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [223] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [223] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [224] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [224] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [225] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [225] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [226] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [226] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [227] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [227] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [228] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [228] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [229] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [229] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [230] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [230] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [231] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [231] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [232] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [232] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [233] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [233] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [234] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [234] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [235] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [235] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [236] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [236] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [237] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [237] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [238] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [238] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [239] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [239] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [240] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [240] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [241] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [241] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [242] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [242] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [243] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [243] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [244] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [244] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [245] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [245] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [246] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [246] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [247] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [247] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [248] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [248] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [249] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [249] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [250] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [250] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [251] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [251] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [252] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [252] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [253] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [253] "reg genblk1.m_tdata_reg[511:0]" +Toggle 0to1 genblk1.m_tdata_reg [254] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [254] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [174] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [1] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [25] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [27] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [30] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [35] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [51] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [53] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [80] "reg genblk1.m_tdata_reg[511:0]" +Toggle 1to0 genblk1.m_tdata_reg [164] "reg genblk1.m_tdata_reg[511:0]" +CHECKSUM: "1259019545 3297052881" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_mx2fn_a_port.r.axis_pl_stage[0].axis_reg_inst +Toggle 0to1 s_tuser [9] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [9] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [1] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [1] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [2] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [2] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [3] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [3] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [4] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [4] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [5] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [5] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [6] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [6] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [7] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [7] "net s_tuser[9:0]" +Toggle 0to1 s_tuser [8] "net s_tuser[9:0]" +Toggle 1to0 s_tuser [8] "net s_tuser[9:0]" +Toggle s_tid "net s_tid[7:0]" +Toggle s_tdest "net s_tdest[7:0]" +Toggle m_tid "net m_tid[7:0]" +Toggle m_tdest "net m_tdest[7:0]" +Toggle genblk1.s_tid_reg "reg genblk1.s_tid_reg[7:0]" +Toggle genblk1.s_tdest_reg "reg genblk1.s_tdest_reg[7:0]" +Toggle 0to1 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [9] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [1] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [2] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [3] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [4] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [5] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [6] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [7] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 1to0 genblk1.m_tuser_reg [8] "reg genblk1.m_tuser_reg[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [9] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [1] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [2] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [3] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [4] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [5] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [6] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [7] "reg genblk1.m_tuser_pre[9:0]" +Toggle 0to1 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle 1to0 genblk1.m_tuser_pre [8] "reg genblk1.m_tuser_pre[9:0]" +Toggle genblk1.m_tid_reg "reg genblk1.m_tid_reg[7:0]" +Toggle genblk1.m_tdest_pre "reg genblk1.m_tdest_pre[7:0]" +Toggle genblk1.m_tdest_reg "reg genblk1.m_tdest_reg[7:0]" +Toggle genblk1.m_tid_pre "reg genblk1.m_tid_pre[7:0]" +Toggle 0to1 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [9] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [1] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [2] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [3] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [4] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [5] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [6] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [7] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 1to0 genblk1.s_tuser_reg [8] "reg genblk1.s_tuser_reg[9:0]" +Toggle 0to1 m_tuser [9] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [9] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [1] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [1] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [2] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [2] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [3] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [3] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [4] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [4] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [5] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [5] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [6] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [6] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [7] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [7] "net m_tuser[9:0]" +Toggle 0to1 m_tuser [8] "net m_tuser[9:0]" +Toggle 1to0 m_tuser [8] "net m_tuser[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_fn2mx_a_port.r.axis_pl[1] +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_fn2mx_b_port.r.axis_pl[0] +Toggle tdata "logic tdata[511:0]" +Toggle 0to1 tvalid "logic tvalid" +Toggle 1to0 tvalid "logic tvalid" +Toggle tuser_vendor "logic tuser_vendor[9:0]" +Toggle 0to1 tlast "logic tlast" +Toggle 1to0 tlast "logic tlast" +Toggle tkeep "logic tkeep[63:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_fn2mx_b_port.r.axis_pl[1] +Toggle tdata "logic tdata[511:0]" +Toggle 0to1 tvalid "logic tvalid" +Toggle 1to0 tvalid "logic tvalid" +Toggle tuser_vendor "logic tuser_vendor[9:0]" +Toggle 0to1 tready "logic tready" +Toggle 1to0 tready "logic tready" +Toggle 0to1 tlast "logic tlast" +Toggle 1to0 tlast "logic tlast" +Toggle tkeep "logic tkeep[63:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_mx2fn_a_port.r.axis_pl[0] +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_mx2fn_a_port.r.axis_pl[1] +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_mx2fn_b_port.r.axis_pl[0] +Toggle tkeep "logic tkeep[63:0]" +Toggle tuser_vendor "logic tuser_vendor[9:0]" +Toggle 0to1 tlast "logic tlast" +Toggle 1to0 tlast "logic tlast" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_mx2fn_b_port.r.axis_pl[1] +Toggle tkeep "logic tkeep[63:0]" +Toggle tuser_vendor "logic tuser_vendor[9:0]" +Toggle 0to1 tready "logic tready" +Toggle 1to0 tready "logic tready" +Toggle 0to1 tlast "logic tlast" +Toggle 1to0 tlast "logic tlast" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_fn2mx_a_port.r.axis_pl[0] +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 tdata [511] "logic tdata[511:0]" +Toggle 1to0 tdata [511] "logic tdata[511:0]" +Toggle 0to1 tdata [0] "logic tdata[511:0]" +Toggle 1to0 tdata [0] "logic tdata[511:0]" +Toggle 0to1 tdata [2] "logic tdata[511:0]" +Toggle 1to0 tdata [2] "logic tdata[511:0]" +Toggle 0to1 tdata [3] "logic tdata[511:0]" +Toggle 1to0 tdata [3] "logic tdata[511:0]" +Toggle 0to1 tdata [4] "logic tdata[511:0]" +Toggle 1to0 tdata [4] "logic tdata[511:0]" +Toggle 0to1 tdata [5] "logic tdata[511:0]" +Toggle 1to0 tdata [5] "logic tdata[511:0]" +Toggle 0to1 tdata [6] "logic tdata[511:0]" +Toggle 1to0 tdata [6] "logic tdata[511:0]" +Toggle 0to1 tdata [7] "logic tdata[511:0]" +Toggle 1to0 tdata [7] "logic tdata[511:0]" +Toggle 0to1 tdata [8] "logic tdata[511:0]" +Toggle 1to0 tdata [8] "logic tdata[511:0]" +Toggle 0to1 tdata [9] "logic tdata[511:0]" +Toggle 1to0 tdata [9] "logic tdata[511:0]" +Toggle 0to1 tdata [10] "logic tdata[511:0]" +Toggle 1to0 tdata [10] "logic tdata[511:0]" +Toggle 0to1 tdata [11] "logic tdata[511:0]" +Toggle 1to0 tdata [11] "logic tdata[511:0]" +Toggle 0to1 tdata [12] "logic tdata[511:0]" +Toggle 1to0 tdata [12] "logic tdata[511:0]" +Toggle 0to1 tdata [13] "logic tdata[511:0]" +Toggle 1to0 tdata [13] "logic tdata[511:0]" +Toggle 0to1 tdata [14] "logic tdata[511:0]" +Toggle 1to0 tdata [14] "logic tdata[511:0]" +Toggle 0to1 tdata [15] "logic tdata[511:0]" +Toggle 1to0 tdata [15] "logic tdata[511:0]" +Toggle 0to1 tdata [16] "logic tdata[511:0]" +Toggle 1to0 tdata [16] "logic tdata[511:0]" +Toggle 0to1 tdata [17] "logic tdata[511:0]" +Toggle 1to0 tdata [17] "logic tdata[511:0]" +Toggle 0to1 tdata [18] "logic tdata[511:0]" +Toggle 1to0 tdata [18] "logic tdata[511:0]" +Toggle 0to1 tdata [19] "logic tdata[511:0]" +Toggle 1to0 tdata [19] "logic tdata[511:0]" +Toggle 0to1 tdata [20] "logic tdata[511:0]" +Toggle 1to0 tdata [20] "logic tdata[511:0]" +Toggle 0to1 tdata [21] "logic tdata[511:0]" +Toggle 1to0 tdata [21] "logic tdata[511:0]" +Toggle 0to1 tdata [22] "logic tdata[511:0]" +Toggle 1to0 tdata [22] "logic tdata[511:0]" +Toggle 0to1 tdata [23] "logic tdata[511:0]" +Toggle 1to0 tdata [23] "logic tdata[511:0]" +Toggle 0to1 tdata [24] "logic tdata[511:0]" +Toggle 1to0 tdata [24] "logic tdata[511:0]" +Toggle 0to1 tdata [26] "logic tdata[511:0]" +Toggle 1to0 tdata [26] "logic tdata[511:0]" +Toggle 0to1 tdata [28] "logic tdata[511:0]" +Toggle 1to0 tdata [28] "logic tdata[511:0]" +Toggle 0to1 tdata [29] "logic tdata[511:0]" +Toggle 1to0 tdata [29] "logic tdata[511:0]" +Toggle 0to1 tdata [31] "logic tdata[511:0]" +Toggle 1to0 tdata [31] "logic tdata[511:0]" +Toggle 0to1 tdata [32] "logic tdata[511:0]" +Toggle 1to0 tdata [32] "logic tdata[511:0]" +Toggle 0to1 tdata [33] "logic tdata[511:0]" +Toggle 1to0 tdata [33] "logic tdata[511:0]" +Toggle 0to1 tdata [34] "logic tdata[511:0]" +Toggle 1to0 tdata [34] "logic tdata[511:0]" +Toggle 0to1 tdata [36] "logic tdata[511:0]" +Toggle 1to0 tdata [36] "logic tdata[511:0]" +Toggle 0to1 tdata [37] "logic tdata[511:0]" +Toggle 1to0 tdata [37] "logic tdata[511:0]" +Toggle 0to1 tdata [38] "logic tdata[511:0]" +Toggle 1to0 tdata [38] "logic tdata[511:0]" +Toggle 0to1 tdata [39] "logic tdata[511:0]" +Toggle 1to0 tdata [39] "logic tdata[511:0]" +Toggle 0to1 tdata [40] "logic tdata[511:0]" +Toggle 1to0 tdata [40] "logic tdata[511:0]" +Toggle 0to1 tdata [41] "logic tdata[511:0]" +Toggle 1to0 tdata [41] "logic tdata[511:0]" +Toggle 0to1 tdata [42] "logic tdata[511:0]" +Toggle 1to0 tdata [42] "logic tdata[511:0]" +Toggle 0to1 tdata [43] "logic tdata[511:0]" +Toggle 1to0 tdata [43] "logic tdata[511:0]" +Toggle 0to1 tdata [44] "logic tdata[511:0]" +Toggle 1to0 tdata [44] "logic tdata[511:0]" +Toggle 0to1 tdata [45] "logic tdata[511:0]" +Toggle 1to0 tdata [45] "logic tdata[511:0]" +Toggle 0to1 tdata [46] "logic tdata[511:0]" +Toggle 1to0 tdata [46] "logic tdata[511:0]" +Toggle 0to1 tdata [47] "logic tdata[511:0]" +Toggle 1to0 tdata [47] "logic tdata[511:0]" +Toggle 0to1 tdata [48] "logic tdata[511:0]" +Toggle 1to0 tdata [48] "logic tdata[511:0]" +Toggle 0to1 tdata [49] "logic tdata[511:0]" +Toggle 1to0 tdata [49] "logic tdata[511:0]" +Toggle 0to1 tdata [50] "logic tdata[511:0]" +Toggle 1to0 tdata [50] "logic tdata[511:0]" +Toggle 0to1 tdata [52] "logic tdata[511:0]" +Toggle 1to0 tdata [52] "logic tdata[511:0]" +Toggle 0to1 tdata [54] "logic tdata[511:0]" +Toggle 1to0 tdata [54] "logic tdata[511:0]" +Toggle 0to1 tdata [55] "logic tdata[511:0]" +Toggle 1to0 tdata [55] "logic tdata[511:0]" +Toggle 0to1 tdata [56] "logic tdata[511:0]" +Toggle 1to0 tdata [56] "logic tdata[511:0]" +Toggle 0to1 tdata [57] "logic tdata[511:0]" +Toggle 1to0 tdata [57] "logic tdata[511:0]" +Toggle 0to1 tdata [58] "logic tdata[511:0]" +Toggle 1to0 tdata [58] "logic tdata[511:0]" +Toggle 0to1 tdata [59] "logic tdata[511:0]" +Toggle 1to0 tdata [59] "logic tdata[511:0]" +Toggle 0to1 tdata [60] "logic tdata[511:0]" +Toggle 1to0 tdata [60] "logic tdata[511:0]" +Toggle 0to1 tdata [61] "logic tdata[511:0]" +Toggle 1to0 tdata [61] "logic tdata[511:0]" +Toggle 0to1 tdata [62] "logic tdata[511:0]" +Toggle 1to0 tdata [62] "logic tdata[511:0]" +Toggle 0to1 tdata [63] "logic tdata[511:0]" +Toggle 1to0 tdata [63] "logic tdata[511:0]" +Toggle 0to1 tdata [64] "logic tdata[511:0]" +Toggle 1to0 tdata [64] "logic tdata[511:0]" +Toggle 0to1 tdata [65] "logic tdata[511:0]" +Toggle 1to0 tdata [65] "logic tdata[511:0]" +Toggle 0to1 tdata [66] "logic tdata[511:0]" +Toggle 1to0 tdata [66] "logic tdata[511:0]" +Toggle 0to1 tdata [71] "logic tdata[511:0]" +Toggle 1to0 tdata [71] "logic tdata[511:0]" +Toggle 0to1 tdata [77] "logic tdata[511:0]" +Toggle 1to0 tdata [77] "logic tdata[511:0]" +Toggle 0to1 tdata [78] "logic tdata[511:0]" +Toggle 1to0 tdata [78] "logic tdata[511:0]" +Toggle 0to1 tdata [79] "logic tdata[511:0]" +Toggle 1to0 tdata [79] "logic tdata[511:0]" +Toggle 0to1 tdata [81] "logic tdata[511:0]" +Toggle 1to0 tdata [81] "logic tdata[511:0]" +Toggle 0to1 tdata [82] "logic tdata[511:0]" +Toggle 1to0 tdata [82] "logic tdata[511:0]" +Toggle 0to1 tdata [83] "logic tdata[511:0]" +Toggle 1to0 tdata [83] "logic tdata[511:0]" +Toggle 0to1 tdata [84] "logic tdata[511:0]" +Toggle 1to0 tdata [84] "logic tdata[511:0]" +Toggle 0to1 tdata [85] "logic tdata[511:0]" +Toggle 1to0 tdata [85] "logic tdata[511:0]" +Toggle 0to1 tdata [86] "logic tdata[511:0]" +Toggle 1to0 tdata [86] "logic tdata[511:0]" +Toggle 0to1 tdata [87] "logic tdata[511:0]" +Toggle 1to0 tdata [87] "logic tdata[511:0]" +Toggle 0to1 tdata [88] "logic tdata[511:0]" +Toggle 1to0 tdata [88] "logic tdata[511:0]" +Toggle 0to1 tdata [89] "logic tdata[511:0]" +Toggle 1to0 tdata [89] "logic tdata[511:0]" +Toggle 0to1 tdata [90] "logic tdata[511:0]" +Toggle 1to0 tdata [90] "logic tdata[511:0]" +Toggle 0to1 tdata [91] "logic tdata[511:0]" +Toggle 1to0 tdata [91] "logic tdata[511:0]" +Toggle 0to1 tdata [92] "logic tdata[511:0]" +Toggle 1to0 tdata [92] "logic tdata[511:0]" +Toggle 0to1 tdata [93] "logic tdata[511:0]" +Toggle 1to0 tdata [93] "logic tdata[511:0]" +Toggle 0to1 tdata [94] "logic tdata[511:0]" +Toggle 1to0 tdata [94] "logic tdata[511:0]" +Toggle 0to1 tdata [95] "logic tdata[511:0]" +Toggle 1to0 tdata [95] "logic tdata[511:0]" +Toggle 0to1 tdata [96] "logic tdata[511:0]" +Toggle 1to0 tdata [96] "logic tdata[511:0]" +Toggle 0to1 tdata [97] "logic tdata[511:0]" +Toggle 1to0 tdata [97] "logic tdata[511:0]" +Toggle 0to1 tdata [98] "logic tdata[511:0]" +Toggle 1to0 tdata [98] "logic tdata[511:0]" +Toggle 0to1 tdata [99] "logic tdata[511:0]" +Toggle 1to0 tdata [99] "logic tdata[511:0]" +Toggle 0to1 tdata [100] "logic tdata[511:0]" +Toggle 1to0 tdata [100] "logic tdata[511:0]" +Toggle 0to1 tdata [101] "logic tdata[511:0]" +Toggle 1to0 tdata [101] "logic tdata[511:0]" +Toggle 0to1 tdata [102] "logic tdata[511:0]" +Toggle 1to0 tdata [102] "logic tdata[511:0]" +Toggle 0to1 tdata [103] "logic tdata[511:0]" +Toggle 1to0 tdata [103] "logic tdata[511:0]" +Toggle 0to1 tdata [104] "logic tdata[511:0]" +Toggle 1to0 tdata [104] "logic tdata[511:0]" +Toggle 0to1 tdata [105] "logic tdata[511:0]" +Toggle 1to0 tdata [105] "logic tdata[511:0]" +Toggle 0to1 tdata [106] "logic tdata[511:0]" +Toggle 1to0 tdata [106] "logic tdata[511:0]" +Toggle 0to1 tdata [107] "logic tdata[511:0]" +Toggle 1to0 tdata [107] "logic tdata[511:0]" +Toggle 0to1 tdata [108] "logic tdata[511:0]" +Toggle 1to0 tdata [108] "logic tdata[511:0]" +Toggle 0to1 tdata [109] "logic tdata[511:0]" +Toggle 1to0 tdata [109] "logic tdata[511:0]" +Toggle 0to1 tdata [110] "logic tdata[511:0]" +Toggle 1to0 tdata [110] "logic tdata[511:0]" +Toggle 0to1 tdata [111] "logic tdata[511:0]" +Toggle 1to0 tdata [111] "logic tdata[511:0]" +Toggle 0to1 tdata [112] "logic tdata[511:0]" +Toggle 1to0 tdata [112] "logic tdata[511:0]" +Toggle 0to1 tdata [113] "logic tdata[511:0]" +Toggle 1to0 tdata [113] "logic tdata[511:0]" +Toggle 0to1 tdata [114] "logic tdata[511:0]" +Toggle 1to0 tdata [114] "logic tdata[511:0]" +Toggle 0to1 tdata [115] "logic tdata[511:0]" +Toggle 1to0 tdata [115] "logic tdata[511:0]" +Toggle 0to1 tdata [116] "logic tdata[511:0]" +Toggle 1to0 tdata [116] "logic tdata[511:0]" +Toggle 0to1 tdata [117] "logic tdata[511:0]" +Toggle 1to0 tdata [117] "logic tdata[511:0]" +Toggle 0to1 tdata [118] "logic tdata[511:0]" +Toggle 1to0 tdata [118] "logic tdata[511:0]" +Toggle 0to1 tdata [119] "logic tdata[511:0]" +Toggle 1to0 tdata [119] "logic tdata[511:0]" +Toggle 0to1 tdata [120] "logic tdata[511:0]" +Toggle 1to0 tdata [120] "logic tdata[511:0]" +Toggle 0to1 tdata [121] "logic tdata[511:0]" +Toggle 1to0 tdata [121] "logic tdata[511:0]" +Toggle 0to1 tdata [122] "logic tdata[511:0]" +Toggle 1to0 tdata [122] "logic tdata[511:0]" +Toggle 0to1 tdata [123] "logic tdata[511:0]" +Toggle 1to0 tdata [123] "logic tdata[511:0]" +Toggle 0to1 tdata [124] "logic tdata[511:0]" +Toggle 1to0 tdata [124] "logic tdata[511:0]" +Toggle 0to1 tdata [125] "logic tdata[511:0]" +Toggle 1to0 tdata [125] "logic tdata[511:0]" +Toggle 0to1 tdata [126] "logic tdata[511:0]" +Toggle 1to0 tdata [126] "logic tdata[511:0]" +Toggle 0to1 tdata [127] "logic tdata[511:0]" +Toggle 1to0 tdata [127] "logic tdata[511:0]" +Toggle 0to1 tdata [128] "logic tdata[511:0]" +Toggle 1to0 tdata [128] "logic tdata[511:0]" +Toggle 0to1 tdata [129] "logic tdata[511:0]" +Toggle 1to0 tdata [129] "logic tdata[511:0]" +Toggle 0to1 tdata [130] "logic tdata[511:0]" +Toggle 1to0 tdata [130] "logic tdata[511:0]" +Toggle 0to1 tdata [131] "logic tdata[511:0]" +Toggle 1to0 tdata [131] "logic tdata[511:0]" +Toggle 0to1 tdata [132] "logic tdata[511:0]" +Toggle 1to0 tdata [132] "logic tdata[511:0]" +Toggle 0to1 tdata [133] "logic tdata[511:0]" +Toggle 1to0 tdata [133] "logic tdata[511:0]" +Toggle 0to1 tdata [134] "logic tdata[511:0]" +Toggle 1to0 tdata [134] "logic tdata[511:0]" +Toggle 0to1 tdata [135] "logic tdata[511:0]" +Toggle 1to0 tdata [135] "logic tdata[511:0]" +Toggle 0to1 tdata [136] "logic tdata[511:0]" +Toggle 1to0 tdata [136] "logic tdata[511:0]" +Toggle 0to1 tdata [137] "logic tdata[511:0]" +Toggle 1to0 tdata [137] "logic tdata[511:0]" +Toggle 0to1 tdata [138] "logic tdata[511:0]" +Toggle 1to0 tdata [138] "logic tdata[511:0]" +Toggle 0to1 tdata [139] "logic tdata[511:0]" +Toggle 1to0 tdata [139] "logic tdata[511:0]" +Toggle 0to1 tdata [140] "logic tdata[511:0]" +Toggle 1to0 tdata [140] "logic tdata[511:0]" +Toggle 0to1 tdata [141] "logic tdata[511:0]" +Toggle 1to0 tdata [141] "logic tdata[511:0]" +Toggle 0to1 tdata [142] "logic tdata[511:0]" +Toggle 1to0 tdata [142] "logic tdata[511:0]" +Toggle 0to1 tdata [143] "logic tdata[511:0]" +Toggle 1to0 tdata [143] "logic tdata[511:0]" +Toggle 0to1 tdata [144] "logic tdata[511:0]" +Toggle 1to0 tdata [144] "logic tdata[511:0]" +Toggle 0to1 tdata [145] "logic tdata[511:0]" +Toggle 1to0 tdata [145] "logic tdata[511:0]" +Toggle 0to1 tdata [146] "logic tdata[511:0]" +Toggle 1to0 tdata [146] "logic tdata[511:0]" +Toggle 0to1 tdata [147] "logic tdata[511:0]" +Toggle 1to0 tdata [147] "logic tdata[511:0]" +Toggle 0to1 tdata [148] "logic tdata[511:0]" +Toggle 1to0 tdata [148] "logic tdata[511:0]" +Toggle 0to1 tdata [149] "logic tdata[511:0]" +Toggle 1to0 tdata [149] "logic tdata[511:0]" +Toggle 0to1 tdata [150] "logic tdata[511:0]" +Toggle 1to0 tdata [150] "logic tdata[511:0]" +Toggle 0to1 tdata [151] "logic tdata[511:0]" +Toggle 1to0 tdata [151] "logic tdata[511:0]" +Toggle 0to1 tdata [152] "logic tdata[511:0]" +Toggle 1to0 tdata [152] "logic tdata[511:0]" +Toggle 0to1 tdata [153] "logic tdata[511:0]" +Toggle 1to0 tdata [153] "logic tdata[511:0]" +Toggle 0to1 tdata [154] "logic tdata[511:0]" +Toggle 1to0 tdata [154] "logic tdata[511:0]" +Toggle 0to1 tdata [155] "logic tdata[511:0]" +Toggle 1to0 tdata [155] "logic tdata[511:0]" +Toggle 0to1 tdata [156] "logic tdata[511:0]" +Toggle 1to0 tdata [156] "logic tdata[511:0]" +Toggle 0to1 tdata [157] "logic tdata[511:0]" +Toggle 1to0 tdata [157] "logic tdata[511:0]" +Toggle 0to1 tdata [158] "logic tdata[511:0]" +Toggle 1to0 tdata [158] "logic tdata[511:0]" +Toggle 0to1 tdata [159] "logic tdata[511:0]" +Toggle 1to0 tdata [159] "logic tdata[511:0]" +Toggle 0to1 tdata [160] "logic tdata[511:0]" +Toggle 1to0 tdata [160] "logic tdata[511:0]" +Toggle 0to1 tdata [161] "logic tdata[511:0]" +Toggle 1to0 tdata [161] "logic tdata[511:0]" +Toggle 0to1 tdata [162] "logic tdata[511:0]" +Toggle 1to0 tdata [162] "logic tdata[511:0]" +Toggle 0to1 tdata [163] "logic tdata[511:0]" +Toggle 1to0 tdata [163] "logic tdata[511:0]" +Toggle 0to1 tdata [165] "logic tdata[511:0]" +Toggle 1to0 tdata [165] "logic tdata[511:0]" +Toggle 0to1 tdata [166] "logic tdata[511:0]" +Toggle 1to0 tdata [166] "logic tdata[511:0]" +Toggle 0to1 tdata [167] "logic tdata[511:0]" +Toggle 1to0 tdata [167] "logic tdata[511:0]" +Toggle 0to1 tdata [168] "logic tdata[511:0]" +Toggle 1to0 tdata [168] "logic tdata[511:0]" +Toggle 0to1 tdata [169] "logic tdata[511:0]" +Toggle 1to0 tdata [169] "logic tdata[511:0]" +Toggle 0to1 tdata [170] "logic tdata[511:0]" +Toggle 1to0 tdata [170] "logic tdata[511:0]" +Toggle 0to1 tdata [171] "logic tdata[511:0]" +Toggle 1to0 tdata [171] "logic tdata[511:0]" +Toggle 0to1 tdata [172] "logic tdata[511:0]" +Toggle 1to0 tdata [172] "logic tdata[511:0]" +Toggle 0to1 tdata [173] "logic tdata[511:0]" +Toggle 1to0 tdata [173] "logic tdata[511:0]" +Toggle 0to1 tdata [175] "logic tdata[511:0]" +Toggle 1to0 tdata [175] "logic tdata[511:0]" +Toggle 0to1 tdata [176] "logic tdata[511:0]" +Toggle 1to0 tdata [176] "logic tdata[511:0]" +Toggle 0to1 tdata [177] "logic tdata[511:0]" +Toggle 1to0 tdata [177] "logic tdata[511:0]" +Toggle 0to1 tdata [178] "logic tdata[511:0]" +Toggle 1to0 tdata [178] "logic tdata[511:0]" +Toggle 0to1 tdata [179] "logic tdata[511:0]" +Toggle 1to0 tdata [179] "logic tdata[511:0]" +Toggle 0to1 tdata [180] "logic tdata[511:0]" +Toggle 1to0 tdata [180] "logic tdata[511:0]" +Toggle 0to1 tdata [181] "logic tdata[511:0]" +Toggle 1to0 tdata [181] "logic tdata[511:0]" +Toggle 0to1 tdata [182] "logic tdata[511:0]" +Toggle 1to0 tdata [182] "logic tdata[511:0]" +Toggle 0to1 tdata [183] "logic tdata[511:0]" +Toggle 1to0 tdata [183] "logic tdata[511:0]" +Toggle 0to1 tdata [184] "logic tdata[511:0]" +Toggle 1to0 tdata [184] "logic tdata[511:0]" +Toggle 0to1 tdata [185] "logic tdata[511:0]" +Toggle 1to0 tdata [185] "logic tdata[511:0]" +Toggle 0to1 tdata [186] "logic tdata[511:0]" +Toggle 1to0 tdata [186] "logic tdata[511:0]" +Toggle 0to1 tdata [187] "logic tdata[511:0]" +Toggle 1to0 tdata [187] "logic tdata[511:0]" +Toggle 0to1 tdata [188] "logic tdata[511:0]" +Toggle 1to0 tdata [188] "logic tdata[511:0]" +Toggle 0to1 tdata [189] "logic tdata[511:0]" +Toggle 1to0 tdata [189] "logic tdata[511:0]" +Toggle 0to1 tdata [190] "logic tdata[511:0]" +Toggle 1to0 tdata [190] "logic tdata[511:0]" +Toggle 0to1 tdata [191] "logic tdata[511:0]" +Toggle 1to0 tdata [191] "logic tdata[511:0]" +Toggle 0to1 tdata [192] "logic tdata[511:0]" +Toggle 1to0 tdata [192] "logic tdata[511:0]" +Toggle 0to1 tdata [193] "logic tdata[511:0]" +Toggle 1to0 tdata [193] "logic tdata[511:0]" +Toggle 0to1 tdata [194] "logic tdata[511:0]" +Toggle 1to0 tdata [194] "logic tdata[511:0]" +Toggle 0to1 tdata [195] "logic tdata[511:0]" +Toggle 1to0 tdata [195] "logic tdata[511:0]" +Toggle 0to1 tdata [196] "logic tdata[511:0]" +Toggle 1to0 tdata [196] "logic tdata[511:0]" +Toggle 0to1 tdata [197] "logic tdata[511:0]" +Toggle 1to0 tdata [197] "logic tdata[511:0]" +Toggle 0to1 tdata [198] "logic tdata[511:0]" +Toggle 1to0 tdata [198] "logic tdata[511:0]" +Toggle 0to1 tdata [199] "logic tdata[511:0]" +Toggle 1to0 tdata [199] "logic tdata[511:0]" +Toggle 0to1 tdata [200] "logic tdata[511:0]" +Toggle 1to0 tdata [200] "logic tdata[511:0]" +Toggle 0to1 tdata [201] "logic tdata[511:0]" +Toggle 1to0 tdata [201] "logic tdata[511:0]" +Toggle 0to1 tdata [202] "logic tdata[511:0]" +Toggle 1to0 tdata [202] "logic tdata[511:0]" +Toggle 0to1 tdata [203] "logic tdata[511:0]" +Toggle 1to0 tdata [203] "logic tdata[511:0]" +Toggle 0to1 tdata [204] "logic tdata[511:0]" +Toggle 1to0 tdata [204] "logic tdata[511:0]" +Toggle 0to1 tdata [205] "logic tdata[511:0]" +Toggle 1to0 tdata [205] "logic tdata[511:0]" +Toggle 0to1 tdata [206] "logic tdata[511:0]" +Toggle 1to0 tdata [206] "logic tdata[511:0]" +Toggle 0to1 tdata [207] "logic tdata[511:0]" +Toggle 1to0 tdata [207] "logic tdata[511:0]" +Toggle 0to1 tdata [208] "logic tdata[511:0]" +Toggle 1to0 tdata [208] "logic tdata[511:0]" +Toggle 0to1 tdata [209] "logic tdata[511:0]" +Toggle 1to0 tdata [209] "logic tdata[511:0]" +Toggle 0to1 tdata [210] "logic tdata[511:0]" +Toggle 1to0 tdata [210] "logic tdata[511:0]" +Toggle 0to1 tdata [211] "logic tdata[511:0]" +Toggle 1to0 tdata [211] "logic tdata[511:0]" +Toggle 0to1 tdata [212] "logic tdata[511:0]" +Toggle 1to0 tdata [212] "logic tdata[511:0]" +Toggle 0to1 tdata [213] "logic tdata[511:0]" +Toggle 1to0 tdata [213] "logic tdata[511:0]" +Toggle 0to1 tdata [214] "logic tdata[511:0]" +Toggle 1to0 tdata [214] "logic tdata[511:0]" +Toggle 0to1 tdata [215] "logic tdata[511:0]" +Toggle 1to0 tdata [215] "logic tdata[511:0]" +Toggle 0to1 tdata [216] "logic tdata[511:0]" +Toggle 1to0 tdata [216] "logic tdata[511:0]" +Toggle 0to1 tdata [217] "logic tdata[511:0]" +Toggle 1to0 tdata [217] "logic tdata[511:0]" +Toggle 0to1 tdata [218] "logic tdata[511:0]" +Toggle 1to0 tdata [218] "logic tdata[511:0]" +Toggle 0to1 tdata [219] "logic tdata[511:0]" +Toggle 1to0 tdata [219] "logic tdata[511:0]" +Toggle 0to1 tdata [220] "logic tdata[511:0]" +Toggle 1to0 tdata [220] "logic tdata[511:0]" +Toggle 0to1 tdata [221] "logic tdata[511:0]" +Toggle 1to0 tdata [221] "logic tdata[511:0]" +Toggle 0to1 tdata [222] "logic tdata[511:0]" +Toggle 1to0 tdata [222] "logic tdata[511:0]" +Toggle 0to1 tdata [223] "logic tdata[511:0]" +Toggle 1to0 tdata [223] "logic tdata[511:0]" +Toggle 0to1 tdata [224] "logic tdata[511:0]" +Toggle 1to0 tdata [224] "logic tdata[511:0]" +Toggle 0to1 tdata [225] "logic tdata[511:0]" +Toggle 1to0 tdata [225] "logic tdata[511:0]" +Toggle 0to1 tdata [226] "logic tdata[511:0]" +Toggle 1to0 tdata [226] "logic tdata[511:0]" +Toggle 0to1 tdata [227] "logic tdata[511:0]" +Toggle 1to0 tdata [227] "logic tdata[511:0]" +Toggle 0to1 tdata [228] "logic tdata[511:0]" +Toggle 1to0 tdata [228] "logic tdata[511:0]" +Toggle 0to1 tdata [229] "logic tdata[511:0]" +Toggle 1to0 tdata [229] "logic tdata[511:0]" +Toggle 0to1 tdata [230] "logic tdata[511:0]" +Toggle 1to0 tdata [230] "logic tdata[511:0]" +Toggle 0to1 tdata [231] "logic tdata[511:0]" +Toggle 1to0 tdata [231] "logic tdata[511:0]" +Toggle 0to1 tdata [232] "logic tdata[511:0]" +Toggle 1to0 tdata [232] "logic tdata[511:0]" +Toggle 0to1 tdata [233] "logic tdata[511:0]" +Toggle 1to0 tdata [233] "logic tdata[511:0]" +Toggle 0to1 tdata [234] "logic tdata[511:0]" +Toggle 1to0 tdata [234] "logic tdata[511:0]" +Toggle 0to1 tdata [235] "logic tdata[511:0]" +Toggle 1to0 tdata [235] "logic tdata[511:0]" +Toggle 0to1 tdata [236] "logic tdata[511:0]" +Toggle 1to0 tdata [236] "logic tdata[511:0]" +Toggle 0to1 tdata [237] "logic tdata[511:0]" +Toggle 1to0 tdata [237] "logic tdata[511:0]" +Toggle 0to1 tdata [238] "logic tdata[511:0]" +Toggle 1to0 tdata [238] "logic tdata[511:0]" +Toggle 0to1 tdata [239] "logic tdata[511:0]" +Toggle 1to0 tdata [239] "logic tdata[511:0]" +Toggle 0to1 tdata [240] "logic tdata[511:0]" +Toggle 1to0 tdata [240] "logic tdata[511:0]" +Toggle 0to1 tdata [241] "logic tdata[511:0]" +Toggle 1to0 tdata [241] "logic tdata[511:0]" +Toggle 0to1 tdata [242] "logic tdata[511:0]" +Toggle 1to0 tdata [242] "logic tdata[511:0]" +Toggle 0to1 tdata [243] "logic tdata[511:0]" +Toggle 1to0 tdata [243] "logic tdata[511:0]" +Toggle 0to1 tdata [244] "logic tdata[511:0]" +Toggle 1to0 tdata [244] "logic tdata[511:0]" +Toggle 0to1 tdata [245] "logic tdata[511:0]" +Toggle 1to0 tdata [245] "logic tdata[511:0]" +Toggle 0to1 tdata [246] "logic tdata[511:0]" +Toggle 1to0 tdata [246] "logic tdata[511:0]" +Toggle 0to1 tdata [247] "logic tdata[511:0]" +Toggle 1to0 tdata [247] "logic tdata[511:0]" +Toggle 0to1 tdata [248] "logic tdata[511:0]" +Toggle 1to0 tdata [248] "logic tdata[511:0]" +Toggle 0to1 tdata [249] "logic tdata[511:0]" +Toggle 1to0 tdata [249] "logic tdata[511:0]" +Toggle 0to1 tdata [250] "logic tdata[511:0]" +Toggle 1to0 tdata [250] "logic tdata[511:0]" +Toggle 0to1 tdata [251] "logic tdata[511:0]" +Toggle 1to0 tdata [251] "logic tdata[511:0]" +Toggle 0to1 tdata [252] "logic tdata[511:0]" +Toggle 1to0 tdata [252] "logic tdata[511:0]" +Toggle 0to1 tdata [253] "logic tdata[511:0]" +Toggle 1to0 tdata [253] "logic tdata[511:0]" +Toggle 0to1 tdata [254] "logic tdata[511:0]" +Toggle 1to0 tdata [254] "logic tdata[511:0]" +Toggle 0to1 tdata [255] "logic tdata[511:0]" +Toggle 1to0 tdata [255] "logic tdata[511:0]" +Toggle 0to1 tdata [320] "logic tdata[511:0]" +Toggle 1to0 tdata [320] "logic tdata[511:0]" +Toggle 0to1 tdata [321] "logic tdata[511:0]" +Toggle 1to0 tdata [321] "logic tdata[511:0]" +Toggle 0to1 tdata [322] "logic tdata[511:0]" +Toggle 1to0 tdata [322] "logic tdata[511:0]" +Toggle 0to1 tdata [323] "logic tdata[511:0]" +Toggle 1to0 tdata [323] "logic tdata[511:0]" +Toggle 0to1 tdata [324] "logic tdata[511:0]" +Toggle 1to0 tdata [324] "logic tdata[511:0]" +Toggle 0to1 tdata [325] "logic tdata[511:0]" +Toggle 1to0 tdata [325] "logic tdata[511:0]" +Toggle 0to1 tdata [326] "logic tdata[511:0]" +Toggle 1to0 tdata [326] "logic tdata[511:0]" +Toggle 0to1 tdata [327] "logic tdata[511:0]" +Toggle 1to0 tdata [327] "logic tdata[511:0]" +Toggle 0to1 tdata [328] "logic tdata[511:0]" +Toggle 1to0 tdata [328] "logic tdata[511:0]" +Toggle 0to1 tdata [329] "logic tdata[511:0]" +Toggle 1to0 tdata [329] "logic tdata[511:0]" +Toggle 0to1 tdata [330] "logic tdata[511:0]" +Toggle 1to0 tdata [330] "logic tdata[511:0]" +Toggle 0to1 tdata [331] "logic tdata[511:0]" +Toggle 1to0 tdata [331] "logic tdata[511:0]" +Toggle 0to1 tdata [332] "logic tdata[511:0]" +Toggle 1to0 tdata [332] "logic tdata[511:0]" +Toggle 0to1 tdata [333] "logic tdata[511:0]" +Toggle 1to0 tdata [333] "logic tdata[511:0]" +Toggle 0to1 tdata [334] "logic tdata[511:0]" +Toggle 1to0 tdata [334] "logic tdata[511:0]" +Toggle 0to1 tdata [335] "logic tdata[511:0]" +Toggle 1to0 tdata [335] "logic tdata[511:0]" +Toggle 0to1 tdata [336] "logic tdata[511:0]" +Toggle 1to0 tdata [336] "logic tdata[511:0]" +Toggle 0to1 tdata [337] "logic tdata[511:0]" +Toggle 1to0 tdata [337] "logic tdata[511:0]" +Toggle 0to1 tdata [338] "logic tdata[511:0]" +Toggle 1to0 tdata [338] "logic tdata[511:0]" +Toggle 0to1 tdata [339] "logic tdata[511:0]" +Toggle 1to0 tdata [339] "logic tdata[511:0]" +Toggle 0to1 tdata [340] "logic tdata[511:0]" +Toggle 1to0 tdata [340] "logic tdata[511:0]" +Toggle 0to1 tdata [341] "logic tdata[511:0]" +Toggle 1to0 tdata [341] "logic tdata[511:0]" +Toggle 0to1 tdata [342] "logic tdata[511:0]" +Toggle 1to0 tdata [342] "logic tdata[511:0]" +Toggle 0to1 tdata [343] "logic tdata[511:0]" +Toggle 1to0 tdata [343] "logic tdata[511:0]" +Toggle 0to1 tdata [344] "logic tdata[511:0]" +Toggle 1to0 tdata [344] "logic tdata[511:0]" +Toggle 0to1 tdata [345] "logic tdata[511:0]" +Toggle 1to0 tdata [345] "logic tdata[511:0]" +Toggle 0to1 tdata [346] "logic tdata[511:0]" +Toggle 1to0 tdata [346] "logic tdata[511:0]" +Toggle 0to1 tdata [347] "logic tdata[511:0]" +Toggle 1to0 tdata [347] "logic tdata[511:0]" +Toggle 0to1 tdata [348] "logic tdata[511:0]" +Toggle 1to0 tdata [348] "logic tdata[511:0]" +Toggle 0to1 tdata [349] "logic tdata[511:0]" +Toggle 1to0 tdata [349] "logic tdata[511:0]" +Toggle 0to1 tdata [350] "logic tdata[511:0]" +Toggle 1to0 tdata [350] "logic tdata[511:0]" +Toggle 0to1 tdata [351] "logic tdata[511:0]" +Toggle 1to0 tdata [351] "logic tdata[511:0]" +Toggle 0to1 tdata [352] "logic tdata[511:0]" +Toggle 1to0 tdata [352] "logic tdata[511:0]" +Toggle 0to1 tdata [353] "logic tdata[511:0]" +Toggle 1to0 tdata [353] "logic tdata[511:0]" +Toggle 0to1 tdata [354] "logic tdata[511:0]" +Toggle 1to0 tdata [354] "logic tdata[511:0]" +Toggle 0to1 tdata [355] "logic tdata[511:0]" +Toggle 1to0 tdata [355] "logic tdata[511:0]" +Toggle 0to1 tdata [356] "logic tdata[511:0]" +Toggle 1to0 tdata [356] "logic tdata[511:0]" +Toggle 0to1 tdata [357] "logic tdata[511:0]" +Toggle 1to0 tdata [357] "logic tdata[511:0]" +Toggle 0to1 tdata [358] "logic tdata[511:0]" +Toggle 1to0 tdata [358] "logic tdata[511:0]" +Toggle 0to1 tdata [359] "logic tdata[511:0]" +Toggle 1to0 tdata [359] "logic tdata[511:0]" +Toggle 0to1 tdata [360] "logic tdata[511:0]" +Toggle 1to0 tdata [360] "logic tdata[511:0]" +Toggle 0to1 tdata [361] "logic tdata[511:0]" +Toggle 1to0 tdata [361] "logic tdata[511:0]" +Toggle 0to1 tdata [362] "logic tdata[511:0]" +Toggle 1to0 tdata [362] "logic tdata[511:0]" +Toggle 0to1 tdata [363] "logic tdata[511:0]" +Toggle 1to0 tdata [363] "logic tdata[511:0]" +Toggle 0to1 tdata [364] "logic tdata[511:0]" +Toggle 1to0 tdata [364] "logic tdata[511:0]" +Toggle 0to1 tdata [365] "logic tdata[511:0]" +Toggle 1to0 tdata [365] "logic tdata[511:0]" +Toggle 0to1 tdata [366] "logic tdata[511:0]" +Toggle 1to0 tdata [366] "logic tdata[511:0]" +Toggle 0to1 tdata [367] "logic tdata[511:0]" +Toggle 1to0 tdata [367] "logic tdata[511:0]" +Toggle 0to1 tdata [368] "logic tdata[511:0]" +Toggle 1to0 tdata [368] "logic tdata[511:0]" +Toggle 0to1 tdata [369] "logic tdata[511:0]" +Toggle 1to0 tdata [369] "logic tdata[511:0]" +Toggle 0to1 tdata [370] "logic tdata[511:0]" +Toggle 1to0 tdata [370] "logic tdata[511:0]" +Toggle 0to1 tdata [371] "logic tdata[511:0]" +Toggle 1to0 tdata [371] "logic tdata[511:0]" +Toggle 0to1 tdata [372] "logic tdata[511:0]" +Toggle 1to0 tdata [372] "logic tdata[511:0]" +Toggle 0to1 tdata [373] "logic tdata[511:0]" +Toggle 1to0 tdata [373] "logic tdata[511:0]" +Toggle 0to1 tdata [374] "logic tdata[511:0]" +Toggle 1to0 tdata [374] "logic tdata[511:0]" +Toggle 0to1 tdata [375] "logic tdata[511:0]" +Toggle 1to0 tdata [375] "logic tdata[511:0]" +Toggle 0to1 tdata [376] "logic tdata[511:0]" +Toggle 1to0 tdata [376] "logic tdata[511:0]" +Toggle 0to1 tdata [377] "logic tdata[511:0]" +Toggle 1to0 tdata [377] "logic tdata[511:0]" +Toggle 0to1 tdata [378] "logic tdata[511:0]" +Toggle 1to0 tdata [378] "logic tdata[511:0]" +Toggle 0to1 tdata [379] "logic tdata[511:0]" +Toggle 1to0 tdata [379] "logic tdata[511:0]" +Toggle 0to1 tdata [380] "logic tdata[511:0]" +Toggle 1to0 tdata [380] "logic tdata[511:0]" +Toggle 0to1 tdata [381] "logic tdata[511:0]" +Toggle 1to0 tdata [381] "logic tdata[511:0]" +Toggle 0to1 tdata [382] "logic tdata[511:0]" +Toggle 1to0 tdata [382] "logic tdata[511:0]" +Toggle 0to1 tdata [383] "logic tdata[511:0]" +Toggle 1to0 tdata [383] "logic tdata[511:0]" +Toggle 0to1 tdata [384] "logic tdata[511:0]" +Toggle 1to0 tdata [384] "logic tdata[511:0]" +Toggle 0to1 tdata [385] "logic tdata[511:0]" +Toggle 1to0 tdata [385] "logic tdata[511:0]" +Toggle 0to1 tdata [386] "logic tdata[511:0]" +Toggle 1to0 tdata [386] "logic tdata[511:0]" +Toggle 0to1 tdata [387] "logic tdata[511:0]" +Toggle 1to0 tdata [387] "logic tdata[511:0]" +Toggle 0to1 tdata [388] "logic tdata[511:0]" +Toggle 1to0 tdata [388] "logic tdata[511:0]" +Toggle 0to1 tdata [389] "logic tdata[511:0]" +Toggle 1to0 tdata [389] "logic tdata[511:0]" +Toggle 0to1 tdata [390] "logic tdata[511:0]" +Toggle 1to0 tdata [390] "logic tdata[511:0]" +Toggle 0to1 tdata [391] "logic tdata[511:0]" +Toggle 1to0 tdata [391] "logic tdata[511:0]" +Toggle 0to1 tdata [392] "logic tdata[511:0]" +Toggle 1to0 tdata [392] "logic tdata[511:0]" +Toggle 0to1 tdata [393] "logic tdata[511:0]" +Toggle 1to0 tdata [393] "logic tdata[511:0]" +Toggle 0to1 tdata [394] "logic tdata[511:0]" +Toggle 1to0 tdata [394] "logic tdata[511:0]" +Toggle 0to1 tdata [395] "logic tdata[511:0]" +Toggle 1to0 tdata [395] "logic tdata[511:0]" +Toggle 0to1 tdata [396] "logic tdata[511:0]" +Toggle 1to0 tdata [396] "logic tdata[511:0]" +Toggle 0to1 tdata [397] "logic tdata[511:0]" +Toggle 1to0 tdata [397] "logic tdata[511:0]" +Toggle 0to1 tdata [398] "logic tdata[511:0]" +Toggle 1to0 tdata [398] "logic tdata[511:0]" +Toggle 0to1 tdata [399] "logic tdata[511:0]" +Toggle 1to0 tdata [399] "logic tdata[511:0]" +Toggle 0to1 tdata [400] "logic tdata[511:0]" +Toggle 1to0 tdata [400] "logic tdata[511:0]" +Toggle 0to1 tdata [401] "logic tdata[511:0]" +Toggle 1to0 tdata [401] "logic tdata[511:0]" +Toggle 0to1 tdata [402] "logic tdata[511:0]" +Toggle 1to0 tdata [402] "logic tdata[511:0]" +Toggle 0to1 tdata [403] "logic tdata[511:0]" +Toggle 1to0 tdata [403] "logic tdata[511:0]" +Toggle 0to1 tdata [404] "logic tdata[511:0]" +Toggle 1to0 tdata [404] "logic tdata[511:0]" +Toggle 0to1 tdata [405] "logic tdata[511:0]" +Toggle 1to0 tdata [405] "logic tdata[511:0]" +Toggle 0to1 tdata [406] "logic tdata[511:0]" +Toggle 1to0 tdata [406] "logic tdata[511:0]" +Toggle 0to1 tdata [407] "logic tdata[511:0]" +Toggle 1to0 tdata [407] "logic tdata[511:0]" +Toggle 0to1 tdata [408] "logic tdata[511:0]" +Toggle 1to0 tdata [408] "logic tdata[511:0]" +Toggle 0to1 tdata [409] "logic tdata[511:0]" +Toggle 1to0 tdata [409] "logic tdata[511:0]" +Toggle 0to1 tdata [410] "logic tdata[511:0]" +Toggle 1to0 tdata [410] "logic tdata[511:0]" +Toggle 0to1 tdata [411] "logic tdata[511:0]" +Toggle 1to0 tdata [411] "logic tdata[511:0]" +Toggle 0to1 tdata [412] "logic tdata[511:0]" +Toggle 1to0 tdata [412] "logic tdata[511:0]" +Toggle 0to1 tdata [413] "logic tdata[511:0]" +Toggle 1to0 tdata [413] "logic tdata[511:0]" +Toggle 0to1 tdata [414] "logic tdata[511:0]" +Toggle 1to0 tdata [414] "logic tdata[511:0]" +Toggle 0to1 tdata [415] "logic tdata[511:0]" +Toggle 1to0 tdata [415] "logic tdata[511:0]" +Toggle 0to1 tdata [416] "logic tdata[511:0]" +Toggle 1to0 tdata [416] "logic tdata[511:0]" +Toggle 0to1 tdata [417] "logic tdata[511:0]" +Toggle 1to0 tdata [417] "logic tdata[511:0]" +Toggle 0to1 tdata [418] "logic tdata[511:0]" +Toggle 1to0 tdata [418] "logic tdata[511:0]" +Toggle 0to1 tdata [419] "logic tdata[511:0]" +Toggle 1to0 tdata [419] "logic tdata[511:0]" +Toggle 0to1 tdata [420] "logic tdata[511:0]" +Toggle 1to0 tdata [420] "logic tdata[511:0]" +Toggle 0to1 tdata [421] "logic tdata[511:0]" +Toggle 1to0 tdata [421] "logic tdata[511:0]" +Toggle 0to1 tdata [422] "logic tdata[511:0]" +Toggle 1to0 tdata [422] "logic tdata[511:0]" +Toggle 0to1 tdata [423] "logic tdata[511:0]" +Toggle 1to0 tdata [423] "logic tdata[511:0]" +Toggle 0to1 tdata [424] "logic tdata[511:0]" +Toggle 1to0 tdata [424] "logic tdata[511:0]" +Toggle 0to1 tdata [425] "logic tdata[511:0]" +Toggle 1to0 tdata [425] "logic tdata[511:0]" +Toggle 0to1 tdata [426] "logic tdata[511:0]" +Toggle 1to0 tdata [426] "logic tdata[511:0]" +Toggle 0to1 tdata [427] "logic tdata[511:0]" +Toggle 1to0 tdata [427] "logic tdata[511:0]" +Toggle 0to1 tdata [428] "logic tdata[511:0]" +Toggle 1to0 tdata [428] "logic tdata[511:0]" +Toggle 0to1 tdata [429] "logic tdata[511:0]" +Toggle 1to0 tdata [429] "logic tdata[511:0]" +Toggle 0to1 tdata [430] "logic tdata[511:0]" +Toggle 1to0 tdata [430] "logic tdata[511:0]" +Toggle 0to1 tdata [431] "logic tdata[511:0]" +Toggle 1to0 tdata [431] "logic tdata[511:0]" +Toggle 0to1 tdata [432] "logic tdata[511:0]" +Toggle 1to0 tdata [432] "logic tdata[511:0]" +Toggle 0to1 tdata [433] "logic tdata[511:0]" +Toggle 1to0 tdata [433] "logic tdata[511:0]" +Toggle 0to1 tdata [434] "logic tdata[511:0]" +Toggle 1to0 tdata [434] "logic tdata[511:0]" +Toggle 0to1 tdata [435] "logic tdata[511:0]" +Toggle 1to0 tdata [435] "logic tdata[511:0]" +Toggle 0to1 tdata [436] "logic tdata[511:0]" +Toggle 1to0 tdata [436] "logic tdata[511:0]" +Toggle 0to1 tdata [437] "logic tdata[511:0]" +Toggle 1to0 tdata [437] "logic tdata[511:0]" +Toggle 0to1 tdata [438] "logic tdata[511:0]" +Toggle 1to0 tdata [438] "logic tdata[511:0]" +Toggle 0to1 tdata [439] "logic tdata[511:0]" +Toggle 1to0 tdata [439] "logic tdata[511:0]" +Toggle 0to1 tdata [440] "logic tdata[511:0]" +Toggle 1to0 tdata [440] "logic tdata[511:0]" +Toggle 0to1 tdata [441] "logic tdata[511:0]" +Toggle 1to0 tdata [441] "logic tdata[511:0]" +Toggle 0to1 tdata [442] "logic tdata[511:0]" +Toggle 1to0 tdata [442] "logic tdata[511:0]" +Toggle 0to1 tdata [443] "logic tdata[511:0]" +Toggle 1to0 tdata [443] "logic tdata[511:0]" +Toggle 0to1 tdata [444] "logic tdata[511:0]" +Toggle 1to0 tdata [444] "logic tdata[511:0]" +Toggle 0to1 tdata [445] "logic tdata[511:0]" +Toggle 1to0 tdata [445] "logic tdata[511:0]" +Toggle 0to1 tdata [446] "logic tdata[511:0]" +Toggle 1to0 tdata [446] "logic tdata[511:0]" +Toggle 0to1 tdata [447] "logic tdata[511:0]" +Toggle 1to0 tdata [447] "logic tdata[511:0]" +Toggle 0to1 tdata [448] "logic tdata[511:0]" +Toggle 1to0 tdata [448] "logic tdata[511:0]" +Toggle 0to1 tdata [449] "logic tdata[511:0]" +Toggle 1to0 tdata [449] "logic tdata[511:0]" +Toggle 0to1 tdata [450] "logic tdata[511:0]" +Toggle 1to0 tdata [450] "logic tdata[511:0]" +Toggle 0to1 tdata [451] "logic tdata[511:0]" +Toggle 1to0 tdata [451] "logic tdata[511:0]" +Toggle 0to1 tdata [452] "logic tdata[511:0]" +Toggle 1to0 tdata [452] "logic tdata[511:0]" +Toggle 0to1 tdata [453] "logic tdata[511:0]" +Toggle 1to0 tdata [453] "logic tdata[511:0]" +Toggle 0to1 tdata [454] "logic tdata[511:0]" +Toggle 1to0 tdata [454] "logic tdata[511:0]" +Toggle 0to1 tdata [455] "logic tdata[511:0]" +Toggle 1to0 tdata [455] "logic tdata[511:0]" +Toggle 0to1 tdata [456] "logic tdata[511:0]" +Toggle 1to0 tdata [456] "logic tdata[511:0]" +Toggle 0to1 tdata [457] "logic tdata[511:0]" +Toggle 1to0 tdata [457] "logic tdata[511:0]" +Toggle 0to1 tdata [458] "logic tdata[511:0]" +Toggle 1to0 tdata [458] "logic tdata[511:0]" +Toggle 0to1 tdata [459] "logic tdata[511:0]" +Toggle 1to0 tdata [459] "logic tdata[511:0]" +Toggle 0to1 tdata [460] "logic tdata[511:0]" +Toggle 1to0 tdata [460] "logic tdata[511:0]" +Toggle 0to1 tdata [461] "logic tdata[511:0]" +Toggle 1to0 tdata [461] "logic tdata[511:0]" +Toggle 0to1 tdata [462] "logic tdata[511:0]" +Toggle 1to0 tdata [462] "logic tdata[511:0]" +Toggle 0to1 tdata [463] "logic tdata[511:0]" +Toggle 1to0 tdata [463] "logic tdata[511:0]" +Toggle 0to1 tdata [464] "logic tdata[511:0]" +Toggle 1to0 tdata [464] "logic tdata[511:0]" +Toggle 0to1 tdata [465] "logic tdata[511:0]" +Toggle 1to0 tdata [465] "logic tdata[511:0]" +Toggle 0to1 tdata [466] "logic tdata[511:0]" +Toggle 1to0 tdata [466] "logic tdata[511:0]" +Toggle 0to1 tdata [467] "logic tdata[511:0]" +Toggle 1to0 tdata [467] "logic tdata[511:0]" +Toggle 0to1 tdata [468] "logic tdata[511:0]" +Toggle 1to0 tdata [468] "logic tdata[511:0]" +Toggle 0to1 tdata [469] "logic tdata[511:0]" +Toggle 1to0 tdata [469] "logic tdata[511:0]" +Toggle 0to1 tdata [470] "logic tdata[511:0]" +Toggle 1to0 tdata [470] "logic tdata[511:0]" +Toggle 0to1 tdata [471] "logic tdata[511:0]" +Toggle 1to0 tdata [471] "logic tdata[511:0]" +Toggle 0to1 tdata [472] "logic tdata[511:0]" +Toggle 1to0 tdata [472] "logic tdata[511:0]" +Toggle 0to1 tdata [473] "logic tdata[511:0]" +Toggle 1to0 tdata [473] "logic tdata[511:0]" +Toggle 0to1 tdata [474] "logic tdata[511:0]" +Toggle 1to0 tdata [474] "logic tdata[511:0]" +Toggle 0to1 tdata [475] "logic tdata[511:0]" +Toggle 1to0 tdata [475] "logic tdata[511:0]" +Toggle 0to1 tdata [476] "logic tdata[511:0]" +Toggle 1to0 tdata [476] "logic tdata[511:0]" +Toggle 0to1 tdata [477] "logic tdata[511:0]" +Toggle 1to0 tdata [477] "logic tdata[511:0]" +Toggle 0to1 tdata [478] "logic tdata[511:0]" +Toggle 1to0 tdata [478] "logic tdata[511:0]" +Toggle 0to1 tdata [479] "logic tdata[511:0]" +Toggle 1to0 tdata [479] "logic tdata[511:0]" +Toggle 0to1 tdata [480] "logic tdata[511:0]" +Toggle 1to0 tdata [480] "logic tdata[511:0]" +Toggle 0to1 tdata [481] "logic tdata[511:0]" +Toggle 1to0 tdata [481] "logic tdata[511:0]" +Toggle 0to1 tdata [482] "logic tdata[511:0]" +Toggle 1to0 tdata [482] "logic tdata[511:0]" +Toggle 0to1 tdata [483] "logic tdata[511:0]" +Toggle 1to0 tdata [483] "logic tdata[511:0]" +Toggle 0to1 tdata [484] "logic tdata[511:0]" +Toggle 1to0 tdata [484] "logic tdata[511:0]" +Toggle 0to1 tdata [485] "logic tdata[511:0]" +Toggle 1to0 tdata [485] "logic tdata[511:0]" +Toggle 0to1 tdata [486] "logic tdata[511:0]" +Toggle 1to0 tdata [486] "logic tdata[511:0]" +Toggle 0to1 tdata [487] "logic tdata[511:0]" +Toggle 1to0 tdata [487] "logic tdata[511:0]" +Toggle 0to1 tdata [488] "logic tdata[511:0]" +Toggle 1to0 tdata [488] "logic tdata[511:0]" +Toggle 0to1 tdata [489] "logic tdata[511:0]" +Toggle 1to0 tdata [489] "logic tdata[511:0]" +Toggle 0to1 tdata [490] "logic tdata[511:0]" +Toggle 1to0 tdata [490] "logic tdata[511:0]" +Toggle 0to1 tdata [491] "logic tdata[511:0]" +Toggle 1to0 tdata [491] "logic tdata[511:0]" +Toggle 0to1 tdata [492] "logic tdata[511:0]" +Toggle 1to0 tdata [492] "logic tdata[511:0]" +Toggle 0to1 tdata [493] "logic tdata[511:0]" +Toggle 1to0 tdata [493] "logic tdata[511:0]" +Toggle 0to1 tdata [494] "logic tdata[511:0]" +Toggle 1to0 tdata [494] "logic tdata[511:0]" +Toggle 0to1 tdata [495] "logic tdata[511:0]" +Toggle 1to0 tdata [495] "logic tdata[511:0]" +Toggle 0to1 tdata [496] "logic tdata[511:0]" +Toggle 1to0 tdata [496] "logic tdata[511:0]" +Toggle 0to1 tdata [497] "logic tdata[511:0]" +Toggle 1to0 tdata [497] "logic tdata[511:0]" +Toggle 0to1 tdata [498] "logic tdata[511:0]" +Toggle 1to0 tdata [498] "logic tdata[511:0]" +Toggle 0to1 tdata [499] "logic tdata[511:0]" +Toggle 1to0 tdata [499] "logic tdata[511:0]" +Toggle 0to1 tdata [500] "logic tdata[511:0]" +Toggle 1to0 tdata [500] "logic tdata[511:0]" +Toggle 0to1 tdata [501] "logic tdata[511:0]" +Toggle 1to0 tdata [501] "logic tdata[511:0]" +Toggle 0to1 tdata [502] "logic tdata[511:0]" +Toggle 1to0 tdata [502] "logic tdata[511:0]" +Toggle 0to1 tdata [503] "logic tdata[511:0]" +Toggle 1to0 tdata [503] "logic tdata[511:0]" +Toggle 0to1 tdata [504] "logic tdata[511:0]" +Toggle 1to0 tdata [504] "logic tdata[511:0]" +Toggle 0to1 tdata [505] "logic tdata[511:0]" +Toggle 1to0 tdata [505] "logic tdata[511:0]" +Toggle 0to1 tdata [506] "logic tdata[511:0]" +Toggle 1to0 tdata [506] "logic tdata[511:0]" +Toggle 0to1 tdata [507] "logic tdata[511:0]" +Toggle 1to0 tdata [507] "logic tdata[511:0]" +Toggle 0to1 tdata [508] "logic tdata[511:0]" +Toggle 1to0 tdata [508] "logic tdata[511:0]" +Toggle 0to1 tdata [509] "logic tdata[511:0]" +Toggle 1to0 tdata [509] "logic tdata[511:0]" +Toggle 0to1 tdata [510] "logic tdata[511:0]" +Toggle 1to0 tdata [510] "logic tdata[511:0]" +Toggle 1to0 tdata [174] "logic tdata[511:0]" +Toggle 1to0 tdata [1] "logic tdata[511:0]" +Toggle 1to0 tdata [25] "logic tdata[511:0]" +Toggle 1to0 tdata [27] "logic tdata[511:0]" +Toggle 1to0 tdata [30] "logic tdata[511:0]" +Toggle 1to0 tdata [35] "logic tdata[511:0]" +Toggle 1to0 tdata [51] "logic tdata[511:0]" +Toggle 1to0 tdata [53] "logic tdata[511:0]" +Toggle 1to0 tdata [80] "logic tdata[511:0]" +Toggle 1to0 tdata [164] "logic tdata[511:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_tx_a_if_t0[0] +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_tx_a_if_t0[1] +Toggle 0to1 tdata [511] "logic tdata[511:0]" +Toggle 1to0 tdata [511] "logic tdata[511:0]" +Toggle 0to1 tdata [320] "logic tdata[511:0]" +Toggle 1to0 tdata [320] "logic tdata[511:0]" +Toggle 0to1 tdata [321] "logic tdata[511:0]" +Toggle 1to0 tdata [321] "logic tdata[511:0]" +Toggle 0to1 tdata [322] "logic tdata[511:0]" +Toggle 1to0 tdata [322] "logic tdata[511:0]" +Toggle 0to1 tdata [323] "logic tdata[511:0]" +Toggle 1to0 tdata [323] "logic tdata[511:0]" +Toggle 0to1 tdata [324] "logic tdata[511:0]" +Toggle 1to0 tdata [324] "logic tdata[511:0]" +Toggle 0to1 tdata [325] "logic tdata[511:0]" +Toggle 1to0 tdata [325] "logic tdata[511:0]" +Toggle 0to1 tdata [326] "logic tdata[511:0]" +Toggle 1to0 tdata [326] "logic tdata[511:0]" +Toggle 0to1 tdata [327] "logic tdata[511:0]" +Toggle 1to0 tdata [327] "logic tdata[511:0]" +Toggle 0to1 tdata [328] "logic tdata[511:0]" +Toggle 1to0 tdata [328] "logic tdata[511:0]" +Toggle 0to1 tdata [329] "logic tdata[511:0]" +Toggle 1to0 tdata [329] "logic tdata[511:0]" +Toggle 0to1 tdata [330] "logic tdata[511:0]" +Toggle 1to0 tdata [330] "logic tdata[511:0]" +Toggle 0to1 tdata [331] "logic tdata[511:0]" +Toggle 1to0 tdata [331] "logic tdata[511:0]" +Toggle 0to1 tdata [332] "logic tdata[511:0]" +Toggle 1to0 tdata [332] "logic tdata[511:0]" +Toggle 0to1 tdata [333] "logic tdata[511:0]" +Toggle 1to0 tdata [333] "logic tdata[511:0]" +Toggle 0to1 tdata [334] "logic tdata[511:0]" +Toggle 1to0 tdata [334] "logic tdata[511:0]" +Toggle 0to1 tdata [335] "logic tdata[511:0]" +Toggle 1to0 tdata [335] "logic tdata[511:0]" +Toggle 0to1 tdata [336] "logic tdata[511:0]" +Toggle 1to0 tdata [336] "logic tdata[511:0]" +Toggle 0to1 tdata [337] "logic tdata[511:0]" +Toggle 1to0 tdata [337] "logic tdata[511:0]" +Toggle 0to1 tdata [338] "logic tdata[511:0]" +Toggle 1to0 tdata [338] "logic tdata[511:0]" +Toggle 0to1 tdata [339] "logic tdata[511:0]" +Toggle 1to0 tdata [339] "logic tdata[511:0]" +Toggle 0to1 tdata [340] "logic tdata[511:0]" +Toggle 1to0 tdata [340] "logic tdata[511:0]" +Toggle 0to1 tdata [341] "logic tdata[511:0]" +Toggle 1to0 tdata [341] "logic tdata[511:0]" +Toggle 0to1 tdata [342] "logic tdata[511:0]" +Toggle 1to0 tdata [342] "logic tdata[511:0]" +Toggle 0to1 tdata [343] "logic tdata[511:0]" +Toggle 1to0 tdata [343] "logic tdata[511:0]" +Toggle 0to1 tdata [344] "logic tdata[511:0]" +Toggle 1to0 tdata [344] "logic tdata[511:0]" +Toggle 0to1 tdata [345] "logic tdata[511:0]" +Toggle 1to0 tdata [345] "logic tdata[511:0]" +Toggle 0to1 tdata [346] "logic tdata[511:0]" +Toggle 1to0 tdata [346] "logic tdata[511:0]" +Toggle 0to1 tdata [347] "logic tdata[511:0]" +Toggle 1to0 tdata [347] "logic tdata[511:0]" +Toggle 0to1 tdata [348] "logic tdata[511:0]" +Toggle 1to0 tdata [348] "logic tdata[511:0]" +Toggle 0to1 tdata [349] "logic tdata[511:0]" +Toggle 1to0 tdata [349] "logic tdata[511:0]" +Toggle 0to1 tdata [350] "logic tdata[511:0]" +Toggle 1to0 tdata [350] "logic tdata[511:0]" +Toggle 0to1 tdata [351] "logic tdata[511:0]" +Toggle 1to0 tdata [351] "logic tdata[511:0]" +Toggle 0to1 tdata [352] "logic tdata[511:0]" +Toggle 1to0 tdata [352] "logic tdata[511:0]" +Toggle 0to1 tdata [353] "logic tdata[511:0]" +Toggle 1to0 tdata [353] "logic tdata[511:0]" +Toggle 0to1 tdata [354] "logic tdata[511:0]" +Toggle 1to0 tdata [354] "logic tdata[511:0]" +Toggle 0to1 tdata [355] "logic tdata[511:0]" +Toggle 1to0 tdata [355] "logic tdata[511:0]" +Toggle 0to1 tdata [356] "logic tdata[511:0]" +Toggle 1to0 tdata [356] "logic tdata[511:0]" +Toggle 0to1 tdata [357] "logic tdata[511:0]" +Toggle 1to0 tdata [357] "logic tdata[511:0]" +Toggle 0to1 tdata [358] "logic tdata[511:0]" +Toggle 1to0 tdata [358] "logic tdata[511:0]" +Toggle 0to1 tdata [359] "logic tdata[511:0]" +Toggle 1to0 tdata [359] "logic tdata[511:0]" +Toggle 0to1 tdata [360] "logic tdata[511:0]" +Toggle 1to0 tdata [360] "logic tdata[511:0]" +Toggle 0to1 tdata [361] "logic tdata[511:0]" +Toggle 1to0 tdata [361] "logic tdata[511:0]" +Toggle 0to1 tdata [362] "logic tdata[511:0]" +Toggle 1to0 tdata [362] "logic tdata[511:0]" +Toggle 0to1 tdata [363] "logic tdata[511:0]" +Toggle 1to0 tdata [363] "logic tdata[511:0]" +Toggle 0to1 tdata [364] "logic tdata[511:0]" +Toggle 1to0 tdata [364] "logic tdata[511:0]" +Toggle 0to1 tdata [365] "logic tdata[511:0]" +Toggle 1to0 tdata [365] "logic tdata[511:0]" +Toggle 0to1 tdata [366] "logic tdata[511:0]" +Toggle 1to0 tdata [366] "logic tdata[511:0]" +Toggle 0to1 tdata [367] "logic tdata[511:0]" +Toggle 1to0 tdata [367] "logic tdata[511:0]" +Toggle 0to1 tdata [368] "logic tdata[511:0]" +Toggle 1to0 tdata [368] "logic tdata[511:0]" +Toggle 0to1 tdata [369] "logic tdata[511:0]" +Toggle 1to0 tdata [369] "logic tdata[511:0]" +Toggle 0to1 tdata [370] "logic tdata[511:0]" +Toggle 1to0 tdata [370] "logic tdata[511:0]" +Toggle 0to1 tdata [371] "logic tdata[511:0]" +Toggle 1to0 tdata [371] "logic tdata[511:0]" +Toggle 0to1 tdata [372] "logic tdata[511:0]" +Toggle 1to0 tdata [372] "logic tdata[511:0]" +Toggle 0to1 tdata [373] "logic tdata[511:0]" +Toggle 1to0 tdata [373] "logic tdata[511:0]" +Toggle 0to1 tdata [374] "logic tdata[511:0]" +Toggle 1to0 tdata [374] "logic tdata[511:0]" +Toggle 0to1 tdata [375] "logic tdata[511:0]" +Toggle 1to0 tdata [375] "logic tdata[511:0]" +Toggle 0to1 tdata [376] "logic tdata[511:0]" +Toggle 1to0 tdata [376] "logic tdata[511:0]" +Toggle 0to1 tdata [377] "logic tdata[511:0]" +Toggle 1to0 tdata [377] "logic tdata[511:0]" +Toggle 0to1 tdata [378] "logic tdata[511:0]" +Toggle 1to0 tdata [378] "logic tdata[511:0]" +Toggle 0to1 tdata [379] "logic tdata[511:0]" +Toggle 1to0 tdata [379] "logic tdata[511:0]" +Toggle 0to1 tdata [380] "logic tdata[511:0]" +Toggle 1to0 tdata [380] "logic tdata[511:0]" +Toggle 0to1 tdata [381] "logic tdata[511:0]" +Toggle 1to0 tdata [381] "logic tdata[511:0]" +Toggle 0to1 tdata [382] "logic tdata[511:0]" +Toggle 1to0 tdata [382] "logic tdata[511:0]" +Toggle 0to1 tdata [383] "logic tdata[511:0]" +Toggle 1to0 tdata [383] "logic tdata[511:0]" +Toggle 0to1 tdata [384] "logic tdata[511:0]" +Toggle 1to0 tdata [384] "logic tdata[511:0]" +Toggle 0to1 tdata [385] "logic tdata[511:0]" +Toggle 1to0 tdata [385] "logic tdata[511:0]" +Toggle 0to1 tdata [386] "logic tdata[511:0]" +Toggle 1to0 tdata [386] "logic tdata[511:0]" +Toggle 0to1 tdata [387] "logic tdata[511:0]" +Toggle 1to0 tdata [387] "logic tdata[511:0]" +Toggle 0to1 tdata [388] "logic tdata[511:0]" +Toggle 1to0 tdata [388] "logic tdata[511:0]" +Toggle 0to1 tdata [389] "logic tdata[511:0]" +Toggle 1to0 tdata [389] "logic tdata[511:0]" +Toggle 0to1 tdata [390] "logic tdata[511:0]" +Toggle 1to0 tdata [390] "logic tdata[511:0]" +Toggle 0to1 tdata [391] "logic tdata[511:0]" +Toggle 1to0 tdata [391] "logic tdata[511:0]" +Toggle 0to1 tdata [392] "logic tdata[511:0]" +Toggle 1to0 tdata [392] "logic tdata[511:0]" +Toggle 0to1 tdata [393] "logic tdata[511:0]" +Toggle 1to0 tdata [393] "logic tdata[511:0]" +Toggle 0to1 tdata [394] "logic tdata[511:0]" +Toggle 1to0 tdata [394] "logic tdata[511:0]" +Toggle 0to1 tdata [395] "logic tdata[511:0]" +Toggle 1to0 tdata [395] "logic tdata[511:0]" +Toggle 0to1 tdata [396] "logic tdata[511:0]" +Toggle 1to0 tdata [396] "logic tdata[511:0]" +Toggle 0to1 tdata [397] "logic tdata[511:0]" +Toggle 1to0 tdata [397] "logic tdata[511:0]" +Toggle 0to1 tdata [398] "logic tdata[511:0]" +Toggle 1to0 tdata [398] "logic tdata[511:0]" +Toggle 0to1 tdata [399] "logic tdata[511:0]" +Toggle 1to0 tdata [399] "logic tdata[511:0]" +Toggle 0to1 tdata [400] "logic tdata[511:0]" +Toggle 1to0 tdata [400] "logic tdata[511:0]" +Toggle 0to1 tdata [401] "logic tdata[511:0]" +Toggle 1to0 tdata [401] "logic tdata[511:0]" +Toggle 0to1 tdata [402] "logic tdata[511:0]" +Toggle 1to0 tdata [402] "logic tdata[511:0]" +Toggle 0to1 tdata [403] "logic tdata[511:0]" +Toggle 1to0 tdata [403] "logic tdata[511:0]" +Toggle 0to1 tdata [404] "logic tdata[511:0]" +Toggle 1to0 tdata [404] "logic tdata[511:0]" +Toggle 0to1 tdata [405] "logic tdata[511:0]" +Toggle 1to0 tdata [405] "logic tdata[511:0]" +Toggle 0to1 tdata [406] "logic tdata[511:0]" +Toggle 1to0 tdata [406] "logic tdata[511:0]" +Toggle 0to1 tdata [407] "logic tdata[511:0]" +Toggle 1to0 tdata [407] "logic tdata[511:0]" +Toggle 0to1 tdata [408] "logic tdata[511:0]" +Toggle 1to0 tdata [408] "logic tdata[511:0]" +Toggle 0to1 tdata [409] "logic tdata[511:0]" +Toggle 1to0 tdata [409] "logic tdata[511:0]" +Toggle 0to1 tdata [410] "logic tdata[511:0]" +Toggle 1to0 tdata [410] "logic tdata[511:0]" +Toggle 0to1 tdata [411] "logic tdata[511:0]" +Toggle 1to0 tdata [411] "logic tdata[511:0]" +Toggle 0to1 tdata [412] "logic tdata[511:0]" +Toggle 1to0 tdata [412] "logic tdata[511:0]" +Toggle 0to1 tdata [413] "logic tdata[511:0]" +Toggle 1to0 tdata [413] "logic tdata[511:0]" +Toggle 0to1 tdata [414] "logic tdata[511:0]" +Toggle 1to0 tdata [414] "logic tdata[511:0]" +Toggle 0to1 tdata [415] "logic tdata[511:0]" +Toggle 1to0 tdata [415] "logic tdata[511:0]" +Toggle 0to1 tdata [416] "logic tdata[511:0]" +Toggle 1to0 tdata [416] "logic tdata[511:0]" +Toggle 0to1 tdata [417] "logic tdata[511:0]" +Toggle 1to0 tdata [417] "logic tdata[511:0]" +Toggle 0to1 tdata [418] "logic tdata[511:0]" +Toggle 1to0 tdata [418] "logic tdata[511:0]" +Toggle 0to1 tdata [419] "logic tdata[511:0]" +Toggle 1to0 tdata [419] "logic tdata[511:0]" +Toggle 0to1 tdata [420] "logic tdata[511:0]" +Toggle 1to0 tdata [420] "logic tdata[511:0]" +Toggle 0to1 tdata [421] "logic tdata[511:0]" +Toggle 1to0 tdata [421] "logic tdata[511:0]" +Toggle 0to1 tdata [422] "logic tdata[511:0]" +Toggle 1to0 tdata [422] "logic tdata[511:0]" +Toggle 0to1 tdata [423] "logic tdata[511:0]" +Toggle 1to0 tdata [423] "logic tdata[511:0]" +Toggle 0to1 tdata [424] "logic tdata[511:0]" +Toggle 1to0 tdata [424] "logic tdata[511:0]" +Toggle 0to1 tdata [425] "logic tdata[511:0]" +Toggle 1to0 tdata [425] "logic tdata[511:0]" +Toggle 0to1 tdata [426] "logic tdata[511:0]" +Toggle 1to0 tdata [426] "logic tdata[511:0]" +Toggle 0to1 tdata [427] "logic tdata[511:0]" +Toggle 1to0 tdata [427] "logic tdata[511:0]" +Toggle 0to1 tdata [428] "logic tdata[511:0]" +Toggle 1to0 tdata [428] "logic tdata[511:0]" +Toggle 0to1 tdata [429] "logic tdata[511:0]" +Toggle 1to0 tdata [429] "logic tdata[511:0]" +Toggle 0to1 tdata [430] "logic tdata[511:0]" +Toggle 1to0 tdata [430] "logic tdata[511:0]" +Toggle 0to1 tdata [431] "logic tdata[511:0]" +Toggle 1to0 tdata [431] "logic tdata[511:0]" +Toggle 0to1 tdata [432] "logic tdata[511:0]" +Toggle 1to0 tdata [432] "logic tdata[511:0]" +Toggle 0to1 tdata [433] "logic tdata[511:0]" +Toggle 1to0 tdata [433] "logic tdata[511:0]" +Toggle 0to1 tdata [434] "logic tdata[511:0]" +Toggle 1to0 tdata [434] "logic tdata[511:0]" +Toggle 0to1 tdata [435] "logic tdata[511:0]" +Toggle 1to0 tdata [435] "logic tdata[511:0]" +Toggle 0to1 tdata [436] "logic tdata[511:0]" +Toggle 1to0 tdata [436] "logic tdata[511:0]" +Toggle 0to1 tdata [437] "logic tdata[511:0]" +Toggle 1to0 tdata [437] "logic tdata[511:0]" +Toggle 0to1 tdata [438] "logic tdata[511:0]" +Toggle 1to0 tdata [438] "logic tdata[511:0]" +Toggle 0to1 tdata [439] "logic tdata[511:0]" +Toggle 1to0 tdata [439] "logic tdata[511:0]" +Toggle 0to1 tdata [440] "logic tdata[511:0]" +Toggle 1to0 tdata [440] "logic tdata[511:0]" +Toggle 0to1 tdata [441] "logic tdata[511:0]" +Toggle 1to0 tdata [441] "logic tdata[511:0]" +Toggle 0to1 tdata [442] "logic tdata[511:0]" +Toggle 1to0 tdata [442] "logic tdata[511:0]" +Toggle 0to1 tdata [443] "logic tdata[511:0]" +Toggle 1to0 tdata [443] "logic tdata[511:0]" +Toggle 0to1 tdata [444] "logic tdata[511:0]" +Toggle 1to0 tdata [444] "logic tdata[511:0]" +Toggle 0to1 tdata [445] "logic tdata[511:0]" +Toggle 1to0 tdata [445] "logic tdata[511:0]" +Toggle 0to1 tdata [446] "logic tdata[511:0]" +Toggle 1to0 tdata [446] "logic tdata[511:0]" +Toggle 0to1 tdata [447] "logic tdata[511:0]" +Toggle 1to0 tdata [447] "logic tdata[511:0]" +Toggle 0to1 tdata [448] "logic tdata[511:0]" +Toggle 1to0 tdata [448] "logic tdata[511:0]" +Toggle 0to1 tdata [449] "logic tdata[511:0]" +Toggle 1to0 tdata [449] "logic tdata[511:0]" +Toggle 0to1 tdata [450] "logic tdata[511:0]" +Toggle 1to0 tdata [450] "logic tdata[511:0]" +Toggle 0to1 tdata [451] "logic tdata[511:0]" +Toggle 1to0 tdata [451] "logic tdata[511:0]" +Toggle 0to1 tdata [452] "logic tdata[511:0]" +Toggle 1to0 tdata [452] "logic tdata[511:0]" +Toggle 0to1 tdata [453] "logic tdata[511:0]" +Toggle 1to0 tdata [453] "logic tdata[511:0]" +Toggle 0to1 tdata [454] "logic tdata[511:0]" +Toggle 1to0 tdata [454] "logic tdata[511:0]" +Toggle 0to1 tdata [455] "logic tdata[511:0]" +Toggle 1to0 tdata [455] "logic tdata[511:0]" +Toggle 0to1 tdata [456] "logic tdata[511:0]" +Toggle 1to0 tdata [456] "logic tdata[511:0]" +Toggle 0to1 tdata [457] "logic tdata[511:0]" +Toggle 1to0 tdata [457] "logic tdata[511:0]" +Toggle 0to1 tdata [458] "logic tdata[511:0]" +Toggle 1to0 tdata [458] "logic tdata[511:0]" +Toggle 0to1 tdata [459] "logic tdata[511:0]" +Toggle 1to0 tdata [459] "logic tdata[511:0]" +Toggle 0to1 tdata [460] "logic tdata[511:0]" +Toggle 1to0 tdata [460] "logic tdata[511:0]" +Toggle 0to1 tdata [461] "logic tdata[511:0]" +Toggle 1to0 tdata [461] "logic tdata[511:0]" +Toggle 0to1 tdata [462] "logic tdata[511:0]" +Toggle 1to0 tdata [462] "logic tdata[511:0]" +Toggle 0to1 tdata [463] "logic tdata[511:0]" +Toggle 1to0 tdata [463] "logic tdata[511:0]" +Toggle 0to1 tdata [464] "logic tdata[511:0]" +Toggle 1to0 tdata [464] "logic tdata[511:0]" +Toggle 0to1 tdata [465] "logic tdata[511:0]" +Toggle 1to0 tdata [465] "logic tdata[511:0]" +Toggle 0to1 tdata [466] "logic tdata[511:0]" +Toggle 1to0 tdata [466] "logic tdata[511:0]" +Toggle 0to1 tdata [467] "logic tdata[511:0]" +Toggle 1to0 tdata [467] "logic tdata[511:0]" +Toggle 0to1 tdata [468] "logic tdata[511:0]" +Toggle 1to0 tdata [468] "logic tdata[511:0]" +Toggle 0to1 tdata [469] "logic tdata[511:0]" +Toggle 1to0 tdata [469] "logic tdata[511:0]" +Toggle 0to1 tdata [470] "logic tdata[511:0]" +Toggle 1to0 tdata [470] "logic tdata[511:0]" +Toggle 0to1 tdata [471] "logic tdata[511:0]" +Toggle 1to0 tdata [471] "logic tdata[511:0]" +Toggle 0to1 tdata [472] "logic tdata[511:0]" +Toggle 1to0 tdata [472] "logic tdata[511:0]" +Toggle 0to1 tdata [473] "logic tdata[511:0]" +Toggle 1to0 tdata [473] "logic tdata[511:0]" +Toggle 0to1 tdata [474] "logic tdata[511:0]" +Toggle 1to0 tdata [474] "logic tdata[511:0]" +Toggle 0to1 tdata [475] "logic tdata[511:0]" +Toggle 1to0 tdata [475] "logic tdata[511:0]" +Toggle 0to1 tdata [476] "logic tdata[511:0]" +Toggle 1to0 tdata [476] "logic tdata[511:0]" +Toggle 0to1 tdata [477] "logic tdata[511:0]" +Toggle 1to0 tdata [477] "logic tdata[511:0]" +Toggle 0to1 tdata [478] "logic tdata[511:0]" +Toggle 1to0 tdata [478] "logic tdata[511:0]" +Toggle 0to1 tdata [479] "logic tdata[511:0]" +Toggle 1to0 tdata [479] "logic tdata[511:0]" +Toggle 0to1 tdata [480] "logic tdata[511:0]" +Toggle 1to0 tdata [480] "logic tdata[511:0]" +Toggle 0to1 tdata [481] "logic tdata[511:0]" +Toggle 1to0 tdata [481] "logic tdata[511:0]" +Toggle 0to1 tdata [482] "logic tdata[511:0]" +Toggle 1to0 tdata [482] "logic tdata[511:0]" +Toggle 0to1 tdata [483] "logic tdata[511:0]" +Toggle 1to0 tdata [483] "logic tdata[511:0]" +Toggle 0to1 tdata [484] "logic tdata[511:0]" +Toggle 1to0 tdata [484] "logic tdata[511:0]" +Toggle 0to1 tdata [485] "logic tdata[511:0]" +Toggle 1to0 tdata [485] "logic tdata[511:0]" +Toggle 0to1 tdata [486] "logic tdata[511:0]" +Toggle 1to0 tdata [486] "logic tdata[511:0]" +Toggle 0to1 tdata [487] "logic tdata[511:0]" +Toggle 1to0 tdata [487] "logic tdata[511:0]" +Toggle 0to1 tdata [488] "logic tdata[511:0]" +Toggle 1to0 tdata [488] "logic tdata[511:0]" +Toggle 0to1 tdata [489] "logic tdata[511:0]" +Toggle 1to0 tdata [489] "logic tdata[511:0]" +Toggle 0to1 tdata [490] "logic tdata[511:0]" +Toggle 1to0 tdata [490] "logic tdata[511:0]" +Toggle 0to1 tdata [491] "logic tdata[511:0]" +Toggle 1to0 tdata [491] "logic tdata[511:0]" +Toggle 0to1 tdata [492] "logic tdata[511:0]" +Toggle 1to0 tdata [492] "logic tdata[511:0]" +Toggle 0to1 tdata [493] "logic tdata[511:0]" +Toggle 1to0 tdata [493] "logic tdata[511:0]" +Toggle 0to1 tdata [494] "logic tdata[511:0]" +Toggle 1to0 tdata [494] "logic tdata[511:0]" +Toggle 0to1 tdata [495] "logic tdata[511:0]" +Toggle 1to0 tdata [495] "logic tdata[511:0]" +Toggle 0to1 tdata [496] "logic tdata[511:0]" +Toggle 1to0 tdata [496] "logic tdata[511:0]" +Toggle 0to1 tdata [497] "logic tdata[511:0]" +Toggle 1to0 tdata [497] "logic tdata[511:0]" +Toggle 0to1 tdata [498] "logic tdata[511:0]" +Toggle 1to0 tdata [498] "logic tdata[511:0]" +Toggle 0to1 tdata [499] "logic tdata[511:0]" +Toggle 1to0 tdata [499] "logic tdata[511:0]" +Toggle 0to1 tdata [500] "logic tdata[511:0]" +Toggle 1to0 tdata [500] "logic tdata[511:0]" +Toggle 0to1 tdata [501] "logic tdata[511:0]" +Toggle 1to0 tdata [501] "logic tdata[511:0]" +Toggle 0to1 tdata [502] "logic tdata[511:0]" +Toggle 1to0 tdata [502] "logic tdata[511:0]" +Toggle 0to1 tdata [503] "logic tdata[511:0]" +Toggle 1to0 tdata [503] "logic tdata[511:0]" +Toggle 0to1 tdata [504] "logic tdata[511:0]" +Toggle 1to0 tdata [504] "logic tdata[511:0]" +Toggle 0to1 tdata [505] "logic tdata[511:0]" +Toggle 1to0 tdata [505] "logic tdata[511:0]" +Toggle 0to1 tdata [506] "logic tdata[511:0]" +Toggle 1to0 tdata [506] "logic tdata[511:0]" +Toggle 0to1 tdata [507] "logic tdata[511:0]" +Toggle 1to0 tdata [507] "logic tdata[511:0]" +Toggle 0to1 tdata [508] "logic tdata[511:0]" +Toggle 1to0 tdata [508] "logic tdata[511:0]" +Toggle 0to1 tdata [509] "logic tdata[511:0]" +Toggle 1to0 tdata [509] "logic tdata[511:0]" +Toggle 0to1 tdata [510] "logic tdata[511:0]" +Toggle 1to0 tdata [510] "logic tdata[511:0]" +Toggle 0to1 tdata [0] "logic tdata[511:0]" +Toggle 1to0 tdata [0] "logic tdata[511:0]" +Toggle 0to1 tdata [24] "logic tdata[511:0]" +Toggle 1to0 tdata [24] "logic tdata[511:0]" +Toggle 0to1 tdata [2] "logic tdata[511:0]" +Toggle 1to0 tdata [2] "logic tdata[511:0]" +Toggle 0to1 tdata [3] "logic tdata[511:0]" +Toggle 1to0 tdata [3] "logic tdata[511:0]" +Toggle 0to1 tdata [4] "logic tdata[511:0]" +Toggle 1to0 tdata [4] "logic tdata[511:0]" +Toggle 0to1 tdata [5] "logic tdata[511:0]" +Toggle 1to0 tdata [5] "logic tdata[511:0]" +Toggle 0to1 tdata [6] "logic tdata[511:0]" +Toggle 1to0 tdata [6] "logic tdata[511:0]" +Toggle 0to1 tdata [7] "logic tdata[511:0]" +Toggle 1to0 tdata [7] "logic tdata[511:0]" +Toggle 0to1 tdata [8] "logic tdata[511:0]" +Toggle 1to0 tdata [8] "logic tdata[511:0]" +Toggle 0to1 tdata [9] "logic tdata[511:0]" +Toggle 1to0 tdata [9] "logic tdata[511:0]" +Toggle 0to1 tdata [10] "logic tdata[511:0]" +Toggle 1to0 tdata [10] "logic tdata[511:0]" +Toggle 0to1 tdata [11] "logic tdata[511:0]" +Toggle 1to0 tdata [11] "logic tdata[511:0]" +Toggle 0to1 tdata [12] "logic tdata[511:0]" +Toggle 1to0 tdata [12] "logic tdata[511:0]" +Toggle 0to1 tdata [13] "logic tdata[511:0]" +Toggle 1to0 tdata [13] "logic tdata[511:0]" +Toggle 0to1 tdata [14] "logic tdata[511:0]" +Toggle 1to0 tdata [14] "logic tdata[511:0]" +Toggle 0to1 tdata [15] "logic tdata[511:0]" +Toggle 1to0 tdata [15] "logic tdata[511:0]" +Toggle 0to1 tdata [16] "logic tdata[511:0]" +Toggle 1to0 tdata [16] "logic tdata[511:0]" +Toggle 0to1 tdata [17] "logic tdata[511:0]" +Toggle 1to0 tdata [17] "logic tdata[511:0]" +Toggle 0to1 tdata [18] "logic tdata[511:0]" +Toggle 1to0 tdata [18] "logic tdata[511:0]" +Toggle 0to1 tdata [19] "logic tdata[511:0]" +Toggle 1to0 tdata [19] "logic tdata[511:0]" +Toggle 0to1 tdata [20] "logic tdata[511:0]" +Toggle 1to0 tdata [20] "logic tdata[511:0]" +Toggle 0to1 tdata [21] "logic tdata[511:0]" +Toggle 1to0 tdata [21] "logic tdata[511:0]" +Toggle 0to1 tdata [22] "logic tdata[511:0]" +Toggle 1to0 tdata [22] "logic tdata[511:0]" +Toggle 0to1 tdata [23] "logic tdata[511:0]" +Toggle 1to0 tdata [23] "logic tdata[511:0]" +Toggle 0to1 tdata [26] "logic tdata[511:0]" +Toggle 1to0 tdata [26] "logic tdata[511:0]" +Toggle 0to1 tdata [29] "logic tdata[511:0]" +Toggle 1to0 tdata [29] "logic tdata[511:0]" +Toggle 0to1 tdata [28] "logic tdata[511:0]" +Toggle 1to0 tdata [28] "logic tdata[511:0]" +Toggle 0to1 tdata [34] "logic tdata[511:0]" +Toggle 1to0 tdata [34] "logic tdata[511:0]" +Toggle 0to1 tdata [31] "logic tdata[511:0]" +Toggle 1to0 tdata [31] "logic tdata[511:0]" +Toggle 0to1 tdata [32] "logic tdata[511:0]" +Toggle 1to0 tdata [32] "logic tdata[511:0]" +Toggle 0to1 tdata [33] "logic tdata[511:0]" +Toggle 1to0 tdata [33] "logic tdata[511:0]" +Toggle 0to1 tdata [50] "logic tdata[511:0]" +Toggle 1to0 tdata [50] "logic tdata[511:0]" +Toggle 0to1 tdata [36] "logic tdata[511:0]" +Toggle 1to0 tdata [36] "logic tdata[511:0]" +Toggle 0to1 tdata [37] "logic tdata[511:0]" +Toggle 1to0 tdata [37] "logic tdata[511:0]" +Toggle 0to1 tdata [38] "logic tdata[511:0]" +Toggle 1to0 tdata [38] "logic tdata[511:0]" +Toggle 0to1 tdata [39] "logic tdata[511:0]" +Toggle 1to0 tdata [39] "logic tdata[511:0]" +Toggle 0to1 tdata [40] "logic tdata[511:0]" +Toggle 1to0 tdata [40] "logic tdata[511:0]" +Toggle 0to1 tdata [41] "logic tdata[511:0]" +Toggle 1to0 tdata [41] "logic tdata[511:0]" +Toggle 0to1 tdata [42] "logic tdata[511:0]" +Toggle 1to0 tdata [42] "logic tdata[511:0]" +Toggle 0to1 tdata [43] "logic tdata[511:0]" +Toggle 1to0 tdata [43] "logic tdata[511:0]" +Toggle 0to1 tdata [44] "logic tdata[511:0]" +Toggle 1to0 tdata [44] "logic tdata[511:0]" +Toggle 0to1 tdata [45] "logic tdata[511:0]" +Toggle 1to0 tdata [45] "logic tdata[511:0]" +Toggle 0to1 tdata [46] "logic tdata[511:0]" +Toggle 1to0 tdata [46] "logic tdata[511:0]" +Toggle 0to1 tdata [47] "logic tdata[511:0]" +Toggle 1to0 tdata [47] "logic tdata[511:0]" +Toggle 0to1 tdata [48] "logic tdata[511:0]" +Toggle 1to0 tdata [48] "logic tdata[511:0]" +Toggle 0to1 tdata [49] "logic tdata[511:0]" +Toggle 1to0 tdata [49] "logic tdata[511:0]" +Toggle 0to1 tdata [66] "logic tdata[511:0]" +Toggle 1to0 tdata [66] "logic tdata[511:0]" +Toggle 0to1 tdata [54] "logic tdata[511:0]" +Toggle 1to0 tdata [54] "logic tdata[511:0]" +Toggle 0to1 tdata [55] "logic tdata[511:0]" +Toggle 1to0 tdata [55] "logic tdata[511:0]" +Toggle 0to1 tdata [56] "logic tdata[511:0]" +Toggle 1to0 tdata [56] "logic tdata[511:0]" +Toggle 0to1 tdata [57] "logic tdata[511:0]" +Toggle 1to0 tdata [57] "logic tdata[511:0]" +Toggle 0to1 tdata [58] "logic tdata[511:0]" +Toggle 1to0 tdata [58] "logic tdata[511:0]" +Toggle 0to1 tdata [59] "logic tdata[511:0]" +Toggle 1to0 tdata [59] "logic tdata[511:0]" +Toggle 0to1 tdata [60] "logic tdata[511:0]" +Toggle 1to0 tdata [60] "logic tdata[511:0]" +Toggle 0to1 tdata [61] "logic tdata[511:0]" +Toggle 1to0 tdata [61] "logic tdata[511:0]" +Toggle 0to1 tdata [62] "logic tdata[511:0]" +Toggle 1to0 tdata [62] "logic tdata[511:0]" +Toggle 0to1 tdata [63] "logic tdata[511:0]" +Toggle 1to0 tdata [63] "logic tdata[511:0]" +Toggle 0to1 tdata [64] "logic tdata[511:0]" +Toggle 1to0 tdata [64] "logic tdata[511:0]" +Toggle 0to1 tdata [65] "logic tdata[511:0]" +Toggle 1to0 tdata [65] "logic tdata[511:0]" +Toggle 0to1 tdata [52] "logic tdata[511:0]" +Toggle 1to0 tdata [52] "logic tdata[511:0]" +Toggle 0to1 tdata [71] "logic tdata[511:0]" +Toggle 1to0 tdata [71] "logic tdata[511:0]" +Toggle 0to1 tdata [79] "logic tdata[511:0]" +Toggle 1to0 tdata [79] "logic tdata[511:0]" +Toggle 0to1 tdata [77] "logic tdata[511:0]" +Toggle 1to0 tdata [77] "logic tdata[511:0]" +Toggle 0to1 tdata [78] "logic tdata[511:0]" +Toggle 1to0 tdata [78] "logic tdata[511:0]" +Toggle 0to1 tdata [163] "logic tdata[511:0]" +Toggle 1to0 tdata [163] "logic tdata[511:0]" +Toggle 0to1 tdata [81] "logic tdata[511:0]" +Toggle 1to0 tdata [81] "logic tdata[511:0]" +Toggle 0to1 tdata [82] "logic tdata[511:0]" +Toggle 1to0 tdata [82] "logic tdata[511:0]" +Toggle 0to1 tdata [83] "logic tdata[511:0]" +Toggle 1to0 tdata [83] "logic tdata[511:0]" +Toggle 0to1 tdata [84] "logic tdata[511:0]" +Toggle 1to0 tdata [84] "logic tdata[511:0]" +Toggle 0to1 tdata [85] "logic tdata[511:0]" +Toggle 1to0 tdata [85] "logic tdata[511:0]" +Toggle 0to1 tdata [86] "logic tdata[511:0]" +Toggle 1to0 tdata [86] "logic tdata[511:0]" +Toggle 0to1 tdata [87] "logic tdata[511:0]" +Toggle 1to0 tdata [87] "logic tdata[511:0]" +Toggle 0to1 tdata [88] "logic tdata[511:0]" +Toggle 1to0 tdata [88] "logic tdata[511:0]" +Toggle 0to1 tdata [89] "logic tdata[511:0]" +Toggle 1to0 tdata [89] "logic tdata[511:0]" +Toggle 0to1 tdata [90] "logic tdata[511:0]" +Toggle 1to0 tdata [90] "logic tdata[511:0]" +Toggle 0to1 tdata [91] "logic tdata[511:0]" +Toggle 1to0 tdata [91] "logic tdata[511:0]" +Toggle 0to1 tdata [92] "logic tdata[511:0]" +Toggle 1to0 tdata [92] "logic tdata[511:0]" +Toggle 0to1 tdata [93] "logic tdata[511:0]" +Toggle 1to0 tdata [93] "logic tdata[511:0]" +Toggle 0to1 tdata [94] "logic tdata[511:0]" +Toggle 1to0 tdata [94] "logic tdata[511:0]" +Toggle 0to1 tdata [95] "logic tdata[511:0]" +Toggle 1to0 tdata [95] "logic tdata[511:0]" +Toggle 0to1 tdata [96] "logic tdata[511:0]" +Toggle 1to0 tdata [96] "logic tdata[511:0]" +Toggle 0to1 tdata [97] "logic tdata[511:0]" +Toggle 1to0 tdata [97] "logic tdata[511:0]" +Toggle 0to1 tdata [98] "logic tdata[511:0]" +Toggle 1to0 tdata [98] "logic tdata[511:0]" +Toggle 0to1 tdata [99] "logic tdata[511:0]" +Toggle 1to0 tdata [99] "logic tdata[511:0]" +Toggle 0to1 tdata [100] "logic tdata[511:0]" +Toggle 1to0 tdata [100] "logic tdata[511:0]" +Toggle 0to1 tdata [101] "logic tdata[511:0]" +Toggle 1to0 tdata [101] "logic tdata[511:0]" +Toggle 0to1 tdata [102] "logic tdata[511:0]" +Toggle 1to0 tdata [102] "logic tdata[511:0]" +Toggle 0to1 tdata [103] "logic tdata[511:0]" +Toggle 1to0 tdata [103] "logic tdata[511:0]" +Toggle 0to1 tdata [104] "logic tdata[511:0]" +Toggle 1to0 tdata [104] "logic tdata[511:0]" +Toggle 0to1 tdata [105] "logic tdata[511:0]" +Toggle 1to0 tdata [105] "logic tdata[511:0]" +Toggle 0to1 tdata [106] "logic tdata[511:0]" +Toggle 1to0 tdata [106] "logic tdata[511:0]" +Toggle 0to1 tdata [107] "logic tdata[511:0]" +Toggle 1to0 tdata [107] "logic tdata[511:0]" +Toggle 0to1 tdata [108] "logic tdata[511:0]" +Toggle 1to0 tdata [108] "logic tdata[511:0]" +Toggle 0to1 tdata [109] "logic tdata[511:0]" +Toggle 1to0 tdata [109] "logic tdata[511:0]" +Toggle 0to1 tdata [110] "logic tdata[511:0]" +Toggle 1to0 tdata [110] "logic tdata[511:0]" +Toggle 0to1 tdata [111] "logic tdata[511:0]" +Toggle 1to0 tdata [111] "logic tdata[511:0]" +Toggle 0to1 tdata [112] "logic tdata[511:0]" +Toggle 1to0 tdata [112] "logic tdata[511:0]" +Toggle 0to1 tdata [113] "logic tdata[511:0]" +Toggle 1to0 tdata [113] "logic tdata[511:0]" +Toggle 0to1 tdata [114] "logic tdata[511:0]" +Toggle 1to0 tdata [114] "logic tdata[511:0]" +Toggle 0to1 tdata [115] "logic tdata[511:0]" +Toggle 1to0 tdata [115] "logic tdata[511:0]" +Toggle 0to1 tdata [116] "logic tdata[511:0]" +Toggle 1to0 tdata [116] "logic tdata[511:0]" +Toggle 0to1 tdata [117] "logic tdata[511:0]" +Toggle 1to0 tdata [117] "logic tdata[511:0]" +Toggle 0to1 tdata [118] "logic tdata[511:0]" +Toggle 1to0 tdata [118] "logic tdata[511:0]" +Toggle 0to1 tdata [119] "logic tdata[511:0]" +Toggle 1to0 tdata [119] "logic tdata[511:0]" +Toggle 0to1 tdata [120] "logic tdata[511:0]" +Toggle 1to0 tdata [120] "logic tdata[511:0]" +Toggle 0to1 tdata [121] "logic tdata[511:0]" +Toggle 1to0 tdata [121] "logic tdata[511:0]" +Toggle 0to1 tdata [122] "logic tdata[511:0]" +Toggle 1to0 tdata [122] "logic tdata[511:0]" +Toggle 0to1 tdata [123] "logic tdata[511:0]" +Toggle 1to0 tdata [123] "logic tdata[511:0]" +Toggle 0to1 tdata [124] "logic tdata[511:0]" +Toggle 1to0 tdata [124] "logic tdata[511:0]" +Toggle 0to1 tdata [125] "logic tdata[511:0]" +Toggle 1to0 tdata [125] "logic tdata[511:0]" +Toggle 0to1 tdata [126] "logic tdata[511:0]" +Toggle 1to0 tdata [126] "logic tdata[511:0]" +Toggle 0to1 tdata [127] "logic tdata[511:0]" +Toggle 1to0 tdata [127] "logic tdata[511:0]" +Toggle 0to1 tdata [128] "logic tdata[511:0]" +Toggle 1to0 tdata [128] "logic tdata[511:0]" +Toggle 0to1 tdata [129] "logic tdata[511:0]" +Toggle 1to0 tdata [129] "logic tdata[511:0]" +Toggle 0to1 tdata [130] "logic tdata[511:0]" +Toggle 1to0 tdata [130] "logic tdata[511:0]" +Toggle 0to1 tdata [131] "logic tdata[511:0]" +Toggle 1to0 tdata [131] "logic tdata[511:0]" +Toggle 0to1 tdata [132] "logic tdata[511:0]" +Toggle 1to0 tdata [132] "logic tdata[511:0]" +Toggle 0to1 tdata [133] "logic tdata[511:0]" +Toggle 1to0 tdata [133] "logic tdata[511:0]" +Toggle 0to1 tdata [134] "logic tdata[511:0]" +Toggle 1to0 tdata [134] "logic tdata[511:0]" +Toggle 0to1 tdata [135] "logic tdata[511:0]" +Toggle 1to0 tdata [135] "logic tdata[511:0]" +Toggle 0to1 tdata [136] "logic tdata[511:0]" +Toggle 1to0 tdata [136] "logic tdata[511:0]" +Toggle 0to1 tdata [137] "logic tdata[511:0]" +Toggle 1to0 tdata [137] "logic tdata[511:0]" +Toggle 0to1 tdata [138] "logic tdata[511:0]" +Toggle 1to0 tdata [138] "logic tdata[511:0]" +Toggle 0to1 tdata [139] "logic tdata[511:0]" +Toggle 1to0 tdata [139] "logic tdata[511:0]" +Toggle 0to1 tdata [140] "logic tdata[511:0]" +Toggle 1to0 tdata [140] "logic tdata[511:0]" +Toggle 0to1 tdata [141] "logic tdata[511:0]" +Toggle 1to0 tdata [141] "logic tdata[511:0]" +Toggle 0to1 tdata [142] "logic tdata[511:0]" +Toggle 1to0 tdata [142] "logic tdata[511:0]" +Toggle 0to1 tdata [143] "logic tdata[511:0]" +Toggle 1to0 tdata [143] "logic tdata[511:0]" +Toggle 0to1 tdata [144] "logic tdata[511:0]" +Toggle 1to0 tdata [144] "logic tdata[511:0]" +Toggle 0to1 tdata [145] "logic tdata[511:0]" +Toggle 1to0 tdata [145] "logic tdata[511:0]" +Toggle 0to1 tdata [146] "logic tdata[511:0]" +Toggle 1to0 tdata [146] "logic tdata[511:0]" +Toggle 0to1 tdata [147] "logic tdata[511:0]" +Toggle 1to0 tdata [147] "logic tdata[511:0]" +Toggle 0to1 tdata [148] "logic tdata[511:0]" +Toggle 1to0 tdata [148] "logic tdata[511:0]" +Toggle 0to1 tdata [149] "logic tdata[511:0]" +Toggle 1to0 tdata [149] "logic tdata[511:0]" +Toggle 0to1 tdata [150] "logic tdata[511:0]" +Toggle 1to0 tdata [150] "logic tdata[511:0]" +Toggle 0to1 tdata [151] "logic tdata[511:0]" +Toggle 1to0 tdata [151] "logic tdata[511:0]" +Toggle 0to1 tdata [152] "logic tdata[511:0]" +Toggle 1to0 tdata [152] "logic tdata[511:0]" +Toggle 0to1 tdata [153] "logic tdata[511:0]" +Toggle 1to0 tdata [153] "logic tdata[511:0]" +Toggle 0to1 tdata [154] "logic tdata[511:0]" +Toggle 1to0 tdata [154] "logic tdata[511:0]" +Toggle 0to1 tdata [155] "logic tdata[511:0]" +Toggle 1to0 tdata [155] "logic tdata[511:0]" +Toggle 0to1 tdata [156] "logic tdata[511:0]" +Toggle 1to0 tdata [156] "logic tdata[511:0]" +Toggle 0to1 tdata [157] "logic tdata[511:0]" +Toggle 1to0 tdata [157] "logic tdata[511:0]" +Toggle 0to1 tdata [158] "logic tdata[511:0]" +Toggle 1to0 tdata [158] "logic tdata[511:0]" +Toggle 0to1 tdata [159] "logic tdata[511:0]" +Toggle 1to0 tdata [159] "logic tdata[511:0]" +Toggle 0to1 tdata [160] "logic tdata[511:0]" +Toggle 1to0 tdata [160] "logic tdata[511:0]" +Toggle 0to1 tdata [161] "logic tdata[511:0]" +Toggle 1to0 tdata [161] "logic tdata[511:0]" +Toggle 0to1 tdata [162] "logic tdata[511:0]" +Toggle 1to0 tdata [162] "logic tdata[511:0]" +Toggle 0to1 tdata [165] "logic tdata[511:0]" +Toggle 1to0 tdata [165] "logic tdata[511:0]" +Toggle 0to1 tdata [166] "logic tdata[511:0]" +Toggle 1to0 tdata [166] "logic tdata[511:0]" +Toggle 0to1 tdata [167] "logic tdata[511:0]" +Toggle 1to0 tdata [167] "logic tdata[511:0]" +Toggle 0to1 tdata [168] "logic tdata[511:0]" +Toggle 1to0 tdata [168] "logic tdata[511:0]" +Toggle 0to1 tdata [169] "logic tdata[511:0]" +Toggle 1to0 tdata [169] "logic tdata[511:0]" +Toggle 0to1 tdata [170] "logic tdata[511:0]" +Toggle 1to0 tdata [170] "logic tdata[511:0]" +Toggle 0to1 tdata [171] "logic tdata[511:0]" +Toggle 1to0 tdata [171] "logic tdata[511:0]" +Toggle 0to1 tdata [172] "logic tdata[511:0]" +Toggle 1to0 tdata [172] "logic tdata[511:0]" +Toggle 0to1 tdata [173] "logic tdata[511:0]" +Toggle 1to0 tdata [173] "logic tdata[511:0]" +Toggle 0to1 tdata [175] "logic tdata[511:0]" +Toggle 1to0 tdata [175] "logic tdata[511:0]" +Toggle 0to1 tdata [176] "logic tdata[511:0]" +Toggle 1to0 tdata [176] "logic tdata[511:0]" +Toggle 0to1 tdata [177] "logic tdata[511:0]" +Toggle 1to0 tdata [177] "logic tdata[511:0]" +Toggle 0to1 tdata [178] "logic tdata[511:0]" +Toggle 1to0 tdata [178] "logic tdata[511:0]" +Toggle 0to1 tdata [179] "logic tdata[511:0]" +Toggle 1to0 tdata [179] "logic tdata[511:0]" +Toggle 0to1 tdata [180] "logic tdata[511:0]" +Toggle 1to0 tdata [180] "logic tdata[511:0]" +Toggle 0to1 tdata [181] "logic tdata[511:0]" +Toggle 1to0 tdata [181] "logic tdata[511:0]" +Toggle 0to1 tdata [182] "logic tdata[511:0]" +Toggle 1to0 tdata [182] "logic tdata[511:0]" +Toggle 0to1 tdata [183] "logic tdata[511:0]" +Toggle 1to0 tdata [183] "logic tdata[511:0]" +Toggle 0to1 tdata [184] "logic tdata[511:0]" +Toggle 1to0 tdata [184] "logic tdata[511:0]" +Toggle 0to1 tdata [185] "logic tdata[511:0]" +Toggle 1to0 tdata [185] "logic tdata[511:0]" +Toggle 0to1 tdata [186] "logic tdata[511:0]" +Toggle 1to0 tdata [186] "logic tdata[511:0]" +Toggle 0to1 tdata [187] "logic tdata[511:0]" +Toggle 1to0 tdata [187] "logic tdata[511:0]" +Toggle 0to1 tdata [188] "logic tdata[511:0]" +Toggle 1to0 tdata [188] "logic tdata[511:0]" +Toggle 0to1 tdata [189] "logic tdata[511:0]" +Toggle 1to0 tdata [189] "logic tdata[511:0]" +Toggle 0to1 tdata [190] "logic tdata[511:0]" +Toggle 1to0 tdata [190] "logic tdata[511:0]" +Toggle 0to1 tdata [191] "logic tdata[511:0]" +Toggle 1to0 tdata [191] "logic tdata[511:0]" +Toggle 0to1 tdata [192] "logic tdata[511:0]" +Toggle 1to0 tdata [192] "logic tdata[511:0]" +Toggle 0to1 tdata [193] "logic tdata[511:0]" +Toggle 1to0 tdata [193] "logic tdata[511:0]" +Toggle 0to1 tdata [194] "logic tdata[511:0]" +Toggle 1to0 tdata [194] "logic tdata[511:0]" +Toggle 0to1 tdata [195] "logic tdata[511:0]" +Toggle 1to0 tdata [195] "logic tdata[511:0]" +Toggle 0to1 tdata [196] "logic tdata[511:0]" +Toggle 1to0 tdata [196] "logic tdata[511:0]" +Toggle 0to1 tdata [197] "logic tdata[511:0]" +Toggle 1to0 tdata [197] "logic tdata[511:0]" +Toggle 0to1 tdata [198] "logic tdata[511:0]" +Toggle 1to0 tdata [198] "logic tdata[511:0]" +Toggle 0to1 tdata [199] "logic tdata[511:0]" +Toggle 1to0 tdata [199] "logic tdata[511:0]" +Toggle 0to1 tdata [200] "logic tdata[511:0]" +Toggle 1to0 tdata [200] "logic tdata[511:0]" +Toggle 0to1 tdata [201] "logic tdata[511:0]" +Toggle 1to0 tdata [201] "logic tdata[511:0]" +Toggle 0to1 tdata [202] "logic tdata[511:0]" +Toggle 1to0 tdata [202] "logic tdata[511:0]" +Toggle 0to1 tdata [203] "logic tdata[511:0]" +Toggle 1to0 tdata [203] "logic tdata[511:0]" +Toggle 0to1 tdata [204] "logic tdata[511:0]" +Toggle 1to0 tdata [204] "logic tdata[511:0]" +Toggle 0to1 tdata [205] "logic tdata[511:0]" +Toggle 1to0 tdata [205] "logic tdata[511:0]" +Toggle 0to1 tdata [206] "logic tdata[511:0]" +Toggle 1to0 tdata [206] "logic tdata[511:0]" +Toggle 0to1 tdata [207] "logic tdata[511:0]" +Toggle 1to0 tdata [207] "logic tdata[511:0]" +Toggle 0to1 tdata [208] "logic tdata[511:0]" +Toggle 1to0 tdata [208] "logic tdata[511:0]" +Toggle 0to1 tdata [209] "logic tdata[511:0]" +Toggle 1to0 tdata [209] "logic tdata[511:0]" +Toggle 0to1 tdata [210] "logic tdata[511:0]" +Toggle 1to0 tdata [210] "logic tdata[511:0]" +Toggle 0to1 tdata [211] "logic tdata[511:0]" +Toggle 1to0 tdata [211] "logic tdata[511:0]" +Toggle 0to1 tdata [212] "logic tdata[511:0]" +Toggle 1to0 tdata [212] "logic tdata[511:0]" +Toggle 0to1 tdata [213] "logic tdata[511:0]" +Toggle 1to0 tdata [213] "logic tdata[511:0]" +Toggle 0to1 tdata [214] "logic tdata[511:0]" +Toggle 1to0 tdata [214] "logic tdata[511:0]" +Toggle 0to1 tdata [215] "logic tdata[511:0]" +Toggle 1to0 tdata [215] "logic tdata[511:0]" +Toggle 0to1 tdata [216] "logic tdata[511:0]" +Toggle 1to0 tdata [216] "logic tdata[511:0]" +Toggle 0to1 tdata [217] "logic tdata[511:0]" +Toggle 1to0 tdata [217] "logic tdata[511:0]" +Toggle 0to1 tdata [218] "logic tdata[511:0]" +Toggle 1to0 tdata [218] "logic tdata[511:0]" +Toggle 0to1 tdata [219] "logic tdata[511:0]" +Toggle 1to0 tdata [219] "logic tdata[511:0]" +Toggle 0to1 tdata [220] "logic tdata[511:0]" +Toggle 1to0 tdata [220] "logic tdata[511:0]" +Toggle 0to1 tdata [221] "logic tdata[511:0]" +Toggle 1to0 tdata [221] "logic tdata[511:0]" +Toggle 0to1 tdata [222] "logic tdata[511:0]" +Toggle 1to0 tdata [222] "logic tdata[511:0]" +Toggle 0to1 tdata [223] "logic tdata[511:0]" +Toggle 1to0 tdata [223] "logic tdata[511:0]" +Toggle 0to1 tdata [224] "logic tdata[511:0]" +Toggle 1to0 tdata [224] "logic tdata[511:0]" +Toggle 0to1 tdata [225] "logic tdata[511:0]" +Toggle 1to0 tdata [225] "logic tdata[511:0]" +Toggle 0to1 tdata [226] "logic tdata[511:0]" +Toggle 1to0 tdata [226] "logic tdata[511:0]" +Toggle 0to1 tdata [227] "logic tdata[511:0]" +Toggle 1to0 tdata [227] "logic tdata[511:0]" +Toggle 0to1 tdata [228] "logic tdata[511:0]" +Toggle 1to0 tdata [228] "logic tdata[511:0]" +Toggle 0to1 tdata [229] "logic tdata[511:0]" +Toggle 1to0 tdata [229] "logic tdata[511:0]" +Toggle 0to1 tdata [230] "logic tdata[511:0]" +Toggle 1to0 tdata [230] "logic tdata[511:0]" +Toggle 0to1 tdata [231] "logic tdata[511:0]" +Toggle 1to0 tdata [231] "logic tdata[511:0]" +Toggle 0to1 tdata [232] "logic tdata[511:0]" +Toggle 1to0 tdata [232] "logic tdata[511:0]" +Toggle 0to1 tdata [233] "logic tdata[511:0]" +Toggle 1to0 tdata [233] "logic tdata[511:0]" +Toggle 0to1 tdata [234] "logic tdata[511:0]" +Toggle 1to0 tdata [234] "logic tdata[511:0]" +Toggle 0to1 tdata [235] "logic tdata[511:0]" +Toggle 1to0 tdata [235] "logic tdata[511:0]" +Toggle 0to1 tdata [236] "logic tdata[511:0]" +Toggle 1to0 tdata [236] "logic tdata[511:0]" +Toggle 0to1 tdata [237] "logic tdata[511:0]" +Toggle 1to0 tdata [237] "logic tdata[511:0]" +Toggle 0to1 tdata [238] "logic tdata[511:0]" +Toggle 1to0 tdata [238] "logic tdata[511:0]" +Toggle 0to1 tdata [239] "logic tdata[511:0]" +Toggle 1to0 tdata [239] "logic tdata[511:0]" +Toggle 0to1 tdata [240] "logic tdata[511:0]" +Toggle 1to0 tdata [240] "logic tdata[511:0]" +Toggle 0to1 tdata [241] "logic tdata[511:0]" +Toggle 1to0 tdata [241] "logic tdata[511:0]" +Toggle 0to1 tdata [242] "logic tdata[511:0]" +Toggle 1to0 tdata [242] "logic tdata[511:0]" +Toggle 0to1 tdata [243] "logic tdata[511:0]" +Toggle 1to0 tdata [243] "logic tdata[511:0]" +Toggle 0to1 tdata [244] "logic tdata[511:0]" +Toggle 1to0 tdata [244] "logic tdata[511:0]" +Toggle 0to1 tdata [245] "logic tdata[511:0]" +Toggle 1to0 tdata [245] "logic tdata[511:0]" +Toggle 0to1 tdata [246] "logic tdata[511:0]" +Toggle 1to0 tdata [246] "logic tdata[511:0]" +Toggle 0to1 tdata [247] "logic tdata[511:0]" +Toggle 1to0 tdata [247] "logic tdata[511:0]" +Toggle 0to1 tdata [248] "logic tdata[511:0]" +Toggle 1to0 tdata [248] "logic tdata[511:0]" +Toggle 0to1 tdata [249] "logic tdata[511:0]" +Toggle 1to0 tdata [249] "logic tdata[511:0]" +Toggle 0to1 tdata [250] "logic tdata[511:0]" +Toggle 1to0 tdata [250] "logic tdata[511:0]" +Toggle 0to1 tdata [251] "logic tdata[511:0]" +Toggle 1to0 tdata [251] "logic tdata[511:0]" +Toggle 0to1 tdata [252] "logic tdata[511:0]" +Toggle 1to0 tdata [252] "logic tdata[511:0]" +Toggle 0to1 tdata [253] "logic tdata[511:0]" +Toggle 1to0 tdata [253] "logic tdata[511:0]" +Toggle 0to1 tdata [254] "logic tdata[511:0]" +Toggle 1to0 tdata [254] "logic tdata[511:0]" +Toggle 0to1 tdata [255] "logic tdata[511:0]" +Toggle 1to0 tdata [255] "logic tdata[511:0]" +Toggle 1to0 tdata [1] "logic tdata[511:0]" +Toggle 1to0 tdata [25] "logic tdata[511:0]" +Toggle 1to0 tdata [27] "logic tdata[511:0]" +Toggle 1to0 tdata [30] "logic tdata[511:0]" +Toggle 1to0 tdata [35] "logic tdata[511:0]" +Toggle 1to0 tdata [51] "logic tdata[511:0]" +Toggle 1to0 tdata [53] "logic tdata[511:0]" +Toggle 1to0 tdata [80] "logic tdata[511:0]" +Toggle 1to0 tdata [164] "logic tdata[511:0]" +Toggle 1to0 tdata [174] "logic tdata[511:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_tx_a_if_t1[0] +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_tx_a_if_t1[1] +Toggle tkeep "logic tkeep[63:0]" +Toggle 0to1 tdata [511] "logic tdata[511:0]" +Toggle 1to0 tdata [511] "logic tdata[511:0]" +Toggle 0to1 tdata [320] "logic tdata[511:0]" +Toggle 1to0 tdata [320] "logic tdata[511:0]" +Toggle 0to1 tdata [321] "logic tdata[511:0]" +Toggle 1to0 tdata [321] "logic tdata[511:0]" +Toggle 0to1 tdata [322] "logic tdata[511:0]" +Toggle 1to0 tdata [322] "logic tdata[511:0]" +Toggle 0to1 tdata [323] "logic tdata[511:0]" +Toggle 1to0 tdata [323] "logic tdata[511:0]" +Toggle 0to1 tdata [324] "logic tdata[511:0]" +Toggle 1to0 tdata [324] "logic tdata[511:0]" +Toggle 0to1 tdata [325] "logic tdata[511:0]" +Toggle 1to0 tdata [325] "logic tdata[511:0]" +Toggle 0to1 tdata [326] "logic tdata[511:0]" +Toggle 1to0 tdata [326] "logic tdata[511:0]" +Toggle 0to1 tdata [327] "logic tdata[511:0]" +Toggle 1to0 tdata [327] "logic tdata[511:0]" +Toggle 0to1 tdata [328] "logic tdata[511:0]" +Toggle 1to0 tdata [328] "logic tdata[511:0]" +Toggle 0to1 tdata [329] "logic tdata[511:0]" +Toggle 1to0 tdata [329] "logic tdata[511:0]" +Toggle 0to1 tdata [330] "logic tdata[511:0]" +Toggle 1to0 tdata [330] "logic tdata[511:0]" +Toggle 0to1 tdata [331] "logic tdata[511:0]" +Toggle 1to0 tdata [331] "logic tdata[511:0]" +Toggle 0to1 tdata [332] "logic tdata[511:0]" +Toggle 1to0 tdata [332] "logic tdata[511:0]" +Toggle 0to1 tdata [333] "logic tdata[511:0]" +Toggle 1to0 tdata [333] "logic tdata[511:0]" +Toggle 0to1 tdata [334] "logic tdata[511:0]" +Toggle 1to0 tdata [334] "logic tdata[511:0]" +Toggle 0to1 tdata [335] "logic tdata[511:0]" +Toggle 1to0 tdata [335] "logic tdata[511:0]" +Toggle 0to1 tdata [336] "logic tdata[511:0]" +Toggle 1to0 tdata [336] "logic tdata[511:0]" +Toggle 0to1 tdata [337] "logic tdata[511:0]" +Toggle 1to0 tdata [337] "logic tdata[511:0]" +Toggle 0to1 tdata [338] "logic tdata[511:0]" +Toggle 1to0 tdata [338] "logic tdata[511:0]" +Toggle 0to1 tdata [339] "logic tdata[511:0]" +Toggle 1to0 tdata [339] "logic tdata[511:0]" +Toggle 0to1 tdata [340] "logic tdata[511:0]" +Toggle 1to0 tdata [340] "logic tdata[511:0]" +Toggle 0to1 tdata [341] "logic tdata[511:0]" +Toggle 1to0 tdata [341] "logic tdata[511:0]" +Toggle 0to1 tdata [342] "logic tdata[511:0]" +Toggle 1to0 tdata [342] "logic tdata[511:0]" +Toggle 0to1 tdata [343] "logic tdata[511:0]" +Toggle 1to0 tdata [343] "logic tdata[511:0]" +Toggle 0to1 tdata [344] "logic tdata[511:0]" +Toggle 1to0 tdata [344] "logic tdata[511:0]" +Toggle 0to1 tdata [345] "logic tdata[511:0]" +Toggle 1to0 tdata [345] "logic tdata[511:0]" +Toggle 0to1 tdata [346] "logic tdata[511:0]" +Toggle 1to0 tdata [346] "logic tdata[511:0]" +Toggle 0to1 tdata [347] "logic tdata[511:0]" +Toggle 1to0 tdata [347] "logic tdata[511:0]" +Toggle 0to1 tdata [348] "logic tdata[511:0]" +Toggle 1to0 tdata [348] "logic tdata[511:0]" +Toggle 0to1 tdata [349] "logic tdata[511:0]" +Toggle 1to0 tdata [349] "logic tdata[511:0]" +Toggle 0to1 tdata [350] "logic tdata[511:0]" +Toggle 1to0 tdata [350] "logic tdata[511:0]" +Toggle 0to1 tdata [351] "logic tdata[511:0]" +Toggle 1to0 tdata [351] "logic tdata[511:0]" +Toggle 0to1 tdata [352] "logic tdata[511:0]" +Toggle 1to0 tdata [352] "logic tdata[511:0]" +Toggle 0to1 tdata [353] "logic tdata[511:0]" +Toggle 1to0 tdata [353] "logic tdata[511:0]" +Toggle 0to1 tdata [354] "logic tdata[511:0]" +Toggle 1to0 tdata [354] "logic tdata[511:0]" +Toggle 0to1 tdata [355] "logic tdata[511:0]" +Toggle 1to0 tdata [355] "logic tdata[511:0]" +Toggle 0to1 tdata [356] "logic tdata[511:0]" +Toggle 1to0 tdata [356] "logic tdata[511:0]" +Toggle 0to1 tdata [357] "logic tdata[511:0]" +Toggle 1to0 tdata [357] "logic tdata[511:0]" +Toggle 0to1 tdata [358] "logic tdata[511:0]" +Toggle 1to0 tdata [358] "logic tdata[511:0]" +Toggle 0to1 tdata [359] "logic tdata[511:0]" +Toggle 1to0 tdata [359] "logic tdata[511:0]" +Toggle 0to1 tdata [360] "logic tdata[511:0]" +Toggle 1to0 tdata [360] "logic tdata[511:0]" +Toggle 0to1 tdata [361] "logic tdata[511:0]" +Toggle 1to0 tdata [361] "logic tdata[511:0]" +Toggle 0to1 tdata [362] "logic tdata[511:0]" +Toggle 1to0 tdata [362] "logic tdata[511:0]" +Toggle 0to1 tdata [363] "logic tdata[511:0]" +Toggle 1to0 tdata [363] "logic tdata[511:0]" +Toggle 0to1 tdata [364] "logic tdata[511:0]" +Toggle 1to0 tdata [364] "logic tdata[511:0]" +Toggle 0to1 tdata [365] "logic tdata[511:0]" +Toggle 1to0 tdata [365] "logic tdata[511:0]" +Toggle 0to1 tdata [366] "logic tdata[511:0]" +Toggle 1to0 tdata [366] "logic tdata[511:0]" +Toggle 0to1 tdata [367] "logic tdata[511:0]" +Toggle 1to0 tdata [367] "logic tdata[511:0]" +Toggle 0to1 tdata [368] "logic tdata[511:0]" +Toggle 1to0 tdata [368] "logic tdata[511:0]" +Toggle 0to1 tdata [369] "logic tdata[511:0]" +Toggle 1to0 tdata [369] "logic tdata[511:0]" +Toggle 0to1 tdata [370] "logic tdata[511:0]" +Toggle 1to0 tdata [370] "logic tdata[511:0]" +Toggle 0to1 tdata [371] "logic tdata[511:0]" +Toggle 1to0 tdata [371] "logic tdata[511:0]" +Toggle 0to1 tdata [372] "logic tdata[511:0]" +Toggle 1to0 tdata [372] "logic tdata[511:0]" +Toggle 0to1 tdata [373] "logic tdata[511:0]" +Toggle 1to0 tdata [373] "logic tdata[511:0]" +Toggle 0to1 tdata [374] "logic tdata[511:0]" +Toggle 1to0 tdata [374] "logic tdata[511:0]" +Toggle 0to1 tdata [375] "logic tdata[511:0]" +Toggle 1to0 tdata [375] "logic tdata[511:0]" +Toggle 0to1 tdata [376] "logic tdata[511:0]" +Toggle 1to0 tdata [376] "logic tdata[511:0]" +Toggle 0to1 tdata [377] "logic tdata[511:0]" +Toggle 1to0 tdata [377] "logic tdata[511:0]" +Toggle 0to1 tdata [378] "logic tdata[511:0]" +Toggle 1to0 tdata [378] "logic tdata[511:0]" +Toggle 0to1 tdata [379] "logic tdata[511:0]" +Toggle 1to0 tdata [379] "logic tdata[511:0]" +Toggle 0to1 tdata [380] "logic tdata[511:0]" +Toggle 1to0 tdata [380] "logic tdata[511:0]" +Toggle 0to1 tdata [381] "logic tdata[511:0]" +Toggle 1to0 tdata [381] "logic tdata[511:0]" +Toggle 0to1 tdata [382] "logic tdata[511:0]" +Toggle 1to0 tdata [382] "logic tdata[511:0]" +Toggle 0to1 tdata [383] "logic tdata[511:0]" +Toggle 1to0 tdata [383] "logic tdata[511:0]" +Toggle 0to1 tdata [384] "logic tdata[511:0]" +Toggle 1to0 tdata [384] "logic tdata[511:0]" +Toggle 0to1 tdata [385] "logic tdata[511:0]" +Toggle 1to0 tdata [385] "logic tdata[511:0]" +Toggle 0to1 tdata [386] "logic tdata[511:0]" +Toggle 1to0 tdata [386] "logic tdata[511:0]" +Toggle 0to1 tdata [387] "logic tdata[511:0]" +Toggle 1to0 tdata [387] "logic tdata[511:0]" +Toggle 0to1 tdata [388] "logic tdata[511:0]" +Toggle 1to0 tdata [388] "logic tdata[511:0]" +Toggle 0to1 tdata [389] "logic tdata[511:0]" +Toggle 1to0 tdata [389] "logic tdata[511:0]" +Toggle 0to1 tdata [390] "logic tdata[511:0]" +Toggle 1to0 tdata [390] "logic tdata[511:0]" +Toggle 0to1 tdata [391] "logic tdata[511:0]" +Toggle 1to0 tdata [391] "logic tdata[511:0]" +Toggle 0to1 tdata [392] "logic tdata[511:0]" +Toggle 1to0 tdata [392] "logic tdata[511:0]" +Toggle 0to1 tdata [393] "logic tdata[511:0]" +Toggle 1to0 tdata [393] "logic tdata[511:0]" +Toggle 0to1 tdata [394] "logic tdata[511:0]" +Toggle 1to0 tdata [394] "logic tdata[511:0]" +Toggle 0to1 tdata [395] "logic tdata[511:0]" +Toggle 1to0 tdata [395] "logic tdata[511:0]" +Toggle 0to1 tdata [396] "logic tdata[511:0]" +Toggle 1to0 tdata [396] "logic tdata[511:0]" +Toggle 0to1 tdata [397] "logic tdata[511:0]" +Toggle 1to0 tdata [397] "logic tdata[511:0]" +Toggle 0to1 tdata [398] "logic tdata[511:0]" +Toggle 1to0 tdata [398] "logic tdata[511:0]" +Toggle 0to1 tdata [399] "logic tdata[511:0]" +Toggle 1to0 tdata [399] "logic tdata[511:0]" +Toggle 0to1 tdata [400] "logic tdata[511:0]" +Toggle 1to0 tdata [400] "logic tdata[511:0]" +Toggle 0to1 tdata [401] "logic tdata[511:0]" +Toggle 1to0 tdata [401] "logic tdata[511:0]" +Toggle 0to1 tdata [402] "logic tdata[511:0]" +Toggle 1to0 tdata [402] "logic tdata[511:0]" +Toggle 0to1 tdata [403] "logic tdata[511:0]" +Toggle 1to0 tdata [403] "logic tdata[511:0]" +Toggle 0to1 tdata [404] "logic tdata[511:0]" +Toggle 1to0 tdata [404] "logic tdata[511:0]" +Toggle 0to1 tdata [405] "logic tdata[511:0]" +Toggle 1to0 tdata [405] "logic tdata[511:0]" +Toggle 0to1 tdata [406] "logic tdata[511:0]" +Toggle 1to0 tdata [406] "logic tdata[511:0]" +Toggle 0to1 tdata [407] "logic tdata[511:0]" +Toggle 1to0 tdata [407] "logic tdata[511:0]" +Toggle 0to1 tdata [408] "logic tdata[511:0]" +Toggle 1to0 tdata [408] "logic tdata[511:0]" +Toggle 0to1 tdata [409] "logic tdata[511:0]" +Toggle 1to0 tdata [409] "logic tdata[511:0]" +Toggle 0to1 tdata [410] "logic tdata[511:0]" +Toggle 1to0 tdata [410] "logic tdata[511:0]" +Toggle 0to1 tdata [411] "logic tdata[511:0]" +Toggle 1to0 tdata [411] "logic tdata[511:0]" +Toggle 0to1 tdata [412] "logic tdata[511:0]" +Toggle 1to0 tdata [412] "logic tdata[511:0]" +Toggle 0to1 tdata [413] "logic tdata[511:0]" +Toggle 1to0 tdata [413] "logic tdata[511:0]" +Toggle 0to1 tdata [414] "logic tdata[511:0]" +Toggle 1to0 tdata [414] "logic tdata[511:0]" +Toggle 0to1 tdata [415] "logic tdata[511:0]" +Toggle 1to0 tdata [415] "logic tdata[511:0]" +Toggle 0to1 tdata [416] "logic tdata[511:0]" +Toggle 1to0 tdata [416] "logic tdata[511:0]" +Toggle 0to1 tdata [417] "logic tdata[511:0]" +Toggle 1to0 tdata [417] "logic tdata[511:0]" +Toggle 0to1 tdata [418] "logic tdata[511:0]" +Toggle 1to0 tdata [418] "logic tdata[511:0]" +Toggle 0to1 tdata [419] "logic tdata[511:0]" +Toggle 1to0 tdata [419] "logic tdata[511:0]" +Toggle 0to1 tdata [420] "logic tdata[511:0]" +Toggle 1to0 tdata [420] "logic tdata[511:0]" +Toggle 0to1 tdata [421] "logic tdata[511:0]" +Toggle 1to0 tdata [421] "logic tdata[511:0]" +Toggle 0to1 tdata [422] "logic tdata[511:0]" +Toggle 1to0 tdata [422] "logic tdata[511:0]" +Toggle 0to1 tdata [423] "logic tdata[511:0]" +Toggle 1to0 tdata [423] "logic tdata[511:0]" +Toggle 0to1 tdata [424] "logic tdata[511:0]" +Toggle 1to0 tdata [424] "logic tdata[511:0]" +Toggle 0to1 tdata [425] "logic tdata[511:0]" +Toggle 1to0 tdata [425] "logic tdata[511:0]" +Toggle 0to1 tdata [426] "logic tdata[511:0]" +Toggle 1to0 tdata [426] "logic tdata[511:0]" +Toggle 0to1 tdata [427] "logic tdata[511:0]" +Toggle 1to0 tdata [427] "logic tdata[511:0]" +Toggle 0to1 tdata [428] "logic tdata[511:0]" +Toggle 1to0 tdata [428] "logic tdata[511:0]" +Toggle 0to1 tdata [429] "logic tdata[511:0]" +Toggle 1to0 tdata [429] "logic tdata[511:0]" +Toggle 0to1 tdata [430] "logic tdata[511:0]" +Toggle 1to0 tdata [430] "logic tdata[511:0]" +Toggle 0to1 tdata [431] "logic tdata[511:0]" +Toggle 1to0 tdata [431] "logic tdata[511:0]" +Toggle 0to1 tdata [432] "logic tdata[511:0]" +Toggle 1to0 tdata [432] "logic tdata[511:0]" +Toggle 0to1 tdata [433] "logic tdata[511:0]" +Toggle 1to0 tdata [433] "logic tdata[511:0]" +Toggle 0to1 tdata [434] "logic tdata[511:0]" +Toggle 1to0 tdata [434] "logic tdata[511:0]" +Toggle 0to1 tdata [435] "logic tdata[511:0]" +Toggle 1to0 tdata [435] "logic tdata[511:0]" +Toggle 0to1 tdata [436] "logic tdata[511:0]" +Toggle 1to0 tdata [436] "logic tdata[511:0]" +Toggle 0to1 tdata [437] "logic tdata[511:0]" +Toggle 1to0 tdata [437] "logic tdata[511:0]" +Toggle 0to1 tdata [438] "logic tdata[511:0]" +Toggle 1to0 tdata [438] "logic tdata[511:0]" +Toggle 0to1 tdata [439] "logic tdata[511:0]" +Toggle 1to0 tdata [439] "logic tdata[511:0]" +Toggle 0to1 tdata [440] "logic tdata[511:0]" +Toggle 1to0 tdata [440] "logic tdata[511:0]" +Toggle 0to1 tdata [441] "logic tdata[511:0]" +Toggle 1to0 tdata [441] "logic tdata[511:0]" +Toggle 0to1 tdata [442] "logic tdata[511:0]" +Toggle 1to0 tdata [442] "logic tdata[511:0]" +Toggle 0to1 tdata [443] "logic tdata[511:0]" +Toggle 1to0 tdata [443] "logic tdata[511:0]" +Toggle 0to1 tdata [444] "logic tdata[511:0]" +Toggle 1to0 tdata [444] "logic tdata[511:0]" +Toggle 0to1 tdata [445] "logic tdata[511:0]" +Toggle 1to0 tdata [445] "logic tdata[511:0]" +Toggle 0to1 tdata [446] "logic tdata[511:0]" +Toggle 1to0 tdata [446] "logic tdata[511:0]" +Toggle 0to1 tdata [447] "logic tdata[511:0]" +Toggle 1to0 tdata [447] "logic tdata[511:0]" +Toggle 0to1 tdata [448] "logic tdata[511:0]" +Toggle 1to0 tdata [448] "logic tdata[511:0]" +Toggle 0to1 tdata [449] "logic tdata[511:0]" +Toggle 1to0 tdata [449] "logic tdata[511:0]" +Toggle 0to1 tdata [450] "logic tdata[511:0]" +Toggle 1to0 tdata [450] "logic tdata[511:0]" +Toggle 0to1 tdata [451] "logic tdata[511:0]" +Toggle 1to0 tdata [451] "logic tdata[511:0]" +Toggle 0to1 tdata [452] "logic tdata[511:0]" +Toggle 1to0 tdata [452] "logic tdata[511:0]" +Toggle 0to1 tdata [453] "logic tdata[511:0]" +Toggle 1to0 tdata [453] "logic tdata[511:0]" +Toggle 0to1 tdata [454] "logic tdata[511:0]" +Toggle 1to0 tdata [454] "logic tdata[511:0]" +Toggle 0to1 tdata [455] "logic tdata[511:0]" +Toggle 1to0 tdata [455] "logic tdata[511:0]" +Toggle 0to1 tdata [456] "logic tdata[511:0]" +Toggle 1to0 tdata [456] "logic tdata[511:0]" +Toggle 0to1 tdata [457] "logic tdata[511:0]" +Toggle 1to0 tdata [457] "logic tdata[511:0]" +Toggle 0to1 tdata [458] "logic tdata[511:0]" +Toggle 1to0 tdata [458] "logic tdata[511:0]" +Toggle 0to1 tdata [459] "logic tdata[511:0]" +Toggle 1to0 tdata [459] "logic tdata[511:0]" +Toggle 0to1 tdata [460] "logic tdata[511:0]" +Toggle 1to0 tdata [460] "logic tdata[511:0]" +Toggle 0to1 tdata [461] "logic tdata[511:0]" +Toggle 1to0 tdata [461] "logic tdata[511:0]" +Toggle 0to1 tdata [462] "logic tdata[511:0]" +Toggle 1to0 tdata [462] "logic tdata[511:0]" +Toggle 0to1 tdata [463] "logic tdata[511:0]" +Toggle 1to0 tdata [463] "logic tdata[511:0]" +Toggle 0to1 tdata [464] "logic tdata[511:0]" +Toggle 1to0 tdata [464] "logic tdata[511:0]" +Toggle 0to1 tdata [465] "logic tdata[511:0]" +Toggle 1to0 tdata [465] "logic tdata[511:0]" +Toggle 0to1 tdata [466] "logic tdata[511:0]" +Toggle 1to0 tdata [466] "logic tdata[511:0]" +Toggle 0to1 tdata [467] "logic tdata[511:0]" +Toggle 1to0 tdata [467] "logic tdata[511:0]" +Toggle 0to1 tdata [468] "logic tdata[511:0]" +Toggle 1to0 tdata [468] "logic tdata[511:0]" +Toggle 0to1 tdata [469] "logic tdata[511:0]" +Toggle 1to0 tdata [469] "logic tdata[511:0]" +Toggle 0to1 tdata [470] "logic tdata[511:0]" +Toggle 1to0 tdata [470] "logic tdata[511:0]" +Toggle 0to1 tdata [471] "logic tdata[511:0]" +Toggle 1to0 tdata [471] "logic tdata[511:0]" +Toggle 0to1 tdata [472] "logic tdata[511:0]" +Toggle 1to0 tdata [472] "logic tdata[511:0]" +Toggle 0to1 tdata [473] "logic tdata[511:0]" +Toggle 1to0 tdata [473] "logic tdata[511:0]" +Toggle 0to1 tdata [474] "logic tdata[511:0]" +Toggle 1to0 tdata [474] "logic tdata[511:0]" +Toggle 0to1 tdata [475] "logic tdata[511:0]" +Toggle 1to0 tdata [475] "logic tdata[511:0]" +Toggle 0to1 tdata [476] "logic tdata[511:0]" +Toggle 1to0 tdata [476] "logic tdata[511:0]" +Toggle 0to1 tdata [477] "logic tdata[511:0]" +Toggle 1to0 tdata [477] "logic tdata[511:0]" +Toggle 0to1 tdata [478] "logic tdata[511:0]" +Toggle 1to0 tdata [478] "logic tdata[511:0]" +Toggle 0to1 tdata [479] "logic tdata[511:0]" +Toggle 1to0 tdata [479] "logic tdata[511:0]" +Toggle 0to1 tdata [480] "logic tdata[511:0]" +Toggle 1to0 tdata [480] "logic tdata[511:0]" +Toggle 0to1 tdata [481] "logic tdata[511:0]" +Toggle 1to0 tdata [481] "logic tdata[511:0]" +Toggle 0to1 tdata [482] "logic tdata[511:0]" +Toggle 1to0 tdata [482] "logic tdata[511:0]" +Toggle 0to1 tdata [483] "logic tdata[511:0]" +Toggle 1to0 tdata [483] "logic tdata[511:0]" +Toggle 0to1 tdata [484] "logic tdata[511:0]" +Toggle 1to0 tdata [484] "logic tdata[511:0]" +Toggle 0to1 tdata [485] "logic tdata[511:0]" +Toggle 1to0 tdata [485] "logic tdata[511:0]" +Toggle 0to1 tdata [486] "logic tdata[511:0]" +Toggle 1to0 tdata [486] "logic tdata[511:0]" +Toggle 0to1 tdata [487] "logic tdata[511:0]" +Toggle 1to0 tdata [487] "logic tdata[511:0]" +Toggle 0to1 tdata [488] "logic tdata[511:0]" +Toggle 1to0 tdata [488] "logic tdata[511:0]" +Toggle 0to1 tdata [489] "logic tdata[511:0]" +Toggle 1to0 tdata [489] "logic tdata[511:0]" +Toggle 0to1 tdata [490] "logic tdata[511:0]" +Toggle 1to0 tdata [490] "logic tdata[511:0]" +Toggle 0to1 tdata [491] "logic tdata[511:0]" +Toggle 1to0 tdata [491] "logic tdata[511:0]" +Toggle 0to1 tdata [492] "logic tdata[511:0]" +Toggle 1to0 tdata [492] "logic tdata[511:0]" +Toggle 0to1 tdata [493] "logic tdata[511:0]" +Toggle 1to0 tdata [493] "logic tdata[511:0]" +Toggle 0to1 tdata [494] "logic tdata[511:0]" +Toggle 1to0 tdata [494] "logic tdata[511:0]" +Toggle 0to1 tdata [495] "logic tdata[511:0]" +Toggle 1to0 tdata [495] "logic tdata[511:0]" +Toggle 0to1 tdata [496] "logic tdata[511:0]" +Toggle 1to0 tdata [496] "logic tdata[511:0]" +Toggle 0to1 tdata [497] "logic tdata[511:0]" +Toggle 1to0 tdata [497] "logic tdata[511:0]" +Toggle 0to1 tdata [498] "logic tdata[511:0]" +Toggle 1to0 tdata [498] "logic tdata[511:0]" +Toggle 0to1 tdata [499] "logic tdata[511:0]" +Toggle 1to0 tdata [499] "logic tdata[511:0]" +Toggle 0to1 tdata [500] "logic tdata[511:0]" +Toggle 1to0 tdata [500] "logic tdata[511:0]" +Toggle 0to1 tdata [501] "logic tdata[511:0]" +Toggle 1to0 tdata [501] "logic tdata[511:0]" +Toggle 0to1 tdata [502] "logic tdata[511:0]" +Toggle 1to0 tdata [502] "logic tdata[511:0]" +Toggle 0to1 tdata [503] "logic tdata[511:0]" +Toggle 1to0 tdata [503] "logic tdata[511:0]" +Toggle 0to1 tdata [504] "logic tdata[511:0]" +Toggle 1to0 tdata [504] "logic tdata[511:0]" +Toggle 0to1 tdata [505] "logic tdata[511:0]" +Toggle 1to0 tdata [505] "logic tdata[511:0]" +Toggle 0to1 tdata [506] "logic tdata[511:0]" +Toggle 1to0 tdata [506] "logic tdata[511:0]" +Toggle 0to1 tdata [507] "logic tdata[511:0]" +Toggle 1to0 tdata [507] "logic tdata[511:0]" +Toggle 0to1 tdata [508] "logic tdata[511:0]" +Toggle 1to0 tdata [508] "logic tdata[511:0]" +Toggle 0to1 tdata [509] "logic tdata[511:0]" +Toggle 1to0 tdata [509] "logic tdata[511:0]" +Toggle 0to1 tdata [510] "logic tdata[511:0]" +Toggle 1to0 tdata [510] "logic tdata[511:0]" +Toggle 0to1 tdata [255] "logic tdata[511:0]" +Toggle 1to0 tdata [255] "logic tdata[511:0]" +Toggle 0to1 tdata [175] "logic tdata[511:0]" +Toggle 1to0 tdata [175] "logic tdata[511:0]" +Toggle 0to1 tdata [176] "logic tdata[511:0]" +Toggle 1to0 tdata [176] "logic tdata[511:0]" +Toggle 0to1 tdata [177] "logic tdata[511:0]" +Toggle 1to0 tdata [177] "logic tdata[511:0]" +Toggle 0to1 tdata [178] "logic tdata[511:0]" +Toggle 1to0 tdata [178] "logic tdata[511:0]" +Toggle 0to1 tdata [179] "logic tdata[511:0]" +Toggle 1to0 tdata [179] "logic tdata[511:0]" +Toggle 0to1 tdata [180] "logic tdata[511:0]" +Toggle 1to0 tdata [180] "logic tdata[511:0]" +Toggle 0to1 tdata [181] "logic tdata[511:0]" +Toggle 1to0 tdata [181] "logic tdata[511:0]" +Toggle 0to1 tdata [182] "logic tdata[511:0]" +Toggle 1to0 tdata [182] "logic tdata[511:0]" +Toggle 0to1 tdata [183] "logic tdata[511:0]" +Toggle 1to0 tdata [183] "logic tdata[511:0]" +Toggle 0to1 tdata [184] "logic tdata[511:0]" +Toggle 1to0 tdata [184] "logic tdata[511:0]" +Toggle 0to1 tdata [185] "logic tdata[511:0]" +Toggle 1to0 tdata [185] "logic tdata[511:0]" +Toggle 0to1 tdata [186] "logic tdata[511:0]" +Toggle 1to0 tdata [186] "logic tdata[511:0]" +Toggle 0to1 tdata [187] "logic tdata[511:0]" +Toggle 1to0 tdata [187] "logic tdata[511:0]" +Toggle 0to1 tdata [188] "logic tdata[511:0]" +Toggle 1to0 tdata [188] "logic tdata[511:0]" +Toggle 0to1 tdata [189] "logic tdata[511:0]" +Toggle 1to0 tdata [189] "logic tdata[511:0]" +Toggle 0to1 tdata [190] "logic tdata[511:0]" +Toggle 1to0 tdata [190] "logic tdata[511:0]" +Toggle 0to1 tdata [191] "logic tdata[511:0]" +Toggle 1to0 tdata [191] "logic tdata[511:0]" +Toggle 0to1 tdata [192] "logic tdata[511:0]" +Toggle 1to0 tdata [192] "logic tdata[511:0]" +Toggle 0to1 tdata [193] "logic tdata[511:0]" +Toggle 1to0 tdata [193] "logic tdata[511:0]" +Toggle 0to1 tdata [194] "logic tdata[511:0]" +Toggle 1to0 tdata [194] "logic tdata[511:0]" +Toggle 0to1 tdata [195] "logic tdata[511:0]" +Toggle 1to0 tdata [195] "logic tdata[511:0]" +Toggle 0to1 tdata [196] "logic tdata[511:0]" +Toggle 1to0 tdata [196] "logic tdata[511:0]" +Toggle 0to1 tdata [197] "logic tdata[511:0]" +Toggle 1to0 tdata [197] "logic tdata[511:0]" +Toggle 0to1 tdata [198] "logic tdata[511:0]" +Toggle 1to0 tdata [198] "logic tdata[511:0]" +Toggle 0to1 tdata [199] "logic tdata[511:0]" +Toggle 1to0 tdata [199] "logic tdata[511:0]" +Toggle 0to1 tdata [200] "logic tdata[511:0]" +Toggle 1to0 tdata [200] "logic tdata[511:0]" +Toggle 0to1 tdata [201] "logic tdata[511:0]" +Toggle 1to0 tdata [201] "logic tdata[511:0]" +Toggle 0to1 tdata [202] "logic tdata[511:0]" +Toggle 1to0 tdata [202] "logic tdata[511:0]" +Toggle 0to1 tdata [203] "logic tdata[511:0]" +Toggle 1to0 tdata [203] "logic tdata[511:0]" +Toggle 0to1 tdata [204] "logic tdata[511:0]" +Toggle 1to0 tdata [204] "logic tdata[511:0]" +Toggle 0to1 tdata [205] "logic tdata[511:0]" +Toggle 1to0 tdata [205] "logic tdata[511:0]" +Toggle 0to1 tdata [206] "logic tdata[511:0]" +Toggle 1to0 tdata [206] "logic tdata[511:0]" +Toggle 0to1 tdata [207] "logic tdata[511:0]" +Toggle 1to0 tdata [207] "logic tdata[511:0]" +Toggle 0to1 tdata [208] "logic tdata[511:0]" +Toggle 1to0 tdata [208] "logic tdata[511:0]" +Toggle 0to1 tdata [209] "logic tdata[511:0]" +Toggle 1to0 tdata [209] "logic tdata[511:0]" +Toggle 0to1 tdata [210] "logic tdata[511:0]" +Toggle 1to0 tdata [210] "logic tdata[511:0]" +Toggle 0to1 tdata [211] "logic tdata[511:0]" +Toggle 1to0 tdata [211] "logic tdata[511:0]" +Toggle 0to1 tdata [212] "logic tdata[511:0]" +Toggle 1to0 tdata [212] "logic tdata[511:0]" +Toggle 0to1 tdata [213] "logic tdata[511:0]" +Toggle 1to0 tdata [213] "logic tdata[511:0]" +Toggle 0to1 tdata [214] "logic tdata[511:0]" +Toggle 1to0 tdata [214] "logic tdata[511:0]" +Toggle 0to1 tdata [215] "logic tdata[511:0]" +Toggle 1to0 tdata [215] "logic tdata[511:0]" +Toggle 0to1 tdata [216] "logic tdata[511:0]" +Toggle 1to0 tdata [216] "logic tdata[511:0]" +Toggle 0to1 tdata [217] "logic tdata[511:0]" +Toggle 1to0 tdata [217] "logic tdata[511:0]" +Toggle 0to1 tdata [218] "logic tdata[511:0]" +Toggle 1to0 tdata [218] "logic tdata[511:0]" +Toggle 0to1 tdata [219] "logic tdata[511:0]" +Toggle 1to0 tdata [219] "logic tdata[511:0]" +Toggle 0to1 tdata [220] "logic tdata[511:0]" +Toggle 1to0 tdata [220] "logic tdata[511:0]" +Toggle 0to1 tdata [221] "logic tdata[511:0]" +Toggle 1to0 tdata [221] "logic tdata[511:0]" +Toggle 0to1 tdata [222] "logic tdata[511:0]" +Toggle 1to0 tdata [222] "logic tdata[511:0]" +Toggle 0to1 tdata [223] "logic tdata[511:0]" +Toggle 1to0 tdata [223] "logic tdata[511:0]" +Toggle 0to1 tdata [224] "logic tdata[511:0]" +Toggle 1to0 tdata [224] "logic tdata[511:0]" +Toggle 0to1 tdata [225] "logic tdata[511:0]" +Toggle 1to0 tdata [225] "logic tdata[511:0]" +Toggle 0to1 tdata [226] "logic tdata[511:0]" +Toggle 1to0 tdata [226] "logic tdata[511:0]" +Toggle 0to1 tdata [227] "logic tdata[511:0]" +Toggle 1to0 tdata [227] "logic tdata[511:0]" +Toggle 0to1 tdata [228] "logic tdata[511:0]" +Toggle 1to0 tdata [228] "logic tdata[511:0]" +Toggle 0to1 tdata [229] "logic tdata[511:0]" +Toggle 1to0 tdata [229] "logic tdata[511:0]" +Toggle 0to1 tdata [230] "logic tdata[511:0]" +Toggle 1to0 tdata [230] "logic tdata[511:0]" +Toggle 0to1 tdata [231] "logic tdata[511:0]" +Toggle 1to0 tdata [231] "logic tdata[511:0]" +Toggle 0to1 tdata [232] "logic tdata[511:0]" +Toggle 1to0 tdata [232] "logic tdata[511:0]" +Toggle 0to1 tdata [233] "logic tdata[511:0]" +Toggle 1to0 tdata [233] "logic tdata[511:0]" +Toggle 0to1 tdata [234] "logic tdata[511:0]" +Toggle 1to0 tdata [234] "logic tdata[511:0]" +Toggle 0to1 tdata [235] "logic tdata[511:0]" +Toggle 1to0 tdata [235] "logic tdata[511:0]" +Toggle 0to1 tdata [236] "logic tdata[511:0]" +Toggle 1to0 tdata [236] "logic tdata[511:0]" +Toggle 0to1 tdata [237] "logic tdata[511:0]" +Toggle 1to0 tdata [237] "logic tdata[511:0]" +Toggle 0to1 tdata [238] "logic tdata[511:0]" +Toggle 1to0 tdata [238] "logic tdata[511:0]" +Toggle 0to1 tdata [239] "logic tdata[511:0]" +Toggle 1to0 tdata [239] "logic tdata[511:0]" +Toggle 0to1 tdata [240] "logic tdata[511:0]" +Toggle 1to0 tdata [240] "logic tdata[511:0]" +Toggle 0to1 tdata [241] "logic tdata[511:0]" +Toggle 1to0 tdata [241] "logic tdata[511:0]" +Toggle 0to1 tdata [242] "logic tdata[511:0]" +Toggle 1to0 tdata [242] "logic tdata[511:0]" +Toggle 0to1 tdata [243] "logic tdata[511:0]" +Toggle 1to0 tdata [243] "logic tdata[511:0]" +Toggle 0to1 tdata [244] "logic tdata[511:0]" +Toggle 1to0 tdata [244] "logic tdata[511:0]" +Toggle 0to1 tdata [245] "logic tdata[511:0]" +Toggle 1to0 tdata [245] "logic tdata[511:0]" +Toggle 0to1 tdata [246] "logic tdata[511:0]" +Toggle 1to0 tdata [246] "logic tdata[511:0]" +Toggle 0to1 tdata [247] "logic tdata[511:0]" +Toggle 1to0 tdata [247] "logic tdata[511:0]" +Toggle 0to1 tdata [248] "logic tdata[511:0]" +Toggle 1to0 tdata [248] "logic tdata[511:0]" +Toggle 0to1 tdata [249] "logic tdata[511:0]" +Toggle 1to0 tdata [249] "logic tdata[511:0]" +Toggle 0to1 tdata [250] "logic tdata[511:0]" +Toggle 1to0 tdata [250] "logic tdata[511:0]" +Toggle 0to1 tdata [251] "logic tdata[511:0]" +Toggle 1to0 tdata [251] "logic tdata[511:0]" +Toggle 0to1 tdata [252] "logic tdata[511:0]" +Toggle 1to0 tdata [252] "logic tdata[511:0]" +Toggle 0to1 tdata [253] "logic tdata[511:0]" +Toggle 1to0 tdata [253] "logic tdata[511:0]" +Toggle 0to1 tdata [254] "logic tdata[511:0]" +Toggle 1to0 tdata [254] "logic tdata[511:0]" +Toggle 0to1 tdata [173] "logic tdata[511:0]" +Toggle 1to0 tdata [173] "logic tdata[511:0]" +Toggle 0to1 tdata [165] "logic tdata[511:0]" +Toggle 1to0 tdata [165] "logic tdata[511:0]" +Toggle 0to1 tdata [166] "logic tdata[511:0]" +Toggle 1to0 tdata [166] "logic tdata[511:0]" +Toggle 0to1 tdata [167] "logic tdata[511:0]" +Toggle 1to0 tdata [167] "logic tdata[511:0]" +Toggle 0to1 tdata [168] "logic tdata[511:0]" +Toggle 1to0 tdata [168] "logic tdata[511:0]" +Toggle 0to1 tdata [169] "logic tdata[511:0]" +Toggle 1to0 tdata [169] "logic tdata[511:0]" +Toggle 0to1 tdata [170] "logic tdata[511:0]" +Toggle 1to0 tdata [170] "logic tdata[511:0]" +Toggle 0to1 tdata [171] "logic tdata[511:0]" +Toggle 1to0 tdata [171] "logic tdata[511:0]" +Toggle 0to1 tdata [172] "logic tdata[511:0]" +Toggle 1to0 tdata [172] "logic tdata[511:0]" +Toggle 0to1 tdata [163] "logic tdata[511:0]" +Toggle 1to0 tdata [163] "logic tdata[511:0]" +Toggle 0to1 tdata [81] "logic tdata[511:0]" +Toggle 1to0 tdata [81] "logic tdata[511:0]" +Toggle 0to1 tdata [82] "logic tdata[511:0]" +Toggle 1to0 tdata [82] "logic tdata[511:0]" +Toggle 0to1 tdata [83] "logic tdata[511:0]" +Toggle 1to0 tdata [83] "logic tdata[511:0]" +Toggle 0to1 tdata [84] "logic tdata[511:0]" +Toggle 1to0 tdata [84] "logic tdata[511:0]" +Toggle 0to1 tdata [85] "logic tdata[511:0]" +Toggle 1to0 tdata [85] "logic tdata[511:0]" +Toggle 0to1 tdata [86] "logic tdata[511:0]" +Toggle 1to0 tdata [86] "logic tdata[511:0]" +Toggle 0to1 tdata [87] "logic tdata[511:0]" +Toggle 1to0 tdata [87] "logic tdata[511:0]" +Toggle 0to1 tdata [88] "logic tdata[511:0]" +Toggle 1to0 tdata [88] "logic tdata[511:0]" +Toggle 0to1 tdata [89] "logic tdata[511:0]" +Toggle 1to0 tdata [89] "logic tdata[511:0]" +Toggle 0to1 tdata [90] "logic tdata[511:0]" +Toggle 1to0 tdata [90] "logic tdata[511:0]" +Toggle 0to1 tdata [91] "logic tdata[511:0]" +Toggle 1to0 tdata [91] "logic tdata[511:0]" +Toggle 0to1 tdata [92] "logic tdata[511:0]" +Toggle 1to0 tdata [92] "logic tdata[511:0]" +Toggle 0to1 tdata [93] "logic tdata[511:0]" +Toggle 1to0 tdata [93] "logic tdata[511:0]" +Toggle 0to1 tdata [94] "logic tdata[511:0]" +Toggle 1to0 tdata [94] "logic tdata[511:0]" +Toggle 0to1 tdata [95] "logic tdata[511:0]" +Toggle 1to0 tdata [95] "logic tdata[511:0]" +Toggle 0to1 tdata [96] "logic tdata[511:0]" +Toggle 1to0 tdata [96] "logic tdata[511:0]" +Toggle 0to1 tdata [97] "logic tdata[511:0]" +Toggle 1to0 tdata [97] "logic tdata[511:0]" +Toggle 0to1 tdata [98] "logic tdata[511:0]" +Toggle 1to0 tdata [98] "logic tdata[511:0]" +Toggle 0to1 tdata [99] "logic tdata[511:0]" +Toggle 1to0 tdata [99] "logic tdata[511:0]" +Toggle 0to1 tdata [100] "logic tdata[511:0]" +Toggle 1to0 tdata [100] "logic tdata[511:0]" +Toggle 0to1 tdata [101] "logic tdata[511:0]" +Toggle 1to0 tdata [101] "logic tdata[511:0]" +Toggle 0to1 tdata [102] "logic tdata[511:0]" +Toggle 1to0 tdata [102] "logic tdata[511:0]" +Toggle 0to1 tdata [103] "logic tdata[511:0]" +Toggle 1to0 tdata [103] "logic tdata[511:0]" +Toggle 0to1 tdata [104] "logic tdata[511:0]" +Toggle 1to0 tdata [104] "logic tdata[511:0]" +Toggle 0to1 tdata [105] "logic tdata[511:0]" +Toggle 1to0 tdata [105] "logic tdata[511:0]" +Toggle 0to1 tdata [106] "logic tdata[511:0]" +Toggle 1to0 tdata [106] "logic tdata[511:0]" +Toggle 0to1 tdata [107] "logic tdata[511:0]" +Toggle 1to0 tdata [107] "logic tdata[511:0]" +Toggle 0to1 tdata [108] "logic tdata[511:0]" +Toggle 1to0 tdata [108] "logic tdata[511:0]" +Toggle 0to1 tdata [109] "logic tdata[511:0]" +Toggle 1to0 tdata [109] "logic tdata[511:0]" +Toggle 0to1 tdata [110] "logic tdata[511:0]" +Toggle 1to0 tdata [110] "logic tdata[511:0]" +Toggle 0to1 tdata [111] "logic tdata[511:0]" +Toggle 1to0 tdata [111] "logic tdata[511:0]" +Toggle 0to1 tdata [112] "logic tdata[511:0]" +Toggle 1to0 tdata [112] "logic tdata[511:0]" +Toggle 0to1 tdata [113] "logic tdata[511:0]" +Toggle 1to0 tdata [113] "logic tdata[511:0]" +Toggle 0to1 tdata [114] "logic tdata[511:0]" +Toggle 1to0 tdata [114] "logic tdata[511:0]" +Toggle 0to1 tdata [115] "logic tdata[511:0]" +Toggle 1to0 tdata [115] "logic tdata[511:0]" +Toggle 0to1 tdata [116] "logic tdata[511:0]" +Toggle 1to0 tdata [116] "logic tdata[511:0]" +Toggle 0to1 tdata [117] "logic tdata[511:0]" +Toggle 1to0 tdata [117] "logic tdata[511:0]" +Toggle 0to1 tdata [118] "logic tdata[511:0]" +Toggle 1to0 tdata [118] "logic tdata[511:0]" +Toggle 0to1 tdata [119] "logic tdata[511:0]" +Toggle 1to0 tdata [119] "logic tdata[511:0]" +Toggle 0to1 tdata [120] "logic tdata[511:0]" +Toggle 1to0 tdata [120] "logic tdata[511:0]" +Toggle 0to1 tdata [121] "logic tdata[511:0]" +Toggle 1to0 tdata [121] "logic tdata[511:0]" +Toggle 0to1 tdata [122] "logic tdata[511:0]" +Toggle 1to0 tdata [122] "logic tdata[511:0]" +Toggle 0to1 tdata [123] "logic tdata[511:0]" +Toggle 1to0 tdata [123] "logic tdata[511:0]" +Toggle 0to1 tdata [124] "logic tdata[511:0]" +Toggle 1to0 tdata [124] "logic tdata[511:0]" +Toggle 0to1 tdata [125] "logic tdata[511:0]" +Toggle 1to0 tdata [125] "logic tdata[511:0]" +Toggle 0to1 tdata [126] "logic tdata[511:0]" +Toggle 1to0 tdata [126] "logic tdata[511:0]" +Toggle 0to1 tdata [127] "logic tdata[511:0]" +Toggle 1to0 tdata [127] "logic tdata[511:0]" +Toggle 0to1 tdata [128] "logic tdata[511:0]" +Toggle 1to0 tdata [128] "logic tdata[511:0]" +Toggle 0to1 tdata [129] "logic tdata[511:0]" +Toggle 1to0 tdata [129] "logic tdata[511:0]" +Toggle 0to1 tdata [130] "logic tdata[511:0]" +Toggle 1to0 tdata [130] "logic tdata[511:0]" +Toggle 0to1 tdata [131] "logic tdata[511:0]" +Toggle 1to0 tdata [131] "logic tdata[511:0]" +Toggle 0to1 tdata [132] "logic tdata[511:0]" +Toggle 1to0 tdata [132] "logic tdata[511:0]" +Toggle 0to1 tdata [133] "logic tdata[511:0]" +Toggle 1to0 tdata [133] "logic tdata[511:0]" +Toggle 0to1 tdata [134] "logic tdata[511:0]" +Toggle 1to0 tdata [134] "logic tdata[511:0]" +Toggle 0to1 tdata [135] "logic tdata[511:0]" +Toggle 1to0 tdata [135] "logic tdata[511:0]" +Toggle 0to1 tdata [136] "logic tdata[511:0]" +Toggle 1to0 tdata [136] "logic tdata[511:0]" +Toggle 0to1 tdata [137] "logic tdata[511:0]" +Toggle 1to0 tdata [137] "logic tdata[511:0]" +Toggle 0to1 tdata [138] "logic tdata[511:0]" +Toggle 1to0 tdata [138] "logic tdata[511:0]" +Toggle 0to1 tdata [139] "logic tdata[511:0]" +Toggle 1to0 tdata [139] "logic tdata[511:0]" +Toggle 0to1 tdata [140] "logic tdata[511:0]" +Toggle 1to0 tdata [140] "logic tdata[511:0]" +Toggle 0to1 tdata [141] "logic tdata[511:0]" +Toggle 1to0 tdata [141] "logic tdata[511:0]" +Toggle 0to1 tdata [142] "logic tdata[511:0]" +Toggle 1to0 tdata [142] "logic tdata[511:0]" +Toggle 0to1 tdata [143] "logic tdata[511:0]" +Toggle 1to0 tdata [143] "logic tdata[511:0]" +Toggle 0to1 tdata [144] "logic tdata[511:0]" +Toggle 1to0 tdata [144] "logic tdata[511:0]" +Toggle 0to1 tdata [145] "logic tdata[511:0]" +Toggle 1to0 tdata [145] "logic tdata[511:0]" +Toggle 0to1 tdata [146] "logic tdata[511:0]" +Toggle 1to0 tdata [146] "logic tdata[511:0]" +Toggle 0to1 tdata [147] "logic tdata[511:0]" +Toggle 1to0 tdata [147] "logic tdata[511:0]" +Toggle 0to1 tdata [148] "logic tdata[511:0]" +Toggle 1to0 tdata [148] "logic tdata[511:0]" +Toggle 0to1 tdata [149] "logic tdata[511:0]" +Toggle 1to0 tdata [149] "logic tdata[511:0]" +Toggle 0to1 tdata [150] "logic tdata[511:0]" +Toggle 1to0 tdata [150] "logic tdata[511:0]" +Toggle 0to1 tdata [151] "logic tdata[511:0]" +Toggle 1to0 tdata [151] "logic tdata[511:0]" +Toggle 0to1 tdata [152] "logic tdata[511:0]" +Toggle 1to0 tdata [152] "logic tdata[511:0]" +Toggle 0to1 tdata [153] "logic tdata[511:0]" +Toggle 1to0 tdata [153] "logic tdata[511:0]" +Toggle 0to1 tdata [154] "logic tdata[511:0]" +Toggle 1to0 tdata [154] "logic tdata[511:0]" +Toggle 0to1 tdata [155] "logic tdata[511:0]" +Toggle 1to0 tdata [155] "logic tdata[511:0]" +Toggle 0to1 tdata [156] "logic tdata[511:0]" +Toggle 1to0 tdata [156] "logic tdata[511:0]" +Toggle 0to1 tdata [157] "logic tdata[511:0]" +Toggle 1to0 tdata [157] "logic tdata[511:0]" +Toggle 0to1 tdata [158] "logic tdata[511:0]" +Toggle 1to0 tdata [158] "logic tdata[511:0]" +Toggle 0to1 tdata [159] "logic tdata[511:0]" +Toggle 1to0 tdata [159] "logic tdata[511:0]" +Toggle 0to1 tdata [160] "logic tdata[511:0]" +Toggle 1to0 tdata [160] "logic tdata[511:0]" +Toggle 0to1 tdata [161] "logic tdata[511:0]" +Toggle 1to0 tdata [161] "logic tdata[511:0]" +Toggle 0to1 tdata [162] "logic tdata[511:0]" +Toggle 1to0 tdata [162] "logic tdata[511:0]" +Toggle 0to1 tdata [79] "logic tdata[511:0]" +Toggle 1to0 tdata [79] "logic tdata[511:0]" +Toggle 0to1 tdata [77] "logic tdata[511:0]" +Toggle 1to0 tdata [77] "logic tdata[511:0]" +Toggle 0to1 tdata [78] "logic tdata[511:0]" +Toggle 1to0 tdata [78] "logic tdata[511:0]" +Toggle 0to1 tdata [71] "logic tdata[511:0]" +Toggle 1to0 tdata [71] "logic tdata[511:0]" +Toggle 0to1 tdata [66] "logic tdata[511:0]" +Toggle 1to0 tdata [66] "logic tdata[511:0]" +Toggle 0to1 tdata [0] "logic tdata[511:0]" +Toggle 1to0 tdata [0] "logic tdata[511:0]" +Toggle 0to1 tdata [31] "logic tdata[511:0]" +Toggle 1to0 tdata [31] "logic tdata[511:0]" +Toggle 0to1 tdata [32] "logic tdata[511:0]" +Toggle 1to0 tdata [32] "logic tdata[511:0]" +Toggle 0to1 tdata [33] "logic tdata[511:0]" +Toggle 1to0 tdata [33] "logic tdata[511:0]" +Toggle 0to1 tdata [34] "logic tdata[511:0]" +Toggle 1to0 tdata [34] "logic tdata[511:0]" +Toggle 0to1 tdata [52] "logic tdata[511:0]" +Toggle 1to0 tdata [52] "logic tdata[511:0]" +Toggle 0to1 tdata [54] "logic tdata[511:0]" +Toggle 1to0 tdata [54] "logic tdata[511:0]" +Toggle 0to1 tdata [55] "logic tdata[511:0]" +Toggle 1to0 tdata [55] "logic tdata[511:0]" +Toggle 0to1 tdata [56] "logic tdata[511:0]" +Toggle 1to0 tdata [56] "logic tdata[511:0]" +Toggle 0to1 tdata [57] "logic tdata[511:0]" +Toggle 1to0 tdata [57] "logic tdata[511:0]" +Toggle 0to1 tdata [58] "logic tdata[511:0]" +Toggle 1to0 tdata [58] "logic tdata[511:0]" +Toggle 0to1 tdata [59] "logic tdata[511:0]" +Toggle 1to0 tdata [59] "logic tdata[511:0]" +Toggle 0to1 tdata [60] "logic tdata[511:0]" +Toggle 1to0 tdata [60] "logic tdata[511:0]" +Toggle 0to1 tdata [61] "logic tdata[511:0]" +Toggle 1to0 tdata [61] "logic tdata[511:0]" +Toggle 0to1 tdata [62] "logic tdata[511:0]" +Toggle 1to0 tdata [62] "logic tdata[511:0]" +Toggle 0to1 tdata [63] "logic tdata[511:0]" +Toggle 1to0 tdata [63] "logic tdata[511:0]" +Toggle 0to1 tdata [64] "logic tdata[511:0]" +Toggle 1to0 tdata [64] "logic tdata[511:0]" +Toggle 0to1 tdata [65] "logic tdata[511:0]" +Toggle 1to0 tdata [65] "logic tdata[511:0]" +Toggle 1to0 tdata [174] "logic tdata[511:0]" +Toggle 1to0 tdata [2] "logic tdata[511:0]" +Toggle 1to0 tdata [3] "logic tdata[511:0]" +Toggle 1to0 tdata [4] "logic tdata[511:0]" +Toggle 1to0 tdata [5] "logic tdata[511:0]" +Toggle 1to0 tdata [6] "logic tdata[511:0]" +Toggle 1to0 tdata [7] "logic tdata[511:0]" +Toggle 1to0 tdata [8] "logic tdata[511:0]" +Toggle 1to0 tdata [9] "logic tdata[511:0]" +Toggle 1to0 tdata [10] "logic tdata[511:0]" +Toggle 1to0 tdata [11] "logic tdata[511:0]" +Toggle 1to0 tdata [12] "logic tdata[511:0]" +Toggle 1to0 tdata [13] "logic tdata[511:0]" +Toggle 1to0 tdata [14] "logic tdata[511:0]" +Toggle 1to0 tdata [15] "logic tdata[511:0]" +Toggle 1to0 tdata [16] "logic tdata[511:0]" +Toggle 1to0 tdata [17] "logic tdata[511:0]" +Toggle 1to0 tdata [18] "logic tdata[511:0]" +Toggle 1to0 tdata [19] "logic tdata[511:0]" +Toggle 1to0 tdata [20] "logic tdata[511:0]" +Toggle 1to0 tdata [21] "logic tdata[511:0]" +Toggle 1to0 tdata [22] "logic tdata[511:0]" +Toggle 1to0 tdata [23] "logic tdata[511:0]" +Toggle 1to0 tdata [24] "logic tdata[511:0]" +Toggle 1to0 tdata [26] "logic tdata[511:0]" +Toggle 1to0 tdata [28] "logic tdata[511:0]" +Toggle 1to0 tdata [29] "logic tdata[511:0]" +Toggle 1to0 tdata [36] "logic tdata[511:0]" +Toggle 1to0 tdata [37] "logic tdata[511:0]" +Toggle 1to0 tdata [38] "logic tdata[511:0]" +Toggle 1to0 tdata [39] "logic tdata[511:0]" +Toggle 1to0 tdata [40] "logic tdata[511:0]" +Toggle 1to0 tdata [41] "logic tdata[511:0]" +Toggle 1to0 tdata [42] "logic tdata[511:0]" +Toggle 1to0 tdata [43] "logic tdata[511:0]" +Toggle 1to0 tdata [44] "logic tdata[511:0]" +Toggle 1to0 tdata [45] "logic tdata[511:0]" +Toggle 1to0 tdata [46] "logic tdata[511:0]" +Toggle 1to0 tdata [47] "logic tdata[511:0]" +Toggle 1to0 tdata [48] "logic tdata[511:0]" +Toggle 1to0 tdata [49] "logic tdata[511:0]" +Toggle 1to0 tdata [50] "logic tdata[511:0]" +Toggle 1to0 tdata [53] "logic tdata[511:0]" +Toggle 1to0 tdata [80] "logic tdata[511:0]" +Toggle 1to0 tdata [164] "logic tdata[511:0]" +Toggle 0to1 tdata [50] "logic tdata[511:0]" +Toggle 0to1 tdata [2] "logic tdata[511:0]" +Toggle 0to1 tdata [3] "logic tdata[511:0]" +Toggle 0to1 tdata [4] "logic tdata[511:0]" +Toggle 0to1 tdata [5] "logic tdata[511:0]" +Toggle 0to1 tdata [6] "logic tdata[511:0]" +Toggle 0to1 tdata [7] "logic tdata[511:0]" +Toggle 0to1 tdata [8] "logic tdata[511:0]" +Toggle 0to1 tdata [9] "logic tdata[511:0]" +Toggle 0to1 tdata [10] "logic tdata[511:0]" +Toggle 0to1 tdata [11] "logic tdata[511:0]" +Toggle 0to1 tdata [12] "logic tdata[511:0]" +Toggle 0to1 tdata [13] "logic tdata[511:0]" +Toggle 0to1 tdata [14] "logic tdata[511:0]" +Toggle 0to1 tdata [15] "logic tdata[511:0]" +Toggle 0to1 tdata [16] "logic tdata[511:0]" +Toggle 0to1 tdata [17] "logic tdata[511:0]" +Toggle 0to1 tdata [18] "logic tdata[511:0]" +Toggle 0to1 tdata [19] "logic tdata[511:0]" +Toggle 0to1 tdata [20] "logic tdata[511:0]" +Toggle 0to1 tdata [21] "logic tdata[511:0]" +Toggle 0to1 tdata [22] "logic tdata[511:0]" +Toggle 0to1 tdata [23] "logic tdata[511:0]" +Toggle 0to1 tdata [24] "logic tdata[511:0]" +Toggle 0to1 tdata [28] "logic tdata[511:0]" +Toggle 0to1 tdata [29] "logic tdata[511:0]" +Toggle 0to1 tdata [36] "logic tdata[511:0]" +Toggle 0to1 tdata [37] "logic tdata[511:0]" +Toggle 0to1 tdata [38] "logic tdata[511:0]" +Toggle 0to1 tdata [39] "logic tdata[511:0]" +Toggle 0to1 tdata [40] "logic tdata[511:0]" +Toggle 0to1 tdata [41] "logic tdata[511:0]" +Toggle 0to1 tdata [42] "logic tdata[511:0]" +Toggle 0to1 tdata [43] "logic tdata[511:0]" +Toggle 0to1 tdata [44] "logic tdata[511:0]" +Toggle 0to1 tdata [45] "logic tdata[511:0]" +Toggle 0to1 tdata [46] "logic tdata[511:0]" +Toggle 0to1 tdata [47] "logic tdata[511:0]" +Toggle 0to1 tdata [48] "logic tdata[511:0]" +Toggle 0to1 tdata [49] "logic tdata[511:0]" +Toggle 1to0 tdata [35] "logic tdata[511:0]" +Toggle 1to0 tdata [1] "logic tdata[511:0]" +Toggle 0to1 tdata [26] "logic tdata[511:0]" +Toggle 1to0 tdata [25] "logic tdata[511:0]" +Toggle 1to0 tdata [27] "logic tdata[511:0]" +Toggle 1to0 tdata [30] "logic tdata[511:0]" +Toggle 1to0 tdata [51] "logic tdata[511:0]" +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_a_if_t0[0] +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_a_if_t0[1] +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_a_if_t1[0] +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_a_if_t1[1] +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_b_if_t0[0] +Toggle tkeep "logic tkeep[63:0]" +Toggle tuser_vendor "logic tuser_vendor[9:0]" +Toggle 0to1 tlast "logic tlast" +Toggle 1to0 tlast "logic tlast" +Toggle 0to1 clk "net clk" +Toggle 1to0 clk "net clk" +Toggle 0to1 rst_n "net rst_n" +Toggle 1to0 rst_n "net rst_n" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_b_if_t0[1] +Toggle tuser_vendor "logic tuser_vendor[9:0]" +Toggle tkeep "logic tkeep[63:0]" +Toggle 0to1 clk "net clk" +Toggle 1to0 clk "net clk" +Toggle 0to1 rst_n "net rst_n" +Toggle 1to0 rst_n "net rst_n" +Toggle 0to1 tlast "logic tlast" +Toggle 1to0 tlast "logic tlast" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_b_if_t1[0] +Toggle tuser_vendor "logic tuser_vendor[9:0]" +Toggle tkeep "logic tkeep[63:0]" +Toggle 0to1 tlast "logic tlast" +Toggle 1to0 tlast "logic tlast" +Toggle 0to1 rst_n "net rst_n" +Toggle 1to0 rst_n "net rst_n" +Toggle 0to1 tready "logic tready" +Toggle 1to0 tready "logic tready" +Toggle 0to1 clk "net clk" +Toggle 1to0 clk "net clk" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_b_if_t1[1] +Toggle 0to1 clk "net clk" +Toggle 1to0 clk "net clk" +Toggle tuser_vendor "logic tuser_vendor[9:0]" +Toggle tkeep "logic tkeep[63:0]" +Toggle 0to1 rst_n "net rst_n" +Toggle 1to0 rst_n "net rst_n" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_fn2mx_a_port.r.axis_pl[0] +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_fn2mx_a_port.r.axis_pl[1] +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 0to1 tdata [511] "logic tdata[511:0]" +Toggle 1to0 tdata [511] "logic tdata[511:0]" +Toggle 0to1 tdata [0] "logic tdata[511:0]" +Toggle 1to0 tdata [0] "logic tdata[511:0]" +Toggle 0to1 tdata [2] "logic tdata[511:0]" +Toggle 1to0 tdata [2] "logic tdata[511:0]" +Toggle 0to1 tdata [3] "logic tdata[511:0]" +Toggle 1to0 tdata [3] "logic tdata[511:0]" +Toggle 0to1 tdata [4] "logic tdata[511:0]" +Toggle 1to0 tdata [4] "logic tdata[511:0]" +Toggle 0to1 tdata [5] "logic tdata[511:0]" +Toggle 1to0 tdata [5] "logic tdata[511:0]" +Toggle 0to1 tdata [6] "logic tdata[511:0]" +Toggle 1to0 tdata [6] "logic tdata[511:0]" +Toggle 0to1 tdata [7] "logic tdata[511:0]" +Toggle 1to0 tdata [7] "logic tdata[511:0]" +Toggle 0to1 tdata [8] "logic tdata[511:0]" +Toggle 1to0 tdata [8] "logic tdata[511:0]" +Toggle 0to1 tdata [9] "logic tdata[511:0]" +Toggle 1to0 tdata [9] "logic tdata[511:0]" +Toggle 0to1 tdata [10] "logic tdata[511:0]" +Toggle 1to0 tdata [10] "logic tdata[511:0]" +Toggle 0to1 tdata [11] "logic tdata[511:0]" +Toggle 1to0 tdata [11] "logic tdata[511:0]" +Toggle 0to1 tdata [12] "logic tdata[511:0]" +Toggle 1to0 tdata [12] "logic tdata[511:0]" +Toggle 0to1 tdata [13] "logic tdata[511:0]" +Toggle 1to0 tdata [13] "logic tdata[511:0]" +Toggle 0to1 tdata [14] "logic tdata[511:0]" +Toggle 1to0 tdata [14] "logic tdata[511:0]" +Toggle 0to1 tdata [15] "logic tdata[511:0]" +Toggle 1to0 tdata [15] "logic tdata[511:0]" +Toggle 0to1 tdata [16] "logic tdata[511:0]" +Toggle 1to0 tdata [16] "logic tdata[511:0]" +Toggle 0to1 tdata [17] "logic tdata[511:0]" +Toggle 1to0 tdata [17] "logic tdata[511:0]" +Toggle 0to1 tdata [18] "logic tdata[511:0]" +Toggle 1to0 tdata [18] "logic tdata[511:0]" +Toggle 0to1 tdata [19] "logic tdata[511:0]" +Toggle 1to0 tdata [19] "logic tdata[511:0]" +Toggle 0to1 tdata [20] "logic tdata[511:0]" +Toggle 1to0 tdata [20] "logic tdata[511:0]" +Toggle 0to1 tdata [21] "logic tdata[511:0]" +Toggle 1to0 tdata [21] "logic tdata[511:0]" +Toggle 0to1 tdata [22] "logic tdata[511:0]" +Toggle 1to0 tdata [22] "logic tdata[511:0]" +Toggle 0to1 tdata [23] "logic tdata[511:0]" +Toggle 1to0 tdata [23] "logic tdata[511:0]" +Toggle 0to1 tdata [24] "logic tdata[511:0]" +Toggle 1to0 tdata [24] "logic tdata[511:0]" +Toggle 0to1 tdata [26] "logic tdata[511:0]" +Toggle 1to0 tdata [26] "logic tdata[511:0]" +Toggle 0to1 tdata [28] "logic tdata[511:0]" +Toggle 1to0 tdata [28] "logic tdata[511:0]" +Toggle 0to1 tdata [29] "logic tdata[511:0]" +Toggle 1to0 tdata [29] "logic tdata[511:0]" +Toggle 0to1 tdata [31] "logic tdata[511:0]" +Toggle 1to0 tdata [31] "logic tdata[511:0]" +Toggle 0to1 tdata [32] "logic tdata[511:0]" +Toggle 1to0 tdata [32] "logic tdata[511:0]" +Toggle 0to1 tdata [33] "logic tdata[511:0]" +Toggle 1to0 tdata [33] "logic tdata[511:0]" +Toggle 0to1 tdata [34] "logic tdata[511:0]" +Toggle 1to0 tdata [34] "logic tdata[511:0]" +Toggle 0to1 tdata [36] "logic tdata[511:0]" +Toggle 1to0 tdata [36] "logic tdata[511:0]" +Toggle 0to1 tdata [37] "logic tdata[511:0]" +Toggle 1to0 tdata [37] "logic tdata[511:0]" +Toggle 0to1 tdata [38] "logic tdata[511:0]" +Toggle 1to0 tdata [38] "logic tdata[511:0]" +Toggle 0to1 tdata [39] "logic tdata[511:0]" +Toggle 1to0 tdata [39] "logic tdata[511:0]" +Toggle 0to1 tdata [40] "logic tdata[511:0]" +Toggle 1to0 tdata [40] "logic tdata[511:0]" +Toggle 0to1 tdata [41] "logic tdata[511:0]" +Toggle 1to0 tdata [41] "logic tdata[511:0]" +Toggle 0to1 tdata [42] "logic tdata[511:0]" +Toggle 1to0 tdata [42] "logic tdata[511:0]" +Toggle 0to1 tdata [43] "logic tdata[511:0]" +Toggle 1to0 tdata [43] "logic tdata[511:0]" +Toggle 0to1 tdata [44] "logic tdata[511:0]" +Toggle 1to0 tdata [44] "logic tdata[511:0]" +Toggle 0to1 tdata [45] "logic tdata[511:0]" +Toggle 1to0 tdata [45] "logic tdata[511:0]" +Toggle 0to1 tdata [46] "logic tdata[511:0]" +Toggle 1to0 tdata [46] "logic tdata[511:0]" +Toggle 0to1 tdata [47] "logic tdata[511:0]" +Toggle 1to0 tdata [47] "logic tdata[511:0]" +Toggle 0to1 tdata [48] "logic tdata[511:0]" +Toggle 1to0 tdata [48] "logic tdata[511:0]" +Toggle 0to1 tdata [49] "logic tdata[511:0]" +Toggle 1to0 tdata [49] "logic tdata[511:0]" +Toggle 0to1 tdata [50] "logic tdata[511:0]" +Toggle 1to0 tdata [50] "logic tdata[511:0]" +Toggle 0to1 tdata [52] "logic tdata[511:0]" +Toggle 1to0 tdata [52] "logic tdata[511:0]" +Toggle 0to1 tdata [54] "logic tdata[511:0]" +Toggle 1to0 tdata [54] "logic tdata[511:0]" +Toggle 0to1 tdata [55] "logic tdata[511:0]" +Toggle 1to0 tdata [55] "logic tdata[511:0]" +Toggle 0to1 tdata [56] "logic tdata[511:0]" +Toggle 1to0 tdata [56] "logic tdata[511:0]" +Toggle 0to1 tdata [57] "logic tdata[511:0]" +Toggle 1to0 tdata [57] "logic tdata[511:0]" +Toggle 0to1 tdata [58] "logic tdata[511:0]" +Toggle 1to0 tdata [58] "logic tdata[511:0]" +Toggle 0to1 tdata [59] "logic tdata[511:0]" +Toggle 1to0 tdata [59] "logic tdata[511:0]" +Toggle 0to1 tdata [60] "logic tdata[511:0]" +Toggle 1to0 tdata [60] "logic tdata[511:0]" +Toggle 0to1 tdata [61] "logic tdata[511:0]" +Toggle 1to0 tdata [61] "logic tdata[511:0]" +Toggle 0to1 tdata [62] "logic tdata[511:0]" +Toggle 1to0 tdata [62] "logic tdata[511:0]" +Toggle 0to1 tdata [63] "logic tdata[511:0]" +Toggle 1to0 tdata [63] "logic tdata[511:0]" +Toggle 0to1 tdata [64] "logic tdata[511:0]" +Toggle 1to0 tdata [64] "logic tdata[511:0]" +Toggle 0to1 tdata [65] "logic tdata[511:0]" +Toggle 1to0 tdata [65] "logic tdata[511:0]" +Toggle 0to1 tdata [66] "logic tdata[511:0]" +Toggle 1to0 tdata [66] "logic tdata[511:0]" +Toggle 0to1 tdata [71] "logic tdata[511:0]" +Toggle 1to0 tdata [71] "logic tdata[511:0]" +Toggle 0to1 tdata [77] "logic tdata[511:0]" +Toggle 1to0 tdata [77] "logic tdata[511:0]" +Toggle 0to1 tdata [78] "logic tdata[511:0]" +Toggle 1to0 tdata [78] "logic tdata[511:0]" +Toggle 0to1 tdata [79] "logic tdata[511:0]" +Toggle 1to0 tdata [79] "logic tdata[511:0]" +Toggle 0to1 tdata [81] "logic tdata[511:0]" +Toggle 1to0 tdata [81] "logic tdata[511:0]" +Toggle 0to1 tdata [82] "logic tdata[511:0]" +Toggle 1to0 tdata [82] "logic tdata[511:0]" +Toggle 0to1 tdata [83] "logic tdata[511:0]" +Toggle 1to0 tdata [83] "logic tdata[511:0]" +Toggle 0to1 tdata [84] "logic tdata[511:0]" +Toggle 1to0 tdata [84] "logic tdata[511:0]" +Toggle 0to1 tdata [85] "logic tdata[511:0]" +Toggle 1to0 tdata [85] "logic tdata[511:0]" +Toggle 0to1 tdata [86] "logic tdata[511:0]" +Toggle 1to0 tdata [86] "logic tdata[511:0]" +Toggle 0to1 tdata [87] "logic tdata[511:0]" +Toggle 1to0 tdata [87] "logic tdata[511:0]" +Toggle 0to1 tdata [88] "logic tdata[511:0]" +Toggle 1to0 tdata [88] "logic tdata[511:0]" +Toggle 0to1 tdata [89] "logic tdata[511:0]" +Toggle 1to0 tdata [89] "logic tdata[511:0]" +Toggle 0to1 tdata [90] "logic tdata[511:0]" +Toggle 1to0 tdata [90] "logic tdata[511:0]" +Toggle 0to1 tdata [91] "logic tdata[511:0]" +Toggle 1to0 tdata [91] "logic tdata[511:0]" +Toggle 0to1 tdata [92] "logic tdata[511:0]" +Toggle 1to0 tdata [92] "logic tdata[511:0]" +Toggle 0to1 tdata [93] "logic tdata[511:0]" +Toggle 1to0 tdata [93] "logic tdata[511:0]" +Toggle 0to1 tdata [94] "logic tdata[511:0]" +Toggle 1to0 tdata [94] "logic tdata[511:0]" +Toggle 0to1 tdata [95] "logic tdata[511:0]" +Toggle 1to0 tdata [95] "logic tdata[511:0]" +Toggle 0to1 tdata [96] "logic tdata[511:0]" +Toggle 1to0 tdata [96] "logic tdata[511:0]" +Toggle 0to1 tdata [97] "logic tdata[511:0]" +Toggle 1to0 tdata [97] "logic tdata[511:0]" +Toggle 0to1 tdata [98] "logic tdata[511:0]" +Toggle 1to0 tdata [98] "logic tdata[511:0]" +Toggle 0to1 tdata [99] "logic tdata[511:0]" +Toggle 1to0 tdata [99] "logic tdata[511:0]" +Toggle 0to1 tdata [100] "logic tdata[511:0]" +Toggle 1to0 tdata [100] "logic tdata[511:0]" +Toggle 0to1 tdata [101] "logic tdata[511:0]" +Toggle 1to0 tdata [101] "logic tdata[511:0]" +Toggle 0to1 tdata [102] "logic tdata[511:0]" +Toggle 1to0 tdata [102] "logic tdata[511:0]" +Toggle 0to1 tdata [103] "logic tdata[511:0]" +Toggle 1to0 tdata [103] "logic tdata[511:0]" +Toggle 0to1 tdata [104] "logic tdata[511:0]" +Toggle 1to0 tdata [104] "logic tdata[511:0]" +Toggle 0to1 tdata [105] "logic tdata[511:0]" +Toggle 1to0 tdata [105] "logic tdata[511:0]" +Toggle 0to1 tdata [106] "logic tdata[511:0]" +Toggle 1to0 tdata [106] "logic tdata[511:0]" +Toggle 0to1 tdata [107] "logic tdata[511:0]" +Toggle 1to0 tdata [107] "logic tdata[511:0]" +Toggle 0to1 tdata [108] "logic tdata[511:0]" +Toggle 1to0 tdata [108] "logic tdata[511:0]" +Toggle 0to1 tdata [109] "logic tdata[511:0]" +Toggle 1to0 tdata [109] "logic tdata[511:0]" +Toggle 0to1 tdata [110] "logic tdata[511:0]" +Toggle 1to0 tdata [110] "logic tdata[511:0]" +Toggle 0to1 tdata [111] "logic tdata[511:0]" +Toggle 1to0 tdata [111] "logic tdata[511:0]" +Toggle 0to1 tdata [112] "logic tdata[511:0]" +Toggle 1to0 tdata [112] "logic tdata[511:0]" +Toggle 0to1 tdata [113] "logic tdata[511:0]" +Toggle 1to0 tdata [113] "logic tdata[511:0]" +Toggle 0to1 tdata [114] "logic tdata[511:0]" +Toggle 1to0 tdata [114] "logic tdata[511:0]" +Toggle 0to1 tdata [115] "logic tdata[511:0]" +Toggle 1to0 tdata [115] "logic tdata[511:0]" +Toggle 0to1 tdata [116] "logic tdata[511:0]" +Toggle 1to0 tdata [116] "logic tdata[511:0]" +Toggle 0to1 tdata [117] "logic tdata[511:0]" +Toggle 1to0 tdata [117] "logic tdata[511:0]" +Toggle 0to1 tdata [118] "logic tdata[511:0]" +Toggle 1to0 tdata [118] "logic tdata[511:0]" +Toggle 0to1 tdata [119] "logic tdata[511:0]" +Toggle 1to0 tdata [119] "logic tdata[511:0]" +Toggle 0to1 tdata [120] "logic tdata[511:0]" +Toggle 1to0 tdata [120] "logic tdata[511:0]" +Toggle 0to1 tdata [121] "logic tdata[511:0]" +Toggle 1to0 tdata [121] "logic tdata[511:0]" +Toggle 0to1 tdata [122] "logic tdata[511:0]" +Toggle 1to0 tdata [122] "logic tdata[511:0]" +Toggle 0to1 tdata [123] "logic tdata[511:0]" +Toggle 1to0 tdata [123] "logic tdata[511:0]" +Toggle 0to1 tdata [124] "logic tdata[511:0]" +Toggle 1to0 tdata [124] "logic tdata[511:0]" +Toggle 0to1 tdata [125] "logic tdata[511:0]" +Toggle 1to0 tdata [125] "logic tdata[511:0]" +Toggle 0to1 tdata [126] "logic tdata[511:0]" +Toggle 1to0 tdata [126] "logic tdata[511:0]" +Toggle 0to1 tdata [127] "logic tdata[511:0]" +Toggle 1to0 tdata [127] "logic tdata[511:0]" +Toggle 0to1 tdata [128] "logic tdata[511:0]" +Toggle 1to0 tdata [128] "logic tdata[511:0]" +Toggle 0to1 tdata [129] "logic tdata[511:0]" +Toggle 1to0 tdata [129] "logic tdata[511:0]" +Toggle 0to1 tdata [130] "logic tdata[511:0]" +Toggle 1to0 tdata [130] "logic tdata[511:0]" +Toggle 0to1 tdata [131] "logic tdata[511:0]" +Toggle 1to0 tdata [131] "logic tdata[511:0]" +Toggle 0to1 tdata [132] "logic tdata[511:0]" +Toggle 1to0 tdata [132] "logic tdata[511:0]" +Toggle 0to1 tdata [133] "logic tdata[511:0]" +Toggle 1to0 tdata [133] "logic tdata[511:0]" +Toggle 0to1 tdata [134] "logic tdata[511:0]" +Toggle 1to0 tdata [134] "logic tdata[511:0]" +Toggle 0to1 tdata [135] "logic tdata[511:0]" +Toggle 1to0 tdata [135] "logic tdata[511:0]" +Toggle 0to1 tdata [136] "logic tdata[511:0]" +Toggle 1to0 tdata [136] "logic tdata[511:0]" +Toggle 0to1 tdata [137] "logic tdata[511:0]" +Toggle 1to0 tdata [137] "logic tdata[511:0]" +Toggle 0to1 tdata [138] "logic tdata[511:0]" +Toggle 1to0 tdata [138] "logic tdata[511:0]" +Toggle 0to1 tdata [139] "logic tdata[511:0]" +Toggle 1to0 tdata [139] "logic tdata[511:0]" +Toggle 0to1 tdata [140] "logic tdata[511:0]" +Toggle 1to0 tdata [140] "logic tdata[511:0]" +Toggle 0to1 tdata [141] "logic tdata[511:0]" +Toggle 1to0 tdata [141] "logic tdata[511:0]" +Toggle 0to1 tdata [142] "logic tdata[511:0]" +Toggle 1to0 tdata [142] "logic tdata[511:0]" +Toggle 0to1 tdata [143] "logic tdata[511:0]" +Toggle 1to0 tdata [143] "logic tdata[511:0]" +Toggle 0to1 tdata [144] "logic tdata[511:0]" +Toggle 1to0 tdata [144] "logic tdata[511:0]" +Toggle 0to1 tdata [145] "logic tdata[511:0]" +Toggle 1to0 tdata [145] "logic tdata[511:0]" +Toggle 0to1 tdata [146] "logic tdata[511:0]" +Toggle 1to0 tdata [146] "logic tdata[511:0]" +Toggle 0to1 tdata [147] "logic tdata[511:0]" +Toggle 1to0 tdata [147] "logic tdata[511:0]" +Toggle 0to1 tdata [148] "logic tdata[511:0]" +Toggle 1to0 tdata [148] "logic tdata[511:0]" +Toggle 0to1 tdata [149] "logic tdata[511:0]" +Toggle 1to0 tdata [149] "logic tdata[511:0]" +Toggle 0to1 tdata [150] "logic tdata[511:0]" +Toggle 1to0 tdata [150] "logic tdata[511:0]" +Toggle 0to1 tdata [151] "logic tdata[511:0]" +Toggle 1to0 tdata [151] "logic tdata[511:0]" +Toggle 0to1 tdata [152] "logic tdata[511:0]" +Toggle 1to0 tdata [152] "logic tdata[511:0]" +Toggle 0to1 tdata [153] "logic tdata[511:0]" +Toggle 1to0 tdata [153] "logic tdata[511:0]" +Toggle 0to1 tdata [154] "logic tdata[511:0]" +Toggle 1to0 tdata [154] "logic tdata[511:0]" +Toggle 0to1 tdata [155] "logic tdata[511:0]" +Toggle 1to0 tdata [155] "logic tdata[511:0]" +Toggle 0to1 tdata [156] "logic tdata[511:0]" +Toggle 1to0 tdata [156] "logic tdata[511:0]" +Toggle 0to1 tdata [157] "logic tdata[511:0]" +Toggle 1to0 tdata [157] "logic tdata[511:0]" +Toggle 0to1 tdata [158] "logic tdata[511:0]" +Toggle 1to0 tdata [158] "logic tdata[511:0]" +Toggle 0to1 tdata [159] "logic tdata[511:0]" +Toggle 1to0 tdata [159] "logic tdata[511:0]" +Toggle 0to1 tdata [160] "logic tdata[511:0]" +Toggle 1to0 tdata [160] "logic tdata[511:0]" +Toggle 0to1 tdata [161] "logic tdata[511:0]" +Toggle 1to0 tdata [161] "logic tdata[511:0]" +Toggle 0to1 tdata [162] "logic tdata[511:0]" +Toggle 1to0 tdata [162] "logic tdata[511:0]" +Toggle 0to1 tdata [163] "logic tdata[511:0]" +Toggle 1to0 tdata [163] "logic tdata[511:0]" +Toggle 0to1 tdata [165] "logic tdata[511:0]" +Toggle 1to0 tdata [165] "logic tdata[511:0]" +Toggle 0to1 tdata [166] "logic tdata[511:0]" +Toggle 1to0 tdata [166] "logic tdata[511:0]" +Toggle 0to1 tdata [167] "logic tdata[511:0]" +Toggle 1to0 tdata [167] "logic tdata[511:0]" +Toggle 0to1 tdata [168] "logic tdata[511:0]" +Toggle 1to0 tdata [168] "logic tdata[511:0]" +Toggle 0to1 tdata [169] "logic tdata[511:0]" +Toggle 1to0 tdata [169] "logic tdata[511:0]" +Toggle 0to1 tdata [170] "logic tdata[511:0]" +Toggle 1to0 tdata [170] "logic tdata[511:0]" +Toggle 0to1 tdata [171] "logic tdata[511:0]" +Toggle 1to0 tdata [171] "logic tdata[511:0]" +Toggle 0to1 tdata [172] "logic tdata[511:0]" +Toggle 1to0 tdata [172] "logic tdata[511:0]" +Toggle 0to1 tdata [173] "logic tdata[511:0]" +Toggle 1to0 tdata [173] "logic tdata[511:0]" +Toggle 0to1 tdata [175] "logic tdata[511:0]" +Toggle 1to0 tdata [175] "logic tdata[511:0]" +Toggle 0to1 tdata [176] "logic tdata[511:0]" +Toggle 1to0 tdata [176] "logic tdata[511:0]" +Toggle 0to1 tdata [177] "logic tdata[511:0]" +Toggle 1to0 tdata [177] "logic tdata[511:0]" +Toggle 0to1 tdata [178] "logic tdata[511:0]" +Toggle 1to0 tdata [178] "logic tdata[511:0]" +Toggle 0to1 tdata [179] "logic tdata[511:0]" +Toggle 1to0 tdata [179] "logic tdata[511:0]" +Toggle 0to1 tdata [180] "logic tdata[511:0]" +Toggle 1to0 tdata [180] "logic tdata[511:0]" +Toggle 0to1 tdata [181] "logic tdata[511:0]" +Toggle 1to0 tdata [181] "logic tdata[511:0]" +Toggle 0to1 tdata [182] "logic tdata[511:0]" +Toggle 1to0 tdata [182] "logic tdata[511:0]" +Toggle 0to1 tdata [183] "logic tdata[511:0]" +Toggle 1to0 tdata [183] "logic tdata[511:0]" +Toggle 0to1 tdata [184] "logic tdata[511:0]" +Toggle 1to0 tdata [184] "logic tdata[511:0]" +Toggle 0to1 tdata [185] "logic tdata[511:0]" +Toggle 1to0 tdata [185] "logic tdata[511:0]" +Toggle 0to1 tdata [186] "logic tdata[511:0]" +Toggle 1to0 tdata [186] "logic tdata[511:0]" +Toggle 0to1 tdata [187] "logic tdata[511:0]" +Toggle 1to0 tdata [187] "logic tdata[511:0]" +Toggle 0to1 tdata [188] "logic tdata[511:0]" +Toggle 1to0 tdata [188] "logic tdata[511:0]" +Toggle 0to1 tdata [189] "logic tdata[511:0]" +Toggle 1to0 tdata [189] "logic tdata[511:0]" +Toggle 0to1 tdata [190] "logic tdata[511:0]" +Toggle 1to0 tdata [190] "logic tdata[511:0]" +Toggle 0to1 tdata [191] "logic tdata[511:0]" +Toggle 1to0 tdata [191] "logic tdata[511:0]" +Toggle 0to1 tdata [192] "logic tdata[511:0]" +Toggle 1to0 tdata [192] "logic tdata[511:0]" +Toggle 0to1 tdata [193] "logic tdata[511:0]" +Toggle 1to0 tdata [193] "logic tdata[511:0]" +Toggle 0to1 tdata [194] "logic tdata[511:0]" +Toggle 1to0 tdata [194] "logic tdata[511:0]" +Toggle 0to1 tdata [195] "logic tdata[511:0]" +Toggle 1to0 tdata [195] "logic tdata[511:0]" +Toggle 0to1 tdata [196] "logic tdata[511:0]" +Toggle 1to0 tdata [196] "logic tdata[511:0]" +Toggle 0to1 tdata [197] "logic tdata[511:0]" +Toggle 1to0 tdata [197] "logic tdata[511:0]" +Toggle 0to1 tdata [198] "logic tdata[511:0]" +Toggle 1to0 tdata [198] "logic tdata[511:0]" +Toggle 0to1 tdata [199] "logic tdata[511:0]" +Toggle 1to0 tdata [199] "logic tdata[511:0]" +Toggle 0to1 tdata [200] "logic tdata[511:0]" +Toggle 1to0 tdata [200] "logic tdata[511:0]" +Toggle 0to1 tdata [201] "logic tdata[511:0]" +Toggle 1to0 tdata [201] "logic tdata[511:0]" +Toggle 0to1 tdata [202] "logic tdata[511:0]" +Toggle 1to0 tdata [202] "logic tdata[511:0]" +Toggle 0to1 tdata [203] "logic tdata[511:0]" +Toggle 1to0 tdata [203] "logic tdata[511:0]" +Toggle 0to1 tdata [204] "logic tdata[511:0]" +Toggle 1to0 tdata [204] "logic tdata[511:0]" +Toggle 0to1 tdata [205] "logic tdata[511:0]" +Toggle 1to0 tdata [205] "logic tdata[511:0]" +Toggle 0to1 tdata [206] "logic tdata[511:0]" +Toggle 1to0 tdata [206] "logic tdata[511:0]" +Toggle 0to1 tdata [207] "logic tdata[511:0]" +Toggle 1to0 tdata [207] "logic tdata[511:0]" +Toggle 0to1 tdata [208] "logic tdata[511:0]" +Toggle 1to0 tdata [208] "logic tdata[511:0]" +Toggle 0to1 tdata [209] "logic tdata[511:0]" +Toggle 1to0 tdata [209] "logic tdata[511:0]" +Toggle 0to1 tdata [210] "logic tdata[511:0]" +Toggle 1to0 tdata [210] "logic tdata[511:0]" +Toggle 0to1 tdata [211] "logic tdata[511:0]" +Toggle 1to0 tdata [211] "logic tdata[511:0]" +Toggle 0to1 tdata [212] "logic tdata[511:0]" +Toggle 1to0 tdata [212] "logic tdata[511:0]" +Toggle 0to1 tdata [213] "logic tdata[511:0]" +Toggle 1to0 tdata [213] "logic tdata[511:0]" +Toggle 0to1 tdata [214] "logic tdata[511:0]" +Toggle 1to0 tdata [214] "logic tdata[511:0]" +Toggle 0to1 tdata [215] "logic tdata[511:0]" +Toggle 1to0 tdata [215] "logic tdata[511:0]" +Toggle 0to1 tdata [216] "logic tdata[511:0]" +Toggle 1to0 tdata [216] "logic tdata[511:0]" +Toggle 0to1 tdata [217] "logic tdata[511:0]" +Toggle 1to0 tdata [217] "logic tdata[511:0]" +Toggle 0to1 tdata [218] "logic tdata[511:0]" +Toggle 1to0 tdata [218] "logic tdata[511:0]" +Toggle 0to1 tdata [219] "logic tdata[511:0]" +Toggle 1to0 tdata [219] "logic tdata[511:0]" +Toggle 0to1 tdata [220] "logic tdata[511:0]" +Toggle 1to0 tdata [220] "logic tdata[511:0]" +Toggle 0to1 tdata [221] "logic tdata[511:0]" +Toggle 1to0 tdata [221] "logic tdata[511:0]" +Toggle 0to1 tdata [222] "logic tdata[511:0]" +Toggle 1to0 tdata [222] "logic tdata[511:0]" +Toggle 0to1 tdata [223] "logic tdata[511:0]" +Toggle 1to0 tdata [223] "logic tdata[511:0]" +Toggle 0to1 tdata [224] "logic tdata[511:0]" +Toggle 1to0 tdata [224] "logic tdata[511:0]" +Toggle 0to1 tdata [225] "logic tdata[511:0]" +Toggle 1to0 tdata [225] "logic tdata[511:0]" +Toggle 0to1 tdata [226] "logic tdata[511:0]" +Toggle 1to0 tdata [226] "logic tdata[511:0]" +Toggle 0to1 tdata [227] "logic tdata[511:0]" +Toggle 1to0 tdata [227] "logic tdata[511:0]" +Toggle 0to1 tdata [228] "logic tdata[511:0]" +Toggle 1to0 tdata [228] "logic tdata[511:0]" +Toggle 0to1 tdata [229] "logic tdata[511:0]" +Toggle 1to0 tdata [229] "logic tdata[511:0]" +Toggle 0to1 tdata [230] "logic tdata[511:0]" +Toggle 1to0 tdata [230] "logic tdata[511:0]" +Toggle 0to1 tdata [231] "logic tdata[511:0]" +Toggle 1to0 tdata [231] "logic tdata[511:0]" +Toggle 0to1 tdata [232] "logic tdata[511:0]" +Toggle 1to0 tdata [232] "logic tdata[511:0]" +Toggle 0to1 tdata [233] "logic tdata[511:0]" +Toggle 1to0 tdata [233] "logic tdata[511:0]" +Toggle 0to1 tdata [234] "logic tdata[511:0]" +Toggle 1to0 tdata [234] "logic tdata[511:0]" +Toggle 0to1 tdata [235] "logic tdata[511:0]" +Toggle 1to0 tdata [235] "logic tdata[511:0]" +Toggle 0to1 tdata [236] "logic tdata[511:0]" +Toggle 1to0 tdata [236] "logic tdata[511:0]" +Toggle 0to1 tdata [237] "logic tdata[511:0]" +Toggle 1to0 tdata [237] "logic tdata[511:0]" +Toggle 0to1 tdata [238] "logic tdata[511:0]" +Toggle 1to0 tdata [238] "logic tdata[511:0]" +Toggle 0to1 tdata [239] "logic tdata[511:0]" +Toggle 1to0 tdata [239] "logic tdata[511:0]" +Toggle 0to1 tdata [240] "logic tdata[511:0]" +Toggle 1to0 tdata [240] "logic tdata[511:0]" +Toggle 0to1 tdata [241] "logic tdata[511:0]" +Toggle 1to0 tdata [241] "logic tdata[511:0]" +Toggle 0to1 tdata [242] "logic tdata[511:0]" +Toggle 1to0 tdata [242] "logic tdata[511:0]" +Toggle 0to1 tdata [243] "logic tdata[511:0]" +Toggle 1to0 tdata [243] "logic tdata[511:0]" +Toggle 0to1 tdata [244] "logic tdata[511:0]" +Toggle 1to0 tdata [244] "logic tdata[511:0]" +Toggle 0to1 tdata [245] "logic tdata[511:0]" +Toggle 1to0 tdata [245] "logic tdata[511:0]" +Toggle 0to1 tdata [246] "logic tdata[511:0]" +Toggle 1to0 tdata [246] "logic tdata[511:0]" +Toggle 0to1 tdata [247] "logic tdata[511:0]" +Toggle 1to0 tdata [247] "logic tdata[511:0]" +Toggle 0to1 tdata [248] "logic tdata[511:0]" +Toggle 1to0 tdata [248] "logic tdata[511:0]" +Toggle 0to1 tdata [249] "logic tdata[511:0]" +Toggle 1to0 tdata [249] "logic tdata[511:0]" +Toggle 0to1 tdata [250] "logic tdata[511:0]" +Toggle 1to0 tdata [250] "logic tdata[511:0]" +Toggle 0to1 tdata [251] "logic tdata[511:0]" +Toggle 1to0 tdata [251] "logic tdata[511:0]" +Toggle 0to1 tdata [252] "logic tdata[511:0]" +Toggle 1to0 tdata [252] "logic tdata[511:0]" +Toggle 0to1 tdata [253] "logic tdata[511:0]" +Toggle 1to0 tdata [253] "logic tdata[511:0]" +Toggle 0to1 tdata [254] "logic tdata[511:0]" +Toggle 1to0 tdata [254] "logic tdata[511:0]" +Toggle 0to1 tdata [255] "logic tdata[511:0]" +Toggle 1to0 tdata [255] "logic tdata[511:0]" +Toggle 0to1 tdata [320] "logic tdata[511:0]" +Toggle 1to0 tdata [320] "logic tdata[511:0]" +Toggle 0to1 tdata [321] "logic tdata[511:0]" +Toggle 1to0 tdata [321] "logic tdata[511:0]" +Toggle 0to1 tdata [322] "logic tdata[511:0]" +Toggle 1to0 tdata [322] "logic tdata[511:0]" +Toggle 0to1 tdata [323] "logic tdata[511:0]" +Toggle 1to0 tdata [323] "logic tdata[511:0]" +Toggle 0to1 tdata [324] "logic tdata[511:0]" +Toggle 1to0 tdata [324] "logic tdata[511:0]" +Toggle 0to1 tdata [325] "logic tdata[511:0]" +Toggle 1to0 tdata [325] "logic tdata[511:0]" +Toggle 0to1 tdata [326] "logic tdata[511:0]" +Toggle 1to0 tdata [326] "logic tdata[511:0]" +Toggle 0to1 tdata [327] "logic tdata[511:0]" +Toggle 1to0 tdata [327] "logic tdata[511:0]" +Toggle 0to1 tdata [328] "logic tdata[511:0]" +Toggle 1to0 tdata [328] "logic tdata[511:0]" +Toggle 0to1 tdata [329] "logic tdata[511:0]" +Toggle 1to0 tdata [329] "logic tdata[511:0]" +Toggle 0to1 tdata [330] "logic tdata[511:0]" +Toggle 1to0 tdata [330] "logic tdata[511:0]" +Toggle 0to1 tdata [331] "logic tdata[511:0]" +Toggle 1to0 tdata [331] "logic tdata[511:0]" +Toggle 0to1 tdata [332] "logic tdata[511:0]" +Toggle 1to0 tdata [332] "logic tdata[511:0]" +Toggle 0to1 tdata [333] "logic tdata[511:0]" +Toggle 1to0 tdata [333] "logic tdata[511:0]" +Toggle 0to1 tdata [334] "logic tdata[511:0]" +Toggle 1to0 tdata [334] "logic tdata[511:0]" +Toggle 0to1 tdata [335] "logic tdata[511:0]" +Toggle 1to0 tdata [335] "logic tdata[511:0]" +Toggle 0to1 tdata [336] "logic tdata[511:0]" +Toggle 1to0 tdata [336] "logic tdata[511:0]" +Toggle 0to1 tdata [337] "logic tdata[511:0]" +Toggle 1to0 tdata [337] "logic tdata[511:0]" +Toggle 0to1 tdata [338] "logic tdata[511:0]" +Toggle 1to0 tdata [338] "logic tdata[511:0]" +Toggle 0to1 tdata [339] "logic tdata[511:0]" +Toggle 1to0 tdata [339] "logic tdata[511:0]" +Toggle 0to1 tdata [340] "logic tdata[511:0]" +Toggle 1to0 tdata [340] "logic tdata[511:0]" +Toggle 0to1 tdata [341] "logic tdata[511:0]" +Toggle 1to0 tdata [341] "logic tdata[511:0]" +Toggle 0to1 tdata [342] "logic tdata[511:0]" +Toggle 1to0 tdata [342] "logic tdata[511:0]" +Toggle 0to1 tdata [343] "logic tdata[511:0]" +Toggle 1to0 tdata [343] "logic tdata[511:0]" +Toggle 0to1 tdata [344] "logic tdata[511:0]" +Toggle 1to0 tdata [344] "logic tdata[511:0]" +Toggle 0to1 tdata [345] "logic tdata[511:0]" +Toggle 1to0 tdata [345] "logic tdata[511:0]" +Toggle 0to1 tdata [346] "logic tdata[511:0]" +Toggle 1to0 tdata [346] "logic tdata[511:0]" +Toggle 0to1 tdata [347] "logic tdata[511:0]" +Toggle 1to0 tdata [347] "logic tdata[511:0]" +Toggle 0to1 tdata [348] "logic tdata[511:0]" +Toggle 1to0 tdata [348] "logic tdata[511:0]" +Toggle 0to1 tdata [349] "logic tdata[511:0]" +Toggle 1to0 tdata [349] "logic tdata[511:0]" +Toggle 0to1 tdata [350] "logic tdata[511:0]" +Toggle 1to0 tdata [350] "logic tdata[511:0]" +Toggle 0to1 tdata [351] "logic tdata[511:0]" +Toggle 1to0 tdata [351] "logic tdata[511:0]" +Toggle 0to1 tdata [352] "logic tdata[511:0]" +Toggle 1to0 tdata [352] "logic tdata[511:0]" +Toggle 0to1 tdata [353] "logic tdata[511:0]" +Toggle 1to0 tdata [353] "logic tdata[511:0]" +Toggle 0to1 tdata [354] "logic tdata[511:0]" +Toggle 1to0 tdata [354] "logic tdata[511:0]" +Toggle 0to1 tdata [355] "logic tdata[511:0]" +Toggle 1to0 tdata [355] "logic tdata[511:0]" +Toggle 0to1 tdata [356] "logic tdata[511:0]" +Toggle 1to0 tdata [356] "logic tdata[511:0]" +Toggle 0to1 tdata [357] "logic tdata[511:0]" +Toggle 1to0 tdata [357] "logic tdata[511:0]" +Toggle 0to1 tdata [358] "logic tdata[511:0]" +Toggle 1to0 tdata [358] "logic tdata[511:0]" +Toggle 0to1 tdata [359] "logic tdata[511:0]" +Toggle 1to0 tdata [359] "logic tdata[511:0]" +Toggle 0to1 tdata [360] "logic tdata[511:0]" +Toggle 1to0 tdata [360] "logic tdata[511:0]" +Toggle 0to1 tdata [361] "logic tdata[511:0]" +Toggle 1to0 tdata [361] "logic tdata[511:0]" +Toggle 0to1 tdata [362] "logic tdata[511:0]" +Toggle 1to0 tdata [362] "logic tdata[511:0]" +Toggle 0to1 tdata [363] "logic tdata[511:0]" +Toggle 1to0 tdata [363] "logic tdata[511:0]" +Toggle 0to1 tdata [364] "logic tdata[511:0]" +Toggle 1to0 tdata [364] "logic tdata[511:0]" +Toggle 0to1 tdata [365] "logic tdata[511:0]" +Toggle 1to0 tdata [365] "logic tdata[511:0]" +Toggle 0to1 tdata [366] "logic tdata[511:0]" +Toggle 1to0 tdata [366] "logic tdata[511:0]" +Toggle 0to1 tdata [367] "logic tdata[511:0]" +Toggle 1to0 tdata [367] "logic tdata[511:0]" +Toggle 0to1 tdata [368] "logic tdata[511:0]" +Toggle 1to0 tdata [368] "logic tdata[511:0]" +Toggle 0to1 tdata [369] "logic tdata[511:0]" +Toggle 1to0 tdata [369] "logic tdata[511:0]" +Toggle 0to1 tdata [370] "logic tdata[511:0]" +Toggle 1to0 tdata [370] "logic tdata[511:0]" +Toggle 0to1 tdata [371] "logic tdata[511:0]" +Toggle 1to0 tdata [371] "logic tdata[511:0]" +Toggle 0to1 tdata [372] "logic tdata[511:0]" +Toggle 1to0 tdata [372] "logic tdata[511:0]" +Toggle 0to1 tdata [373] "logic tdata[511:0]" +Toggle 1to0 tdata [373] "logic tdata[511:0]" +Toggle 0to1 tdata [374] "logic tdata[511:0]" +Toggle 1to0 tdata [374] "logic tdata[511:0]" +Toggle 0to1 tdata [375] "logic tdata[511:0]" +Toggle 1to0 tdata [375] "logic tdata[511:0]" +Toggle 0to1 tdata [376] "logic tdata[511:0]" +Toggle 1to0 tdata [376] "logic tdata[511:0]" +Toggle 0to1 tdata [377] "logic tdata[511:0]" +Toggle 1to0 tdata [377] "logic tdata[511:0]" +Toggle 0to1 tdata [378] "logic tdata[511:0]" +Toggle 1to0 tdata [378] "logic tdata[511:0]" +Toggle 0to1 tdata [379] "logic tdata[511:0]" +Toggle 1to0 tdata [379] "logic tdata[511:0]" +Toggle 0to1 tdata [380] "logic tdata[511:0]" +Toggle 1to0 tdata [380] "logic tdata[511:0]" +Toggle 0to1 tdata [381] "logic tdata[511:0]" +Toggle 1to0 tdata [381] "logic tdata[511:0]" +Toggle 0to1 tdata [382] "logic tdata[511:0]" +Toggle 1to0 tdata [382] "logic tdata[511:0]" +Toggle 0to1 tdata [383] "logic tdata[511:0]" +Toggle 1to0 tdata [383] "logic tdata[511:0]" +Toggle 0to1 tdata [384] "logic tdata[511:0]" +Toggle 1to0 tdata [384] "logic tdata[511:0]" +Toggle 0to1 tdata [385] "logic tdata[511:0]" +Toggle 1to0 tdata [385] "logic tdata[511:0]" +Toggle 0to1 tdata [386] "logic tdata[511:0]" +Toggle 1to0 tdata [386] "logic tdata[511:0]" +Toggle 0to1 tdata [387] "logic tdata[511:0]" +Toggle 1to0 tdata [387] "logic tdata[511:0]" +Toggle 0to1 tdata [388] "logic tdata[511:0]" +Toggle 1to0 tdata [388] "logic tdata[511:0]" +Toggle 0to1 tdata [389] "logic tdata[511:0]" +Toggle 1to0 tdata [389] "logic tdata[511:0]" +Toggle 0to1 tdata [390] "logic tdata[511:0]" +Toggle 1to0 tdata [390] "logic tdata[511:0]" +Toggle 0to1 tdata [391] "logic tdata[511:0]" +Toggle 1to0 tdata [391] "logic tdata[511:0]" +Toggle 0to1 tdata [392] "logic tdata[511:0]" +Toggle 1to0 tdata [392] "logic tdata[511:0]" +Toggle 0to1 tdata [393] "logic tdata[511:0]" +Toggle 1to0 tdata [393] "logic tdata[511:0]" +Toggle 0to1 tdata [394] "logic tdata[511:0]" +Toggle 1to0 tdata [394] "logic tdata[511:0]" +Toggle 0to1 tdata [395] "logic tdata[511:0]" +Toggle 1to0 tdata [395] "logic tdata[511:0]" +Toggle 0to1 tdata [396] "logic tdata[511:0]" +Toggle 1to0 tdata [396] "logic tdata[511:0]" +Toggle 0to1 tdata [397] "logic tdata[511:0]" +Toggle 1to0 tdata [397] "logic tdata[511:0]" +Toggle 0to1 tdata [398] "logic tdata[511:0]" +Toggle 1to0 tdata [398] "logic tdata[511:0]" +Toggle 0to1 tdata [399] "logic tdata[511:0]" +Toggle 1to0 tdata [399] "logic tdata[511:0]" +Toggle 0to1 tdata [400] "logic tdata[511:0]" +Toggle 1to0 tdata [400] "logic tdata[511:0]" +Toggle 0to1 tdata [401] "logic tdata[511:0]" +Toggle 1to0 tdata [401] "logic tdata[511:0]" +Toggle 0to1 tdata [402] "logic tdata[511:0]" +Toggle 1to0 tdata [402] "logic tdata[511:0]" +Toggle 0to1 tdata [403] "logic tdata[511:0]" +Toggle 1to0 tdata [403] "logic tdata[511:0]" +Toggle 0to1 tdata [404] "logic tdata[511:0]" +Toggle 1to0 tdata [404] "logic tdata[511:0]" +Toggle 0to1 tdata [405] "logic tdata[511:0]" +Toggle 1to0 tdata [405] "logic tdata[511:0]" +Toggle 0to1 tdata [406] "logic tdata[511:0]" +Toggle 1to0 tdata [406] "logic tdata[511:0]" +Toggle 0to1 tdata [407] "logic tdata[511:0]" +Toggle 1to0 tdata [407] "logic tdata[511:0]" +Toggle 0to1 tdata [408] "logic tdata[511:0]" +Toggle 1to0 tdata [408] "logic tdata[511:0]" +Toggle 0to1 tdata [409] "logic tdata[511:0]" +Toggle 1to0 tdata [409] "logic tdata[511:0]" +Toggle 0to1 tdata [410] "logic tdata[511:0]" +Toggle 1to0 tdata [410] "logic tdata[511:0]" +Toggle 0to1 tdata [411] "logic tdata[511:0]" +Toggle 1to0 tdata [411] "logic tdata[511:0]" +Toggle 0to1 tdata [412] "logic tdata[511:0]" +Toggle 1to0 tdata [412] "logic tdata[511:0]" +Toggle 0to1 tdata [413] "logic tdata[511:0]" +Toggle 1to0 tdata [413] "logic tdata[511:0]" +Toggle 0to1 tdata [414] "logic tdata[511:0]" +Toggle 1to0 tdata [414] "logic tdata[511:0]" +Toggle 0to1 tdata [415] "logic tdata[511:0]" +Toggle 1to0 tdata [415] "logic tdata[511:0]" +Toggle 0to1 tdata [416] "logic tdata[511:0]" +Toggle 1to0 tdata [416] "logic tdata[511:0]" +Toggle 0to1 tdata [417] "logic tdata[511:0]" +Toggle 1to0 tdata [417] "logic tdata[511:0]" +Toggle 0to1 tdata [418] "logic tdata[511:0]" +Toggle 1to0 tdata [418] "logic tdata[511:0]" +Toggle 0to1 tdata [419] "logic tdata[511:0]" +Toggle 1to0 tdata [419] "logic tdata[511:0]" +Toggle 0to1 tdata [420] "logic tdata[511:0]" +Toggle 1to0 tdata [420] "logic tdata[511:0]" +Toggle 0to1 tdata [421] "logic tdata[511:0]" +Toggle 1to0 tdata [421] "logic tdata[511:0]" +Toggle 0to1 tdata [422] "logic tdata[511:0]" +Toggle 1to0 tdata [422] "logic tdata[511:0]" +Toggle 0to1 tdata [423] "logic tdata[511:0]" +Toggle 1to0 tdata [423] "logic tdata[511:0]" +Toggle 0to1 tdata [424] "logic tdata[511:0]" +Toggle 1to0 tdata [424] "logic tdata[511:0]" +Toggle 0to1 tdata [425] "logic tdata[511:0]" +Toggle 1to0 tdata [425] "logic tdata[511:0]" +Toggle 0to1 tdata [426] "logic tdata[511:0]" +Toggle 1to0 tdata [426] "logic tdata[511:0]" +Toggle 0to1 tdata [427] "logic tdata[511:0]" +Toggle 1to0 tdata [427] "logic tdata[511:0]" +Toggle 0to1 tdata [428] "logic tdata[511:0]" +Toggle 1to0 tdata [428] "logic tdata[511:0]" +Toggle 0to1 tdata [429] "logic tdata[511:0]" +Toggle 1to0 tdata [429] "logic tdata[511:0]" +Toggle 0to1 tdata [430] "logic tdata[511:0]" +Toggle 1to0 tdata [430] "logic tdata[511:0]" +Toggle 0to1 tdata [431] "logic tdata[511:0]" +Toggle 1to0 tdata [431] "logic tdata[511:0]" +Toggle 0to1 tdata [432] "logic tdata[511:0]" +Toggle 1to0 tdata [432] "logic tdata[511:0]" +Toggle 0to1 tdata [433] "logic tdata[511:0]" +Toggle 1to0 tdata [433] "logic tdata[511:0]" +Toggle 0to1 tdata [434] "logic tdata[511:0]" +Toggle 1to0 tdata [434] "logic tdata[511:0]" +Toggle 0to1 tdata [435] "logic tdata[511:0]" +Toggle 1to0 tdata [435] "logic tdata[511:0]" +Toggle 0to1 tdata [436] "logic tdata[511:0]" +Toggle 1to0 tdata [436] "logic tdata[511:0]" +Toggle 0to1 tdata [437] "logic tdata[511:0]" +Toggle 1to0 tdata [437] "logic tdata[511:0]" +Toggle 0to1 tdata [438] "logic tdata[511:0]" +Toggle 1to0 tdata [438] "logic tdata[511:0]" +Toggle 0to1 tdata [439] "logic tdata[511:0]" +Toggle 1to0 tdata [439] "logic tdata[511:0]" +Toggle 0to1 tdata [440] "logic tdata[511:0]" +Toggle 1to0 tdata [440] "logic tdata[511:0]" +Toggle 0to1 tdata [441] "logic tdata[511:0]" +Toggle 1to0 tdata [441] "logic tdata[511:0]" +Toggle 0to1 tdata [442] "logic tdata[511:0]" +Toggle 1to0 tdata [442] "logic tdata[511:0]" +Toggle 0to1 tdata [443] "logic tdata[511:0]" +Toggle 1to0 tdata [443] "logic tdata[511:0]" +Toggle 0to1 tdata [444] "logic tdata[511:0]" +Toggle 1to0 tdata [444] "logic tdata[511:0]" +Toggle 0to1 tdata [445] "logic tdata[511:0]" +Toggle 1to0 tdata [445] "logic tdata[511:0]" +Toggle 0to1 tdata [446] "logic tdata[511:0]" +Toggle 1to0 tdata [446] "logic tdata[511:0]" +Toggle 0to1 tdata [447] "logic tdata[511:0]" +Toggle 1to0 tdata [447] "logic tdata[511:0]" +Toggle 0to1 tdata [448] "logic tdata[511:0]" +Toggle 1to0 tdata [448] "logic tdata[511:0]" +Toggle 0to1 tdata [449] "logic tdata[511:0]" +Toggle 1to0 tdata [449] "logic tdata[511:0]" +Toggle 0to1 tdata [450] "logic tdata[511:0]" +Toggle 1to0 tdata [450] "logic tdata[511:0]" +Toggle 0to1 tdata [451] "logic tdata[511:0]" +Toggle 1to0 tdata [451] "logic tdata[511:0]" +Toggle 0to1 tdata [452] "logic tdata[511:0]" +Toggle 1to0 tdata [452] "logic tdata[511:0]" +Toggle 0to1 tdata [453] "logic tdata[511:0]" +Toggle 1to0 tdata [453] "logic tdata[511:0]" +Toggle 0to1 tdata [454] "logic tdata[511:0]" +Toggle 1to0 tdata [454] "logic tdata[511:0]" +Toggle 0to1 tdata [455] "logic tdata[511:0]" +Toggle 1to0 tdata [455] "logic tdata[511:0]" +Toggle 0to1 tdata [456] "logic tdata[511:0]" +Toggle 1to0 tdata [456] "logic tdata[511:0]" +Toggle 0to1 tdata [457] "logic tdata[511:0]" +Toggle 1to0 tdata [457] "logic tdata[511:0]" +Toggle 0to1 tdata [458] "logic tdata[511:0]" +Toggle 1to0 tdata [458] "logic tdata[511:0]" +Toggle 0to1 tdata [459] "logic tdata[511:0]" +Toggle 1to0 tdata [459] "logic tdata[511:0]" +Toggle 0to1 tdata [460] "logic tdata[511:0]" +Toggle 1to0 tdata [460] "logic tdata[511:0]" +Toggle 0to1 tdata [461] "logic tdata[511:0]" +Toggle 1to0 tdata [461] "logic tdata[511:0]" +Toggle 0to1 tdata [462] "logic tdata[511:0]" +Toggle 1to0 tdata [462] "logic tdata[511:0]" +Toggle 0to1 tdata [463] "logic tdata[511:0]" +Toggle 1to0 tdata [463] "logic tdata[511:0]" +Toggle 0to1 tdata [464] "logic tdata[511:0]" +Toggle 1to0 tdata [464] "logic tdata[511:0]" +Toggle 0to1 tdata [465] "logic tdata[511:0]" +Toggle 1to0 tdata [465] "logic tdata[511:0]" +Toggle 0to1 tdata [466] "logic tdata[511:0]" +Toggle 1to0 tdata [466] "logic tdata[511:0]" +Toggle 0to1 tdata [467] "logic tdata[511:0]" +Toggle 1to0 tdata [467] "logic tdata[511:0]" +Toggle 0to1 tdata [468] "logic tdata[511:0]" +Toggle 1to0 tdata [468] "logic tdata[511:0]" +Toggle 0to1 tdata [469] "logic tdata[511:0]" +Toggle 1to0 tdata [469] "logic tdata[511:0]" +Toggle 0to1 tdata [470] "logic tdata[511:0]" +Toggle 1to0 tdata [470] "logic tdata[511:0]" +Toggle 0to1 tdata [471] "logic tdata[511:0]" +Toggle 1to0 tdata [471] "logic tdata[511:0]" +Toggle 0to1 tdata [472] "logic tdata[511:0]" +Toggle 1to0 tdata [472] "logic tdata[511:0]" +Toggle 0to1 tdata [473] "logic tdata[511:0]" +Toggle 1to0 tdata [473] "logic tdata[511:0]" +Toggle 0to1 tdata [474] "logic tdata[511:0]" +Toggle 1to0 tdata [474] "logic tdata[511:0]" +Toggle 0to1 tdata [475] "logic tdata[511:0]" +Toggle 1to0 tdata [475] "logic tdata[511:0]" +Toggle 0to1 tdata [476] "logic tdata[511:0]" +Toggle 1to0 tdata [476] "logic tdata[511:0]" +Toggle 0to1 tdata [477] "logic tdata[511:0]" +Toggle 1to0 tdata [477] "logic tdata[511:0]" +Toggle 0to1 tdata [478] "logic tdata[511:0]" +Toggle 1to0 tdata [478] "logic tdata[511:0]" +Toggle 0to1 tdata [479] "logic tdata[511:0]" +Toggle 1to0 tdata [479] "logic tdata[511:0]" +Toggle 0to1 tdata [480] "logic tdata[511:0]" +Toggle 1to0 tdata [480] "logic tdata[511:0]" +Toggle 0to1 tdata [481] "logic tdata[511:0]" +Toggle 1to0 tdata [481] "logic tdata[511:0]" +Toggle 0to1 tdata [482] "logic tdata[511:0]" +Toggle 1to0 tdata [482] "logic tdata[511:0]" +Toggle 0to1 tdata [483] "logic tdata[511:0]" +Toggle 1to0 tdata [483] "logic tdata[511:0]" +Toggle 0to1 tdata [484] "logic tdata[511:0]" +Toggle 1to0 tdata [484] "logic tdata[511:0]" +Toggle 0to1 tdata [485] "logic tdata[511:0]" +Toggle 1to0 tdata [485] "logic tdata[511:0]" +Toggle 0to1 tdata [486] "logic tdata[511:0]" +Toggle 1to0 tdata [486] "logic tdata[511:0]" +Toggle 0to1 tdata [487] "logic tdata[511:0]" +Toggle 1to0 tdata [487] "logic tdata[511:0]" +Toggle 0to1 tdata [488] "logic tdata[511:0]" +Toggle 1to0 tdata [488] "logic tdata[511:0]" +Toggle 0to1 tdata [489] "logic tdata[511:0]" +Toggle 1to0 tdata [489] "logic tdata[511:0]" +Toggle 0to1 tdata [490] "logic tdata[511:0]" +Toggle 1to0 tdata [490] "logic tdata[511:0]" +Toggle 0to1 tdata [491] "logic tdata[511:0]" +Toggle 1to0 tdata [491] "logic tdata[511:0]" +Toggle 0to1 tdata [492] "logic tdata[511:0]" +Toggle 1to0 tdata [492] "logic tdata[511:0]" +Toggle 0to1 tdata [493] "logic tdata[511:0]" +Toggle 1to0 tdata [493] "logic tdata[511:0]" +Toggle 0to1 tdata [494] "logic tdata[511:0]" +Toggle 1to0 tdata [494] "logic tdata[511:0]" +Toggle 0to1 tdata [495] "logic tdata[511:0]" +Toggle 1to0 tdata [495] "logic tdata[511:0]" +Toggle 0to1 tdata [496] "logic tdata[511:0]" +Toggle 1to0 tdata [496] "logic tdata[511:0]" +Toggle 0to1 tdata [497] "logic tdata[511:0]" +Toggle 1to0 tdata [497] "logic tdata[511:0]" +Toggle 0to1 tdata [498] "logic tdata[511:0]" +Toggle 1to0 tdata [498] "logic tdata[511:0]" +Toggle 0to1 tdata [499] "logic tdata[511:0]" +Toggle 1to0 tdata [499] "logic tdata[511:0]" +Toggle 0to1 tdata [500] "logic tdata[511:0]" +Toggle 1to0 tdata [500] "logic tdata[511:0]" +Toggle 0to1 tdata [501] "logic tdata[511:0]" +Toggle 1to0 tdata [501] "logic tdata[511:0]" +Toggle 0to1 tdata [502] "logic tdata[511:0]" +Toggle 1to0 tdata [502] "logic tdata[511:0]" +Toggle 0to1 tdata [503] "logic tdata[511:0]" +Toggle 1to0 tdata [503] "logic tdata[511:0]" +Toggle 0to1 tdata [504] "logic tdata[511:0]" +Toggle 1to0 tdata [504] "logic tdata[511:0]" +Toggle 0to1 tdata [505] "logic tdata[511:0]" +Toggle 1to0 tdata [505] "logic tdata[511:0]" +Toggle 0to1 tdata [506] "logic tdata[511:0]" +Toggle 1to0 tdata [506] "logic tdata[511:0]" +Toggle 0to1 tdata [507] "logic tdata[511:0]" +Toggle 1to0 tdata [507] "logic tdata[511:0]" +Toggle 0to1 tdata [508] "logic tdata[511:0]" +Toggle 1to0 tdata [508] "logic tdata[511:0]" +Toggle 0to1 tdata [509] "logic tdata[511:0]" +Toggle 1to0 tdata [509] "logic tdata[511:0]" +Toggle 0to1 tdata [510] "logic tdata[511:0]" +Toggle 1to0 tdata [510] "logic tdata[511:0]" +Toggle 1to0 tdata [174] "logic tdata[511:0]" +Toggle 1to0 tdata [1] "logic tdata[511:0]" +Toggle 1to0 tdata [25] "logic tdata[511:0]" +Toggle 1to0 tdata [27] "logic tdata[511:0]" +Toggle 1to0 tdata [30] "logic tdata[511:0]" +Toggle 1to0 tdata [35] "logic tdata[511:0]" +Toggle 1to0 tdata [51] "logic tdata[511:0]" +Toggle 1to0 tdata [53] "logic tdata[511:0]" +Toggle 1to0 tdata [80] "logic tdata[511:0]" +Toggle 1to0 tdata [164] "logic tdata[511:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_fn2mx_b_port.r.axis_pl[0] +Toggle 1to0 tlast "logic tlast" +Toggle 0to1 tlast "logic tlast" +Toggle tdata "logic tdata[511:0]" +Toggle 1to0 tvalid "logic tvalid" +Toggle 0to1 tvalid "logic tvalid" +Toggle tkeep "logic tkeep[63:0]" +Toggle tuser_vendor "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_fn2mx_b_port.r.axis_pl[1] +Toggle 1to0 tready "logic tready" +Toggle 0to1 tready "logic tready" +Toggle 1to0 tlast "logic tlast" +Toggle 0to1 tlast "logic tlast" +Toggle tdata "logic tdata[511:0]" +Toggle 1to0 tvalid "logic tvalid" +Toggle 0to1 tvalid "logic tvalid" +Toggle tkeep "logic tkeep[63:0]" +Toggle tuser_vendor "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_mx2fn_a_port.r.axis_pl[0] +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_mx2fn_a_port.r.axis_pl[1] +Toggle 0to1 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [9] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [1] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [2] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [3] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [4] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [5] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [6] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [7] "logic tuser_vendor[9:0]" +Toggle 0to1 tuser_vendor [8] "logic tuser_vendor[9:0]" +Toggle 1to0 tuser_vendor [8] "logic tuser_vendor[9:0]" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_mx2fn_b_port.r.axis_pl[0] +Toggle tuser_vendor "logic tuser_vendor[9:0]" +Toggle tkeep "logic tkeep[63:0]" +Toggle 0to1 tvalid "logic tvalid" +Toggle 1to0 tvalid "logic tvalid" +Toggle 0to1 tlast "logic tlast" +Toggle 1to0 tlast "logic tlast" +CHECKSUM: "2277721912 701653482" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_mx2fn_b_port.r.axis_pl[1] +Toggle tkeep "logic tkeep[63:0]" +Toggle tuser_vendor "logic tuser_vendor[9:0]" +CHECKSUM: "2245513748 3340936883" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pg_csr_inst +Toggle 1to0 waddr_reg [16] "logic waddr_reg[17:0]" +Toggle 0to1 waddr_reg [16] "logic waddr_reg[17:0]" +Toggle 1to0 waddr_reg [15] "logic waddr_reg[17:0]" +Toggle 0to1 waddr_reg [15] "logic waddr_reg[17:0]" +Toggle 1to0 waddr_reg [17] "logic waddr_reg[17:0]" +Toggle 0to1 waddr_reg [17] "logic waddr_reg[17:0]" +Toggle 0to1 port_csr_port_stp_dfh_update.dfh.end_of_list "logic port_csr_port_stp_dfh_update.dfh.end_of_list" +Toggle 1to0 user_clk_freq_sts_0 [1] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [1] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [2] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [2] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [3] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [3] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [4] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [4] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [5] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [5] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [6] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [6] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [7] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [7] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [8] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [8] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [9] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [9] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [10] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [10] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [11] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [11] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [12] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [12] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [13] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [13] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [14] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [14] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [15] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [15] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [16] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [16] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [17] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [17] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [18] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [18] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [19] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [19] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [20] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [20] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [21] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [21] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [22] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [22] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [23] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [23] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [24] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [24] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [25] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [25] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [26] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [26] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [27] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [27] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [28] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [28] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [29] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [29] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [30] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [30] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [31] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [31] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [32] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [32] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [33] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [33] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [34] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [34] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [35] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [35] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [36] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [36] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [37] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [37] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [38] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [38] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [39] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [39] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [40] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [40] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [41] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [41] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [42] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [42] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [43] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [43] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [44] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [44] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [45] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [45] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [46] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [46] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [47] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [47] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [48] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [48] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [49] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [49] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [50] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [50] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [51] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [51] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [52] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [52] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [53] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [53] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [54] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [54] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [55] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [55] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [56] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [56] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [57] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [57] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [58] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [58] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [59] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [59] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [60] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [60] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [61] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [61] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [62] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [63] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [63] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 user_clk_freq_sts_0 [0] "logic user_clk_freq_sts_0[63:0]" +Toggle 0to1 user_clk_freq_sts_0 [0] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 pg_csr_user_clk_freq_cmd1_update.user_clk_freq_cmd1.FreqCntrClkSel "logic pg_csr_user_clk_freq_cmd1_update.user_clk_freq_cmd1.FreqCntrClkSel" +Toggle 1to0 pg_csr_user_clk_freq_cmd1_reset.user_clk_freq_cmd1.FreqCntrClkSel "logic pg_csr_user_clk_freq_cmd1_reset.user_clk_freq_cmd1.FreqCntrClkSel" +Toggle 1to0 pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.UsrClkCmdMmRst "logic pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.UsrClkCmdMmRst" +Toggle 1to0 pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.UsrClkCmdPllMgmtRst "logic pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.UsrClkCmdPllMgmtRst" +Toggle 1to0 pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.UsrClkCmdPllRst "logic pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.UsrClkCmdPllRst" +Toggle 1to0 pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.UsrClkCmdWr "logic pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.UsrClkCmdWr" +Toggle 1to0 pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.UsrClkCmdMmRst "logic pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.UsrClkCmdMmRst" +Toggle 1to0 pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.UsrClkCmdPllMgmtRst "logic pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.UsrClkCmdPllMgmtRst" +Toggle 1to0 pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.UsrClkCmdPllRst "logic pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.UsrClkCmdPllRst" +Toggle 1to0 pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.UsrClkCmdWr "logic pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.UsrClkCmdWr" +Toggle 1to0 o_port_ctrl [63] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [2] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [2] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [1] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [1] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [61] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [61] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [60] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [60] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [59] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [59] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [58] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [58] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [57] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [57] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [56] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [56] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [55] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [55] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [54] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [54] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [53] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [53] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [52] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [52] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [51] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [51] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [50] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [50] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [49] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [49] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [48] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [48] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [47] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [47] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [46] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [46] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [45] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [45] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [44] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [44] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [43] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [43] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [42] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [42] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [41] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [41] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [40] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [40] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [39] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [39] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [38] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [38] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [37] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [37] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [36] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [36] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [35] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [35] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [34] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [34] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [33] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [33] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [32] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [32] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [31] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [31] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [30] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [30] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [29] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [29] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [28] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [28] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [27] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [27] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [26] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [26] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [25] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [25] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [24] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [24] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [23] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [23] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [22] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [22] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [21] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [21] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [20] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [20] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [19] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [19] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [18] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [18] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [17] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [17] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [16] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [16] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [15] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [15] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [14] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [14] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [13] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [13] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [12] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [12] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [11] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [11] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [10] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [10] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [9] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [9] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [8] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [8] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [7] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [7] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [6] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [6] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [5] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [5] "logic o_port_ctrl[63:0]" +Toggle 1to0 o_port_ctrl [62] "logic o_port_ctrl[63:0]" +Toggle 0to1 o_port_ctrl [62] "logic o_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [2] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [62] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [62] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [61] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [61] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [60] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [60] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [59] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [59] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [58] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [58] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [57] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [57] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [56] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [56] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [55] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [55] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [54] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [54] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [53] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [53] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [52] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [52] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [51] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [51] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [50] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [50] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [49] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [49] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [48] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [48] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [47] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [47] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [46] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [46] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [45] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [45] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [44] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [44] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [43] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [43] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [42] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [42] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [41] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [41] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [40] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [40] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [39] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [39] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [38] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [38] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [37] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [37] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [36] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [36] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [35] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [35] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [34] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [34] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [33] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [33] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [32] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [32] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [31] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [31] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [30] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [30] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [29] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [29] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [28] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [28] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [27] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [27] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [26] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [26] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [25] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [25] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [24] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [24] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [23] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [23] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [22] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [22] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [21] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [21] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [20] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [20] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [19] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [19] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [18] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [18] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [17] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [17] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [16] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [16] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [15] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [15] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [14] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [14] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [13] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [13] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [12] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [12] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [11] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [11] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [10] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [10] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [9] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [9] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [8] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [8] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [7] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [7] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [6] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [6] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [5] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [5] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [63] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [63] "logic i_port_ctrl[63:0]" +ANNOTATION: " Assigned to 'h0 value " +Toggle port_csr_port_status_reset.word.upper32 "logic port_csr_port_status_reset.word.upper32[31:0]" +Toggle 0to1 port_csr_port_control_update.data [63] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [31] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [31] "logic port_csr_port_control_reset.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value " +Toggle port_csr_port_status_update.word.upper32 "logic port_csr_port_status_update.word.upper32[31:0]" +Toggle 0to1 port_csr_port_status_update.port_status.port_freeze "logic port_csr_port_status_update.port_status.port_freeze" +Toggle 0to1 port_csr_port_status_reset.port_status.port_freeze "logic port_csr_port_status_reset.port_status.port_freeze" +Toggle 0to1 i_pr_freeze "logic i_pr_freeze" +Toggle 0to1 port_csr_port_control_update.port_control.latency_tolerance "logic port_csr_port_control_update.port_control.latency_tolerance" +Toggle 0to1 port_csr_port_control_reset.port_control.latency_tolerance "logic port_csr_port_control_reset.port_control.latency_tolerance" +Toggle 0to1 port_csr_port_control.port_control.latency_tolerance "logic port_csr_port_control.port_control.latency_tolerance" +Toggle 0to1 o_port_ctrl [63] "logic o_port_ctrl[63:0]" +ANNOTATION: " Assigned to'h0 and fixed values " +Toggle port_csr_port_capability_update.word.upper32 "logic port_csr_port_capability_update.word.upper32[31:0]" +ANNOTATION: " Assigned to'h0 and fixed values " +Toggle port_csr_port_capability_update.word.lower32 "logic port_csr_port_capability_update.word.lower32[31:0]" +ANNOTATION: " Assigned to'h0 and fixed values " +Toggle port_csr_port_capability_reset.word.upper32 "logic port_csr_port_capability_reset.word.upper32[31:0]" +ANNOTATION: " Assigned to'h0 and fixed values " +Toggle port_csr_port_capability_update.data "logic port_csr_port_capability_update.data[63:0]" +ANNOTATION: " Assigned to'h0 and fixed values " +Toggle port_csr_port_capability_update.port_capability.mmio_size "logic port_csr_port_capability_update.port_capability.mmio_size[15:0]" +ANNOTATION: " Assigned to'h0 and fixed values " +Toggle port_csr_port_capability_update.port_capability.num_supp_int "logic port_csr_port_capability_update.port_capability.num_supp_int[3:0]" +ANNOTATION: " Assigned to'h0 and fixed values " +Toggle port_csr_port_capability_reset.word.lower32 "logic port_csr_port_capability_reset.word.lower32[31:0]" +ANNOTATION: " Assigned to'h0 and fixed values " +Toggle port_csr_port_capability_reset.data "logic port_csr_port_capability_reset.data[63:0]" +ANNOTATION: " Assigned to'h0 and fixed values " +Toggle port_csr_port_capability_reset.port_capability.num_supp_int "logic port_csr_port_capability_reset.port_capability.num_supp_int[3:0]" +ANNOTATION: " Assigned to'h0 and fixed values " +Toggle port_csr_port_capability_reset.port_capability.mmio_size "logic port_csr_port_capability_reset.port_capability.mmio_size[15:0]" +ANNOTATION: " Ro and reserved fields " +Toggle port_csr_port_stp_dfh_reset.word.lower32 "logic port_csr_port_stp_dfh_reset.word.lower32[31:0]" +ANNOTATION: " R0 registers " +Toggle port_csr_port_afu_id_h_reset.data "logic port_csr_port_afu_id_h_reset.data[63:0]" +ANNOTATION: " R0 registers " +Toggle port_csr_port_afu_id_h_reset.word.lower32 "logic port_csr_port_afu_id_h_reset.word.lower32[31:0]" +ANNOTATION: " R0 registers " +Toggle port_csr_port_afu_id_h_reset.word.upper32 "logic port_csr_port_afu_id_h_reset.word.upper32[31:0]" +ANNOTATION: " R0 registers " +Toggle port_csr_port_afu_id_h_update.data "logic port_csr_port_afu_id_h_update.data[63:0]" +ANNOTATION: " R0 registers " +Toggle port_csr_port_afu_id_h_update.port_afu_id_h.afu_id_h "logic port_csr_port_afu_id_h_update.port_afu_id_h.afu_id_h[63:0]" +ANNOTATION: " R0 registers " +Toggle port_csr_port_afu_id_h_update.word.lower32 "logic port_csr_port_afu_id_h_update.word.lower32[31:0]" +ANNOTATION: " R0 registers " +Toggle port_csr_port_afu_id_h_update.word.upper32 "logic port_csr_port_afu_id_h_update.word.upper32[31:0]" +ANNOTATION: " R0 registers " +Toggle port_csr_port_afu_id_l_reset.data "logic port_csr_port_afu_id_l_reset.data[63:0]" +ANNOTATION: " R0 registers " +Toggle port_csr_port_afu_id_l_reset.port_afu_id_l.afu_id_l "logic port_csr_port_afu_id_l_reset.port_afu_id_l.afu_id_l[63:0]" +ANNOTATION: " R0 registers " +Toggle port_csr_port_afu_id_l_reset.word.lower32 "logic port_csr_port_afu_id_l_reset.word.lower32[31:0]" +ANNOTATION: " R0 registers " +Toggle port_csr_port_afu_id_l_reset.word.upper32 "logic port_csr_port_afu_id_l_reset.word.upper32[31:0]" +ANNOTATION: " R0 registers " +Toggle port_csr_port_afu_id_l_update.data "logic port_csr_port_afu_id_l_update.data[63:0]" +ANNOTATION: " R0 registers " +Toggle port_csr_port_afu_id_l_update.port_afu_id_l.afu_id_l "logic port_csr_port_afu_id_l_update.port_afu_id_l.afu_id_l[63:0]" +ANNOTATION: " R0 registers " +Toggle port_csr_port_afu_id_l_update.word.lower32 "logic port_csr_port_afu_id_l_update.word.lower32[31:0]" +ANNOTATION: " R0 registers " +Toggle port_csr_port_afu_id_l_update.word.upper32 "logic port_csr_port_afu_id_l_update.word.upper32[31:0]" +ANNOTATION: " R0 registers " +Toggle port_csr_port_afu_id_h_reset.port_afu_id_h.afu_id_h "logic port_csr_port_afu_id_h_reset.port_afu_id_h.afu_id_h[63:0]" +Toggle rom_next "logic rom_next[5:0]" +Toggle rom_state "logic rom_state[5:0]" +Toggle rom_data "logic rom_data[63:0]" +ANNOTATION: " RO register excluded " +Toggle user_clk_freq_sts_1 "logic user_clk_freq_sts_1[63:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_port_dfh_update.word.upper32 "logic port_csr_port_dfh_update.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_port_dfh_update.word.lower32 "logic port_csr_port_dfh_update.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_first_afu_offset_reset.word.upper32 "logic port_csr_first_afu_offset_reset.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_first_afu_offset_update.data "logic port_csr_first_afu_offset_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_first_afu_offset_update.first_afu_offset.first_afu_offset "logic port_csr_first_afu_offset_update.first_afu_offset.first_afu_offset[23:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_first_afu_offset_update.word.lower32 "logic port_csr_first_afu_offset_update.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_first_afu_offset_update.word.upper32 "logic port_csr_first_afu_offset_update.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_first_afu_offset_reset.word.lower32 "logic port_csr_first_afu_offset_reset.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_first_afu_offset_reset.data "logic port_csr_first_afu_offset_reset.data[63:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_first_afu_offset_reset.first_afu_offset.first_afu_offset "logic port_csr_first_afu_offset_reset.first_afu_offset.first_afu_offset[23:0]" +Toggle 0to1 pg_csr_user_clk_freq_sts1_reset.user_clk_freq_sts1.FreqCntrClkMeasured "logic pg_csr_user_clk_freq_sts1_reset.user_clk_freq_sts1.FreqCntrClkMeasured" +ANNOTATION: " Assigned to 'h0 value. " +Toggle pg_csr_user_clk_freq_sts1_reset.user_clk_freq_sts1.FreqCntrMeasuredFreq "logic pg_csr_user_clk_freq_sts1_reset.user_clk_freq_sts1.FreqCntrMeasuredFreq[16:0]" +ANNOTATION: " Assigned to 'h0 value. " +Toggle pg_csr_user_clk_freq_sts1_reset.user_clk_freq_sts1.FreqCntrVersion "logic pg_csr_user_clk_freq_sts1_reset.user_clk_freq_sts1.FreqCntrVersion[3:0]" +ANNOTATION: " Assigned to 'h0 value. " +Toggle pg_csr_user_clk_freq_sts1_reset.user_clk_freq_sts1.FreqPLLRef "logic pg_csr_user_clk_freq_sts1_reset.user_clk_freq_sts1.FreqPLLRef[17:0]" +ANNOTATION: " This is R0 only register and functional scenario for same not testing, hence excluded " +Toggle pg_csr_user_clk_freq_sts1_update.data "logic pg_csr_user_clk_freq_sts1_update.data[63:0]" +Toggle 0to1 pg_csr_user_clk_freq_sts1_update.user_clk_freq_sts1.FreqCntrClkMeasured "logic pg_csr_user_clk_freq_sts1_update.user_clk_freq_sts1.FreqCntrClkMeasured" +ANNOTATION: " This is R0 only register and functional scenario for same not testing, hence excluded " +Toggle pg_csr_user_clk_freq_sts1_update.user_clk_freq_sts1.FreqCntrMeasuredFreq "logic pg_csr_user_clk_freq_sts1_update.user_clk_freq_sts1.FreqCntrMeasuredFreq[16:0]" +ANNOTATION: " This is R0 only register and functional scenario for same not testing, hence excluded " +Toggle pg_csr_user_clk_freq_sts1_update.user_clk_freq_sts1.FreqCntrVersion "logic pg_csr_user_clk_freq_sts1_update.user_clk_freq_sts1.FreqCntrVersion[3:0]" +ANNOTATION: " This is R0 only register and functional scenario for same not testing, hence excluded " +Toggle pg_csr_user_clk_freq_sts1_update.user_clk_freq_sts1.FreqPLLRef "logic pg_csr_user_clk_freq_sts1_update.user_clk_freq_sts1.FreqPLLRef[17:0]" +ANNOTATION: " Attributes fields " +Toggle port_control_attr.port_control.flr_port_reset "logic port_control_attr.port_control.flr_port_reset[3:0]" +ANNOTATION: " Assigned to 'h0 value. " +Toggle pg_csr_user_clk_freq_sts1_reset.data "logic pg_csr_user_clk_freq_sts1_reset.data[63:0]" +ANNOTATION: " This is R0 only register and functional scenario for same not testing, hence excluded " +Toggle pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStDat "logic pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStDat[31:0]" +Toggle 0to1 pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStMmError "logic pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStMmError" +Toggle 0to1 pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStMmRst "logic pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStMmRst" +ANNOTATION: " This is R0 only register and functional scenario for same not testing, hence excluded " +Toggle pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStPllActClk "logic pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStPllActClk[1:0]" +Toggle 0to1 pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStPllLocked "logic pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStPllLocked" +Toggle 0to1 pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStPllMgmtRst "logic pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStPllMgmtRst" +Toggle 0to1 pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStPllRst "logic pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStPllRst" +ANNOTATION: " This is R0 only register and functional scenario for same not testing, hence excluded " +Toggle pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStSeq "logic pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStSeq[1:0]" +Toggle 0to1 pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStWr "logic pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStWr" +ANNOTATION: " This is R0 only register and functional scenario for same not testing, hence excluded " +Toggle pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStAdr "logic pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStAdr[9:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStDat "logic pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStDat[31:0]" +Toggle 0to1 pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStMmError "logic pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStMmError" +Toggle 0to1 pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStMmRst "logic pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStMmRst" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStPllActClk "logic pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStPllActClk[1:0]" +Toggle 0to1 pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStPllLocked "logic pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStPllLocked" +Toggle 0to1 pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStPllMgmtRst "logic pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStPllMgmtRst" +Toggle 0to1 pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStPllRst "logic pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStPllRst" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStSeq "logic pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStSeq[1:0]" +Toggle 0to1 pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStWr "logic pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStWr" +Toggle pg_csr_user_clk_freq_sts0_update.data "logic pg_csr_user_clk_freq_sts0_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStAdr "logic pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStAdr[9:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.UsrClkCmdDat "logic pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.UsrClkCmdDat[31:0]" +Toggle 0to1 pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.UsrClkCmdMmRst "logic pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.UsrClkCmdMmRst" +Toggle 0to1 pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.UsrClkCmdPllMgmtRst "logic pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.UsrClkCmdPllMgmtRst" +Toggle 0to1 pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.UsrClkCmdPllRst "logic pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.UsrClkCmdPllRst" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.UsrClkCmdSeq "logic pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.UsrClkCmdSeq[1:0]" +Toggle 0to1 pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.UsrClkCmdWr "logic pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.UsrClkCmdWr" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd1_reset.data "logic pg_csr_user_clk_freq_cmd1_reset.data[63:0]" +Toggle 0to1 pg_csr_user_clk_freq_cmd1_reset.user_clk_freq_cmd1.FreqCntrClkSel "logic pg_csr_user_clk_freq_cmd1_reset.user_clk_freq_cmd1.FreqCntrClkSel" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd1_update.data "logic pg_csr_user_clk_freq_cmd1_update.data[63:0]" +Toggle 0to1 pg_csr_user_clk_freq_cmd1_update.user_clk_freq_cmd1.FreqCntrClkSel "logic pg_csr_user_clk_freq_cmd1_update.user_clk_freq_cmd1.FreqCntrClkSel" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_sts0_reset.data "logic pg_csr_user_clk_freq_sts0_reset.data[63:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.UsrClkCmdAdr "logic pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.UsrClkCmdAdr[9:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.UsrClkCmdDat "logic pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.UsrClkCmdDat[31:0]" +Toggle 0to1 pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.UsrClkCmdMmRst "logic pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.UsrClkCmdMmRst" +Toggle 0to1 pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.UsrClkCmdPllMgmtRst "logic pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.UsrClkCmdPllMgmtRst" +Toggle 0to1 pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.UsrClkCmdPllRst "logic pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.UsrClkCmdPllRst" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.UsrClkCmdSeq "logic pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.UsrClkCmdSeq[1:0]" +Toggle 0to1 pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.UsrClkCmdWr "logic pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.UsrClkCmdWr" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd0_update.data "logic pg_csr_user_clk_freq_cmd0_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.UsrClkCmdAdr "logic pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.UsrClkCmdAdr[9:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd0_reset.data "logic pg_csr_user_clk_freq_cmd0_reset.data[63:0]" +ANNOTATION: " Attributes fields " +Toggle fme_pr_dfh_attr.dfh.end_of_list "logic fme_pr_dfh_attr.dfh.end_of_list[3:0]" +ANNOTATION: " Attributes fields " +Toggle fme_pr_ctrl_attr.fme_pr_ctrl.pr_kind "logic fme_pr_ctrl_attr.fme_pr_ctrl.pr_kind[3:0]" +ANNOTATION: " Attributes fields " +Toggle fme_pr_ctrl_attr.fme_pr_ctrl.pr_reset "logic fme_pr_ctrl_attr.fme_pr_ctrl.pr_reset[3:0]" +ANNOTATION: " Attributes fields " +Toggle fme_pr_ctrl_attr.fme_pr_ctrl.pr_reset_ack "logic fme_pr_ctrl_attr.fme_pr_ctrl.pr_reset_ack[3:0]" +ANNOTATION: " Attributes fields " +Toggle fme_pr_ctrl_attr.fme_pr_ctrl.pr_start_request "logic fme_pr_ctrl_attr.fme_pr_ctrl.pr_start_request[3:0]" +ANNOTATION: " Attributes fields " +Toggle fme_pr_ctrl_attr.fme_pr_ctrl.pr_data_push_complete "logic fme_pr_ctrl_attr.fme_pr_ctrl.pr_data_push_complete[3:0]" +Toggle fme_csr_fme_pr_status_update.word.upper32 "logic fme_csr_fme_pr_status_update.word.upper32[31:0]" +Toggle fme_csr_fme_pr_status_update.word.lower32 "logic fme_csr_fme_pr_status_update.word.lower32[31:0]" +Toggle fme_csr_fme_pr_status_update.fme_pr_status.security_block_status "logic fme_csr_fme_pr_status_update.fme_pr_status.security_block_status[31:0]" +Toggle 0to1 fme_csr_fme_pr_status_update.fme_pr_status.pr_status "logic fme_csr_fme_pr_status_update.fme_pr_status.pr_status" +Toggle fme_csr_fme_pr_status_update.fme_pr_status.pr_host_status "logic fme_csr_fme_pr_status_update.fme_pr_status.pr_host_status[3:0]" +Toggle fme_csr_fme_pr_status_update.fme_pr_status.numb_credits "logic fme_csr_fme_pr_status_update.fme_pr_status.numb_credits[8:0]" +Toggle fme_csr_fme_pr_status_reset.fme_pr_status.altera_pr_ctrl_status "logic fme_csr_fme_pr_status_reset.fme_pr_status.altera_pr_ctrl_status[2:0]" +Toggle fme_csr_fme_pr_status_reset.fme_pr_status.numb_credits "logic fme_csr_fme_pr_status_reset.fme_pr_status.numb_credits[8:0]" +Toggle fme_csr_fme_pr_status_reset.fme_pr_status.pr_host_status "logic fme_csr_fme_pr_status_reset.fme_pr_status.pr_host_status[3:0]" +Toggle 0to1 fme_csr_fme_pr_status_reset.fme_pr_status.pr_status "logic fme_csr_fme_pr_status_reset.fme_pr_status.pr_status" +Toggle fme_csr_fme_pr_status_reset.fme_pr_status.security_block_status "logic fme_csr_fme_pr_status_reset.fme_pr_status.security_block_status[31:0]" +Toggle fme_csr_fme_pr_status_reset.word.lower32 "logic fme_csr_fme_pr_status_reset.word.lower32[31:0]" +Toggle fme_csr_fme_pr_status_reset.word.upper32 "logic fme_csr_fme_pr_status_reset.word.upper32[31:0]" +Toggle fme_csr_fme_pr_status_update.data "logic fme_csr_fme_pr_status_update.data[63:0]" +Toggle fme_csr_fme_pr_status_update.fme_pr_status.altera_pr_ctrl_status "logic fme_csr_fme_pr_status_update.fme_pr_status.altera_pr_ctrl_status[2:0]" +Toggle fme_csr_fme_pr_status_reset.data "logic fme_csr_fme_pr_status_reset.data[63:0]" +ANNOTATION: " R0 registers " +Toggle fme_csr_fme_pr_dfh_update.word.upper32 "logic fme_csr_fme_pr_dfh_update.word.upper32[31:0]" +ANNOTATION: " R0 registers " +Toggle fme_csr_fme_pr_dfh_update.word.lower32 "logic fme_csr_fme_pr_dfh_update.word.lower32[31:0]" +Toggle fme_csr_fme_pr_ctrl_update.word.upper32 "logic fme_csr_fme_pr_ctrl_update.word.upper32[31:0]" +Toggle fme_csr_fme_pr_data_reset.data "logic fme_csr_fme_pr_data_reset.data[63:0]" +Toggle fme_csr_fme_pr_data_reset.word.lower32 "logic fme_csr_fme_pr_data_reset.word.lower32[31:0]" +Toggle fme_csr_fme_pr_data_reset.word.upper32 "logic fme_csr_fme_pr_data_reset.word.upper32[31:0]" +Toggle fme_csr_fme_pr_data_update.data "logic fme_csr_fme_pr_data_update.data[63:0]" +Toggle fme_csr_fme_pr_data_update.word.lower32 "logic fme_csr_fme_pr_data_update.word.lower32[31:0]" +Toggle fme_csr_fme_pr_data_update.word.upper32 "logic fme_csr_fme_pr_data_update.word.upper32[31:0]" +ANNOTATION: " R0 registers " +Toggle fme_csr_fme_pr_dfh_update.dfh.next_dfh_offset "logic fme_csr_fme_pr_dfh_update.dfh.next_dfh_offset[23:0]" +Toggle fme_csr_fme_pr_ctrl_update.word.lower32 "logic fme_csr_fme_pr_ctrl_update.word.lower32[31:0]" +Toggle fme_csr_fme_pr_ctrl_reset.word.upper32 "logic fme_csr_fme_pr_ctrl_reset.word.upper32[31:0]" +Toggle fme_csr_fme_pr_ctrl_update.data "logic fme_csr_fme_pr_ctrl_update.data[63:0]" +Toggle fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.config_data "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.config_data[31:0]" +Toggle 0to1 fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_kind "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_kind" +Toggle fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_region_id "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_region_id[1:0]" +Toggle 0to1 fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_reset "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_reset" +Toggle 0to1 fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_reset_ack "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_reset_ack" +Toggle 0to1 fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_start_request "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_start_request" +Toggle fme_csr_fme_pr_ctrl_reset.word.lower32 "logic fme_csr_fme_pr_ctrl_reset.word.lower32[31:0]" +Toggle fme_csr_fme_pr_ctrl_reset.data "logic fme_csr_fme_pr_ctrl_reset.data[63:0]" +Toggle fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.config_data "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.config_data[31:0]" +Toggle 0to1 fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_data_push_complete "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_data_push_complete" +Toggle 0to1 fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_kind "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_kind" +Toggle fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_region_id "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_region_id[1:0]" +Toggle 0to1 fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_reset "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_reset" +Toggle 0to1 fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_reset_ack "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_reset_ack" +Toggle 0to1 fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_start_request "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_start_request" +Toggle fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.reserved1 "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.reserved1[2:0]" +Toggle FME_PR_IF_ID_MAX "bit FME_PR_IF_ID_MAX[1:0]" +Toggle fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.reserved5 "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.reserved5[2:0]" +ANNOTATION: " Ro and reserved fields " +Toggle port_csr_port_stp_dfh_update.dfh.reserved "logic port_csr_port_stp_dfh_update.dfh.reserved[18:0]" +ANNOTATION: " Ro and reserved fields " +Toggle port_csr_port_stp_dfh_reset.dfh.reserved "logic port_csr_port_stp_dfh_reset.dfh.reserved[18:0]" +ANNOTATION: " Assigned to 'h0 value " +Toggle port_csr_port_status_update.port_status.reserved1 "logic port_csr_port_status_update.port_status.reserved1[62:0]" +ANNOTATION: " Assigned to 'h0 value " +Toggle port_csr_port_status_reset.port_status.reserved1 "logic port_csr_port_status_reset.port_status.reserved1[62:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_port_dfh_update.port_dfh.reserved "logic port_csr_port_dfh_update.port_dfh.reserved[18:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_port_dfh_reset.port_dfh.reserved "logic port_csr_port_dfh_reset.port_dfh.reserved[18:0]" +Toggle port_csr_port_control_update.port_control.reserved5 "logic port_csr_port_control_update.port_control.reserved5[58:0]" +Toggle 1to0 port_csr_port_control_update.port_control.reserved1 "logic port_csr_port_control_update.port_control.reserved1" +Toggle port_csr_port_control_reset.port_control.reserved5 "logic port_csr_port_control_reset.port_control.reserved5[58:0]" +Toggle 1to0 port_csr_port_control_reset.port_control.reserved1 "logic port_csr_port_control_reset.port_control.reserved1" +Toggle 1to0 port_csr_port_control.port_control.reserved1 "logic port_csr_port_control.port_control.reserved1" +Toggle port_csr_port_control.port_control.reserved5 "logic port_csr_port_control.port_control.reserved5[58:0]" +ANNOTATION: " Assigned to'h0 and fixed values " +Toggle port_csr_port_capability_update.port_capability.reserved36 "logic port_csr_port_capability_update.port_capability.reserved36[27:0]" +ANNOTATION: " Assigned to'h0 and fixed values " +Toggle port_csr_port_capability_update.port_capability.reserved24 "logic port_csr_port_capability_update.port_capability.reserved24[7:0]" +ANNOTATION: " Assigned to'h0 and fixed values " +Toggle port_csr_port_capability_update.port_capability.reserved0 "logic port_csr_port_capability_update.port_capability.reserved0[7:0]" +ANNOTATION: " Assigned to'h0 and fixed values " +Toggle port_csr_port_capability_reset.port_capability.reserved36 "logic port_csr_port_capability_reset.port_capability.reserved36[27:0]" +ANNOTATION: " Assigned to'h0 and fixed values " +Toggle port_csr_port_capability_reset.port_capability.reserved24 "logic port_csr_port_capability_reset.port_capability.reserved24[7:0]" +ANNOTATION: " Assigned to'h0 and fixed values " +Toggle port_csr_port_capability_reset.port_capability.reserved0 "logic port_csr_port_capability_reset.port_capability.reserved0[7:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_first_afu_offset_update.first_afu_offset.reserved "logic port_csr_first_afu_offset_update.first_afu_offset.reserved[39:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_first_afu_offset_reset.first_afu_offset.reserved "logic port_csr_first_afu_offset_reset.first_afu_offset.reserved[39:0]" +Toggle pg_csr_user_clk_freq_sts1_update.user_clk_freq_sts1.Reserved51 "logic pg_csr_user_clk_freq_sts1_update.user_clk_freq_sts1.Reserved51[8:0]" +Toggle pg_csr_user_clk_freq_sts1_update.user_clk_freq_sts1.Reserved41 "logic pg_csr_user_clk_freq_sts1_update.user_clk_freq_sts1.Reserved41[14:0]" +Toggle pg_csr_user_clk_freq_sts1_reset.user_clk_freq_sts1.Reserved51 "logic pg_csr_user_clk_freq_sts1_reset.user_clk_freq_sts1.Reserved51[8:0]" +Toggle pg_csr_user_clk_freq_sts1_reset.user_clk_freq_sts1.Reserved41 "logic pg_csr_user_clk_freq_sts1_reset.user_clk_freq_sts1.Reserved41[14:0]" +Toggle pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.Reserved4 "logic pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.Reserved4[1:0]" +Toggle pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.Reserved3 "logic pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.Reserved3[2:0]" +Toggle pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.Reserved2 "logic pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.Reserved2[1:0]" +Toggle pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.Reserved1 "logic pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.Reserved1[2:0]" +Toggle pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.Reserved0 "logic pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.Reserved0[1:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.Reserved4 "logic pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.Reserved4[1:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.Reserved3 "logic pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.Reserved3[2:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.Reserved2 "logic pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.Reserved2[1:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.Reserved1 "logic pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.Reserved1[2:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.Reserved0 "logic pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.Reserved0[1:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd1_update.user_clk_freq_cmd1.Reserved1 "logic pg_csr_user_clk_freq_cmd1_update.user_clk_freq_cmd1.Reserved1[30:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd1_update.user_clk_freq_cmd1.Reserved0 "logic pg_csr_user_clk_freq_cmd1_update.user_clk_freq_cmd1.Reserved0[31:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd1_reset.user_clk_freq_cmd1.Reserved1 "logic pg_csr_user_clk_freq_cmd1_reset.user_clk_freq_cmd1.Reserved1[30:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd1_reset.user_clk_freq_cmd1.Reserved0 "logic pg_csr_user_clk_freq_cmd1_reset.user_clk_freq_cmd1.Reserved0[31:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.Reserved4 "logic pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.Reserved4[5:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.Reserved3 "logic pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.Reserved3[2:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.Reserved2 "logic pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.Reserved2[1:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.Reserved1 "logic pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.Reserved1[2:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.Reserved0 "logic pg_csr_user_clk_freq_cmd0_update.user_clk_freq_cmd0.Reserved0[1:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.Reserved4 "logic pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.Reserved4[5:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.Reserved3 "logic pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.Reserved3[2:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.Reserved2 "logic pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.Reserved2[1:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.Reserved1 "logic pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.Reserved1[2:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.Reserved0 "logic pg_csr_user_clk_freq_cmd0_reset.user_clk_freq_cmd0.Reserved0[1:0]" +ANNOTATION: " R0 registers " +Toggle pg_csr_user_clk_dfh_update.user_clk_dfh.Reserved41 "logic pg_csr_user_clk_dfh_update.user_clk_dfh.Reserved41[18:0]" +ANNOTATION: " R0 registers " +Toggle pg_csr_user_clk_dfh_reset.user_clk_dfh.Reserved41 "logic pg_csr_user_clk_dfh_reset.user_clk_dfh.Reserved41[18:0]" +ANNOTATION: " Attributes fields " +Toggle fme_pr_status_attr.fme_pr_status.reserved23 "logic fme_pr_status_attr.fme_pr_status.reserved23[3:0]" +Toggle fme_csr_fme_pr_status_update.fme_pr_status.reserved28 "logic fme_csr_fme_pr_status_update.fme_pr_status.reserved28[3:0]" +Toggle 1to0 fme_csr_fme_pr_status_update.fme_pr_status.reserved23 "logic fme_csr_fme_pr_status_update.fme_pr_status.reserved23" +Toggle fme_csr_fme_pr_status_update.fme_pr_status.reserved17 "logic fme_csr_fme_pr_status_update.fme_pr_status.reserved17[2:0]" +Toggle fme_csr_fme_pr_status_update.fme_pr_status.reserved9 "logic fme_csr_fme_pr_status_update.fme_pr_status.reserved9[6:0]" +Toggle fme_csr_fme_pr_status_reset.fme_pr_status.reserved28 "logic fme_csr_fme_pr_status_reset.fme_pr_status.reserved28[3:0]" +Toggle 1to0 fme_csr_fme_pr_status_reset.fme_pr_status.reserved23 "logic fme_csr_fme_pr_status_reset.fme_pr_status.reserved23" +Toggle fme_csr_fme_pr_status_reset.fme_pr_status.reserved17 "logic fme_csr_fme_pr_status_reset.fme_pr_status.reserved17[2:0]" +Toggle fme_csr_fme_pr_status_reset.fme_pr_status.reserved9 "logic fme_csr_fme_pr_status_reset.fme_pr_status.reserved9[6:0]" +Toggle fme_csr_fme_pr_error_update.fme_pr_error.reserved7 "logic fme_csr_fme_pr_error_update.fme_pr_error.reserved7[56:0]" +Toggle fme_csr_fme_pr_error_reset.fme_pr_error.reserved7 "logic fme_csr_fme_pr_error_reset.fme_pr_error.reserved7[56:0]" +ANNOTATION: " R0 registers " +Toggle fme_csr_fme_pr_dfh_update.dfh.reserved "logic fme_csr_fme_pr_dfh_update.dfh.reserved[18:0]" +ANNOTATION: " R0 registers " +Toggle fme_csr_fme_pr_dfh_reset.dfh.reserved "logic fme_csr_fme_pr_dfh_reset.dfh.reserved[18:0]" +Toggle fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.reserved15 "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.reserved15[16:0]" +Toggle fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.reserved10 "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.reserved10[1:0]" +Toggle fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.reserved5 "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.reserved5[2:0]" +Toggle fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.reserved1 "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.reserved1[2:0]" +Toggle 1to0 rst_n "net rst_n" +Toggle fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.reserved15 "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.reserved15[16:0]" +Toggle fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.reserved10 "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.reserved10[1:0]" +Toggle fme_csr_fme_pr_intfc_id_h_reset.data "logic fme_csr_fme_pr_intfc_id_h_reset.data[63:0]" +ANNOTATION: " Attributes fields " +Toggle port_control_attr.port_control.reserved1 "logic port_control_attr.port_control.reserved1[3:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5098_update.word.upper32 "logic fme_csr_dummy_5098_update.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5098_update.data "logic fme_csr_dummy_5098_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5098_update.word.lower32 "logic fme_csr_dummy_5098_update.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5098_reset.word.upper32 "logic fme_csr_dummy_5098_reset.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5098_reset.word.lower32 "logic fme_csr_dummy_5098_reset.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5098_reset.data "logic fme_csr_dummy_5098_reset.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5090_update.word.upper32 "logic fme_csr_dummy_5090_update.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5090_update.word.lower32 "logic fme_csr_dummy_5090_update.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5090_update.data "logic fme_csr_dummy_5090_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5090_reset.word.upper32 "logic fme_csr_dummy_5090_reset.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5090_reset.word.lower32 "logic fme_csr_dummy_5090_reset.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5090_reset.data "logic fme_csr_dummy_5090_reset.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5088_update.word.upper32 "logic fme_csr_dummy_5088_update.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5088_update.word.lower32 "logic fme_csr_dummy_5088_update.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5088_update.data "logic fme_csr_dummy_5088_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5088_reset.word.upper32 "logic fme_csr_dummy_5088_reset.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5088_reset.word.lower32 "logic fme_csr_dummy_5088_reset.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5088_reset.data "logic fme_csr_dummy_5088_reset.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5080_update.word.upper32 "logic fme_csr_dummy_5080_update.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5080_update.word.lower32 "logic fme_csr_dummy_5080_update.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5080_update.data "logic fme_csr_dummy_5080_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5080_reset.word.upper32 "logic fme_csr_dummy_5080_reset.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5080_reset.word.lower32 "logic fme_csr_dummy_5080_reset.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5080_reset.data "logic fme_csr_dummy_5080_reset.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5078_update.word.upper32 "logic fme_csr_dummy_5078_update.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5078_update.word.lower32 "logic fme_csr_dummy_5078_update.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5078_update.data "logic fme_csr_dummy_5078_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5078_reset.word.upper32 "logic fme_csr_dummy_5078_reset.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5078_reset.word.lower32 "logic fme_csr_dummy_5078_reset.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5078_reset.data "logic fme_csr_dummy_5078_reset.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5070_update.word.upper32 "logic fme_csr_dummy_5070_update.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5070_update.word.lower32 "logic fme_csr_dummy_5070_update.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5070_update.data "logic fme_csr_dummy_5070_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5070_reset.word.upper32 "logic fme_csr_dummy_5070_reset.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5070_reset.word.lower32 "logic fme_csr_dummy_5070_reset.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5070_reset.data "logic fme_csr_dummy_5070_reset.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5068_update.word.upper32 "logic fme_csr_dummy_5068_update.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5068_update.word.lower32 "logic fme_csr_dummy_5068_update.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5068_update.data "logic fme_csr_dummy_5068_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5068_reset.word.upper32 "logic fme_csr_dummy_5068_reset.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5068_reset.word.lower32 "logic fme_csr_dummy_5068_reset.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5068_reset.data "logic fme_csr_dummy_5068_reset.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5060_update.word.upper32 "logic fme_csr_dummy_5060_update.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5060_update.word.lower32 "logic fme_csr_dummy_5060_update.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5060_update.data "logic fme_csr_dummy_5060_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5060_reset.word.upper32 "logic fme_csr_dummy_5060_reset.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5060_reset.word.lower32 "logic fme_csr_dummy_5060_reset.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5060_reset.data "logic fme_csr_dummy_5060_reset.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5058_update.word.upper32 "logic fme_csr_dummy_5058_update.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5058_update.word.lower32 "logic fme_csr_dummy_5058_update.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5058_update.data "logic fme_csr_dummy_5058_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5058_reset.word.upper32 "logic fme_csr_dummy_5058_reset.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5058_reset.word.lower32 "logic fme_csr_dummy_5058_reset.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5058_reset.data "logic fme_csr_dummy_5058_reset.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5050_update.word.upper32 "logic fme_csr_dummy_5050_update.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5050_update.word.lower32 "logic fme_csr_dummy_5050_update.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5050_update.data "logic fme_csr_dummy_5050_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5050_reset.word.upper32 "logic fme_csr_dummy_5050_reset.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5050_reset.word.lower32 "logic fme_csr_dummy_5050_reset.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5050_reset.data "logic fme_csr_dummy_5050_reset.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5048_update.word.upper32 "logic fme_csr_dummy_5048_update.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5048_update.word.lower32 "logic fme_csr_dummy_5048_update.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5048_update.data "logic fme_csr_dummy_5048_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5048_reset.word.upper32 "logic fme_csr_dummy_5048_reset.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5048_reset.word.lower32 "logic fme_csr_dummy_5048_reset.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5048_reset.data "logic fme_csr_dummy_5048_reset.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5040_update.word.upper32 "logic fme_csr_dummy_5040_update.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5040_update.word.lower32 "logic fme_csr_dummy_5040_update.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5040_update.data "logic fme_csr_dummy_5040_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5040_reset.word.upper32 "logic fme_csr_dummy_5040_reset.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5040_reset.word.lower32 "logic fme_csr_dummy_5040_reset.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5040_reset.data "logic fme_csr_dummy_5040_reset.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5038_update.word.upper32 "logic fme_csr_dummy_5038_update.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5038_update.word.lower32 "logic fme_csr_dummy_5038_update.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5038_update.data "logic fme_csr_dummy_5038_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5038_reset.word.lower32 "logic fme_csr_dummy_5038_reset.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5038_reset.word.upper32 "logic fme_csr_dummy_5038_reset.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5038_reset.data "logic fme_csr_dummy_5038_reset.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5030_update.word.upper32 "logic fme_csr_dummy_5030_update.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5030_update.word.lower32 "logic fme_csr_dummy_5030_update.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5030_update.data "logic fme_csr_dummy_5030_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5030_reset.word.upper32 "logic fme_csr_dummy_5030_reset.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5030_reset.word.lower32 "logic fme_csr_dummy_5030_reset.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5030_reset.data "logic fme_csr_dummy_5030_reset.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5028_update.word.upper32 "logic fme_csr_dummy_5028_update.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5028_update.word.lower32 "logic fme_csr_dummy_5028_update.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5028_update.data "logic fme_csr_dummy_5028_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5028_reset.word.upper32 "logic fme_csr_dummy_5028_reset.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5028_reset.word.lower32 "logic fme_csr_dummy_5028_reset.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_5028_reset.data "logic fme_csr_dummy_5028_reset.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_50A0_update.word.upper32 "logic fme_csr_dummy_50A0_update.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_50A0_update.word.lower32 "logic fme_csr_dummy_50A0_update.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_50A0_update.data "logic fme_csr_dummy_50A0_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_50A0_reset.word.upper32 "logic fme_csr_dummy_50A0_reset.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_50A0_reset.word.lower32 "logic fme_csr_dummy_50A0_reset.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value hence excluded " +Toggle fme_csr_dummy_50A0_reset.data "logic fme_csr_dummy_50A0_reset.data[63:0]" +Toggle fme_csr_fme_pr_intfc_id_h_reset.word.lower32 "logic fme_csr_fme_pr_intfc_id_h_reset.word.lower32[31:0]" +Toggle fme_csr_fme_pr_intfc_id_l_update.word.upper32 "logic fme_csr_fme_pr_intfc_id_l_update.word.upper32[31:0]" +Toggle fme_csr_fme_pr_intfc_id_l_update.word.lower32 "logic fme_csr_fme_pr_intfc_id_l_update.word.lower32[31:0]" +Toggle fme_csr_fme_pr_intfc_id_l_update.data "logic fme_csr_fme_pr_intfc_id_l_update.data[63:0]" +Toggle fme_csr_fme_pr_intfc_id_l_reset.word.upper32 "logic fme_csr_fme_pr_intfc_id_l_reset.word.upper32[31:0]" +Toggle fme_csr_fme_pr_intfc_id_l_reset.word.lower32 "logic fme_csr_fme_pr_intfc_id_l_reset.word.lower32[31:0]" +Toggle fme_csr_fme_pr_intfc_id_l_reset.data "logic fme_csr_fme_pr_intfc_id_l_reset.data[63:0]" +Toggle fme_csr_fme_pr_intfc_id_h_update.word.upper32 "logic fme_csr_fme_pr_intfc_id_h_update.word.upper32[31:0]" +Toggle fme_csr_fme_pr_intfc_id_h_update.word.lower32 "logic fme_csr_fme_pr_intfc_id_h_update.word.lower32[31:0]" +Toggle fme_csr_fme_pr_intfc_id_h_update.data "logic fme_csr_fme_pr_intfc_id_h_update.data[63:0]" +Toggle fme_csr_fme_pr_intfc_id_h_reset.word.upper32 "logic fme_csr_fme_pr_intfc_id_h_reset.word.upper32[31:0]" +ANNOTATION: " R0 registers " +Toggle fme_csr_fme_pr_dfh_reset.data "logic fme_csr_fme_pr_dfh_reset.data[63:0]" +ANNOTATION: " R0 registers " +Toggle fme_csr_fme_pr_dfh_update.dfh.feature_type "logic fme_csr_fme_pr_dfh_update.dfh.feature_type[3:0]" +ANNOTATION: " R0 registers " +Toggle fme_csr_fme_pr_dfh_update.dfh.feature_rev "logic fme_csr_fme_pr_dfh_update.dfh.feature_rev[3:0]" +ANNOTATION: " R0 registers " +Toggle fme_csr_fme_pr_dfh_update.dfh.feature_id "logic fme_csr_fme_pr_dfh_update.dfh.feature_id[11:0]" +Toggle 1to0 fme_csr_fme_pr_dfh_update.dfh.end_of_list "logic fme_csr_fme_pr_dfh_update.dfh.end_of_list" +ANNOTATION: " R0 registers " +Toggle fme_csr_fme_pr_dfh_update.data "logic fme_csr_fme_pr_dfh_update.data[63:0]" +ANNOTATION: " R0 registers " +Toggle fme_csr_fme_pr_dfh_reset.word.upper32 "logic fme_csr_fme_pr_dfh_reset.word.upper32[31:0]" +ANNOTATION: " R0 registers " +Toggle fme_csr_fme_pr_dfh_reset.word.lower32 "logic fme_csr_fme_pr_dfh_reset.word.lower32[31:0]" +ANNOTATION: " R0 registers " +Toggle fme_csr_fme_pr_dfh_reset.dfh.next_dfh_offset "logic fme_csr_fme_pr_dfh_reset.dfh.next_dfh_offset[23:0]" +ANNOTATION: " R0 registers " +Toggle fme_csr_fme_pr_dfh_reset.dfh.feature_type "logic fme_csr_fme_pr_dfh_reset.dfh.feature_type[3:0]" +ANNOTATION: " R0 registers " +Toggle fme_csr_fme_pr_dfh_reset.dfh.feature_rev "logic fme_csr_fme_pr_dfh_reset.dfh.feature_rev[3:0]" +ANNOTATION: " R0 registers " +Toggle fme_csr_fme_pr_dfh_reset.dfh.feature_id "logic fme_csr_fme_pr_dfh_reset.dfh.feature_id[11:0]" +Toggle 1to0 fme_csr_fme_pr_dfh_reset.dfh.end_of_list "logic fme_csr_fme_pr_dfh_reset.dfh.end_of_list" +ANNOTATION: " R0 registers " +Toggle pg_csr_user_clk_dfh_reset.data "logic pg_csr_user_clk_dfh_reset.data[63:0]" +ANNOTATION: " R0 registers " +Toggle pg_csr_user_clk_dfh_reset.user_clk_dfh.NextDfhOffset "logic pg_csr_user_clk_dfh_reset.user_clk_dfh.NextDfhOffset[23:0]" +ANNOTATION: " R0 registers " +Toggle pg_csr_user_clk_dfh_reset.user_clk_dfh.FeatureType "logic pg_csr_user_clk_dfh_reset.user_clk_dfh.FeatureType[3:0]" +Toggle 1to0 pg_csr_user_clk_dfh_reset.user_clk_dfh.EOL "logic pg_csr_user_clk_dfh_reset.user_clk_dfh.EOL" +ANNOTATION: " R0 registers " +Toggle pg_csr_user_clk_dfh_reset.user_clk_dfh.CciVersion "logic pg_csr_user_clk_dfh_reset.user_clk_dfh.CciVersion[11:0]" +ANNOTATION: " R0 registers " +Toggle pg_csr_user_clk_dfh_reset.user_clk_dfh.CciMinorRev "logic pg_csr_user_clk_dfh_reset.user_clk_dfh.CciMinorRev[3:0]" +ANNOTATION: " R0 registers " +Toggle pg_csr_user_clk_dfh_update.data "logic pg_csr_user_clk_dfh_update.data[63:0]" +ANNOTATION: " R0 registers " +Toggle pg_csr_user_clk_dfh_update.user_clk_dfh.NextDfhOffset "logic pg_csr_user_clk_dfh_update.user_clk_dfh.NextDfhOffset[23:0]" +ANNOTATION: " R0 registers " +Toggle pg_csr_user_clk_dfh_update.user_clk_dfh.FeatureType "logic pg_csr_user_clk_dfh_update.user_clk_dfh.FeatureType[3:0]" +Toggle 1to0 pg_csr_user_clk_dfh_update.user_clk_dfh.EOL "logic pg_csr_user_clk_dfh_update.user_clk_dfh.EOL" +ANNOTATION: " R0 registers " +Toggle pg_csr_user_clk_dfh_update.user_clk_dfh.CciVersion "logic pg_csr_user_clk_dfh_update.user_clk_dfh.CciVersion[11:0]" +ANNOTATION: " R0 registers " +Toggle pg_csr_user_clk_dfh_update.user_clk_dfh.CciMinorRev "logic pg_csr_user_clk_dfh_update.user_clk_dfh.CciMinorRev[3:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_port_dfh_reset.port_dfh.afu_maj_version "logic port_csr_port_dfh_reset.port_dfh.afu_maj_version[3:0]" +ANNOTATION: " Ro and reserved fields " +Toggle port_csr_port_stp_dfh_update.dfh.next_dfh_offset "logic port_csr_port_stp_dfh_update.dfh.next_dfh_offset[23:0]" +ANNOTATION: " Ro and reserved fields " +Toggle port_csr_port_stp_dfh_update.dfh.feature_type "logic port_csr_port_stp_dfh_update.dfh.feature_type[3:0]" +ANNOTATION: " Ro and reserved fields " +Toggle port_csr_port_stp_dfh_update.dfh.feature_rev "logic port_csr_port_stp_dfh_update.dfh.feature_rev[3:0]" +ANNOTATION: " Ro and reserved fields " +Toggle port_csr_port_stp_dfh_update.dfh.feature_id "logic port_csr_port_stp_dfh_update.dfh.feature_id[11:0]" +Toggle 1to0 port_csr_port_stp_dfh_update.dfh.end_of_list "logic port_csr_port_stp_dfh_update.dfh.end_of_list" +ANNOTATION: " Ro and reserved fields " +Toggle port_csr_port_stp_dfh_update.data "logic port_csr_port_stp_dfh_update.data[63:0]" +ANNOTATION: " Ro and reserved fields " +Toggle port_csr_port_stp_dfh_reset.word.upper32 "logic port_csr_port_stp_dfh_reset.word.upper32[31:0]" +ANNOTATION: " Ro and reserved fields " +Toggle port_csr_port_stp_dfh_reset.dfh.next_dfh_offset "logic port_csr_port_stp_dfh_reset.dfh.next_dfh_offset[23:0]" +ANNOTATION: " Ro and reserved fields " +Toggle port_csr_port_stp_dfh_reset.dfh.feature_type "logic port_csr_port_stp_dfh_reset.dfh.feature_type[3:0]" +ANNOTATION: " Ro and reserved fields " +Toggle port_csr_port_stp_dfh_reset.dfh.feature_rev "logic port_csr_port_stp_dfh_reset.dfh.feature_rev[3:0]" +ANNOTATION: " Ro and reserved fields " +Toggle port_csr_port_stp_dfh_reset.dfh.feature_id "logic port_csr_port_stp_dfh_reset.dfh.feature_id[11:0]" +Toggle 1to0 port_csr_port_stp_dfh_reset.dfh.end_of_list "logic port_csr_port_stp_dfh_reset.dfh.end_of_list" +ANNOTATION: " Ro and reserved fields " +Toggle port_csr_port_stp_dfh_reset.data "logic port_csr_port_stp_dfh_reset.data[63:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_port_dfh_update.port_dfh.next_dfh_offset "logic port_csr_port_dfh_update.port_dfh.next_dfh_offset[23:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_port_dfh_update.port_dfh.feature_type "logic port_csr_port_dfh_update.port_dfh.feature_type[3:0]" +Toggle 1to0 port_csr_port_dfh_update.port_dfh.end_of_list "logic port_csr_port_dfh_update.port_dfh.end_of_list" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_port_dfh_update.port_dfh.corefim_version "logic port_csr_port_dfh_update.port_dfh.corefim_version[11:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_port_dfh_update.port_dfh.afu_maj_version "logic port_csr_port_dfh_update.port_dfh.afu_maj_version[3:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_port_dfh_update.data "logic port_csr_port_dfh_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_port_dfh_reset.word.upper32 "logic port_csr_port_dfh_reset.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_port_dfh_reset.word.lower32 "logic port_csr_port_dfh_reset.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_port_dfh_reset.port_dfh.next_dfh_offset "logic port_csr_port_dfh_reset.port_dfh.next_dfh_offset[23:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_port_dfh_reset.port_dfh.feature_type "logic port_csr_port_dfh_reset.port_dfh.feature_type[3:0]" +Toggle 1to0 port_csr_port_dfh_reset.port_dfh.end_of_list "logic port_csr_port_dfh_reset.port_dfh.end_of_list" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_port_dfh_reset.port_dfh.corefim_version "logic port_csr_port_dfh_reset.port_dfh.corefim_version[11:0]" +Toggle 1to0 user_clk_freq_sts_0 [62] "logic user_clk_freq_sts_0[63:0]" +Toggle 1to0 i_port_ctrl [2] "logic i_port_ctrl[63:0]" +ANNOTATION: " R0 fields " +Toggle port_stp_status_attr.port_stp_status.unsupported_rd "logic port_stp_status_attr.port_stp_status.unsupported_rd[3:0]" +ANNOTATION: " R0 fields " +Toggle port_stp_status_attr.port_stp_status.tx_fifo_underflow "logic port_stp_status_attr.port_stp_status.tx_fifo_underflow[3:0]" +ANNOTATION: " R0 fields " +Toggle port_stp_status_attr.port_stp_status.tx_fifo_overflow "logic port_stp_status_attr.port_stp_status.tx_fifo_overflow[3:0]" +ANNOTATION: " R0 fields " +Toggle port_stp_status_attr.port_stp_status.stp_in_reset "logic port_stp_status_attr.port_stp_status.stp_in_reset[3:0]" +ANNOTATION: " R0 fields " +Toggle port_stp_status_attr.port_stp_status.rx_fifo_underflow "logic port_stp_status_attr.port_stp_status.rx_fifo_underflow[3:0]" +ANNOTATION: " R0 fields " +Toggle port_stp_status_attr.port_stp_status.rx_fifo_overflow "logic port_stp_status_attr.port_stp_status.rx_fifo_overflow[3:0]" +ANNOTATION: " R0 fields " +Toggle port_stp_status_attr.port_stp_status.rw_time_out "logic port_stp_status_attr.port_stp_status.rw_time_out[3:0]" +ANNOTATION: " R0 fields " +Toggle port_stp_status_attr.port_stp_status.mmio_time_out "logic port_stp_status_attr.port_stp_status.mmio_time_out[3:0]" +Toggle port_csr_port_stp_status_reset.port_stp_status.tx_fifo_count "logic port_csr_port_stp_status_reset.port_stp_status.tx_fifo_count[3:0]" +Toggle 1to0 port_csr_port_stp_status_reset.port_stp_status.stp_in_reset "logic port_csr_port_stp_status_reset.port_stp_status.stp_in_reset" +Toggle 1to0 port_csr_port_stp_status_reset.port_stp_status.rx_fifo_underflow "logic port_csr_port_stp_status_reset.port_stp_status.rx_fifo_underflow" +Toggle 1to0 port_csr_port_stp_status_reset.port_stp_status.rx_fifo_overflow "logic port_csr_port_stp_status_reset.port_stp_status.rx_fifo_overflow" +Toggle port_csr_port_stp_status_reset.port_stp_status.rx_fifo_count "logic port_csr_port_stp_status_reset.port_stp_status.rx_fifo_count[3:0]" +Toggle 1to0 port_csr_port_stp_status_reset.port_stp_status.rw_time_out "logic port_csr_port_stp_status_reset.port_stp_status.rw_time_out" +Toggle port_csr_port_stp_status_reset.port_stp_status.num_mmio_wr "logic port_csr_port_stp_status_reset.port_stp_status.num_mmio_wr[15:0]" +Toggle port_csr_port_stp_status_reset.port_stp_status.num_mmio_resp "logic port_csr_port_stp_status_reset.port_stp_status.num_mmio_resp[15:0]" +Toggle port_csr_port_stp_status_reset.port_stp_status.num_mmio_req "logic port_csr_port_stp_status_reset.port_stp_status.num_mmio_req[15:0]" +Toggle 1to0 port_csr_port_stp_status_reset.port_stp_status.mmio_time_out "logic port_csr_port_stp_status_reset.port_stp_status.mmio_time_out" +Toggle port_csr_port_stp_status_reset.data "logic port_csr_port_stp_status_reset.data[63:0]" +ANNOTATION: " Ro and reserved fields " +Toggle port_csr_port_stp_dfh_update.word.upper32 "logic port_csr_port_stp_dfh_update.word.upper32[31:0]" +ANNOTATION: " Ro and reserved fields " +Toggle port_csr_port_stp_dfh_update.word.lower32 "logic port_csr_port_stp_dfh_update.word.lower32[31:0]" +Toggle 1to0 remotestp_awaddr_hit_reg "logic remotestp_awaddr_hit_reg" +Toggle 1to0 remotestp_awaddr_hit "logic remotestp_awaddr_hit" +Toggle 1to0 remotestp_araddr_hit_reg "logic remotestp_araddr_hit_reg" +Toggle 1to0 port_csr_port_stp_status_reset.port_stp_status.tx_fifo_overflow "logic port_csr_port_stp_status_reset.port_stp_status.tx_fifo_overflow" +Toggle 1to0 port_csr_port_stp_status_update.port_stp_status.tx_fifo_underflow "logic port_csr_port_stp_status_update.port_stp_status.tx_fifo_underflow" +Toggle 1to0 port_csr_port_stp_status_update.port_stp_status.tx_fifo_overflow "logic port_csr_port_stp_status_update.port_stp_status.tx_fifo_overflow" +ANNOTATION: " R0 fields " +Toggle port_csr_port_stp_status_update.port_stp_status.tx_fifo_count "logic port_csr_port_stp_status_update.port_stp_status.tx_fifo_count[3:0]" +Toggle 1to0 port_csr_port_stp_status_update.port_stp_status.stp_in_reset "logic port_csr_port_stp_status_update.port_stp_status.stp_in_reset" +Toggle 1to0 port_csr_port_stp_status_update.port_stp_status.rx_fifo_underflow "logic port_csr_port_stp_status_update.port_stp_status.rx_fifo_underflow" +Toggle 1to0 port_csr_port_stp_status_update.port_stp_status.rx_fifo_overflow "logic port_csr_port_stp_status_update.port_stp_status.rx_fifo_overflow" +ANNOTATION: " R0 fields " +Toggle port_csr_port_stp_status_update.port_stp_status.rx_fifo_count "logic port_csr_port_stp_status_update.port_stp_status.rx_fifo_count[3:0]" +Toggle 1to0 port_csr_port_stp_status_update.port_stp_status.rw_time_out "logic port_csr_port_stp_status_update.port_stp_status.rw_time_out" +ANNOTATION: " R0 fields " +Toggle port_csr_port_stp_status_update.port_stp_status.num_mmio_wr "logic port_csr_port_stp_status_update.port_stp_status.num_mmio_wr[15:0]" +ANNOTATION: " R0 fields " +Toggle port_csr_port_stp_status_update.port_stp_status.num_mmio_resp "logic port_csr_port_stp_status_update.port_stp_status.num_mmio_resp[15:0]" +ANNOTATION: " R0 fields " +Toggle port_csr_port_stp_status_update.port_stp_status.num_mmio_req "logic port_csr_port_stp_status_update.port_stp_status.num_mmio_req[15:0]" +Toggle 1to0 port_csr_port_stp_status_update.port_stp_status.mmio_time_out "logic port_csr_port_stp_status_update.port_stp_status.mmio_time_out" +Toggle port_csr_port_stp_status_update.data "logic port_csr_port_stp_status_update.data[63:0]" +Toggle port_csr_port_stp_status_reset.word.upper32 "logic port_csr_port_stp_status_reset.word.upper32[31:0]" +Toggle port_csr_port_stp_status_reset.word.lower32 "logic port_csr_port_stp_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_stp_status_reset.port_stp_status.unsupported_rd "logic port_csr_port_stp_status_reset.port_stp_status.unsupported_rd" +Toggle 1to0 port_csr_port_stp_status_reset.port_stp_status.tx_fifo_underflow "logic port_csr_port_stp_status_reset.port_stp_status.tx_fifo_underflow" +Toggle 1to0 fme_csr_fme_pr_error_reset.fme_pr_error.host_init_timeout "logic fme_csr_fme_pr_error_reset.fme_pr_error.host_init_timeout" +Toggle 1to0 fme_csr_fme_pr_error_reset.fme_pr_error.secure_load_failed "logic fme_csr_fme_pr_error_reset.fme_pr_error.secure_load_failed" +Toggle 1to0 fme_csr_fme_pr_error_reset.fme_pr_error.ip_init_incompatible_bitstream "logic fme_csr_fme_pr_error_reset.fme_pr_error.ip_init_incompatible_bitstream" +Toggle 1to0 fme_csr_fme_pr_error_reset.fme_pr_error.host_init_operation_error "logic fme_csr_fme_pr_error_reset.fme_pr_error.host_init_operation_error" +Toggle 1to0 fme_csr_fme_pr_error_update.fme_pr_error.secure_load_failed "logic fme_csr_fme_pr_error_update.fme_pr_error.secure_load_failed" +Toggle 1to0 fme_csr_fme_pr_error_update.fme_pr_error.ip_init_incompatible_bitstream "logic fme_csr_fme_pr_error_update.fme_pr_error.ip_init_incompatible_bitstream" +Toggle 1to0 fme_csr_fme_pr_error_update.fme_pr_error.host_init_timeout "logic fme_csr_fme_pr_error_update.fme_pr_error.host_init_timeout" +Toggle fme_csr_fme_pr_error_reset.word.upper32 "logic fme_csr_fme_pr_error_reset.word.upper32[31:0]" +ANNOTATION: " Attributes fields " +Toggle fme_pr_error_attr.fme_pr_error.secure_load_failed "logic fme_pr_error_attr.fme_pr_error.secure_load_failed[3:0]" +ANNOTATION: " Attributes fields " +Toggle fme_pr_error_attr.fme_pr_error.ip_init_incompatible_bitstream "logic fme_pr_error_attr.fme_pr_error.ip_init_incompatible_bitstream[3:0]" +ANNOTATION: " Attributes fields " +Toggle fme_pr_error_attr.fme_pr_error.host_init_timeout "logic fme_pr_error_attr.fme_pr_error.host_init_timeout[3:0]" +ANNOTATION: " Attributes fields " +Toggle fme_pr_status_attr.fme_pr_status.pr_status "logic fme_pr_status_attr.fme_pr_status.pr_status[3:0]" +Toggle i_remotestp_status "logic i_remotestp_status[63:0]" +ANNOTATION: " Attributes fields " +Toggle port_control_attr.port_control.latency_tolerance "logic port_control_attr.port_control.latency_tolerance[3:0]" +ANNOTATION: " Assigned to 'h0 value and reserved fields " +Toggle port_csr_port_dfh_reset.data "logic port_csr_port_dfh_reset.data[63:0]" +Toggle 1to0 port_csr_port_stp_status_update.port_stp_status.unsupported_rd "logic port_csr_port_stp_status_update.port_stp_status.unsupported_rd" +Toggle port_dfh_attr.port_dfh.end_of_list "logic port_dfh_attr.port_dfh.end_of_list[3:0]" +ANNOTATION: " R0 fields " +Toggle port_csr_port_stp_status_update.word.upper32 "logic port_csr_port_stp_status_update.word.upper32[31:0]" +ANNOTATION: " R0 fields " +Toggle port_csr_port_stp_status_update.word.lower32 "logic port_csr_port_stp_status_update.word.lower32[31:0]" +Toggle port_status_attr.port_status.port_freeze "logic port_status_attr.port_status.port_freeze[3:0]" +Toggle port_stp_dfh_attr.dfh.end_of_list "logic port_stp_dfh_attr.dfh.end_of_list[3:0]" +ANNOTATION: " Assigned to 'h0 value " +Toggle pg_csr_pr_scratchpad_reset.data "logic pg_csr_pr_scratchpad_reset.data[63:0]" +ANNOTATION: " Assigned to 'h0 value " +Toggle port_csr_port_scratchpad0_update.word.upper32 "logic port_csr_port_scratchpad0_update.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value " +Toggle port_csr_port_scratchpad0_update.word.lower32 "logic port_csr_port_scratchpad0_update.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value " +Toggle port_csr_port_scratchpad0_update.data "logic port_csr_port_scratchpad0_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value " +Toggle port_csr_port_scratchpad0_reset.word.upper32 "logic port_csr_port_scratchpad0_reset.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value " +Toggle port_csr_port_scratchpad0_reset.word.lower32 "logic port_csr_port_scratchpad0_reset.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value " +Toggle port_csr_port_scratchpad0_reset.data "logic port_csr_port_scratchpad0_reset.data[63:0]" +ANNOTATION: " Assigned to 'h0 value " +Toggle port_csr_port_mailbox_update.word.upper32 "logic port_csr_port_mailbox_update.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value " +Toggle port_csr_port_mailbox_update.word.lower32 "logic port_csr_port_mailbox_update.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value " +Toggle port_csr_port_mailbox_update.data "logic port_csr_port_mailbox_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value " +Toggle port_csr_port_mailbox_reset.word.upper32 "logic port_csr_port_mailbox_reset.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value " +Toggle port_csr_port_mailbox_reset.word.lower32 "logic port_csr_port_mailbox_reset.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value " +Toggle port_csr_port_mailbox_reset.data "logic port_csr_port_mailbox_reset.data[63:0]" +ANNOTATION: " Assigned to 'h0 value " +Toggle pg_csr_pr_scratchpad_update.word.upper32 "logic pg_csr_pr_scratchpad_update.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value " +Toggle pg_csr_pr_scratchpad_update.word.lower32 "logic pg_csr_pr_scratchpad_update.word.lower32[31:0]" +ANNOTATION: " Assigned to 'h0 value " +Toggle pg_csr_pr_scratchpad_update.data "logic pg_csr_pr_scratchpad_update.data[63:0]" +ANNOTATION: " Assigned to 'h0 value " +Toggle pg_csr_pr_scratchpad_reset.word.upper32 "logic pg_csr_pr_scratchpad_reset.word.upper32[31:0]" +ANNOTATION: " Assigned to 'h0 value " +Toggle pg_csr_pr_scratchpad_reset.word.lower32 "logic pg_csr_pr_scratchpad_reset.word.lower32[31:0]" +Toggle port_csr_port_control.data "logic port_csr_port_control.data[63:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [30] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [30] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.data [62] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [62] "logic port_csr_port_status_reset.data[63:0]" +Toggle port_csr_port_control_reset.word.upper32 "logic port_csr_port_control_reset.word.upper32[31:0]" +Toggle port_csr_port_control.word.upper32 "logic port_csr_port_control.word.upper32[31:0]" +Toggle port_csr_port_control.word.lower32 "logic port_csr_port_control.word.lower32[31:0]" +Toggle 1to0 i_pr_freeze "logic i_pr_freeze" +Toggle 0to1 fme_csr_fme_pr_dfh_update.dfh.end_of_list "logic fme_csr_fme_pr_dfh_update.dfh.end_of_list" +Toggle 1to0 fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_data_push_complete "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_data_push_complete" +Toggle 1to0 fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_kind "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_kind" +Toggle 1to0 fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_reset "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_reset" +Toggle 1to0 fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_start_request "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_start_request" +Toggle 1to0 fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_kind "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_kind" +Toggle 1to0 fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_reset "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_reset" +Toggle 1to0 fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_reset_ack "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_reset_ack" +Toggle 0to1 fme_csr_fme_pr_dfh_reset.dfh.end_of_list "logic fme_csr_fme_pr_dfh_reset.dfh.end_of_list" +Toggle 0to1 fme_csr_fme_pr_status_reset.fme_pr_status.reserved23 "logic fme_csr_fme_pr_status_reset.fme_pr_status.reserved23" +Toggle 0to1 fme_csr_fme_pr_status_update.fme_pr_status.reserved23 "logic fme_csr_fme_pr_status_update.fme_pr_status.reserved23" +Toggle 0to1 pg_csr_user_clk_dfh_reset.user_clk_dfh.EOL "logic pg_csr_user_clk_dfh_reset.user_clk_dfh.EOL" +Toggle 0to1 pg_csr_user_clk_dfh_update.user_clk_dfh.EOL "logic pg_csr_user_clk_dfh_update.user_clk_dfh.EOL" +Toggle 1to0 port_csr_port_control_update.port_control.latency_tolerance "logic port_csr_port_control_update.port_control.latency_tolerance" +Toggle 1to0 port_csr_port_control_reset.port_control.latency_tolerance "logic port_csr_port_control_reset.port_control.latency_tolerance" +Toggle 0to1 port_csr_port_control_reset.port_control.reserved1 "logic port_csr_port_control_reset.port_control.reserved1" +Toggle 0to1 port_csr_port_dfh_reset.port_dfh.end_of_list "logic port_csr_port_dfh_reset.port_dfh.end_of_list" +Toggle 0to1 port_csr_port_dfh_update.port_dfh.end_of_list "logic port_csr_port_dfh_update.port_dfh.end_of_list" +Toggle 0to1 port_csr_port_stp_dfh_reset.dfh.end_of_list "logic port_csr_port_stp_dfh_reset.dfh.end_of_list" +Toggle fme_csr_fme_pr_error_reset.data "logic fme_csr_fme_pr_error_reset.data[63:0]" +Toggle 0to1 fme_csr_fme_pr_error_reset.fme_pr_error.ip_init_protocol_error "logic fme_csr_fme_pr_error_reset.fme_pr_error.ip_init_protocol_error" +Toggle 1to0 fme_csr_fme_pr_error_reset.fme_pr_error.ip_init_protocol_error "logic fme_csr_fme_pr_error_reset.fme_pr_error.ip_init_protocol_error" +Toggle 0to1 fme_csr_fme_pr_error_reset.fme_pr_error.ip_init_incompatible_bitstream "logic fme_csr_fme_pr_error_reset.fme_pr_error.ip_init_incompatible_bitstream" +Toggle 0to1 fme_csr_fme_pr_error_reset.fme_pr_error.ip_init_crc_error "logic fme_csr_fme_pr_error_reset.fme_pr_error.ip_init_crc_error" +Toggle 1to0 fme_csr_fme_pr_error_reset.fme_pr_error.ip_init_crc_error "logic fme_csr_fme_pr_error_reset.fme_pr_error.ip_init_crc_error" +Toggle 0to1 fme_csr_fme_pr_error_reset.fme_pr_error.host_init_timeout "logic fme_csr_fme_pr_error_reset.fme_pr_error.host_init_timeout" +Toggle 0to1 fme_csr_fme_pr_error_reset.fme_pr_error.host_init_operation_error "logic fme_csr_fme_pr_error_reset.fme_pr_error.host_init_operation_error" +Toggle 0to1 fme_csr_fme_pr_error_reset.fme_pr_error.host_init_fifo_overflow "logic fme_csr_fme_pr_error_reset.fme_pr_error.host_init_fifo_overflow" +Toggle 1to0 fme_csr_fme_pr_error_reset.fme_pr_error.host_init_fifo_overflow "logic fme_csr_fme_pr_error_reset.fme_pr_error.host_init_fifo_overflow" +Toggle 0to1 fme_csr_fme_pr_error_reset.fme_pr_error.secure_load_failed "logic fme_csr_fme_pr_error_reset.fme_pr_error.secure_load_failed" +Toggle fme_csr_fme_pr_error_reset.word.lower32 "logic fme_csr_fme_pr_error_reset.word.lower32[31:0]" +Toggle fme_csr_fme_pr_error_update.data "logic fme_csr_fme_pr_error_update.data[63:0]" +Toggle fme_csr_fme_pr_error_update.word.lower32 "logic fme_csr_fme_pr_error_update.word.lower32[31:0]" +Toggle 0to1 fme_csr_fme_pr_error_update.fme_pr_error.secure_load_failed "logic fme_csr_fme_pr_error_update.fme_pr_error.secure_load_failed" +Toggle 0to1 fme_csr_fme_pr_error_update.fme_pr_error.ip_init_protocol_error "logic fme_csr_fme_pr_error_update.fme_pr_error.ip_init_protocol_error" +Toggle 1to0 fme_csr_fme_pr_error_update.fme_pr_error.ip_init_protocol_error "logic fme_csr_fme_pr_error_update.fme_pr_error.ip_init_protocol_error" +Toggle 0to1 fme_csr_fme_pr_error_update.fme_pr_error.ip_init_incompatible_bitstream "logic fme_csr_fme_pr_error_update.fme_pr_error.ip_init_incompatible_bitstream" +Toggle 0to1 fme_csr_fme_pr_error_update.fme_pr_error.ip_init_crc_error "logic fme_csr_fme_pr_error_update.fme_pr_error.ip_init_crc_error" +Toggle 1to0 fme_csr_fme_pr_error_update.fme_pr_error.ip_init_crc_error "logic fme_csr_fme_pr_error_update.fme_pr_error.ip_init_crc_error" +Toggle 0to1 fme_csr_fme_pr_error_update.fme_pr_error.host_init_timeout "logic fme_csr_fme_pr_error_update.fme_pr_error.host_init_timeout" +Toggle 0to1 fme_csr_fme_pr_error_update.fme_pr_error.host_init_operation_error "logic fme_csr_fme_pr_error_update.fme_pr_error.host_init_operation_error" +Toggle 1to0 fme_csr_fme_pr_error_update.fme_pr_error.host_init_operation_error "logic fme_csr_fme_pr_error_update.fme_pr_error.host_init_operation_error" +Toggle 0to1 fme_csr_fme_pr_error_update.fme_pr_error.host_init_fifo_overflow "logic fme_csr_fme_pr_error_update.fme_pr_error.host_init_fifo_overflow" +Toggle 1to0 fme_csr_fme_pr_error_update.fme_pr_error.host_init_fifo_overflow "logic fme_csr_fme_pr_error_update.fme_pr_error.host_init_fifo_overflow" +Toggle fme_csr_fme_pr_error_update.word.upper32 "logic fme_csr_fme_pr_error_update.word.upper32[31:0]" +Toggle 1to0 fme_csr_fme_pr_status_reset.fme_pr_status.pr_status "logic fme_csr_fme_pr_status_reset.fme_pr_status.pr_status" +Toggle 1to0 fme_csr_fme_pr_status_update.fme_pr_status.pr_status "logic fme_csr_fme_pr_status_update.fme_pr_status.pr_status" +Toggle 1to0 fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_reset_ack "logic fme_csr_fme_pr_ctrl_reset.fme_pr_ctrl.pr_reset_ack" +Toggle 0to1 i_port_ctrl [1] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [1] "logic i_port_ctrl[63:0]" +Toggle 0to1 i_port_ctrl [0] "logic i_port_ctrl[63:0]" +Toggle 1to0 i_port_ctrl [0] "logic i_port_ctrl[63:0]" +ANNOTATION: " Attributes fields " +Toggle fme_pr_error_attr.fme_pr_error.host_init_fifo_overflow "logic fme_pr_error_attr.fme_pr_error.host_init_fifo_overflow[3:0]" +ANNOTATION: " Attributes fields " +Toggle fme_pr_error_attr.fme_pr_error.ip_init_protocol_error "logic fme_pr_error_attr.fme_pr_error.ip_init_protocol_error[3:0]" +ANNOTATION: " Attributes fields " +Toggle fme_pr_error_attr.fme_pr_error.ip_init_crc_error "logic fme_pr_error_attr.fme_pr_error.ip_init_crc_error[3:0]" +ANNOTATION: " Attributes fields " +Toggle fme_pr_error_attr.fme_pr_error.host_init_operation_error "logic fme_pr_error_attr.fme_pr_error.host_init_operation_error[3:0]" +Toggle 0to1 hw_state.pwr_good_n "logic hw_state.pwr_good_n" +Toggle 1to0 hw_state.pwr_good_n "logic hw_state.pwr_good_n" +Toggle 1to0 pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStWr "logic pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStWr" +Toggle 1to0 pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStPllRst "logic pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStPllRst" +Toggle 1to0 pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStPllMgmtRst "logic pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStPllMgmtRst" +Toggle 1to0 pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStPllLocked "logic pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStPllLocked" +Toggle 1to0 pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStMmRst "logic pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStMmRst" +Toggle 1to0 pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStMmError "logic pg_csr_user_clk_freq_sts0_reset.user_clk_freq_sts0.UsrClkStMmError" +Toggle 1to0 pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStMmError "logic pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStMmError" +Toggle 1to0 pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStWr "logic pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStWr" +Toggle 1to0 pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStPllRst "logic pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStPllRst" +Toggle 1to0 pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStPllMgmtRst "logic pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStPllMgmtRst" +Toggle 1to0 pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStPllLocked "logic pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStPllLocked" +Toggle 1to0 pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStMmRst "logic pg_csr_user_clk_freq_sts0_update.user_clk_freq_sts0.UsrClkStMmRst" +Toggle 1to0 pg_csr_user_clk_freq_sts1_reset.user_clk_freq_sts1.FreqCntrClkMeasured "logic pg_csr_user_clk_freq_sts1_reset.user_clk_freq_sts1.FreqCntrClkMeasured" +Toggle 1to0 pg_csr_user_clk_freq_sts1_update.user_clk_freq_sts1.FreqCntrClkMeasured "logic pg_csr_user_clk_freq_sts1_update.user_clk_freq_sts1.FreqCntrClkMeasured" +ANNOTATION: " Attributes fields " +Toggle port_control_attr.port_control.port_soft_reset_ack "logic port_control_attr.port_control.port_soft_reset_ack[3:0]" +ANNOTATION: " Attributes fields " +Toggle port_control_attr.port_control.port_soft_reset "logic port_control_attr.port_control.port_soft_reset[3:0]" +Toggle 0to1 port_csr_port_control.port_control.reserved1 "logic port_csr_port_control.port_control.reserved1" +Toggle 1to0 port_csr_port_control.port_control.latency_tolerance "logic port_csr_port_control.port_control.latency_tolerance" +Toggle 0to1 port_csr_port_control_reset.port_control.port_soft_reset "logic port_csr_port_control_reset.port_control.port_soft_reset" +Toggle 1to0 port_csr_port_control_reset.port_control.port_soft_reset "logic port_csr_port_control_reset.port_control.port_soft_reset" +Toggle 0to1 port_csr_port_control_reset.data [63] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [63] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [5] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [5] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [6] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [6] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [7] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [7] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [8] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [8] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [9] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [9] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [10] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [10] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [11] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [11] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [12] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [12] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [13] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [13] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [14] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [14] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [15] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [15] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [16] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [16] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [17] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [17] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [18] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [18] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [19] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [19] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [20] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [20] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [21] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [21] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [22] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [22] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [23] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [23] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [24] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [24] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [25] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [25] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [26] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [26] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [27] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [27] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [28] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [28] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [29] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [29] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [30] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [30] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [31] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [31] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [32] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [32] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [33] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [33] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [34] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [34] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [35] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [35] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [36] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [36] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [37] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [37] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [38] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [38] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [39] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [39] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [40] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [40] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [41] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [41] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [42] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [42] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [43] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [43] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [44] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [44] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [45] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [45] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [46] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [46] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [47] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [47] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [48] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [48] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [49] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [49] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [50] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [50] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [51] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [51] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [52] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [52] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [53] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [53] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [54] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [54] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [55] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [55] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [56] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [56] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [57] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [57] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [58] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [58] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [59] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [59] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [60] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [60] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [61] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [61] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [62] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [62] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [2] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [2] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [1] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [1] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.data [0] "logic port_csr_port_control_reset.data[63:0]" +Toggle 1to0 port_csr_port_control_reset.data [0] "logic port_csr_port_control_reset.data[63:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [0] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [0] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [31] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [30] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [30] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [29] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [29] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [28] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [28] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [27] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [27] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [26] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [26] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [25] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [25] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [24] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [24] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [23] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [23] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [22] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [22] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [21] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [21] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [20] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [20] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [19] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [19] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [18] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [18] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [17] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [17] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [16] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [16] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [15] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [15] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [14] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [14] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [13] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [13] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [12] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [12] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [11] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [11] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [10] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [10] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [9] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [9] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [8] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [8] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [7] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [7] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [6] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [6] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [5] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [5] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [4] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [4] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [3] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [3] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [2] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [2] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_reset.word.lower32 [1] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_reset.word.lower32 [1] "logic port_csr_port_control_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.data [63] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [62] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [62] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [5] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [5] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [6] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [6] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [7] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [7] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [8] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [8] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [9] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [9] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [10] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [10] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [11] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [11] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [12] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [12] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [13] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [13] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [14] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [14] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [15] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [15] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [16] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [16] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [17] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [17] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [18] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [18] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [19] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [19] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [20] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [20] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [21] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [21] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [22] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [22] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [23] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [23] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [24] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [24] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [25] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [25] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [26] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [26] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [27] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [27] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [28] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [28] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [29] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [29] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [30] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [30] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [31] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [31] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [32] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [32] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [33] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [33] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [34] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [34] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [35] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [35] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [36] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [36] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [37] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [37] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [38] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [38] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [39] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [39] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [40] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [40] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [41] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [41] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [42] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [42] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [43] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [43] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [44] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [44] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [45] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [45] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [46] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [46] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [47] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [47] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [48] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [48] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [49] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [49] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [50] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [50] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [51] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [51] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [52] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [52] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [53] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [53] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [54] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [54] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [55] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [55] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [56] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [56] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [57] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [57] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [58] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [58] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [59] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [59] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [60] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [60] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [61] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [61] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [2] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [2] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [0] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [0] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.data [1] "logic port_csr_port_control_update.data[63:0]" +Toggle 1to0 port_csr_port_control_update.data [1] "logic port_csr_port_control_update.data[63:0]" +Toggle 0to1 port_csr_port_control_update.port_control.port_soft_reset "logic port_csr_port_control_update.port_control.port_soft_reset" +Toggle 1to0 port_csr_port_control_update.port_control.port_soft_reset "logic port_csr_port_control_update.port_control.port_soft_reset" +Toggle 0to1 port_csr_port_control_update.port_control.reserved1 "logic port_csr_port_control_update.port_control.reserved1" +Toggle 1to0 port_csr_port_control_update.word.lower32 [31] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [30] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [30] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [5] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [5] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [6] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [6] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [7] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [7] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [8] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [8] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [9] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [9] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [10] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [10] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [11] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [11] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [12] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [12] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [13] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [13] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [14] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [14] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [15] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [15] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [16] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [16] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [17] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [17] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [18] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [18] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [19] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [19] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [20] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [20] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [21] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [21] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [22] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [22] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [23] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [23] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [24] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [24] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [25] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [25] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [26] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [26] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [27] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [27] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [28] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [28] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [29] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [29] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [0] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [0] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [1] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [1] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control_update.word.lower32 [2] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_control_update.word.lower32 [2] "logic port_csr_port_control_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_control.port_control.port_soft_reset_ack "logic port_csr_port_control.port_control.port_soft_reset_ack" +Toggle 1to0 port_csr_port_control.port_control.port_soft_reset_ack "logic port_csr_port_control.port_control.port_soft_reset_ack" +Toggle 0to1 port_csr_port_control.port_control.port_soft_reset "logic port_csr_port_control.port_control.port_soft_reset" +Toggle 1to0 port_csr_port_control.port_control.port_soft_reset "logic port_csr_port_control.port_control.port_soft_reset" +Toggle 0to1 port_csr_port_control.port_control.flr_port_reset "logic port_csr_port_control.port_control.flr_port_reset" +Toggle 1to0 port_csr_port_control.port_control.flr_port_reset "logic port_csr_port_control.port_control.flr_port_reset" +Toggle 0to1 port_csr_port_status_reset.data [63] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [63] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [62] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [37] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [37] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [38] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [38] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [39] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [39] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [40] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [40] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [41] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [41] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [42] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [42] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [43] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [43] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [44] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [44] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [45] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [45] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [46] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [46] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [47] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [47] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [48] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [48] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [49] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [49] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [50] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [50] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [51] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [51] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [52] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [52] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [53] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [53] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [54] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [54] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [55] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [55] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [56] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [56] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [57] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [57] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [58] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [58] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [59] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [59] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [60] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [60] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [61] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [61] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [36] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [36] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [26] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [26] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [27] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [27] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [28] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [28] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [29] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [29] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [30] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [30] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [31] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [31] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [32] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [32] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [33] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [33] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [34] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [34] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [35] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [35] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [25] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [25] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [10] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [10] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [11] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [11] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [12] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [12] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [13] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [13] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [14] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [14] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [15] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [15] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [16] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [16] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [17] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [17] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [18] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [18] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [19] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [19] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [20] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [20] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [21] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [21] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [22] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [22] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [23] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [23] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [24] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [24] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [9] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [9] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [1] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [1] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [2] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [2] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [3] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [3] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [4] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [4] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [5] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [5] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [6] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [6] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [7] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [7] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [8] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [8] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.data [0] "logic port_csr_port_status_reset.data[63:0]" +Toggle 1to0 port_csr_port_status_reset.data [0] "logic port_csr_port_status_reset.data[63:0]" +Toggle 0to1 port_csr_port_stp_status_reset.port_stp_status.mmio_time_out "logic port_csr_port_stp_status_reset.port_stp_status.mmio_time_out" +Toggle 0to1 port_csr_port_stp_status_update.port_stp_status.mmio_time_out "logic port_csr_port_stp_status_update.port_stp_status.mmio_time_out" +Toggle 0to1 port_csr_port_stp_status_reset.port_stp_status.unsupported_rd "logic port_csr_port_stp_status_reset.port_stp_status.unsupported_rd" +Toggle 0to1 port_csr_port_stp_status_reset.port_stp_status.tx_fifo_underflow "logic port_csr_port_stp_status_reset.port_stp_status.tx_fifo_underflow" +Toggle 0to1 port_csr_port_stp_status_reset.port_stp_status.tx_fifo_overflow "logic port_csr_port_stp_status_reset.port_stp_status.tx_fifo_overflow" +Toggle 0to1 port_csr_port_stp_status_reset.port_stp_status.stp_in_reset "logic port_csr_port_stp_status_reset.port_stp_status.stp_in_reset" +Toggle 0to1 port_csr_port_stp_status_reset.port_stp_status.rx_fifo_underflow "logic port_csr_port_stp_status_reset.port_stp_status.rx_fifo_underflow" +Toggle 0to1 port_csr_port_stp_status_reset.port_stp_status.rw_time_out "logic port_csr_port_stp_status_reset.port_stp_status.rw_time_out" +Toggle 0to1 port_csr_port_stp_status_update.port_stp_status.rw_time_out "logic port_csr_port_stp_status_update.port_stp_status.rw_time_out" +Toggle 0to1 port_csr_port_stp_status_update.port_stp_status.unsupported_rd "logic port_csr_port_stp_status_update.port_stp_status.unsupported_rd" +Toggle 0to1 port_csr_port_stp_status_update.port_stp_status.tx_fifo_underflow "logic port_csr_port_stp_status_update.port_stp_status.tx_fifo_underflow" +Toggle 0to1 port_csr_port_stp_status_update.port_stp_status.tx_fifo_overflow "logic port_csr_port_stp_status_update.port_stp_status.tx_fifo_overflow" +Toggle 0to1 port_csr_port_stp_status_update.port_stp_status.stp_in_reset "logic port_csr_port_stp_status_update.port_stp_status.stp_in_reset" +Toggle 0to1 port_csr_port_stp_status_update.port_stp_status.rx_fifo_underflow "logic port_csr_port_stp_status_update.port_stp_status.rx_fifo_underflow" +Toggle 0to1 port_csr_port_stp_status_update.port_stp_status.rx_fifo_overflow "logic port_csr_port_stp_status_update.port_stp_status.rx_fifo_overflow" +Toggle 1to0 port_csr_port_status_reset.port_status.port_freeze "logic port_csr_port_status_reset.port_status.port_freeze" +Toggle 0to1 port_csr_port_status_update.word.lower32 [0] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [0] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [31] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [31] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [30] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [29] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [29] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [28] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [28] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [27] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [27] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [26] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [26] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [25] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [25] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [24] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [24] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [23] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [23] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [22] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [22] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [21] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [21] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [20] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [20] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [19] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [19] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [18] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [18] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [17] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [17] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [16] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [16] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [15] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [15] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [14] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [14] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [13] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [13] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [12] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [12] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [11] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [11] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [10] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [10] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [9] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [9] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [8] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [8] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [7] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [7] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [6] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [6] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [5] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [5] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [4] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [4] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [3] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [3] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [2] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [2] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_update.word.lower32 [1] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.word.lower32 [1] "logic port_csr_port_status_update.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_update.port_status.port_freeze "logic port_csr_port_status_update.port_status.port_freeze" +Toggle 0to1 port_csr_port_status_update.data [0] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [0] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [63] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [63] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [62] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [61] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [61] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [60] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [60] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [59] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [59] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [58] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [58] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [57] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [57] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [56] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [56] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [55] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [55] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [54] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [54] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [53] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [53] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [52] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [52] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [51] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [51] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [50] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [50] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [49] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [49] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [48] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [48] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [47] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [47] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [46] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [46] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [45] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [45] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [44] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [44] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [43] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [43] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [42] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [42] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [41] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [41] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [40] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [40] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [39] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [39] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [38] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [38] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [37] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [37] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [36] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [36] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [35] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [35] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [34] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [34] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [33] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [33] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [32] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [32] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [31] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [31] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [30] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [30] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [29] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [29] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [28] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [28] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [27] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [27] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [26] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [26] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [25] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [25] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [24] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [24] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [23] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [23] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [22] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [22] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [21] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [21] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [20] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [20] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [19] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [19] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [18] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [18] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [17] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [17] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [16] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [16] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [15] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [15] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [14] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [14] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [13] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [13] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [12] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [12] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [11] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [11] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [10] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [10] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [9] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [9] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [8] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [8] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [7] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [7] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [6] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [6] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [5] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [5] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [4] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [4] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [3] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [3] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [2] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [2] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_update.data [1] "logic port_csr_port_status_update.data[63:0]" +Toggle 1to0 port_csr_port_status_update.data [1] "logic port_csr_port_status_update.data[63:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [0] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [0] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [31] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [31] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [30] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [29] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [29] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [28] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [28] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [27] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [27] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [26] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [26] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [25] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [25] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [24] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [24] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [23] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [23] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [22] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [22] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [21] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [21] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [20] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [20] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [19] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [19] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [18] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [18] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [17] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [17] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [16] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [16] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [15] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [15] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [14] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [14] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [13] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [13] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [12] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [12] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [11] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [11] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [10] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [10] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [9] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [9] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [8] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [8] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [7] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [7] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [6] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [6] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [5] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [5] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [4] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [4] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [3] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [3] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [2] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [2] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_status_reset.word.lower32 [1] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 1to0 port_csr_port_status_reset.word.lower32 [1] "logic port_csr_port_status_reset.word.lower32[31:0]" +Toggle 0to1 port_csr_port_stp_status_reset.port_stp_status.rx_fifo_overflow "logic port_csr_port_stp_status_reset.port_stp_status.rx_fifo_overflow" +Toggle 0to1 fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_data_push_complete "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_data_push_complete" +Toggle 1to0 fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_data_push_complete "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_data_push_complete" +Toggle 1to0 fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_start_request "logic fme_csr_fme_pr_ctrl_update.fme_pr_ctrl.pr_start_request" +Toggle port_csr_port_control_update.word.upper32 "logic port_csr_port_control_update.word.upper32[31:0]" +Toggle 0to1 remotestp_araddr_hit "logic remotestp_araddr_hit" +Toggle 1to0 remotestp_araddr_hit "logic remotestp_araddr_hit" +Toggle 0to1 remotestp_awaddr_hit_reg "logic remotestp_awaddr_hit_reg" +Toggle 0to1 remotestp_awaddr_hit "logic remotestp_awaddr_hit" +Toggle 0to1 remotestp_araddr_hit_reg "logic remotestp_araddr_hit_reg" +CHECKSUM: "3973102288 873504640" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main +Toggle 1to0 uclk_usr_q1 "logic uclk_usr_q1" +Toggle 0to1 uclk_usr_q1 "logic uclk_usr_q1" +Toggle 1to0 uclk_usr_q2 "logic uclk_usr_q2" +Toggle 0to1 uclk_usr_q2 "logic uclk_usr_q2" +Toggle 0to1 clk_div2_q1 "logic clk_div2_q1" +Toggle 1to0 clk_div2_q1 "logic clk_div2_q1" +Toggle 0to1 uclk_usr_div2_q2 "logic uclk_usr_div2_q2" +Toggle 1to0 uclk_usr_div2_q2 "logic uclk_usr_div2_q2" +Toggle 0to1 uclk_usr_div2_q1 "logic uclk_usr_div2_q1" +Toggle 1to0 uclk_usr_div2_q1 "logic uclk_usr_div2_q1" +Toggle 0to1 clk_div4_q2 "logic clk_div4_q2" +Toggle 1to0 clk_div4_q2 "logic clk_div4_q2" +Toggle 0to1 clk_div4_q1 "logic clk_div4_q1" +Toggle 1to0 clk_div4_q1 "logic clk_div4_q1" +Toggle 0to1 clk_div2_q2 "logic clk_div2_q2" +Toggle 1to0 clk_div2_q2 "logic clk_div2_q2" +Toggle 0to1 pr2sr_tdo "logic pr2sr_tdo" +Toggle 1to0 pr2sr_tdo "logic pr2sr_tdo" +Toggle 0to1 sr2pr_tckena "logic sr2pr_tckena" +Toggle 1to0 sr2pr_tckena "logic sr2pr_tckena" +Toggle 0to1 sr2pr_tms "logic sr2pr_tms" +Toggle 1to0 sr2pr_tms "logic sr2pr_tms" +Toggle 0to1 sr2pr_tdi "logic sr2pr_tdi" +Toggle 1to0 sr2pr_tdi "logic sr2pr_tdi" +CHECKSUM: "2948434777 858782335" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_emif +Toggle 1to0 address [25] "logic address[26:0]" +Toggle 0to1 address [25] "logic address[26:0]" +Toggle 1to0 address [24] "logic address[26:0]" +Toggle 0to1 address [24] "logic address[26:0]" +Toggle 1to0 address [23] "logic address[26:0]" +Toggle 0to1 address [23] "logic address[26:0]" +Toggle 1to0 address [22] "logic address[26:0]" +Toggle 0to1 address [22] "logic address[26:0]" +Toggle 1to0 address [21] "logic address[26:0]" +Toggle 0to1 address [21] "logic address[26:0]" +Toggle 1to0 address [20] "logic address[26:0]" +Toggle 0to1 address [20] "logic address[26:0]" +Toggle 1to0 address [19] "logic address[26:0]" +Toggle 0to1 address [19] "logic address[26:0]" +Toggle 1to0 address [18] "logic address[26:0]" +Toggle 0to1 address [18] "logic address[26:0]" +Toggle 1to0 address [17] "logic address[26:0]" +Toggle 0to1 address [17] "logic address[26:0]" +Toggle 1to0 address [16] "logic address[26:0]" +Toggle 0to1 address [16] "logic address[26:0]" +Toggle 1to0 address [15] "logic address[26:0]" +Toggle 0to1 address [15] "logic address[26:0]" +Toggle 1to0 address [14] "logic address[26:0]" +Toggle 0to1 address [14] "logic address[26:0]" +Toggle 1to0 address [13] "logic address[26:0]" +Toggle 0to1 address [13] "logic address[26:0]" +Toggle 1to0 address [12] "logic address[26:0]" +Toggle 0to1 address [12] "logic address[26:0]" +Toggle 1to0 address [11] "logic address[26:0]" +Toggle 0to1 address [11] "logic address[26:0]" +Toggle 1to0 address [26] "logic address[26:0]" +Toggle 0to1 address [26] "logic address[26:0]" +Toggle 1to0 burstcount [1] "logic burstcount[6:0]" +Toggle 1to0 burstcount [2] "logic burstcount[6:0]" +Toggle 1to0 burstcount [5] "logic burstcount[6:0]" +Toggle 0to1 burstcount [5] "logic burstcount[6:0]" +Toggle 1to0 burstcount [4] "logic burstcount[6:0]" +Toggle 0to1 burstcount [4] "logic burstcount[6:0]" +Toggle 1to0 burstcount [3] "logic burstcount[6:0]" +Toggle 0to1 burstcount [3] "logic burstcount[6:0]" +Toggle 1to0 burstcount [6] "logic burstcount[6:0]" +Toggle 0to1 burstcount [6] "logic burstcount[6:0]" +Toggle byteenable "logic byteenable[71:0]" +Toggle 0to1 ecc_interrupt "logic ecc_interrupt" +Toggle 1to0 ecc_interrupt "logic ecc_interrupt" +Toggle 0to1 writeresponsevalid "logic writeresponsevalid" +Toggle 1to0 writeresponsevalid "logic writeresponsevalid" +Toggle 0to1 readdata [575] "logic readdata[575:0]" +Toggle 1to0 readdata [575] "logic readdata[575:0]" +Toggle 0to1 readdata [512] "logic readdata[575:0]" +Toggle 1to0 readdata [512] "logic readdata[575:0]" +Toggle 0to1 readdata [513] "logic readdata[575:0]" +Toggle 1to0 readdata [513] "logic readdata[575:0]" +Toggle 0to1 readdata [514] "logic readdata[575:0]" +Toggle 1to0 readdata [514] "logic readdata[575:0]" +Toggle 0to1 readdata [515] "logic readdata[575:0]" +Toggle 1to0 readdata [515] "logic readdata[575:0]" +Toggle 0to1 readdata [516] "logic readdata[575:0]" +Toggle 1to0 readdata [516] "logic readdata[575:0]" +Toggle 0to1 readdata [517] "logic readdata[575:0]" +Toggle 1to0 readdata [517] "logic readdata[575:0]" +Toggle 0to1 readdata [518] "logic readdata[575:0]" +Toggle 1to0 readdata [518] "logic readdata[575:0]" +Toggle 0to1 readdata [519] "logic readdata[575:0]" +Toggle 1to0 readdata [519] "logic readdata[575:0]" +Toggle 0to1 readdata [520] "logic readdata[575:0]" +Toggle 1to0 readdata [520] "logic readdata[575:0]" +Toggle 0to1 readdata [521] "logic readdata[575:0]" +Toggle 1to0 readdata [521] "logic readdata[575:0]" +Toggle 0to1 readdata [522] "logic readdata[575:0]" +Toggle 1to0 readdata [522] "logic readdata[575:0]" +Toggle 0to1 readdata [523] "logic readdata[575:0]" +Toggle 1to0 readdata [523] "logic readdata[575:0]" +Toggle 0to1 readdata [524] "logic readdata[575:0]" +Toggle 1to0 readdata [524] "logic readdata[575:0]" +Toggle 0to1 readdata [525] "logic readdata[575:0]" +Toggle 1to0 readdata [525] "logic readdata[575:0]" +Toggle 0to1 readdata [526] "logic readdata[575:0]" +Toggle 1to0 readdata [526] "logic readdata[575:0]" +Toggle 0to1 readdata [527] "logic readdata[575:0]" +Toggle 1to0 readdata [527] "logic readdata[575:0]" +Toggle 0to1 readdata [528] "logic readdata[575:0]" +Toggle 1to0 readdata [528] "logic readdata[575:0]" +Toggle 0to1 readdata [529] "logic readdata[575:0]" +Toggle 1to0 readdata [529] "logic readdata[575:0]" +Toggle 0to1 readdata [530] "logic readdata[575:0]" +Toggle 1to0 readdata [530] "logic readdata[575:0]" +Toggle 0to1 readdata [531] "logic readdata[575:0]" +Toggle 1to0 readdata [531] "logic readdata[575:0]" +Toggle 0to1 readdata [532] "logic readdata[575:0]" +Toggle 1to0 readdata [532] "logic readdata[575:0]" +Toggle 0to1 readdata [533] "logic readdata[575:0]" +Toggle 1to0 readdata [533] "logic readdata[575:0]" +Toggle 0to1 readdata [534] "logic readdata[575:0]" +Toggle 1to0 readdata [534] "logic readdata[575:0]" +Toggle 0to1 readdata [535] "logic readdata[575:0]" +Toggle 1to0 readdata [535] "logic readdata[575:0]" +Toggle 0to1 readdata [536] "logic readdata[575:0]" +Toggle 1to0 readdata [536] "logic readdata[575:0]" +Toggle 0to1 readdata [537] "logic readdata[575:0]" +Toggle 1to0 readdata [537] "logic readdata[575:0]" +Toggle 0to1 readdata [538] "logic readdata[575:0]" +Toggle 1to0 readdata [538] "logic readdata[575:0]" +Toggle 0to1 readdata [539] "logic readdata[575:0]" +Toggle 1to0 readdata [539] "logic readdata[575:0]" +Toggle 0to1 readdata [540] "logic readdata[575:0]" +Toggle 1to0 readdata [540] "logic readdata[575:0]" +Toggle 0to1 readdata [541] "logic readdata[575:0]" +Toggle 1to0 readdata [541] "logic readdata[575:0]" +Toggle 0to1 readdata [542] "logic readdata[575:0]" +Toggle 1to0 readdata [542] "logic readdata[575:0]" +Toggle 0to1 readdata [543] "logic readdata[575:0]" +Toggle 1to0 readdata [543] "logic readdata[575:0]" +Toggle 0to1 readdata [544] "logic readdata[575:0]" +Toggle 1to0 readdata [544] "logic readdata[575:0]" +Toggle 0to1 readdata [545] "logic readdata[575:0]" +Toggle 1to0 readdata [545] "logic readdata[575:0]" +Toggle 0to1 readdata [546] "logic readdata[575:0]" +Toggle 1to0 readdata [546] "logic readdata[575:0]" +Toggle 0to1 readdata [547] "logic readdata[575:0]" +Toggle 1to0 readdata [547] "logic readdata[575:0]" +Toggle 0to1 readdata [548] "logic readdata[575:0]" +Toggle 1to0 readdata [548] "logic readdata[575:0]" +Toggle 0to1 readdata [549] "logic readdata[575:0]" +Toggle 1to0 readdata [549] "logic readdata[575:0]" +Toggle 0to1 readdata [550] "logic readdata[575:0]" +Toggle 1to0 readdata [550] "logic readdata[575:0]" +Toggle 0to1 readdata [551] "logic readdata[575:0]" +Toggle 1to0 readdata [551] "logic readdata[575:0]" +Toggle 0to1 readdata [552] "logic readdata[575:0]" +Toggle 1to0 readdata [552] "logic readdata[575:0]" +Toggle 0to1 readdata [553] "logic readdata[575:0]" +Toggle 1to0 readdata [553] "logic readdata[575:0]" +Toggle 0to1 readdata [554] "logic readdata[575:0]" +Toggle 1to0 readdata [554] "logic readdata[575:0]" +Toggle 0to1 readdata [555] "logic readdata[575:0]" +Toggle 1to0 readdata [555] "logic readdata[575:0]" +Toggle 0to1 readdata [556] "logic readdata[575:0]" +Toggle 1to0 readdata [556] "logic readdata[575:0]" +Toggle 0to1 readdata [557] "logic readdata[575:0]" +Toggle 1to0 readdata [557] "logic readdata[575:0]" +Toggle 0to1 readdata [558] "logic readdata[575:0]" +Toggle 1to0 readdata [558] "logic readdata[575:0]" +Toggle 0to1 readdata [559] "logic readdata[575:0]" +Toggle 1to0 readdata [559] "logic readdata[575:0]" +Toggle 0to1 readdata [560] "logic readdata[575:0]" +Toggle 1to0 readdata [560] "logic readdata[575:0]" +Toggle 0to1 readdata [561] "logic readdata[575:0]" +Toggle 1to0 readdata [561] "logic readdata[575:0]" +Toggle 0to1 readdata [562] "logic readdata[575:0]" +Toggle 1to0 readdata [562] "logic readdata[575:0]" +Toggle 0to1 readdata [563] "logic readdata[575:0]" +Toggle 1to0 readdata [563] "logic readdata[575:0]" +Toggle 0to1 readdata [564] "logic readdata[575:0]" +Toggle 1to0 readdata [564] "logic readdata[575:0]" +Toggle 0to1 readdata [565] "logic readdata[575:0]" +Toggle 1to0 readdata [565] "logic readdata[575:0]" +Toggle 0to1 readdata [566] "logic readdata[575:0]" +Toggle 1to0 readdata [566] "logic readdata[575:0]" +Toggle 0to1 readdata [567] "logic readdata[575:0]" +Toggle 1to0 readdata [567] "logic readdata[575:0]" +Toggle 0to1 readdata [568] "logic readdata[575:0]" +Toggle 1to0 readdata [568] "logic readdata[575:0]" +Toggle 0to1 readdata [569] "logic readdata[575:0]" +Toggle 1to0 readdata [569] "logic readdata[575:0]" +Toggle 0to1 readdata [570] "logic readdata[575:0]" +Toggle 1to0 readdata [570] "logic readdata[575:0]" +Toggle 0to1 readdata [571] "logic readdata[575:0]" +Toggle 1to0 readdata [571] "logic readdata[575:0]" +Toggle 0to1 readdata [572] "logic readdata[575:0]" +Toggle 1to0 readdata [572] "logic readdata[575:0]" +Toggle 0to1 readdata [573] "logic readdata[575:0]" +Toggle 1to0 readdata [573] "logic readdata[575:0]" +Toggle 0to1 readdata [574] "logic readdata[575:0]" +Toggle 1to0 readdata [574] "logic readdata[575:0]" +Toggle 0to1 writedata [575] "logic writedata[575:0]" +Toggle 1to0 writedata [575] "logic writedata[575:0]" +Toggle 0to1 writedata [512] "logic writedata[575:0]" +Toggle 1to0 writedata [512] "logic writedata[575:0]" +Toggle 0to1 writedata [513] "logic writedata[575:0]" +Toggle 1to0 writedata [513] "logic writedata[575:0]" +Toggle 0to1 writedata [514] "logic writedata[575:0]" +Toggle 1to0 writedata [514] "logic writedata[575:0]" +Toggle 0to1 writedata [515] "logic writedata[575:0]" +Toggle 1to0 writedata [515] "logic writedata[575:0]" +Toggle 0to1 writedata [516] "logic writedata[575:0]" +Toggle 1to0 writedata [516] "logic writedata[575:0]" +Toggle 0to1 writedata [517] "logic writedata[575:0]" +Toggle 1to0 writedata [517] "logic writedata[575:0]" +Toggle 0to1 writedata [518] "logic writedata[575:0]" +Toggle 1to0 writedata [518] "logic writedata[575:0]" +Toggle 0to1 writedata [519] "logic writedata[575:0]" +Toggle 1to0 writedata [519] "logic writedata[575:0]" +Toggle 0to1 writedata [520] "logic writedata[575:0]" +Toggle 1to0 writedata [520] "logic writedata[575:0]" +Toggle 0to1 writedata [521] "logic writedata[575:0]" +Toggle 1to0 writedata [521] "logic writedata[575:0]" +Toggle 0to1 writedata [522] "logic writedata[575:0]" +Toggle 1to0 writedata [522] "logic writedata[575:0]" +Toggle 0to1 writedata [523] "logic writedata[575:0]" +Toggle 1to0 writedata [523] "logic writedata[575:0]" +Toggle 0to1 writedata [524] "logic writedata[575:0]" +Toggle 1to0 writedata [524] "logic writedata[575:0]" +Toggle 0to1 writedata [525] "logic writedata[575:0]" +Toggle 1to0 writedata [525] "logic writedata[575:0]" +Toggle 0to1 writedata [526] "logic writedata[575:0]" +Toggle 1to0 writedata [526] "logic writedata[575:0]" +Toggle 0to1 writedata [527] "logic writedata[575:0]" +Toggle 1to0 writedata [527] "logic writedata[575:0]" +Toggle 0to1 writedata [528] "logic writedata[575:0]" +Toggle 1to0 writedata [528] "logic writedata[575:0]" +Toggle 0to1 writedata [529] "logic writedata[575:0]" +Toggle 1to0 writedata [529] "logic writedata[575:0]" +Toggle 0to1 writedata [530] "logic writedata[575:0]" +Toggle 1to0 writedata [530] "logic writedata[575:0]" +Toggle 0to1 writedata [531] "logic writedata[575:0]" +Toggle 1to0 writedata [531] "logic writedata[575:0]" +Toggle 0to1 writedata [532] "logic writedata[575:0]" +Toggle 1to0 writedata [532] "logic writedata[575:0]" +Toggle 0to1 writedata [533] "logic writedata[575:0]" +Toggle 1to0 writedata [533] "logic writedata[575:0]" +Toggle 0to1 writedata [534] "logic writedata[575:0]" +Toggle 1to0 writedata [534] "logic writedata[575:0]" +Toggle 0to1 writedata [535] "logic writedata[575:0]" +Toggle 1to0 writedata [535] "logic writedata[575:0]" +Toggle 0to1 writedata [536] "logic writedata[575:0]" +Toggle 1to0 writedata [536] "logic writedata[575:0]" +Toggle 0to1 writedata [537] "logic writedata[575:0]" +Toggle 1to0 writedata [537] "logic writedata[575:0]" +Toggle 0to1 writedata [538] "logic writedata[575:0]" +Toggle 1to0 writedata [538] "logic writedata[575:0]" +Toggle 0to1 writedata [539] "logic writedata[575:0]" +Toggle 1to0 writedata [539] "logic writedata[575:0]" +Toggle 0to1 writedata [540] "logic writedata[575:0]" +Toggle 1to0 writedata [540] "logic writedata[575:0]" +Toggle 0to1 writedata [541] "logic writedata[575:0]" +Toggle 1to0 writedata [541] "logic writedata[575:0]" +Toggle 0to1 writedata [542] "logic writedata[575:0]" +Toggle 1to0 writedata [542] "logic writedata[575:0]" +Toggle 0to1 writedata [543] "logic writedata[575:0]" +Toggle 1to0 writedata [543] "logic writedata[575:0]" +Toggle 0to1 writedata [544] "logic writedata[575:0]" +Toggle 1to0 writedata [544] "logic writedata[575:0]" +Toggle 0to1 writedata [545] "logic writedata[575:0]" +Toggle 1to0 writedata [545] "logic writedata[575:0]" +Toggle 0to1 writedata [546] "logic writedata[575:0]" +Toggle 1to0 writedata [546] "logic writedata[575:0]" +Toggle 0to1 writedata [547] "logic writedata[575:0]" +Toggle 1to0 writedata [547] "logic writedata[575:0]" +Toggle 0to1 writedata [548] "logic writedata[575:0]" +Toggle 1to0 writedata [548] "logic writedata[575:0]" +Toggle 0to1 writedata [549] "logic writedata[575:0]" +Toggle 1to0 writedata [549] "logic writedata[575:0]" +Toggle 0to1 writedata [550] "logic writedata[575:0]" +Toggle 1to0 writedata [550] "logic writedata[575:0]" +Toggle 0to1 writedata [551] "logic writedata[575:0]" +Toggle 1to0 writedata [551] "logic writedata[575:0]" +Toggle 0to1 writedata [552] "logic writedata[575:0]" +Toggle 1to0 writedata [552] "logic writedata[575:0]" +Toggle 0to1 writedata [553] "logic writedata[575:0]" +Toggle 1to0 writedata [553] "logic writedata[575:0]" +Toggle 0to1 writedata [554] "logic writedata[575:0]" +Toggle 1to0 writedata [554] "logic writedata[575:0]" +Toggle 0to1 writedata [555] "logic writedata[575:0]" +Toggle 1to0 writedata [555] "logic writedata[575:0]" +Toggle 0to1 writedata [556] "logic writedata[575:0]" +Toggle 1to0 writedata [556] "logic writedata[575:0]" +Toggle 0to1 writedata [557] "logic writedata[575:0]" +Toggle 1to0 writedata [557] "logic writedata[575:0]" +Toggle 0to1 writedata [558] "logic writedata[575:0]" +Toggle 1to0 writedata [558] "logic writedata[575:0]" +Toggle 0to1 writedata [559] "logic writedata[575:0]" +Toggle 1to0 writedata [559] "logic writedata[575:0]" +Toggle 0to1 writedata [560] "logic writedata[575:0]" +Toggle 1to0 writedata [560] "logic writedata[575:0]" +Toggle 0to1 writedata [561] "logic writedata[575:0]" +Toggle 1to0 writedata [561] "logic writedata[575:0]" +Toggle 0to1 writedata [562] "logic writedata[575:0]" +Toggle 1to0 writedata [562] "logic writedata[575:0]" +Toggle 0to1 writedata [563] "logic writedata[575:0]" +Toggle 1to0 writedata [563] "logic writedata[575:0]" +Toggle 0to1 writedata [564] "logic writedata[575:0]" +Toggle 1to0 writedata [564] "logic writedata[575:0]" +Toggle 0to1 writedata [565] "logic writedata[575:0]" +Toggle 1to0 writedata [565] "logic writedata[575:0]" +Toggle 0to1 writedata [566] "logic writedata[575:0]" +Toggle 1to0 writedata [566] "logic writedata[575:0]" +Toggle 0to1 writedata [567] "logic writedata[575:0]" +Toggle 1to0 writedata [567] "logic writedata[575:0]" +Toggle 0to1 writedata [568] "logic writedata[575:0]" +Toggle 1to0 writedata [568] "logic writedata[575:0]" +Toggle 0to1 writedata [569] "logic writedata[575:0]" +Toggle 1to0 writedata [569] "logic writedata[575:0]" +Toggle 0to1 writedata [570] "logic writedata[575:0]" +Toggle 1to0 writedata [570] "logic writedata[575:0]" +Toggle 0to1 writedata [571] "logic writedata[575:0]" +Toggle 1to0 writedata [571] "logic writedata[575:0]" +Toggle 0to1 writedata [572] "logic writedata[575:0]" +Toggle 1to0 writedata [572] "logic writedata[575:0]" +Toggle 0to1 writedata [573] "logic writedata[575:0]" +Toggle 1to0 writedata [573] "logic writedata[575:0]" +Toggle 0to1 writedata [574] "logic writedata[575:0]" +Toggle 1to0 writedata [574] "logic writedata[575:0]" +CHECKSUM: "509893243 416426085" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_ctrl +Condition 2 "646959288" "(((!req_pr_start_1x)) ? req_clr_err : req_clr_err_1x) 1 -1" +ANNOTATION: " PR FLOW taken taken care at unit level hence excluded " +Condition 16 "4195840746" "(pr_ip_sink_ready && pr_ip_datavalid) 1 -1" +ANNOTATION: " PR FLOW taken taken care at unit level hence excluded " +Condition 11 "4223883810" "(((pr_ip_success & req_pr_push_cmplt_1x)) ? PR_CTL_REQ_COMPLETE : PR_CTL_PR_IN_PROGRESS) 1 -1" +ANNOTATION: " PR FLOW taken taken care at unit level hence excluded " +Condition 14 "760480173" "((((!req_pr_start_1x)) && ((!req_pr_push_cmplt_1x))) ? PR_CTL_WAIT_FOR_REQ : PR_CTL_REINIT_SERVICE) 1 -1" +ANNOTATION: " PR FLOW taken taken care at unit level hence excluded " +Condition 4 "3062045099" "(((pr_control_state[PR_CTL_WAIT_FOR_REQ_BIT] & (!master_reset))) ? PR_RST_ACK : PR_RST_REQ) 1 -1" +ANNOTATION: " PR FLOW taken taken care at unit level hence excluded " +Condition 12 "2458064432" "(pr_freeze_wait_cmplt ? PR_CTL_PORT_OO_RESET : PR_CTL_REQ_COMPLETE) 1 -1" +ANNOTATION: " PR FLOW taken taken care at unit level hence excluded " +Condition 13 "1177473825" "(pr_reset_wait_cmplt ? PR_CTL_REINIT_SERVICE : PR_CTL_PORT_OO_RESET) 1 -1" +ANNOTATION: " PR FLOW taken taken care at unit level hence excluded " +Condition 7 "3178294690" "(req_clr_err_1x ? PR_CTL_REQ_COMPLETE : PR_CTL_PORT_RESET) 1 -1" +ANNOTATION: " PR FLOW taken taken care at unit level hence excluded " +Condition 10 "3685229754" "(((!pr_fifo_empty)) ? PR_CTL_PR_IN_PROGRESS : PR_CTL_INITIATE_PR) 1 -1" +ANNOTATION: " PR FLOW taken taken care at unit level hence excluded " +Condition 5 "1437247168" "(((!req_pr_control_reset)) ? PR_RST_IDLE : PR_RST_ACK) 1 -1" +ANNOTATION: " PR FLOW taken taken care at unit level hence excluded " +Condition 9 "2389850356" "(pr_freeze_wait_cmplt ? PR_CTL_INITIATE_PR : PR_CTL_AFU_FREEZE) 1 -1" +ANNOTATION: " PR FLOW taken taken care at unit level hence excluded " +Condition 8 "764555221" "(pr_reset_wait_cmplt ? PR_CTL_AFU_FREEZE : PR_CTL_PORT_RESET) 1 -1" +Condition 3 "1022244949" "(req_pr_control_reset ? PR_RST_REQ : PR_RST_IDLE) 1 -1" +CHECKSUM: "509893243 1549584433" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_ctrl +Toggle 1to0 req_pr_push_cmplt_1x "logic req_pr_push_cmplt_1x" +Toggle 0to1 req_pr_push_cmplt_1x "logic req_pr_push_cmplt_1x" +Toggle 1to0 req_pr_push_cmplt "logic req_pr_push_cmplt" +Toggle 0to1 req_pr_push_cmplt "logic req_pr_push_cmplt" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle rsp_pr_fifo_credits "logic rsp_pr_fifo_credits[8:0]" +Toggle 1to0 rsp_pr_ack_reset "logic rsp_pr_ack_reset" +Toggle 0to1 rsp_pr_ack_reset "logic rsp_pr_ack_reset" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle pr_ip_status_sw_remap "logic pr_ip_status_sw_remap[2:0]" +Toggle 1to0 pr_ip_success "logic pr_ip_success" +Toggle 0to1 pr_ip_success "logic pr_ip_success" +Toggle 1to0 pr_port_mask [0] "logic pr_port_mask[0:0]" +Toggle 0to1 pr_port_mask [0] "logic pr_port_mask[0:0]" +Toggle 1to0 pr_reset [0] "logic pr_reset[0:0]" +Toggle 0to1 pr_reset [0] "logic pr_reset[0:0]" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle pr_reset_cycle_cnt "logic pr_reset_cycle_cnt[7:0]" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle pr_reset_next "logic pr_reset_next[2:0]" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle pr_reset_state "logic pr_reset_state[2:0]" +Toggle 1to0 pr_reset_wait_cmplt "logic pr_reset_wait_cmplt" +Toggle 0to1 pr_reset_wait_cmplt "logic pr_reset_wait_cmplt" +Toggle 1to0 req_pr_control_reset "logic req_pr_control_reset" +Toggle 0to1 req_pr_control_reset "logic req_pr_control_reset" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle pr_ip_status "logic pr_ip_status[2:0]" +Toggle 1to0 pr_fifo_empty "logic pr_fifo_empty" +Toggle 0to1 pr_fifo_empty "logic pr_fifo_empty" +Toggle 1to0 pr_fifo_full "logic pr_fifo_full" +Toggle 0to1 pr_fifo_full "logic pr_fifo_full" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle pr_fifo_num_entries "logic pr_fifo_num_entries[8:0]" +Toggle 1to0 pr_fifo_pop "logic pr_fifo_pop" +Toggle 0to1 pr_fifo_pop "logic pr_fifo_pop" +Toggle 1to0 pr_fifo_pop_q "logic pr_fifo_pop_q" +Toggle 0to1 pr_fifo_pop_q "logic pr_fifo_pop_q" +Toggle 1to0 pr_fifo_push "logic pr_fifo_push" +Toggle 0to1 pr_fifo_push "logic pr_fifo_push" +Toggle 1to0 pr_freeze [0] "logic pr_freeze[0:0]" +Toggle 0to1 pr_freeze [0] "logic pr_freeze[0:0]" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle pr_freeze_cycle_cnt "logic pr_freeze_cycle_cnt[7:0]" +Toggle 1to0 pr_freeze_wait_cmplt "logic pr_freeze_wait_cmplt" +Toggle 0to1 pr_freeze_wait_cmplt "logic pr_freeze_wait_cmplt" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle pr_host_status_sw_remap "logic pr_host_status_sw_remap[3:0]" +Toggle 1to0 pr_ip_datavalid "logic pr_ip_datavalid" +Toggle 0to1 pr_ip_datavalid "logic pr_ip_datavalid" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle pr_ip_dword_cnt "logic pr_ip_dword_cnt[31:0]" +Toggle 1to0 pr_ip_reset_n "logic pr_ip_reset_n" +Toggle 0to1 pr_ip_reset_n "logic pr_ip_reset_n" +Toggle 1to0 pr_ip_sink_data_mismatch "logic pr_ip_sink_data_mismatch" +Toggle 0to1 pr_ip_sink_data_mismatch "logic pr_ip_sink_data_mismatch" +Toggle 1to0 pr_ip_sink_ready "logic pr_ip_sink_ready" +Toggle 0to1 pr_ip_sink_ready "logic pr_ip_sink_ready" +Toggle 1to0 pr_ip_sink_ready_raw "logic pr_ip_sink_ready_raw" +Toggle 0to1 pr_ip_sink_ready_raw "logic pr_ip_sink_ready_raw" +Toggle 1to0 pr_ip_start "logic pr_ip_start" +Toggle 0to1 pr_ip_start "logic pr_ip_start" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle pr_fifo_dout_w_parity "logic pr_fifo_dout_w_parity[35:0]" +Toggle 1to0 i_pr_control [4] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [4] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [8] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [8] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [9] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [9] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [12] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [12] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [13] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [13] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [14] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [14] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [32] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [32] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [33] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [33] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [34] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [34] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [35] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [35] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [36] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [36] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [37] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [37] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [38] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [38] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [39] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [39] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [40] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [40] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [41] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [41] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [42] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [42] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [43] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [43] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [44] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [44] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [45] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [45] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [46] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [46] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [47] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [47] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [48] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [48] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [49] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [49] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [50] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [50] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [51] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [51] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [52] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [52] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [53] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [53] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [54] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [54] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [55] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [55] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [56] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [56] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [57] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [57] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [58] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [58] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [59] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [59] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [60] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [60] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [61] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [61] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [62] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [62] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [63] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [63] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [0] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [0] "logic i_pr_control[63:0]" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle i_pr_data "logic i_pr_data[63:0]" +Toggle 1to0 i_pr_data_valid "logic i_pr_data_valid" +Toggle 0to1 i_pr_data_valid "logic i_pr_data_valid" +Toggle 1to0 i_pr_status [1] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [1] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [2] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [2] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [3] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [3] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [4] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [4] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [5] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [5] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [6] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [6] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [7] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [7] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [8] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [8] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [24] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [24] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [25] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [25] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [26] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [26] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [27] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [27] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [0] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [0] "logic i_pr_status[63:0]" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle o_pr_control "logic o_pr_control[63:0]" +Toggle 1to0 o_pr_fifo_parity_err "logic o_pr_fifo_parity_err" +Toggle 0to1 o_pr_fifo_parity_err "logic o_pr_fifo_parity_err" +Toggle 1to0 o_pr_freeze [0] "logic o_pr_freeze[0:0]" +Toggle 0to1 o_pr_freeze [0] "logic o_pr_freeze[0:0]" +Toggle 1to0 o_pr_reset [0] "logic o_pr_reset[0:0]" +Toggle 0to1 o_pr_reset [0] "logic o_pr_reset[0:0]" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle o_pr_status "logic o_pr_status[63:0]" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle parity_during_rd "logic parity_during_rd[3:0]" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle parity_during_wr "logic parity_during_wr[3:0]" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle parity_during_wr_q "logic parity_during_wr_q[3:0]" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle pr_control_next "logic pr_control_next[8:0]" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle pr_control_state "logic pr_control_state[8:0]" +Toggle 1to0 pr_ctl_fifo_aclr "logic pr_ctl_fifo_aclr" +Toggle 0to1 pr_ctl_fifo_aclr "logic pr_ctl_fifo_aclr" +Toggle 1to0 pr_ctl_ip_reset "logic pr_ctl_ip_reset" +Toggle 0to1 pr_ctl_ip_reset "logic pr_ctl_ip_reset" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle pr_data_q "logic pr_data_q[63:0]" +Toggle 1to0 pr_data_valid_q "logic pr_data_valid_q" +Toggle 0to1 pr_data_valid_q "logic pr_data_valid_q" +Toggle 1to0 pr_fifo_aclr "logic pr_fifo_aclr" +Toggle 0to1 pr_fifo_aclr "logic pr_fifo_aclr" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle pr_fifo_din_w_parity "logic pr_fifo_din_w_parity[35:0]" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle pr_fifo_dout "logic pr_fifo_dout[31:0]" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle expected_parity "logic expected_parity[3:0]" +Toggle 1to0 i_pr_status [22] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [22] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [21] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [21] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [20] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [20] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [19] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [19] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [18] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [18] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [17] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [17] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [16] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [16] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [15] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [15] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [14] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [14] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [13] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [13] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [12] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [12] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [11] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [11] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [10] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [10] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [9] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [9] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [63] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [63] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [62] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [62] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [61] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [61] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [60] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [60] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [59] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [59] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [58] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [58] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [57] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [57] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [56] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [56] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [55] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [55] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [54] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [54] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [53] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [53] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [52] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [52] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [51] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [51] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [50] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [50] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [49] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [49] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [48] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [48] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [47] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [47] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [46] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [46] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [45] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [45] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [44] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [44] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [43] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [43] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [42] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [42] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [41] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [41] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [40] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [40] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [39] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [39] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [38] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [38] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [37] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [37] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [36] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [36] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [35] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [35] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [34] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [34] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [33] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [33] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [32] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [32] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [31] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [31] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [30] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [30] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [29] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [29] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [28] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [28] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_status [23] "logic i_pr_status[63:0]" +Toggle 0to1 i_pr_status [23] "logic i_pr_status[63:0]" +Toggle 1to0 i_pr_control [10] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [10] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [7] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [7] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [6] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [6] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [5] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [5] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [3] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [3] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [2] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [2] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [1] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [1] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [11] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [11] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [30] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [30] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [29] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [29] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [28] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [28] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [27] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [27] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [26] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [26] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [25] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [25] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [24] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [24] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [23] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [23] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [22] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [22] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [21] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [21] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [20] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [20] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [19] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [19] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [18] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [18] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [17] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [17] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [16] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [16] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [15] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [15] "logic i_pr_control[63:0]" +Toggle 1to0 i_pr_control [31] "logic i_pr_control[63:0]" +Toggle 0to1 i_pr_control [31] "logic i_pr_control[63:0]" +Toggle 0to1 o_pr_error [63] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [63] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [8] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [8] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [9] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [9] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [10] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [10] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [11] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [11] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [12] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [12] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [13] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [13] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [14] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [14] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [15] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [15] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [16] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [16] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [17] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [17] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [18] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [18] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [19] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [19] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [20] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [20] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [21] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [21] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [22] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [22] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [23] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [23] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [24] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [24] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [25] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [25] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [26] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [26] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [27] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [27] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [28] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [28] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [29] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [29] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [30] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [30] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [31] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [31] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [32] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [32] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [33] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [33] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [34] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [34] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [35] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [35] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [36] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [36] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [37] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [37] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [38] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [38] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [39] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [39] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [40] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [40] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [41] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [41] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [42] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [42] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [43] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [43] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [44] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [44] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [45] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [45] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [46] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [46] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [47] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [47] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [48] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [48] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [49] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [49] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [50] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [50] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [51] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [51] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [52] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [52] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [53] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [53] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [55] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [55] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [56] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [56] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [57] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [57] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [58] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [58] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [59] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [59] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [60] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [60] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [61] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [61] "logic o_pr_error[63:0]" +Toggle 0to1 req_pr_start_1x "logic req_pr_start_1x" +Toggle 1to0 req_pr_start_1x "logic req_pr_start_1x" +Toggle 0to1 req_pr_start "logic req_pr_start" +Toggle 1to0 req_pr_start "logic req_pr_start" +Toggle 0to1 req_clr_err "logic req_clr_err" +Toggle 1to0 req_clr_err "logic req_clr_err" +Toggle 0to1 pr_ip_error "logic pr_ip_error" +Toggle 1to0 pr_ip_error "logic pr_ip_error" +Toggle 0to1 req_clr_err_1x "logic req_clr_err_1x" +Toggle 1to0 req_clr_err_1x "logic req_clr_err_1x" +Toggle 0to1 rsp_pr_access_cmplt "logic rsp_pr_access_cmplt" +Toggle 1to0 rsp_pr_access_cmplt "logic rsp_pr_access_cmplt" +Toggle 0to1 rsp_err_overflow "logic rsp_err_overflow" +Toggle 1to0 rsp_err_overflow "logic rsp_err_overflow" +Toggle 0to1 err_clr_prev_state "logic err_clr_prev_state" +Toggle 1to0 err_clr_prev_state "logic err_clr_prev_state" +Toggle 0to1 master_reset "logic master_reset" +Toggle 1to0 master_reset "logic master_reset" +Toggle 0to1 o_pr_error [62] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [62] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [54] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [54] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [0] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [0] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [7] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [7] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [6] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [6] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [5] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [5] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [4] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [4] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [3] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [3] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [2] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [2] "logic o_pr_error[63:0]" +Toggle 0to1 o_pr_error [1] "logic o_pr_error[63:0]" +Toggle 1to0 o_pr_error [1] "logic o_pr_error[63:0]" +CHECKSUM: "1147811792 461004779" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_ctrl_io +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle inp2prc_pg_pr_status "logic inp2prc_pg_pr_status[63:0]" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle prc2out_pg_pr_ctrl "logic prc2out_pg_pr_ctrl[63:0]" +Toggle 1to0 prc2out_pg_pr_data_v "logic prc2out_pg_pr_data_v" +Toggle 0to1 prc2out_pg_pr_data_v "logic prc2out_pg_pr_data_v" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle prc2out_pg_pr_status "logic prc2out_pg_pr_status[63:0]" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle inp2prc_pg_pr_ctrl "logic inp2prc_pg_pr_ctrl[63:0]" +Toggle inp2prc_pg_error "logic inp2prc_pg_error[63:0]" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle prc2out_pg_pr_data "logic prc2out_pg_pr_data[63:0]" +ANNOTATION: " PR IP is not required to verify hence excluded " +Toggle inp2prc_pg_pr_error "logic inp2prc_pg_pr_error[63:0]" +CHECKSUM: "2725671737 1763230933" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.emif[0].ddr4_softreset_sync +Toggle 0to1 reset "logic reset" +Toggle 1to0 reset "logic reset" +CHECKSUM: "2725671737 1763230933" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.emif[1].ddr4_softreset_sync +Toggle 0to1 reset "logic reset" +Toggle 1to0 reset "logic reset" +CHECKSUM: "599439132 2452160250" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.RSP_Q[0].rsp_q +ANNOTATION: " Not used " +Toggle fifo_eccstatus "net fifo_eccstatus[1:0]" +Toggle 0to1 almost_empty "net almost_empty" +Toggle 1to0 almost_empty "net almost_empty" +Toggle fifo_dout "net fifo_dout[575:0]" +Toggle fifo_din "net fifo_din[575:0]" +Toggle 0to1 full "net full" +Toggle 1to0 full "net full" +Toggle 0to1 fifo_err "logic fifo_err" +Toggle 1to0 fifo_err "logic fifo_err" +Toggle 0to1 almost_full "net almost_full" +Toggle 1to0 almost_full "net almost_full" +CHECKSUM: "599439132 2452160250" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.RSP_Q[1].rsp_q +Toggle fifo_eccstatus "net fifo_eccstatus[1:0]" +Toggle fifo_dout "net fifo_dout[575:0]" +Toggle 0to1 almost_empty "net almost_empty" +Toggle 1to0 almost_empty "net almost_empty" +Toggle 0to1 fifo_err "logic fifo_err" +Toggle 1to0 fifo_err "logic fifo_err" +Toggle 0to1 full "net full" +Toggle 1to0 full "net full" +Toggle fifo_din "net fifo_din[575:0]" +CHECKSUM: "599439132 1241846098" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.req_q +Toggle fifo_eccstatus "net fifo_eccstatus[1:0]" +Toggle 0to1 almost_empty "net almost_empty" +Toggle 1to0 almost_empty "net almost_empty" +Toggle fifo_dout "net fifo_dout[683:0]" +Toggle fifo_din "net fifo_din[683:0]" +Toggle 0to1 full "net full" +Toggle 1to0 full "net full" +Toggle 0to1 fifo_err "logic fifo_err" +Toggle 1to0 fifo_err "logic fifo_err" +CHECKSUM: "599439132 995603160" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.req_mdata_q +Toggle fifo_eccstatus "net fifo_eccstatus[1:0]" +Toggle 0to1 almost_empty "net almost_empty" +Toggle 1to0 almost_empty "net almost_empty" +Toggle fifo_din "net fifo_din[7:0]" +Toggle fifo_dout "net fifo_dout[7:0]" +Toggle 0to1 full "net full" +Toggle 1to0 full "net full" +Toggle 0to1 fifo_err "logic fifo_err" +Toggle 1to0 fifo_err "logic fifo_err" +CHECKSUM: "1259019545 702362531" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_fn2mx_a_port.r.axis_pl_stage[0].axis_reg_inst +Condition 1 "4206754987" "(((~genblk1.s_tready_pre)) && genblk1.s_tready_reg) 1 -1" (1 "01") +CHECKSUM: "1259019545 702362531" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_fn2mx_b_port.r.axis_pl_stage[0].axis_reg_inst +Condition 2 "1399699162" "(m_tready || ((~m_tvalid))) 1 -1" (1 "00") +Condition 2 "1399699162" "(m_tready || ((~m_tvalid))) 1 -1" (3 "10") +Condition 1 "4206754987" "(((~genblk1.s_tready_pre)) && genblk1.s_tready_reg) 1 -1" (1 "01") +CHECKSUM: "1259019545 702362531" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_mx2fn_a_port.r.axis_pl_stage[0].axis_reg_inst +Condition 1 "4206754987" "(((~genblk1.s_tready_pre)) && genblk1.s_tready_reg) 1 -1" (1 "01") +CHECKSUM: "1259019545 702362531" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_fn2mx_a_port.r.axis_pl_stage[0].axis_reg_inst +ANNOTATION: " Not poassible to achive baackpressurefor this condition " +Condition 1 "4206754987" "(((~genblk1.s_tready_pre)) && genblk1.s_tready_reg) 1 -1" (1 "01") +CHECKSUM: "1259019545 702362531" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_mx2fn_a_port.r.axis_pl_stage[0].axis_reg_inst +ANNOTATION: " Not poassible to achive baackpressurefor this condition " +Condition 1 "4206754987" "(((~genblk1.s_tready_pre)) && genblk1.s_tready_reg) 1 -1" (1 "01") +CHECKSUM: "2063190404 2684740673" +INSTANCE: tb_top.DUT.afu_top.port_gasket.port_reset_fsm_inst +Block 26 "695072072" "vf_flr_access_error <= 1'b1;" +Block 33 "3310845274" "flr_rcvd_vf_flag <= 1'b0;" +CHECKSUM: "599439132 3833084147" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.RSP_Q[1].rsp_q +Block 4 "2246164006" "fifo_err <= 1'b1;" +Block 5 "1895881913" "fifo_err <= 1'b1;" +CHECKSUM: "599439132 3833084147" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.RSP_Q[0].rsp_q +Block 4 "2246164006" "fifo_err <= 1'b1;" +Block 5 "1895881913" "fifo_err <= 1'b1;" +CHECKSUM: "599439132 3833084147" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.req_mdata_q +Block 4 "2246164006" "fifo_err <= 1'b1;" +Block 5 "1895881913" "fifo_err <= 1'b1;" +CHECKSUM: "599439132 3833084147" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.genblk2.mem_intf_reorder_inst.req_q +Block 4 "2246164006" "fifo_err <= 1'b1;" +Block 5 "1895881913" "fifo_err <= 1'b1;" +CHECKSUM: "509893243 3394510795" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_ctrl +Block 7 "3930656511" "pr_host_status_sw_remap <= 'b1;" +Block 11 "1788681413" "pr_host_status_sw_remap <= 'h00000005;" +Block 10 "2126561687" "pr_host_status_sw_remap <= 'h00000004;" +Block 9 "2325789298" "pr_host_status_sw_remap <= 'h00000003;" +Block 8 "2196759437" "pr_host_status_sw_remap <= 'h00000002;" +Block 36 "4281501622" "pr_control_next = (req_clr_err_1x ? PR_CTL_REQ_COMPLETE : PR_CTL_PORT_RESET);" +Block 37 "3123871423" "pr_control_next = (pr_reset_wait_cmplt ? PR_CTL_AFU_FREEZE : PR_CTL_PORT_RESET);" +Block 40 "604634788" "pr_control_next = ((pr_ip_success & req_pr_push_cmplt_1x) ? PR_CTL_REQ_COMPLETE : PR_CTL_PR_IN_PROGRESS);" +Block 39 "2071605344" "pr_control_next = ((!pr_fifo_empty) ? PR_CTL_PR_IN_PROGRESS : PR_CTL_INITIATE_PR);" +Block 38 "4122579806" "pr_control_next = (pr_freeze_wait_cmplt ? PR_CTL_INITIATE_PR : PR_CTL_AFU_FREEZE);" +Block 46 "313980686" "pr_fifo_pop = ((!pr_fifo_empty) & (!(pr_ip_datavalid & (!pr_ip_sink_ready))));" +Block 54 "1266242830" "pr_ctl_ip_reset <= 1'b1;" +Block 56 "1219899953" "pr_ctl_ip_reset <= 1'b1;" +Block 55 "794108049" "pr_ctl_ip_reset <= 1'b1;" +Block 57 "2918128844" "pr_reset <= 1'b1;" +Block 58 "3025202326" "pr_reset <= 1'b1;" +Block 65 "1968987337" "pr_ip_status_sw_remap = pr_pkg::SW_CONFIGURATION_SYSTEM_IS_BUSY;" +Block 68 "1904439724" "pr_ip_status_sw_remap = pr_pkg::SW_PR_ERROR_IS_TRIGGERED;" +Block 67 "3149450234" "pr_ip_status_sw_remap = pr_pkg::SW_PR_OPERATION_SUCCESSFUL;" +Block 66 "1885848429" "pr_ip_status_sw_remap = pr_pkg::SW_PR_OPERATION_IN_PROGRESS;" +Block 78 "2839576873" "pr_ip_sink_data_mismatch <= (pr_fifo_dout != pr_ip_dword_cnt);" +Block 81 "1477680655" "pr_ip_dword_cnt <= (pr_ip_dword_cnt + 1'b1);" +Block 80 "258109999" "pr_ip_dword_cnt <= (pr_fifo_dout + 1'b1);" +Block 79 "1790066008" "if ((pr_fifo_dout != pr_ip_dword_cnt))" +Block 73 "858703991" "pr_ip_sink_ready = 1'b1;" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[0].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[0].lane_gen[0].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[0].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[0].lane_gen[3].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[0].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[1].lane_gen[0].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[0].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[1].lane_gen[1].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[0].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[1].lane_gen[2].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "2585759907" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[1].emif_ddr4_inst.emif_s10_0.arch.arch_inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_0 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[0].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[0].lane_gen[1].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[0].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[0].lane_gen[2].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "3943323962" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[0].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst +Assert unnamed$$_0 "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[1].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[0].lane_gen[2].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[0].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[2].lane_gen[3].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[1].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[2].lane_gen[3].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "4249558537" +INSTANCE: tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_bpf_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "149290882" +INSTANCE: tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_pgsk_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "1407468455" +INSTANCE: tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_rsv_e_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "596308268" +INSTANCE: tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_rsv_f_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "3982549083" +INSTANCE: tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_st2mm_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[1].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[2].lane_gen[0].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "3013853906" +INSTANCE: tb_top.DUT.eth_ac_wrapper.axi_eth_sideband_tx[0] +Assert assert_payload_undef_when_valid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +CHECKSUM: "1700546831" +INSTANCE: tb_top.DUT.eth_ac_wrapper.axis_eth_tx[0] +Assert assert_payload_undef_when_valid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +CHECKSUM: "1667185649" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.hssi_afu_st_rx[0] +Assert assert_payload_undef_when_valid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +CHECKSUM: "1667185649" +INSTANCE: tb_top.DUT.hssi_ss_st_rx[0] +Assert assert_payload_undef_when_valid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +CHECKSUM: "2105066374" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.hssi_afu_st_tx[0] +Assert assert_payload_undef_when_valid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +CHECKSUM: "2105066374" +INSTANCE: tb_top.DUT.hssi_ss_st_tx[0] +Assert assert_payload_undef_when_valid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +CHECKSUM: "2649117191" +INSTANCE: tb_top.DUT.emif_fme_irq_if +Assert assert_tvalid_undef_when_not_in_reset "assertion" +CHECKSUM: "2649117191" +INSTANCE: tb_top.DUT.ext_fme_irq_if[0] +Assert assert_tvalid_undef_when_not_in_reset "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_a_port[3] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_b_port[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_b_port[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_b_port[2] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_b_port[3] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.axi_rx_if_T1 +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.ho2mx_rx_port +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2950189467" +INSTANCE: tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_rsv_b_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "3156651152" +INSTANCE: tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_achk_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "3315981227" +INSTANCE: tb_top.DUT.bpf.mm_interconnect_0.bpf_rsv_6_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "3217566904" +INSTANCE: tb_top.DUT.bpf.mm_interconnect_0.bpf_rsv_7_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_tx_a_if_t0[1] +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_tx_a_if_t1[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_tx_a_if_t1[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_fn2mx_a_port.r.axis_pl[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.pcie_wrapper.bar2mux_tx_st[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.pcie_wrapper.bar2mux_tx_st[2] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.pcie_wrapper.bar2mux_tx_st[3] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.pcie_wrapper.bar2mux_tx_st[4] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.pcie_wrapper.mux2adpt_rx_st +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.pcie_wrapper.mux2adpt_tx_st +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.pcie_wrapper.mux2bar_rx_st[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.pcie_wrapper.mux2bar_rx_st[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.pcie_wrapper.mux2bar_rx_st[2] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.pcie_wrapper.mux2bar_rx_st[3] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.pcie_wrapper.mux2bar_rx_st[4] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "3624794903" +INSTANCE: tb_top.DUT.pcie_wrapper.pcie_top.pcie_bridge.pcie_tx_bridge.pcie_tx_bridge_htile +Assert assert_forward_pkt_cnt_overflow "assertion" +Assert assert_forward_pkt_cnt_underflow "assertion" +CHECKSUM: "509893243" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_ctrl +Assert unnamed$$_0_0 "assertion" +Assert unnamed$$_0_0 "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[0].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[1].lane_gen[3].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "2438023511" +INSTANCE: tb_top.DUT.pcie_wrapper.adpt2pcie_tx_st +Assert assert_tdata_tuser_ch0_undef_when_valid_high "assertion" +Assert assert_valid_undef "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tdata_tuser_ch1_undef_when_valid_high "assertion" +CHECKSUM: "2438023511" +INSTANCE: tb_top.DUT.pcie_wrapper.arb2adpt_tx_st +Assert assert_tdata_tuser_ch0_undef_when_valid_high "assertion" +Assert assert_valid_undef "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tdata_tuser_ch1_undef_when_valid_high "assertion" +CHECKSUM: "2438023511" +INSTANCE: tb_top.DUT.pcie_wrapper.fltr2arb_tx_st +Assert assert_tdata_tuser_ch0_undef_when_valid_high "assertion" +Assert assert_valid_undef "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tdata_tuser_ch1_undef_when_valid_high "assertion" +CHECKSUM: "2438023511" +INSTANCE: tb_top.DUT.pcie_wrapper.fltr2msix_tx_st +Assert assert_tdata_tuser_ch0_undef_when_valid_high "assertion" +Assert assert_valid_undef "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tdata_tuser_ch1_undef_when_valid_high "assertion" +CHECKSUM: "2438023511" +INSTANCE: tb_top.DUT.pcie_wrapper.pcie_aligned_tx_st +Assert assert_tdata_tuser_ch0_undef_when_valid_high "assertion" +Assert assert_valid_undef "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tdata_tuser_ch1_undef_when_valid_high "assertion" +CHECKSUM: "2438023511" +INSTANCE: tb_top.DUT.pcie_wrapper.pcie_top.pcie_bridge.pcie_axis_tx_if +Assert assert_tdata_tuser_ch0_undef_when_valid_high "assertion" +Assert assert_valid_undef "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tdata_tuser_ch1_undef_when_valid_high "assertion" +CHECKSUM: "3577499112" +INSTANCE: tb_top.DUT.pcie_wrapper.pcie_top.pcie_bridge +Assert assert_rx_avst_fifo_overflow "assertion" +CHECKSUM: "2649117191" +INSTANCE: tb_top.DUT.ext_fme_irq_if[1] +Assert assert_tvalid_undef_when_not_in_reset "assertion" +CHECKSUM: "2649117191" +INSTANCE: tb_top.DUT.ext_fme_irq_if[2] +Assert assert_tvalid_undef_when_not_in_reset "assertion" +CHECKSUM: "272988997" +INSTANCE: tb_top.DUT.pcie_rx_st +Assert assert_tdata_tuser_ch0_undef_when_valid_high "assertion" +Assert assert_valid_undef "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tdata_tuser_ch1_undef_when_valid_high "assertion" +CHECKSUM: "272988997" +INSTANCE: tb_top.DUT.pcie_wrapper.adpt2adpt_rx_st +Assert assert_tdata_tuser_ch0_undef_when_valid_high "assertion" +Assert assert_valid_undef "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tdata_tuser_ch1_undef_when_valid_high "assertion" +CHECKSUM: "272988997" +INSTANCE: tb_top.DUT.pcie_wrapper.pcie2adpt_rx_st +Assert assert_tdata_tuser_ch0_undef_when_valid_high "assertion" +Assert assert_valid_undef "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tdata_tuser_ch1_undef_when_valid_high "assertion" +CHECKSUM: "1775144990" +INSTANCE: tb_top.DUT.pcie_wrapper.mmio2arb_tx_st +Assert assert_tdata_tuser_ch0_undef_when_valid_high "assertion" +Assert assert_valid_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +CHECKSUM: "1775144990" +INSTANCE: tb_top.DUT.pcie_wrapper.msix2arb_tx_st +Assert assert_tdata_tuser_ch0_undef_when_valid_high "assertion" +Assert assert_valid_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +CHECKSUM: "2438023511" +INSTANCE: tb_top.DUT.pcie_tx_st +Assert assert_tdata_tuser_ch0_undef_when_valid_high "assertion" +Assert assert_valid_undef "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tdata_tuser_ch1_undef_when_valid_high "assertion" +CHECKSUM: "2438023511" +INSTANCE: tb_top.DUT.pcie_wrapper.adpt2fltr_tx_st +Assert assert_tdata_tuser_ch0_undef_when_valid_high "assertion" +Assert assert_valid_undef "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tdata_tuser_ch1_undef_when_valid_high "assertion" +CHECKSUM: "1270336168" +INSTANCE: tb_top.DUT.bpf.mm_interconnect_0.bpf_fme_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "2346868557" +INSTANCE: tb_top.DUT.eth_ac_wrapper.eth_top.address_decoder_inst.mm_interconnect_0.mm_to_mac_0_avalon_universal_slave_0_agent +Assert ERROR_write_response_and_read_response_cannot_happen_same_time "assertion" +CHECKSUM: "2346868557" +INSTANCE: tb_top.DUT.eth_ac_wrapper.eth_top.address_decoder_inst.mm_interconnect_0.mm_to_phy_0_avalon_universal_slave_0_agent +Assert ERROR_write_response_and_read_response_cannot_happen_same_time "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[1].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[2].lane_gen[1].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_fn2mx_a_port.r.axis_pl[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_mx2fn_a_port.r.axis_pl[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_mx2fn_a_port.r.axis_pl[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_fn2mx_a_port.r.axis_pl[0] +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +CHECKSUM: "3943323962" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[1].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst +Assert unnamed$$_0 "assertion" +CHECKSUM: "2585759907" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[0].emif_ddr4_inst.emif_s10_0.arch.arch_inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_0 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[1].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[0].lane_gen[0].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.afu_rx_b_port[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.afu_rx_b_port[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_a_port[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.afu_tx_a_port[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.afu_tx_a_port[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.afu_tx_b_port[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.afu_tx_b_port[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_mx2fn_a_port.r.axis_pl[0] +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_mx2fn_a_port.r.axis_pl[1] +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.tag_remap.map.ho2mx_rx_in +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.tag_remap.map.mx2ho_tx_out[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[1].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[1].lane_gen[0].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[1].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[0].lane_gen[3].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.tag_remap.mx2ho_tx_port_vec[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.tag_remap.mx2ho_tx_remap_vec[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.pcie_ss_axis_rx_if +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.pcie_ss_axis_tx_if +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.pcie_wrapper.adpt2mux_rx_st +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.pcie_wrapper.adpt2mux_tx_st +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.pcie_wrapper.bar2mux_tx_st[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[1].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[0].lane_gen[1].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_a_port[3] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_b_port[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_b_port[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_b_port[2] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_b_port[3] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[1].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[1].lane_gen[3].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[0].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[2].lane_gen[2].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.arb2ho_tx_port +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.arb2mx_rx_b +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.axis_axil_bridge.axis_tx_st[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.axis_axil_bridge.axis_tx_st[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_a_port[2] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_a_port[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_a_port[2] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[1].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[1].lane_gen[2].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.ho2mx_rx_remap +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.local_commit.commit_in +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_a_port[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_a_port[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[1].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[2].lane_gen[2].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "523854596" +INSTANCE: tb_top.DUT.bpf.mm_interconnect_0.bpf_emif_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "3164597302" +INSTANCE: tb_top.DUT.bpf.mm_interconnect_0.bpf_rsv_5_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "2909001026" +INSTANCE: tb_top.DUT.bpf.mm_interconnect_0.bpf_pcie_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "1228243273" +INSTANCE: tb_top.DUT.bpf.mm_interconnect_0.bpf_hssi_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "914132256" +INSTANCE: tb_top.DUT.bpf.mm_interconnect_0.bpf_pmci_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "2923597957" +INSTANCE: tb_top.DUT.emif_top_inst +Assert assert_pr_freeze_undif "assertion" +CHECKSUM: "2632955550" +INSTANCE: tb_top.DUT.pcie_wrapper.msix_rsp +Assert assert_tdata_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +CHECKSUM: "1432213158" +INSTANCE: tb_top.DUT.eth_ac_wrapper.axis_eth_rx[0] +Assert assert_payload_undef_when_valid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +CHECKSUM: "3815094446" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.afu_eth_sideband_rx[0] +Assert assert_payload_undef_when_valid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +CHECKSUM: "3815094446" +INSTANCE: tb_top.DUT.eth_ac_wrapper.axi_eth_sideband_rx[0] +Assert assert_payload_undef_when_valid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +CHECKSUM: "3013853906" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_hssi_top_inst.afu_eth_sideband_tx[0] +Assert assert_payload_undef_when_valid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[0].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[2].lane_gen[0].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_a_if_t1[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_a_if_t1[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_tx_a_if_t0[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.sink_in[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.sink_in[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_port +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_remap +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.axi_rx_if_T1 +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_a_if_t0[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_a_if_t0[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tdata_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.port_traffic_control_inst.tx_fifo_st +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.port_traffic_control_inst.tx_st +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.tx_filter_if +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.tx_filter_mmio_if +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.tx_port_control_if +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.afu_rx_a_port[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "2277721912" +INSTANCE: tb_top.DUT.afu_top.afu_rx_a_port[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[0].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[2].lane_gen[1].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "3127617925" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[1].emif_ddr4_inst.emif_s10_0.arch.arch_inst.io_tiles_wrap_inst.abphy_tiles.io_tiles_abphy_inst.tile_gen[1].lane_gen[1].lane_inst.lane_inst.inst.inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_120 "assertion" +Assert unnamed$$_119 "assertion" +Assert unnamed$$_118 "assertion" +Assert unnamed$$_117 "assertion" +Assert unnamed$$_116 "assertion" +Assert unnamed$$_115 "assertion" +Assert unnamed$$_114 "assertion" +Assert unnamed$$_113 "assertion" +Assert unnamed$$_112 "assertion" +Assert unnamed$$_111 "assertion" +Assert unnamed$$_110 "assertion" +Assert unnamed$$_109 "assertion" +Assert unnamed$$_108 "assertion" +Assert unnamed$$_107 "assertion" +Assert unnamed$$_106 "assertion" +Assert unnamed$$_105 "assertion" +Assert unnamed$$_104 "assertion" +Assert unnamed$$_103 "assertion" +Assert unnamed$$_102 "assertion" +Assert unnamed$$_101 "assertion" +Assert unnamed$$_100 "assertion" +Assert unnamed$$_99 "assertion" +Assert unnamed$$_98 "assertion" +Assert unnamed$$_97 "assertion" +Assert unnamed$$_96 "assertion" +Assert unnamed$$_95 "assertion" +Assert unnamed$$_94 "assertion" +Assert unnamed$$_93 "assertion" +Assert unnamed$$_92 "assertion" +Assert unnamed$$_91 "assertion" +Assert unnamed$$_90 "assertion" +Assert unnamed$$_89 "assertion" +Assert unnamed$$_88 "assertion" +Assert unnamed$$_87 "assertion" +Assert unnamed$$_86 "assertion" +Assert unnamed$$_85 "assertion" +Assert unnamed$$_84 "assertion" +Assert unnamed$$_83 "assertion" +Assert unnamed$$_82 "assertion" +Assert unnamed$$_81 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "2916460945" +INSTANCE: tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_bpf_mst_altera_axi4lite_master_agent +Assert ERROR_arlock_reserved_value "assertion" +Assert ERROR_arlock_reserved_value "assertion" +Assert ERROR_awlock_reserved_value "assertion" +Assert ERROR_awlock_reserved_value "assertion" +CHECKSUM: "2916460945" +INSTANCE: tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_st2mm_mst_altera_axi4lite_master_agent +Assert ERROR_arlock_reserved_value "assertion" +Assert ERROR_arlock_reserved_value "assertion" +Assert ERROR_awlock_reserved_value "assertion" +Assert ERROR_awlock_reserved_value "assertion" +CHECKSUM: "4029470343" +INSTANCE: tb_top.DUT.bpf.mm_interconnect_0.bpf_apf_mst_altera_axi4lite_master_agent +Assert ERROR_arlock_reserved_value "assertion" +Assert ERROR_arlock_reserved_value "assertion" +Assert ERROR_awlock_reserved_value "assertion" +Assert ERROR_awlock_reserved_value "assertion" +CHECKSUM: "1067207953" +INSTANCE: tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_rsv_d_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "947286115" +INSTANCE: tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_rsv_c_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "1400506628 313161863" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot +Branch 0 "3382341477" "pr_freeze_fnmx_q1" (0) "pr_freeze_fnmx_q1 1" +Branch 0 "3382341477" "pr_freeze_fnmx_q1" (0) "pr_freeze_fnmx_q1 1" +Branch 0 "3382341477" "pr_freeze_fnmx_q1" (0) "pr_freeze_fnmx_q1 1" +Branch 0 "3382341477" "pr_freeze_fnmx_q1" (0) "pr_freeze_fnmx_q1 1" +Branch 4 "803207236" "pr_freeze_fnmx_q1" (0) "pr_freeze_fnmx_q1 1" +Branch 4 "803207236" "pr_freeze_fnmx_q1" (0) "pr_freeze_fnmx_q1 1" +Branch 4 "803207236" "pr_freeze_fnmx_q1" (0) "pr_freeze_fnmx_q1 1" +Branch 4 "803207236" "pr_freeze_fnmx_q1" (0) "pr_freeze_fnmx_q1 1" +CHECKSUM: "2280438776" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[1].emif_ddr4_inst.emif_s10_0.arch.arch_inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "4127926496" +INSTANCE: tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_bpf_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "2224506641" +INSTANCE: tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_pgsk_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "3268548664" +INSTANCE: tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_rsv_e_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "2836192897" +INSTANCE: tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_rsv_f_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "10498724" +INSTANCE: tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_st2mm_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_a_port[3] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_b_port[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_b_port[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_b_port[2] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_b_port[3] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.he_lb_inst.he_lb_req.axi_rx_if_T1 +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.ho2mx_rx_port +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "1520901232" +INSTANCE: tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_rsv_b_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "746432510" +INSTANCE: tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_achk_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "4155671392" +INSTANCE: tb_top.DUT.bpf.mm_interconnect_0.bpf_rsv_6_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "4088745538" +INSTANCE: tb_top.DUT.bpf.mm_interconnect_0.bpf_rsv_7_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_tx_a_if_t0[1] +ANNOTATION: " clk and rst_n are not connected " +Assert assert_tvalid_undef_when_not_in_reset "assertion" +ANNOTATION: " clk and rst_n are not connected " +Assert assert_tvalid_tready_handshake "assertion" +ANNOTATION: " clk and rst_n are not connected " +Assert assert_tuser_undef_when_tvalid_high "assertion" +ANNOTATION: " clk and rst_n are not connected " +Assert assert_tready_undef_when_not_in_reset "assertion" +ANNOTATION: " clk and rst_n are not connected " +Assert assert_tlast_undef_when_tvalid_high "assertion" +ANNOTATION: " clk and rst_n are not connected " +Assert assert_tkeep_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_tx_a_if_t1[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_tx_a_if_t1[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_tx_b_if_t0[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_fn2mx_a_port.r.axis_pl[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.pcie_wrapper.bar2mux_tx_st[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.pcie_wrapper.bar2mux_tx_st[2] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.pcie_wrapper.bar2mux_tx_st[3] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.pcie_wrapper.bar2mux_tx_st[4] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.pcie_wrapper.mux2adpt_rx_st +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.pcie_wrapper.mux2adpt_tx_st +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.pcie_wrapper.mux2bar_rx_st[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.pcie_wrapper.mux2bar_rx_st[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.pcie_wrapper.mux2bar_rx_st[2] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.pcie_wrapper.mux2bar_rx_st[3] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.pcie_wrapper.mux2bar_rx_st[4] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "452467608" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_ctrl +Assert unnamed$$_0_0 "assertion" +CHECKSUM: "3410993657" +INSTANCE: tb_top.DUT.bpf.mm_interconnect_0.bpf_fme_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_fn2mx_a_port.r.axis_pl[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_fn2mx_b_port.r.axis_pl[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_fn2mx_b_port.r.axis_pl[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_mx2fn_a_port.r.axis_pl[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_mx2fn_a_port.r.axis_pl[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[0].pr_frz_mx2fn_b_port.r.axis_pl[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_fn2mx_a_port.r.axis_pl[0] +ANNOTATION: " Not supported " +Assert assert_tvalid_tready_handshake "assertion" +CHECKSUM: "2280438776" +INSTANCE: tb_top.DUT.emif_top_inst.mem_bank[0].emif_ddr4_inst.emif_s10_0.arch.arch_inst +Assert unnamed$$_0 "assertion" +Assert unnamed$$_80 "assertion" +Assert unnamed$$_79 "assertion" +Assert unnamed$$_78 "assertion" +Assert unnamed$$_77 "assertion" +Assert unnamed$$_76 "assertion" +Assert unnamed$$_75 "assertion" +Assert unnamed$$_74 "assertion" +Assert unnamed$$_73 "assertion" +Assert unnamed$$_72 "assertion" +Assert unnamed$$_71 "assertion" +Assert unnamed$$_70 "assertion" +Assert unnamed$$_69 "assertion" +Assert unnamed$$_68 "assertion" +Assert unnamed$$_67 "assertion" +Assert unnamed$$_66 "assertion" +Assert unnamed$$_65 "assertion" +Assert unnamed$$_64 "assertion" +Assert unnamed$$_63 "assertion" +Assert unnamed$$_62 "assertion" +Assert unnamed$$_61 "assertion" +Assert unnamed$$_60 "assertion" +Assert unnamed$$_59 "assertion" +Assert unnamed$$_58 "assertion" +Assert unnamed$$_57 "assertion" +Assert unnamed$$_56 "assertion" +Assert unnamed$$_55 "assertion" +Assert unnamed$$_54 "assertion" +Assert unnamed$$_53 "assertion" +Assert unnamed$$_52 "assertion" +Assert unnamed$$_51 "assertion" +Assert unnamed$$_50 "assertion" +Assert unnamed$$_49 "assertion" +Assert unnamed$$_48 "assertion" +Assert unnamed$$_47 "assertion" +Assert unnamed$$_46 "assertion" +Assert unnamed$$_45 "assertion" +Assert unnamed$$_44 "assertion" +Assert unnamed$$_43 "assertion" +Assert unnamed$$_42 "assertion" +Assert unnamed$$_41 "assertion" +Assert unnamed$$_40 "assertion" +Assert unnamed$$_39 "assertion" +Assert unnamed$$_38 "assertion" +Assert unnamed$$_37 "assertion" +Assert unnamed$$_36 "assertion" +Assert unnamed$$_35 "assertion" +Assert unnamed$$_34 "assertion" +Assert unnamed$$_33 "assertion" +Assert unnamed$$_32 "assertion" +Assert unnamed$$_31 "assertion" +Assert unnamed$$_30 "assertion" +Assert unnamed$$_29 "assertion" +Assert unnamed$$_28 "assertion" +Assert unnamed$$_27 "assertion" +Assert unnamed$$_26 "assertion" +Assert unnamed$$_25 "assertion" +Assert unnamed$$_24 "assertion" +Assert unnamed$$_23 "assertion" +Assert unnamed$$_22 "assertion" +Assert unnamed$$_21 "assertion" +Assert unnamed$$_20 "assertion" +Assert unnamed$$_19 "assertion" +Assert unnamed$$_18 "assertion" +Assert unnamed$$_17 "assertion" +Assert unnamed$$_16 "assertion" +Assert unnamed$$_15 "assertion" +Assert unnamed$$_14 "assertion" +Assert unnamed$$_13 "assertion" +Assert unnamed$$_12 "assertion" +Assert unnamed$$_11 "assertion" +Assert unnamed$$_10 "assertion" +Assert unnamed$$_9 "assertion" +Assert unnamed$$_8 "assertion" +Assert unnamed$$_7 "assertion" +Assert unnamed$$_6 "assertion" +Assert unnamed$$_5 "assertion" +Assert unnamed$$_4 "assertion" +Assert unnamed$$_3 "assertion" +Assert unnamed$$_2 "assertion" +Assert unnamed$$_1 "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.afu_rx_b_port[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.afu_rx_b_port[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_a_port[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.afu_tx_a_port[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.afu_tx_a_port[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.afu_tx_b_port[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.afu_tx_b_port[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_fn2mx_b_port.r.axis_pl[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_fn2mx_b_port.r.axis_pl[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_mx2fn_a_port.r.axis_pl[0] +Assert assert_tvalid_tready_handshake "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_mx2fn_a_port.r.axis_pl[1] +Assert assert_tvalid_tready_handshake "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_mx2fn_b_port.r.axis_pl[0] +Assert assert_tlast_undef_when_tvalid_high "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.p[1].pr_frz_mx2fn_b_port.r.axis_pl[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.tag_remap.map.ho2mx_rx_in +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.tag_remap.map.mx2ho_tx_out[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.tag_remap.mx2ho_tx_port_vec[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.tag_remap.mx2ho_tx_remap_vec[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.pcie_ss_axis_rx_if +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.pcie_ss_axis_tx_if +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.pcie_wrapper.adpt2mux_rx_st +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.pcie_wrapper.adpt2mux_tx_st +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.pcie_wrapper.bar2mux_tx_st[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_tx_b_if_t0[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_a_port[3] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_b_port[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_b_port[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_b_port[2] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_b_port[3] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.arb2ho_tx_port +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.arb2mx_rx_b +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.axis_axil_bridge.axis_tx_st[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.axis_axil_bridge.axis_tx_st[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_a_port[2] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_a_port[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.fn2mx_tx_a_port[2] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.ho2mx_rx_remap +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.local_commit.commit_in +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_a_port[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.mx2fn_rx_a_port[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "572096978" +INSTANCE: tb_top.DUT.bpf.mm_interconnect_0.bpf_emif_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "4253145466" +INSTANCE: tb_top.DUT.bpf.mm_interconnect_0.bpf_rsv_5_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "3091857097" +INSTANCE: tb_top.DUT.bpf.mm_interconnect_0.bpf_pcie_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "2900098174" +INSTANCE: tb_top.DUT.bpf.mm_interconnect_0.bpf_hssi_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "186836096" +INSTANCE: tb_top.DUT.bpf.mm_interconnect_0.bpf_pmci_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_a_if_t1[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_a_if_t1[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_b_if_t0[0] +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_b_if_t0[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_b_if_t1[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_b_if_t1[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_tx_a_if_t0[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.sink_in[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.sink_in[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_port +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_remap +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main.he_lb_inst.he_lb_req.axi_rx_if_T1 +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_a_if_t0[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.axi_rx_a_if_t0[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.port_traffic_control_inst.tx_fifo_st +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.port_traffic_control_inst.tx_st +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.tx_filter_if +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.tx_filter_mmio_if +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.afu_intf_inst.tx_port_control_if +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.afu_rx_a_port[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.afu_rx_a_port[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "856017130" +INSTANCE: tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_bpf_mst_altera_axi4lite_master_agent +Assert ERROR_arlock_reserved_value "assertion" +Assert ERROR_awlock_reserved_value "assertion" +CHECKSUM: "856017130" +INSTANCE: tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_st2mm_mst_altera_axi4lite_master_agent +Assert ERROR_arlock_reserved_value "assertion" +Assert ERROR_awlock_reserved_value "assertion" +CHECKSUM: "574637587" +INSTANCE: tb_top.DUT.bpf.mm_interconnect_0.bpf_apf_mst_altera_axi4lite_master_agent +Assert ERROR_arlock_reserved_value "assertion" +Assert ERROR_awlock_reserved_value "assertion" +CHECKSUM: "785937395" +INSTANCE: tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_rsv_d_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "3896659198" +INSTANCE: tb_top.DUT.afu_top.apf.mm_interconnect_0.apf_rsv_c_slv_altera_axi4lite_slave_agent +Assert ERROR_pkt_trans_write_not_asserted_when_write_cp_valid_is_asserted "assertion" +Assert ERROR_write_transaction_occurs_when_write_rsp_fifo_is_full "assertion" +Assert ERROR_write_response_occurs_when_write_rsp_fifo_is_empty "assertion" +Assert ERROR_readdata_receive_but_read_ID_fifo_is_empty "assertion" +Assert ERROR_read_transaction_occurs_when_read_rsp_fifo_is_full "assertion" +CHECKSUM: "2829284533 99381342" +INSTANCE: tb_top.DUT.afu_top.port_gasket +Toggle remotestp_status "logic remotestp_status[63:0]" +CHECKSUM: "4168874858 3413342008" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot +Toggle 1to0 pr_freeze_emif_q1 "logic pr_freeze_emif_q1" +Toggle 1to0 pr_freeze_emif_q0 "logic pr_freeze_emif_q0" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.local_commit.commit_skid.axis_pl[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.local_commit.commit_skid.axis_pl[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[0].skid.axis_pl[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[0].skid.axis_pl[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[0].skid.axis_pl[2] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[1].skid.axis_pl[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[1].skid.axis_pl[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.mx2ho_tx_ab_mux.in_pipe[1].skid.axis_pl[2] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.tag_remap.map.rx_axis_pipe.axis_pl[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.tag_remap.map.rx_axis_pipe.axis_pl[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.tag_remap.map.tx_pipe[0].tx_axis_pipe.axis_pl[0] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "4202741256" +INSTANCE: tb_top.DUT.afu_top.tag_remap.map.tx_pipe[0].tx_axis_pipe.axis_pl[1] +Assert assert_tkeep_undef_when_tvalid_high "assertion" +Assert assert_tvalid_undef_when_not_in_reset "assertion" +Assert assert_tvalid_tready_handshake "assertion" +Assert assert_tuser_undef_when_tvalid_high "assertion" +Assert assert_tready_undef_when_not_in_reset "assertion" +Assert assert_tlast_undef_when_tvalid_high "assertion" +CHECKSUM: "997395244 2982532473" +INSTANCE: tb_top.DUT.afu_top.port_gasket.pr_slot.afu_main +Toggle 0to1 pclkDiv2_q2 "logic pclkDiv2_q2" +Toggle 0to1 pclkDiv4_q1 "logic pclkDiv4_q1" +Toggle 0to1 pclkDiv4_q2 "logic pclkDiv4_q2" +Toggle 0to1 pclkDiv2_q1 "logic pclkDiv2_q1" +Toggle 0to1 uclk_usrDiv2_q2 "logic uclk_usrDiv2_q2" +Toggle 0to1 uclk_usrDiv2_q1 "logic uclk_usrDiv2_q1" diff --git a/verification/coverage/ral_exclusions.el b/verification/coverage/ral_exclusions.el new file mode 100644 index 0000000..104e1b9 --- /dev/null +++ b/verification/coverage/ral_exclusions.el @@ -0,0 +1,49 @@ +//================================================== +// This file contains the Excluded objects +// Generated By User: ppawar2x +// Format Version: 2 +// Date: Mon Feb 21 04:18:29 2022 +// ExclMode: default +//================================================== +CHECKSUM: "3290005536 3012674018" +covergroup $unit::ral_reg_afu_intf_AFU_INTF_FIRST_ERROR::cg_vals + ANNOTATION: " Not implemented " + coveritem "MaxReadReqSizeErr_value" + ANNOTATION: " Not implemented " + coveritem "VfFlrAccessErr_value" + ANNOTATION: " Not implemented " + coveritem "Vf_num_value" +CHECKSUM: "1645436629 3970278941" +covergroup $unit::ral_reg_afu_intf_AFU_INTF_ERROR::cg_vals + coveritem "Vf_num_value" + coveritem "VfFlrAccessErr_value" + coveritem "MaxReadReqSizeErr_value" + coveritem "BlockingTraffic_value" +CHECKSUM: "3501822084 2129602682" +covergroup $unit::coverage::HE_HSSI + ANNOTATION: " Not connected tied to \"0\" in the design " + coveritem "HSSI_ovfl_err" +CHECKSUM: "1689659821 3448440120" +covergroup $unit::ral_reg_afu_intf_AFU_INTF_DUMMY0::cg_vals + +CHECKSUM: "763488289 3448440120" +covergroup $unit::ral_reg_afu_intf_AFU_INTF_DUMMY1::cg_vals + +CHECKSUM: "3501822084 2129602682" +covergroup $unit::coverage::HE_HSSI + ANNOTATION: " Not connected tied to \"0\" in the design " + coveritem "HSSI_ovfl_err" +CHECKSUM: "1645436629 3970278941" +covergroup $unit::ral_reg_afu_intf_AFU_INTF_ERROR::cg_vals + coveritem "BlockingTraffic_value" + coveritem "Vf_num_value" + coveritem "VfFlrAccessErr_value" + coveritem "MaxReadReqSizeErr_value" +CHECKSUM: "3290005536 3012674018" +covergroup $unit::ral_reg_afu_intf_AFU_INTF_FIRST_ERROR::cg_vals + ANNOTATION: " Not implemented " + coveritem "Vf_num_value" + ANNOTATION: " Not implemented " + coveritem "VfFlrAccessErr_value" + ANNOTATION: " Not implemented " + coveritem "MaxReadReqSizeErr_value" diff --git a/verification/scripts/.gitignore b/verification/scripts/.gitignore new file mode 100644 index 0000000..3d05b10 --- /dev/null +++ b/verification/scripts/.gitignore @@ -0,0 +1 @@ +test_lib.svh diff --git a/verification/scripts/Makefile_MSIM.mk b/verification/scripts/Makefile_MSIM.mk new file mode 100644 index 0000000..ade747f --- /dev/null +++ b/verification/scripts/Makefile_MSIM.mk @@ -0,0 +1,199 @@ +# Copyright 2021 Intel Corporation +# SPDX-License-Identifier: MIT + +# Description: +# Makefile for VCS + +ifndef OFS_ROOTDIR + $(error undefined OFS_ROOTDIR) +endif +ifndef WORKDIR + WORKDIR := $(OFS_ROOTDIR) +endif + + +VERDIR_COMMON = $(OFS_ROOTDIR)/ofs-common/verification +TEST_DIR := $(shell $(VERDIR)/scripts/create_dir.pl $(VERDIR)/sim_msim/$(TESTNAME) ) + +SCRIPTS_DIR = $(VERDIR)/scripts +D5005_DIR = $(OFS_ROOTDIR)/sim/scripts + +export VIPDIR = $(VERDIR) +export RALDIR = $(VERDIR)/testbench/ral +export QLIB_DIR = $(SCRIPTS_DIR)/../sim_msim/libraries +export VIP_DIR = $(SCRIPTS_DIR)/.. + + +# initialize variables +QUARTUS_INSTALL_DIR=$(QUARTUS_HOME) +QSYS_SIMDIR=$(SCRIPTS_DIR)/qip +SKIP_FILE_COPY=0 +SKIP_ELAB=0 +SKIP_SIM=0 +USER_DEFINED_ELAB_OPTIONS="" +USER_DEFINED_SIM_OPTIONS="-finish exit" +TOP_LEVEL_NAME="tb_top" + +export SCRIPTS_DIR=$(VERDIR)/scripts +VLOG_OPT = +define+QUESTA +VLOG_OPT = +define+MODEL_TECH +VLOG_OPT = +define+MODELTECH +VLOG_OPT += +incdir+$(QUESTA_HOME)/verilog_src/uvm-1.2/src +VLOG_OPT += +incdir+$(VIPDIR)/vip/axi_vip/include/verilog +VLOG_OPT += +incdir+$(VIPDIR)/vip/axi_vip/include/sverilog +VLOG_OPT += +incdir+$(VIPDIR)/vip/axi_vip/src/verilog/mti +VLOG_OPT += +incdir+$(VIPDIR)/vip/axi_vip/src/sverilog/mti +VLOG_OPT += +incdir+$(VIPDIR)/vip/pcie_vip/include/verilog +VLOG_OPT += +incdir+$(VIPDIR)/vip/pcie_vip/include/sverilog +VLOG_OPT += +incdir+$(VIPDIR)/vip/pcie_vip/src/verilog/mti +VLOG_OPT += +incdir+$(VIPDIR)/vip/pcie_vip/src/sverilog/mti +VLOG_OPT += +incdir+$(VERDIR)/tests/sequences/pcie_seq +VLOG_OPT += +incdir+$(VERDIR)/tests/sequences +VLOG_OPT += +incdir+$(VERDIR)/tests +VLOG_OPT += +incdir+$(VERDIR)/testbench +VLOG_OPT += +incdir+$(VERDIR)/testbench/ral +VLOG_OPT += +incdir+$(VERDIR)/testbench/tb_pcie +VLOG_OPT += +incdir+$(VERDIR)/testbench/tb_pcie/src/verilog/mti +VLOG_OPT += +incdir+$(VIP_DIR)/vip/axi_vip/lib/linux64 +VLOG_OPT += +incdir+$(VIP_DIR)/vip/pcie_vip/lib/linux64 + +VLOG_OPT += +define+IGNORE_DF_SIM_EXIT +VLOG_OPT += +define+SIM_MODE +define+SIM_SERIAL #Enable PCIE Serial link up for p-tile +VLOG_OPT += +define+SIMULATION_MODE +VLOG_OPT += +define+UVM_DISABLE_AUTO_ITEM_RECORDING +define+UVM_NO_DEPRECATED +VLOG_OPT += +define+UVM_PACKER_MAX_BYTES=1500000 +VLOG_OPT += +define+MMIO_TIMEOUT_IN_CYCLES=1024 +VLOG_OPT += +define+SVT_PCIE_ENABLE_GEN3+GEN3 +VLOG_OPT += +define+SVT_UVM_TECHNOLOGY +VLOG_OPT += +define+SYNOPSYS_SV +VLOG_OPT += +define+BASE_AFU=dummy_afu+ +VLOG_OPT += +incdir+$(WORKDIR)/ofs-common/src/common/includes +VLOG_OPT += +incdir+$(WORKDIR)/src/includes +VLOG_OPT += +incdir+$(RALDIR) + +SIMV_OPT = +UVM_TESTNAME=$(TESTNAME) +TIMEOUT=$(TIMEOUT) +SIMV_OPT += -l runsim.log + + +ifndef SEED + SIMV_OPT += +ntb_random_seed_automatic +else + SIMV_OPT += +ntb_random_seed=$(SEED) +endif + +ifdef TEST_LPBK + VLOG_OPT += +define+TEST_LPBK +endif + +ifdef REMOVE_HSSI + VLOG_OPT += +define+REMOVE_HSSI +endif + +ifndef MSG + SIMV_OPT += +UVM_VERBOSITY=LOW +else + SIMV_OPT += +UVM_VERBOSITY=$(MSG) +endif + + +ifdef DEBUG +SIMV_OPT += -l runsim.log +VLOG_OPT += +define+RUNSIM +endif + + +ifdef QUIT + SIMV_OPT_EXTRA = +UVM_MAX_QUIT_COUNT=1 +else + SIMV_OPT_EXTRA = "" +endif + + +## The Platform Interface Manager is always available for use by AFUs, +## whether or not a specific AFU requires it. These parameters define +## the platform-dependent PIM instance that will be created below +## during cmplib. +PIM_TEMPLATE_DIR=$(VERDIR)/msim_ip_libraries/pim_template +PIM_PLATFORM_NAME=d5005 +# PIM sources, dynamically generated by ofs_pim_sim_setup.sh below +PIM_FLIST=$(PIM_TEMPLATE_DIR)/pim_source_files.list + +ifdef AFU_WITH_PIM + # Simulating an AFU wrapped by the PIM's ofs_plat_afu() top-level + # module wrapper. + AFU_WITH_PIM_DIR=$(VERDIR)/sim_msim/afu_with_pim + AFU_FLIST=$(AFU_WITH_PIM_DIR)/afu_sim_files.list +else + # Normal simulation with default exerciser AFUs + AFU_FLIST=$(D5005_DIR)/afu_flist.f +endif + +dump: + make DUMP=1 + +clean: + @if [ -d worklib ]; then rm -rf worklib; fi; + @if [ -d libs ]; then rm -rf libs; fi; + @rm -rf simv* csrc *.out* *.OUT *.log *.txt *.h *.setup *.vpd test_lib.svh .vlogansetup.* *.tr *.hex *.xml DVEfiles; + @rm -rf $(VERDIR)/sim_msim $(VERDIR)/msim_ip_libraries $(VERDIR)/vip $(SCRIPTS_DIR)/qip $(SCRIPTS_DIR)/rtl_comb.f $(SCRIPTS_DIR)/rtl_comb_common.f $(SCRIPTS_DIR)/rtl_pcie.f $(SCRIPTS_DIR)/transcript; + +clean_dve: + @if [ -d worklib ]; then rm -rf worklib; fi; + @if [ -d libs ]; then rm -rf libs; fi; + @rm -rf simv* csrc *.out* *.OUT *.log *.txt *.h *.setup *.vpd test_lib.svh .vlogansetup.* *.tr *.hex *.xml; + +setup: clean_dve + @echo WORK \> DEFAULT > synopsys_sim.setup + @echo DEFAULT \: worklib >> synopsys_sim.setup + @mkdir worklib + @echo VIPDIR $(VIPDIR) + @echo \`include \"$(TESTNAME).svh\" > test_lib.svh + test -s $(VERDIR)/sim_msim || mkdir $(VERDIR)/sim_msim + test -s $(VERDIR)/vip || mkdir $(VERDIR)/vip + test -s $(VERDIR)/vip/axi_vip || mkdir $(VERDIR)/vip/axi_vip + test -s $(VERDIR)/vip/pcie_vip || mkdir $(VERDIR)/vip/pcie_vip + rsync -avz --checksum --ignore-times --exclude pim_template ../msim_ip_libraries/* $(VERDIR)/sim_msim/ + @echo '' + @echo VCS_HOME: $(VCS_HOME) + @$(DESIGNWARE_HOME)/bin/dw_vip_setup -path ../vip/axi_vip -add axi_system_env_svt -svlog + @$(DESIGNWARE_HOME)/bin/dw_vip_setup -path ../vip/pcie_vip -add pcie_device_agent_svt -svlog + @echo '' + +cmplib: + "$(OFS_ROOTDIR)"/ofs-common/scripts/common/sim/gen_sim_files.sh d5005 + mkdir -p ../msim_ip_libraries + # Generate the PIM template for the target platform + "$(OFS_ROOTDIR)"/ofs-common/scripts/common/sim/ofs_pim_sim_setup.sh -t "$(PIM_TEMPLATE_DIR)" -b "${PIM_PLATFORM_NAME}" + test -s $(SCRIPTS_DIR)/qip || ln -s $(D5005_DIR)/qip_sim_script qip + cd $(VERDIR)/msim_ip_libraries + vsim -c -do msim_lib.do | tee msim_cmplib.log + perl msim_lib_gen.pl msim_cmplib.log + +vlog: setup +ifdef AFU_WITH_PIM + rm -rf "$(AFU_WITH_PIM_DIR)" + mkdir -p "$(AFU_WITH_PIM_DIR)" + # Construct the simulation build environment for the target AFU + "$(OFS_ROOTDIR)"/ofs-common/scripts/common/sim/ofs_pim_sim_setup.sh -t "$(AFU_WITH_PIM_DIR)" -r "$(PIM_TEMPLATE_DIR)" -b "${PIM_PLATFORM_NAME}" "$(AFU_WITH_PIM)" +endif + test -s $(SCRIPTS_DIR)/rtl_comb.f || ln -s $(D5005_DIR)/rtl_comb.f rtl_comb.f + cd $(VERDIR)/sim_msim && vlog $(VLOG_OPT) -suppress 2388,13364,8303,8386,2892,7061,7033 -64 -mfcu -timescale=1ns/1ns -l msim_vlog.log +libext+.v+.sv -lint -sv +define+QUESTA -f $(D5005_DIR)/msim_ip_flist.f -f $(SCRIPTS_DIR)/rtl_comb.f -F "$(PIM_FLIST)" -F "$(AFU_FLIST)" -f $(SCRIPTS_DIR)/questa_list.f -f $(SCRIPTS_DIR)/msim_ver_list.f + + +vopt: + vopt $(TOP_LEVEL_NAME) -o des $(VLOG_OPT) -suppress 2732,12003,7033,3837,8386,13364,2388,7061,7033,7077,19,8303,12110 -f msim_lib.f -L $(QUESTA_HOME)/uvm-1.2 -work $(VERDIR)/sim_msim/libraries/work -l msim_vopt.log + +build: vlog vopt + +ifeq ($(DUMP),1) +run: + gcc -m64 -fPIC -DQUESTA -g -W -shared -x c -I $(QUESTA_HOME)/include -I $(QUESTA_HOME)/verilog_src/uvm-1.2/src/dpi $(QUESTA_HOME)/verilog_src/uvm-1.2/src/dpi/uvm_dpi.cc -o $(VERDIR)/sim_msim/uvm_dpi.so + + cd $(VERDIR)/sim_msim && mkdir $(TEST_DIR) && cd $(TEST_DIR) && cp -f ../*.hex . && cp -f $(OFS_ROOTDIR)/ofs-common/src/common/fme_id_rom/fme_id.mif . && cp $(QLIB_DIR)/../recalibration.mif . && cp $(SCRIPTS_DIR)/msim_lib.f . && vsim -suppress 2732,12003,7033,3837,8386,13364,2388,7061,7033,7077,19,8303,12110,3197,3748 -64 -nosva des -lib $(VERDIR)/sim_msim/libraries/work -permit_unmatched_virtual_intf +UVM_TESTNAME=$(TESTNAME) -sv_lib $(VERDIR)/sim_msim/uvm_dpi -sv_lib $(VERDIR)/vip/pcie_vip/lib/linux64/libvcap -sv_lib $(VERDIR)/vip/axi_vip/lib/linux64/libvcap -c -l runsim.log -do "add log -r /*; run -all; quit -f"; + +else +run: + gcc -m64 -fPIC -DQUESTA -g -W -shared -x c -I $(QUESTA_HOME)/include -I $(QUESTA_HOME)/verilog_src/uvm-1.2/src/dpi $(QUESTA_HOME)/verilog_src/uvm-1.2/src/dpi/uvm_dpi.cc -o $(VERDIR)/sim_msim/uvm_dpi.so + + cd $(VERDIR)/sim_msim && mkdir $(TEST_DIR) && cd $(TEST_DIR) && cp -f ../*.hex . && cp -f $(OFS_ROOTDIR)/ofs-common/src/common/fme_id_rom/fme_id.mif . && cp $(QLIB_DIR)/../recalibration.mif . && cp $(SCRIPTS_DIR)/msim_lib.f . && vsim -suppress 2732,12003,7033,3837,8386,13364,2388,7061,7033,7077,19,8303,12110,3197,3748 -64 -nosva des -lib $(VERDIR)/sim_msim/libraries/work -permit_unmatched_virtual_intf +UVM_TESTNAME=$(TESTNAME) -sv_lib $(VERDIR)/sim_msim/uvm_dpi -sv_lib $(VERDIR)/vip/pcie_vip/lib/linux64/libvcap -sv_lib $(VERDIR)/vip/axi_vip/lib/linux64/libvcap -c -l runsim.log -do "run -all; quit -f"; +endif diff --git a/verification/scripts/Makefile_VCS.mk b/verification/scripts/Makefile_VCS.mk new file mode 100755 index 0000000..969604c --- /dev/null +++ b/verification/scripts/Makefile_VCS.mk @@ -0,0 +1,208 @@ +# Copyright 2021 Intel Corporation +# SPDX-License-Identifier: MIT + +ifndef WORKDIR + $(error undefined WORKDIR) +endif + +#ifndef UVM_HOME +# $(error undefined UVM_HOME) +#endif + +#ifndef TESTNAME +# $(error undefined TESTNAME) +#endif +VERDIR_COMMON = $(OFS_ROOTDIR)/ofs-common/verification +TEST_DIR := $(shell ./create_dir.pl $(VERDIR)/sim/$(TESTNAME) ) +SCRIPTS_DIR=$(VERDIR)/scripts +# Synthesis scripts directory. Some synthesis scripts also work for setting up +# simulation. +SYN_SCRIPTS_DIR=$(WORKDIR)/scripts/common/syn + +D5005_DIR = $(OFS_ROOTDIR)/sim/scripts + +VCDFILE = $(SCRIPTS_DIR)/vpd_dump.key + +export LIB_DIR = $(SCRIPTS_DIR)/../sim/libraries +#VLOG_OPT = -kdb -full64 -error=noMPD -ntb_opts uvm-1.2 +vcs+initreg+random +vcs+lic+wait -ntb_opts dtm -sverilog -timescale=1ns/1fs +libext+.v+.sv -CFLAGS -debug_pp -l vlog.log -assert enable_diag -ignore unique_checks -debug_all +VLOG_OPT = -kdb -full64 -error=noMPD -ntb_opts uvm-1.2 +vcs+initreg+random +vcs+lic+wait -ntb_opts dtm -sverilog -timescale=1ns/1fs +libext+.v+.sv -l vlog.log -assert enable_diag -ignore unique_checks +VLOG_OPT += -Mdir=./csrc +warn=noBCNACMBP -CFLAGS -y $(VERDIR)/vip/pcie_vip/src/verilog/vcs -y $(VERDIR)/vip/pcie_vip/src/sverilog/vcs -P $(VERDIR)/scripts/vip/pli.tab $(WORKDIR)/scripts/vip/msglog.o -notice -work work +incdir+./ +VLOG_OPT += +define+IGNORE_DF_SIM_EXIT +VLOG_OPT += +define+SIM_MODE +define+SIM_SERIAL +VLOG_OPT += +define+SIMULATION_MODE +VLOG_OPT += +define+UVM_DISABLE_AUTO_ITEM_RECORDING +VLOG_OPT += +define+UVM_PACKER_MAX_BYTES=1500000 +VLOG_OPT += +define+MMIO_TIMEOUT_IN_CYCLES=1024 +VLOG_OPT += +define+SVT_PCIE_ENABLE_GEN3+GEN3 +VLOG_OPT += +define+SVT_UVM_TECHNOLOGY +VLOG_OPT += +define+SYNOPSYS_SV +#ifeq ($(SITE),pdx) +#$else +VLOG_OPT += +define+DESIGNWARE_HOME=$(DESIGNWARE_HOME) +#endif +VLOG_OPT += +define+define+__ALTERA_STD__METASTABLE_SIM +VLOG_OPT += +define+BASE_AFU=dummy_afu+ +VLOG_OPT += +define+SVT_AXI_MAX_TDATA_WIDTH=784 +define+SVT_AXI_MAX_TUSER_WIDTH=44 +VLOG_OPT += +incdir+$(WORKDIR)/ofs-common/src/common/includes +VLOG_OPT += +incdir+$(WORKDIR)/src/includes +#VLOG_OPT += +incdir+$(WORKDIR)/src/fims/d5005/includes + +VCS_OPT = -full64 -ntb_opts uvm-1.2 -licqueue +vcs+lic+wait -l vcs.log + +SIMV_OPT = +UVM_TESTNAME=$(TESTNAME) +TIMEOUT=$(TIMEOUT) +#SIMV_OPT += +UVM_NO_RELNOTES +SIMV_OPT += -l runsim.log +SIMV_OPT += +ntb_disable_cnst_null_object_warning=1 -assert nopostproc +vcs+lic+wait +vcs+initreg+0 +SIMV_OPT += +UVM_PHASE_TRACE +SIMV_OPT += +vcs+lic+wait +ifdef COV + COV_TST := $(shell basename $(TEST_DIR)) + VLOG_OPT += +define+ENABLE_R1_COVERAGE +define+ENABLE_COV_MSG +define+COV -cm line+cond+fsm+tgl+branch+assert -cm_dir simv.vdb + VCS_OPT += -cm line+cond+fsm+tgl+branch+assert -cm_dir simv.vdb + SIMV_OPT += -coverage -cm line+cond+fsm+tgl+branch+assert+group -cm_name $(COV_TST) -cm_dir ../regression.vdb + #SIMV_OPT += -cm line+cond+fsm+tgl+branch -cm_name seed.1 -cm_dir regression.vdb +endif + + + +#SIMV_OPT += +vcs+lic+wait -ucli + +ifndef SEED + SIMV_OPT += +ntb_random_seed_automatic +else + SIMV_OPT += +ntb_random_seed=$(SEED) +endif + +#Suppress unique/priority case/if warnings +#ifdef NORT_WARN + VCS_OPT += -ignore all +#endif + +ifndef MSG + SIMV_OPT += +UVM_VERBOSITY=LOW +else + SIMV_OPT += +UVM_VERBOSITY=$(MSG) +endif + +ifdef DUMP + VLOG_OPT += -debug_all + VCS_OPT += -debug_all + SIMV_OPT += -ucli -i $(VCDFILE) +endif + +ifdef GUI + VCS_OPT += -debug_all +memcbk + SIMV_OPT += -gui +endif + +ifdef QUIT + SIMV_OPT_EXTRA = +UVM_MAX_QUIT_COUNT=1 +else + SIMV_OPT_EXTRA = "" +endif + +## The Platform Interface Manager is always available for use by AFUs, +## whether or not a specific AFU requires it. These parameters define +## the platform-dependent PIM instance that will be created below +## during cmplib. +PIM_TEMPLATE_DIR=$(VERDIR)/ip_libraries/pim_template +PIM_PLATFORM_NAME=d5005 +PIM_INI_FILE=$(WORKDIR)/src/fims/d5005/ofs_d5005.ini +# PIM sources, dynamically generated by ofs_pim_sim_setup.sh below +PIM_FLIST=$(PIM_TEMPLATE_DIR)/pim_source_files.list + +ifdef AFU_WITH_PIM + # Simulating an AFU wrapped by the PIM's ofs_plat_afu() top-level + # module wrapper. + AFU_WITH_PIM_DIR=$(VERDIR)/sim/afu_with_pim + AFU_FLIST=$(AFU_WITH_PIM_DIR)/afu_sim_files.list +else + # Normal simulation with default exerciser AFUs + AFU_FLIST=$(D5005_DIR)/afu_flist.f +endif + +batch: vcs + ./simv $(SIMV_OPT) $(SIMV_OPT_EXTRA) + +dump: + make DUMP=1 + +clean: + @if [ -d worklib ]; then rm -rf worklib; fi; + @if [ -d libs ]; then rm -rf libs; fi; + @rm -rf simv* csrc *.out* *.OUT *.log *.txt *.h *.setup *.vpd test_lib.svh .vlogansetup.* *.tr *.ver *.hex *.xml *.mif DVEfiles; + #@rm -rf $(VERDIR)/sim $(VERDIR)/ip_libraries $(VERDIR)/vip $(VERDIR)/scripts/qip $(VERDIR)/scripts/rtl_comb.f $(VERDIR)/scripts/rtl_comb_common.f $(VERDIR)/scripts/rtl_pcie.f $(VERDIR)/scripts/ip_list.f $(VERDIR)/scripts/ip_flist.f; + @rm -rf $(VERDIR)/sim $(VERDIR)/ip_libraries $(VERDIR)/vip $(VERDIR)/scripts/qip +clean_dve: + @if [ -d worklib ]; then rm -rf worklib; fi; + @if [ -d libs ]; then rm -rf libs; fi; + @rm -rf simv* csrc *.out* *.OUT *.log *.txt *.h *.setup *.vpd test_lib.svh .vlogansetup.* *.tr *.ver *.hex *.xml *.mif; + +setup: clean_dve + @echo WORK \> DEFAULT > synopsys_sim.setup + @echo DEFAULT \: worklib >> synopsys_sim.setup + @mkdir worklib + @echo \`include \"$(TESTNAME).svh\" > test_lib.svh + test -s $(VERDIR)/sim || mkdir $(VERDIR)/sim + test -s $(VERDIR)/vip || mkdir $(VERDIR)/vip + test -s $(VERDIR)/vip/axi_vip || mkdir $(VERDIR)/vip/axi_vip + test -s $(VERDIR)/vip/pcie_vip || mkdir $(VERDIR)/vip/pcie_vip + rsync -avz --checksum --ignore-times --exclude pim_template ../ip_libraries/* $(VERDIR)/sim/ + @echo '' + @echo VCS_HOME: $(VCS_HOME) + @$(DESIGNWARE_HOME)/bin/dw_vip_setup -path ../vip/axi_vip -add axi_system_env_svt -svlog + @$(DESIGNWARE_HOME)/bin/dw_vip_setup -path ../vip/pcie_vip -add pcie_device_agent_svt -svlog + @echo '' + +cmplib: + "$(OFS_ROOTDIR)"/ofs-common/scripts/common/sim/gen_sim_files.sh d5005 + mkdir -p ../ip_libraries + # Generate the PIM template for the target platform + "$(OFS_ROOTDIR)"/ofs-common/scripts/common/sim/ofs_pim_sim_setup.sh -t "$(PIM_TEMPLATE_DIR)" -b "${PIM_PLATFORM_NAME}" + test -s $(SCRIPTS_DIR)/qip || ln -s $(D5005_DIR)/qip_sim_script qip + cp -f qip/synopsys/vcsmx/synopsys_sim.setup ../ip_libraries/ + cd ../ip_libraries && ../scripts/qip/synopsys/vcsmx/vcsmx_setup.sh SKIP_SIM=1 QSYS_SIMDIR=../scripts/qip QUARTUS_INSTALL_DIR=$(QUARTUS_HOME) USER_DEFINED_COMPILE_OPTIONS="+define+__ALTERA_STD__METASTABLE_SIM" + +## When AFU_WITH_PIM= is set, construct a PIM environment and +## configure the AFU sources specified in filelist.txt using OPAE's +## afu_sim_setup. The AFU will be compiled into the simulation instead of +## the default device exercisers. +$(AFU_FLIST): +ifdef AFU_WITH_PIM + rm -rf "$(AFU_WITH_PIM_DIR)" + mkdir -p "$(AFU_WITH_PIM_DIR)" + # Construct the simulation build environment for the target AFU + "$(OFS_ROOTDIR)"/ofs-common/scripts/common/sim/ofs_pim_sim_setup.sh -t "$(AFU_WITH_PIM_DIR)" -r "$(PIM_TEMPLATE_DIR)" -b "${PIM_PLATFORM_NAME}" "$(AFU_WITH_PIM)" +endif + +vlog: setup $(AFU_FLIST) + test -s $(SCRIPTS_DIR)/rtl_comb.f || ln -s $(D5005_DIR)/rtl_comb.f rtl_comb.f + cd $(VERDIR)/sim && vlogan -ntb_opts uvm-1.2 -sverilog + cd $(VERDIR)/sim && vlogan -full64 -ntb_opts uvm-1.2 -sverilog -timescale=1ns/1ns -l vlog_uvm.log + cd $(VERDIR)/sim && vlogan $(VLOG_OPT) -f $(OFS_ROOTDIR)/sim/scripts/ip_flist.f -f $(SCRIPTS_DIR)/rtl_comb.f -F "$(PIM_FLIST)" -F "$(AFU_FLIST)" -f $(SCRIPTS_DIR)/ver_list.f + +build: vcs + +vcs: vlog + cd $(VERDIR)/sim && vcs $(VCS_OPT) tb_top + +view: + dve -full64 -vpd inter.vpd& +run: +ifndef TEST_DIR + $(error undefined TESTNAME) +else + cd $(VERDIR)/sim && mkdir $(TEST_DIR) && cd $(TEST_DIR) && cp ../*.hex . && cp $(OFS_ROOTDIR)/ofs-common/src/common/fme_id_rom/fme_id.mif . && cp $(LIB_DIR)/../recalibration.mif . && ../simv $(SIMV_OPT) $(SIMV_OPT_EXTRA); +endif +rundb: +ifndef TESTNAME + $(error undefined TESTNAME) +else + cd $(VERDIR)/sim && ./simv $(SIMV_OPT) $(SIMV_OPT_EXTRA) +endif + +build_run: vcs run +build_all: cmplib vcs +do_it_all: cmplib vcs run + + diff --git a/verification/scripts/aldec/rivierapro_setup.tcl b/verification/scripts/aldec/rivierapro_setup.tcl new file mode 100644 index 0000000..d614a8a --- /dev/null +++ b/verification/scripts/aldec/rivierapro_setup.tcl @@ -0,0 +1,381 @@ +# Copyright (C) 2001-2021 Intel Corporation +# SPDX-License-Identifier: MIT + +# ACDS 21.1 169 linux 2021.09.22.02:17:27 +# ---------------------------------------- +# Auto-generated simulation script rivierapro_setup.tcl +# ---------------------------------------- +# This script provides commands to simulate the following IP detected in +# your Quartus project: +# config_reset_release.config_reset_release +# cfg_mon.cfg_mon +# sys_pll.sys_pll +# avst_pipeline_st_pipeline_stage_0.avst_pipeline_st_pipeline_stage_0 +# avst_pipeline_st_pipeline_stage_1.avst_pipeline_st_pipeline_stage_1 +# PR_IP.PR_IP +# qph_user_clk_iopll_s10_RF100M.qph_user_clk_iopll_s10_RF100M +# qph_user_clk_iopll_reconfig.qph_user_clk_iopll_reconfig +# remote_debug_jtag_only_clock_in.remote_debug_jtag_only_clock_in +# host_if.host_if +# jop_blaster.jop_blaster +# remote_debug_jtag_only_reset_in.remote_debug_jtag_only_reset_in +# sys_clk.sys_clk +# pcie_ep_g3x16.pcie_ep_g3x16 +# address_decode_clk_csr.address_decode_clk_csr +# address_decode_master_0.address_decode_master_0 +# address_decode_merlin_master_translator_0.address_decode_merlin_master_translator_0 +# address_decode_mm_to_mac.address_decode_mm_to_mac +# address_decode_mm_to_phy.address_decode_mm_to_phy +# address_decode_rx_xcvr_clk.address_decode_rx_xcvr_clk +# address_decode_tx_xcvr_clk.address_decode_tx_xcvr_clk +# address_decode_tx_xcvr_half_clk.address_decode_tx_xcvr_half_clk +# altera_eth_10g_mac.altera_eth_10g_mac +# altera_eth_10gbaser_phy.altera_eth_10gbaser_phy +# altera_xcvr_atx_pll_ip.altera_xcvr_atx_pll_ip +# pll.pll +# reset_control.reset_control +# spi_bridge_reset_in.spi_bridge_reset_in +# spi_bridge_spi_0.spi_bridge_spi_0 +# spi_bridge_clock_in.spi_bridge_clock_in +# fme_id_rom.fme_id_rom +# apf_clock_bridge.apf_clock_bridge +# apf_reset_bridge.apf_reset_bridge +# apf_bpf_mst.apf_bpf_mst +# apf_bpf_slv.apf_bpf_slv +# apf_st2mm_mst.apf_st2mm_mst +# apf_st2mm_slv.apf_st2mm_slv +# apf_pgsk_slv.apf_pgsk_slv +# apf_achk_slv.apf_achk_slv +# apf_rsv_b_slv.apf_rsv_b_slv +# apf_rsv_c_slv.apf_rsv_c_slv +# apf_rsv_d_slv.apf_rsv_d_slv +# apf_rsv_e_slv.apf_rsv_e_slv +# apf_rsv_f_slv.apf_rsv_f_slv +# bpf_clock_bridge.bpf_clock_bridge +# bpf_reset_bridge.bpf_reset_bridge +# bpf_apf_mst.bpf_apf_mst +# bpf_apf_slv.bpf_apf_slv +# bpf_fme_mst.bpf_fme_mst +# bpf_fme_slv.bpf_fme_slv +# bpf_pmci_slv.bpf_pmci_slv +# bpf_pcie_slv.bpf_pcie_slv +# bpf_emif_slv.bpf_emif_slv +# bpf_hssi_slv.bpf_hssi_slv +# bpf_rsv_5_slv.bpf_rsv_5_slv +# bpf_rsv_6_slv.bpf_rsv_6_slv +# bpf_rsv_7_slv.bpf_rsv_7_slv +# emif_ddr4_no_ecc.emif_ddr4_no_ecc +# avmm_cdc.avmm_cdc +# avmm_pipeline_bridge.avmm_pipeline_bridge +# remote_debug_jtag_only.remote_debug_jtag_only +# address_decode.address_decode +# spi_bridge.spi_bridge +# apf.apf +# bpf.bpf +# +# Intel recommends that you source this Quartus-generated IP simulation +# script from your own customized top-level script, and avoid editing this +# generated script. +# +# To write a top-level script that compiles Intel simulation libraries and +# the Quartus-generated IP in your project, along with your design and +# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below +# into a new file, e.g. named "aldec.do", and modify the text as directed. +# +# ---------------------------------------- +# # TOP-LEVEL TEMPLATE - BEGIN +# # +# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to +# # construct paths to the files required to simulate the IP in your Quartus +# # project. By default, the IP script assumes that you are launching the +# # simulator from the IP script location. If launching from another +# # location, set QSYS_SIMDIR to the output directory you specified when you +# # generated the IP script, relative to the directory from which you launch +# # the simulator. +# # +# set QSYS_SIMDIR