This is one of my bachelor degree projects. In my university there are three projects that contribute to my final score (up to 6 points).
This one in particular is the final project from the course "Reti Logiche" so the project is about logical networks and VHDL programming.
If you want to try it yourself, I leave the rules and the specification files.
To get perfect score you need to run successfully all simulations inside Simulation.
If you have contributions, need support, have suggestions, or just want to get in touch with the me, send me an email!
This software is licensed under the terms of the MIT license. See LICENSE for more details.