High Level Overview
OpenSoC Fabric is an on-chip network generator designed be hierarchical, modular, and high parameterizable. It aims to provide a complete and powerful on-chip network generator with the end goal of using it to design a complete an open-source System-on-Chip (SoC). OpenSoC Fabric consists of a hierarchy of modules, using Scala's object-oriented constructs. Each module (e.g., router) has an abstract definition which includes all the input and output ports as well as functionality common to all child classes. Child modules then define specific attributed and functionality. In addition, the interface between modules is standardized. This way, users wishing to extend or replace modules may easily do so by using principles of object-oriented programming. Each module also takes a list of parameters at the time of instantiation to set values to internal variables. An overview of the hierarchy of classes is shown in hierachy tree diagram below. The block diagram below shows the modules that that flits traverse from the time they enter the network until they exit.
| OpenSoC Fabric Hierarchy | OpenSoC Fabric Block Diagram |
|---|---|
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OpenSoC Fabric implements state-of-the-art wormhole flow control using pipelined input-queued routers with and without virtual channels (VCs), and separable allocators with round-robin arbiters. In addition, a mesh and a flattened butterfly topologies are provided that support concentration, each with dimension-order routing (DOR). While we have plans to extend the functionality of this infrastructure, we rely on the contributions of users to make this tool more comprehensive. OpenSoC Fabric also includes a test harness (testbench) which generates and injects packets, and also ejects packets from the network. The test harness also defines whether compiling OpenSoC Fabric using Chisel will generate C++ or Verilog, as shown in the figure below.
This manual is organized as follows:
- Using and Compiling OpenSoC Fabric explains how to compile and use this infrastructure, including an overview of the test harness with emphasis on statistics and traffic patterns.
- User Parameters explains each parameter passed from the top-level module below the hierarchy.
- Architecture outlines the functionality, input and output interface, as well as the structure of each module.
- Interoperability and Future Plans provides a brief overview of our immediate plans, especially as they relate standardized interfaces to provide to interoperability with other IP blocks in the context of designing a complete SoC.