Future Plans

Future Plans

The current version of OpenSoC Fabric includes essential functionality to implement a state-of-the-art on-chip network with VCs. Our plans for future work include features that would either help usability or extend functionality. We are certainly open to suggestions from users. However, being a community-driven tool, OpenSoC Fabric depends on the contributions of users to grow into a more feature-complete package.

• Torus topology: While there are a number of topologies (including fat trees) that we think should be included, our next pick is a torus topology, both folded and unfolded. This class will also implement ring topologies, because they are a special case of a torus. Implementing topologies that are non-traditional for on-chip networks will help OpenSoC Fabric to move one level higher in network hierarchy to apply OpenSoC Fabric to model internode communication as well as on-chip optical networks. This will help broaden the design-space exploration for future high performance computing.

• Multiple Arbitration Schemes: We currently only support the round robin arbitration scheme. In order to extensive design space exploration, different arbitration schemes are required.

• Define traffic classes at network endpoints: Currently injection and ejection queues do not use VCs or any other separation at network boundaries. VCs are only used inside the network for performance improvements and to avoid network deadlocks. However, we intend to divide the injection and ejection queues at every endpoint to one per traffic class (one traffic class may be assigned to multiple VCs) such as to avoid protocol deadlocks.

• Validation: We plan to validate OpenSoc Fabric against existing validated software models (like BookSim) or independently produced RTL (like Open Source Network-on-Chip Router RTL). We also plan to verify the functionality of the software models Chisel produces against the RTL.

• Debugging and visualization: We also would like to create a suite of tools to more easily debug designs, visualize the network, and produce power and area estimations in the software models.

• Endpoint connectivity: As previously stated, we are currently planning to implement the AXI4-Lite interface at the network endpoints. As the list of features and use cases grows, we can extend the list of interfaces to include either custom or more powerful standardized interfaces. In addition, some of these interfaces may include coherency support.

• More traffic patterns and tracing support: We plan to define more synthetic traffic patterns in the test hardness, as well as the ability to read traffic from an input file such as to replay communication traces collected through other means.