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This wiki explains the use and the internal architecture of the OpenSoC Fabric on-chip network generator, a parameterizable and powerful on-chip network generator for evaluating future large-scape chip multiprocessors and SoCs. OpenSoC Fabric leverages a new hardware DSL, Chisel, which contains powerful abstractions provided by its base language, Scala, and generates both software (C++) and hardware (Verilog) models from a single code base. The OpenSoC Fabric infrastructure is modeled after existing state-of-the-art simulators, offers large and powerful collections of configuration options, and is open-source with object-oriented design and functional programming to make functionality extension as easy as possible. This manual does not provide a tutorial on Chisel, which is left to online resources dedicated to this purpose. OpenSoC Fabric is released open-source under a Modified BSD license, to allow anyone to edit the code and contribute back. Being an open-source project, OpenSoC Fabric relies on collaborative effort. For more information, please refer to our website.
Farzad Fatollahi-Fard, David Donofrio, George Michelogiannakis, John Shalf Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, California 94720 Contact : http://opensocfabric.org/contact.php
"OpenSoC Fabric, Copyright (c) 2014, The Regents of the University of California, through Lawrence Berkeley National Laboratory (subject to receipt of any required approvals from the U.S. Dept. of Energy). All rights reserved."
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OpenSoC Fabric, Copyright (c) 2014, The Regents of the University of California, through Lawrence Berkeley National Laboratory (subject to receipt of any required approvals from the U.S. Dept. of Energy). All rights reserved.
If you have questions about your rights to use or distribute this software, please contact Berkeley Lab's Technology Transfer Department at TTD@lbl.gov.
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