👋 Hello, I'm Joyen Benitto
I’m a SoC Design Engineer at InCore Semiconductors, working on a core-agnostic SoC generator—both the methodology and the tooling that enables it. My focus is on hardware design automation, building scalable methodologies that streamline SoC development.
My interests lie at the intersection of RTL design, CAD tools, and architecture exploration. I work primarily with Bluespec, SystemVerilog, Python, C++ and C, but I also enjoy using Rust when the problem demands it.
I believe that hardware should be as composable as software, and I’m always exploring ways to make that a reality. If you're working on similar ideas—or just curious—feel free to reach out, contribute, or report issues in any of my repositories.