portfolio.html

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title: Projects & Portfolio
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<a href="https://johnnygox17.github.io/rfproto/" class="project-href">
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  <img src="https://upload.wikimedia.org/wikipedia/commons/thumb/c/c3/Python-logo-notext.svg/1869px-Python-logo-notext.svg.png" alt="Python logo" style="width:10%">
  <h2><code>rfproto</code> Python Library</h2>
  <p><code>rfproto</code> is a Python library for RF and SDR prototyping. It contains helpful reuse methods for RF measurements, as well as experimenting with topics like communication systems, radar, antenna arrays, etc.</p>
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<a href="https://jscholarship.library.jhu.edu/handle/1774.2/64205" class="project-href">
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  <img src="/assets/images/phased_array.png" alt="Phased Array">
  <h2>FPGA-Based ADBF Using ML for MIMO Systems</h2>
  <p>This Masters Thesis research shows the development of a novel Deep Learning model (CNN), trained to perform Adaptive Digital Beamforming. The model was shown to vastly outperform the current state-of-the-art Adaptive Digital Beamforming FPGA implementation, with a 10x decrease in latency and a 10x decrease in programmable logic resource utilization.</p>
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<a href="https://github.com/JohnnyGOX17/4ch-RF-FE" class="project-href">
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  <img src="/assets/images/4ch_RF_FE_KiCad.png" alt="P2P-GPU">
  <h2>4-Channel RF Diplexer Front End</h2>
  <p>An open-source (KiCAD) RF front end with 4 independent RX & TX channels optimized for MIMO/Radar prototyping. It implements an I2C bus for digital control of each channel’s attenuation and single-ended control of T/R switch for fast action. A switch-mode power supply and separate low dropout regulators for each channel are utilized to provide low-ripple power to RF Low Noise Amplifiers.</p>
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<a href="https://forums.ni.com/t5/NI-Labs-Toolkits/FlexRIO-Peer-to-Peer-GPU/ta-p/3660064" class="project-href">
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  <img src="/assets/images/NI_FPGA_P2P_GPU.png" alt="P2P-GPU">
  <h2>FlexRIO Peer-to-Peer GPU</h2>
  <p>NI FlexRIO driver and example CUDA/C++/FPGA code for implementing peer-to-peer (P2P) data streams between a National Instruments FlexRIO device and a NVIDIA GPU using a zero-copy, bidirectional, DMA communication path via GPUDirect kernel driver.</p>
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<a href="https://forums.ni.com/t5/NI-Labs-Toolkits/Remote-FPGA-Debugging-with-ChipScope-XVC-and-LabVIEW/ta-p/3546726" class="project-href">
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  <img src="/assets/images/xvc_ila.png" alt="XVC">
  <h2>Remote Debug with XVC</h2>
  <p>Whitepaper and VHDL example code on how to incorporate Integrated Logic Analyzers (ILA) into a design and perform remote JTAG debugging using the Xilinx Virtual Cable (XVC) protocol on a LabVIEW TCP/IP server that is bus-connected to the FPGA to access JTAG as memory-mapped registers.</p>
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<a href="https://forums.ni.com/t5/Examples-and-IP-for-Software/High-Speed-Serial-Streaming-to-Disk/ta-p/3668207" class="project-href">
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  <img src="/assets/images/ni_datarecorder.jpeg" alt="data-recorder">
  <h2>High-Speed Stream-to-Disk</h2>
  <p>This LabVIEW and FPGA example shows best practices for efficient streaming data to disk/RAID with the lowest overhead and highest data rates over PCIe.</p>
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