This code example shows how to configure the SMPU (Shared Memory Protection Unit) and describes its operation and initial settings.
The device used in this code example (CE) is:
The board used for testing is:
- TRAVEO™ T2G Cluster 6M Lite Kit (KIT_T2G_C-2D-6M_LITE)
In this example, the SMPU is used for protection. If access violation is detected, a fault is generated.
Protection Unit
- An address range that is accessed by the transfer
- Subregion: An address range is partitioned into eight equally-sized subregions and subregion can individual disables
- Access attributes such as:
- Read/write attribute
- Execute attribute to distinguish a code access from a data access
- User/privilege attribute to distinguish access; for example, OS/kernel access from a task/thread access
- Secure/non-secure attribute to distinguish a secure access from a non-secure access; the Arm Cortex-M CPUs do not natively support this attribute
- A protection context attribute to distinguish accesses from different protection contexts; for Peripheral-DMA (P-DMA) and Memory-DMA (M-DMA), this attribute is extended with a channel identifier, to distinguish accesses from different channels
- Memory protection
- Provided by memory protection units (MPUs) and shared memory protection units (SMPUs)
- MPUs distinguish user and privileged accesses from a single bus master
- SMPUs distinguish between different protection contexts and between secure and non-secure accesses
- Peripheral protection
- Provided by peripheral protection units (PPUs)
- The PPUs distinguish between different protection contexts; they also distinguish secure from non-secure accesses and user mode accesses from privileged mode accesses
- Protection pair structure
- Software Protection Unit (SWPU): SWPUs define flash write (or erase) permissions, and eFuse read and write permissions. An SWPU comprises of the following:
- Flash Write Protection Unit (FWPU)
- eFuse Read Protection Unit (ERPU)
- eFuse Write Protection Unit (EWPU)
More details can be found in:
- TRAVEO™ T2G CYT4DN
This CE has been developed for:
- TRAVEO™ T2G Cluster 6M Lite Kit (KIT_T2G_C-2D-6M_LITE)
Figure 1. KIT_T2G_C-2D-6M_LITE (Top View)
No changes are required from the board's default settings.
This design consists of a shared memory region for processor communication and uses the CM0+, the CM7_0 and the CM7_1 core. The PPU and UART communication is configured in the CM0+ core. Access to the SMPU protected memory region is done using the CM7_0 and CM7_1 core. CM7_0 can read the value of the shared memory region 1, CM7_1 can read the value of the shared memory region 2. Every other access will cause the system to generate a fault, which requires a reset to recover from.
STDIN / STDOUT setting
Initialization of the GPIO for UART is done in the cy_retarget_io_init() function.
- Initialize the pin specified by CYBSP_DEBUG_UART_TX as UART TX, the pin specified by CYBSP_DEBUG_UART_RX as UART RX (these pins are connected to KitProg3 COM port)
- The serial port parameters are set to 8N1 and 115200 baud
Cy_SCB_UART_Get() returns the user input from the terminal as received data.
Shared memory region
A shared SRAM memory region is defined in the linker file (linker.ld) of both core types. The region has the same address for all cores, which makes content stored in it accessible by these cores. The region is specified to be an address range of 0x100 and is dynamically placed after the private memory placeholder by using variables. In this example, the shared memory is evaluated to be at address 0x28000800.
Bus master configuration
In this example, two different protection context (PC) are used:
- PC5: Read and write access is not allowed for user and privileged
- PC6: Read and write access is allowed for user and privileged
CM7_0 is configured to be in protection context 6 and CM7_1 is configured to be in protection content 5. Bus masters are configured, using the Cy_Prot_ConfigBusMaster() and Cy_Prot_SetActivePC() function.
Memory protection
Two different memory addresses (TEST0_ADDR and TEST1_ADDR) are protected by receiving and configuring a SMPU structure. This is done by first receiving a free SMPU structure using Cy_Prot_GetSmpuStruct(), followed by disabling and configuring this structure using Cy_Prot_DisableSmpuSlaveStruct() and Cy_Prot_ConfigSmpuSlaveStruct(). To make the protection available, the corresponding SMPU structure needs to be enabled again, using Cy_Prot_EnableSmpuSlaveStruct().
Enabling CM7s
After that, CM0+ enable both CM7_0/1 cores, using the Cy_SysEnableCM7() function.
Core communication
To allow communication between different cores, a variable is defined and periodically checked by all cores. Depending on an ENUM value, placed by CM0+ and based on user input, the CM7_0 and CM7_1 core act and try to return the content from the specified memory address by using the shared memory.
Detection of access violation
A bus master access to a memory address protected by the SMPU, will be evaluated by the bus master's protection context. If the PC matches the requested access, it will be allowed, if not, the SMPU prevents the access and raises a pending fault. Pending faults are checked by the CM0+ core by calling Cy_SysFault_GetPendingFault() and prohibit further functioning of this example.
For this example, a terminal emulator is required to display outputs and receive keys pressed. You can install a terminal emulator if you do not have one. In this example, Tera Term was used as the terminal emulator.
After code compilation, perform the following steps to flashing the device:
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Connect the board to your PC using the provided USB cable through the KitProg3 USB connector.
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Open a terminal program and select the KitProg3 COM port. Set the serial port parameters to 8N1 and 115200 baud.
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Program the board using one of the following:
- Select the code example project in the Project Explorer.
- In the Quick Panel, scroll down, and click [Project Name] Program (KitProg3_MiniProg4).
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After programming, the code example starts automatically. Confirm that the messages are displayed on the UART terminal.
- Terminal output on program startup
- Terminal output on program startup
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When
1and4is pressed, the cores try a memory read, which is allowed.- Terminal output of cores when reading is allowed
- Terminal output of cores when reading is allowed
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When
2is pressed, CM7_0 tries to read an address without proper rights.- Terminal output after CM7_0 tries to read a protected address
- Terminal output after CM7_0 tries to read a protected address
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When
3is pressed, CM7_1 tries to read an address without proper rights.- Terminal output after CM7_1 tries to read a protected address
- Terminal output after CM7_1 tries to read a protected address
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You can debug the example to step through the code. In the IDE, use the [Project Name] Debug (KitProg3_MiniProg4) configuration in the Quick Panel. For details, see the "Program and debug" section in the Eclipse IDE for ModusToolbox™ software user guide.
Note: (Only while debugging) On the CM7 CPU, some code in main() may execute before the debugger halts at the beginning of main(). This means that some code executes twice: once before the debugger stops execution, and again after the debugger resets the program counter to the beginning of main(). See KBA231071 to learn about this and for the workaround.
Relevant Application notes are:
- AN235305 - Getting started with TRAVEO™ T2G family MCUs in ModusToolbox™
- AN219843 - Protection configuration in TRAVEO™ T2G MCU
ModusToolbox™ is available online:
Associated TRAVEO™ T2G MCUs can be found on:
More code examples can be found on the GIT repository:
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