RAM Retention in DeepSleep Power Mode

This code example demonstrates how to set RAM into Retention mode before entering DeepSleep power mode.

Device

The device used in this code example (CE) is:

• TRAVEO™ T2G CYT4DN Series

Board

The board used for testing is:

• TRAVEO™ T2G Cluster 6M Lite Kit (KIT_T2G_C-2D-6M_LITE)

Scope of work

TRAVEO™ T2G MCUs provides the Static RAM (SRAM) Retention function in DeepSleep mode. This code example writes known data into SRAM Controller 1 and sets the SRAM into Retention mode before entering DeepSleep mode. After wakeup from DeepSleep mode, data written to SRAM Controller 1 is read back and compared to the data written before entering DeepSleep mode to check if the data is retained.

Introduction

SRAM Interface

• Optional memory size: 640 KB
• Advanced eXtensible Interface (AXI) bus interfaces:
  • In the fast clock domain for the CM7 CPUs
• Advanced High-performance Bus (AHB)-Lite bus interface:
  • In the slow clock domain for all bus masters (CM0+ CPU, Crypto, P-DMA, M-DMA, debug interface, and optional external bus master). The slow bus infrastructure combines the bus masters in the slow clock domain.
• Programmable wait states.
• Error Correction Code (ECC) function
  • Single-bit error correction and double-bit error detection (SECDED)
  • ECC error injection
• RAM retention function
• RAM power-up delay control
  • Setting the power stabilization wait after switching on the SRAM power domain.

Device Power Modes

The TVII-C device can operate in different power modes that are intended to minimize the average power consumption in an application. The power modes supported by TVII-C in the order of decreasing power consumption are:

Power Mode	Description	Entry Condition	Wakeup Source	Wakeup Action
Active	Primary mode of operation; all peripherals are available (programmable).	Wakeup from Sleep/DeepSleep modes, Hibernate reset, or any other reset.	Not applicable	Not applicable
Low-Power Active Profile	A low-power profile of Active mode; most peripherals are available with limited capabilities	Register write from Active mode and wakeup from LPSLEEP/DeepSleep modes.	Not applicable	Not applicable
Sleep	CPU is in Sleep mode; all other peripherals are available.	Register write from Active mode or wakeup from DeepSleep through debugger	Any interrupt to CPU	Interrupt
Low-Power Sleep Profile	A low-power profile of Sleep mode; CPU is in Sleep mode; most peripherals are available with limited capabilities.	Register write from LPACTIVE mode.	Any interrupt to CPU	Interrupt
DeepSleep	All high-frequency clocks and peripherals are turned off. Low-frequency clock (ILO) and low-power analog and digital peripherals are available for operation and as wakeup sources. SRAM can be retained (configurable).	Register write from Active or LPACTIVE modes.	GPIO interrupt, event generators, SCB, watchdog timer, and RTC alarms and debugger	Interrupt or Debug
Hibernate	GPIO states are frozen; all high-frequency clocks and peripherals are switched off. Low-frequency clocks (32 kHz), WCO, or LPECO can function. Device resets on wakeup event.	Register write from Active or LPACTIVE modes.	WAKEUP pins, RTC alarm, and watchdog timer	Hibernate Reset

More details can be found in:

• TRAVEO™ T2G CYT4DN
  • Technical Reference Manual (TRM)
  • Registers TRM
  • Data Sheet

Hardware setup

This CE has been developed for:

• TRAVEO™ T2G Cluster 6M Lite Kit (KIT_T2G_C-2D-6M_LITE)
  

Figure 1. KIT_T2G_C-2D-6M_LITE (Top View)

No changes are required from the board's default settings.

Implementation

This multi-core application has the main function running on the CM7_0 core.

• Power state machine
  
  

Setting up RTC as wakeup source

This example uses RTC (Real Time Clock) as a wakeup source from DeepSleep mode. The RTC is configured and controlled by HAL (Hardware Abstraction Layer) functions.

• After initializing the RTC by Cy_RTC_SelectClockSource(), Cy_RTC_Init() sets the current time and date
• Cy_RTC_SetInterruptMask() enables RTC events that generate RTC interrupts at the specified timing
• In SetRtcAlarmDateTime() function, Cy_RTC_SetAlarmDateAndTime() sets the alarm event occurrence after 10 seconds

SRAM configuration and transition to DeepSleep mode

• After in system initialization is completed, known data is written to SRAM_CONTROLLER1 memory location (0x28040000 to 0x2807FFFF). In main function, Retention mode is enabled before entering DeepSleep mode, and after wakeup from DeepSleep mode via RTC Interrupt (every 10 second interrupt is triggered), SRAM is put in enabled mode. These operations can be done by setting CPUSS_RAM1_PWR_CTL_PWR_MODE field.
• The transition to DeepSleep mode is made by a call to Cy_SysPm_CpuEnterDeepSleep(), a HAL function, which manages whether the current MCU state meets the conditions for transition to DeepSleep. In this example, the TX FIFO of the UART used for string output to the terminal should be empty, so Cy_SysLib_Delay() is used to wait until it becomes empty.
• After wakeup, the data written in SRAM_CONTROLLER1 memory location is read back to check if data is retained or not. Result is then printed on the terminal and the loop starts again.

Miscellaneous settings

• STDIN / STDOUT setting

  • Calling cy_retarget_io_init() function to use UART as STDIN / STDOUT
    • Initialize the port defined as CYBSP_DEBUG_UART_TX as UART TX, defined as CYBSP_DEBUG_UART_RX as UART RX (these pins are connected to KitProg3 COM port)
    • The serial port parameters become to 8N1 and 115200 baud
  • In PrintDebugString() function, the current time obtained by Cy_RTC_GetDateAndTime() is output to the terminal along with a debug string

Cores other than CM7_0

Since all cores must transition to DeepSleep for the entire system becomes DeepSleep mode, cores other than CM7_0 are provided as projects to explicitly transition to DeepSleep.

Run and Test

For this CE, a terminal emulator is required for displaying outputs. Install a terminal emulator if you do not have one. Instructions in this document use Tera Term.

After code compilation, perform the following steps to flashing the device:

1. Connect the board to your PC using the provided USB cable through the KitProg3 USB connector.

2. Open a terminal program and select the KitProg3 COM port. Set the serial port parameters to 8N1 and 115200 baud.

3. Program the board using one of the following:

   • Select the CE project in the Project Explorer.
   • In the Quick Panel, scroll down, and click [Project Name] Program (KitProg3_MiniProg4).

4. After programming, the CE starts automatically. Confirm that the messages are displayed on the UART terminal.

   • Terminal output on program startup
     

5. You can debug the example to step through the code. In the IDE, use the [Project Name] Debug (KitProg3_MiniProg4) configuration in the Quick Panel. For details, see the "Program and debug" section in the Eclipse IDE for ModusToolbox™ software user guide.

Note: (Only while debugging) On the CM7 CPU, some code in main() may execute before the debugger halts at the beginning of main(). This means that some code executes twice: once before the debugger stops execution, and again after the debugger resets the program counter to the beginning of main(). See KBA231071 to learn about this and for the workaround.

References

Relevant Application notes are:

• AN235305 - Getting started with TRAVEO™ T2G family MCUs in ModusToolbox™
• AN220222 - Low Power Mode Procedure in TRAVEO™ T2G Family
• AN220152 - How to Retain RAM Data in Reset Procedure and Low-Power Mode Transition in TRAVEO™ T2G Family
• AN220190 - How to use RTC in TRAVEO™ T2G family

ModusToolbox™ is available online:

• https://www.infineon.com/modustoolbox

Associated TRAVEO™ T2G MCUs can be found on:

• https://www.infineon.com/cms/en/product/microcontroller/32-bit-traveo-t2g-arm-cortex-microcontroller/

More code examples can be found on the GIT repository:

• TRAVEO™ T2G Code examples

For additional trainings, visit our webpage:

• TRAVEO™ T2G trainings

For questions and support, use the TRAVEO™ T2G Forum:

• https://community.infineon.com/t5/TRAVEO-T2G/bd-p/TraveoII