This code example shows how to switch the bank configuration of flash memory.
The device used in this code example (CE) is:
The board used for testing is:
- TRAVEO™ T2G evaluation kit (KIT_T2G-B-H_EVK, KIT_T2G-B-H_LITE)
TRAVEO™ T2G MCUs have a Dual Bank mode in Code and Data Flash memory, where the area is divided into two banks in addition to the Single Bank mode used for normal mapping. In Dual Bank mode, either logical bank 0 or 1 can be the active bank and the other side becomes the inactive bank by performing bank switching. This feature allows for quick activation of the new firmware and rollback to the old firmware after a firmware rewrite via OTA (Over-The-Air). In addition, the new firmware can be written to the inactive bank while the application is running in the active bank, significantly reducing system downtime. This CE shows how to switch the bank mode on code flash memory.
Code Flash
- Optional memory size: 4 MB, 6 MB, and 8 MB
- Programming and erasing functions
- ECC function: 64 bits + 8 bits
- Erase sector size of 32 KB for large sector and 8 KB for small sector
- Program size: 64 bits, 256 bits, and 4096 bits
- Supports Single Bank and Dual Bank modes
- Supports reading while programming/erasing
- 1,000 program/erase cycles
- Retention of 20 years
Work Flash
- Optional memory size: 256 KB
- Programming and erasing functions
- ECC function: 32 bits + 7 bits
- Erase sector size is 2 KB for large sector and 128 bytes for small sector
- Program size: 32 bits
- Supports Single Bank and Dual Bank modes
- Supports reading while programming/erasing
- Supports differential sensing architecture
- 250,000 program/erase cycles
- Retention of 10 years
More details can be found in Technical Reference Manual (TRM), Registers TRM and Data Sheet.
This CE has been developed for:
-
TRAVEO™ T2G evaluation kit (KIT_T2G-B-H_EVK)
No changes are required from the board's default settings. -
TRAVEO™ T2G Body High Lite evaluation kit (KIT_T2G-B-H_LITE)
No changes are required from the board's default settings.
The figure below shows the overview of Code Flash bank modes on device that has 8MB Code Flash memory:
In this CE, different data are placed at two addresses in Single-Bank mode (the red and purple rectangle in figure above) that would be the same address in Dual-Bank mode, and each data is checked to see at which address it appears in mapping A and mapping B in single-bank mode and dual-bank mode.
Bank switching operation
- When changing the bank mode, it must be operated by a code located outside of the Code Flash. This is because a change in the value of a specific address due to bank mode switching may cause the program to perform an unintended operation. In this CE, main() and some functions which might be called by main() are located in internal SRAM.
- The bank mode is switched by two bits MAIN_BANK_MODE and MAIN_MAP in the FLASHC_FLASH_CTL register.
- After setting these to the appropriate values, the register should be read back to ensure that the write operation reaches the register from the write buffer.
- Then calling __ISB() to ensure that the already read instructions in CPU pipeline are discarded and setting FLASHC_FLASH_CMD_INV bit of FLASHC_FLASH_CMD to invalidate cache and buffers on flash memory.
Miscellaneous settings
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STDIO setting
- Calling cy_retarget_io_init() function to use UART as STDIN/STDOUT
- Initialize the pin specified by CYBSP_DEBUG_UART_TX as UART TX, the pin specified by CYBSP_DEBUG_UART_RX as UART RX (these pins are connected to KitProg3 COM port)
- The serial port parameters become to 8N1 and 115200 baud
- Calling cy_retarget_io_init() function to use UART as STDIN/STDOUT
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GPIO setting to use the user button
- Calling cyhal_gpio_init() function to initialize GPIO as input mode to read the user button state
- Calling cyhal_gpio_read() to read out the button state
Confirming bank switching result
- When the main() function detects that the user button has been pressed, it switches bank modes sequentially like this: Single Bank -> Dual Bank (mapping A) -> Dual Bank (mapping B) -> Single Bank ...
- You can see in the terminal how the addresses of the different data placed at the two addresses (the red and purple squares in the figure above) change in each bank mode.
For this CE, a terminal emulator is required for displaying outputs and get inputs. Install a terminal emulator if you do not have one. Instructions in this document use Tera Term.
After code compilation, perform the following steps to flashing the device:
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Connect the board to your PC using the provided USB cable through the KitProg3 USB connector.
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Open a terminal program and select the KitProg3 COM port. Set the serial port parameters to 8N1 and 115200 baud.
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Program the board using one of the following:
- Select the CE project in the Project Explorer.
- In the Quick Panel, scroll down, and click [Project Name] Program (KitProg3_MiniProg4).
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After programming, the CE starts automatically. Confirm that the messages are displayed on the UART terminal.
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You can debug the example to step through the code. In the IDE, use the [Project Name] Debug (KitProg3_MiniProg4) configuration in the Quick Panel. For details, see the "Program and debug" section in the Eclipse IDE for ModusToolbox™ software user guide.
Note: (Only while debugging) On the CM7 CPU, some code in main() may execute before the debugger halts at the beginning of main(). This means that some code executes twice: once before the debugger stops execution, and again after the debugger resets the program counter to the beginning of main(). See KBA231071 to learn about this and for the workaround.
Relevant Application notes are:
- AN235305 - GETTING STARTED WITH TRAVEO™ T2G FAMILY MCUS IN MODUSTOOLBOX™
- AN220242 - Flash accessing procedure for TRAVEO™ T2G family
- AN229058 - Secured firmware over-the-air (FOTA) update in TRAVEO™ T2G MCU
ModusToolbox™ is available online:
Associated TRAVEO™ T2G MCUs can be found on:
More code examples can be found on the GIT repository:
For additional trainings, visit our webpage:
For questions and support, use the TRAVEO™ T2G Forum: