Add IWDG as STM32.wdtEnable(timeout) / STM32.wdtReset()

cores/stm32l4/STM32.cpp

@@ -45,6 +45,13 @@ uint64_t STM32Class::getSerial()
     return (((uint64_t)serial0 << 16) | ((uint64_t)serial1 >> 16));
 }
 
+void STM32Class::getUID(uint32_t uid[3])
+{
+    uid[0] = *((uint32_t*)0x1fff7590);
+    uid[1] = *((uint32_t*)0x1fff7594);
+    uid[2] = *((uint32_t*)0x1fff7598);
+}
+
 float STM32Class::getVBAT()
 {
     int32_t vbat_data, vref_data, vrefint;
@@ -196,6 +203,17 @@ void STM32Class::reset()
     stm32l4_system_reset();
 }
 
+void  STM32Class::wdtEnable(uint32_t timeout)
+{
+    stm32l4_iwdg_enable(timeout);
+}
+
+void  STM32Class::wdtReset()
+{
+    stm32l4_iwdg_reset();
+}
+
+
 bool STM32Class::flashErase(uint32_t address, uint32_t count)
 {
     if (address & 2047) {

cores/stm32l4/STM32.h

@@ -56,6 +56,7 @@
 class STM32Class {
 public:
     uint64_t getSerial();
+    void getUID(uint32_t uid[3]);
 
     float getVBAT();
     float getVREF();
@@ -72,6 +73,9 @@ class STM32Class {
     void  shutdown(uint32_t pin, uint32_t mode, uint32_t timeout = 0);
     void  reset();
 
+    void  wdtEnable(uint32_t timeout);
+    void  wdtReset();
+
     bool  flashErase(uint32_t address, uint32_t count);
     bool  flashProgram(uint32_t address, const void *data, uint32_t count);
 

cores/stm32l4/stm32l4_wiring_private.h

@@ -51,6 +51,7 @@ extern "C" {
 #include "stm32l4_flash.h"
 #include "stm32l4_sdmmc.h"
 #include "stm32l4_sdspi.h"
+#include "stm32l4_iwdg.h"
 
 #define STM32L4_SVCALL_IRQ_PRIORITY  15
 #define STM32L4_PENDSV_IRQ_PRIORITY  15

system/STM32L4xx/Include/stm32l4_iwdg.h

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2017 Thomas Roell.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal with the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ *  1. Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimers.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimers in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. Neither the name of Thomas Roell, nor the names of its contributors
+ *     may be used to endorse or promote products derived from this Software
+ *     without specific prior written permission.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+ * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * WITH THE SOFTWARE.
+ */
+
+#if !defined(_STM32L4_IWDG_H)
+#define _STM32L4_IWDG_H
+
+#include <stdint.h>
+
+#include "stm32l4xx.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern void stm32l4_iwdg_enable(uint32_t timeout);
+
+static inline void stm32l4_iwdg_reset(void)
+{
+    IWDG->KR = 0xaaaa;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _STM32L4_NVIC_H */

system/STM32L4xx/Source/Makefile

@@ -51,6 +51,7 @@ LSRCS = \
 	stm32l4_exti.c \
 	stm32l4_flash.c \
 	stm32l4_i2c.c \
+	stm32l4_iwdg.c \
 	stm32l4_gpio.c \
 	stm32l4_nvic.c \
 	stm32l4_qspi.c \

system/STM32L4xx/Source/boot_stm32l4xx.c

@@ -163,7 +163,7 @@ __attribute__((naked)) void reset_stm32l4xx(void)
 
 	FLASH->ACR = FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_2WS;
 
-	if (!(PWR->SR1 & PWR_SR1_SBF))
+	if (!(PWR->SR1 & PWR_SR1_SBF) && !(RCC->CSR & (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF | RCC_CSR_BORRSTF | RCC_CSR_OBLRSTF | RCC_CSR_FWRSTF)))
 	{
 	    stm32l4_iap();
 	}

system/STM32L4xx/Source/stm32l4_iwdg.c

@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2017 Thomas Roell.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal with the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ *  1. Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimers.
+ *  2. Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimers in the
+ *     documentation and/or other materials provided with the distribution.
+ *  3. Neither the name of Thomas Roell, nor the names of its contributors
+ *     may be used to endorse or promote products derived from this Software
+ *     without specific prior written permission.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+ * CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * WITH THE SOFTWARE.
+ */
+
+#include <stdio.h>
+
+#include "stm32l4xx.h"
+#include "stm32l4_iwdg.h"
+
+#include "armv7m.h"
+
+void stm32l4_iwdg_enable(uint32_t timeout)
+{
+    uint32_t iwdg_pr, iwdg_rl, iwdg_sr;
+
+    if (timeout > 32000)
+    {
+	timeout = 32000;
+    }
+
+    iwdg_pr = 0;
+    iwdg_rl = (timeout * 32768) / (4 * 1000);
+
+    while (iwdg_rl > 4096)
+    {
+	iwdg_pr++;
+	iwdg_rl >>= 1;
+    }
+
+    IWDG->KR = 0xcccc;
+    IWDG->KR = 0x5555;
+    IWDG->PR = iwdg_pr;
+    IWDG->RLR = iwdg_rl -1;
+
+    do
+    {
+	iwdg_sr = IWDG->SR;
+    }
+    while (iwdg_sr & (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU));
+
+    IWDG->KR = 0xaaaa;
+}

system/STM32L4xx/Source/stm32l4_system.c

@@ -651,27 +651,27 @@ void stm32l4_system_initialize(uint32_t hclk, uint32_t pclk1, uint32_t pclk2, ui
 	    stm32l4_system_device.reset = SYSTEM_RESET_OTHER;
 	}
 
-	if (RCC->CSR & RCC_CSR_FWRSTF)
+	else if (RCC->CSR & RCC_CSR_FWRSTF)
 	{
 	    stm32l4_system_device.reset = SYSTEM_RESET_FIREWALL;
 	}
 
-	if (RCC->CSR & RCC_CSR_BORRSTF)
+	else if (RCC->CSR & RCC_CSR_BORRSTF)
 	{
 	    stm32l4_system_device.reset = SYSTEM_RESET_BROWNOUT;
 	}
 
-	if (RCC->CSR & (RCC_CSR_IWDGRSTF | RCC_CSR_WWDGRSTF))
+	else if (RCC->CSR & (RCC_CSR_IWDGRSTF | RCC_CSR_WWDGRSTF))
 	{
 	    stm32l4_system_device.reset = SYSTEM_RESET_WATCHDOG;
 	}
 
-	if (RCC->CSR & RCC_CSR_SFTRSTF)
+	else if (RCC->CSR & RCC_CSR_SFTRSTF)
 	{
 	    stm32l4_system_device.reset = SYSTEM_RESET_SOFTWARE;
 	}
 
-	if (RCC->CSR & RCC_CSR_PINRSTF)
+	else if (RCC->CSR & RCC_CSR_PINRSTF)
 	{
 	    stm32l4_system_device.reset = SYSTEM_RESET_EXTERNAL;
 	}
@@ -852,6 +852,10 @@ void stm32l4_system_initialize(uint32_t hclk, uint32_t pclk1, uint32_t pclk2, ui
 	CoreDebug->DEMCR &= ~0x01000000;
     }
 
+    /* Avoid IWDG/WWDG triggering reset while debugging.
+     */
+    DBGMCU->APB1FZR1 |= (DBGMCU_APB1FZR1_DBG_IWDG_STOP | DBGMCU_APB1FZR1_DBG_WWDG_STOP);
+
     RCC->AHB1SMENR &= ~(RCC_AHB1SMENR_FLASHSMEN |
 			RCC_AHB1SMENR_SRAM1SMEN);