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<title>參考索引</title>
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<h1>參考索引 </h1>
<h2><a href="#A">A</a> <a href="#B">B</a> <a href="#C">C</a> <a href="#D">D</a> <a href="#E">E</a> <a href="#F">F</a> G <a href="#H">H</a> <a href="#I">I</a> J K <a href="#L">L</a> <a href="#M">M</a> <a href="#N">N</a> O <a href="#P">P</a> <a href="#Q">Q</a> <a href="#R">R</a> <a href="#S">S</a> <a href="#T">T</a> <a href="#U">U</a> <a href="#V">V</a> <a href="#W">W</a> <a href="#X">X</a> Y Z</h2>
<a class="clsTOCItem" href="PentiumM_HH/ERB/__cycles_divider_busy.html" target="right">% 除法器忙週期</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Events4/2nd-Level_Cache_Read_References.html" target="right">二級快取</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l2_ozq_cancels0.html" target="right">2_OZQ_CANCELS0</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Pentium4P_HH/AdviceP_HH/4mb_aliasing.html" target="right">4MB 重疊</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/64k_aliasing.html" target="right">64K 重疊</a>
<h2><a name=A></a>A</h2>
<a class="clsTOCItem" href="Reference_HH/reference.html" target="right">關於參考資訊</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Lips/Address_Calculation.html" target="right">地址計算</a>
<br><a class="clsTOCItem" href="PentiumM_HH/AdviceB_HH/about_processor_counters.html" target="right">建議</a>    
<br>    <a class="clsTOCItem" href="Itanium2_HH/AdviceIPF2_HH/about_advice_for_the_intel(R)_itanium(R)_2_processor.html" target="right">英特爾(R) 安騰(R) 2 處理器</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/about_advice_for_the_intel(r)_pentium(r)_4_processor.html" target="right">英特爾(R) 奔騰(R) 4 處理器</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Pentium4P_HH/AdviceP_HH/about_advice_for_the_processor.html" target="right">含第三代數據流單指令多數據擴充套件指令集 (SSE3) 的英特爾(R) 奔騰(R) 4 處理器</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/AdviceB_HH/about_processor_counters.html" target="right">英特爾(R) 奔騰(R) M 處理器</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/alat_capacity_miss.html" target="right">ALAT_CAPACITY_MISS</a>  
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/alat_ear_events.html" target="right">ALAT_EAR_EVENTS</a>  
<br><a class="clsTOCItem" href="Pentium4_HH/Events4/all_uc_from_the_processor.html" target="right">所有 UC</a>  
<br><a class="clsTOCItem" href="Pentium4_HH/Events4/all_wc_from_the_processor.html" target="right">所有 WC</a>  
<br><a class="clsTOCItem" href="Pentium4_HH/Events4/all_wcb_evictions.html" target="right">所有 WCB 收回</a>  
<br><a class="clsTOCItem" href="Pentium4_HH/Events4/stalls_of_store_buffer_resources.html" target="right">分配暫停</a>  
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/avg_cpt.html" target="right">AVG_CPT</a>  
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/avg_ia32_ipt.html" target="right">AVG_IA32_IPT</a>  
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/avg_ia64_ipt.html" target="right">AVG_IA64_IPT</a>  
<br><a class="clsTOCItem" href="Pentium4_HH/Pentium4P_HH/AdviceP_HH/Avoiding_4MB_Aliasing.html" target="right">避免</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Pentium4P_HH/AdviceP_HH/4mb_aliasing.html" target="right">4MB 重疊</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/avoiding_64k_aliasing.html" target="right">64k 重疊</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/avoiding_blocked_store_forwards.html" target="right">阻塞的儲存轉發</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/avoiding_branch_mispredictions.html" target="right">分支預測失誤</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/avoiding_cache_line_splits.html" target="right">快取線拆分</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/avoiding_dtlb_page_walk_misses.html" target="right">DTLB 頁查詢未命中</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/avoiding_first-level_cache_load_misses.html" target="right">一級快取載入未命中</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/avoiding_itlb_page_walk_misses.html" target="right">ITLB 頁查詢未命中</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/avoiding_memory_ordering_pipeline_clears.html" target="right">記憶體順序管道清除</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/avoiding_pipeline_clears.html" target="right">管道清除</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/avoiding_second-level_cache_load_misses.html" target="right">二級快取載入未命中</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/avoiding_self-modifying_code_pipeline_clears.html" target="right">自我修改程式碼管道清除</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/sse_denormal_numbers.html" target="right">SSE 非規格化數</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/avoiding_sse_denormals.html" target="right">SSE 非規格化</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/found_x87_denormal_numbers_.html" target="right">x87 非規格化數</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Pentium4P_HH/AdviceP_HH/avoiding_x87_denormals.html" target="right">x87 非規格化</a>
<h2><a name=B></a>B</h2>
<a class="clsTOCItem" href="Itanium2_HH/Events642/back_end_bubble.html" target="right">BACK_END_BUBBLE</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/baclears_asserted.html" target="right">聲言 BACLEARS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/be_br_mispred_detail.html" target="right">BE_BR_MISPRED_DETAIL</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/be_exe_bubble.html" target="right">BE_EXE_BUBBLE</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/be_flush_bubble.html" target="right">BE_FLUSH_BUBBLE</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/be_l1d_fpu_bubble.html" target="right">BE_L1D_FPU_BUBBLE</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/be_lost_bw_due_to_fe.html" target="right">BE_LOST_BW_DUE_TO_FE</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/be_rse_bubble.html" target="right">BE_RSE_BUBBLE</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bil_hitm_line_ratio.html" target="right">BIL_HITM_LINE_RATIO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bil_ratio.html" target="right">BIL_RATIO</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/blocked_store_forwards.html" target="right">阻塞的儲存轉發</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/avoiding_first-level_cache_load_misses.html" target="right">模組化</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/bogus_branches.html" target="right">偽分支</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/mispredicted_branch_instructions_(mispredicted_at_decoding).html" target="right">BR_BAC_MISSP_EXEC</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/call_instructions_executed.html" target="right">BR_CALL_EXEC</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/mispredicted_call_instructions_executed.html" target="right">BR_CALL_MISSP_EXEC</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/conditional_branch_instructions_executed.html" target="right">BR_CND_EXEC</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/mispredicted_conditional_branch_instructions_executed.html" target="right">BR_CND_MISSP_EXEC</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/indirect_call_instructions_executed.html" target="right">BR_IND_CALL_EXEC</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/indirect_branch_instructions_executed.html" target="right">BR_IND_EXEC</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/mispredicted_indirect_branch_instructions_executed.html" target="right">BR_IND_MISSP_EXEC</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/branch_instructions_executed.html" target="right">BR_INST_EXEC</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/BR_MISPRED_DETAIL.html" target="right">BR_MISPRED_DETAIL</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/br_mispred_detail2.html" target="right">BR_MISPRED_DETAIL2</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/mispredicted_branch_instructions_(mispredicted_at_execution).html" target="right">BR_MISSP_EXEC</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/br_path_pred.html" target="right">BR_PATH_PRED</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/br_path_pred2.html" target="right">BR_PATH_PRED2</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/mispredicted_return_branch_instructions_executed_(mispredicted_at_decoding).html" target="right">BR_RET_BAC_MISSP_EXEC</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/return_branch_instructions_executed.html" target="right">BR_RET_EXEC</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/mispredicted_return_branch_instructions_executed_(mispredicted_at_execution).html" target="right">BR_RET_MISSP_EXEC</a>
<br><a class="clsTOCItem" href="PentiumM_HH/AdviceB_HH/frequent_branch_mispredictions.html" target="right">分支</a>
<br>    <a class="clsTOCItem" href="XScale_HH/XscEvents/Branch_Instruction_Executed_(0x5).html" target="right">執行的事件</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/branch_instructions_decoded.html" target="right">解碼的指令</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/branch_instructions_executed.html" target="right">執行的指令</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/branch_instructions_retired.html" target="right">失效的指令</a>
<br>    <a class="clsTOCItem" href="XScale_HH/XscEvents/Branch_Misprediction_(0x6).html" target="right">預測失誤事件</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/ER4/branch_misprediction_rate.html" target="right">預測失誤比率</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/branch_mispredictions.html" target="right">預測失誤</a>  
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/optimizing_branch_prediction.html" target="right">預測</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/branch_event.html" target="right">BRANCH_EVENT</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bril_hitm_line_ratio.html" target="right">BRIL_HITM_LINE_RATIO</a>
<br><a class="clsTOCItem" href="PentiumM_HH/AdviceB_HH/high_bus_utilization.html" target="right">匯流排</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Events4/bus_accesses_from_all_agents.html" target="right">匯流排訪問</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bus_addr_bpri.html" target="right">BUS_ADDR_BPRI</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/bus_all.html" target="right">BUS_ALL</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/bus_backsnp_req.html" target="right">BUS_BACKSNP_REQ</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bus_brq_live_req.html" target="right">BUS_BRQ_LIVE_REQ</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/BUS_BRQ_LIVE_REQ_HI.html" target="right">BUS_BRQ_LIVE_REQ_HI</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/BUS_BRQ_LIVE_REQ_LO.html" target="right">BUS_BRQ_LIVE_REQ_LO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/bus_brq_req_inserted.html" target="right">BUS_BRQ_REQ_INSERTED</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bus_burst.html" target="right">BUS_BURST</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/bus_data_cycle.html" target="right">BUS_DATA_CYCLE</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/BUS_HITM.html" target="right">BUS_HITM</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bus_hitm_ratio.html" target="right">BUS_HITM_RATIO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bus_hits_ratio.html" target="right">BUS_HITS_RATIO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/bus_io.html" target="right">BUS_IO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bus_io_cycle_ratio.html" target="right">BUS_IO_CYCLE_RATIO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bus_io_rd_ratio.html" target="right">BUS_IO_RD_RATIO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bus_ioq_live_req.html" target="right">BUS_IOQ_LIVE_REQ</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/BUS_IOQ_LIVE_REQ_HI.html" target="right">BUS_IOQ_LIVE_REQ_HI</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/BUS_IOQ_LIVE_REQ_LO.html" target="right">BUS_IOQ_LIVE_REQ_LO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/bus_lock.html" target="right">BUS_LOCK</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/BUS_MEM_READ.html" target="right">BUS_MEM_READ</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/BUS_MEM_READ_OUT_HI.html" target="right">BUS_MEM_READ_OUT_HI</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/BUS_MEM_READ_OUT_LO.html" target="right">BUS_MEM_READ_OUT_LO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bus_mem_read_outstanding.html" target="right">BUS_MEM_READ_OUTSTANDING</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/BUS_MEMORY.html" target="right">BUS_MEMORY</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bus_ooq_live_req.html" target="right">BUS_OOQ_LIVE_REQ</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/BUS_OOQ_LIVE_REQ_HI.html" target="right">BUS_OOQ_LIVE_REQ_HI</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/BUS_OOQ_LIVE_REQ_LO.html" target="right">BUS_OOQ_LIVE_REQ_LO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bus_partial.html" target="right">BUS_PARTIAL</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bus_partial_ratio.html" target="right">BUS_PARTIAL_RATIO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/BUS_RD_ALL.html" target="right">BUS_RD_ALL</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/BUS_RD_DATA.html" target="right">BUS_RD_DATA</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bus_rd_data_ratio.html" target="right">BUS_RD_DATA_RATIO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/BUS_RD_HIT.html" target="right">BUS_RD_HIT</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/BUS_RD_HITM.html" target="right">BUS_RD_HITM</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bus_rd_hitm_ratio.html" target="right">BUS_RD_HITM_RATIO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bus_rd_instructions.html" target="right">BUS_RD_INSTRUCTIONS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/BUS_RD_INVAL.html" target="right">BUS_RD_INVAL</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/BUS_RD_INVAL_ALL_HITM.html" target="right">BUS_RD_INVAL_ALL_HITM</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bus_rd_inval_bst.html" target="right">BUS_RD_INVAL_BST</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/BUS_RD_INVAL_BST_HITM.html" target="right">BUS_RD_INVAL_BST_HITM</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bus_rd_inval_bst_memory.html" target="right">BUS_RD_INVAL_BST_MEMORY</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/BUS_RD_INVAL_HITM.html" target="right">BUS_RD_INVAL_HITM</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bus_rd_inval_memory.html" target="right">BUS_RD_INVAL_MEMORY</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/BUS_RD_IO.html" target="right">BUS_RD_IO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/BUS_RD_PRTL.html" target="right">BUS_RD_PRTL</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bus_rd_prtl_ratio.html" target="right">BUS_RD_PRTL_RATIO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/bus_snoop_stall_cycles.html" target="right">BUS_SNOOP_STALL_CYCLES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/bus_snoopq_req.html" target="right">BUS_SNOOPQ_REQ</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/bus_snoops.html" target="right">BUS_SNOOPS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/bus_snoops_hitm.html" target="right">BUS_SNOOPS_HITM</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/bus_wb_ratio.html" target="right">BUS_WB_RATIO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/BUS_WR_WB.html" target="right">BUS_WR_WB</a>
<h2><a name=C></a>C</h2>
<a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/avoiding_first-level_cache_load_misses.html" target="right">快取</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/avoiding_first-level_cache_load_misses.html" target="right">模組化</a>
<br>   <span
class=clsTOCItem> </span><a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/cache_line_splits_due_to_loads.html" target="right">載入導致的快取線拆分</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/cache_line_splits_due_to_stores.html" target="right">儲存導致的快取線拆分</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/cacheable_read_ratio.html" target="right">CACHEABLE_READ_RATIO</a>
<br><a class="clsTOCItem" href="calculating_cpi.html" target="right">計算</a>
<br>    <a class="clsTOCItem" href="calculating_cpi.html" target="right">CPI</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/call_instructions_executed.html" target="right">call 指令</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/call_instructions_executed.html" target="right">英特爾(R) 奔騰(R) M 處理器事件</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/cautionary_statement.html" target="right">注意事項聲明</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/clocks_while_interrupts_masked.html" target="right">中斷遮蔽時鐘週期</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/clocks_while_interrupts_masked_and_an_interrupt_is_pending.html" target="right">且中斷暫停</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/clockticks.html" target="right">時鐘訊號</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/ER4/Clockticks_per_Instructions_Retired.html" target="right">每失效指令</a>
<br><a class="clsTOCItem" href="PentiumM_HH/AdviceB_HH/frequent_branch_mispredictions.html" target="right">cmov</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/code_debug_register_matches.html" target="right">CODE_DEBUG_REGISTER_MATCHES</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Events4/64k_aliasing_conflicts.html" target="right">編碼缺陷</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/collect_additional_events_to_characterize_the_trace_cache_delivery_performance.html" target="right">採集附加的事件</a>
<br><a class="clsTOCItem" href="PentiumM_HH/AdviceB_HH/significant_floating_point_activity.html" target="right">編譯器驅動</a>
<br><a class="clsTOCItem" href="XScale_HH/LipsXSc/Coprocessor_Result_Penalty.html" target="right">協處理器結果</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Events4/Clockticks.html" target="right">CPI</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Events4/Instructions_retired.html" target="right">限制事件</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/clockticks.html" target="right">CPU_CLK_UNHALTED</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/cpu_cpl_changes.html" target="right">CPU_CPL_CHANGES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/CPU_CYCLES.html" target="right">CPU_CYCLES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/ctrl_spec_miss_ratio.html" target="right">CTRL_SPEC_MISS_RATIO</a>
<br>週期    <a class="clsTOCItem" href="PentiumM_HH/AdviceB_HH/poor_cpi.html" target="right">CPI 不佳</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/cycles_divider_busy.html" target="right">除法器忙</a>
<br>    <a class="clsTOCItem" href="XScale_HH/LipsXSc/Cycle_Information.html" target="right">資訊</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/cycles_instruction_fetch_stalled.html" target="right">指令獲取暫停</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/cycles_l2_data_bus_busy.html" target="right">二級數據總線忙</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/cycles_l2_data_bus_busy_transferring_data_to_cpu.html" target="right">二級數據總線傳輸數據到 CPU 忙</a>    
<br>    <a class="clsTOCItem" href="Pentium4_HH/ER4/cycles_per_retired_uop.html" target="right">每失效的微操作</a>
<h2><a name=D></a>D</h2>
<a class="clsTOCItem" href="XScale_HH/XscEvents/Data_Dependency_Stall_(0x2).html" target="right">數據相關暫停</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/data_memory_references_all.html" target="right">數據記憶體引用（所有）</a>
<br>    <a class="clsTOCItem" href="XScale_HH/XscEvents/Data_Dependency_Stall_(0x2).html" target="right">相關暫停</a>
<br>    <a class="clsTOCItem" href="XScale_HH/LipsXSc/Data_Process_Penalty.html" target="right">處理結果</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/data_debug_register_fault.html" target="right">DATA_DEBUG_REGISTER_FAULT</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/data_debug_register_matches.html" target="right">DATA_DEBUG_REGISTER_MATCHES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/DATA_EAR_EVENTS.html" target="right">DATA_EAR_EVENTS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/DATA_REFERENCES_SET0.html" target="right">DATA_REFERENCES_SET0</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/DATA_REFERENCES_SET1.html" target="right">DATA_REFERENCES_SET1</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/data_spec_miss_ratio.html" target="right">DATA_SPEC_MISS_RATIO</a>
<br><a class="clsTOCItem" href="XScale_HH/XscEvents/Data_Cache_Buffer_Full_Contiguous_Counter_(0x9).html" target="right">數據快取暫停</a>
<br>    <a class="clsTOCItem" href="XScale_HH/XscEvents/Data_Cache_Buffer_Full_Cycle_Counter_(0x8).html" target="right">持續時間</a>
<br><a class="clsTOCItem" href="XScale_HH/XscEvents/Data_Cache_Access_(0xa).html" target="right">數據快取</a>
<br>    <a class="clsTOCItem" href="XScale_HH/XscEvents/Data_Cache_Access_(0xa).html" target="right">訪問</a>
<br>    <a class="clsTOCItem" href="XScale_HH/XscEvents/Data_Cache_Miss_(0xb).html" target="right">未命中</a>
<br>    <a class="clsTOCItem" href="XScale_HH/XscEvents/Data_Cache_Write-back_(0xc).html" target="right">寫回</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/decoder_esp_additions_executed.html" target="right">解碼器</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/decoder_esp_additions_executed.html" target="right">英特爾(R) 奔騰(R) M 處理器事件</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Pentium4P_HH/AdviceP_HH/try_the_following_enhancements_to_decrease_trace_cache_misses.html" target="right">降低</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/decreasing_read_bus_utilization.html" target="right">讀取匯流排利用率</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/decreasing_trace_cache_misses.html" target="right">跟蹤快取未命中</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/decreasing_write_bus_utilization.html" target="right">寫入匯流排利用率</a>
<br><a class="clsTOCItem" href="disclaimer.html" target="right">免責聲明與法律資訊</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/disp_stalled.html" target="right">DISP_STALLED</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/downward_prefetches_issued.html" target="right">向下</a>
<br><a class="clsTOCItem" href="PentiumM_HH/AdviceB_HH/high_bus_utilization.html" target="right">聲言 DRDY</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/dtlb_page_walk_misses.html" target="right">DTLB</a>
<br>    <a class="clsTOCItem" href="XScale_HH/XscEvents/Data_TLB_Miss_(0x4).html" target="right">未命中</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/ERB/dtlb_miss_rate.html" target="right">未命中比率</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/dtlb_page_walk_misses.html" target="right">頁查詢未命中</a>    
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/dtlb_inserts_hpw.html" target="right">DTLB_INSERTS_HPW</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/dtlb_inserts_hpw_retired.html" target="right">DTLB_INSERTS_HPW_RETIRED</a>
<h2><a name=E></a>E</h2>
<a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/eliminating_branches.html" target="right">消除分支</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/l1_cacheable_data_reads_and_writes.html" target="right">EMON_DCACHE_ALL_REF</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/l1_cacheable_data_reads.html" target="right">EMON_DCACHE_CACHE_LD</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/l1_cacheable_lock_reads.html" target="right">EMON_DCACHE_CACHE_LOCK</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/l1_cacheable_data_writes.html" target="right">EMON_DCACHE_CACHE_ST</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/dtlb_misses.html" target="right">EMON_DTLB_MISSES</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/decoder_esp_additions_executed.html" target="right">EMON_ESP_UOPS</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/fused_micro-ops_retired.html" target="right">EMON_FUSED_UOPS_RET</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/SpeedStep(R)_Technology_Transitions_(Voltage_transitions_only).html" target="right">EMON_Gv3_TRANS</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/downward_prefetches_issued.html" target="right">EMON_PREF_RQSTS_DN</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/upward_prefetches_issued.html" target="right">EMON_PREF_RQSTS_UP</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/sse_packed-single_and_scalar-single_instructions_retired.html" target="right">EMON_SSE_SSE2_COMP_INST_RETIRED</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/sse_packed-single_instructions_retired.html" target="right">EMON_SSE_SSE2_INST_RETIRED</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/thermal_trip.html" target="right">EMON_THERMAL_TRIP</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/encbr_mispred_detail.html" target="right">ENCBR_MISPRED_DETAIL</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Events4/Thread_Independent_due_to_ESCR_Restriction_TI_E.html" target="right">ESCR 限制</a>
<br><a class="clsTOCItem" href="PentiumM_HH/LipsB/esp_folding.html" target="right">esp 壓縮</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/About_Derived_Events_for_the_Intel(R)_Itanium(R)_2_Processor.html" target="right">事件比率</a>
<br>    <a class="clsTOCItem" href="Itanium2_HH/ER642/About_Derived_Events_for_the_Intel(R)_Itanium(R)_2_Processor.html" target="right">英特爾(R) 安騰(R) 2 處理器</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/ER4/about.html" target="right">英特爾(R) 奔騰(R) 4 處理器</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Pentium4P_HH/ERP/about.html" target="right">含第三代數據流單指令多數據擴充套件指令集 (SSE3) 的英特爾(R) 奔騰(R) 4 處理器</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/ERB/abouteventratios_for_intel(r)_b_processors.html" target="right">英特爾(R) 奔騰(R) M 處理器</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/aboutevents_for_intel(r)_b_processors.html" target="right">事件</a>
<br>    <a class="clsTOCItem" href="XScale_HH/XscEvents/about_events.html" target="right">英特爾 XScale(R) 微體系結構</a>
<br>    <a class="clsTOCItem" href="Itanium2_HH/Events642/about_events_for_the_itanium(r)_2_processor.html" target="right">英特爾(R) 安騰(R) 2 處理器</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Events4/about.html" target="right">英特爾(R) 奔騰(R) 4 處理器</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Pentium4P_HH/EventsP/instructions_completed_.html" target="right">含第三代數據流單指令多數據擴充套件指令集 (SSE3) 的英特爾(R) 奔騰(R) 4 處理器</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/aboutevents_for_intel(r)_b_processors.html" target="right">英特爾(R) 奔騰(R) M 處理器</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Events4/aboutevents.html" target="right">英特爾(R) 至強(TM) 處理器的</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/extern_dp_pins_0_to_3.html" target="right">EXTERN_DP_PINS_0_TO_3</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/extern_dp_pins_4_to_5.html" target="right">EXTERN_DP_PINS_4_TO_5</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/external_bus_burst_instruction_fetches.html" target="right">外部匯流排</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/external_bus_burst_instruction_fetches.html" target="right">脈衝指令獲取</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/external_bus_burst_read_operations.html" target="right">脈衝讀取操作</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/external_bus_burst_transactions.html" target="right">脈衝事務</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/external_bus_cycles_lock_signal_asserted.html" target="right">週期 — 聲言 LOCK 訊號</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/external_bus_cycles_while_bnr_asserted.html" target="right">BNR 期間的週期</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/external_bus_cycles_while_hit_asserted.html" target="right">HIT 期間的週期</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/external_bus_cycles_while_hitm_asserted.html" target="right">HITM 期間的週期</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/external_bus_cycles_while_processor_receiving_data.html" target="right">處理器接收數據期間的週期</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/external_bus_cycles_while_receive_active.html" target="right">接收期間的週期</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/external_bus_cycles_while_snoop_stalled.html" target="right">嗅探暫停期間的週期</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/external_bus_deferred_reply_transactions.html" target="right">應答延遲事務</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/external_bus_i_o_bus_transactions.html" target="right">I/O 匯流排事務</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/external_bus_invalidate_transactions.html" target="right">失效事務</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/external_bus_memory_transactions.html" target="right">記憶體事務</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/external_bus_partial_memory_transactions.html" target="right">部分記憶體事務</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/external_bus_partial_write_transactions.html" target="right">部分寫入事務</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/external_bus_read_for_ownership_transaction.html" target="right">所有權讀取事務</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/external_bus_request_outstanding.html" target="right">請求未決</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/external_bus_transactions.html" target="right">事務</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/external_bus_writeback_transactions.html" target="right">寫回事務</a>
<h2><a name=F></a>F</h2>
<a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/pipeline_clears_from_memory_ordering_issues.html" target="right">錯誤共享</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/fe_bubble.html" target="right">FE_BUBBLE</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/FE_LOST_BW.html" target="right">FE_LOST_BW</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Lips/FIFO_Buffer.html" target="right">FIFO 快取區</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/first-level_cache_load_misses.html" target="right">一級快取載入未命中</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Lips/lipsfp_doesnt_pair.html" target="right">浮點</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Lips/lipsfp_doesnt_pair.html" target="right">與整數指令無法配對</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/floating-point_assist_(micro-code).html" target="right">協助（微程式碼）</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/ERB/fp_assist_performance_impact.html" target="right">協助效能影響</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/ER4/floating-point_computation_instructions.html" target="right">計算指令</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/fp_computational_operations_executed.html" target="right">執行的計算型操作</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/fp_operations_retired.html" target="right">失效的操作</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Events4/tc_flushes.html" target="right">清除</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/fp_failed_fchkf.html" target="right">FP_FAILED_FCHKF</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/fp_false_sirstall.html" target="right">FP_FALSE_SIRSTALL</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/fp_flush_to_zero.html" target="right">FP_FLUSH_TO_ZERO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/fp_ops_retired.html" target="right">FP_OPS_RETIRED</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/fp_true_sirstall.html" target="right">FP_TRUE_SIRSTALL</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Events4/trace_cache_deliver_mode.html" target="right">前端</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/full_sized_read_invalidate_bus_utilization.html" target="right">完整大小讀取失效匯流排利用率</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/fused_micro-ops_retired.html" target="right">熔合的</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/fused_micro-ops_retired.html" target="right">英特爾(R) 奔騰(R) M 處理器事件</a>
<h2><a name=H></a>H</h2>
<a class="clsTOCItem" href="PentiumM_HH/EventsB/hardware_interrupts_received.html" target="right">接收的硬體中斷</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/hpw_data_references.html" target="right">HPW_DATA_REFERENCES</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Events4/about_ht_classifications.html" target="right">HT 技術</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Events4/about_ht_classifications.html" target="right">超執行緒技術</a>
<h2><a name=I></a>I</h2>
<a class="clsTOCItem" href="Itanium2_HH/Events642/IA32_INST_RETIRED.html" target="right">IA32_INST_RETIRED</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/ia32_ipc.html" target="right">IA32_IPC</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/IA32_ISA_TRANSITIONS.html" target="right">IA32_ISA_TRANSITIONS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/IA64_INST_RETIRED.html" target="right">IA64_INST_RETIRED</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/ia64_ipc.html" target="right">IA64_IPC</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/IA64_TAGGED_INST_RETIRED.html" target="right">IA64_TAGGED_INST_RETIRED</a>
<br><a class="clsTOCItem" href="XScale_HH/XscEvents/Undeliverable_Instruction_(0x1).html" target="right">指令快取</a>
<br>    <a class="clsTOCItem" href="XScale_HH/XscEvents/Undeliverable_Instruction_(0x1).html" target="right">無法傳遞</a>
<br>    <a class="clsTOCItem" href="XScale_HH/XscEvents/Instruction_Cache_Miss_(0x0).html" target="right">未命中</a>    
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/ideal_be_lost_bw_due_to_fe.html" target="right">IDEAL_BE_LOST_BW_DUE_TO_FE</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Lips/lipsprev_imm_disp.html" target="right">立即數運算元與地址位移量</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/INST_CHKA_LDC_ALAT.html" target="right">INST_CHKA_LDC_ALAT</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/inst_dispersed.html" target="right">INST_DISPERSED</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/INST_FAILED_CHKA_LDC_ALAT.html" target="right">INST_FAILED_CHKA_LDC_ALAT</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/INST_FAILED_CHKS_RETIRED.html" target="right">INST_FAILED_CHKS_RETIRED</a>
<br><a class="clsTOCItem" href="XScale_HH/LipsXSc/Multiply_Instruction_Resource_Latency_Penalty.html" target="right">指令</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/instructions_decoded.html" target="right">解碼的</a>
<br>    <a class="clsTOCItem" href="XScale_HH/XscEvents/Instruction_Executed_(0x7).html" target="right">執行的</a>
<br>    <a class="clsTOCItem" href="Reference_HH/About_Instruction_Sets.html" target="right">指令集</a>
<br>    <a class="clsTOCItem" href="Pentium4_HH/Lips/LipsUnreachable_Code.html" target="right">未執行的</a>
<br>    <a class="clsTOCItem" href="XScale_HH/LipsXSc/Multiply_Instruction_Resource_Latency_Penalty.html" target="right">資源延遲</a>
<br>    <a class="clsTOCItem" href="XScale_HH/XscEvents/Instruction_TLB_Miss_(0x3).html" target="right">TLB 未命中</a>    
<br><a class="clsTOCItem" href="XScale_HH/LipsXSc/IS_LDMSTM.html" target="right">指令選擇</a>
<br>    <a class="clsTOCItem" href="XScale_HH/LipsXSc/IS_CONCheck.html" target="right">條件檢查的</a>
<br>    <a class="clsTOCItem" href="XScale_HH/LipsXSc/IS_LDMSTM.html" target="right">LDM/STM 的</a>
<br>    <a class="clsTOCItem" href="XScale_HH/LipsXSc/IS_MULtoShift.html" target="right">將 MUL 替換為移位操作的</a>
<br>    <a class="clsTOCItem" href="XScale_HH/LipsXSc/IS_ShiftByREG.html" target="right">按暫存器移位的</a>
<br>    <a class="clsTOCItem" href="XScale_HH/LipsXSc/IS_SWP.html" target="right">SWP/SWPB 的</a>
<br>    <a class="clsTOCItem" href="XScale_HH/LipsXSc/IS_ADDRMODE.html" target="right">更有效使用定址模式的</a>    
<br><a class="clsTOCItem" href="Reference_HH/inbma.html" target="right">英特爾 NetBurst(R) 微體系結構</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/speedstep(r)_technology_transitions_(all_transitions).html" target="right">英特爾 SpeedStep(R) 技術</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/SpeedStep(R)_Technology_Transitions_(Voltage_transitions_only).html" target="right">英特爾(R) 奔騰(R) M 處理器事件</a>
<br><a class="clsTOCItem" href="Reference_HH/Intel_s_Software_Developer_s_Manuals.html" target="right">線上英特爾(R) 處理器資訊</a>
<br><a class="clsTOCItem" href="XScale_HH/LipsXSc/MAC.html" target="right">TMRC/TMRRC/TEXTRM 與 MAC 單元互動</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/ISB_BUNPAIRS_IN.html" target="right">ISB_BUNPAIRS_IN</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/isb_lines_in.html" target="right">ISB_LINES_IN</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/itlb_page_walk_misses.html" target="right">ITLB 頁查詢未命中</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/ITLB_MISSES_FETCH.html" target="right">ITLB_MISSES_FETCH</a>
<h2><a name=L></a>L</h2>
<a class="clsTOCItem" href="PentiumM_HH/EventsB/l1_cacheable_data_reads.html" target="right">一級可快取</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/l1_cacheable_data_reads.html" target="right">數據讀取</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/l1_cacheable_data_reads_and_writes.html" target="right">數據讀取與寫入</a>
<br> <a class="clsTOCItem" href="PentiumM_HH/EventsB/l1_cacheable_data_writes.html" target="right">data writes</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/l1_cacheable_lock_reads.html" target="right">鎖定讀取</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/L1D_READS_SET0.html" target="right">L1D_READS_SET0</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/L1D_READS_SET1.html" target="right">L1D_READS_SET1</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l1dtlb_ear_events.html" target="right">L1DTLB_EAR_EVENTS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l1dtlb_for_l1d_miss_ratio.html" target="right">L1DTLB_FOR_L1D_MISS_RATIO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l1dtlb_references.html" target="right">L1DTLB_REFERENCES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/L1DTLB_TRANSFER.html" target="right">L1DTLB_TRANSFER</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l1i_demand_miss_ratio.html" target="right">L1I_DEMAND_MISS_RATIO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/L1I_EAR_EVENTS.html" target="right">L1I_EAR_EVENTS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/L1I_FETCH_ISB_HIT.html" target="right">L1I_FETCH_ISB_HIT</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l1i_fetch_rab_hit.html" target="right">L1I_FETCH_RAB_HIT</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l1i_fills.html" target="right">L1I_FILLS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l1i_miss_ratio.html" target="right">L1I_MISS_RATIO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l1i_prefetch_miss_ratio.html" target="right">L1I_PREFETCH_MISS_RATIO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l1i_prefetch_stall.html" target="right">L1I_PREFETCH_STALL</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/L1I_PREFETCHES.html" target="right">L1I_PREFETCHES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l1i_purge.html" target="right">L1I_PURGE</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l1i_pvab_overflow.html" target="right">L1I_PVAB_OVERFLOW</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l1i_rab_almost_full.html" target="right">L1I_RAB_ALMOST_FULL</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l1i_rab_full.html" target="right">L1I_RAB_FULL</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/L1I_READS.html" target="right">L1I_READS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l1i_references.html" target="right">L1I_REFERENCES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l1i_snoop.html" target="right">L1I_SNOOP</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l1i_strm_prefetches.html" target="right">L1I_STRM_PREFETCHES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l1itlb_ear_events.html" target="right">L1ITLB_EAR_EVENTS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l1itlb_inserts_hpw.html" target="right">L1ITLB_INSERTS_HPW</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l1itlb_miss_ratio.html" target="right">L1ITLB_MISS_RATIO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l1itlb_references.html" target="right">L1ITLB_REFERENCES</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/l2_address_strobes__address_bus_utilization.html" target="right">二級地址選通 => 地址匯流排利用率</a>
<br><a class="clsTOCItem" href="PentiumM_HH/ERB/l2_bus_busy_loading_data.html" target="right">二級匯流排忙於載入數據</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/l2_cache_instruction_fetch_misses_highly_correlated.html" target="right">二級快取</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/l2_cache_instruction_fetch_misses_highly_correlated.html" target="right">指令獲取未命中</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/l2_cache_instruction_fetches.html" target="right">二級指令獲取</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/ERB/l2_cache_miss_performance_impact_.html" target="right">二級未命中效能影響</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/l2_cache_read_misses_highly_correlated.html" target="right">二級讀取未命中</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/l2_cache_reads.html" target="right">二級讀取</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/l2_cache_requests.html" target="right">二級請求</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/l2_cache_write_misses_highly_correlated.html" target="right">二級寫入未命中</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/l2_cache_writes.html" target="right">二級寫入</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l2_bad_lines_selected.html" target="right">L2_BAD_LINES_SELECTED</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l2_bypass.html" target="right">L2_BYPASS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l2_data_ratio.html" target="right">L2_DATA_RATIO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l2_data_reads.html" target="right">L2_DATA_READS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/L2_DATA_REFERENCES.html" target="right">L2_DATA_REFERENCES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l2_data_writes.html" target="right">L2_DATA_WRITES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l2_force_recirc.html" target="right">L2_FORCE_RECIRC</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l2_got_recirc_ifetch.html" target="right">L2_GOT_RECIRC_IFETCH</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l2_got_recirc_ozq_acc.html" target="right">L2_GOT_RECIRC_OZQ_ACC</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l2_ifet_cancels.html" target="right">L2_IFET_CANCELS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/L2_INST_DEMAND_READS.html" target="right">L2_INST_DEMAND_READS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l2_inst_fetches.html" target="right">L2_INST_FETCHES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/L2_INST_PREFETCHES.html" target="right">L2_INST_PREFETCHES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l2_inst_references.html" target="right">L2_INST_REFERENCES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/L2_ISSUED_RECIRC_IFETCH.html" target="right">L2_ISSUED_RECIRC_IFETCH</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/L2_ISSUED_RECIRC_OZQ_ACC.html" target="right">L2_ISSUED_RECIRC_OZQ_ACC</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l2_l3access_cancel.html" target="right">L2_L3ACCESS_CANCEL</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/l2_lines_allocated_(hardware-prefetched_only).html" target="right">L2_LINES_IN</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/l2_lines_evicted_(hardware-prefetched_only).html" target="right">L2_LINES_OUT</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/l2_m-state_lines_evicted_(hardware-prefetched_only).html" target="right">L2_M_LINES_OUT</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l2_miss_ratio.html" target="right">L2_MISS_RATIO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/L2_MISSES.html" target="right">L2_MISSES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/L2_OPS_ISSUED.html" target="right">L2_OPS_ISSUED</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l2_ozdb_full.html" target="right">L2_OZDB_FULL</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l2_ozq_acquire.html" target="right">L2_OZQ_ACQUIRE</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l2_ozq_cancels1.html" target="right">L2_OZQ_CANCELS1</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/L2_OZQ_CANCELS2.html" target="right">L2_OZQ_CANCELS2</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l2_ozq_full.html" target="right">L2_OZQ_FULL</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l2_ozq_release.html" target="right">L2_OZQ_RELEASE</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l2_recirc_attempts.html" target="right">L2_RECIRC_ATTEMPTS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/L2_REFERENCES.html" target="right">L2_REFERENCES</a>
<br><a class="clsTOCItem" href="PentiumM_HH/EventsB/l2_cache_request_misses_(highly_correlated%2c_hardware-prefetched_only).html" target="right">L2_REQUESTS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/L2_STORE_HIT_SHARED.html" target="right">L2_STORE_HIT_SHARED</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l2_synth_probe.html" target="right">L2_SYNTH_PROBE</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l2_victimb_full.html" target="right">L2_VICTIMB_FULL</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l2_wb_hits.html" target="right">L2_WB_HITS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l2_wb_misses.html" target="right">L2_WB_MISSES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l2_wb_references.html" target="right">L2_WB_REFERENCES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l2dtlb_miss_ratio.html" target="right">L2DTLB_MISS_RATIO0</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l2dtlb_miss_ratio1.html" target="right">L2DTLB_MISS_RATIO1</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/L2DTLB_MISSES.html" target="right">L2DTLB_MISSES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l3_data_hits.html" target="right">L3_DATA_HITS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l3_data_miss_ratio.html" target="right">L3_DATA_MISS_RATIO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l3_data_read_misses.html" target="right">L3_DATA_READ_MISSES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l3_data_read_ratio.html" target="right">L3_DATA_READ_RATIO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l3_data_read_references.html" target="right">L3_DATA_READ_REFERENCES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l3_inst_hits.html" target="right">L3_INST_HITS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l3_inst_miss_ratio.html" target="right">L3_INST_MISS_RATIO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l3_inst_misses.html" target="right">L3_INST_MISSES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l3_inst_ratio.html" target="right">L3_INST_RATIO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l3_inst_references.html" target="right">L3_INST_REFERENCES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/l3_lines_replaced.html" target="right">L3_LINES_REPLACED</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l3_miss_ratio.html" target="right">L3_MISS_RATIO</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/L3_MISSES.html" target="right">L3_MISSES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l3_read_hits.html" target="right">L3_READ_HITS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l3_read_misses.html" target="right">L3_READ_MISSES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l3_read_references.html" target="right">L3_READ_REFERENCES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/L3_READS.html" target="right">L3_READS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/L3_REFERENCES.html" target="right">L3_REFERENCES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l3_store_hits.html" target="right">L3_STORE_HITS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l3_store_misses.html" target="right">L3_STORE_MISSES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l3_store_references.html" target="right">L3_STORE_REFERENCES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l3_write_hits.html" target="right">L3_WRITE_HITS</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l3_write_misses.html" target="right">L3_WRITE_MISSES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/ER642/l3_write_references.html" target="right">L3_WRITE_REFERENCES</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/L3_WRITES.html" target="right">L3_WRITES</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Lips/lipslabel.html" target="right">標籤</a>
<br><a class="clsTOCItem" href="PentiumM_HH/LipsB/long_latency.html" target="right">延遲</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/LipsB/long_latency.html" target="right">長</a>
<br><a class="clsTOCItem" href="PentiumM_HH/LipsB/leave_instruction.html" target="right">leave</a>
<br><a class="clsTOCItem" href="PentiumM_HH/ERB/load_port_ratio.html" target="right">載入埠</a>
<br><a class="clsTOCItem" href="XScale_HH/LipsXSc/Load_Store_Multiple_of_n_Register.html" target="right">載入/儲存</a>
<br>    <a class="clsTOCItem" href="XScale_HH/LipsXSc/Load_Store_Multiple_of_n_Register.html" target="right">n 個</a>
<br>    <a class="clsTOCItem" href="XScale_HH/LipsXSc/Load_Operand_Penalty.html" target="right">運算元</a>
<br><a class="clsTOCItem" href="Itanium2_HH/Events642/loads_retired.html" target="right">LOADS_RETIRED</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Lips/LipsLongInst.html" target="right">長指令配對限制</a>
<br><a class="clsTOCItem" href="Pentium4_HH/Advice4_HH/Loop_Unrolling.html" target="right">循環展開</a>
<h2><a name=M></a>M</h2>
<a class="clsTOCItem" href="PentiumM_HH/EventsB/l2_m-state_lines_evicted_(excluding_hardware-prefetched).html" target="right">m 狀態</a>
<br>    <a class="clsTOCItem" href="PentiumM_HH/EventsB/l2_m-state_lines_evicted_(hardware-prefetched_only).html" target="right">英特爾(R) 奔騰(R) M 處理器事件</a>