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References

  1. Digital Design with an Introduction to the Verilog HDL, VHDL, and SystemVerilog, M.Morris Mano and Michael D. Ciletti, Pearson Education, 6th Edition, 2018.

  2. Synthesis and Optimization of Digital Circuits, Giovanni De Micheli, McGraw Hill Education; 1st Edition, 2017.

  3. Introduction to Logic and Computer Design, Alan B Marcovitz, McGraw-Hill Education, 2007.

  4. Stuck-at-fault

  5. Stuck at fault: fault model

This experiment is developed by Dr. Biswajith R. Bhowmik and his UG students: Nitin Chaudhary, Syed Abdul Gafoor, Vikas Keshavamurthy Bhat and Manojna K P Department of Computer Science and Engineering, National Institute of Technology Karnataka