From 3e909b635b207fd327191b728d15614fe09ffa7a Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Tue, 2 Apr 2024 10:19:16 +0100 Subject: [PATCH] Makefile.config: break cpufeatures into 1 line entries and sort them Signed-off-by: Colin Ian King --- Makefile.config | 155 +++++++++++++++++++++++++++++++++++++----------- 1 file changed, 122 insertions(+), 33 deletions(-) diff --git a/Makefile.config b/Makefile.config index ee0bda0a6..bd22f4681 100644 --- a/Makefile.config +++ b/Makefile.config @@ -1132,39 +1132,128 @@ XXHASH_H: .PHONY: cpufeatures cpufeatures: \ configdir \ - ALIGNED_64 ALIGNED_128 ALIGNED_64K ATTRIBUTE_ALWAYS_INLINE \ - ATTRIBUTE_FAST_MATH ATTRIBUTE_HOT ATTRIBUTE_NOINLINE \ - ATTRIBUTE_NORETURN ATTRIBUTE_PACKED ATTRIBUTE_PURE \ - ATTRIBUTE_WARN_UNUSED_RESULT ATTRIBUTE_WEAK \ - ASM_ALPHA_DRAINA ASM_ALPHA_HALT ASM_ARM_YIELD ASM_ARM_TLBI \ - ASM_HPPA_DIAG ASM_HPPA_RFI ASM_LOONG64_CPUCFG ASM_LOONG64_DBAR \ - ASM_LOONG64_RDTIME ASM_LOONG64_TLBRD ASM_LOONG64_TLBSRCH \ - ASM_M68K_EORI_SR ASM_MB ASM_MIPS_WAIT \ - ASM_NOP ASM_S390_PTLB ASM_SH4_RTE ASM_SH4_SLEEP ASM_SPARC_MEMBAR \ - ASM_SPARC_RDPR ASM_SPARC_TICK ASM_PPC64_DARN ASM_PPC64_DCBST \ - ASM_PPC64_DCBT ASM_PPC64_DCBTST ASM_PPC64_ICBI ASM_PPC64_MSYNC \ - ASM_PPC64_TLBIE ASM_RISCV_FENCE ASM_RISCV_FENCE_I ASM_RISCV_SFENCE_VMA \ - ASM_X86_CLDEMOTE ASM_X86_CLFLUSH ASM_X86_CLFLUSHOPT ASM_X86_CLWB \ - ASM_X86_CLTS ASM_X86_HLT ASM_X86_INVD ASM_X86_INVLPG ASM_X86_LFENCE \ - ASM_X86_LGDT ASM_X86_LLDT ASM_X86_LMSW ASM_X86_MFENCE ASM_X86_MOV_CR0 \ - ASM_X86_MOV_DR0 ASM_X86_PAUSE ASM_X86_PREFETCHT0 ASM_X86_PREFETCHT1 \ - ASM_X86_PREFETCHT2 ASM_X86_PREFETCHNTA ASM_X86_RDMSR ASM_X86_RDPMC \ - ASM_X86_RDRAND ASM_X86_RDSEED ASM_X86_RDTSC ASM_X86_RDTSCP \ - ASM_X86_REP_STOSB ASM_X86_REP_STOSW \ - ASM_X86_REP_STOSD ASM_X86_REP_STOSQ ASM_X86_SERIALIZE ASM_X86_SFENCE \ - ASM_X86_TPAUSE ASM_X86_WBINVD ASM_X86_WRMSR ASM_NOTHING \ - MM_ADD_EPI8 MM_DPBUSD_EPI32 MM_DPWSSD_EPI32 MM_LOADU_SI128 MM_STOREU_SI128 \ - MM256_ADD_EPI8 MM256_DPBUSD_EPI32 MM256_DPWSSD_EPI32 MM256_LOADU_SI256 MM256_STOREU_SI256 \ - MM512_ADD_EPI8 MM512_DPBUSD_EPI32 MM512_DPWSSD_EPI32 MM512_LOADU_SI512 MM512_STOREU_SI512 \ - PRAGMA PRAGMA_INSIDE PRAGMA_NO_HARD_DFP RESTRICT LABEL_AS_VALUE \ - TARGET_CLONES TARGET_CLONES_MMX \ - TARGET_CLONES_AVX TARGET_CLONES_AVX2 TARGET_CLONES_AVXVNNI TARGET_CLONES_SSE \ - TARGET_CLONES_SSE2 TARGET_CLONES_SSE3 TARGET_CLONES_SSSE3 \ - TARGET_CLONES_SSE4_1 TARGET_CLONES_SSE4_2 TARGET_CLONES_SKYLAKE_AVX512 \ - TARGET_CLONES_COOPERLAKE TARGET_CLONES_TIGERLAKE TARGET_CLONES_SAPPHIRERAPIDS \ - TARGET_CLONES_ALDERLAKE TARGET_CLONES_ROCKETLAKE TARGET_CLONES_GRANITERAPIDS \ - TARGET_CLONES_ARROWLAKE TARGET_CLONES_PANTHERLAKE \ - TARGET_CLONES_POWER9 VLA_ARG VECMATH + ALIGNED_128 \ + ALIGNED_64 \ + ALIGNED_64K \ + ASM_ALPHA_DRAINA \ + ASM_ALPHA_HALT \ + ASM_ARM_TLBI \ + ASM_ARM_YIELD \ + ASM_HPPA_DIAG \ + ASM_HPPA_RFI \ + ASM_LOONG64_CPUCFG \ + ASM_LOONG64_DBAR \ + ASM_LOONG64_RDTIME \ + ASM_LOONG64_TLBRD \ + ASM_LOONG64_TLBSRCH \ + ASM_M68K_EORI_SR \ + ASM_MB \ + ASM_MIPS_WAIT \ + ASM_NOP \ + ASM_NOTHING \ + ASM_PPC64_DARN \ + ASM_PPC64_DCBST \ + ASM_PPC64_DCBT \ + ASM_PPC64_DCBTST \ + ASM_PPC64_ICBI \ + ASM_PPC64_MSYNC \ + ASM_PPC64_TLBIE \ + ASM_RISCV_FENCE \ + ASM_RISCV_FENCE_I \ + ASM_RISCV_SFENCE_VMA \ + ASM_S390_PTLB \ + ASM_SH4_RTE \ + ASM_SH4_SLEEP \ + ASM_SPARC_MEMBAR \ + ASM_SPARC_RDPR \ + ASM_SPARC_TICK \ + ASM_X86_CLDEMOTE \ + ASM_X86_CLFLUSH \ + ASM_X86_CLFLUSHOPT \ + ASM_X86_CLTS \ + ASM_X86_CLWB \ + ASM_X86_HLT \ + ASM_X86_INVD \ + ASM_X86_INVLPG \ + ASM_X86_LFENCE \ + ASM_X86_LGDT \ + ASM_X86_LLDT \ + ASM_X86_LMSW \ + ASM_X86_MFENCE \ + ASM_X86_MOV_CR0 \ + ASM_X86_MOV_DR0 \ + ASM_X86_PAUSE \ + ASM_X86_PREFETCHNTA \ + ASM_X86_PREFETCHT0 \ + ASM_X86_PREFETCHT1 \ + ASM_X86_PREFETCHT2 \ + ASM_X86_RDMSR \ + ASM_X86_RDPMC \ + ASM_X86_RDRAND \ + ASM_X86_RDSEED \ + ASM_X86_RDTSC \ + ASM_X86_RDTSCP \ + ASM_X86_REP_STOSB \ + ASM_X86_REP_STOSD \ + ASM_X86_REP_STOSQ \ + ASM_X86_REP_STOSW \ + ASM_X86_SERIALIZE \ + ASM_X86_SFENCE \ + ASM_X86_TPAUSE \ + ASM_X86_WBINVD \ + ASM_X86_WRMSR \ + ATTRIBUTE_ALWAYS_INLINE \ + ATTRIBUTE_FAST_MATH \ + ATTRIBUTE_HOT \ + ATTRIBUTE_NOINLINE \ + ATTRIBUTE_NORETURN \ + ATTRIBUTE_PACKED \ + ATTRIBUTE_PURE \ + ATTRIBUTE_WARN_UNUSED_RESULT \ + ATTRIBUTE_WEAK \ + LABEL_AS_VALUE \ + MM256_ADD_EPI8 \ + MM256_DPBUSD_EPI32 \ + MM256_DPWSSD_EPI32 \ + MM256_LOADU_SI256 \ + MM256_STOREU_SI256 \ + MM512_ADD_EPI8 \ + MM512_DPBUSD_EPI32 \ + MM512_DPWSSD_EPI32 \ + MM512_LOADU_SI512 \ + MM512_STOREU_SI512 \ + MM_ADD_EPI8 \ + MM_DPBUSD_EPI32 \ + MM_DPWSSD_EPI32 \ + MM_LOADU_SI128 \ + MM_STOREU_SI128 \ + PRAGMA \ + PRAGMA_INSIDE \ + PRAGMA_NO_HARD_DFP \ + RESTRICT \ + TARGET_CLONES \ + TARGET_CLONES_ALDERLAKE \ + TARGET_CLONES_ARROWLAKE \ + TARGET_CLONES_AVX \ + TARGET_CLONES_AVX2 \ + TARGET_CLONES_AVXVNNI \ + TARGET_CLONES_COOPERLAKE \ + TARGET_CLONES_GRANITERAPIDS \ + TARGET_CLONES_MMX \ + TARGET_CLONES_PANTHERLAKE \ + TARGET_CLONES_POWER9 \ + TARGET_CLONES_ROCKETLAKE \ + TARGET_CLONES_SAPPHIRERAPIDS \ + TARGET_CLONES_SKYLAKE_AVX512 \ + TARGET_CLONES_SSE \ + TARGET_CLONES_SSE2 \ + TARGET_CLONES_SSE3 \ + TARGET_CLONES_SSE4_1 \ + TARGET_CLONES_SSE4_2 \ + TARGET_CLONES_SSSE3 \ + TARGET_CLONES_TIGERLAKE \ + VLA_ARG \ + VECMATH ALIGNED_64: $(call check,test-aligned-64,HAVE_ALIGNED_64,64 byte alignment attribute)