Create blank.yml

[ChristyRachel]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DflipflopIF is
Port ( D : in STD_LOGIC;
CLK : in STD_LOGIC;
QOUT : out STD_LOGIC);
end entity DflipflopIF;

architecture Exp of DflipflopIF is
begin

process (CLK)
begin
if (CLK = '1') then QOUT <= D;
end if;
end process;
end architecture Exp;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Dflipflop is
port ( D0 : in STD_LOGIC;
CLK : in STD_LOGIC;
OUT1 : out STD_LOGIC);
end entity Dflipflop;

architecture Expression of Dflipflop is

component DflipflopIF is
port ( D,CLK : in STD_LOGIC; QOUT : out STD_LOGIC);
end component DflipflopIF;

signal Q0,Q1 : STD_LOGIC;
begin

F1 : DflipflopIF port map(D=>D0,CLK=>CLK,QOUT=>Q0);
F2 : DflipflopIF port map(D=>Q0,CLK=>CLK,QOUT=>Q1);
F3 : DflipflopIF port map(D=>Q1,CLK=>CLK,QOUT=>OUT1);

end architecture Expression;