diff --git a/badger/tests/sp605/spartan6_clocks.v b/badger/tests/sp605/spartan6_clocks.v index 491da65be..e8223f286 100644 --- a/badger/tests/sp605/spartan6_clocks.v +++ b/badger/tests/sp605/spartan6_clocks.v @@ -93,8 +93,7 @@ PLL_ADV #( .CLKOUT2_DIVIDE(plladv_mult), .CLKOUT2_DUTY_CYCLE(0.5), .CLKOUT2_PHASE( 0.0), // 200 MHz .REF_JITTER(0.005), .COMPENSATION("SYSTEM_SYNCHRONOUS") -) -PLL_ADV_inst ( +) PLL_ADV_inst ( .CLKINSEL(1'b1), .CLKIN1(sysclk_buf), .CLKOUT0(clk_1x_buf), // 62.5 MHz, 90 degree diff --git a/badger/tests/spi_test.py b/badger/tests/spi_test.py index c3fd7199e..5532e8ccc 100755 --- a/badger/tests/spi_test.py +++ b/badger/tests/spi_test.py @@ -428,12 +428,14 @@ def remote_program(s, file_name, ad, size): f = open(file_name, 'rb') # assume that '.bin' file size is always less than whole pages for ba in reversed(range(start_p, stop_p)): - print("block %d" % ba) + print("block %d\r" % ba, end='', flush=True) f.seek((ba << 8) - ad) bd = f.read(PAGE) while not (write_enable(s, True)): time.sleep(WAIT) page_program(s, ba << 8, bd) + else: + print('') f.close() return diff --git a/board_support/ac701/base.xdc b/board_support/ac701/base.xdc index 6d697fe38..1e44bc246 100644 --- a/board_support/ac701/base.xdc +++ b/board_support/ac701/base.xdc @@ -15,7 +15,5 @@ set_property -dict "PACKAGE_PIN T24 IOSTANDARD LVCMOS33" [get_ports {LED[1]}] set_property -dict "PACKAGE_PIN T25 IOSTANDARD LVCMOS33" [get_ports {LED[2]}] set_property -dict "PACKAGE_PIN R26 IOSTANDARD LVCMOS33" [get_ports {LED[3]}] -set_property -dict "PACKAGE_PIN U4 IOSTANDARD LVCMOS15" [get_ports {RESET}] - # UG471 page 50 -set_property INTERNAL_VREF 0.90 [get_banks BANK13] +set_property INTERNAL_VREF 0.90 [get_iobanks 13] diff --git a/dsp/chirp/ramps.v b/dsp/chirp/ramps.v index 2f651b4a5..1f118f6bd 100644 --- a/dsp/chirp/ramps.v +++ b/dsp/chirp/ramps.v @@ -52,8 +52,8 @@ always @(posedge clk) begin amp_nonzero <= |amp_r; if (gate) amp_r <= amp_railed ? amp_flat : amp_step; // amplitude needs to be back to zero when next reset hits - // for robustness to incorrect parameters, force it low - if (reset) amp_r <= 0; + // for robustness to incorrect parameters, force it low + if (reset) amp_r <= 0; a_warning_r <= reset & amp_nonzero; end assign amp = amp_r; diff --git a/dsp/cic_wave_recorder_tb.v b/dsp/cic_wave_recorder_tb.v index 0783ddc74..ae436620e 100644 --- a/dsp/cic_wave_recorder_tb.v +++ b/dsp/cic_wave_recorder_tb.v @@ -184,9 +184,7 @@ module cic_wave_recorder_tb; .lsb_mask (1), .buf_stat_w (16), .buf_auto_flip (1) - ) - dut - ( + ) dut ( .iclk (iclk), .reset (reset), .stb_in (ext_trig), diff --git a/dsp/demand_gpt.v b/dsp/demand_gpt.v index 65e31626c..3adc307d1 100644 --- a/dsp/demand_gpt.v +++ b/dsp/demand_gpt.v @@ -15,7 +15,7 @@ reg gate_check=0; reg [8:0] count=0; // XXX generous, but not general always @(posedge clk) begin - gate_check <= gate; + gate_check <= gate; count <= count + gate; if (trig && gate_check) begin time_err_r <= (count+gate) != gpt; diff --git a/dsp/digaree/user_tb.v b/dsp/digaree/user_tb.v index 5c7b19dd2..c2df92fbc 100644 --- a/dsp/digaree/user_tb.v +++ b/dsp/digaree/user_tb.v @@ -94,7 +94,7 @@ always @(posedge sf_clk) begin if (trig_done && conveyor_cnt < data_len) begin meas <= conveyor[conveyor_cnt]; - conveyor_cnt <= conveyor_cnt + 1; + conveyor_cnt <= conveyor_cnt + 1; end end diff --git a/dsp/fchan_subset.v b/dsp/fchan_subset.v index 80b26f7a7..b24b0d0ec 100644 --- a/dsp/fchan_subset.v +++ b/dsp/fchan_subset.v @@ -31,7 +31,7 @@ generate for (ix=0; ix>> 1) + intg; // Integrator + sum <= xmr + ymr; + sum1 <= sum; + sum_f <= sum1 + sum; // 2-tap filter [1, 1] + if (reset) intg <= 0; + else intg <= (sum_f >>> 1) + intg; // Integrator end assign sum_filt = sum_f; assign z = intg[dwi+intg_scale:intg_scale-1]; diff --git a/dsp/iq_deinterleaver_multichannel.v b/dsp/iq_deinterleaver_multichannel.v index 289a053cb..ff988d2a4 100644 --- a/dsp/iq_deinterleaver_multichannel.v +++ b/dsp/iq_deinterleaver_multichannel.v @@ -29,9 +29,7 @@ module iq_deinterleaver_multichannel #( .scale_wi (SCALE_WI), .dwi (DWI), .davr (DAVR) - ) - i_iq_deinterleaver - ( + ) i_iq_deinterleaver ( .clk (clk), .scale_in (scale_in), .iq_data_in (iq_data_in[(ch_id+1)*DWI-1:ch_id*DWI]), diff --git a/dsp/iq_mixer_multichannel.v b/dsp/iq_mixer_multichannel.v index b4400e63f..579253493 100644 --- a/dsp/iq_mixer_multichannel.v +++ b/dsp/iq_mixer_multichannel.v @@ -30,9 +30,7 @@ module iq_mixer_multichannel #( .dwi (DWI), .davr (DAVR), .dwlo (DWLO) - ) - i_mixer_cos - ( + ) i_mixer_cos ( .clk (clk), .adcf (adc[(ch_id+1)*DWI-1: ch_id*DWI]), .mult (cos), @@ -44,9 +42,7 @@ module iq_mixer_multichannel #( .dwi (DWI), .davr (DAVR), .dwlo (DWLO) - ) - i_mixer_sin - ( + ) i_mixer_sin ( .clk (clk), .adcf (adc[(ch_id+1)*DWI-1: ch_id*DWI]), .mult (sin), diff --git a/fpga_family/mgt/gtp_common_2_50.tcl b/fpga_family/mgt/gtp_common_2_50.tcl new file mode 100644 index 000000000..5e1604eae --- /dev/null +++ b/fpga_family/mgt/gtp_common_2_50.tcl @@ -0,0 +1,52 @@ +set cfg_dict { + CONFIG.identical_val_tx_line_rate {2.50} + CONFIG.gt0_val {true} + CONFIG.gt0_val_drp_clock {50} + CONFIG.gt0_val_rx_refclk {REFCLK0_Q0} + CONFIG.gt0_val_tx_refclk {REFCLK0_Q0} + CONFIG.gt0_val_txbuf_en {true} + CONFIG.gt0_val_rxbuf_en {true} + CONFIG.gt0_val_port_rxslide {false} + CONFIG.gt0_usesharedlogic {0} + CONFIG.identical_val_rx_line_rate {2.50} + CONFIG.gt_val_tx_pll {PLL0} + CONFIG.gt_val_rx_pll {PLL1} + CONFIG.identical_val_tx_reference_clock {125.000} + CONFIG.identical_val_rx_reference_clock {125.000} + CONFIG.gt0_val_tx_line_rate {2.50} + CONFIG.gt0_val_tx_data_width {20} + CONFIG.gt0_val_tx_int_datawidth {20} + CONFIG.gt0_val_tx_reference_clock {125.000} + CONFIG.gt0_val_rx_line_rate {2.50} + CONFIG.gt0_val_rx_data_width {20} + CONFIG.gt0_val_rx_int_datawidth {20} + CONFIG.gt0_val_rx_reference_clock {125.000} + CONFIG.gt0_val_cpll_fbdiv {4} + CONFIG.gt0_val_cpll_rxout_div {4} + CONFIG.gt0_val_cpll_txout_div {4} + CONFIG.gt0_val_tx_buffer_bypass_mode {Auto} + CONFIG.gt0_val_txoutclk_source {false} + CONFIG.gt0_val_rx_buffer_bypass_mode {Auto} + CONFIG.gt0_val_rxusrclk {RXOUTCLK} + CONFIG.gt0_val_rxslide_mode {OFF} + CONFIG.gt0_val_port_txbufstatus {true} + CONFIG.gt0_val_port_rxbufstatus {true} + CONFIG.gt0_val_port_rxpmareset {true} + CONFIG.gt0_val_align_mcomma_det {true} + CONFIG.gt0_val_align_pcomma_det {true} + CONFIG.gt0_val_comma_preset {User_defined} + CONFIG.gt0_val_align_pcomma_value {1111110000} + CONFIG.gt0_val_align_mcomma_value {0011001111} + CONFIG.gt0_val_align_comma_enable {1111111111} + CONFIG.gt0_val_align_comma_double {true} + CONFIG.gt0_val_align_comma_word {Two_Byte_Boundaries} + CONFIG.gt0_val_port_rxpcommaalignen {false} + CONFIG.gt0_val_port_rxmcommaalignen {false} + CONFIG.gt0_val_dfe_mode {LPM-Auto} + CONFIG.gt0_val_rx_termination_voltage {Programmable} + CONFIG.gt0_val_rx_cm_trim {800} + CONFIG.gt0_val_port_rxdfereset {true} + CONFIG.gt0_val_pd_trans_time_to_p2 {100} + CONFIG.gt0_val_pd_trans_time_from_p2 {60} + CONFIG.gt0_val_pd_trans_time_non_p2 {25} +} diff --git a/fpga_family/mgt/gtp_ethernet_2_50.tcl b/fpga_family/mgt/gtp_ethernet_2_50.tcl new file mode 100644 index 000000000..a44f0dcab --- /dev/null +++ b/fpga_family/mgt/gtp_ethernet_2_50.tcl @@ -0,0 +1,52 @@ +set cfg_dict { + CONFIG.identical_val_tx_line_rate {2.50} + CONFIG.gt0_val {true} + CONFIG.gt0_val_drp_clock {50} + CONFIG.gt0_val_rx_refclk {REFCLK0_Q0} + CONFIG.gt0_val_tx_refclk {REFCLK0_Q0} + CONFIG.gt0_val_txbuf_en {true} + CONFIG.gt0_val_rxbuf_en {true} + CONFIG.gt0_val_port_rxslide {false} + CONFIG.gt0_usesharedlogic {0} + CONFIG.identical_val_rx_line_rate {2.50} + CONFIG.gt_val_tx_pll {PLL0} + CONFIG.gt_val_rx_pll {PLL0} + CONFIG.identical_val_tx_reference_clock {125.000} + CONFIG.identical_val_rx_reference_clock {125.000} + CONFIG.gt0_val_tx_line_rate {2.50} + CONFIG.gt0_val_tx_data_width {20} + CONFIG.gt0_val_tx_int_datawidth {20} + CONFIG.gt0_val_tx_reference_clock {125.000} + CONFIG.gt0_val_rx_line_rate {2.50} + CONFIG.gt0_val_rx_data_width {20} + CONFIG.gt0_val_rx_int_datawidth {20} + CONFIG.gt0_val_rx_reference_clock {125.000} + CONFIG.gt0_val_cpll_fbdiv {4} + CONFIG.gt0_val_cpll_rxout_div {4} + CONFIG.gt0_val_cpll_txout_div {4} + CONFIG.gt0_val_tx_buffer_bypass_mode {Auto} + CONFIG.gt0_val_txoutclk_source {false} + CONFIG.gt0_val_rx_buffer_bypass_mode {Auto} + CONFIG.gt0_val_rxusrclk {RXOUTCLK} + CONFIG.gt0_val_rxslide_mode {OFF} + CONFIG.gt0_val_port_txbufstatus {true} + CONFIG.gt0_val_port_rxbufstatus {true} + CONFIG.gt0_val_port_rxpmareset {true} + CONFIG.gt0_val_align_mcomma_det {true} + CONFIG.gt0_val_align_pcomma_det {true} + CONFIG.gt0_val_comma_preset {User_defined} + CONFIG.gt0_val_align_pcomma_value {1111110000} + CONFIG.gt0_val_align_mcomma_value {0011001111} + CONFIG.gt0_val_align_comma_enable {1111111111} + CONFIG.gt0_val_align_comma_double {true} + CONFIG.gt0_val_align_comma_word {Two_Byte_Boundaries} + CONFIG.gt0_val_port_rxpcommaalignen {false} + CONFIG.gt0_val_port_rxmcommaalignen {false} + CONFIG.gt0_val_dfe_mode {LPM-Auto} + CONFIG.gt0_val_rx_termination_voltage {Programmable} + CONFIG.gt0_val_rx_cm_trim {800} + CONFIG.gt0_val_port_rxdfereset {true} + CONFIG.gt0_val_pd_trans_time_to_p2 {100} + CONFIG.gt0_val_pd_trans_time_from_p2 {60} + CONFIG.gt0_val_pd_trans_time_non_p2 {25} +} diff --git a/fpga_family/spartan6/spartan6_clocks.v b/fpga_family/spartan6/spartan6_clocks.v index 161733ab5..e8223f286 100644 --- a/fpga_family/spartan6/spartan6_clocks.v +++ b/fpga_family/spartan6/spartan6_clocks.v @@ -82,6 +82,7 @@ DCM_SP #( BUFG bufg125_tx(.I(xclk125_buf), .O(clk_eth)); PLL_ADV #( + .SIM_DEVICE("SPARTAN6"), .BANDWIDTH("OPTIMIZED"), .CLKIN1_PERIOD(clkin_period), .CLKFBOUT_MULT(plladv_mult), // 200x5=1000 @@ -92,8 +93,7 @@ PLL_ADV #( .CLKOUT2_DIVIDE(plladv_mult), .CLKOUT2_DUTY_CYCLE(0.5), .CLKOUT2_PHASE( 0.0), // 200 MHz .REF_JITTER(0.005), .COMPENSATION("SYSTEM_SYNCHRONOUS") -) -PLL_ADV_inst ( +) PLL_ADV_inst ( .CLKINSEL(1'b1), .CLKIN1(sysclk_buf), .CLKOUT0(clk_1x_buf), // 62.5 MHz, 90 degree diff --git a/fpga_family/xilinx/xadc_tempvoltmon.v b/fpga_family/xilinx/xadc_tempvoltmon.v index a9d43b441..8a8d43a1f 100644 --- a/fpga_family/xilinx/xadc_tempvoltmon.v +++ b/fpga_family/xilinx/xadc_tempvoltmon.v @@ -168,8 +168,7 @@ module xadc_tempvoltmon #( // Simulation attributes: Set for proper simulation behavior .SIM_DEVICE("7SERIES"), // Select target device (values) .SIM_MONITOR_FILE("design.txt") // Analog simulation data file name - ) - XADC_inst ( + ) XADC_inst ( // ALARMS: 8-bit (each) output: ALM, OT .ALM(alm), // 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram .OT(otemp), // 1-bit output: Over-Temperature alarm diff --git a/localbus/jit_rad_gateway_tb.v b/localbus/jit_rad_gateway_tb.v index c21be8cec..6d71cbb51 100644 --- a/localbus/jit_rad_gateway_tb.v +++ b/localbus/jit_rad_gateway_tb.v @@ -6,14 +6,14 @@ reg lb_clk=0; integer cc; reg fail=0; initial begin - if ($test$plusargs("vcd")) begin - $dumpfile("jit_rad_gateway.vcd"); - $dumpvars(5, jit_rad_gateway_tb); - end - for (cc=0; cc<2000; cc=cc+1) begin - #10; lb_clk=1; - #10; lb_clk=0; - end + if ($test$plusargs("vcd")) begin + $dumpfile("jit_rad_gateway.vcd"); + $dumpvars(5, jit_rad_gateway_tb); + end + for (cc=0; cc<2000; cc=cc+1) begin + #10; lb_clk=1; + #10; lb_clk=0; + end $display("%s", fail ? "FAIL" : "PASS"); if (fail) $stop(0); $finish(0); diff --git a/peripheral_drivers/strobe_gen.v b/peripheral_drivers/strobe_gen.v index eb934a050..6b30c43e1 100644 --- a/peripheral_drivers/strobe_gen.v +++ b/peripheral_drivers/strobe_gen.v @@ -2,11 +2,10 @@ module strobe_gen #( parameter TYPE="RISE_EDGE" -) -( - input I_clk, - input I_signal, - output O_strobe +) ( + input I_clk, + input I_signal, + output O_strobe ); reg [1:0] sig_r; generate @@ -19,7 +18,7 @@ else endgenerate always @(posedge I_clk) begin - sig_r<={sig_r[0],I_signal}; + sig_r<={sig_r[0],I_signal}; end assign O_strobe=(sig_r==2'b01); diff --git a/projects/cmoc_top/bmb7_cu/clocks.v b/projects/cmoc_top/bmb7_cu/clocks.v index cfe507d25..3d7cbc859 100644 --- a/projects/cmoc_top/bmb7_cu/clocks.v +++ b/projects/cmoc_top/bmb7_cu/clocks.v @@ -42,8 +42,7 @@ PLLE2_BASE #( .CLKOUT1_DIVIDE(pll_div), .CLKOUT1_DUTY_CYCLE(0.5), .CLKOUT1_PHASE(90.0), // 125 MHz .REF_JITTER1(0.0), .STARTUP_WAIT("FALSE") -) -PLLE2_BASE_inst ( +) PLLE2_BASE_inst ( .CLKIN1(sysclk_buf), .CLKOUT0(pll_clk_0), // 125 MHz, 0 degree .CLKOUT1(pll_clk_90), // 125 MHz, 90 degree diff --git a/projects/comms_top/gige_eth/Makefile b/projects/comms_top/gige_eth/Makefile index f49bab27c..bd8c5a312 100644 --- a/projects/comms_top/gige_eth/Makefile +++ b/projects/comms_top/gige_eth/Makefile @@ -17,7 +17,7 @@ VERILOG_DEFINE_FLAGS = include $(COMMS_TOP_DIR)/rules.mk include $(BUILD_DIR)/top_rules.mk -all: gen $(APP_NAME).bit +all: $(APP_NAME).bit $(APP_NAME).bit: $(IP_TCL) @@ -35,5 +35,5 @@ ifneq (,$(findstring bit,$(MAKECMDGOALS))) endif endif -CLEAN += *.bit ../test/*.dat +CLEAN += *.bit *.bin ../test/*.dat include $(BUILD_DIR)/bottom_rules.mk diff --git a/projects/comms_top/gige_eth/gige_top.v b/projects/comms_top/gige_eth/gige_top.v index 9df12e5e4..d90114de5 100644 --- a/projects/comms_top/gige_eth/gige_top.v +++ b/projects/comms_top/gige_eth/gige_top.v @@ -29,6 +29,7 @@ module gige_top ( localparam IPADDR = {8'd192, 8'd168, 8'd1, 8'd179}; localparam MACADDR = 48'h00105ad155b5; + localparam DOUBLEBIT = 0; // XXX DOUBLEBIT = 1 fails hardware test `define AC701 `ifdef AC701 @@ -58,6 +59,7 @@ module gige_top ( gtp_sys_clk_mmcm i_gtp_sys_clk_mmcm ( .clk_in (sys_clk_fast), .sys_clk (sys_clk), // Buffered 50 MHz + .reset (1'b0), .locked () ); `else @@ -87,21 +89,31 @@ module gige_top ( // Route 62.5 MHz TXOUTCLK through clock manager to generate 125 MHz clock // Ethernet clock managers + wire gmii_tx_clk_half; mgt_eth_clks i_gt_eth_clks_tx ( .reset (~gt_cpll_locked[0]), .mgt_out_clk (gt0_tx_out_clk), // From transceiver - .mgt_usr_clk (gt0_tx_usr_clk), // Buffered 62.5 MHz + .mgt_usr_clk (gmii_tx_clk_half), // Buffered 62.5 MHz .gmii_clk (gmii_tx_clk), // Buffered 125 MHz .pll_lock (tx0_pll_lock) ); + wire gmii_rx_clk_half; mgt_eth_clks i_gt_eth_clks_rx ( .reset (~gt_cpll_locked[0]), .mgt_out_clk (gt0_rx_out_clk), // From transceiver - .mgt_usr_clk (gt0_rx_usr_clk), + .mgt_usr_clk (gmii_rx_clk_half), .gmii_clk (gmii_rx_clk), .pll_lock (rx0_pll_lock) ); + // two cases: gt0_*_out_clk = 125 MHz or 62.5 MHz + generate if (DOUBLEBIT) begin : G_DOUBLEBIT + assign gt0_tx_usr_clk = gmii_tx_clk; + assign gt0_rx_usr_clk = gmii_rx_clk; + end else begin: G_SLOW + assign gt0_tx_usr_clk = gmii_tx_clk_half; + assign gt0_rx_usr_clk = gmii_rx_clk_half; + end endgenerate // ---------------------------------- // GTP Instantiation @@ -167,9 +179,10 @@ module gige_top ( eth_gtx_bridge #( .IP (IPADDR), .MAC (MACADDR), - .GTX_DW (GTX_ETH_WIDTH)) + .GTX_DW (GTX_ETH_WIDTH), + .DOUBLEBIT (DOUBLEBIT)) i_eth_gtx_bridge ( - .gtx_tx_clk (gt0_tx_usr_clk), // Transceiver clock at half rate + .gtx_tx_clk (gt0_tx_usr_clk), // Transceiver clock, sometimes at half rate .gmii_tx_clk (gmii_tx_clk), // Clock for Ethernet fabric - 125 MHz for 1GbE .gmii_rx_clk (gmii_rx_clk), .gtx_rxd (gt0_rxd), diff --git a/projects/comms_top/gige_eth/gtp_gige_top.tcl b/projects/comms_top/gige_eth/gtp_gige_top.tcl index a03869fb2..53e306ba9 100644 --- a/projects/comms_top/gige_eth/gtp_gige_top.tcl +++ b/projects/comms_top/gige_eth/gtp_gige_top.tcl @@ -17,7 +17,10 @@ source $MGT_CONFIG_DIR/mgt_gen.tcl set quad 0 set pll0_refclk "REFCLK0" set pll1_refclk "REFCLK0" +# Stupid but working with 62.5 MHz clk: add_gtcommon $MGT_CONFIG_DIR/gtp_common_1_25.tcl $quad $pll0_refclk $pll1_refclk +# for DOUBLEBIT experiments: +# add_gtcommon $MGT_CONFIG_DIR/gtp_common_2_50.tcl $quad $pll0_refclk $pll1_refclk # proc add_gt_protocol {gt_type config_file quad_num gt_num en8b10b pll_type} @@ -28,7 +31,10 @@ set gt 0 set en8b10b 0 set endrp 0 set pll_type "PLL0" +# Stupid but working with 62.5 MHz clk: add_gt_protocol $gt_type $MGT_CONFIG_DIR/gtp_ethernet.tcl $quad $gt $en8b10b $endrp $pll_type +# for DOUBLEBIT experiments: +# add_gt_protocol $gt_type $MGT_CONFIG_DIR/gtp_ethernet_2_50.tcl $quad $gt $en8b10b $endrp $pll_type # proc add_aux_ip {ipname config_file module_name} add_aux_ip clk_wiz $MGT_CONFIG_DIR/mgt_eth_clk.tcl mgt_eth_mmcm diff --git a/projects/test_marble_family/first_readout.sh b/projects/test_marble_family/first_readout.sh index bf607bf9f..1a85dd1d8 100644 --- a/projects/test_marble_family/first_readout.sh +++ b/projects/test_marble_family/first_readout.sh @@ -10,7 +10,7 @@ python3 -m xadctemp -a $IP -p 803 echo "Reading kintex 7 DNA for $IP" python3 -m leep.cli leep://$IP:803 reg dna_high dna_low echo "Connect Digilent 8 LED board to Pmod J12 and check if all them blink at different rate" -python3 -m leep.cli leep://$IP:803 reg led_user_mode=2 +python3 -m leep.cli leep://$IP:803 reg led_user_mode=2 misc_config=132 tt=$(mktemp /tmp/quick_XXXXXX) python3 -m spi_test --ip $IP --udp 804 --otp --pages=1 --dump $tt hexdump $tt | head -n 2 diff --git a/projects/test_marble_family/marble_top.v b/projects/test_marble_family/marble_top.v index 951958da9..5ee3b864c 100644 --- a/projects/test_marble_family/marble_top.v +++ b/projects/test_marble_family/marble_top.v @@ -359,7 +359,9 @@ marble_base #( // Unsupported: defparam with more than one dot defparam base.rtefi.p4_client.engine.seven = 1; `endif -assign Pmod1 = leds; +// Let Pmod float by default for golden bitfile use-case +wire enable_pmod_out = ext_config[3]; +assign Pmod1 = enable_pmod_out ? leds : 8'bzzzzzzzz; assign LD16 = leds[0]; assign LD17 = leds[1]; diff --git a/projects/test_marble_family/static_regmap.json b/projects/test_marble_family/static_regmap.json index 4f5cdaf01..7720610ad 100644 --- a/projects/test_marble_family/static_regmap.json +++ b/projects/test_marble_family/static_regmap.json @@ -39,7 +39,7 @@ "addr_width": 0, "sign": "unsigned", "base_addr": 327688, - "data_width": 3 + "data_width": 8 }, "wr_dac": { "access": "rw", diff --git a/projects/test_marble_family/xadc_tempmon.v b/projects/test_marble_family/xadc_tempmon.v index 95cc5da56..1630bd621 100644 --- a/projects/test_marble_family/xadc_tempmon.v +++ b/projects/test_marble_family/xadc_tempmon.v @@ -124,8 +124,7 @@ module xadc_tempmon #( // Simulation attributes: Set for proper simulation behavior .SIM_DEVICE("7SERIES"), // Select target device (values) .SIM_MONITOR_FILE("design.txt") // Analog simulation data file name - ) - XADC_inst ( + ) XADC_inst ( // ALARMS: 8-bit (each) output: ALM, OT .ALM(alm), // 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram .OT(otemp), // 1-bit output: Over-Temperature alarm diff --git a/rtsim/afilter_siso_tb.v b/rtsim/afilter_siso_tb.v index c3a0b88ae..4b69a2365 100644 --- a/rtsim/afilter_siso_tb.v +++ b/rtsim/afilter_siso_tb.v @@ -13,15 +13,15 @@ integer cc; `ifdef SIMULATE initial begin if ($test$plusargs("vcd")) begin - $dumpfile("afilter_siso.vcd"); - $dumpvars(5, afilter_siso_tb); - end - for (cc=0; cc<400; cc=cc+1) begin - clk=0; #4; - clk=1; #4; - end - $display("WARNING: Not a self-checking testbench. Will always PASS. Relies on external post-processing."); - $display("PASS"); + $dumpfile("afilter_siso.vcd"); + $dumpvars(5, afilter_siso_tb); + end + for (cc=0; cc<400; cc=cc+1) begin + clk=0; #4; + clk=1; #4; + end + $display("WARNING: Not a self-checking testbench. Will always PASS. Relies on external post-processing."); + $display("PASS"); end `endif // `ifdef SIMULATE diff --git a/serial_io/dec_8b10b.v b/serial_io/dec_8b10b.v index 59f90c2f1..6f61ccd8b 100644 --- a/serial_io/dec_8b10b.v +++ b/serial_io/dec_8b10b.v @@ -43,8 +43,8 @@ module dec_8b10b (datain, dispin, dataout, dispout, code_err, disp_err) ; wire p04 = !ai & !bi & !ci & !di ; wire disp6a = p31 | (p22 & dispin) ; // pos disp if p22 and was pos, or p31. - wire disp6a2 = p31 & dispin ; // disp is ++ after 4 bits - wire disp6a0 = p13 & ! dispin ; // -- disp after 4 bits + wire disp6a2 = p31 & dispin ; // disp is ++ after 4 bits + wire disp6a0 = p13 & ! dispin ; // -- disp after 4 bits wire disp6b = (((ei & ii & ! disp6a0) | (disp6a & (ei | ii)) | disp6a2 | (ei & ii & di)) & (ei | ii | di)) ; @@ -153,7 +153,7 @@ module dec_8b10b (datain, dispin, dataout, dispout, code_err, disp_err) ; assign dataout = {xko, xho, xgo, xfo, xeo, xdo, xco, xbo, xao} ; // my disp err fires for any legal codes that violate disparity, may fire for illegal codes - assign disp_err = ((dispin & disp6p) | (disp6n & !dispin) | + assign disp_err = ((dispin & disp6p) | (disp6n & !dispin) | (dispin & !disp6n & fi & gi) | (dispin & ai & bi & ci) | (dispin & !disp6n & disp4p) | diff --git a/serial_io/enc_8b10b.v b/serial_io/enc_8b10b.v index ad820d722..8915ccf82 100644 --- a/serial_io/enc_8b10b.v +++ b/serial_io/enc_8b10b.v @@ -92,8 +92,8 @@ module enc_8b10b (datain, dispin, dataout, dispout) ; // K29 is 11101 // K30 is 11110 - so K23/27/29/30 are ei & l31 wire illegalk = ki & - (ai | bi | !ci | !di | !ei) & // not K28.0->7 - (!fi | !gi | !hi | !ei | !l31) ; // not K23/27/29/30.7 + (ai | bi | !ci | !di | !ei) & // not K28.0->7 + (!fi | !gi | !hi | !ei | !l31) ; // not K23/27/29/30.7 // now determine whether to do the complementing // complement if prev disp is - and pd1s6 is set, or + and nd1s6 is set diff --git a/serial_io/eth_gtx_bridge.v b/serial_io/eth_gtx_bridge.v index 981d85faf..dbf08100d 100644 --- a/serial_io/eth_gtx_bridge.v +++ b/serial_io/eth_gtx_bridge.v @@ -3,7 +3,7 @@ // ------------------------------------ // eth_gtx_bridge.v // -// DEPRECATED +// DEPRECATED (but still used in projects/comms_top!) // Wrapper around rtefi_blob and eth_gtx_hook with a TX/RX path width conversion for GTX compatibility // Note that this module "just" instantiates two others: // eth_gtx_hook and rtefi_blob. @@ -18,10 +18,11 @@ module eth_gtx_bridge #( parameter IP = {8'd192, 8'd168, 8'd7, 8'd4}, parameter MAC = 48'h112233445566, - parameter JUMBO_DW = 14, // Not used, just holdover for compatibility with older eth_gtx_bridge - parameter GTX_DW = 20) // Parallel GTX data width; Supported values are 10b and 20b + parameter JUMBO_DW = 14, // Not used, just holdover for compatibility with older eth_gtx_bridge + parameter GTX_DW = 20, // Parallel GTX data width; Supported values are 10b and 20b + parameter DOUBLEBIT = 0) // Experimental ( - input gtx_tx_clk, // Transceiver clock at half rate + input gtx_tx_clk, // Transceiver clock, sometimes at half rate input gmii_tx_clk, // Clock for Ethernet fabric - 125 MHz for 1GbE input gmii_rx_clk, input [GTX_DW-1:0] gtx_rxd, @@ -60,7 +61,7 @@ module eth_gtx_bridge #( wire [7:0] gmii_rxd, gmii_txd; wire gmii_tx_en, gmii_rx_dv; - eth_gtx_hook #(.JUMBO_DW(14), .GTX_DW(20)) hook( + eth_gtx_hook #(.JUMBO_DW(14), .GTX_DW(GTX_DW), .DOUBLEBIT(DOUBLEBIT)) hook( .gtx_tx_clk (gtx_tx_clk), .gmii_tx_clk (gmii_tx_clk), .gmii_rx_clk (gmii_rx_clk), diff --git a/serial_io/eth_gtx_hook.v b/serial_io/eth_gtx_hook.v index 2e8c25e67..531d49e34 100644 --- a/serial_io/eth_gtx_hook.v +++ b/serial_io/eth_gtx_hook.v @@ -3,14 +3,20 @@ // ------------------------------------ // eth_gtx_hook.v // ------------------------------------ +// Converts between an internal/virtual GMII Ethernet port (8-bit, 125 MHz) +// and the user pins of an on-chip serdes +// GTX_DW = 10 : 125 MHz serdes clk for Spartan-6 LXT +// GTX_DW = 20 DOUBLEBIT = 0 : 62.5 MHz serdes clk for Xilinx 7-series +// GTX_DW = 20 DOUBLEBIT = 1 : 125 MHz serdes clk for Xilinx 7-series (experimental) module eth_gtx_hook #( - parameter JUMBO_DW = 14, // Not used, just holdover for compatibility with older eth_gtx_bridge + parameter JUMBO_DW = 14, // Not used, just holdover for compatibility with older eth_gtx_bridge parameter EVENINIT = 0, parameter ENC_DISPINIT=1'b0, - parameter GTX_DW = 20) // Parallel GTX data width; Supported values are 10b and 20b + parameter GTX_DW = 20, // Parallel GTX data width; Supported values are 10b and 20b + parameter DOUBLEBIT = 0) // Experimental ( - input gtx_tx_clk, // Transceiver clock at half rate + input gtx_tx_clk, // Transceiver clock, sometimes at half rate input gmii_tx_clk, // Clock for Ethernet fabric - 125 MHz for 1GbE input gmii_rx_clk, input [GTX_DW-1:0] gtx_rxd, @@ -29,20 +35,44 @@ module eth_gtx_hook #( ); - wire [9:0] gtx_txd_10; + wire [9:0] gtx_txd_10; // driven by i_gmii_link + wire [9:0] gtx_rxd_10; // input to i_gmii_link // ---------------------------------- // Data width and rate conversion // --------------------------------- - wire [9:0] gtx_rxd_10; - - generate if (GTX_DW==20) begin: G_GTX_DATA_CONV - + generate if ((GTX_DW==20) && DOUBLEBIT) begin: G_GTX_DOUBLEBIT_CONV + + // gmii and gtx clocks are considered the same in this stanza + // One could also write this bit rearrangement with a generate loop, + // but I don't mind being explicit about it. + assign gtx_txd = { + gtx_txd_10[9], gtx_txd_10[9], gtx_txd_10[8], gtx_txd_10[8], + gtx_txd_10[7], gtx_txd_10[7], gtx_txd_10[6], gtx_txd_10[6], + gtx_txd_10[5], gtx_txd_10[5], gtx_txd_10[4], gtx_txd_10[4], + gtx_txd_10[3], gtx_txd_10[3], gtx_txd_10[2], gtx_txd_10[2], + gtx_txd_10[1], gtx_txd_10[1], gtx_txd_10[0], gtx_txd_10[0]}; + assign gtx_rxd_10 = { + gtx_rxd[19], gtx_rxd[17], + gtx_rxd[15], gtx_rxd[13], + gtx_rxd[11], gtx_rxd[9], + gtx_rxd[7], gtx_rxd[5], + gtx_rxd[3], gtx_rxd[1]}; + wire confused = // XXX how to read out this status bit in hardware? + (gtx_rxd[19]^gtx_rxd[18]) | (gtx_rxd[17]^gtx_rxd[16]) | + (gtx_rxd[15]^gtx_rxd[14]) | (gtx_rxd[13]^gtx_rxd[12]) | + (gtx_rxd[11]^gtx_rxd[10]) | (gtx_rxd[9]^gtx_rxd[8]) | + (gtx_rxd[7]^gtx_rxd[6]) | (gtx_rxd[5]^gtx_rxd[4]) | + (gtx_rxd[3]^gtx_rxd[2]) | (gtx_rxd[1]^gtx_rxd[0]); + + end else if (GTX_DW==20) begin: G_GTX_DATA_CONV + + // gtx clock is half the gmii clock rate in this stanza reg [9:0] gtx_rxd_10_r=0; reg [9:0] gtx_txd_r=0; - wire [9:0] gtp_rxd_l = gtx_rxd[9:0]; - wire [9:0] gtp_rxd_h = gtx_rxd[19:10]; + wire [9:0] gtx_rxd_l = gtx_rxd[9:0]; + wire [9:0] gtx_rxd_h = gtx_rxd[19:10]; reg [19:0] gtx_txd_l=0; reg even=EVENINIT; @@ -52,10 +82,16 @@ module eth_gtx_hook #( always @(posedge gmii_rx_clk) begin even <= ~even; - gtx_rxd_10_r <= even ? gtp_rxd_l : gtp_rxd_h; + // This next line would be a CDC, except Vivado "knows" that + // gmii_rx_clk and gtx_rx_clk are "related clocks". + // Note that gtx_rx_clk is only implicit in this module: + // it's the clock domain of the gtx_rxd input port. + gtx_rxd_10_r <= even ? gtx_rxd_l : gtx_rxd_h; end always @(posedge gtx_tx_clk) begin + // This next line would be a CDC, except Vivado "knows" that + // gtx_tx_clk and gmii_tx_clk are "related clocks". gtx_txd_l <= {gtx_txd_10, gtx_txd_r}; end @@ -64,6 +100,7 @@ module eth_gtx_hook #( end else begin + // gmii and gtx clocks are considered the same in this stanza assign gtx_txd = gtx_txd_10; assign gtx_rxd_10 = gtx_rxd; diff --git a/serial_io/gmii_gtp.v b/serial_io/gmii_gtp.v index d0d61600b..44493f290 100644 --- a/serial_io/gmii_gtp.v +++ b/serial_io/gmii_gtp.v @@ -1,7 +1,6 @@ module gmii_gtp #( parameter dw = 10 -) -( +) ( // gmii side input gmii_tx_clk, input gmii_rx_clk, diff --git a/serial_io/oversampling_rx_8b9b.v b/serial_io/oversampling_rx_8b9b.v index 280019791..9789c0423 100644 --- a/serial_io/oversampling_rx_8b9b.v +++ b/serial_io/oversampling_rx_8b9b.v @@ -44,7 +44,7 @@ assign inv_clk_4x = ~(clk_4x); else d_in <= {d_in[2:0], data_in}; end - always @(clk or async_reset) begin + always @(clk or async_reset) begin if (async_reset) d_out <= 0; else if (serdes_strobe) diff --git a/soc/picorv32/gateware/lb_merge.v b/soc/picorv32/gateware/lb_merge.v index dcdae6e8d..46c012cb8 100644 --- a/soc/picorv32/gateware/lb_merge.v +++ b/soc/picorv32/gateware/lb_merge.v @@ -12,28 +12,28 @@ module lb_merge #( ) ( input clk, output collision, - output busy, + output busy, // Controlling bus A (CPU) input lb_write_a, input lb_read_a, input [31:0] lb_wdata_a, input [ADW-1:0] lb_addr_a, output [31:0] lb_rdata_a, - input lb_rvalid_a, + input lb_rvalid_a, // Controlling bus B (LB) input lb_write_b, input lb_read_b, input [31:0] lb_wdata_b, input [ADW-1:0] lb_addr_b, output [31:0] lb_rdata_b, - input lb_rvalid_b, + input lb_rvalid_b, // Controlled bus output lb_merge_write, output lb_merge_read, output [31:0] lb_merge_wdata, output [ADW-1:0] lb_merge_addr, input [31:0] lb_merge_rdata, - output lb_merge_rvalid + output lb_merge_rvalid ); assign lb_merge_read = lb_read_a | lb_read_b; diff --git a/soc/picorv32/gateware/spi_pack.v b/soc/picorv32/gateware/spi_pack.v index d5ed35e59..54f652c22 100644 --- a/soc/picorv32/gateware/spi_pack.v +++ b/soc/picorv32/gateware/spi_pack.v @@ -9,7 +9,7 @@ module spi_pack #( output spi_sck, // serial clock output spi_copi, // controller out / peripheral in input spi_cipo, // controller in / peripheral out - output [31:0] spi_cfg_reg, + output [31:0] spi_cfg_reg, // PicoRV32 packed MEM Bus interface input [68:0] mem_packed_fwd, //CPU > SPI output [32:0] mem_packed_ret //CPU < SPI diff --git a/soc/picorv32/gateware/stream_fifo.v b/soc/picorv32/gateware/stream_fifo.v index d12bdfe65..946b3be59 100644 --- a/soc/picorv32/gateware/stream_fifo.v +++ b/soc/picorv32/gateware/stream_fifo.v @@ -9,12 +9,12 @@ module stream_fifo #( input [DW-1:0] d_in, input d_in_valid, input d_in_last, - output d_in_ready, + output d_in_ready, input d_out_ready, output [DW-1:0] d_out, output d_out_last, output d_out_valid, - output fifo_empty + output fifo_empty ); wire d_out_last_i; diff --git a/soc/picorv32/gateware/uart_pack.v b/soc/picorv32/gateware/uart_pack.v index 3e9fb3054..5bb673a36 100644 --- a/soc/picorv32/gateware/uart_pack.v +++ b/soc/picorv32/gateware/uart_pack.v @@ -97,8 +97,7 @@ reg urx_tready=0; uart_rx #( .DATA_WIDTH(DATA_WIDTH) -) -uart_rx_inst ( +) uart_rx_inst ( .clk(clk), .rst(rst), .output_axis_tdata(urx_tdata), diff --git a/soc/picorv32/gateware/xadc_mon.v b/soc/picorv32/gateware/xadc_mon.v index 24696a726..dfdad44a5 100644 --- a/soc/picorv32/gateware/xadc_mon.v +++ b/soc/picorv32/gateware/xadc_mon.v @@ -39,10 +39,10 @@ reg data_rdy=0; always @(posedge reset or posedge lb_clk) begin if (reset) begin reset_wait <= 4'b0; - rst_sync <= 1'b1; - rst_sync_int <= 1'b1; - rst_sync_int1 <= 1'b1; - rst_sync_int2 <= 1'b1; + rst_sync <= 1'b1; + rst_sync_int <= 1'b1; + rst_sync_int1 <= 1'b1; + rst_sync_int2 <= 1'b1; daddr_in <= 7'b0; den_in <= 1'b0; addr_out <= 0; @@ -50,10 +50,10 @@ always @(posedge reset or posedge lb_clk) begin data_rdy <= 1'b0; end else begin reset_wait <= reset_wait_done ? 4'hf : reset_wait + 1'b1; - rst_sync <= 1'b0; - rst_sync_int <= rst_sync; - rst_sync_int1 <= rst_sync_int; - rst_sync_int2 <= rst_sync_int1; + rst_sync <= 1'b0; + rst_sync_int <= rst_sync; + rst_sync_int1 <= rst_sync_int; + rst_sync_int2 <= rst_sync_int1; daddr_in <= {2'b0, channel_out}; den_in <= eoc_out; if (drdy_out) begin