Merge branch 'master' into cmoc_updates

BerkeleyLab · Jan 24, 2025 · e110116 · e110116
2 parents c5f6b66 + 06b84d9
commit e110116
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Showing 37 changed files with 263 additions and 115 deletions.
diff --git a/badger/tests/sp605/spartan6_clocks.v b/badger/tests/sp605/spartan6_clocks.v
@@ -93,8 +93,7 @@ PLL_ADV #(
     .CLKOUT2_DIVIDE(plladv_mult),  .CLKOUT2_DUTY_CYCLE(0.5), .CLKOUT2_PHASE( 0.0), // 200 MHz
     .REF_JITTER(0.005),
     .COMPENSATION("SYSTEM_SYNCHRONOUS")
-)
-PLL_ADV_inst (
+) PLL_ADV_inst (
     .CLKINSEL(1'b1),
     .CLKIN1(sysclk_buf),
     .CLKOUT0(clk_1x_buf),        // 62.5 MHz, 90 degree

diff --git a/badger/tests/spi_test.py b/badger/tests/spi_test.py
@@ -428,12 +428,14 @@ def remote_program(s, file_name, ad, size):
     f = open(file_name, 'rb')
     # assume that '.bin' file size is always less than whole pages
     for ba in reversed(range(start_p, stop_p)):
-        print("block %d" % ba)
+        print("block %d\r" % ba, end='', flush=True)
         f.seek((ba << 8) - ad)
         bd = f.read(PAGE)
         while not (write_enable(s, True)):
             time.sleep(WAIT)
         page_program(s, ba << 8, bd)
+    else:
+        print('')
     f.close()
     return
 

diff --git a/board_support/ac701/base.xdc b/board_support/ac701/base.xdc
@@ -15,7 +15,5 @@ set_property -dict "PACKAGE_PIN T24 IOSTANDARD LVCMOS33" [get_ports {LED[1]}]
 set_property -dict "PACKAGE_PIN T25 IOSTANDARD LVCMOS33" [get_ports {LED[2]}]
 set_property -dict "PACKAGE_PIN R26 IOSTANDARD LVCMOS33" [get_ports {LED[3]}]
 
-set_property -dict "PACKAGE_PIN U4 IOSTANDARD LVCMOS15" [get_ports {RESET}]
-
 # UG471 page 50
-set_property INTERNAL_VREF 0.90 [get_banks BANK13]
+set_property INTERNAL_VREF 0.90 [get_iobanks 13]
diff --git a/dsp/chirp/ramps.v b/dsp/chirp/ramps.v
@@ -52,8 +52,8 @@ always @(posedge clk) begin
 	amp_nonzero <= |amp_r;
 	if (gate) amp_r <= amp_railed ? amp_flat : amp_step;
 	// amplitude needs to be back to zero when next reset hits
-        // for robustness to incorrect parameters, force it low
-        if (reset) amp_r <= 0;
+	// for robustness to incorrect parameters, force it low
+	if (reset) amp_r <= 0;
 	a_warning_r <= reset & amp_nonzero;
 end
 assign amp = amp_r;

diff --git a/dsp/cic_wave_recorder_tb.v b/dsp/cic_wave_recorder_tb.v
@@ -184,9 +184,7 @@ module cic_wave_recorder_tb;
       .lsb_mask      (1),
       .buf_stat_w    (16),
       .buf_auto_flip (1)
-      )
-   dut
-   (
+   ) dut (
       .iclk         (iclk),
       .reset        (reset),
       .stb_in       (ext_trig),

diff --git a/dsp/demand_gpt.v b/dsp/demand_gpt.v
@@ -15,7 +15,7 @@ reg gate_check=0;
 reg [8:0] count=0;  // XXX generous, but not general
 
 always @(posedge clk) begin
-        gate_check <= gate;
+	gate_check <= gate;
 	count <= count + gate;
 	if (trig && gate_check) begin
 		time_err_r <= (count+gate) != gpt;

diff --git a/dsp/digaree/user_tb.v b/dsp/digaree/user_tb.v
@@ -94,7 +94,7 @@ always @(posedge sf_clk) begin
 
 	if (trig_done && conveyor_cnt < data_len) begin
 		meas <= conveyor[conveyor_cnt];
-                conveyor_cnt <= conveyor_cnt + 1;
+		conveyor_cnt <= conveyor_cnt + 1;
 	end
 end
 

diff --git a/dsp/fchan_subset.v b/dsp/fchan_subset.v
@@ -31,7 +31,7 @@ generate
 		for (ix=0; ix<len; ix=ix+1) begin
 			assign keep_use[ix] = keep[len-1-ix];
 		end
-        end
+	end
 	else begin : G_NKEEP_OLD
 		for (ix=0; ix<len; ix=ix+1) begin
 			assign keep_use[ix] = keep[ix];

diff --git a/dsp/hosted/phs_avg.v b/dsp/hosted/phs_avg.v
@@ -28,7 +28,7 @@
 // real when iq==1 and imaginary when iq==0.
 
 module phs_avg #(
-    parameter dwi = 17
+	parameter dwi = 17
 ) (
 	input clk,  // timespec 6.66 ns
 	input reset,
@@ -50,11 +50,11 @@ assign ky_addr = iq;
 reg signed [dwj-1:0] kx1 = 0, ky1 = 0;
 reg signed [(dwi+dwj)-1:0] prod_x = 0, prod_y = 0;
 always @(posedge clk) begin
-        // Delay gains, to multiply I*R
-        kx1 <= kx;
-        ky1 <= ky;
-        prod_x <= x * kx1;
-        prod_y <= y * ky1;
+	// Delay gains, to multiply I*R
+	kx1 <= kx;
+	ky1 <= ky;
+	prod_x <= x * kx1;
+	prod_y <= y * ky1;
 end
 
 wire signed [dwi+5:0] xmr = prod_x[(dwi+dwj)-2:dwj-7];
@@ -64,11 +64,11 @@ reg signed [dwi+6:0] sum = 0, sum1 = 0;
 reg signed [dwi+7:0] sum_f = 0;
 reg signed [dwi+intg_scale:0] intg = 0;
 always @(posedge clk) begin
-        sum <= xmr + ymr;
-        sum1 <= sum;
-        sum_f <= sum1 + sum;  // 2-tap filter [1, 1]
-        if (reset) intg <= 0;
-        else intg <= (sum_f >>> 1) + intg; // Integrator
+	sum <= xmr + ymr;
+	sum1 <= sum;
+	sum_f <= sum1 + sum;  // 2-tap filter [1, 1]
+	if (reset) intg <= 0;
+	else intg <= (sum_f >>> 1) + intg; // Integrator
 end
 assign sum_filt = sum_f;
 assign z = intg[dwi+intg_scale:intg_scale-1];

diff --git a/dsp/iq_deinterleaver_multichannel.v b/dsp/iq_deinterleaver_multichannel.v
@@ -29,9 +29,7 @@ module iq_deinterleaver_multichannel #(
          .scale_wi  (SCALE_WI),
          .dwi       (DWI),
          .davr      (DAVR)
-      )
-      i_iq_deinterleaver
-      (
+      ) i_iq_deinterleaver (
          .clk        (clk),
          .scale_in   (scale_in),
          .iq_data_in (iq_data_in[(ch_id+1)*DWI-1:ch_id*DWI]),

diff --git a/dsp/iq_mixer_multichannel.v b/dsp/iq_mixer_multichannel.v
@@ -30,9 +30,7 @@ module iq_mixer_multichannel #(
          .dwi       (DWI),
          .davr      (DAVR),
          .dwlo      (DWLO)
-      )
-      i_mixer_cos
-      (
+      ) i_mixer_cos (
          .clk    (clk),
          .adcf   (adc[(ch_id+1)*DWI-1: ch_id*DWI]),
          .mult   (cos),
@@ -44,9 +42,7 @@ module iq_mixer_multichannel #(
          .dwi       (DWI),
          .davr      (DAVR),
          .dwlo      (DWLO)
-      )
-      i_mixer_sin
-      (
+      ) i_mixer_sin (
          .clk    (clk),
          .adcf   (adc[(ch_id+1)*DWI-1: ch_id*DWI]),
          .mult   (sin),

diff --git a/fpga_family/mgt/gtp_common_2_50.tcl b/fpga_family/mgt/gtp_common_2_50.tcl
@@ -0,0 +1,52 @@
+set cfg_dict {
+   CONFIG.identical_val_tx_line_rate       {2.50}
+   CONFIG.gt0_val                          {true}
+   CONFIG.gt0_val_drp_clock                {50}
+   CONFIG.gt0_val_rx_refclk                {REFCLK0_Q0}
+   CONFIG.gt0_val_tx_refclk                {REFCLK0_Q0}
+   CONFIG.gt0_val_txbuf_en                 {true}
+   CONFIG.gt0_val_rxbuf_en                 {true}
+   CONFIG.gt0_val_port_rxslide             {false}
+   CONFIG.gt0_usesharedlogic               {0}
+   CONFIG.identical_val_rx_line_rate       {2.50}
+   CONFIG.gt_val_tx_pll                    {PLL0}
+   CONFIG.gt_val_rx_pll                    {PLL1}
+   CONFIG.identical_val_tx_reference_clock {125.000}
+   CONFIG.identical_val_rx_reference_clock {125.000}
+   CONFIG.gt0_val_tx_line_rate             {2.50}
+   CONFIG.gt0_val_tx_data_width            {20}
+   CONFIG.gt0_val_tx_int_datawidth         {20}
+   CONFIG.gt0_val_tx_reference_clock       {125.000}
+   CONFIG.gt0_val_rx_line_rate             {2.50}
+   CONFIG.gt0_val_rx_data_width            {20}
+   CONFIG.gt0_val_rx_int_datawidth         {20}
+   CONFIG.gt0_val_rx_reference_clock       {125.000}
+   CONFIG.gt0_val_cpll_fbdiv               {4}
+   CONFIG.gt0_val_cpll_rxout_div           {4}
+   CONFIG.gt0_val_cpll_txout_div           {4}
+   CONFIG.gt0_val_tx_buffer_bypass_mode    {Auto}
+   CONFIG.gt0_val_txoutclk_source          {false}
+   CONFIG.gt0_val_rx_buffer_bypass_mode    {Auto}
+   CONFIG.gt0_val_rxusrclk                 {RXOUTCLK}
+   CONFIG.gt0_val_rxslide_mode             {OFF}
+   CONFIG.gt0_val_port_txbufstatus         {true}
+   CONFIG.gt0_val_port_rxbufstatus         {true}
+   CONFIG.gt0_val_port_rxpmareset          {true}
+   CONFIG.gt0_val_align_mcomma_det         {true}
+   CONFIG.gt0_val_align_pcomma_det         {true}
+   CONFIG.gt0_val_comma_preset             {User_defined}
+   CONFIG.gt0_val_align_pcomma_value       {1111110000}
+   CONFIG.gt0_val_align_mcomma_value       {0011001111}
+   CONFIG.gt0_val_align_comma_enable       {1111111111}
+   CONFIG.gt0_val_align_comma_double       {true}
+   CONFIG.gt0_val_align_comma_word         {Two_Byte_Boundaries}
+   CONFIG.gt0_val_port_rxpcommaalignen     {false}
+   CONFIG.gt0_val_port_rxmcommaalignen     {false}
+   CONFIG.gt0_val_dfe_mode                 {LPM-Auto}
+   CONFIG.gt0_val_rx_termination_voltage   {Programmable}
+   CONFIG.gt0_val_rx_cm_trim               {800}
+   CONFIG.gt0_val_port_rxdfereset          {true}
+   CONFIG.gt0_val_pd_trans_time_to_p2      {100}
+   CONFIG.gt0_val_pd_trans_time_from_p2    {60}
+   CONFIG.gt0_val_pd_trans_time_non_p2     {25}
+}
diff --git a/fpga_family/mgt/gtp_ethernet_2_50.tcl b/fpga_family/mgt/gtp_ethernet_2_50.tcl
@@ -0,0 +1,52 @@
+set cfg_dict {
+   CONFIG.identical_val_tx_line_rate       {2.50}
+   CONFIG.gt0_val                          {true}
+   CONFIG.gt0_val_drp_clock                {50}
+   CONFIG.gt0_val_rx_refclk                {REFCLK0_Q0}
+   CONFIG.gt0_val_tx_refclk                {REFCLK0_Q0}
+   CONFIG.gt0_val_txbuf_en                 {true}
+   CONFIG.gt0_val_rxbuf_en                 {true}
+   CONFIG.gt0_val_port_rxslide             {false}
+   CONFIG.gt0_usesharedlogic               {0}
+   CONFIG.identical_val_rx_line_rate       {2.50}
+   CONFIG.gt_val_tx_pll                    {PLL0}
+   CONFIG.gt_val_rx_pll                    {PLL0}
+   CONFIG.identical_val_tx_reference_clock {125.000}
+   CONFIG.identical_val_rx_reference_clock {125.000}
+   CONFIG.gt0_val_tx_line_rate             {2.50}
+   CONFIG.gt0_val_tx_data_width            {20}
+   CONFIG.gt0_val_tx_int_datawidth         {20}
+   CONFIG.gt0_val_tx_reference_clock       {125.000}
+   CONFIG.gt0_val_rx_line_rate             {2.50}
+   CONFIG.gt0_val_rx_data_width            {20}
+   CONFIG.gt0_val_rx_int_datawidth         {20}
+   CONFIG.gt0_val_rx_reference_clock       {125.000}
+   CONFIG.gt0_val_cpll_fbdiv               {4}
+   CONFIG.gt0_val_cpll_rxout_div           {4}
+   CONFIG.gt0_val_cpll_txout_div           {4}
+   CONFIG.gt0_val_tx_buffer_bypass_mode    {Auto}
+   CONFIG.gt0_val_txoutclk_source          {false}
+   CONFIG.gt0_val_rx_buffer_bypass_mode    {Auto}
+   CONFIG.gt0_val_rxusrclk                 {RXOUTCLK}
+   CONFIG.gt0_val_rxslide_mode             {OFF}
+   CONFIG.gt0_val_port_txbufstatus         {true}
+   CONFIG.gt0_val_port_rxbufstatus         {true}
+   CONFIG.gt0_val_port_rxpmareset          {true}
+   CONFIG.gt0_val_align_mcomma_det         {true}
+   CONFIG.gt0_val_align_pcomma_det         {true}
+   CONFIG.gt0_val_comma_preset             {User_defined}
+   CONFIG.gt0_val_align_pcomma_value       {1111110000}
+   CONFIG.gt0_val_align_mcomma_value       {0011001111}
+   CONFIG.gt0_val_align_comma_enable       {1111111111}
+   CONFIG.gt0_val_align_comma_double       {true}
+   CONFIG.gt0_val_align_comma_word         {Two_Byte_Boundaries}
+   CONFIG.gt0_val_port_rxpcommaalignen     {false}
+   CONFIG.gt0_val_port_rxmcommaalignen     {false}
+   CONFIG.gt0_val_dfe_mode                 {LPM-Auto}
+   CONFIG.gt0_val_rx_termination_voltage   {Programmable}
+   CONFIG.gt0_val_rx_cm_trim               {800}
+   CONFIG.gt0_val_port_rxdfereset          {true}
+   CONFIG.gt0_val_pd_trans_time_to_p2      {100}
+   CONFIG.gt0_val_pd_trans_time_from_p2    {60}
+   CONFIG.gt0_val_pd_trans_time_non_p2     {25}
+}
diff --git a/fpga_family/spartan6/spartan6_clocks.v b/fpga_family/spartan6/spartan6_clocks.v
@@ -82,6 +82,7 @@ DCM_SP #(
 BUFG bufg125_tx(.I(xclk125_buf), .O(clk_eth));
 
 PLL_ADV #(
+    .SIM_DEVICE("SPARTAN6"),
     .BANDWIDTH("OPTIMIZED"),
     .CLKIN1_PERIOD(clkin_period),
     .CLKFBOUT_MULT(plladv_mult), // 200x5=1000
@@ -92,8 +93,7 @@ PLL_ADV #(
     .CLKOUT2_DIVIDE(plladv_mult),  .CLKOUT2_DUTY_CYCLE(0.5), .CLKOUT2_PHASE( 0.0), // 200 MHz
     .REF_JITTER(0.005),
     .COMPENSATION("SYSTEM_SYNCHRONOUS")
-)
-PLL_ADV_inst (
+) PLL_ADV_inst (
     .CLKINSEL(1'b1),
     .CLKIN1(sysclk_buf),
     .CLKOUT0(clk_1x_buf),        // 62.5 MHz, 90 degree

diff --git a/fpga_family/xilinx/xadc_tempvoltmon.v b/fpga_family/xilinx/xadc_tempvoltmon.v
@@ -168,8 +168,7 @@ module xadc_tempvoltmon #(
     // Simulation attributes: Set for proper simulation behavior
     .SIM_DEVICE("7SERIES"),            // Select target device (values)
     .SIM_MONITOR_FILE("design.txt")  // Analog simulation data file name
-  )
-  XADC_inst (
+  ) XADC_inst (
     // ALARMS: 8-bit (each) output: ALM, OT
     .ALM(alm),                   // 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram
     .OT(otemp),                  // 1-bit output: Over-Temperature alarm

diff --git a/localbus/jit_rad_gateway_tb.v b/localbus/jit_rad_gateway_tb.v
@@ -6,14 +6,14 @@ reg lb_clk=0;
 integer cc;
 reg fail=0;
 initial begin
-        if ($test$plusargs("vcd")) begin
-                $dumpfile("jit_rad_gateway.vcd");
-                $dumpvars(5, jit_rad_gateway_tb);
-        end
-        for (cc=0; cc<2000; cc=cc+1) begin
-                #10; lb_clk=1;
-                #10; lb_clk=0;
-        end
+	if ($test$plusargs("vcd")) begin
+		$dumpfile("jit_rad_gateway.vcd");
+		$dumpvars(5, jit_rad_gateway_tb);
+	end
+	for (cc=0; cc<2000; cc=cc+1) begin
+		#10; lb_clk=1;
+		#10; lb_clk=0;
+	end
 	$display("%s", fail ? "FAIL" : "PASS");
 	if (fail) $stop(0);
 	$finish(0);

diff --git a/peripheral_drivers/strobe_gen.v b/peripheral_drivers/strobe_gen.v
@@ -2,11 +2,10 @@
 
 module strobe_gen #(
 	parameter TYPE="RISE_EDGE"
-)
-(
-    input I_clk,
-    input I_signal,
-    output O_strobe
+) (
+	input I_clk,
+	input I_signal,
+	output O_strobe
 );
 reg [1:0] sig_r;
 generate
@@ -19,7 +18,7 @@ else
 endgenerate
 
 always @(posedge I_clk) begin
-    sig_r<={sig_r[0],I_signal};
+	sig_r<={sig_r[0],I_signal};
 end
 assign O_strobe=(sig_r==2'b01);
 

diff --git a/projects/cmoc_top/bmb7_cu/clocks.v b/projects/cmoc_top/bmb7_cu/clocks.v
@@ -42,8 +42,7 @@ PLLE2_BASE #(
     .CLKOUT1_DIVIDE(pll_div),  .CLKOUT1_DUTY_CYCLE(0.5), .CLKOUT1_PHASE(90.0), // 125 MHz
     .REF_JITTER1(0.0),
     .STARTUP_WAIT("FALSE")
-)
-PLLE2_BASE_inst (
+) PLLE2_BASE_inst (
     .CLKIN1(sysclk_buf),
     .CLKOUT0(pll_clk_0),        // 125 MHz, 0 degree
     .CLKOUT1(pll_clk_90),       // 125 MHz, 90 degree

diff --git a/projects/comms_top/gige_eth/Makefile b/projects/comms_top/gige_eth/Makefile
@@ -17,7 +17,7 @@ VERILOG_DEFINE_FLAGS =
 include $(COMMS_TOP_DIR)/rules.mk
 include $(BUILD_DIR)/top_rules.mk
 
-all: gen $(APP_NAME).bit
+all: $(APP_NAME).bit
 
 $(APP_NAME).bit: $(IP_TCL)
 
@@ -35,5 +35,5 @@ ifneq (,$(findstring bit,$(MAKECMDGOALS)))
     endif
 endif
 
-CLEAN += *.bit ../test/*.dat
+CLEAN += *.bit *.bin ../test/*.dat
 include $(BUILD_DIR)/bottom_rules.mk