From cc3fa4b569c9e964b1f5288ba7af4753dffbbea2 Mon Sep 17 00:00:00 2001 From: Larry Doolittle Date: Mon, 29 Jan 2024 09:01:53 -0800 Subject: [PATCH] More small improvements to preprocessor hygiene --- cmoc/cryomodule.v | 3 +++ dsp/ccfilt.v | 1 + dsp/digaree/sf_main.v | 1 + rtsim/rtsim.v | 1 + 4 files changed, 6 insertions(+) diff --git a/cmoc/cryomodule.v b/cmoc/cryomodule.v index 5760529b0..da2096b0d 100644 --- a/cmoc/cryomodule.v +++ b/cmoc/cryomodule.v @@ -441,4 +441,7 @@ always @(posedge lb_clk) begin end assign lb_out = lb_out_r; +`undef SAT +`undef UNIFORM + endmodule diff --git a/dsp/ccfilt.v b/dsp/ccfilt.v index f48212376..f351be793 100644 --- a/dsp/ccfilt.v +++ b/dsp/ccfilt.v @@ -57,6 +57,7 @@ always @(posedge clk) begin end reg valid3=0; always @(posedge clk) valid3 <= valid2; +`undef UNIFORM `ifdef SIMULATE reg [3:0] ch_id=0; diff --git a/dsp/digaree/sf_main.v b/dsp/digaree/sf_main.v index 80ed94bc0..ff107d30f 100644 --- a/dsp/digaree/sf_main.v +++ b/dsp/digaree/sf_main.v @@ -161,6 +161,7 @@ assign valid_o = valid_r; assign sat_happened = valid_r & sat_happened_r; `undef SAT +`undef UNSAT endmodule diff --git a/rtsim/rtsim.v b/rtsim/rtsim.v index 3bd48429e..ae30d7684 100644 --- a/rtsim/rtsim.v +++ b/rtsim/rtsim.v @@ -101,6 +101,7 @@ always @(posedge clk) begin eig_drive <= eig_drive0; edrive_clip <= ~`UNIFORM(sum_eig_drive[19:17]); end +`undef UNIFORM `undef SAT // Reserve space for several possible clipping status signals