More small improvements to preprocessor hygiene

cmoc/cryomodule.v

@@ -441,4 +441,7 @@ always @(posedge lb_clk) begin
 end
 assign lb_out = lb_out_r;
 
+`undef SAT
+`undef UNIFORM
+
 endmodule

dsp/ccfilt.v

@@ -57,6 +57,7 @@ always @(posedge clk) begin
 end
 reg valid3=0;
 always @(posedge clk) valid3 <= valid2;
+`undef UNIFORM
 
 `ifdef SIMULATE
 reg [3:0] ch_id=0;

dsp/digaree/sf_main.v

@@ -161,6 +161,7 @@ assign valid_o = valid_r;
 assign sat_happened = valid_r & sat_happened_r;
 
 `undef SAT
+`undef UNSAT
 
 endmodule
 

rtsim/rtsim.v

@@ -101,6 +101,7 @@ always @(posedge clk) begin
   eig_drive <= eig_drive0;
   edrive_clip <= ~`UNIFORM(sum_eig_drive[19:17]);
 end
+`undef UNIFORM
 `undef SAT
 
 // Reserve space for several possible clipping status signals