From bbc11fffbd37203fe816097ba2a9c160bdd97227 Mon Sep 17 00:00:00 2001 From: Alessio Amodio Date: Wed, 20 Dec 2023 15:57:06 -0800 Subject: [PATCH] marble.tcl: gitid_for_verilog broken assignment fixed --- projects/test_marble_family/marble.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/test_marble_family/marble.tcl b/projects/test_marble_family/marble.tcl index 56938c0cc..298d3e6d5 100644 --- a/projects/test_marble_family/marble.tcl +++ b/projects/test_marble_family/marble.tcl @@ -52,7 +52,7 @@ set_property verilog_define [list "CHIP_FAMILY_7SERIES"] [current_fileset] # Get shorter git commit ID for verilog and bitfile filename set gitid_for_filename [exec git describe --always --abbrev=8 --dirty] -set gitid_for_verilog 32'h$[string range $gitid_for_filename 0 7] +set gitid_for_verilog 32'h[exec git rev-parse --short=8 HEAD] set new_defs [list "GIT_32BIT_ID=$gitid_for_verilog" "REVC_1W"] launch_runs synth_1