test_marble_family: remove some lint

.. that shows up on at least some g++ and Verilator versions
BerkeleyLab · Jan 30, 2024 · adf5934 · adf5934
1 parent a3fe8ee
commit adf5934
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Showing 3 changed files with 4 additions and 3 deletions.
diff --git a/projects/test_marble_family/Makefile b/projects/test_marble_family/Makefile
@@ -148,7 +148,7 @@ read_trx.dat: read_trx.py
 # including lb_marble_slave.v, is here.
 Vmarble_base: $(MARBLE_BASE_V) marble_base_sim.cpp ethernet_model.c tap_alloc.c crc32.c
 	rm -f ethernet_model.o tap_alloc.o crc32.o  # can't leave C version around for C++ to find
-	$(VERILATOR) --trace-fst $(VLATOR_LINT_IGNORE) -DSIMULATE -cc --exe $^
+	$(VERILATOR) --trace-fst $(VLATOR_LINT_IGNORE) -DSIMULATE -cc -CFLAGS -Wno-logical-op --exe $^
 	MAKEFLAGS="" make -C obj_dir -f Vmarble_base.mk USER_CPPFLAGS="-I $(BADGER_DIR)/tests"
 	mv obj_dir/$@ $@
 # Recipe:

diff --git a/projects/test_marble_family/lb_marble_slave.v b/projects/test_marble_family/lb_marble_slave.v
@@ -124,8 +124,9 @@ generate if (MMC_CTRACE) begin : mmc_ctrace
 	ctrace #(.dw(4), .tw(12), .aw(ctrace_aw)) mmc_ctrace(
 		.clk(clk), .data(mmc_pins), .start(csb_toggle & ctrace_arm),
 		.running(ctrace_running), .pc_mon(ctrace_pc_mon),
-		.lb_clk(clk), .lb_addr(addr[ctrace_aw-1:0]), .lb_out(ctrace_out)
+		.lb_clk(clk), .lb_addr(addr[ctrace_aw-1:0]), .lb_out(ctrace_out[15:0])
 	);
+        assign ctrace_out[19:16] = 0;
 end else if (GPS_CTRACE) begin : gps_ctrace
 	localparam ctrace_aw=14;
 	wire [ctrace_aw-1:0] ctrace_pc_mon;  // not used

diff --git a/projects/test_marble_family/marble_base_sim.cpp b/projects/test_marble_family/marble_base_sim.cpp
@@ -99,7 +99,7 @@ void spi_model(unsigned char *SCLK, unsigned char *CSB, unsigned char *MOSI, uns
 		unsigned word_ix;
 		unsigned pattern_ix;
 		uint16_t tx_word;
-	} state = {0};
+	} state = {0, 0, 0, 0};
 	static int cc=0;
 	// Write "1234ABCD" to first half of page 3
 	// (well, the high bit is set for the 1234 part)