From 76d084f0b0111f788f930f9cd225d469d6d5e062 Mon Sep 17 00:00:00 2001 From: Larry Doolittle Date: Tue, 28 Nov 2023 21:44:05 -0800 Subject: [PATCH] Attempt to add testing of P2 HA pins --- board_support/marblemini/marble_base.v | 2 +- projects/oscope/marble_family/oscope_top.sv | 5 +- projects/test_marble_family/Makefile | 2 +- projects/test_marble_family/fmc_test_iam.py | 42 +++++++++++----- projects/test_marble_family/lb_marble_slave.v | 19 +++++-- projects/test_marble_family/marble_top.csv | 49 +++++++++++++++++++ projects/test_marble_family/marble_top.v | 11 ++++- .../test_marble_family/static_regmap.json | 14 ++++++ 8 files changed, 122 insertions(+), 22 deletions(-) diff --git a/board_support/marblemini/marble_base.v b/board_support/marblemini/marble_base.v index 8f9f999cf..e69a5864d 100644 --- a/board_support/marblemini/marble_base.v +++ b/board_support/marblemini/marble_base.v @@ -80,7 +80,7 @@ module marble_base ( input [31:0] lb_data_in, // Something physical - inout [135:0] fmc_test, + inout [183:0] fmc_test, output ZEST_PWR_EN, output [7:0] LED ); diff --git a/projects/oscope/marble_family/oscope_top.sv b/projects/oscope/marble_family/oscope_top.sv index 04b63e113..53886e0f5 100644 --- a/projects/oscope/marble_family/oscope_top.sv +++ b/projects/oscope/marble_family/oscope_top.sv @@ -173,6 +173,9 @@ assign LD17 = 1; // vestiges of CERN FMC tester support wire old_scl1, old_scl2, old_sda1, old_sda2; +// placeholders +wire [23:0] FMC2_HA_P; +wire [23:0] FMC2_HA_N; // Real, portable implementation // Consider pulling 3-state drivers out of this @@ -203,7 +206,7 @@ marble_base #( .lb_rd_valid(lb_rd_valid), .lb_data_out(lb_data_out), .lb_data_in(lb_din), - .fmc_test({FMC2_LA_P, FMC2_LA_N, FMC1_LA_P, FMC1_LA_N}), + .fmc_test({FMC2_HA_P, FMC2_HA_N, FMC2_LA_P, FMC2_LA_N, FMC1_LA_P, FMC1_LA_N}), .WR_DAC_SCLK(WR_DAC_SCLK), .WR_DAC_DIN(WR_DAC_DIN), .WR_DAC1_SYNC(WR_DAC1_SYNC), .WR_DAC2_SYNC(WR_DAC2_SYNC), .LED(LED) diff --git a/projects/test_marble_family/Makefile b/projects/test_marble_family/Makefile index 5c5bce8a8..a4f5b0d3d 100644 --- a/projects/test_marble_family/Makefile +++ b/projects/test_marble_family/Makefile @@ -132,7 +132,7 @@ marble1.xdc: $(BADGER_DIR)/tests/meta-xdc.py $(patsubst %,$(BOARD_SUPPORT_DIR)/m $(PYTHON) $^ > $@ marble2.xdc: $(BADGER_DIR)/tests/meta-xdc.py $(patsubst %,$(BOARD_SUPPORT_DIR)/marble/%, Marble.xdc pin_map.csv) pin_map_fmc.csv marble_top.csv - $(PYTHON) $^ | sed -e '/FMC._LA_/s/IOSTANDARD LVCMOS25/IOSTANDARD LVCMOS25 PULLTYPE PULLUP/' > $@ + $(PYTHON) $^ | sed -e '/FMC._.A_/s/IOSTANDARD LVCMOS25/IOSTANDARD LVCMOS25 PULLTYPE PULLUP/' > $@ # ===== # Initialization file for i2cbridge diff --git a/projects/test_marble_family/fmc_test_iam.py b/projects/test_marble_family/fmc_test_iam.py index 2341d1d9e..ea9fcc94d 100644 --- a/projects/test_marble_family/fmc_test_iam.py +++ b/projects/test_marble_family/fmc_test_iam.py @@ -1,5 +1,6 @@ -# FMC tester based on IAM Electronic FPGA Mezzanine Card (FMC) Loopback Module +# PoC Marble FMC tester based on IAM Electronic FPGA Mezzanine Card (FMC) Loopback Module # https://www.iamelectronic.com/shop/produkt/fpga-mezzanine-card-fmc-loopback-module +# Still doesn't cover LA_1 to GBTCLK0_M2C or LA_18 to GBTCLK1_M2C (HPC) import leep from sys import argv @@ -11,7 +12,7 @@ def tobin(x, count=8): return "".join([str((x >> y) & 1) for y in range(count-1, -1, -1)]) -# highly customized for this application +# stupidly customized for 68-pin LA banks in this application # input is numeric, 22 bits + 22 bits + 24 bits def to_bin_fmc(v): al = tobin(v[0], count=22) @@ -24,23 +25,38 @@ def get_iam_fmc(addr): r_set = ["_test_in_" + s for s in ["l", "m", "h"]] # print(r_set) r_set2 = ["fmc1" + r for r in r_set] + ["fmc2" + r for r in r_set] + r_set2 += ["fmc2h_test_in_l", "fmc2h_test_in_h"] # print(r_set2) d = addr.reg_read(r_set2) # print(d) p1 = to_bin_fmc(d[0:3]) p2 = to_bin_fmc(d[3:6]) - return (p1, p2) + p2h = tobin(d[7], count=24) + tobin(d[6], count=24) + return (p1, p2, p2h) def set_iam_fmc(addr, p, bit): a = 1 << bit - al = (a >> 0) & 0x3fffff - am = (a >> 22) & 0x3fffff - ah = (a >> 44) & 0xffffff - port = "fmc%d" % p - r_set = [(port+"_test_l", al), (port+"_test_m", am), (port+"_test_h", ah)] - port = "fmc%d" % (3-p) - r_set += [(port+"_test_l", 0), (port+"_test_m", 0), (port+"_test_h", 0)] + if p != 3: # LPC + al = (a >> 0) & 0x3fffff + am = (a >> 22) & 0x3fffff + ah = (a >> 44) & 0xffffff + port = "fmc%d" % p + r_set = [(port+"_test_l", al), (port+"_test_m", am), (port+"_test_h", ah)] + else: # HPC + al = (a >> 0) & 0xffffff + ah = (a >> 24) & 0xffffff + port = "fmc2h" + r_set = [(port+"_test_l", al), (port+"_test_h", ah)] + if p != 1: + port = "fmc1" + r_set += [(port+"_test_l", 0), (port+"_test_m", 0), (port+"_test_h", 0)] + if p != 2: + port = "fmc2" + r_set += [(port+"_test_l", 0), (port+"_test_m", 0), (port+"_test_h", 0)] + if p != 3: + port = "fmc2h" + r_set += [(port+"_test_l", 0), (port+"_test_h", 0)] # print(r_set) addr.reg_write(r_set) @@ -48,11 +64,11 @@ def set_iam_fmc(addr, p, bit): def test_iam_fmc(addr): gitid = addr.codehash print("# test_iam_fmc " + gitid) - for px in [1, 2]: - for bx in range(68): + for px in [1, 2, 3]: + for bx in range(48 if px == 3 else 68): set_iam_fmc(addr, px, bx) r = get_iam_fmc(addr) - print(px, "%3d" % bx, r[0], r[1]) + print(px, "%3d" % bx, r[0], r[1], r[2]) if __name__ == "__main__": diff --git a/projects/test_marble_family/lb_marble_slave.v b/projects/test_marble_family/lb_marble_slave.v index 28715a1ad..22a161a8b 100644 --- a/projects/test_marble_family/lb_marble_slave.v +++ b/projects/test_marble_family/lb_marble_slave.v @@ -64,7 +64,7 @@ module lb_marble_slave #( input [3:0] gps, output [3:0] ext_config, // Output to hardware - inout [135:0] fmc_test, + inout [183:0] fmc_test, output [1:0] led_user_mode, output led1, // PWM output led2 // PWM @@ -290,6 +290,8 @@ reg [23:0] fmc1_test_in_h=0; reg [21:0] fmc2_test_in_l=0; reg [21:0] fmc2_test_in_m=0; reg [23:0] fmc2_test_in_h=0; +reg [23:0] fmc2h_test_in_l=0; +reg [23:0] fmc2h_test_in_h=0; // First read cycle reg [31:0] reg_bank_0=0, dbg_mem_out=0; @@ -332,8 +334,8 @@ always @(posedge clk) if (do_rd) begin 4'hb: reg_bank_1 <= fmc2_test_in_l; 4'hc: reg_bank_1 <= fmc2_test_in_m; 4'hd: reg_bank_1 <= fmc2_test_in_h; - // xxxx1e unused - // xxxx1f unused + 4'he: reg_bank_1 <= fmc2h_test_in_l; + 4'hf: reg_bank_1 <= fmc2h_test_in_h; default: reg_bank_1 <= "zzzz"; endcase end @@ -373,6 +375,7 @@ wire local_write = control_strobe & ~control_rd & (addr[23:16]==5); reg stop_sim=0; // clearly only useful in simulation reg [67:0] fmc1_test_r=0; reg [67:0] fmc2_test_r=0; +reg [47:0] fmc2h_test_r=0; always @(posedge clk) if (local_write) case (addr[4:0]) 1: led_user_r <= data_out; 2: led_1_df <= data_out; @@ -392,6 +395,8 @@ always @(posedge clk) if (local_write) case (addr[4:0]) 19: fmc2_test_r[21:0] <= data_out; 20: fmc2_test_r[43:22] <= data_out; 21: fmc2_test_r[67:44] <= data_out; + 22: fmc2h_test_r[23:0] <= data_out; + 23: fmc2h_test_r[47:24] <= data_out; endcase // always @(posedge clk) begin @@ -429,12 +434,14 @@ assign zest_pwr_en = misc_config[3]; assign ext_config = misc_config[7:4]; // 3-state -wire [67:0] fmc1_test, fmc2_test; genvar ix; -generate for (ix=0; ix<68; ix=ix+1) begin: fmc_bit +generate for (ix=0; ix<68; ix=ix+1) begin: fmc_lbit assign fmc_test[ix+0] = fmc1_test_r[ix] ? 1'b0 : 1'bz; assign fmc_test[ix+68] = fmc2_test_r[ix] ? 1'b0 : 1'bz; end endgenerate +generate for (ix=0; ix<48; ix=ix+1) begin: fmc_hbit + assign fmc_test[ix+136] = fmc2h_test_r[ix] ? 1'b0 : 1'bz; +end endgenerate always @(posedge clk) begin fmc1_test_in_l <= fmc_test[21:0]; fmc1_test_in_m <= fmc_test[43:22]; @@ -442,6 +449,8 @@ always @(posedge clk) begin fmc2_test_in_l <= fmc_test[89:68]; fmc2_test_in_m <= fmc_test[111:90]; fmc2_test_in_h <= fmc_test[135:112]; + fmc2h_test_in_l <= fmc_test[159:136]; + fmc2h_test_in_h <= fmc_test[183:160]; end // Bus activity trace output diff --git a/projects/test_marble_family/marble_top.csv b/projects/test_marble_family/marble_top.csv index e2f05a96d..ea6544c36 100644 --- a/projects/test_marble_family/marble_top.csv +++ b/projects/test_marble_family/marble_top.csv @@ -1,3 +1,52 @@ +FMC2_HA00_CC_P FMC2_HA_P[0] +FMC2_HA00_CC_N FMC2_HA_N[0] +FMC2_HA01_CC_P FMC2_HA_P[1] +FMC2_HA01_CC_N FMC2_HA_N[1] +FMC2_HA02_P FMC2_HA_P[2] +FMC2_HA02_N FMC2_HA_N[2] +FMC2_HA03_P FMC2_HA_P[3] +FMC2_HA03_N FMC2_HA_N[3] +FMC2_HA04_P FMC2_HA_P[4] +FMC2_HA04_N FMC2_HA_N[4] +FMC2_HA05_P FMC2_HA_P[5] +FMC2_HA05_N FMC2_HA_N[5] +FMC2_HA06_P FMC2_HA_P[6] +FMC2_HA06_N FMC2_HA_N[6] +FMC2_HA07_P FMC2_HA_P[7] +FMC2_HA07_N FMC2_HA_N[7] +FMC2_HA08_P FMC2_HA_P[8] +FMC2_HA08_N FMC2_HA_N[8] +FMC2_HA09_P FMC2_HA_P[9] +FMC2_HA09_N FMC2_HA_N[9] +FMC2_HA10_P FMC2_HA_P[10] +FMC2_HA10_N FMC2_HA_N[10] +FMC2_HA11_P FMC2_HA_P[11] +FMC2_HA11_N FMC2_HA_N[11] +FMC2_HA12_P FMC2_HA_P[12] +FMC2_HA12_N FMC2_HA_N[12] +FMC2_HA13_P FMC2_HA_P[13] +FMC2_HA13_N FMC2_HA_N[13] +FMC2_HA14_P FMC2_HA_P[14] +FMC2_HA14_N FMC2_HA_N[14] +FMC2_HA15_P FMC2_HA_P[15] +FMC2_HA15_N FMC2_HA_N[15] +FMC2_HA16_P FMC2_HA_P[16] +FMC2_HA16_N FMC2_HA_N[16] +FMC2_HA17_CC_P FMC2_HA_P[17] +FMC2_HA17_CC_N FMC2_HA_N[17] +FMC2_HA18_P FMC2_HA_P[18] +FMC2_HA18_N FMC2_HA_N[18] +FMC2_HA19_P FMC2_HA_P[19] +FMC2_HA19_N FMC2_HA_N[19] +FMC2_HA20_P FMC2_HA_P[20] +FMC2_HA20_N FMC2_HA_N[20] +FMC2_HA21_P FMC2_HA_P[21] +FMC2_HA21_N FMC2_HA_N[21] +FMC2_HA22_P FMC2_HA_P[22] +FMC2_HA22_N FMC2_HA_N[22] +FMC2_HA23_P FMC2_HA_P[23] +FMC2_HA23_N FMC2_HA_N[23] + # Literal output follows set_clock_groups -name async_clks -asynchronous \ diff --git a/projects/test_marble_family/marble_top.v b/projects/test_marble_family/marble_top.v index d73bc4ee4..fc1e060ae 100644 --- a/projects/test_marble_family/marble_top.v +++ b/projects/test_marble_family/marble_top.v @@ -66,6 +66,10 @@ module marble_top( inout [33:0] FMC1_LA_N, inout [33:0] FMC2_LA_P, inout [33:0] FMC2_LA_N, +`ifdef MARBLE_V2 + inout [23:0] FMC2_HA_P, + inout [23:0] FMC2_HA_N, +`endif // output ZEST_PWR_EN, `ifdef MARBLE_MINI @@ -85,6 +89,11 @@ module marble_top( `include "marble_features_params.vh" +`ifndef MARBLE_V2 +wire [23:0] FMC2_HA_P; +wire [23:0] FMC2_HA_N; +`endif + wire gtpclk0, gtpclk; // Gateway GTP refclk to fabric IBUFDS_GTE2 passi_125(.I(GTPREFCLK_P), .IB(GTPREFCLK_N), .CEB(1'b0), .O(gtpclk0)); @@ -264,7 +273,7 @@ marble_base #( .FPGA_RxD(FPGA_RxD), .FPGA_TxD(FPGA_TxD), .twi_scl({dum_scl, old_scl1, old_scl2, TWI_SCL}), .twi_sda({dum_sda, old_sda1, old_sda2, TWI_SDA}), - .fmc_test({FMC2_LA_P, FMC2_LA_N, FMC1_LA_P, FMC1_LA_N}), + .fmc_test({FMC2_HA_P, FMC2_HA_N, FMC2_LA_P, FMC2_LA_N, FMC1_LA_P, FMC1_LA_N}), .TWI_RST(TWI_RST), .TWI_INT(TWI_INT), .WR_DAC_SCLK(WR_DAC_SCLK), .WR_DAC_DIN(WR_DAC_DIN), .WR_DAC1_SYNC(WR_DAC1_SYNC), .WR_DAC2_SYNC(WR_DAC2_SYNC), diff --git a/projects/test_marble_family/static_regmap.json b/projects/test_marble_family/static_regmap.json index 1f248f90f..248be283a 100644 --- a/projects/test_marble_family/static_regmap.json +++ b/projects/test_marble_family/static_regmap.json @@ -111,6 +111,20 @@ "base_addr": 327701, "data_width": 24 }, + "fmc2h_test_l": { + "access": "rw", + "addr_width": 0, + "sign": "unsigned", + "base_addr": 327702, + "data_width": 24 + }, + "fmc2h_test_h": { + "access": "rw", + "addr_width": 0, + "sign": "unsigned", + "base_addr": 327703, + "data_width": 24 + }, "twi_prog": { "access": "rw", "addr_width": 10,