From 76ae987eff3c7d07e1754273d7df6b941d6b85d0 Mon Sep 17 00:00:00 2001 From: sdmurthy Date: Sat, 1 Feb 2025 12:05:10 -0800 Subject: [PATCH] Reuse marble_features.yaml from test_marble_family --- projects/cmoc_top/marblemini/Makefile | 2 +- .../cmoc_top/marblemini/marble_features.yaml | 39 ------------------- projects/test_marble_family/Makefile | 4 +- .../test_marble_family/marble_features.yaml | 4 +- 4 files changed, 5 insertions(+), 44 deletions(-) delete mode 100644 projects/cmoc_top/marblemini/marble_features.yaml diff --git a/projects/cmoc_top/marblemini/Makefile b/projects/cmoc_top/marblemini/Makefile index 36b9a94dd..173be6001 100644 --- a/projects/cmoc_top/marblemini/Makefile +++ b/projects/cmoc_top/marblemini/Makefile @@ -52,7 +52,7 @@ $(APP_NAME)_regmap.json: $(AUTOGEN_DIR)/regmap_cryomodule.json $(OSCOPE_COMMON_D $(PYTHON) $(OSCOPE_COMMON_DIR)/shorten_names.py -o $@ -i $(APP_NAME)_regmap_long.json # actual file output is marble_features_(defs/params).vh -marble_features_defs.vh marble_features_params.vh: $(BUILD_DIR)/gen_features.py marble_features.yaml +marble_features_defs.vh marble_features_params.vh: $(BUILD_DIR)/gen_features.py $(TEST_MARBLE_FAMILY)/marble_features.yaml $(PYTHON) $< -i $(filter %.yaml, $^) -c $(HARDWARE) --split include $(BUILD_DIR)/bottom_rules.mk diff --git a/projects/cmoc_top/marblemini/marble_features.yaml b/projects/cmoc_top/marblemini/marble_features.yaml deleted file mode 100644 index 6245d0a46..000000000 --- a/projects/cmoc_top/marblemini/marble_features.yaml +++ /dev/null @@ -1,39 +0,0 @@ -# Defs are made available as Verilog defines -# Params are made available as Verilog localparams and included in ROM metadata -# XXX reuse from test_marble_family - -marblemini: - defs: - MARBLE_MINI: 1 - USE_SI570: 0 - USE_I2CBRIDGE: 1 - MMC_CTRACE: 0 - GPS_CTRACE: 0 - params: - carrier: "Marble Mini" - carrier_rev: "v1" - default_enable_rx: 1 - misc_config_default: 4 - use_rgmii_idelay: 1 - # Options are gtp_ref_clk or sys_clk - # sys_clk is only usable if use_rgmii_idelay: 0 - sysclk_src: "gtp_ref_clk" - -marble: - defs: - MARBLE_V2: 1 - USE_SI570: 1 - USE_I2CBRIDGE: 1 - MMC_CTRACE: 0 - GPS_CTRACE: 0 - params: - carrier: "Marble" - carrier_rev: "v2" - default_enable_rx: 1 - misc_config_default: 4 - use_rgmii_idelay: 1 - # Options are gtp_ref_clk, ddr_ref_clk, or sys_clk - # sys_clk is only usable if use_rgmii_idelay: 0 - # ddr_ref_clk is recommended over gtp_ref_clk to avoid having basic - # boot and communications depend on ADN4600 programming - sysclk_src: "ddr_ref_clk" diff --git a/projects/test_marble_family/Makefile b/projects/test_marble_family/Makefile index 7123313b7..54cbc33f1 100644 --- a/projects/test_marble_family/Makefile +++ b/projects/test_marble_family/Makefile @@ -66,10 +66,10 @@ config_romx.v: marble_regmap.json $(filter-out config_romx.v, $(MARBLE_SYNTH_SOU # gen_features.py rules (note the use of PHONY targets) # actual file outputs are marble_features_params.vh and marble_features_defs.vh marble1_features: $(BUILD_DIR)/gen_features.py marble_features.yaml - $(PYTHON) $< -i $(filter %.yaml, $^) -c marble_mini --split + $(PYTHON) $< -i $(filter %.yaml, $^) -c marblemini --split marble2_features: $(BUILD_DIR)/gen_features.py marble_features.yaml - $(PYTHON) $< -i $(filter %.yaml, $^) -c marble_v2 --split + $(PYTHON) $< -i $(filter %.yaml, $^) -c marble --split .PHONY: marble1_features marble2_features # ==== diff --git a/projects/test_marble_family/marble_features.yaml b/projects/test_marble_family/marble_features.yaml index ebdc53555..b2832d43f 100644 --- a/projects/test_marble_family/marble_features.yaml +++ b/projects/test_marble_family/marble_features.yaml @@ -1,7 +1,7 @@ # Defs are made available as Verilog defines # Params are made available as Verilog localparams and included in ROM metadata -marble_mini: +marblemini: defs: MARBLE_MINI: 1 USE_SI570: 0 @@ -18,7 +18,7 @@ marble_mini: # sys_clk is only usable if use_rgmii_idelay: 0 sysclk_src: "gtp_ref_clk" -marble_v2: +marble: defs: MARBLE_V2: 1 USE_SI570: 1