Improve handling of SAT macro

Lets two Makefiles drop -Wno-macro-redefinition (icarus) or -Wno-REDEFMACRO (verilator)

cmoc/Makefile

@@ -10,7 +10,6 @@ include $(BADGER_DIR)/rules.mk
 
 NEWAD_ARGS += -y
 
-VFLAGS += -Wno-macro-redefinition
 TEST_BENCH = xy_pi_clip_tb fdbk_core_tb tgen_tb circle_buf_tb cryomodule_tb cryomodule_badger_tb rf_controller_tb
 
 RTEFI_CLIENT_LIST = hello.v speed_test.v mem_gateway.v
@@ -55,7 +54,7 @@ cryomodule_check: cryomodule.dat
 $(AUTOGEN_DIR)/config_romx.v:
 	mkdir -p $(AUTOGEN_DIR); $(PYTHON) $(BUILD_DIR)/config_crunch.py --OUTPUT=$@
 
-VFLAGS_DEP += -y $(BADGER_DIR) -Wno-macro-redefinition
+VFLAGS_DEP += -y $(BADGER_DIR)
 
 cryomodule_badger_tb.v: $(RTEFI_V) $(AUTOGEN_DIR)/config_romx.v cordicg_b22.v cryomodule_auto
 

dsp/ccfilt.v

@@ -81,6 +81,8 @@ always @(posedge clk) begin
 	valid4 <= valid3;
 end
 
+`undef SAT
+
 // Instantiate half-band filter .. or not
 wire [outw-1:0] d5;
 wire valid5;

dsp/complex_mul.v

@@ -79,6 +79,7 @@ always @(posedge clk) begin
 end
 assign z = zr[dw:1];
 assign z_all = mux_r;
+`undef SAT
 
 // This gate input isn't really used, but describes the length of this
 // pipeline to let users keep track of the data flow.

dsp/complex_mul_flat.v

@@ -41,6 +41,7 @@ always @(posedge clk) begin
 	I_small <= `SAT(z_I_sel, 19, 18);
 	Q_small <= `SAT(z_Q_sel, 19, 18);
 end
+`undef SAT
 
 assign z_I_all = z_I_all_i;
 assign z_Q_all = z_Q_all_i;

dsp/cpxmul_fullspeed.v

@@ -29,7 +29,7 @@ module cpxmul_fullspeed #(
    reg signed [DWI*2-1:0] sum1=0, sum2=0, sum3=0;
    reg signed [DWI*2-OUT_SHIFT-1:0] sum1_r=0, sum2_r=0;
 
-   `define SAT(x,old,new) ((~|x[old:new] | &x[old:new]) ? x[new:0] : {x[old],{new{~x[old]}}})
+`define SAT(x,old,new) ((~|x[old:new] | &x[old:new]) ? x[new:0] : {x[old],{new{~x[old]}}})
    always @(posedge clk) begin
       mul1 <= re_a*re_b;
       mul2 <= im_a*im_b;
@@ -43,5 +43,6 @@ module cpxmul_fullspeed #(
 
    assign re_out = `SAT(sum1_r, DWI*2-OUT_SHIFT-1, OWI-1);
    assign im_out = `SAT(sum2_r, DWI*2-OUT_SHIFT-1, OWI-1);
+`undef SAT
 
 endmodule

dsp/digaree/sf_main.v

@@ -160,6 +160,8 @@ assign r = sat;
 assign valid_o = valid_r;
 assign sat_happened = valid_r & sat_happened_r;
 
+`undef SAT
+
 endmodule
 
 // ALU and register file, no instruction sequencing

dsp/fdownconvert.v

@@ -73,6 +73,8 @@ always @(posedge clk) begin
 	time_err_r <= (mod2 ^ ~last_mod2) | ~a_gate;
 end
 
+`undef SAT
+
 assign o_data = iq_out0;
 assign o_gate = 1'b1;
 assign o_trig = mod2;

dsp/flevel_set.v

@@ -41,6 +41,8 @@ always @(posedge clk) begin
 	time_err_r <= ~i_gate | ~q_gate;
 end
 
+`undef SAT
+
 assign o_data = sum2[16:1];
 assign o_gate = 1'b1;
 assign o_trig = 1'b0;

dsp/fwashout.v

@@ -32,6 +32,7 @@ end
 `define SAT(x,old,new) ((~|x[old:new] | &x[old:new]) ? x[new:0] : {x[old],{new{~x[old]}}})
 wire signed [a_dw+cut-1:0] clipped=`SAT(sub,a_dw+cut,a_dw+cut-1);
 assign o_data = clipped[a_dw+cut-1:cut];
+`undef SAT
 
 // Intended for raw ADC inputs.
 // Could go back and make this module handle other data patterns

dsp/hosted/lp.v

@@ -62,6 +62,8 @@ always @(posedge clk) begin
 end
 assign y = yr[18+shift:1];
 
+`undef SAT
+
 endmodule
 
 

dsp/hosted/lp_2notch.v

@@ -44,6 +44,7 @@ wire [22:0] y_sum = y1+y2+y3;
 `define SAT(x,old,new) ((~|x[old:new] | &x[old:new]) ? x[new:0] : {x[old],{new{~x[old]}}})
 reg [21:0] y_out=0;
 always @(posedge clk) y_out <= `SAT(y_sum, 22, 21);
+`undef SAT
 
 // Very stupid extra delay, only here to keep historical I-Q relationship.
 // XXX get rid of this!

dsp/hosted/mp_proc.v

@@ -107,8 +107,6 @@ assign setmp_addr = {1'b0, ~state[0]};
 assign coeff_addr = {~state2[1],state2[0]};
 assign   lim_addr = {state6[2],state4[0]};
 
-`define SAT(x,old,new) ((~|x[old:new] | &x[old:new]) ? x[new:0] : {x[old],{new{~x[old]}}})
-
 reg [7:0] stb=0;
 always @(posedge clk) stb <= {stb[6:0],sync};
 

dsp/hosted/non_iq_interleaved_piloop.v

@@ -20,12 +20,6 @@
 // DELAY: 9 cycles of delay at @clk
 `timescale 1ns / 1ns
 
-// Universal definition; note: old and new are msb numbers, not bit widths.
-//  0. assert old > new
-//  1. Should really be called downsize and check for saturate
-//  2. if x[old:new] are all ones or zeros: then it's safe to resize the signal
-//  3. Else: Rail the signal
-`define SAT(x,old,new) ((~|x[old:new] | &x[old:new]) ? x[new:0] : {x[old],{new{~x[old]}}})
 
 // TODO: Potentially parameterize input and output signal widths
 //     : Rename Ref_i/q to Setpoint_i/q
@@ -57,9 +51,15 @@ initial begin
 end
 
 parameter KW = 18; // Bit-width of PI gains
-
 // Assuming K's are w bits wide
 
+// Universal definition; note: old and new are msb numbers, not bit widths.
+//  0. assert old > new
+//  1. Should really be called downsize and check for saturate
+//  2. if x[old:new] are all ones or zeros: then it's safe to resize the signal
+//  3. Else: Rail the signal
+`define SAT(x,old,new) ((~|x[old:new] | &x[old:new]) ? x[new:0] : {x[old],{new{~x[old]}}})
+
 // Clamp errors - long story, not efficient, but see llc-suite fdbk_loop.v
 wire signed [17:0] err1_i = $signed(`SAT(err_i, 18, 13)) <<< 3;
 wire signed [17:0] err1_q = $signed(`SAT(err_q, 18, 13)) <<< 3;
@@ -96,4 +96,5 @@ always @ (posedge clk) begin
 	pi_out_i <= `SAT(pi_out_I_s, 18, 17);
 	pi_out_q <= `SAT(pi_out_Q_s, 18, 17);
 end
+`undef SAT
 endmodule

dsp/iq_modulator.v

@@ -16,7 +16,6 @@ module iq_modulator #(
 // also plan that abs(ampi+ampq*i) < 1
 
 // Universal definition; note: old and new are msb numbers, not bit widths.
-`undef SAT
 `define SAT(x,old,new) ((~|x[old:new] | &x[old:new]) ? x[new:0] : {x[old],{new{~x[old]}}})
 reg signed [2*WIDTH-1:0] p1=0, p2=0;  // product registers
 wire signed [WIDTH:0] p1s = p1[2*WIDTH-2:WIDTH-2];
@@ -30,5 +29,6 @@ always @(posedge clk) begin
 	d3 <= `SAT(sum, WIDTH+1, WIDTH);
 end
 assign d_out = d3[WIDTH:1];
+`undef SAT
 
 endmodule

dsp/ll_prop.v

@@ -42,6 +42,7 @@ always @(posedge clk) begin
 	sum_iq <= prod_iq_lim + drive_iq;
 	sum_iq_s <= `SAT(sum_iq,18,17);
 end
+`undef SAT
 
 assign out_iq=sum_iq_s;
 

dsp/multiply_accumulate.v

@@ -1,6 +1,5 @@
 `timescale 1ns / 1ns
 
-`define SAT(x,old,new) ((~|x[old:new] | &x[old:new]) ? x[new:0] : {x[old],{new{~x[old]}}})
 /// TL;DR
 /// accumulated += ((constant * signal) >>> downscale) + correction
 ///
@@ -25,6 +24,8 @@ parameter KW = 18;  // Constant Width
 parameter SW = 18;  // Signal Width
 parameter OW = 21;  // OutputWidth: Desired bitwidth of the accumulator
 
+`define SAT(x,old,new) ((~|x[old:new] | &x[old:new]) ? x[new:0] : {x[old],{new{~x[old]}}})
+
 reg signed [KW+SW-1: 0] integrator_in_large=0;
 reg signed [OW-1: 0] integrator_sum=0;
 
@@ -40,6 +41,8 @@ always @ (posedge clk) begin
 	end
 end
 
+`undef SAT
+
 assign accumulated = integrator_sum;
 
 endmodule

dsp/upconv.v

@@ -36,7 +36,7 @@ wire signed [15:0] i2i, i2q;
 interp1 inti(.clk(clk), .x(d2i), .y(i2i));
 interp1 intq(.clk(clk), .x(d2q), .y(i2q));
 
-`define SAT(x,old,new) ((~|x[old:new] | &x[old:new]) ? x : {x[old],{new{~x[old]}}})
+`define SAT(x,old,new) ((~|x[old:new] | &x[old:new]) ? x[new:0] : {x[old],{new{~x[old]}}})
 reg signed [31:0] cosp=0, sinp=0;
 wire signed [17:0] cosp_msb = cosp[30:13];
 wire signed [17:0] sinp_msb = sinp[30:13];
@@ -52,5 +52,6 @@ assign out_d = sum2[16:1];
 
 assign cos_interp = i2i;
 assign sin_interp = i2q;
+`undef SAT
 
 endmodule

dsp/xy_pi_clip.v

@@ -99,6 +99,7 @@ always @(posedge clk) begin
 end
 
 wire signed [29:0] mr_sat = `SAT(mr_ff,42,29);
+`undef SAT
 
 reg signed [35:0] mr=0;
 reg signed [30:0] lim1=0;

projects/test_marble_family/pps_lock/Makefile

@@ -4,7 +4,7 @@ VERILOG = iverilog$(ICARUS_SUFFIX) -Wall -Wno-timescale
 VVP = vvp$(ICARUS_SUFFIX)
 GTKWAVE = gtkwave
 VERILATOR = verilator
-VLATOR_LINT_IGNORE = -Wno-PINMISSING -Wno-WIDTH -Wno-REDEFMACRO -Wno-PINCONNECTEMPTY
+VLATOR_LINT_IGNORE = -Wno-PINMISSING -Wno-WIDTH -Wno-PINCONNECTEMPTY
 
 %_tb: %_tb.v
 	$(VERILOG) ${VFLAGS_$@} -o $@ $(filter %.v, $^)

rtsim/Makefile

@@ -11,7 +11,6 @@ ifneq (clean,$(MAKECMDGOALS))
 	-include $(DEPDIR)/resonator.bit.d
 endif
 
-VFLAGS += -Wno-macro-redefinition
 VVP_FLAGS += +trace
 
 # -y for yosys

rtsim/adc_em.v

@@ -51,6 +51,7 @@ always @(posedge clk) sum <= in + (awgn <<< 3) + offset;
 wire signed [14:0] sum_trunc = sum[18:4];
 reg signed [13:0] sat=0;
 always @(posedge clk) sat <= `SAT(sum_trunc,14,13);
+`undef SAT
 
 // Adjustable delay
 wire signed [13:0] dval;

rtsim/cav_elec.v

@@ -192,6 +192,7 @@ always @(posedge clk) begin
 	if (~iq) refl_r  <= `SAT(refl_sum,   20,17);
 	if ( iq) fwd_r   <= `SAT(fwd_ref,    18,17);
 end
+`undef SAT
 
 assign field   = iq ? probe_r : 0;
 assign forward = iq ? fwd_r   : 0;

rtsim/dot_prod.v

@@ -42,6 +42,7 @@ always @(posedge clk) begin
 	if (zero) acc2 <= `SAT(acc1,23,19);
 	strobe_r <= zero;
 end
+`undef SAT
 
 assign result = acc2[19:2];
 assign strobe = strobe_r;

rtsim/mag_square.v

@@ -24,6 +24,7 @@ always @(posedge clk) begin
 	if (~iq) mag1 <= sqr2+sqr3+1;
 	mag2 <= `SAT(mag1,19,18);
 end
+`undef SAT
 // mag2 must be positive!
 assign mag2_out = mag2;
 

rtsim/resonator.v

@@ -127,6 +127,7 @@ always @(posedge clk) begin
 	sat_result <= `SAT(sum_result,36,35);
 	clip_r <= ~(~|sum_result[36:35] | &sum_result[36:35]);
 end
+`undef SAT
 
 assign ab_in = sat_result;
 assign position = sat_result[35:18];

rtsim/rtsim.v

@@ -101,6 +101,7 @@ always @(posedge clk) begin
   eig_drive <= eig_drive0;
   edrive_clip <= ~`UNIFORM(sum_eig_drive[19:17]);
 end
+`undef SAT
 
 // Reserve space for several possible clipping status signals
 // Caller should take care of latching, reporting, and clearing.

rtsim/station.v

@@ -60,9 +60,6 @@ module station(
 
 `AUTOMATIC_decode
 
-`define SAT(x,old,new) ((~|x[old:new] | &x[old:new]) ? x[new:0] : {x[old],{new{~x[old]}}})
-`define UNIFORM(x) ((~|(x)) | &(x))  // All 0's or all 1's
-
 // Virtual Piezo
 // Couple the piezo to mechanical drive
 (* lb_automatic *)