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audio_process_map.map
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Release 14.7 Map P.20131013 (nt64)
Xilinx Map Application Log File for Design 'audio_process'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx9-csg324-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o audio_process_map.ncd audio_process.ngd
audio_process.pcf
Target Device : xc6slx9
Target Package : csg324
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Sat Mar 12 12:45:34 2016
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 6 secs
Total CPU time at the beginning of Placer: 6 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:b23cac2d) REAL time: 6 secs
Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 43 IOs, 39 are locked
and 4 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:b23cac2d) REAL time: 7 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:b23cac2d) REAL time: 7 secs
Phase 4.2 Initial Placement for Architecture Specific Features
...
.
WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found
that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
IOB component <ac97_bit_clock> is placed at site <V4>. The corresponding BUFG
component <ac97_bit_clock_BUFGP/BUFG> is placed at site <BUFGMUX_X3Y5>. There
is only a select set of IOBs that can use the fast path to the Clocker
buffer, and they are not being used. You may want to analyze why this problem
exists and correct it. This is normally an ERROR but the
CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <ac97_bit_clock.PAD>
allowing your design to continue. This constraint disables all clock placer
rules related to the specified COMP.PIN. The use of this override is highly
discouraged as it may lead to very poor timing results. It is recommended
that this error condition be corrected in the design.
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:50d3f26) REAL time: 9 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:50d3f26) REAL time: 9 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:50d3f26) REAL time: 9 secs
Phase 7.3 Local Placement Optimization
...
Phase 7.3 Local Placement Optimization (Checksum:40fb4244) REAL time: 9 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:5128cd6) REAL time: 9 secs
Phase 9.8 Global Placement
...............
.....................................................................................................................................
.......................
........
Phase 9.8 Global Placement (Checksum:35652861) REAL time: 14 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:35652861) REAL time: 14 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:4dedad07) REAL time: 16 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:4dedad07) REAL time: 16 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:e798d3ab) REAL time: 16 secs
Total REAL time to Placer completion: 16 secs
Total CPU time to Placer completion: 16 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 2
Slice Logic Utilization:
Number of Slice Registers: 917 out of 11,440 8%
Number used as Flip Flops: 917
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 609 out of 5,720 10%
Number used as logic: 454 out of 5,720 7%
Number using O6 output only: 247
Number using O5 output only: 48
Number using O5 and O6: 159
Number used as ROM: 0
Number used as Memory: 102 out of 1,440 7%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 102
Number using O6 output only: 29
Number using O5 output only: 0
Number using O5 and O6: 73
Number used exclusively as route-thrus: 53
Number with same-slice register load: 50
Number with same-slice carry load: 3
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 279 out of 1,430 19%
Number of MUXCYs used: 192 out of 2,860 6%
Number of LUT Flip Flop pairs used: 863
Number with an unused Flip Flop: 137 out of 863 15%
Number with an unused LUT: 254 out of 863 29%
Number of fully used LUT-FF pairs: 472 out of 863 54%
Number of unique control sets: 15
Number of slice register sites lost
to control set restrictions: 52 out of 11,440 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 43 out of 200 21%
Number of LOCed IOBs: 39 out of 43 90%
Specific Feature Utilization:
Number of RAMB16BWERs: 2 out of 32 6%
Number of RAMB8BWERs: 1 out of 64 1%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 8 out of 16 50%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 2.14
Peak Memory Usage: 419 MB
Total REAL time to MAP completion: 17 secs
Total CPU time to MAP completion: 17 secs
Mapping completed.
See MAP report file "audio_process_map.mrp" for details.