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Website for the OpenROAD tutorial held at the MICRO 2022 conference

Verilog 27 10 Updated Oct 6, 2022

Advanced Architecture Labs with CVA6

SystemVerilog 54 26 Updated Jan 16, 2024

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Python 1,440 388 Updated Feb 26, 2025

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Verilog 385 315 Updated Mar 8, 2025

Logic synthesis and ABC based optimization

C++ 49 41 Updated Feb 11, 2025

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog 1,810 612 Updated Mar 10, 2025

OpenROAD users should look at this repository first for instructions on getting started

102 6 Updated Apr 3, 2021
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